1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "ARMFPUName.h"
11 #include "ARMFeatures.h"
12 #include "MCTargetDesc/ARMAddressingModes.h"
13 #include "MCTargetDesc/ARMArchName.h"
14 #include "MCTargetDesc/ARMBaseInfo.h"
15 #include "MCTargetDesc/ARMMCExpr.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/ADT/Twine.h"
21 #include "llvm/MC/MCAsmInfo.h"
22 #include "llvm/MC/MCAssembler.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCDisassembler.h"
25 #include "llvm/MC/MCELFStreamer.h"
26 #include "llvm/MC/MCExpr.h"
27 #include "llvm/MC/MCInst.h"
28 #include "llvm/MC/MCInstrDesc.h"
29 #include "llvm/MC/MCInstrInfo.h"
30 #include "llvm/MC/MCObjectFileInfo.h"
31 #include "llvm/MC/MCParser/MCAsmLexer.h"
32 #include "llvm/MC/MCParser/MCAsmParser.h"
33 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
34 #include "llvm/MC/MCRegisterInfo.h"
35 #include "llvm/MC/MCSection.h"
36 #include "llvm/MC/MCStreamer.h"
37 #include "llvm/MC/MCSubtargetInfo.h"
38 #include "llvm/MC/MCSymbol.h"
39 #include "llvm/MC/MCTargetAsmParser.h"
40 #include "llvm/Support/ARMBuildAttributes.h"
41 #include "llvm/Support/ARMEHABI.h"
42 #include "llvm/Support/COFF.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/ELF.h"
45 #include "llvm/Support/MathExtras.h"
46 #include "llvm/Support/SourceMgr.h"
47 #include "llvm/Support/TargetRegistry.h"
48 #include "llvm/Support/raw_ostream.h"
56 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
61 typedef SmallVector<SMLoc, 4> Locs;
66 Locs PersonalityIndexLocs;
71 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
73 bool hasFnStart() const { return !FnStartLocs.empty(); }
74 bool cantUnwind() const { return !CantUnwindLocs.empty(); }
75 bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
76 bool hasPersonality() const {
77 return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
80 void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
81 void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
82 void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
83 void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
84 void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
86 void saveFPReg(int Reg) { FPReg = Reg; }
87 int getFPReg() const { return FPReg; }
89 void emitFnStartLocNotes() const {
90 for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
92 Parser.Note(*FI, ".fnstart was specified here");
94 void emitCantUnwindLocNotes() const {
95 for (Locs::const_iterator UI = CantUnwindLocs.begin(),
96 UE = CantUnwindLocs.end(); UI != UE; ++UI)
97 Parser.Note(*UI, ".cantunwind was specified here");
99 void emitHandlerDataLocNotes() const {
100 for (Locs::const_iterator HI = HandlerDataLocs.begin(),
101 HE = HandlerDataLocs.end(); HI != HE; ++HI)
102 Parser.Note(*HI, ".handlerdata was specified here");
104 void emitPersonalityLocNotes() const {
105 for (Locs::const_iterator PI = PersonalityLocs.begin(),
106 PE = PersonalityLocs.end(),
107 PII = PersonalityIndexLocs.begin(),
108 PIE = PersonalityIndexLocs.end();
109 PI != PE || PII != PIE;) {
110 if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
111 Parser.Note(*PI++, ".personality was specified here");
112 else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
113 Parser.Note(*PII++, ".personalityindex was specified here");
115 llvm_unreachable(".personality and .personalityindex cannot be "
116 "at the same location");
121 FnStartLocs = Locs();
122 CantUnwindLocs = Locs();
123 PersonalityLocs = Locs();
124 HandlerDataLocs = Locs();
125 PersonalityIndexLocs = Locs();
130 class ARMAsmParser : public MCTargetAsmParser {
131 MCSubtargetInfo &STI;
133 const MCInstrInfo &MII;
134 const MCRegisterInfo *MRI;
137 ARMTargetStreamer &getTargetStreamer() {
138 MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
139 return static_cast<ARMTargetStreamer &>(TS);
142 // Map of register aliases registers via the .req directive.
143 StringMap<unsigned> RegisterReqs;
145 bool NextSymbolIsThumb;
148 ARMCC::CondCodes Cond; // Condition for IT block.
149 unsigned Mask:4; // Condition mask for instructions.
150 // Starting at first 1 (from lsb).
151 // '1' condition as indicated in IT.
152 // '0' inverse of condition (else).
153 // Count of instructions in IT block is
154 // 4 - trailingzeroes(mask)
156 bool FirstCond; // Explicit flag for when we're parsing the
157 // First instruction in the IT block. It's
158 // implied in the mask, so needs special
161 unsigned CurPosition; // Current position in parsing of IT
162 // block. In range [0,3]. Initialized
163 // according to count of instructions in block.
164 // ~0U if no active IT block.
166 bool inITBlock() { return ITState.CurPosition != ~0U;}
167 void forwardITPosition() {
168 if (!inITBlock()) return;
169 // Move to the next instruction in the IT block, if there is one. If not,
170 // mark the block as done.
171 unsigned TZ = countTrailingZeros(ITState.Mask);
172 if (++ITState.CurPosition == 5 - TZ)
173 ITState.CurPosition = ~0U; // Done with the IT block after this.
177 MCAsmParser &getParser() const { return Parser; }
178 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
180 void Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges = None) {
181 return Parser.Note(L, Msg, Ranges);
183 bool Warning(SMLoc L, const Twine &Msg,
184 ArrayRef<SMRange> Ranges = None) {
185 return Parser.Warning(L, Msg, Ranges);
187 bool Error(SMLoc L, const Twine &Msg,
188 ArrayRef<SMRange> Ranges = None) {
189 return Parser.Error(L, Msg, Ranges);
192 int tryParseRegister();
193 bool tryParseRegisterWithWriteBack(OperandVector &);
194 int tryParseShiftRegister(OperandVector &);
195 bool parseRegisterList(OperandVector &);
196 bool parseMemory(OperandVector &);
197 bool parseOperand(OperandVector &, StringRef Mnemonic);
198 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
199 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
200 unsigned &ShiftAmount);
201 bool parseLiteralValues(unsigned Size, SMLoc L);
202 bool parseDirectiveThumb(SMLoc L);
203 bool parseDirectiveARM(SMLoc L);
204 bool parseDirectiveThumbFunc(SMLoc L);
205 bool parseDirectiveCode(SMLoc L);
206 bool parseDirectiveSyntax(SMLoc L);
207 bool parseDirectiveReq(StringRef Name, SMLoc L);
208 bool parseDirectiveUnreq(SMLoc L);
209 bool parseDirectiveArch(SMLoc L);
210 bool parseDirectiveEabiAttr(SMLoc L);
211 bool parseDirectiveCPU(SMLoc L);
212 bool parseDirectiveFPU(SMLoc L);
213 bool parseDirectiveFnStart(SMLoc L);
214 bool parseDirectiveFnEnd(SMLoc L);
215 bool parseDirectiveCantUnwind(SMLoc L);
216 bool parseDirectivePersonality(SMLoc L);
217 bool parseDirectiveHandlerData(SMLoc L);
218 bool parseDirectiveSetFP(SMLoc L);
219 bool parseDirectivePad(SMLoc L);
220 bool parseDirectiveRegSave(SMLoc L, bool IsVector);
221 bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
222 bool parseDirectiveLtorg(SMLoc L);
223 bool parseDirectiveEven(SMLoc L);
224 bool parseDirectivePersonalityIndex(SMLoc L);
225 bool parseDirectiveUnwindRaw(SMLoc L);
226 bool parseDirectiveTLSDescSeq(SMLoc L);
227 bool parseDirectiveMovSP(SMLoc L);
228 bool parseDirectiveObjectArch(SMLoc L);
229 bool parseDirectiveArchExtension(SMLoc L);
230 bool parseDirectiveAlign(SMLoc L);
231 bool parseDirectiveThumbSet(SMLoc L);
233 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
234 bool &CarrySetting, unsigned &ProcessorIMod,
236 void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
237 bool &CanAcceptCarrySet,
238 bool &CanAcceptPredicationCode);
240 bool isThumb() const {
241 // FIXME: Can tablegen auto-generate this?
242 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
244 bool isThumbOne() const {
245 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
247 bool isThumbTwo() const {
248 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
250 bool hasThumb() const {
251 return STI.getFeatureBits() & ARM::HasV4TOps;
253 bool hasV6Ops() const {
254 return STI.getFeatureBits() & ARM::HasV6Ops;
256 bool hasV6MOps() const {
257 return STI.getFeatureBits() & ARM::HasV6MOps;
259 bool hasV7Ops() const {
260 return STI.getFeatureBits() & ARM::HasV7Ops;
262 bool hasV8Ops() const {
263 return STI.getFeatureBits() & ARM::HasV8Ops;
265 bool hasARM() const {
266 return !(STI.getFeatureBits() & ARM::FeatureNoARM);
270 uint64_t FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
271 setAvailableFeatures(FB);
273 bool isMClass() const {
274 return STI.getFeatureBits() & ARM::FeatureMClass;
277 /// @name Auto-generated Match Functions
280 #define GET_ASSEMBLER_HEADER
281 #include "ARMGenAsmMatcher.inc"
285 OperandMatchResultTy parseITCondCode(OperandVector &);
286 OperandMatchResultTy parseCoprocNumOperand(OperandVector &);
287 OperandMatchResultTy parseCoprocRegOperand(OperandVector &);
288 OperandMatchResultTy parseCoprocOptionOperand(OperandVector &);
289 OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &);
290 OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &);
291 OperandMatchResultTy parseProcIFlagsOperand(OperandVector &);
292 OperandMatchResultTy parseMSRMaskOperand(OperandVector &);
293 OperandMatchResultTy parseBankedRegOperand(OperandVector &);
294 OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low,
296 OperandMatchResultTy parsePKHLSLImm(OperandVector &O) {
297 return parsePKHImm(O, "lsl", 0, 31);
299 OperandMatchResultTy parsePKHASRImm(OperandVector &O) {
300 return parsePKHImm(O, "asr", 1, 32);
302 OperandMatchResultTy parseSetEndImm(OperandVector &);
303 OperandMatchResultTy parseShifterImm(OperandVector &);
304 OperandMatchResultTy parseRotImm(OperandVector &);
305 OperandMatchResultTy parseBitfield(OperandVector &);
306 OperandMatchResultTy parsePostIdxReg(OperandVector &);
307 OperandMatchResultTy parseAM3Offset(OperandVector &);
308 OperandMatchResultTy parseFPImm(OperandVector &);
309 OperandMatchResultTy parseVectorList(OperandVector &);
310 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
313 // Asm Match Converter Methods
314 void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
315 void cvtThumbBranches(MCInst &Inst, const OperandVector &);
317 bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
318 bool processInstruction(MCInst &Inst, const OperandVector &Ops);
319 bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
320 bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
323 enum ARMMatchResultTy {
324 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
325 Match_RequiresNotITBlock,
327 Match_RequiresThumb2,
328 #define GET_OPERAND_DIAGNOSTIC_TYPES
329 #include "ARMGenAsmMatcher.inc"
333 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
334 const MCInstrInfo &MII,
335 const MCTargetOptions &Options)
336 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(MII), UC(_Parser) {
337 MCAsmParserExtension::Initialize(_Parser);
339 // Cache the MCRegisterInfo.
340 MRI = getContext().getRegisterInfo();
342 // Initialize the set of available features.
343 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
345 // Not in an ITBlock to start with.
346 ITState.CurPosition = ~0U;
348 NextSymbolIsThumb = false;
351 // Implementation of the MCTargetAsmParser interface:
352 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
353 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
354 SMLoc NameLoc, OperandVector &Operands) override;
355 bool ParseDirective(AsmToken DirectiveID) override;
357 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
358 unsigned Kind) override;
359 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
361 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
362 OperandVector &Operands, MCStreamer &Out,
364 bool MatchingInlineAsm) override;
365 void onLabelParsed(MCSymbol *Symbol) override;
367 } // end anonymous namespace
371 /// ARMOperand - Instances of this class represent a parsed ARM machine
373 class ARMOperand : public MCParsedAsmOperand {
383 k_InstSyncBarrierOpt,
395 k_VectorListAllLanes,
401 k_BitfieldDescriptor,
405 SMLoc StartLoc, EndLoc, AlignmentLoc;
406 SmallVector<unsigned, 8> Registers;
409 ARMCC::CondCodes Val;
416 struct CoprocOptionOp {
429 ARM_ISB::InstSyncBOpt Val;
433 ARM_PROC::IFlags Val;
453 // A vector register list is a sequential list of 1 to 4 registers.
454 struct VectorListOp {
461 struct VectorIndexOp {
469 /// Combined record for all forms of ARM address expressions.
472 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
474 const MCConstantExpr *OffsetImm; // Offset immediate value
475 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
476 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
477 unsigned ShiftImm; // shift for OffsetReg.
478 unsigned Alignment; // 0 = no alignment specified
479 // n = alignment in bytes (2, 4, 8, 16, or 32)
480 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
483 struct PostIdxRegOp {
486 ARM_AM::ShiftOpc ShiftTy;
490 struct ShifterImmOp {
495 struct RegShiftedRegOp {
496 ARM_AM::ShiftOpc ShiftTy;
502 struct RegShiftedImmOp {
503 ARM_AM::ShiftOpc ShiftTy;
520 struct CoprocOptionOp CoprocOption;
521 struct MBOptOp MBOpt;
522 struct ISBOptOp ISBOpt;
523 struct ITMaskOp ITMask;
524 struct IFlagsOp IFlags;
525 struct MMaskOp MMask;
526 struct BankedRegOp BankedReg;
529 struct VectorListOp VectorList;
530 struct VectorIndexOp VectorIndex;
532 struct MemoryOp Memory;
533 struct PostIdxRegOp PostIdxReg;
534 struct ShifterImmOp ShifterImm;
535 struct RegShiftedRegOp RegShiftedReg;
536 struct RegShiftedImmOp RegShiftedImm;
537 struct RotImmOp RotImm;
538 struct BitfieldOp Bitfield;
542 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
543 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
545 StartLoc = o.StartLoc;
562 case k_DPRRegisterList:
563 case k_SPRRegisterList:
564 Registers = o.Registers;
567 case k_VectorListAllLanes:
568 case k_VectorListIndexed:
569 VectorList = o.VectorList;
576 CoprocOption = o.CoprocOption;
581 case k_MemBarrierOpt:
584 case k_InstSyncBarrierOpt:
589 case k_PostIndexRegister:
590 PostIdxReg = o.PostIdxReg;
596 BankedReg = o.BankedReg;
601 case k_ShifterImmediate:
602 ShifterImm = o.ShifterImm;
604 case k_ShiftedRegister:
605 RegShiftedReg = o.RegShiftedReg;
607 case k_ShiftedImmediate:
608 RegShiftedImm = o.RegShiftedImm;
610 case k_RotateImmediate:
613 case k_BitfieldDescriptor:
614 Bitfield = o.Bitfield;
617 VectorIndex = o.VectorIndex;
622 /// getStartLoc - Get the location of the first token of this operand.
623 SMLoc getStartLoc() const override { return StartLoc; }
624 /// getEndLoc - Get the location of the last token of this operand.
625 SMLoc getEndLoc() const override { return EndLoc; }
626 /// getLocRange - Get the range between the first and last token of this
628 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
630 /// getAlignmentLoc - Get the location of the Alignment token of this operand.
631 SMLoc getAlignmentLoc() const {
632 assert(Kind == k_Memory && "Invalid access!");
636 ARMCC::CondCodes getCondCode() const {
637 assert(Kind == k_CondCode && "Invalid access!");
641 unsigned getCoproc() const {
642 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
646 StringRef getToken() const {
647 assert(Kind == k_Token && "Invalid access!");
648 return StringRef(Tok.Data, Tok.Length);
651 unsigned getReg() const override {
652 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
656 const SmallVectorImpl<unsigned> &getRegList() const {
657 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
658 Kind == k_SPRRegisterList) && "Invalid access!");
662 const MCExpr *getImm() const {
663 assert(isImm() && "Invalid access!");
667 unsigned getVectorIndex() const {
668 assert(Kind == k_VectorIndex && "Invalid access!");
669 return VectorIndex.Val;
672 ARM_MB::MemBOpt getMemBarrierOpt() const {
673 assert(Kind == k_MemBarrierOpt && "Invalid access!");
677 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
678 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
682 ARM_PROC::IFlags getProcIFlags() const {
683 assert(Kind == k_ProcIFlags && "Invalid access!");
687 unsigned getMSRMask() const {
688 assert(Kind == k_MSRMask && "Invalid access!");
692 unsigned getBankedReg() const {
693 assert(Kind == k_BankedReg && "Invalid access!");
694 return BankedReg.Val;
697 bool isCoprocNum() const { return Kind == k_CoprocNum; }
698 bool isCoprocReg() const { return Kind == k_CoprocReg; }
699 bool isCoprocOption() const { return Kind == k_CoprocOption; }
700 bool isCondCode() const { return Kind == k_CondCode; }
701 bool isCCOut() const { return Kind == k_CCOut; }
702 bool isITMask() const { return Kind == k_ITCondMask; }
703 bool isITCondCode() const { return Kind == k_CondCode; }
704 bool isImm() const override { return Kind == k_Immediate; }
705 // checks whether this operand is an unsigned offset which fits is a field
706 // of specified width and scaled by a specific number of bits
707 template<unsigned width, unsigned scale>
708 bool isUnsignedOffset() const {
709 if (!isImm()) return false;
710 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
711 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
712 int64_t Val = CE->getValue();
713 int64_t Align = 1LL << scale;
714 int64_t Max = Align * ((1LL << width) - 1);
715 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
719 // checks whether this operand is an signed offset which fits is a field
720 // of specified width and scaled by a specific number of bits
721 template<unsigned width, unsigned scale>
722 bool isSignedOffset() const {
723 if (!isImm()) return false;
724 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
725 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
726 int64_t Val = CE->getValue();
727 int64_t Align = 1LL << scale;
728 int64_t Max = Align * ((1LL << (width-1)) - 1);
729 int64_t Min = -Align * (1LL << (width-1));
730 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
735 // checks whether this operand is a memory operand computed as an offset
736 // applied to PC. the offset may have 8 bits of magnitude and is represented
737 // with two bits of shift. textually it may be either [pc, #imm], #imm or
738 // relocable expression...
739 bool isThumbMemPC() const {
742 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
743 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
744 if (!CE) return false;
745 Val = CE->getValue();
748 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
749 if(Memory.BaseRegNum != ARM::PC) return false;
750 Val = Memory.OffsetImm->getValue();
753 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
755 bool isFPImm() const {
756 if (!isImm()) return false;
757 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
758 if (!CE) return false;
759 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
762 bool isFBits16() const {
763 if (!isImm()) return false;
764 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
765 if (!CE) return false;
766 int64_t Value = CE->getValue();
767 return Value >= 0 && Value <= 16;
769 bool isFBits32() const {
770 if (!isImm()) return false;
771 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
772 if (!CE) return false;
773 int64_t Value = CE->getValue();
774 return Value >= 1 && Value <= 32;
776 bool isImm8s4() const {
777 if (!isImm()) return false;
778 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
779 if (!CE) return false;
780 int64_t Value = CE->getValue();
781 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
783 bool isImm0_1020s4() const {
784 if (!isImm()) return false;
785 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
786 if (!CE) return false;
787 int64_t Value = CE->getValue();
788 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
790 bool isImm0_508s4() const {
791 if (!isImm()) return false;
792 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
793 if (!CE) return false;
794 int64_t Value = CE->getValue();
795 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
797 bool isImm0_508s4Neg() const {
798 if (!isImm()) return false;
799 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
800 if (!CE) return false;
801 int64_t Value = -CE->getValue();
802 // explicitly exclude zero. we want that to use the normal 0_508 version.
803 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
805 bool isImm0_239() const {
806 if (!isImm()) return false;
807 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
808 if (!CE) return false;
809 int64_t Value = CE->getValue();
810 return Value >= 0 && Value < 240;
812 bool isImm0_255() const {
813 if (!isImm()) return false;
814 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
815 if (!CE) return false;
816 int64_t Value = CE->getValue();
817 return Value >= 0 && Value < 256;
819 bool isImm0_4095() const {
820 if (!isImm()) return false;
821 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
822 if (!CE) return false;
823 int64_t Value = CE->getValue();
824 return Value >= 0 && Value < 4096;
826 bool isImm0_4095Neg() const {
827 if (!isImm()) return false;
828 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
829 if (!CE) return false;
830 int64_t Value = -CE->getValue();
831 return Value > 0 && Value < 4096;
833 bool isImm0_1() const {
834 if (!isImm()) return false;
835 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
836 if (!CE) return false;
837 int64_t Value = CE->getValue();
838 return Value >= 0 && Value < 2;
840 bool isImm0_3() const {
841 if (!isImm()) return false;
842 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
843 if (!CE) return false;
844 int64_t Value = CE->getValue();
845 return Value >= 0 && Value < 4;
847 bool isImm0_7() const {
848 if (!isImm()) return false;
849 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
850 if (!CE) return false;
851 int64_t Value = CE->getValue();
852 return Value >= 0 && Value < 8;
854 bool isImm0_15() const {
855 if (!isImm()) return false;
856 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
857 if (!CE) return false;
858 int64_t Value = CE->getValue();
859 return Value >= 0 && Value < 16;
861 bool isImm0_31() const {
862 if (!isImm()) return false;
863 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
864 if (!CE) return false;
865 int64_t Value = CE->getValue();
866 return Value >= 0 && Value < 32;
868 bool isImm0_63() const {
869 if (!isImm()) return false;
870 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
871 if (!CE) return false;
872 int64_t Value = CE->getValue();
873 return Value >= 0 && Value < 64;
875 bool isImm8() const {
876 if (!isImm()) return false;
877 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
878 if (!CE) return false;
879 int64_t Value = CE->getValue();
882 bool isImm16() const {
883 if (!isImm()) return false;
884 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
885 if (!CE) return false;
886 int64_t Value = CE->getValue();
889 bool isImm32() const {
890 if (!isImm()) return false;
891 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
892 if (!CE) return false;
893 int64_t Value = CE->getValue();
896 bool isShrImm8() const {
897 if (!isImm()) return false;
898 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
899 if (!CE) return false;
900 int64_t Value = CE->getValue();
901 return Value > 0 && Value <= 8;
903 bool isShrImm16() const {
904 if (!isImm()) return false;
905 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
906 if (!CE) return false;
907 int64_t Value = CE->getValue();
908 return Value > 0 && Value <= 16;
910 bool isShrImm32() const {
911 if (!isImm()) return false;
912 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
913 if (!CE) return false;
914 int64_t Value = CE->getValue();
915 return Value > 0 && Value <= 32;
917 bool isShrImm64() const {
918 if (!isImm()) return false;
919 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
920 if (!CE) return false;
921 int64_t Value = CE->getValue();
922 return Value > 0 && Value <= 64;
924 bool isImm1_7() const {
925 if (!isImm()) return false;
926 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
927 if (!CE) return false;
928 int64_t Value = CE->getValue();
929 return Value > 0 && Value < 8;
931 bool isImm1_15() const {
932 if (!isImm()) return false;
933 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
934 if (!CE) return false;
935 int64_t Value = CE->getValue();
936 return Value > 0 && Value < 16;
938 bool isImm1_31() const {
939 if (!isImm()) return false;
940 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
941 if (!CE) return false;
942 int64_t Value = CE->getValue();
943 return Value > 0 && Value < 32;
945 bool isImm1_16() const {
946 if (!isImm()) return false;
947 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
948 if (!CE) return false;
949 int64_t Value = CE->getValue();
950 return Value > 0 && Value < 17;
952 bool isImm1_32() const {
953 if (!isImm()) return false;
954 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
955 if (!CE) return false;
956 int64_t Value = CE->getValue();
957 return Value > 0 && Value < 33;
959 bool isImm0_32() const {
960 if (!isImm()) return false;
961 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
962 if (!CE) return false;
963 int64_t Value = CE->getValue();
964 return Value >= 0 && Value < 33;
966 bool isImm0_65535() const {
967 if (!isImm()) return false;
968 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
969 if (!CE) return false;
970 int64_t Value = CE->getValue();
971 return Value >= 0 && Value < 65536;
973 bool isImm256_65535Expr() const {
974 if (!isImm()) return false;
975 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
976 // If it's not a constant expression, it'll generate a fixup and be
978 if (!CE) return true;
979 int64_t Value = CE->getValue();
980 return Value >= 256 && Value < 65536;
982 bool isImm0_65535Expr() const {
983 if (!isImm()) return false;
984 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
985 // If it's not a constant expression, it'll generate a fixup and be
987 if (!CE) return true;
988 int64_t Value = CE->getValue();
989 return Value >= 0 && Value < 65536;
991 bool isImm24bit() const {
992 if (!isImm()) return false;
993 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
994 if (!CE) return false;
995 int64_t Value = CE->getValue();
996 return Value >= 0 && Value <= 0xffffff;
998 bool isImmThumbSR() const {
999 if (!isImm()) return false;
1000 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1001 if (!CE) return false;
1002 int64_t Value = CE->getValue();
1003 return Value > 0 && Value < 33;
1005 bool isPKHLSLImm() const {
1006 if (!isImm()) return false;
1007 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1008 if (!CE) return false;
1009 int64_t Value = CE->getValue();
1010 return Value >= 0 && Value < 32;
1012 bool isPKHASRImm() const {
1013 if (!isImm()) return false;
1014 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1015 if (!CE) return false;
1016 int64_t Value = CE->getValue();
1017 return Value > 0 && Value <= 32;
1019 bool isAdrLabel() const {
1020 // If we have an immediate that's not a constant, treat it as a label
1021 // reference needing a fixup. If it is a constant, but it can't fit
1022 // into shift immediate encoding, we reject it.
1023 if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
1024 else return (isARMSOImm() || isARMSOImmNeg());
1026 bool isARMSOImm() const {
1027 if (!isImm()) return false;
1028 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1029 if (!CE) return false;
1030 int64_t Value = CE->getValue();
1031 return ARM_AM::getSOImmVal(Value) != -1;
1033 bool isARMSOImmNot() const {
1034 if (!isImm()) return false;
1035 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1036 if (!CE) return false;
1037 int64_t Value = CE->getValue();
1038 return ARM_AM::getSOImmVal(~Value) != -1;
1040 bool isARMSOImmNeg() const {
1041 if (!isImm()) return false;
1042 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1043 if (!CE) return false;
1044 int64_t Value = CE->getValue();
1045 // Only use this when not representable as a plain so_imm.
1046 return ARM_AM::getSOImmVal(Value) == -1 &&
1047 ARM_AM::getSOImmVal(-Value) != -1;
1049 bool isT2SOImm() const {
1050 if (!isImm()) return false;
1051 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1052 if (!CE) return false;
1053 int64_t Value = CE->getValue();
1054 return ARM_AM::getT2SOImmVal(Value) != -1;
1056 bool isT2SOImmNot() const {
1057 if (!isImm()) return false;
1058 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1059 if (!CE) return false;
1060 int64_t Value = CE->getValue();
1061 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1062 ARM_AM::getT2SOImmVal(~Value) != -1;
1064 bool isT2SOImmNeg() const {
1065 if (!isImm()) return false;
1066 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1067 if (!CE) return false;
1068 int64_t Value = CE->getValue();
1069 // Only use this when not representable as a plain so_imm.
1070 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1071 ARM_AM::getT2SOImmVal(-Value) != -1;
1073 bool isSetEndImm() const {
1074 if (!isImm()) return false;
1075 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1076 if (!CE) return false;
1077 int64_t Value = CE->getValue();
1078 return Value == 1 || Value == 0;
1080 bool isReg() const override { return Kind == k_Register; }
1081 bool isRegList() const { return Kind == k_RegisterList; }
1082 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1083 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1084 bool isToken() const override { return Kind == k_Token; }
1085 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1086 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1087 bool isMem() const override { return Kind == k_Memory; }
1088 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1089 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
1090 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
1091 bool isRotImm() const { return Kind == k_RotateImmediate; }
1092 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1093 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
1094 bool isPostIdxReg() const {
1095 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
1097 bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1100 // No offset of any kind.
1101 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1102 (alignOK || Memory.Alignment == Alignment);
1104 bool isMemPCRelImm12() const {
1105 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1107 // Base register must be PC.
1108 if (Memory.BaseRegNum != ARM::PC)
1110 // Immediate offset in range [-4095, 4095].
1111 if (!Memory.OffsetImm) return true;
1112 int64_t Val = Memory.OffsetImm->getValue();
1113 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1115 bool isAlignedMemory() const {
1116 return isMemNoOffset(true);
1118 bool isAlignedMemoryNone() const {
1119 return isMemNoOffset(false, 0);
1121 bool isDupAlignedMemoryNone() const {
1122 return isMemNoOffset(false, 0);
1124 bool isAlignedMemory16() const {
1125 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1127 return isMemNoOffset(false, 0);
1129 bool isDupAlignedMemory16() const {
1130 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1132 return isMemNoOffset(false, 0);
1134 bool isAlignedMemory32() const {
1135 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1137 return isMemNoOffset(false, 0);
1139 bool isDupAlignedMemory32() const {
1140 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1142 return isMemNoOffset(false, 0);
1144 bool isAlignedMemory64() const {
1145 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1147 return isMemNoOffset(false, 0);
1149 bool isDupAlignedMemory64() const {
1150 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1152 return isMemNoOffset(false, 0);
1154 bool isAlignedMemory64or128() const {
1155 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1157 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1159 return isMemNoOffset(false, 0);
1161 bool isDupAlignedMemory64or128() const {
1162 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1164 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1166 return isMemNoOffset(false, 0);
1168 bool isAlignedMemory64or128or256() const {
1169 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1171 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1173 if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
1175 return isMemNoOffset(false, 0);
1177 bool isAddrMode2() const {
1178 if (!isMem() || Memory.Alignment != 0) return false;
1179 // Check for register offset.
1180 if (Memory.OffsetRegNum) return true;
1181 // Immediate offset in range [-4095, 4095].
1182 if (!Memory.OffsetImm) return true;
1183 int64_t Val = Memory.OffsetImm->getValue();
1184 return Val > -4096 && Val < 4096;
1186 bool isAM2OffsetImm() const {
1187 if (!isImm()) return false;
1188 // Immediate offset in range [-4095, 4095].
1189 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1190 if (!CE) return false;
1191 int64_t Val = CE->getValue();
1192 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1194 bool isAddrMode3() const {
1195 // If we have an immediate that's not a constant, treat it as a label
1196 // reference needing a fixup. If it is a constant, it's something else
1197 // and we reject it.
1198 if (isImm() && !isa<MCConstantExpr>(getImm()))
1200 if (!isMem() || Memory.Alignment != 0) return false;
1201 // No shifts are legal for AM3.
1202 if (Memory.ShiftType != ARM_AM::no_shift) return false;
1203 // Check for register offset.
1204 if (Memory.OffsetRegNum) return true;
1205 // Immediate offset in range [-255, 255].
1206 if (!Memory.OffsetImm) return true;
1207 int64_t Val = Memory.OffsetImm->getValue();
1208 // The #-0 offset is encoded as INT32_MIN, and we have to check
1210 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1212 bool isAM3Offset() const {
1213 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1215 if (Kind == k_PostIndexRegister)
1216 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1217 // Immediate offset in range [-255, 255].
1218 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1219 if (!CE) return false;
1220 int64_t Val = CE->getValue();
1221 // Special case, #-0 is INT32_MIN.
1222 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1224 bool isAddrMode5() const {
1225 // If we have an immediate that's not a constant, treat it as a label
1226 // reference needing a fixup. If it is a constant, it's something else
1227 // and we reject it.
1228 if (isImm() && !isa<MCConstantExpr>(getImm()))
1230 if (!isMem() || Memory.Alignment != 0) return false;
1231 // Check for register offset.
1232 if (Memory.OffsetRegNum) return false;
1233 // Immediate offset in range [-1020, 1020] and a multiple of 4.
1234 if (!Memory.OffsetImm) return true;
1235 int64_t Val = Memory.OffsetImm->getValue();
1236 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1239 bool isMemTBB() const {
1240 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1241 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1245 bool isMemTBH() const {
1246 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1247 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1248 Memory.Alignment != 0 )
1252 bool isMemRegOffset() const {
1253 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1257 bool isT2MemRegOffset() const {
1258 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1259 Memory.Alignment != 0)
1261 // Only lsl #{0, 1, 2, 3} allowed.
1262 if (Memory.ShiftType == ARM_AM::no_shift)
1264 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1268 bool isMemThumbRR() const {
1269 // Thumb reg+reg addressing is simple. Just two registers, a base and
1270 // an offset. No shifts, negations or any other complicating factors.
1271 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1272 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1274 return isARMLowRegister(Memory.BaseRegNum) &&
1275 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1277 bool isMemThumbRIs4() const {
1278 if (!isMem() || Memory.OffsetRegNum != 0 ||
1279 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1281 // Immediate offset, multiple of 4 in range [0, 124].
1282 if (!Memory.OffsetImm) return true;
1283 int64_t Val = Memory.OffsetImm->getValue();
1284 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1286 bool isMemThumbRIs2() const {
1287 if (!isMem() || Memory.OffsetRegNum != 0 ||
1288 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1290 // Immediate offset, multiple of 4 in range [0, 62].
1291 if (!Memory.OffsetImm) return true;
1292 int64_t Val = Memory.OffsetImm->getValue();
1293 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1295 bool isMemThumbRIs1() const {
1296 if (!isMem() || Memory.OffsetRegNum != 0 ||
1297 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1299 // Immediate offset in range [0, 31].
1300 if (!Memory.OffsetImm) return true;
1301 int64_t Val = Memory.OffsetImm->getValue();
1302 return Val >= 0 && Val <= 31;
1304 bool isMemThumbSPI() const {
1305 if (!isMem() || Memory.OffsetRegNum != 0 ||
1306 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1308 // Immediate offset, multiple of 4 in range [0, 1020].
1309 if (!Memory.OffsetImm) return true;
1310 int64_t Val = Memory.OffsetImm->getValue();
1311 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1313 bool isMemImm8s4Offset() const {
1314 // If we have an immediate that's not a constant, treat it as a label
1315 // reference needing a fixup. If it is a constant, it's something else
1316 // and we reject it.
1317 if (isImm() && !isa<MCConstantExpr>(getImm()))
1319 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1321 // Immediate offset a multiple of 4 in range [-1020, 1020].
1322 if (!Memory.OffsetImm) return true;
1323 int64_t Val = Memory.OffsetImm->getValue();
1324 // Special case, #-0 is INT32_MIN.
1325 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1327 bool isMemImm0_1020s4Offset() const {
1328 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1330 // Immediate offset a multiple of 4 in range [0, 1020].
1331 if (!Memory.OffsetImm) return true;
1332 int64_t Val = Memory.OffsetImm->getValue();
1333 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1335 bool isMemImm8Offset() const {
1336 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1338 // Base reg of PC isn't allowed for these encodings.
1339 if (Memory.BaseRegNum == ARM::PC) return false;
1340 // Immediate offset in range [-255, 255].
1341 if (!Memory.OffsetImm) return true;
1342 int64_t Val = Memory.OffsetImm->getValue();
1343 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1345 bool isMemPosImm8Offset() const {
1346 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1348 // Immediate offset in range [0, 255].
1349 if (!Memory.OffsetImm) return true;
1350 int64_t Val = Memory.OffsetImm->getValue();
1351 return Val >= 0 && Val < 256;
1353 bool isMemNegImm8Offset() const {
1354 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1356 // Base reg of PC isn't allowed for these encodings.
1357 if (Memory.BaseRegNum == ARM::PC) return false;
1358 // Immediate offset in range [-255, -1].
1359 if (!Memory.OffsetImm) return false;
1360 int64_t Val = Memory.OffsetImm->getValue();
1361 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1363 bool isMemUImm12Offset() const {
1364 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1366 // Immediate offset in range [0, 4095].
1367 if (!Memory.OffsetImm) return true;
1368 int64_t Val = Memory.OffsetImm->getValue();
1369 return (Val >= 0 && Val < 4096);
1371 bool isMemImm12Offset() const {
1372 // If we have an immediate that's not a constant, treat it as a label
1373 // reference needing a fixup. If it is a constant, it's something else
1374 // and we reject it.
1375 if (isImm() && !isa<MCConstantExpr>(getImm()))
1378 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1380 // Immediate offset in range [-4095, 4095].
1381 if (!Memory.OffsetImm) return true;
1382 int64_t Val = Memory.OffsetImm->getValue();
1383 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1385 bool isPostIdxImm8() const {
1386 if (!isImm()) return false;
1387 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1388 if (!CE) return false;
1389 int64_t Val = CE->getValue();
1390 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1392 bool isPostIdxImm8s4() const {
1393 if (!isImm()) return false;
1394 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1395 if (!CE) return false;
1396 int64_t Val = CE->getValue();
1397 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1401 bool isMSRMask() const { return Kind == k_MSRMask; }
1402 bool isBankedReg() const { return Kind == k_BankedReg; }
1403 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1406 bool isSingleSpacedVectorList() const {
1407 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1409 bool isDoubleSpacedVectorList() const {
1410 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1412 bool isVecListOneD() const {
1413 if (!isSingleSpacedVectorList()) return false;
1414 return VectorList.Count == 1;
1417 bool isVecListDPair() const {
1418 if (!isSingleSpacedVectorList()) return false;
1419 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1420 .contains(VectorList.RegNum));
1423 bool isVecListThreeD() const {
1424 if (!isSingleSpacedVectorList()) return false;
1425 return VectorList.Count == 3;
1428 bool isVecListFourD() const {
1429 if (!isSingleSpacedVectorList()) return false;
1430 return VectorList.Count == 4;
1433 bool isVecListDPairSpaced() const {
1434 if (Kind != k_VectorList) return false;
1435 if (isSingleSpacedVectorList()) return false;
1436 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1437 .contains(VectorList.RegNum));
1440 bool isVecListThreeQ() const {
1441 if (!isDoubleSpacedVectorList()) return false;
1442 return VectorList.Count == 3;
1445 bool isVecListFourQ() const {
1446 if (!isDoubleSpacedVectorList()) return false;
1447 return VectorList.Count == 4;
1450 bool isSingleSpacedVectorAllLanes() const {
1451 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1453 bool isDoubleSpacedVectorAllLanes() const {
1454 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1456 bool isVecListOneDAllLanes() const {
1457 if (!isSingleSpacedVectorAllLanes()) return false;
1458 return VectorList.Count == 1;
1461 bool isVecListDPairAllLanes() const {
1462 if (!isSingleSpacedVectorAllLanes()) return false;
1463 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1464 .contains(VectorList.RegNum));
1467 bool isVecListDPairSpacedAllLanes() const {
1468 if (!isDoubleSpacedVectorAllLanes()) return false;
1469 return VectorList.Count == 2;
1472 bool isVecListThreeDAllLanes() const {
1473 if (!isSingleSpacedVectorAllLanes()) return false;
1474 return VectorList.Count == 3;
1477 bool isVecListThreeQAllLanes() const {
1478 if (!isDoubleSpacedVectorAllLanes()) return false;
1479 return VectorList.Count == 3;
1482 bool isVecListFourDAllLanes() const {
1483 if (!isSingleSpacedVectorAllLanes()) return false;
1484 return VectorList.Count == 4;
1487 bool isVecListFourQAllLanes() const {
1488 if (!isDoubleSpacedVectorAllLanes()) return false;
1489 return VectorList.Count == 4;
1492 bool isSingleSpacedVectorIndexed() const {
1493 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1495 bool isDoubleSpacedVectorIndexed() const {
1496 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1498 bool isVecListOneDByteIndexed() const {
1499 if (!isSingleSpacedVectorIndexed()) return false;
1500 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1503 bool isVecListOneDHWordIndexed() const {
1504 if (!isSingleSpacedVectorIndexed()) return false;
1505 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1508 bool isVecListOneDWordIndexed() const {
1509 if (!isSingleSpacedVectorIndexed()) return false;
1510 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1513 bool isVecListTwoDByteIndexed() const {
1514 if (!isSingleSpacedVectorIndexed()) return false;
1515 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1518 bool isVecListTwoDHWordIndexed() const {
1519 if (!isSingleSpacedVectorIndexed()) return false;
1520 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1523 bool isVecListTwoQWordIndexed() const {
1524 if (!isDoubleSpacedVectorIndexed()) return false;
1525 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1528 bool isVecListTwoQHWordIndexed() const {
1529 if (!isDoubleSpacedVectorIndexed()) return false;
1530 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1533 bool isVecListTwoDWordIndexed() const {
1534 if (!isSingleSpacedVectorIndexed()) return false;
1535 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1538 bool isVecListThreeDByteIndexed() const {
1539 if (!isSingleSpacedVectorIndexed()) return false;
1540 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1543 bool isVecListThreeDHWordIndexed() const {
1544 if (!isSingleSpacedVectorIndexed()) return false;
1545 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1548 bool isVecListThreeQWordIndexed() const {
1549 if (!isDoubleSpacedVectorIndexed()) return false;
1550 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1553 bool isVecListThreeQHWordIndexed() const {
1554 if (!isDoubleSpacedVectorIndexed()) return false;
1555 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1558 bool isVecListThreeDWordIndexed() const {
1559 if (!isSingleSpacedVectorIndexed()) return false;
1560 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1563 bool isVecListFourDByteIndexed() const {
1564 if (!isSingleSpacedVectorIndexed()) return false;
1565 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1568 bool isVecListFourDHWordIndexed() const {
1569 if (!isSingleSpacedVectorIndexed()) return false;
1570 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1573 bool isVecListFourQWordIndexed() const {
1574 if (!isDoubleSpacedVectorIndexed()) return false;
1575 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1578 bool isVecListFourQHWordIndexed() const {
1579 if (!isDoubleSpacedVectorIndexed()) return false;
1580 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1583 bool isVecListFourDWordIndexed() const {
1584 if (!isSingleSpacedVectorIndexed()) return false;
1585 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1588 bool isVectorIndex8() const {
1589 if (Kind != k_VectorIndex) return false;
1590 return VectorIndex.Val < 8;
1592 bool isVectorIndex16() const {
1593 if (Kind != k_VectorIndex) return false;
1594 return VectorIndex.Val < 4;
1596 bool isVectorIndex32() const {
1597 if (Kind != k_VectorIndex) return false;
1598 return VectorIndex.Val < 2;
1601 bool isNEONi8splat() const {
1602 if (!isImm()) return false;
1603 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1604 // Must be a constant.
1605 if (!CE) return false;
1606 int64_t Value = CE->getValue();
1607 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1609 return Value >= 0 && Value < 256;
1612 bool isNEONi16splat() const {
1613 if (isNEONByteReplicate(2))
1614 return false; // Leave that for bytes replication and forbid by default.
1617 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1618 // Must be a constant.
1619 if (!CE) return false;
1620 int64_t Value = CE->getValue();
1621 // i16 value in the range [0,255] or [0x0100, 0xff00]
1622 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1625 bool isNEONi32splat() const {
1626 if (isNEONByteReplicate(4))
1627 return false; // Leave that for bytes replication and forbid by default.
1630 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1631 // Must be a constant.
1632 if (!CE) return false;
1633 int64_t Value = CE->getValue();
1634 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1635 return (Value >= 0 && Value < 256) ||
1636 (Value >= 0x0100 && Value <= 0xff00) ||
1637 (Value >= 0x010000 && Value <= 0xff0000) ||
1638 (Value >= 0x01000000 && Value <= 0xff000000);
1641 bool isNEONByteReplicate(unsigned NumBytes) const {
1644 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1645 // Must be a constant.
1648 int64_t Value = CE->getValue();
1650 return false; // Don't bother with zero.
1652 unsigned char B = Value & 0xff;
1653 for (unsigned i = 1; i < NumBytes; ++i) {
1655 if ((Value & 0xff) != B)
1660 bool isNEONi16ByteReplicate() const { return isNEONByteReplicate(2); }
1661 bool isNEONi32ByteReplicate() const { return isNEONByteReplicate(4); }
1662 bool isNEONi32vmov() const {
1663 if (isNEONByteReplicate(4))
1664 return false; // Let it to be classified as byte-replicate case.
1667 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1668 // Must be a constant.
1671 int64_t Value = CE->getValue();
1672 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1673 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1674 return (Value >= 0 && Value < 256) ||
1675 (Value >= 0x0100 && Value <= 0xff00) ||
1676 (Value >= 0x010000 && Value <= 0xff0000) ||
1677 (Value >= 0x01000000 && Value <= 0xff000000) ||
1678 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1679 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1681 bool isNEONi32vmovNeg() const {
1682 if (!isImm()) return false;
1683 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1684 // Must be a constant.
1685 if (!CE) return false;
1686 int64_t Value = ~CE->getValue();
1687 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1688 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1689 return (Value >= 0 && Value < 256) ||
1690 (Value >= 0x0100 && Value <= 0xff00) ||
1691 (Value >= 0x010000 && Value <= 0xff0000) ||
1692 (Value >= 0x01000000 && Value <= 0xff000000) ||
1693 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1694 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1697 bool isNEONi64splat() const {
1698 if (!isImm()) return false;
1699 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1700 // Must be a constant.
1701 if (!CE) return false;
1702 uint64_t Value = CE->getValue();
1703 // i64 value with each byte being either 0 or 0xff.
1704 for (unsigned i = 0; i < 8; ++i)
1705 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1709 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1710 // Add as immediates when possible. Null MCExpr = 0.
1712 Inst.addOperand(MCOperand::CreateImm(0));
1713 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1714 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1716 Inst.addOperand(MCOperand::CreateExpr(Expr));
1719 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1720 assert(N == 2 && "Invalid number of operands!");
1721 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1722 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1723 Inst.addOperand(MCOperand::CreateReg(RegNum));
1726 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1727 assert(N == 1 && "Invalid number of operands!");
1728 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1731 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1732 assert(N == 1 && "Invalid number of operands!");
1733 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1736 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1737 assert(N == 1 && "Invalid number of operands!");
1738 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1741 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1742 assert(N == 1 && "Invalid number of operands!");
1743 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1746 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1747 assert(N == 1 && "Invalid number of operands!");
1748 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1751 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1752 assert(N == 1 && "Invalid number of operands!");
1753 Inst.addOperand(MCOperand::CreateReg(getReg()));
1756 void addRegOperands(MCInst &Inst, unsigned N) const {
1757 assert(N == 1 && "Invalid number of operands!");
1758 Inst.addOperand(MCOperand::CreateReg(getReg()));
1761 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1762 assert(N == 3 && "Invalid number of operands!");
1763 assert(isRegShiftedReg() &&
1764 "addRegShiftedRegOperands() on non-RegShiftedReg!");
1765 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1766 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1767 Inst.addOperand(MCOperand::CreateImm(
1768 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1771 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1772 assert(N == 2 && "Invalid number of operands!");
1773 assert(isRegShiftedImm() &&
1774 "addRegShiftedImmOperands() on non-RegShiftedImm!");
1775 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1776 // Shift of #32 is encoded as 0 where permitted
1777 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1778 Inst.addOperand(MCOperand::CreateImm(
1779 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1782 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1783 assert(N == 1 && "Invalid number of operands!");
1784 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1788 void addRegListOperands(MCInst &Inst, unsigned N) const {
1789 assert(N == 1 && "Invalid number of operands!");
1790 const SmallVectorImpl<unsigned> &RegList = getRegList();
1791 for (SmallVectorImpl<unsigned>::const_iterator
1792 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1793 Inst.addOperand(MCOperand::CreateReg(*I));
1796 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1797 addRegListOperands(Inst, N);
1800 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1801 addRegListOperands(Inst, N);
1804 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1805 assert(N == 1 && "Invalid number of operands!");
1806 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1807 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1810 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1811 assert(N == 1 && "Invalid number of operands!");
1812 // Munge the lsb/width into a bitfield mask.
1813 unsigned lsb = Bitfield.LSB;
1814 unsigned width = Bitfield.Width;
1815 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1816 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1817 (32 - (lsb + width)));
1818 Inst.addOperand(MCOperand::CreateImm(Mask));
1821 void addImmOperands(MCInst &Inst, unsigned N) const {
1822 assert(N == 1 && "Invalid number of operands!");
1823 addExpr(Inst, getImm());
1826 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1827 assert(N == 1 && "Invalid number of operands!");
1828 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1829 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1832 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1833 assert(N == 1 && "Invalid number of operands!");
1834 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1835 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1838 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1839 assert(N == 1 && "Invalid number of operands!");
1840 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1841 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1842 Inst.addOperand(MCOperand::CreateImm(Val));
1845 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1846 assert(N == 1 && "Invalid number of operands!");
1847 // FIXME: We really want to scale the value here, but the LDRD/STRD
1848 // instruction don't encode operands that way yet.
1849 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1850 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1853 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1854 assert(N == 1 && "Invalid number of operands!");
1855 // The immediate is scaled by four in the encoding and is stored
1856 // in the MCInst as such. Lop off the low two bits here.
1857 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1858 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1861 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1862 assert(N == 1 && "Invalid number of operands!");
1863 // The immediate is scaled by four in the encoding and is stored
1864 // in the MCInst as such. Lop off the low two bits here.
1865 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1866 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1869 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1870 assert(N == 1 && "Invalid number of operands!");
1871 // The immediate is scaled by four in the encoding and is stored
1872 // in the MCInst as such. Lop off the low two bits here.
1873 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1874 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1877 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1878 assert(N == 1 && "Invalid number of operands!");
1879 // The constant encodes as the immediate-1, and we store in the instruction
1880 // the bits as encoded, so subtract off one here.
1881 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1882 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1885 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1886 assert(N == 1 && "Invalid number of operands!");
1887 // The constant encodes as the immediate-1, and we store in the instruction
1888 // the bits as encoded, so subtract off one here.
1889 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1890 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1893 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1894 assert(N == 1 && "Invalid number of operands!");
1895 // The constant encodes as the immediate, except for 32, which encodes as
1897 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1898 unsigned Imm = CE->getValue();
1899 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1902 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1903 assert(N == 1 && "Invalid number of operands!");
1904 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1905 // the instruction as well.
1906 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1907 int Val = CE->getValue();
1908 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1911 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1912 assert(N == 1 && "Invalid number of operands!");
1913 // The operand is actually a t2_so_imm, but we have its bitwise
1914 // negation in the assembly source, so twiddle it here.
1915 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1916 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1919 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1920 assert(N == 1 && "Invalid number of operands!");
1921 // The operand is actually a t2_so_imm, but we have its
1922 // negation in the assembly source, so twiddle it here.
1923 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1924 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1927 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1928 assert(N == 1 && "Invalid number of operands!");
1929 // The operand is actually an imm0_4095, but we have its
1930 // negation in the assembly source, so twiddle it here.
1931 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1932 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1935 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1936 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1937 Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
1941 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1942 assert(SR && "Unknown value type!");
1943 Inst.addOperand(MCOperand::CreateExpr(SR));
1946 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
1947 assert(N == 1 && "Invalid number of operands!");
1949 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1951 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1955 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1956 assert(SR && "Unknown value type!");
1957 Inst.addOperand(MCOperand::CreateExpr(SR));
1961 assert(isMem() && "Unknown value type!");
1962 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
1963 Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
1966 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1967 assert(N == 1 && "Invalid number of operands!");
1968 // The operand is actually a so_imm, but we have its bitwise
1969 // negation in the assembly source, so twiddle it here.
1970 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1971 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1974 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1975 assert(N == 1 && "Invalid number of operands!");
1976 // The operand is actually a so_imm, but we have its
1977 // negation in the assembly source, so twiddle it here.
1978 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1979 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1982 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1983 assert(N == 1 && "Invalid number of operands!");
1984 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1987 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
1988 assert(N == 1 && "Invalid number of operands!");
1989 Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
1992 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1993 assert(N == 1 && "Invalid number of operands!");
1994 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1997 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1998 assert(N == 1 && "Invalid number of operands!");
1999 int32_t Imm = Memory.OffsetImm->getValue();
2000 Inst.addOperand(MCOperand::CreateImm(Imm));
2003 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
2004 assert(N == 1 && "Invalid number of operands!");
2005 assert(isImm() && "Not an immediate!");
2007 // If we have an immediate that's not a constant, treat it as a label
2008 // reference needing a fixup.
2009 if (!isa<MCConstantExpr>(getImm())) {
2010 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2014 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2015 int Val = CE->getValue();
2016 Inst.addOperand(MCOperand::CreateImm(Val));
2019 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
2020 assert(N == 2 && "Invalid number of operands!");
2021 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2022 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
2025 void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2026 addAlignedMemoryOperands(Inst, N);
2029 void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2030 addAlignedMemoryOperands(Inst, N);
2033 void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2034 addAlignedMemoryOperands(Inst, N);
2037 void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2038 addAlignedMemoryOperands(Inst, N);
2041 void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2042 addAlignedMemoryOperands(Inst, N);
2045 void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2046 addAlignedMemoryOperands(Inst, N);
2049 void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2050 addAlignedMemoryOperands(Inst, N);
2053 void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2054 addAlignedMemoryOperands(Inst, N);
2057 void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2058 addAlignedMemoryOperands(Inst, N);
2061 void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2062 addAlignedMemoryOperands(Inst, N);
2065 void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2066 addAlignedMemoryOperands(Inst, N);
2069 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
2070 assert(N == 3 && "Invalid number of operands!");
2071 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2072 if (!Memory.OffsetRegNum) {
2073 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2074 // Special case for #-0
2075 if (Val == INT32_MIN) Val = 0;
2076 if (Val < 0) Val = -Val;
2077 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2079 // For register offset, we encode the shift type and negation flag
2081 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2082 Memory.ShiftImm, Memory.ShiftType);
2084 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2085 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2086 Inst.addOperand(MCOperand::CreateImm(Val));
2089 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2090 assert(N == 2 && "Invalid number of operands!");
2091 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2092 assert(CE && "non-constant AM2OffsetImm operand!");
2093 int32_t Val = CE->getValue();
2094 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2095 // Special case for #-0
2096 if (Val == INT32_MIN) Val = 0;
2097 if (Val < 0) Val = -Val;
2098 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2099 Inst.addOperand(MCOperand::CreateReg(0));
2100 Inst.addOperand(MCOperand::CreateImm(Val));
2103 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2104 assert(N == 3 && "Invalid number of operands!");
2105 // If we have an immediate that's not a constant, treat it as a label
2106 // reference needing a fixup. If it is a constant, it's something else
2107 // and we reject it.
2109 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2110 Inst.addOperand(MCOperand::CreateReg(0));
2111 Inst.addOperand(MCOperand::CreateImm(0));
2115 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2116 if (!Memory.OffsetRegNum) {
2117 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2118 // Special case for #-0
2119 if (Val == INT32_MIN) Val = 0;
2120 if (Val < 0) Val = -Val;
2121 Val = ARM_AM::getAM3Opc(AddSub, Val);
2123 // For register offset, we encode the shift type and negation flag
2125 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
2127 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2128 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2129 Inst.addOperand(MCOperand::CreateImm(Val));
2132 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
2133 assert(N == 2 && "Invalid number of operands!");
2134 if (Kind == k_PostIndexRegister) {
2136 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
2137 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2138 Inst.addOperand(MCOperand::CreateImm(Val));
2143 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
2144 int32_t Val = CE->getValue();
2145 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2146 // Special case for #-0
2147 if (Val == INT32_MIN) Val = 0;
2148 if (Val < 0) Val = -Val;
2149 Val = ARM_AM::getAM3Opc(AddSub, Val);
2150 Inst.addOperand(MCOperand::CreateReg(0));
2151 Inst.addOperand(MCOperand::CreateImm(Val));
2154 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2155 assert(N == 2 && "Invalid number of operands!");
2156 // If we have an immediate that's not a constant, treat it as a label
2157 // reference needing a fixup. If it is a constant, it's something else
2158 // and we reject it.
2160 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2161 Inst.addOperand(MCOperand::CreateImm(0));
2165 // The lower two bits are always zero and as such are not encoded.
2166 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2167 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2168 // Special case for #-0
2169 if (Val == INT32_MIN) Val = 0;
2170 if (Val < 0) Val = -Val;
2171 Val = ARM_AM::getAM5Opc(AddSub, Val);
2172 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2173 Inst.addOperand(MCOperand::CreateImm(Val));
2176 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2177 assert(N == 2 && "Invalid number of operands!");
2178 // If we have an immediate that's not a constant, treat it as a label
2179 // reference needing a fixup. If it is a constant, it's something else
2180 // and we reject it.
2182 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2183 Inst.addOperand(MCOperand::CreateImm(0));
2187 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2188 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2189 Inst.addOperand(MCOperand::CreateImm(Val));
2192 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2193 assert(N == 2 && "Invalid number of operands!");
2194 // The lower two bits are always zero and as such are not encoded.
2195 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2196 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2197 Inst.addOperand(MCOperand::CreateImm(Val));
2200 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2201 assert(N == 2 && "Invalid number of operands!");
2202 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2203 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2204 Inst.addOperand(MCOperand::CreateImm(Val));
2207 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2208 addMemImm8OffsetOperands(Inst, N);
2211 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2212 addMemImm8OffsetOperands(Inst, N);
2215 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2216 assert(N == 2 && "Invalid number of operands!");
2217 // If this is an immediate, it's a label reference.
2219 addExpr(Inst, getImm());
2220 Inst.addOperand(MCOperand::CreateImm(0));
2224 // Otherwise, it's a normal memory reg+offset.
2225 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2226 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2227 Inst.addOperand(MCOperand::CreateImm(Val));
2230 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2231 assert(N == 2 && "Invalid number of operands!");
2232 // If this is an immediate, it's a label reference.
2234 addExpr(Inst, getImm());
2235 Inst.addOperand(MCOperand::CreateImm(0));
2239 // Otherwise, it's a normal memory reg+offset.
2240 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2241 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2242 Inst.addOperand(MCOperand::CreateImm(Val));
2245 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2246 assert(N == 2 && "Invalid number of operands!");
2247 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2248 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2251 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2252 assert(N == 2 && "Invalid number of operands!");
2253 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2254 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2257 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2258 assert(N == 3 && "Invalid number of operands!");
2260 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2261 Memory.ShiftImm, Memory.ShiftType);
2262 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2263 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2264 Inst.addOperand(MCOperand::CreateImm(Val));
2267 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2268 assert(N == 3 && "Invalid number of operands!");
2269 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2270 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2271 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
2274 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2275 assert(N == 2 && "Invalid number of operands!");
2276 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2277 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2280 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2281 assert(N == 2 && "Invalid number of operands!");
2282 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2283 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2284 Inst.addOperand(MCOperand::CreateImm(Val));
2287 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2288 assert(N == 2 && "Invalid number of operands!");
2289 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2290 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2291 Inst.addOperand(MCOperand::CreateImm(Val));
2294 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2295 assert(N == 2 && "Invalid number of operands!");
2296 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2297 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2298 Inst.addOperand(MCOperand::CreateImm(Val));
2301 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2302 assert(N == 2 && "Invalid number of operands!");
2303 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2304 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2305 Inst.addOperand(MCOperand::CreateImm(Val));
2308 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2309 assert(N == 1 && "Invalid number of operands!");
2310 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2311 assert(CE && "non-constant post-idx-imm8 operand!");
2312 int Imm = CE->getValue();
2313 bool isAdd = Imm >= 0;
2314 if (Imm == INT32_MIN) Imm = 0;
2315 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2316 Inst.addOperand(MCOperand::CreateImm(Imm));
2319 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2320 assert(N == 1 && "Invalid number of operands!");
2321 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2322 assert(CE && "non-constant post-idx-imm8s4 operand!");
2323 int Imm = CE->getValue();
2324 bool isAdd = Imm >= 0;
2325 if (Imm == INT32_MIN) Imm = 0;
2326 // Immediate is scaled by 4.
2327 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2328 Inst.addOperand(MCOperand::CreateImm(Imm));
2331 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2332 assert(N == 2 && "Invalid number of operands!");
2333 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2334 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2337 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2338 assert(N == 2 && "Invalid number of operands!");
2339 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2340 // The sign, shift type, and shift amount are encoded in a single operand
2341 // using the AM2 encoding helpers.
2342 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2343 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2344 PostIdxReg.ShiftTy);
2345 Inst.addOperand(MCOperand::CreateImm(Imm));
2348 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2349 assert(N == 1 && "Invalid number of operands!");
2350 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2353 void addBankedRegOperands(MCInst &Inst, unsigned N) const {
2354 assert(N == 1 && "Invalid number of operands!");
2355 Inst.addOperand(MCOperand::CreateImm(unsigned(getBankedReg())));
2358 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2359 assert(N == 1 && "Invalid number of operands!");
2360 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2363 void addVecListOperands(MCInst &Inst, unsigned N) const {
2364 assert(N == 1 && "Invalid number of operands!");
2365 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2368 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2369 assert(N == 2 && "Invalid number of operands!");
2370 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2371 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2374 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2375 assert(N == 1 && "Invalid number of operands!");
2376 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2379 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2380 assert(N == 1 && "Invalid number of operands!");
2381 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2384 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2385 assert(N == 1 && "Invalid number of operands!");
2386 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2389 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2390 assert(N == 1 && "Invalid number of operands!");
2391 // The immediate encodes the type of constant as well as the value.
2392 // Mask in that this is an i8 splat.
2393 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2394 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2397 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2398 assert(N == 1 && "Invalid number of operands!");
2399 // The immediate encodes the type of constant as well as the value.
2400 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2401 unsigned Value = CE->getValue();
2403 Value = (Value >> 8) | 0xa00;
2406 Inst.addOperand(MCOperand::CreateImm(Value));
2409 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2410 assert(N == 1 && "Invalid number of operands!");
2411 // The immediate encodes the type of constant as well as the value.
2412 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2413 unsigned Value = CE->getValue();
2414 if (Value >= 256 && Value <= 0xff00)
2415 Value = (Value >> 8) | 0x200;
2416 else if (Value > 0xffff && Value <= 0xff0000)
2417 Value = (Value >> 16) | 0x400;
2418 else if (Value > 0xffffff)
2419 Value = (Value >> 24) | 0x600;
2420 Inst.addOperand(MCOperand::CreateImm(Value));
2423 void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const {
2424 assert(N == 1 && "Invalid number of operands!");
2425 // The immediate encodes the type of constant as well as the value.
2426 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2427 unsigned Value = CE->getValue();
2428 assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2429 Inst.getOpcode() == ARM::VMOVv16i8) &&
2430 "All vmvn instructions that wants to replicate non-zero byte "
2431 "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2432 unsigned B = ((~Value) & 0xff);
2433 B |= 0xe00; // cmode = 0b1110
2434 Inst.addOperand(MCOperand::CreateImm(B));
2436 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2437 assert(N == 1 && "Invalid number of operands!");
2438 // The immediate encodes the type of constant as well as the value.
2439 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2440 unsigned Value = CE->getValue();
2441 if (Value >= 256 && Value <= 0xffff)
2442 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2443 else if (Value > 0xffff && Value <= 0xffffff)
2444 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2445 else if (Value > 0xffffff)
2446 Value = (Value >> 24) | 0x600;
2447 Inst.addOperand(MCOperand::CreateImm(Value));
2450 void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const {
2451 assert(N == 1 && "Invalid number of operands!");
2452 // The immediate encodes the type of constant as well as the value.
2453 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2454 unsigned Value = CE->getValue();
2455 assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2456 Inst.getOpcode() == ARM::VMOVv16i8) &&
2457 "All instructions that wants to replicate non-zero byte "
2458 "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2459 unsigned B = Value & 0xff;
2460 B |= 0xe00; // cmode = 0b1110
2461 Inst.addOperand(MCOperand::CreateImm(B));
2463 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2464 assert(N == 1 && "Invalid number of operands!");
2465 // The immediate encodes the type of constant as well as the value.
2466 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2467 unsigned Value = ~CE->getValue();
2468 if (Value >= 256 && Value <= 0xffff)
2469 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2470 else if (Value > 0xffff && Value <= 0xffffff)
2471 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2472 else if (Value > 0xffffff)
2473 Value = (Value >> 24) | 0x600;
2474 Inst.addOperand(MCOperand::CreateImm(Value));
2477 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2478 assert(N == 1 && "Invalid number of operands!");
2479 // The immediate encodes the type of constant as well as the value.
2480 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2481 uint64_t Value = CE->getValue();
2483 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2484 Imm |= (Value & 1) << i;
2486 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2489 void print(raw_ostream &OS) const override;
2491 static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) {
2492 auto Op = make_unique<ARMOperand>(k_ITCondMask);
2493 Op->ITMask.Mask = Mask;
2499 static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC,
2501 auto Op = make_unique<ARMOperand>(k_CondCode);
2508 static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) {
2509 auto Op = make_unique<ARMOperand>(k_CoprocNum);
2510 Op->Cop.Val = CopVal;
2516 static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) {
2517 auto Op = make_unique<ARMOperand>(k_CoprocReg);
2518 Op->Cop.Val = CopVal;
2524 static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S,
2526 auto Op = make_unique<ARMOperand>(k_CoprocOption);
2533 static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) {
2534 auto Op = make_unique<ARMOperand>(k_CCOut);
2535 Op->Reg.RegNum = RegNum;
2541 static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) {
2542 auto Op = make_unique<ARMOperand>(k_Token);
2543 Op->Tok.Data = Str.data();
2544 Op->Tok.Length = Str.size();
2550 static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,
2552 auto Op = make_unique<ARMOperand>(k_Register);
2553 Op->Reg.RegNum = RegNum;
2559 static std::unique_ptr<ARMOperand>
2560 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2561 unsigned ShiftReg, unsigned ShiftImm, SMLoc S,
2563 auto Op = make_unique<ARMOperand>(k_ShiftedRegister);
2564 Op->RegShiftedReg.ShiftTy = ShTy;
2565 Op->RegShiftedReg.SrcReg = SrcReg;
2566 Op->RegShiftedReg.ShiftReg = ShiftReg;
2567 Op->RegShiftedReg.ShiftImm = ShiftImm;
2573 static std::unique_ptr<ARMOperand>
2574 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2575 unsigned ShiftImm, SMLoc S, SMLoc E) {
2576 auto Op = make_unique<ARMOperand>(k_ShiftedImmediate);
2577 Op->RegShiftedImm.ShiftTy = ShTy;
2578 Op->RegShiftedImm.SrcReg = SrcReg;
2579 Op->RegShiftedImm.ShiftImm = ShiftImm;
2585 static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm,
2587 auto Op = make_unique<ARMOperand>(k_ShifterImmediate);
2588 Op->ShifterImm.isASR = isASR;
2589 Op->ShifterImm.Imm = Imm;
2595 static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S,
2597 auto Op = make_unique<ARMOperand>(k_RotateImmediate);
2598 Op->RotImm.Imm = Imm;
2604 static std::unique_ptr<ARMOperand>
2605 CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) {
2606 auto Op = make_unique<ARMOperand>(k_BitfieldDescriptor);
2607 Op->Bitfield.LSB = LSB;
2608 Op->Bitfield.Width = Width;
2614 static std::unique_ptr<ARMOperand>
2615 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
2616 SMLoc StartLoc, SMLoc EndLoc) {
2617 assert (Regs.size() > 0 && "RegList contains no registers?");
2618 KindTy Kind = k_RegisterList;
2620 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2621 Kind = k_DPRRegisterList;
2622 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2623 contains(Regs.front().second))
2624 Kind = k_SPRRegisterList;
2626 // Sort based on the register encoding values.
2627 array_pod_sort(Regs.begin(), Regs.end());
2629 auto Op = make_unique<ARMOperand>(Kind);
2630 for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2631 I = Regs.begin(), E = Regs.end(); I != E; ++I)
2632 Op->Registers.push_back(I->second);
2633 Op->StartLoc = StartLoc;
2634 Op->EndLoc = EndLoc;
2638 static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum,
2640 bool isDoubleSpaced,
2642 auto Op = make_unique<ARMOperand>(k_VectorList);
2643 Op->VectorList.RegNum = RegNum;
2644 Op->VectorList.Count = Count;
2645 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2651 static std::unique_ptr<ARMOperand>
2652 CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
2654 auto Op = make_unique<ARMOperand>(k_VectorListAllLanes);
2655 Op->VectorList.RegNum = RegNum;
2656 Op->VectorList.Count = Count;
2657 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2663 static std::unique_ptr<ARMOperand>
2664 CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,
2665 bool isDoubleSpaced, SMLoc S, SMLoc E) {
2666 auto Op = make_unique<ARMOperand>(k_VectorListIndexed);
2667 Op->VectorList.RegNum = RegNum;
2668 Op->VectorList.Count = Count;
2669 Op->VectorList.LaneIndex = Index;
2670 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2676 static std::unique_ptr<ARMOperand>
2677 CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) {
2678 auto Op = make_unique<ARMOperand>(k_VectorIndex);
2679 Op->VectorIndex.Val = Idx;
2685 static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S,
2687 auto Op = make_unique<ARMOperand>(k_Immediate);
2694 static std::unique_ptr<ARMOperand>
2695 CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm,
2696 unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType,
2697 unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S,
2698 SMLoc E, SMLoc AlignmentLoc = SMLoc()) {
2699 auto Op = make_unique<ARMOperand>(k_Memory);
2700 Op->Memory.BaseRegNum = BaseRegNum;
2701 Op->Memory.OffsetImm = OffsetImm;
2702 Op->Memory.OffsetRegNum = OffsetRegNum;
2703 Op->Memory.ShiftType = ShiftType;
2704 Op->Memory.ShiftImm = ShiftImm;
2705 Op->Memory.Alignment = Alignment;
2706 Op->Memory.isNegative = isNegative;
2709 Op->AlignmentLoc = AlignmentLoc;
2713 static std::unique_ptr<ARMOperand>
2714 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
2715 unsigned ShiftImm, SMLoc S, SMLoc E) {
2716 auto Op = make_unique<ARMOperand>(k_PostIndexRegister);
2717 Op->PostIdxReg.RegNum = RegNum;
2718 Op->PostIdxReg.isAdd = isAdd;
2719 Op->PostIdxReg.ShiftTy = ShiftTy;
2720 Op->PostIdxReg.ShiftImm = ShiftImm;
2726 static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt,
2728 auto Op = make_unique<ARMOperand>(k_MemBarrierOpt);
2729 Op->MBOpt.Val = Opt;
2735 static std::unique_ptr<ARMOperand>
2736 CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) {
2737 auto Op = make_unique<ARMOperand>(k_InstSyncBarrierOpt);
2738 Op->ISBOpt.Val = Opt;
2744 static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags,
2746 auto Op = make_unique<ARMOperand>(k_ProcIFlags);
2747 Op->IFlags.Val = IFlags;
2753 static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) {
2754 auto Op = make_unique<ARMOperand>(k_MSRMask);
2755 Op->MMask.Val = MMask;
2761 static std::unique_ptr<ARMOperand> CreateBankedReg(unsigned Reg, SMLoc S) {
2762 auto Op = make_unique<ARMOperand>(k_BankedReg);
2763 Op->BankedReg.Val = Reg;
2770 } // end anonymous namespace.
2772 void ARMOperand::print(raw_ostream &OS) const {
2775 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2778 OS << "<ccout " << getReg() << ">";
2780 case k_ITCondMask: {
2781 static const char *const MaskStr[] = {
2782 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2783 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2785 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2786 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2790 OS << "<coprocessor number: " << getCoproc() << ">";
2793 OS << "<coprocessor register: " << getCoproc() << ">";
2795 case k_CoprocOption:
2796 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2799 OS << "<mask: " << getMSRMask() << ">";
2802 OS << "<banked reg: " << getBankedReg() << ">";
2805 getImm()->print(OS);
2807 case k_MemBarrierOpt:
2808 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
2810 case k_InstSyncBarrierOpt:
2811 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2815 << " base:" << Memory.BaseRegNum;
2818 case k_PostIndexRegister:
2819 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2820 << PostIdxReg.RegNum;
2821 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2822 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2823 << PostIdxReg.ShiftImm;
2826 case k_ProcIFlags: {
2827 OS << "<ARM_PROC::";
2828 unsigned IFlags = getProcIFlags();
2829 for (int i=2; i >= 0; --i)
2830 if (IFlags & (1 << i))
2831 OS << ARM_PROC::IFlagsToString(1 << i);
2836 OS << "<register " << getReg() << ">";
2838 case k_ShifterImmediate:
2839 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2840 << " #" << ShifterImm.Imm << ">";
2842 case k_ShiftedRegister:
2843 OS << "<so_reg_reg "
2844 << RegShiftedReg.SrcReg << " "
2845 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2846 << " " << RegShiftedReg.ShiftReg << ">";
2848 case k_ShiftedImmediate:
2849 OS << "<so_reg_imm "
2850 << RegShiftedImm.SrcReg << " "
2851 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2852 << " #" << RegShiftedImm.ShiftImm << ">";
2854 case k_RotateImmediate:
2855 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2857 case k_BitfieldDescriptor:
2858 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2859 << ", width: " << Bitfield.Width << ">";
2861 case k_RegisterList:
2862 case k_DPRRegisterList:
2863 case k_SPRRegisterList: {
2864 OS << "<register_list ";
2866 const SmallVectorImpl<unsigned> &RegList = getRegList();
2867 for (SmallVectorImpl<unsigned>::const_iterator
2868 I = RegList.begin(), E = RegList.end(); I != E; ) {
2870 if (++I < E) OS << ", ";
2877 OS << "<vector_list " << VectorList.Count << " * "
2878 << VectorList.RegNum << ">";
2880 case k_VectorListAllLanes:
2881 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2882 << VectorList.RegNum << ">";
2884 case k_VectorListIndexed:
2885 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2886 << VectorList.Count << " * " << VectorList.RegNum << ">";
2889 OS << "'" << getToken() << "'";
2892 OS << "<vectorindex " << getVectorIndex() << ">";
2897 /// @name Auto-generated Match Functions
2900 static unsigned MatchRegisterName(StringRef Name);
2904 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2905 SMLoc &StartLoc, SMLoc &EndLoc) {
2906 StartLoc = Parser.getTok().getLoc();
2907 EndLoc = Parser.getTok().getEndLoc();
2908 RegNo = tryParseRegister();
2910 return (RegNo == (unsigned)-1);
2913 /// Try to parse a register name. The token must be an Identifier when called,
2914 /// and if it is a register name the token is eaten and the register number is
2915 /// returned. Otherwise return -1.
2917 int ARMAsmParser::tryParseRegister() {
2918 const AsmToken &Tok = Parser.getTok();
2919 if (Tok.isNot(AsmToken::Identifier)) return -1;
2921 std::string lowerCase = Tok.getString().lower();
2922 unsigned RegNum = MatchRegisterName(lowerCase);
2924 RegNum = StringSwitch<unsigned>(lowerCase)
2925 .Case("r13", ARM::SP)
2926 .Case("r14", ARM::LR)
2927 .Case("r15", ARM::PC)
2928 .Case("ip", ARM::R12)
2929 // Additional register name aliases for 'gas' compatibility.
2930 .Case("a1", ARM::R0)
2931 .Case("a2", ARM::R1)
2932 .Case("a3", ARM::R2)
2933 .Case("a4", ARM::R3)
2934 .Case("v1", ARM::R4)
2935 .Case("v2", ARM::R5)
2936 .Case("v3", ARM::R6)
2937 .Case("v4", ARM::R7)
2938 .Case("v5", ARM::R8)
2939 .Case("v6", ARM::R9)
2940 .Case("v7", ARM::R10)
2941 .Case("v8", ARM::R11)
2942 .Case("sb", ARM::R9)
2943 .Case("sl", ARM::R10)
2944 .Case("fp", ARM::R11)
2948 // Check for aliases registered via .req. Canonicalize to lower case.
2949 // That's more consistent since register names are case insensitive, and
2950 // it's how the original entry was passed in from MC/MCParser/AsmParser.
2951 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2952 // If no match, return failure.
2953 if (Entry == RegisterReqs.end())
2955 Parser.Lex(); // Eat identifier token.
2956 return Entry->getValue();
2959 Parser.Lex(); // Eat identifier token.
2964 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
2965 // If a recoverable error occurs, return 1. If an irrecoverable error
2966 // occurs, return -1. An irrecoverable error is one where tokens have been
2967 // consumed in the process of trying to parse the shifter (i.e., when it is
2968 // indeed a shifter operand, but malformed).
2969 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
2970 SMLoc S = Parser.getTok().getLoc();
2971 const AsmToken &Tok = Parser.getTok();
2972 if (Tok.isNot(AsmToken::Identifier))
2975 std::string lowerCase = Tok.getString().lower();
2976 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2977 .Case("asl", ARM_AM::lsl)
2978 .Case("lsl", ARM_AM::lsl)
2979 .Case("lsr", ARM_AM::lsr)
2980 .Case("asr", ARM_AM::asr)
2981 .Case("ror", ARM_AM::ror)
2982 .Case("rrx", ARM_AM::rrx)
2983 .Default(ARM_AM::no_shift);
2985 if (ShiftTy == ARM_AM::no_shift)
2988 Parser.Lex(); // Eat the operator.
2990 // The source register for the shift has already been added to the
2991 // operand list, so we need to pop it off and combine it into the shifted
2992 // register operand instead.
2993 std::unique_ptr<ARMOperand> PrevOp(
2994 (ARMOperand *)Operands.pop_back_val().release());
2995 if (!PrevOp->isReg())
2996 return Error(PrevOp->getStartLoc(), "shift must be of a register");
2997 int SrcReg = PrevOp->getReg();
3002 if (ShiftTy == ARM_AM::rrx) {
3003 // RRX Doesn't have an explicit shift amount. The encoder expects
3004 // the shift register to be the same as the source register. Seems odd,
3008 // Figure out if this is shifted by a constant or a register (for non-RRX).
3009 if (Parser.getTok().is(AsmToken::Hash) ||
3010 Parser.getTok().is(AsmToken::Dollar)) {
3011 Parser.Lex(); // Eat hash.
3012 SMLoc ImmLoc = Parser.getTok().getLoc();
3013 const MCExpr *ShiftExpr = nullptr;
3014 if (getParser().parseExpression(ShiftExpr, EndLoc)) {
3015 Error(ImmLoc, "invalid immediate shift value");
3018 // The expression must be evaluatable as an immediate.
3019 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
3021 Error(ImmLoc, "invalid immediate shift value");
3024 // Range check the immediate.
3025 // lsl, ror: 0 <= imm <= 31
3026 // lsr, asr: 0 <= imm <= 32
3027 Imm = CE->getValue();
3029 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
3030 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
3031 Error(ImmLoc, "immediate shift value out of range");
3034 // shift by zero is a nop. Always send it through as lsl.
3035 // ('as' compatibility)
3037 ShiftTy = ARM_AM::lsl;
3038 } else if (Parser.getTok().is(AsmToken::Identifier)) {
3039 SMLoc L = Parser.getTok().getLoc();
3040 EndLoc = Parser.getTok().getEndLoc();
3041 ShiftReg = tryParseRegister();
3042 if (ShiftReg == -1) {
3043 Error(L, "expected immediate or register in shift operand");
3047 Error(Parser.getTok().getLoc(),
3048 "expected immediate or register in shift operand");
3053 if (ShiftReg && ShiftTy != ARM_AM::rrx)
3054 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
3058 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
3065 /// Try to parse a register name. The token must be an Identifier when called.
3066 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
3067 /// if there is a "writeback". 'true' if it's not a register.
3069 /// TODO this is likely to change to allow different register types and or to
3070 /// parse for a specific register type.
3071 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) {
3072 const AsmToken &RegTok = Parser.getTok();
3073 int RegNo = tryParseRegister();
3077 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
3078 RegTok.getEndLoc()));
3080 const AsmToken &ExclaimTok = Parser.getTok();
3081 if (ExclaimTok.is(AsmToken::Exclaim)) {
3082 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
3083 ExclaimTok.getLoc()));
3084 Parser.Lex(); // Eat exclaim token
3088 // Also check for an index operand. This is only legal for vector registers,
3089 // but that'll get caught OK in operand matching, so we don't need to
3090 // explicitly filter everything else out here.
3091 if (Parser.getTok().is(AsmToken::LBrac)) {
3092 SMLoc SIdx = Parser.getTok().getLoc();
3093 Parser.Lex(); // Eat left bracket token.
3095 const MCExpr *ImmVal;
3096 if (getParser().parseExpression(ImmVal))
3098 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
3100 return TokError("immediate value expected for vector index");
3102 if (Parser.getTok().isNot(AsmToken::RBrac))
3103 return Error(Parser.getTok().getLoc(), "']' expected");
3105 SMLoc E = Parser.getTok().getEndLoc();
3106 Parser.Lex(); // Eat right bracket token.
3108 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
3116 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
3117 /// instruction with a symbolic operand name.
3118 /// We accept "crN" syntax for GAS compatibility.
3119 /// <operand-name> ::= <prefix><number>
3120 /// If CoprocOp is 'c', then:
3121 /// <prefix> ::= c | cr
3122 /// If CoprocOp is 'p', then :
3124 /// <number> ::= integer in range [0, 15]
3125 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
3126 // Use the same layout as the tablegen'erated register name matcher. Ugly,
3128 if (Name.size() < 2 || Name[0] != CoprocOp)
3130 Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front();
3132 switch (Name.size()) {
3153 // CP10 and CP11 are VFP/NEON and so vector instructions should be used.
3154 // However, old cores (v5/v6) did use them in that way.
3155 case '0': return 10;
3156 case '1': return 11;
3157 case '2': return 12;
3158 case '3': return 13;
3159 case '4': return 14;
3160 case '5': return 15;
3165 /// parseITCondCode - Try to parse a condition code for an IT instruction.
3166 ARMAsmParser::OperandMatchResultTy
3167 ARMAsmParser::parseITCondCode(OperandVector &Operands) {
3168 SMLoc S = Parser.getTok().getLoc();
3169 const AsmToken &Tok = Parser.getTok();
3170 if (!Tok.is(AsmToken::Identifier))
3171 return MatchOperand_NoMatch;
3172 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
3173 .Case("eq", ARMCC::EQ)
3174 .Case("ne", ARMCC::NE)
3175 .Case("hs", ARMCC::HS)
3176 .Case("cs", ARMCC::HS)
3177 .Case("lo", ARMCC::LO)
3178 .Case("cc", ARMCC::LO)
3179 .Case("mi", ARMCC::MI)
3180 .Case("pl", ARMCC::PL)
3181 .Case("vs", ARMCC::VS)
3182 .Case("vc", ARMCC::VC)
3183 .Case("hi", ARMCC::HI)
3184 .Case("ls", ARMCC::LS)
3185 .Case("ge", ARMCC::GE)
3186 .Case("lt", ARMCC::LT)
3187 .Case("gt", ARMCC::GT)
3188 .Case("le", ARMCC::LE)
3189 .Case("al", ARMCC::AL)
3192 return MatchOperand_NoMatch;
3193 Parser.Lex(); // Eat the token.
3195 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
3197 return MatchOperand_Success;
3200 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
3201 /// token must be an Identifier when called, and if it is a coprocessor
3202 /// number, the token is eaten and the operand is added to the operand list.
3203 ARMAsmParser::OperandMatchResultTy
3204 ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
3205 SMLoc S = Parser.getTok().getLoc();
3206 const AsmToken &Tok = Parser.getTok();
3207 if (Tok.isNot(AsmToken::Identifier))
3208 return MatchOperand_NoMatch;
3210 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
3212 return MatchOperand_NoMatch;
3213 // ARMv7 and v8 don't allow cp10/cp11 due to VFP/NEON specific instructions
3214 if ((hasV7Ops() || hasV8Ops()) && (Num == 10 || Num == 11))
3215 return MatchOperand_NoMatch;
3217 Parser.Lex(); // Eat identifier token.
3218 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
3219 return MatchOperand_Success;
3222 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
3223 /// token must be an Identifier when called, and if it is a coprocessor
3224 /// number, the token is eaten and the operand is added to the operand list.
3225 ARMAsmParser::OperandMatchResultTy
3226 ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
3227 SMLoc S = Parser.getTok().getLoc();
3228 const AsmToken &Tok = Parser.getTok();
3229 if (Tok.isNot(AsmToken::Identifier))
3230 return MatchOperand_NoMatch;
3232 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
3234 return MatchOperand_NoMatch;
3236 Parser.Lex(); // Eat identifier token.
3237 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
3238 return MatchOperand_Success;
3241 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
3242 /// coproc_option : '{' imm0_255 '}'
3243 ARMAsmParser::OperandMatchResultTy
3244 ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
3245 SMLoc S = Parser.getTok().getLoc();
3247 // If this isn't a '{', this isn't a coprocessor immediate operand.
3248 if (Parser.getTok().isNot(AsmToken::LCurly))
3249 return MatchOperand_NoMatch;
3250 Parser.Lex(); // Eat the '{'
3253 SMLoc Loc = Parser.getTok().getLoc();
3254 if (getParser().parseExpression(Expr)) {
3255 Error(Loc, "illegal expression");
3256 return MatchOperand_ParseFail;
3258 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3259 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
3260 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
3261 return MatchOperand_ParseFail;
3263 int Val = CE->getValue();
3265 // Check for and consume the closing '}'
3266 if (Parser.getTok().isNot(AsmToken::RCurly))
3267 return MatchOperand_ParseFail;
3268 SMLoc E = Parser.getTok().getEndLoc();
3269 Parser.Lex(); // Eat the '}'
3271 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
3272 return MatchOperand_Success;
3275 // For register list parsing, we need to map from raw GPR register numbering
3276 // to the enumeration values. The enumeration values aren't sorted by
3277 // register number due to our using "sp", "lr" and "pc" as canonical names.
3278 static unsigned getNextRegister(unsigned Reg) {
3279 // If this is a GPR, we need to do it manually, otherwise we can rely
3280 // on the sort ordering of the enumeration since the other reg-classes
3282 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3285 default: llvm_unreachable("Invalid GPR number!");
3286 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
3287 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
3288 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
3289 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
3290 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
3291 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3292 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
3293 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
3297 // Return the low-subreg of a given Q register.
3298 static unsigned getDRegFromQReg(unsigned QReg) {
3300 default: llvm_unreachable("expected a Q register!");
3301 case ARM::Q0: return ARM::D0;
3302 case ARM::Q1: return ARM::D2;
3303 case ARM::Q2: return ARM::D4;
3304 case ARM::Q3: return ARM::D6;
3305 case ARM::Q4: return ARM::D8;
3306 case ARM::Q5: return ARM::D10;
3307 case ARM::Q6: return ARM::D12;
3308 case ARM::Q7: return ARM::D14;
3309 case ARM::Q8: return ARM::D16;
3310 case ARM::Q9: return ARM::D18;
3311 case ARM::Q10: return ARM::D20;
3312 case ARM::Q11: return ARM::D22;
3313 case ARM::Q12: return ARM::D24;
3314 case ARM::Q13: return ARM::D26;
3315 case ARM::Q14: return ARM::D28;
3316 case ARM::Q15: return ARM::D30;
3320 /// Parse a register list.
3321 bool ARMAsmParser::parseRegisterList(OperandVector &Operands) {
3322 assert(Parser.getTok().is(AsmToken::LCurly) &&
3323 "Token is not a Left Curly Brace");
3324 SMLoc S = Parser.getTok().getLoc();
3325 Parser.Lex(); // Eat '{' token.
3326 SMLoc RegLoc = Parser.getTok().getLoc();
3328 // Check the first register in the list to see what register class
3329 // this is a list of.
3330 int Reg = tryParseRegister();
3332 return Error(RegLoc, "register expected");
3334 // The reglist instructions have at most 16 registers, so reserve
3335 // space for that many.
3337 SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3339 // Allow Q regs and just interpret them as the two D sub-registers.
3340 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3341 Reg = getDRegFromQReg(Reg);
3342 EReg = MRI->getEncodingValue(Reg);
3343 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3346 const MCRegisterClass *RC;
3347 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3348 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3349 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3350 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3351 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3352 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3354 return Error(RegLoc, "invalid register in register list");
3356 // Store the register.
3357 EReg = MRI->getEncodingValue(Reg);
3358 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3360 // This starts immediately after the first register token in the list,
3361 // so we can see either a comma or a minus (range separator) as a legal
3363 while (Parser.getTok().is(AsmToken::Comma) ||
3364 Parser.getTok().is(AsmToken::Minus)) {
3365 if (Parser.getTok().is(AsmToken::Minus)) {
3366 Parser.Lex(); // Eat the minus.
3367 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3368 int EndReg = tryParseRegister();
3370 return Error(AfterMinusLoc, "register expected");
3371 // Allow Q regs and just interpret them as the two D sub-registers.
3372 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3373 EndReg = getDRegFromQReg(EndReg) + 1;
3374 // If the register is the same as the start reg, there's nothing
3378 // The register must be in the same register class as the first.
3379 if (!RC->contains(EndReg))
3380 return Error(AfterMinusLoc, "invalid register in register list");
3381 // Ranges must go from low to high.
3382 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3383 return Error(AfterMinusLoc, "bad range in register list");
3385 // Add all the registers in the range to the register list.
3386 while (Reg != EndReg) {
3387 Reg = getNextRegister(Reg);
3388 EReg = MRI->getEncodingValue(Reg);
3389 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3393 Parser.Lex(); // Eat the comma.
3394 RegLoc = Parser.getTok().getLoc();
3396 const AsmToken RegTok = Parser.getTok();
3397 Reg = tryParseRegister();
3399 return Error(RegLoc, "register expected");
3400 // Allow Q regs and just interpret them as the two D sub-registers.
3401 bool isQReg = false;
3402 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3403 Reg = getDRegFromQReg(Reg);
3406 // The register must be in the same register class as the first.
3407 if (!RC->contains(Reg))
3408 return Error(RegLoc, "invalid register in register list");
3409 // List must be monotonically increasing.
3410 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3411 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3412 Warning(RegLoc, "register list not in ascending order");
3414 return Error(RegLoc, "register list not in ascending order");
3416 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3417 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3418 ") in register list");
3421 // VFP register lists must also be contiguous.
3422 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3424 return Error(RegLoc, "non-contiguous register range");
3425 EReg = MRI->getEncodingValue(Reg);
3426 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3428 EReg = MRI->getEncodingValue(++Reg);
3429 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3433 if (Parser.getTok().isNot(AsmToken::RCurly))
3434 return Error(Parser.getTok().getLoc(), "'}' expected");
3435 SMLoc E = Parser.getTok().getEndLoc();
3436 Parser.Lex(); // Eat '}' token.
3438 // Push the register list operand.
3439 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3441 // The ARM system instruction variants for LDM/STM have a '^' token here.
3442 if (Parser.getTok().is(AsmToken::Caret)) {
3443 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3444 Parser.Lex(); // Eat '^' token.
3450 // Helper function to parse the lane index for vector lists.
3451 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3452 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3453 Index = 0; // Always return a defined index value.
3454 if (Parser.getTok().is(AsmToken::LBrac)) {
3455 Parser.Lex(); // Eat the '['.
3456 if (Parser.getTok().is(AsmToken::RBrac)) {
3457 // "Dn[]" is the 'all lanes' syntax.
3458 LaneKind = AllLanes;
3459 EndLoc = Parser.getTok().getEndLoc();
3460 Parser.Lex(); // Eat the ']'.
3461 return MatchOperand_Success;
3464 // There's an optional '#' token here. Normally there wouldn't be, but
3465 // inline assemble puts one in, and it's friendly to accept that.
3466 if (Parser.getTok().is(AsmToken::Hash))
3467 Parser.Lex(); // Eat '#' or '$'.
3469 const MCExpr *LaneIndex;
3470 SMLoc Loc = Parser.getTok().getLoc();
3471 if (getParser().parseExpression(LaneIndex)) {
3472 Error(Loc, "illegal expression");
3473 return MatchOperand_ParseFail;
3475 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3477 Error(Loc, "lane index must be empty or an integer");
3478 return MatchOperand_ParseFail;
3480 if (Parser.getTok().isNot(AsmToken::RBrac)) {
3481 Error(Parser.getTok().getLoc(), "']' expected");
3482 return MatchOperand_ParseFail;
3484 EndLoc = Parser.getTok().getEndLoc();
3485 Parser.Lex(); // Eat the ']'.
3486 int64_t Val = CE->getValue();
3488 // FIXME: Make this range check context sensitive for .8, .16, .32.
3489 if (Val < 0 || Val > 7) {
3490 Error(Parser.getTok().getLoc(), "lane index out of range");
3491 return MatchOperand_ParseFail;
3494 LaneKind = IndexedLane;
3495 return MatchOperand_Success;
3498 return MatchOperand_Success;
3501 // parse a vector register list
3502 ARMAsmParser::OperandMatchResultTy
3503 ARMAsmParser::parseVectorList(OperandVector &Operands) {
3504 VectorLaneTy LaneKind;
3506 SMLoc S = Parser.getTok().getLoc();
3507 // As an extension (to match gas), support a plain D register or Q register
3508 // (without encosing curly braces) as a single or double entry list,
3510 if (Parser.getTok().is(AsmToken::Identifier)) {
3511 SMLoc E = Parser.getTok().getEndLoc();
3512 int Reg = tryParseRegister();
3514 return MatchOperand_NoMatch;
3515 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3516 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3517 if (Res != MatchOperand_Success)
3521 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3524 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3528 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3533 return MatchOperand_Success;
3535 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3536 Reg = getDRegFromQReg(Reg);
3537 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3538 if (Res != MatchOperand_Success)
3542 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3543 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3544 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3547 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3548 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3549 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3553 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3558 return MatchOperand_Success;
3560 Error(S, "vector register expected");
3561 return MatchOperand_ParseFail;
3564 if (Parser.getTok().isNot(AsmToken::LCurly))
3565 return MatchOperand_NoMatch;
3567 Parser.Lex(); // Eat '{' token.
3568 SMLoc RegLoc = Parser.getTok().getLoc();
3570 int Reg = tryParseRegister();
3572 Error(RegLoc, "register expected");
3573 return MatchOperand_ParseFail;
3577 unsigned FirstReg = Reg;
3578 // The list is of D registers, but we also allow Q regs and just interpret
3579 // them as the two D sub-registers.
3580 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3581 FirstReg = Reg = getDRegFromQReg(Reg);
3582 Spacing = 1; // double-spacing requires explicit D registers, otherwise
3583 // it's ambiguous with four-register single spaced.
3589 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3590 return MatchOperand_ParseFail;
3592 while (Parser.getTok().is(AsmToken::Comma) ||
3593 Parser.getTok().is(AsmToken::Minus)) {
3594 if (Parser.getTok().is(AsmToken::Minus)) {
3596 Spacing = 1; // Register range implies a single spaced list.
3597 else if (Spacing == 2) {
3598 Error(Parser.getTok().getLoc(),
3599 "sequential registers in double spaced list");
3600 return MatchOperand_ParseFail;
3602 Parser.Lex(); // Eat the minus.
3603 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3604 int EndReg = tryParseRegister();
3606 Error(AfterMinusLoc, "register expected");
3607 return MatchOperand_ParseFail;
3609 // Allow Q regs and just interpret them as the two D sub-registers.
3610 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3611 EndReg = getDRegFromQReg(EndReg) + 1;
3612 // If the register is the same as the start reg, there's nothing
3616 // The register must be in the same register class as the first.
3617 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3618 Error(AfterMinusLoc, "invalid register in register list");
3619 return MatchOperand_ParseFail;
3621 // Ranges must go from low to high.
3623 Error(AfterMinusLoc, "bad range in register list");
3624 return MatchOperand_ParseFail;
3626 // Parse the lane specifier if present.
3627 VectorLaneTy NextLaneKind;
3628 unsigned NextLaneIndex;
3629 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3630 MatchOperand_Success)
3631 return MatchOperand_ParseFail;
3632 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3633 Error(AfterMinusLoc, "mismatched lane index in register list");
3634 return MatchOperand_ParseFail;
3637 // Add all the registers in the range to the register list.
3638 Count += EndReg - Reg;
3642 Parser.Lex(); // Eat the comma.
3643 RegLoc = Parser.getTok().getLoc();
3645 Reg = tryParseRegister();
3647 Error(RegLoc, "register expected");
3648 return MatchOperand_ParseFail;
3650 // vector register lists must be contiguous.
3651 // It's OK to use the enumeration values directly here rather, as the
3652 // VFP register classes have the enum sorted properly.
3654 // The list is of D registers, but we also allow Q regs and just interpret
3655 // them as the two D sub-registers.
3656 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3658 Spacing = 1; // Register range implies a single spaced list.
3659 else if (Spacing == 2) {
3661 "invalid register in double-spaced list (must be 'D' register')");
3662 return MatchOperand_ParseFail;
3664 Reg = getDRegFromQReg(Reg);
3665 if (Reg != OldReg + 1) {
3666 Error(RegLoc, "non-contiguous register range");
3667 return MatchOperand_ParseFail;
3671 // Parse the lane specifier if present.
3672 VectorLaneTy NextLaneKind;
3673 unsigned NextLaneIndex;
3674 SMLoc LaneLoc = Parser.getTok().getLoc();
3675 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3676 MatchOperand_Success)
3677 return MatchOperand_ParseFail;
3678 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3679 Error(LaneLoc, "mismatched lane index in register list");
3680 return MatchOperand_ParseFail;
3684 // Normal D register.
3685 // Figure out the register spacing (single or double) of the list if
3686 // we don't know it already.
3688 Spacing = 1 + (Reg == OldReg + 2);
3690 // Just check that it's contiguous and keep going.
3691 if (Reg != OldReg + Spacing) {
3692 Error(RegLoc, "non-contiguous register range");
3693 return MatchOperand_ParseFail;
3696 // Parse the lane specifier if present.
3697 VectorLaneTy NextLaneKind;
3698 unsigned NextLaneIndex;
3699 SMLoc EndLoc = Parser.getTok().getLoc();
3700 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3701 return MatchOperand_ParseFail;
3702 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3703 Error(EndLoc, "mismatched lane index in register list");
3704 return MatchOperand_ParseFail;
3708 if (Parser.getTok().isNot(AsmToken::RCurly)) {
3709 Error(Parser.getTok().getLoc(), "'}' expected");
3710 return MatchOperand_ParseFail;
3712 E = Parser.getTok().getEndLoc();
3713 Parser.Lex(); // Eat '}' token.
3717 // Two-register operands have been converted to the
3718 // composite register classes.
3720 const MCRegisterClass *RC = (Spacing == 1) ?
3721 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3722 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3723 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3726 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3727 (Spacing == 2), S, E));
3730 // Two-register operands have been converted to the
3731 // composite register classes.
3733 const MCRegisterClass *RC = (Spacing == 1) ?
3734 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3735 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3736 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3738 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3743 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3749 return MatchOperand_Success;
3752 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3753 ARMAsmParser::OperandMatchResultTy
3754 ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
3755 SMLoc S = Parser.getTok().getLoc();
3756 const AsmToken &Tok = Parser.getTok();
3759 if (Tok.is(AsmToken::Identifier)) {
3760 StringRef OptStr = Tok.getString();
3762 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3763 .Case("sy", ARM_MB::SY)
3764 .Case("st", ARM_MB::ST)
3765 .Case("ld", ARM_MB::LD)
3766 .Case("sh", ARM_MB::ISH)
3767 .Case("ish", ARM_MB::ISH)
3768 .Case("shst", ARM_MB::ISHST)
3769 .Case("ishst", ARM_MB::ISHST)
3770 .Case("ishld", ARM_MB::ISHLD)
3771 .Case("nsh", ARM_MB::NSH)
3772 .Case("un", ARM_MB::NSH)
3773 .Case("nshst", ARM_MB::NSHST)
3774 .Case("nshld", ARM_MB::NSHLD)
3775 .Case("unst", ARM_MB::NSHST)
3776 .Case("osh", ARM_MB::OSH)
3777 .Case("oshst", ARM_MB::OSHST)
3778 .Case("oshld", ARM_MB::OSHLD)
3781 // ishld, oshld, nshld and ld are only available from ARMv8.
3782 if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
3783 Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
3787 return MatchOperand_NoMatch;
3789 Parser.Lex(); // Eat identifier token.
3790 } else if (Tok.is(AsmToken::Hash) ||
3791 Tok.is(AsmToken::Dollar) ||
3792 Tok.is(AsmToken::Integer)) {
3793 if (Parser.getTok().isNot(AsmToken::Integer))
3794 Parser.Lex(); // Eat '#' or '$'.
3795 SMLoc Loc = Parser.getTok().getLoc();
3797 const MCExpr *MemBarrierID;
3798 if (getParser().parseExpression(MemBarrierID)) {
3799 Error(Loc, "illegal expression");
3800 return MatchOperand_ParseFail;
3803 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3805 Error(Loc, "constant expression expected");
3806 return MatchOperand_ParseFail;
3809 int Val = CE->getValue();
3811 Error(Loc, "immediate value out of range");
3812 return MatchOperand_ParseFail;
3815 Opt = ARM_MB::RESERVED_0 + Val;
3817 return MatchOperand_ParseFail;
3819 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3820 return MatchOperand_Success;
3823 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3824 ARMAsmParser::OperandMatchResultTy
3825 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
3826 SMLoc S = Parser.getTok().getLoc();
3827 const AsmToken &Tok = Parser.getTok();
3830 if (Tok.is(AsmToken::Identifier)) {
3831 StringRef OptStr = Tok.getString();
3833 if (OptStr.equals_lower("sy"))
3836 return MatchOperand_NoMatch;
3838 Parser.Lex(); // Eat identifier token.
3839 } else if (Tok.is(AsmToken::Hash) ||
3840 Tok.is(AsmToken::Dollar) ||
3841 Tok.is(AsmToken::Integer)) {
3842 if (Parser.getTok().isNot(AsmToken::Integer))
3843 Parser.Lex(); // Eat '#' or '$'.
3844 SMLoc Loc = Parser.getTok().getLoc();
3846 const MCExpr *ISBarrierID;
3847 if (getParser().parseExpression(ISBarrierID)) {
3848 Error(Loc, "illegal expression");
3849 return MatchOperand_ParseFail;
3852 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3854 Error(Loc, "constant expression expected");
3855 return MatchOperand_ParseFail;
3858 int Val = CE->getValue();
3860 Error(Loc, "immediate value out of range");
3861 return MatchOperand_ParseFail;
3864 Opt = ARM_ISB::RESERVED_0 + Val;
3866 return MatchOperand_ParseFail;
3868 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3869 (ARM_ISB::InstSyncBOpt)Opt, S));
3870 return MatchOperand_Success;
3874 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3875 ARMAsmParser::OperandMatchResultTy
3876 ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
3877 SMLoc S = Parser.getTok().getLoc();
3878 const AsmToken &Tok = Parser.getTok();
3879 if (!Tok.is(AsmToken::Identifier))
3880 return MatchOperand_NoMatch;
3881 StringRef IFlagsStr = Tok.getString();
3883 // An iflags string of "none" is interpreted to mean that none of the AIF
3884 // bits are set. Not a terribly useful instruction, but a valid encoding.
3885 unsigned IFlags = 0;
3886 if (IFlagsStr != "none") {
3887 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3888 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3889 .Case("a", ARM_PROC::A)
3890 .Case("i", ARM_PROC::I)
3891 .Case("f", ARM_PROC::F)
3894 // If some specific iflag is already set, it means that some letter is
3895 // present more than once, this is not acceptable.
3896 if (Flag == ~0U || (IFlags & Flag))
3897 return MatchOperand_NoMatch;
3903 Parser.Lex(); // Eat identifier token.
3904 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3905 return MatchOperand_Success;
3908 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3909 ARMAsmParser::OperandMatchResultTy
3910 ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
3911 SMLoc S = Parser.getTok().getLoc();
3912 const AsmToken &Tok = Parser.getTok();
3913 if (!Tok.is(AsmToken::Identifier))
3914 return MatchOperand_NoMatch;
3915 StringRef Mask = Tok.getString();
3918 // See ARMv6-M 10.1.1
3919 std::string Name = Mask.lower();
3920 unsigned FlagsVal = StringSwitch<unsigned>(Name)
3921 // Note: in the documentation:
3922 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3923 // for MSR APSR_nzcvq.
3924 // but we do make it an alias here. This is so to get the "mask encoding"
3925 // bits correct on MSR APSR writes.
3927 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3928 // should really only be allowed when writing a special register. Note
3929 // they get dropped in the MRS instruction reading a special register as
3930 // the SYSm field is only 8 bits.
3932 // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3933 // includes the DSP extension but that is not checked.
3934 .Case("apsr", 0x800)
3935 .Case("apsr_nzcvq", 0x800)
3936 .Case("apsr_g", 0x400)
3937 .Case("apsr_nzcvqg", 0xc00)
3938 .Case("iapsr", 0x801)
3939 .Case("iapsr_nzcvq", 0x801)
3940 .Case("iapsr_g", 0x401)
3941 .Case("iapsr_nzcvqg", 0xc01)
3942 .Case("eapsr", 0x802)
3943 .Case("eapsr_nzcvq", 0x802)
3944 .Case("eapsr_g", 0x402)
3945 .Case("eapsr_nzcvqg", 0xc02)
3946 .Case("xpsr", 0x803)
3947 .Case("xpsr_nzcvq", 0x803)
3948 .Case("xpsr_g", 0x403)
3949 .Case("xpsr_nzcvqg", 0xc03)
3950 .Case("ipsr", 0x805)
3951 .Case("epsr", 0x806)
3952 .Case("iepsr", 0x807)
3955 .Case("primask", 0x810)
3956 .Case("basepri", 0x811)
3957 .Case("basepri_max", 0x812)
3958 .Case("faultmask", 0x813)
3959 .Case("control", 0x814)
3962 if (FlagsVal == ~0U)
3963 return MatchOperand_NoMatch;
3965 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3966 // basepri, basepri_max and faultmask only valid for V7m.
3967 return MatchOperand_NoMatch;
3969 Parser.Lex(); // Eat identifier token.
3970 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3971 return MatchOperand_Success;
3974 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3975 size_t Start = 0, Next = Mask.find('_');
3976 StringRef Flags = "";
3977 std::string SpecReg = Mask.slice(Start, Next).lower();
3978 if (Next != StringRef::npos)
3979 Flags = Mask.slice(Next+1, Mask.size());
3981 // FlagsVal contains the complete mask:
3983 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3984 unsigned FlagsVal = 0;
3986 if (SpecReg == "apsr") {
3987 FlagsVal = StringSwitch<unsigned>(Flags)
3988 .Case("nzcvq", 0x8) // same as CPSR_f
3989 .Case("g", 0x4) // same as CPSR_s
3990 .Case("nzcvqg", 0xc) // same as CPSR_fs
3993 if (FlagsVal == ~0U) {
3995 return MatchOperand_NoMatch;
3997 FlagsVal = 8; // No flag
3999 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
4000 // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
4001 if (Flags == "all" || Flags == "")
4003 for (int i = 0, e = Flags.size(); i != e; ++i) {
4004 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
4011 // If some specific flag is already set, it means that some letter is
4012 // present more than once, this is not acceptable.
4013 if (FlagsVal == ~0U || (FlagsVal & Flag))
4014 return MatchOperand_NoMatch;
4017 } else // No match for special register.
4018 return MatchOperand_NoMatch;
4020 // Special register without flags is NOT equivalent to "fc" flags.
4021 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
4022 // two lines would enable gas compatibility at the expense of breaking
4028 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4029 if (SpecReg == "spsr")
4032 Parser.Lex(); // Eat identifier token.
4033 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
4034 return MatchOperand_Success;
4037 /// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for
4038 /// use in the MRS/MSR instructions added to support virtualization.
4039 ARMAsmParser::OperandMatchResultTy
4040 ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) {
4041 SMLoc S = Parser.getTok().getLoc();
4042 const AsmToken &Tok = Parser.getTok();
4043 if (!Tok.is(AsmToken::Identifier))
4044 return MatchOperand_NoMatch;
4045 StringRef RegName = Tok.getString();
4047 // The values here come from B9.2.3 of the ARM ARM, where bits 4-0 are SysM
4049 unsigned Encoding = StringSwitch<unsigned>(RegName.lower())
4050 .Case("r8_usr", 0x00)
4051 .Case("r9_usr", 0x01)
4052 .Case("r10_usr", 0x02)
4053 .Case("r11_usr", 0x03)
4054 .Case("r12_usr", 0x04)
4055 .Case("sp_usr", 0x05)
4056 .Case("lr_usr", 0x06)
4057 .Case("r8_fiq", 0x08)
4058 .Case("r9_fiq", 0x09)
4059 .Case("r10_fiq", 0x0a)
4060 .Case("r11_fiq", 0x0b)
4061 .Case("r12_fiq", 0x0c)
4062 .Case("sp_fiq", 0x0d)
4063 .Case("lr_fiq", 0x0e)
4064 .Case("lr_irq", 0x10)
4065 .Case("sp_irq", 0x11)
4066 .Case("lr_svc", 0x12)
4067 .Case("sp_svc", 0x13)
4068 .Case("lr_abt", 0x14)
4069 .Case("sp_abt", 0x15)
4070 .Case("lr_und", 0x16)
4071 .Case("sp_und", 0x17)
4072 .Case("lr_mon", 0x1c)
4073 .Case("sp_mon", 0x1d)
4074 .Case("elr_hyp", 0x1e)
4075 .Case("sp_hyp", 0x1f)
4076 .Case("spsr_fiq", 0x2e)
4077 .Case("spsr_irq", 0x30)
4078 .Case("spsr_svc", 0x32)
4079 .Case("spsr_abt", 0x34)
4080 .Case("spsr_und", 0x36)
4081 .Case("spsr_mon", 0x3c)
4082 .Case("spsr_hyp", 0x3e)
4085 if (Encoding == ~0U)
4086 return MatchOperand_NoMatch;
4088 Parser.Lex(); // Eat identifier token.
4089 Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S));
4090 return MatchOperand_Success;
4093 ARMAsmParser::OperandMatchResultTy
4094 ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low,
4096 const AsmToken &Tok = Parser.getTok();
4097 if (Tok.isNot(AsmToken::Identifier)) {
4098 Error(Parser.getTok().getLoc(), Op + " operand expected.");
4099 return MatchOperand_ParseFail;
4101 StringRef ShiftName = Tok.getString();
4102 std::string LowerOp = Op.lower();
4103 std::string UpperOp = Op.upper();
4104 if (ShiftName != LowerOp && ShiftName != UpperOp) {
4105 Error(Parser.getTok().getLoc(), Op + " operand expected.");
4106 return MatchOperand_ParseFail;
4108 Parser.Lex(); // Eat shift type token.
4110 // There must be a '#' and a shift amount.
4111 if (Parser.getTok().isNot(AsmToken::Hash) &&
4112 Parser.getTok().isNot(AsmToken::Dollar)) {
4113 Error(Parser.getTok().getLoc(), "'#' expected");
4114 return MatchOperand_ParseFail;
4116 Parser.Lex(); // Eat hash token.
4118 const MCExpr *ShiftAmount;
4119 SMLoc Loc = Parser.getTok().getLoc();
4121 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4122 Error(Loc, "illegal expression");
4123 return MatchOperand_ParseFail;
4125 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4127 Error(Loc, "constant expression expected");
4128 return MatchOperand_ParseFail;
4130 int Val = CE->getValue();
4131 if (Val < Low || Val > High) {
4132 Error(Loc, "immediate value out of range");
4133 return MatchOperand_ParseFail;
4136 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
4138 return MatchOperand_Success;
4141 ARMAsmParser::OperandMatchResultTy
4142 ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
4143 const AsmToken &Tok = Parser.getTok();
4144 SMLoc S = Tok.getLoc();
4145 if (Tok.isNot(AsmToken::Identifier)) {
4146 Error(S, "'be' or 'le' operand expected");
4147 return MatchOperand_ParseFail;
4149 int Val = StringSwitch<int>(Tok.getString().lower())
4153 Parser.Lex(); // Eat the token.
4156 Error(S, "'be' or 'le' operand expected");
4157 return MatchOperand_ParseFail;
4159 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
4161 S, Tok.getEndLoc()));
4162 return MatchOperand_Success;
4165 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
4166 /// instructions. Legal values are:
4167 /// lsl #n 'n' in [0,31]
4168 /// asr #n 'n' in [1,32]
4169 /// n == 32 encoded as n == 0.
4170 ARMAsmParser::OperandMatchResultTy
4171 ARMAsmParser::parseShifterImm(OperandVector &Operands) {
4172 const AsmToken &Tok = Parser.getTok();
4173 SMLoc S = Tok.getLoc();
4174 if (Tok.isNot(AsmToken::Identifier)) {
4175 Error(S, "shift operator 'asr' or 'lsl' expected");
4176 return MatchOperand_ParseFail;
4178 StringRef ShiftName = Tok.getString();
4180 if (ShiftName == "lsl" || ShiftName == "LSL")
4182 else if (ShiftName == "asr" || ShiftName == "ASR")
4185 Error(S, "shift operator 'asr' or 'lsl' expected");
4186 return MatchOperand_ParseFail;
4188 Parser.Lex(); // Eat the operator.
4190 // A '#' and a shift amount.
4191 if (Parser.getTok().isNot(AsmToken::Hash) &&
4192 Parser.getTok().isNot(AsmToken::Dollar)) {
4193 Error(Parser.getTok().getLoc(), "'#' expected");
4194 return MatchOperand_ParseFail;
4196 Parser.Lex(); // Eat hash token.
4197 SMLoc ExLoc = Parser.getTok().getLoc();
4199 const MCExpr *ShiftAmount;
4201 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4202 Error(ExLoc, "malformed shift expression");
4203 return MatchOperand_ParseFail;
4205 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4207 Error(ExLoc, "shift amount must be an immediate");
4208 return MatchOperand_ParseFail;
4211 int64_t Val = CE->getValue();
4213 // Shift amount must be in [1,32]
4214 if (Val < 1 || Val > 32) {
4215 Error(ExLoc, "'asr' shift amount must be in range [1,32]");
4216 return MatchOperand_ParseFail;
4218 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
4219 if (isThumb() && Val == 32) {
4220 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
4221 return MatchOperand_ParseFail;
4223 if (Val == 32) Val = 0;
4225 // Shift amount must be in [1,32]
4226 if (Val < 0 || Val > 31) {
4227 Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
4228 return MatchOperand_ParseFail;
4232 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
4234 return MatchOperand_Success;
4237 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
4238 /// of instructions. Legal values are:
4239 /// ror #n 'n' in {0, 8, 16, 24}
4240 ARMAsmParser::OperandMatchResultTy
4241 ARMAsmParser::parseRotImm(OperandVector &Operands) {
4242 const AsmToken &Tok = Parser.getTok();
4243 SMLoc S = Tok.getLoc();
4244 if (Tok.isNot(AsmToken::Identifier))
4245 return MatchOperand_NoMatch;
4246 StringRef ShiftName = Tok.getString();
4247 if (ShiftName != "ror" && ShiftName != "ROR")
4248 return MatchOperand_NoMatch;
4249 Parser.Lex(); // Eat the operator.
4251 // A '#' and a rotate amount.
4252 if (Parser.getTok().isNot(AsmToken::Hash) &&
4253 Parser.getTok().isNot(AsmToken::Dollar)) {
4254 Error(Parser.getTok().getLoc(), "'#' expected");
4255 return MatchOperand_ParseFail;
4257 Parser.Lex(); // Eat hash token.
4258 SMLoc ExLoc = Parser.getTok().getLoc();
4260 const MCExpr *ShiftAmount;
4262 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4263 Error(ExLoc, "malformed rotate expression");
4264 return MatchOperand_ParseFail;
4266 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4268 Error(ExLoc, "rotate amount must be an immediate");
4269 return MatchOperand_ParseFail;
4272 int64_t Val = CE->getValue();
4273 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
4274 // normally, zero is represented in asm by omitting the rotate operand
4276 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
4277 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
4278 return MatchOperand_ParseFail;
4281 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
4283 return MatchOperand_Success;
4286 ARMAsmParser::OperandMatchResultTy
4287 ARMAsmParser::parseBitfield(OperandVector &Operands) {
4288 SMLoc S = Parser.getTok().getLoc();
4289 // The bitfield descriptor is really two operands, the LSB and the width.
4290 if (Parser.getTok().isNot(AsmToken::Hash) &&
4291 Parser.getTok().isNot(AsmToken::Dollar)) {
4292 Error(Parser.getTok().getLoc(), "'#' expected");
4293 return MatchOperand_ParseFail;
4295 Parser.Lex(); // Eat hash token.
4297 const MCExpr *LSBExpr;
4298 SMLoc E = Parser.getTok().getLoc();
4299 if (getParser().parseExpression(LSBExpr)) {
4300 Error(E, "malformed immediate expression");
4301 return MatchOperand_ParseFail;
4303 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
4305 Error(E, "'lsb' operand must be an immediate");
4306 return MatchOperand_ParseFail;
4309 int64_t LSB = CE->getValue();
4310 // The LSB must be in the range [0,31]
4311 if (LSB < 0 || LSB > 31) {
4312 Error(E, "'lsb' operand must be in the range [0,31]");
4313 return MatchOperand_ParseFail;
4315 E = Parser.getTok().getLoc();
4317 // Expect another immediate operand.
4318 if (Parser.getTok().isNot(AsmToken::Comma)) {
4319 Error(Parser.getTok().getLoc(), "too few operands");
4320 return MatchOperand_ParseFail;
4322 Parser.Lex(); // Eat hash token.
4323 if (Parser.getTok().isNot(AsmToken::Hash) &&
4324 Parser.getTok().isNot(AsmToken::Dollar)) {
4325 Error(Parser.getTok().getLoc(), "'#' expected");
4326 return MatchOperand_ParseFail;
4328 Parser.Lex(); // Eat hash token.
4330 const MCExpr *WidthExpr;
4332 if (getParser().parseExpression(WidthExpr, EndLoc)) {
4333 Error(E, "malformed immediate expression");
4334 return MatchOperand_ParseFail;
4336 CE = dyn_cast<MCConstantExpr>(WidthExpr);
4338 Error(E, "'width' operand must be an immediate");
4339 return MatchOperand_ParseFail;
4342 int64_t Width = CE->getValue();
4343 // The LSB must be in the range [1,32-lsb]
4344 if (Width < 1 || Width > 32 - LSB) {
4345 Error(E, "'width' operand must be in the range [1,32-lsb]");
4346 return MatchOperand_ParseFail;
4349 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4351 return MatchOperand_Success;
4354 ARMAsmParser::OperandMatchResultTy
4355 ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
4356 // Check for a post-index addressing register operand. Specifically:
4357 // postidx_reg := '+' register {, shift}
4358 // | '-' register {, shift}
4359 // | register {, shift}
4361 // This method must return MatchOperand_NoMatch without consuming any tokens
4362 // in the case where there is no match, as other alternatives take other
4364 AsmToken Tok = Parser.getTok();
4365 SMLoc S = Tok.getLoc();
4366 bool haveEaten = false;
4368 if (Tok.is(AsmToken::Plus)) {
4369 Parser.Lex(); // Eat the '+' token.
4371 } else if (Tok.is(AsmToken::Minus)) {
4372 Parser.Lex(); // Eat the '-' token.
4377 SMLoc E = Parser.getTok().getEndLoc();
4378 int Reg = tryParseRegister();
4381 return MatchOperand_NoMatch;
4382 Error(Parser.getTok().getLoc(), "register expected");
4383 return MatchOperand_ParseFail;
4386 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4387 unsigned ShiftImm = 0;
4388 if (Parser.getTok().is(AsmToken::Comma)) {
4389 Parser.Lex(); // Eat the ','.
4390 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4391 return MatchOperand_ParseFail;
4393 // FIXME: Only approximates end...may include intervening whitespace.
4394 E = Parser.getTok().getLoc();
4397 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4400 return MatchOperand_Success;
4403 ARMAsmParser::OperandMatchResultTy
4404 ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
4405 // Check for a post-index addressing register operand. Specifically:
4406 // am3offset := '+' register
4413 // This method must return MatchOperand_NoMatch without consuming any tokens
4414 // in the case where there is no match, as other alternatives take other
4416 AsmToken Tok = Parser.getTok();
4417 SMLoc S = Tok.getLoc();
4419 // Do immediates first, as we always parse those if we have a '#'.
4420 if (Parser.getTok().is(AsmToken::Hash) ||
4421 Parser.getTok().is(AsmToken::Dollar)) {
4422 Parser.Lex(); // Eat '#' or '$'.
4423 // Explicitly look for a '-', as we need to encode negative zero
4425 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4426 const MCExpr *Offset;
4428 if (getParser().parseExpression(Offset, E))
4429 return MatchOperand_ParseFail;
4430 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4432 Error(S, "constant expression expected");
4433 return MatchOperand_ParseFail;
4435 // Negative zero is encoded as the flag value INT32_MIN.
4436 int32_t Val = CE->getValue();
4437 if (isNegative && Val == 0)
4441 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4443 return MatchOperand_Success;
4447 bool haveEaten = false;
4449 if (Tok.is(AsmToken::Plus)) {
4450 Parser.Lex(); // Eat the '+' token.
4452 } else if (Tok.is(AsmToken::Minus)) {
4453 Parser.Lex(); // Eat the '-' token.
4458 Tok = Parser.getTok();
4459 int Reg = tryParseRegister();
4462 return MatchOperand_NoMatch;
4463 Error(Tok.getLoc(), "register expected");
4464 return MatchOperand_ParseFail;
4467 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4468 0, S, Tok.getEndLoc()));
4470 return MatchOperand_Success;
4473 /// Convert parsed operands to MCInst. Needed here because this instruction
4474 /// only has two register operands, but multiplication is commutative so
4475 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4476 void ARMAsmParser::cvtThumbMultiply(MCInst &Inst,
4477 const OperandVector &Operands) {
4478 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1);
4479 ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1);
4480 // If we have a three-operand form, make sure to set Rn to be the operand
4481 // that isn't the same as Rd.
4483 if (Operands.size() == 6 &&
4484 ((ARMOperand &)*Operands[4]).getReg() ==
4485 ((ARMOperand &)*Operands[3]).getReg())
4487 ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1);
4488 Inst.addOperand(Inst.getOperand(0));
4489 ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2);
4492 void ARMAsmParser::cvtThumbBranches(MCInst &Inst,
4493 const OperandVector &Operands) {
4494 int CondOp = -1, ImmOp = -1;
4495 switch(Inst.getOpcode()) {
4497 case ARM::tBcc: CondOp = 1; ImmOp = 2; break;
4500 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4502 default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4504 // first decide whether or not the branch should be conditional
4505 // by looking at it's location relative to an IT block
4507 // inside an IT block we cannot have any conditional branches. any
4508 // such instructions needs to be converted to unconditional form
4509 switch(Inst.getOpcode()) {
4510 case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4511 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4514 // outside IT blocks we can only have unconditional branches with AL
4515 // condition code or conditional branches with non-AL condition code
4516 unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode();
4517 switch(Inst.getOpcode()) {
4520 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4524 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4529 // now decide on encoding size based on branch target range
4530 switch(Inst.getOpcode()) {
4531 // classify tB as either t2B or t1B based on range of immediate operand
4533 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
4534 if (!op.isSignedOffset<11, 1>() && isThumbTwo())
4535 Inst.setOpcode(ARM::t2B);
4538 // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4540 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
4541 if (!op.isSignedOffset<8, 1>() && isThumbTwo())
4542 Inst.setOpcode(ARM::t2Bcc);
4546 ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1);
4547 ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2);
4550 /// Parse an ARM memory expression, return false if successful else return true
4551 /// or an error. The first token must be a '[' when called.
4552 bool ARMAsmParser::parseMemory(OperandVector &Operands) {
4554 assert(Parser.getTok().is(AsmToken::LBrac) &&
4555 "Token is not a Left Bracket");
4556 S = Parser.getTok().getLoc();
4557 Parser.Lex(); // Eat left bracket token.
4559 const AsmToken &BaseRegTok = Parser.getTok();
4560 int BaseRegNum = tryParseRegister();
4561 if (BaseRegNum == -1)
4562 return Error(BaseRegTok.getLoc(), "register expected");
4564 // The next token must either be a comma, a colon or a closing bracket.
4565 const AsmToken &Tok = Parser.getTok();
4566 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4567 !Tok.is(AsmToken::RBrac))
4568 return Error(Tok.getLoc(), "malformed memory operand");
4570 if (Tok.is(AsmToken::RBrac)) {
4571 E = Tok.getEndLoc();
4572 Parser.Lex(); // Eat right bracket token.
4574 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4575 ARM_AM::no_shift, 0, 0, false,
4578 // If there's a pre-indexing writeback marker, '!', just add it as a token
4579 // operand. It's rather odd, but syntactically valid.
4580 if (Parser.getTok().is(AsmToken::Exclaim)) {
4581 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4582 Parser.Lex(); // Eat the '!'.
4588 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4589 "Lost colon or comma in memory operand?!");
4590 if (Tok.is(AsmToken::Comma)) {
4591 Parser.Lex(); // Eat the comma.
4594 // If we have a ':', it's an alignment specifier.
4595 if (Parser.getTok().is(AsmToken::Colon)) {
4596 Parser.Lex(); // Eat the ':'.
4597 E = Parser.getTok().getLoc();
4598 SMLoc AlignmentLoc = Tok.getLoc();
4601 if (getParser().parseExpression(Expr))
4604 // The expression has to be a constant. Memory references with relocations
4605 // don't come through here, as they use the <label> forms of the relevant
4607 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4609 return Error (E, "constant expression expected");
4612 switch (CE->getValue()) {
4615 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4616 case 16: Align = 2; break;
4617 case 32: Align = 4; break;
4618 case 64: Align = 8; break;
4619 case 128: Align = 16; break;
4620 case 256: Align = 32; break;
4623 // Now we should have the closing ']'
4624 if (Parser.getTok().isNot(AsmToken::RBrac))
4625 return Error(Parser.getTok().getLoc(), "']' expected");
4626 E = Parser.getTok().getEndLoc();
4627 Parser.Lex(); // Eat right bracket token.
4629 // Don't worry about range checking the value here. That's handled by
4630 // the is*() predicates.
4631 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4632 ARM_AM::no_shift, 0, Align,
4633 false, S, E, AlignmentLoc));
4635 // If there's a pre-indexing writeback marker, '!', just add it as a token
4637 if (Parser.getTok().is(AsmToken::Exclaim)) {
4638 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4639 Parser.Lex(); // Eat the '!'.
4645 // If we have a '#', it's an immediate offset, else assume it's a register
4646 // offset. Be friendly and also accept a plain integer (without a leading
4647 // hash) for gas compatibility.
4648 if (Parser.getTok().is(AsmToken::Hash) ||
4649 Parser.getTok().is(AsmToken::Dollar) ||
4650 Parser.getTok().is(AsmToken::Integer)) {
4651 if (Parser.getTok().isNot(AsmToken::Integer))
4652 Parser.Lex(); // Eat '#' or '$'.
4653 E = Parser.getTok().getLoc();
4655 bool isNegative = getParser().getTok().is(AsmToken::Minus);
4656 const MCExpr *Offset;
4657 if (getParser().parseExpression(Offset))
4660 // The expression has to be a constant. Memory references with relocations
4661 // don't come through here, as they use the <label> forms of the relevant
4663 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4665 return Error (E, "constant expression expected");
4667 // If the constant was #-0, represent it as INT32_MIN.
4668 int32_t Val = CE->getValue();
4669 if (isNegative && Val == 0)
4670 CE = MCConstantExpr::Create(INT32_MIN, getContext());
4672 // Now we should have the closing ']'
4673 if (Parser.getTok().isNot(AsmToken::RBrac))
4674 return Error(Parser.getTok().getLoc(), "']' expected");
4675 E = Parser.getTok().getEndLoc();
4676 Parser.Lex(); // Eat right bracket token.
4678 // Don't worry about range checking the value here. That's handled by
4679 // the is*() predicates.
4680 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4681 ARM_AM::no_shift, 0, 0,
4684 // If there's a pre-indexing writeback marker, '!', just add it as a token
4686 if (Parser.getTok().is(AsmToken::Exclaim)) {
4687 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4688 Parser.Lex(); // Eat the '!'.
4694 // The register offset is optionally preceded by a '+' or '-'
4695 bool isNegative = false;
4696 if (Parser.getTok().is(AsmToken::Minus)) {
4698 Parser.Lex(); // Eat the '-'.
4699 } else if (Parser.getTok().is(AsmToken::Plus)) {
4701 Parser.Lex(); // Eat the '+'.
4704 E = Parser.getTok().getLoc();
4705 int OffsetRegNum = tryParseRegister();
4706 if (OffsetRegNum == -1)
4707 return Error(E, "register expected");
4709 // If there's a shift operator, handle it.
4710 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4711 unsigned ShiftImm = 0;
4712 if (Parser.getTok().is(AsmToken::Comma)) {
4713 Parser.Lex(); // Eat the ','.
4714 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4718 // Now we should have the closing ']'
4719 if (Parser.getTok().isNot(AsmToken::RBrac))
4720 return Error(Parser.getTok().getLoc(), "']' expected");
4721 E = Parser.getTok().getEndLoc();
4722 Parser.Lex(); // Eat right bracket token.
4724 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum,
4725 ShiftType, ShiftImm, 0, isNegative,
4728 // If there's a pre-indexing writeback marker, '!', just add it as a token
4730 if (Parser.getTok().is(AsmToken::Exclaim)) {
4731 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4732 Parser.Lex(); // Eat the '!'.
4738 /// parseMemRegOffsetShift - one of these two:
4739 /// ( lsl | lsr | asr | ror ) , # shift_amount
4741 /// return true if it parses a shift otherwise it returns false.
4742 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4744 SMLoc Loc = Parser.getTok().getLoc();
4745 const AsmToken &Tok = Parser.getTok();
4746 if (Tok.isNot(AsmToken::Identifier))
4748 StringRef ShiftName = Tok.getString();
4749 if (ShiftName == "lsl" || ShiftName == "LSL" ||
4750 ShiftName == "asl" || ShiftName == "ASL")
4752 else if (ShiftName == "lsr" || ShiftName == "LSR")
4754 else if (ShiftName == "asr" || ShiftName == "ASR")
4756 else if (ShiftName == "ror" || ShiftName == "ROR")
4758 else if (ShiftName == "rrx" || ShiftName == "RRX")
4761 return Error(Loc, "illegal shift operator");
4762 Parser.Lex(); // Eat shift type token.
4764 // rrx stands alone.
4766 if (St != ARM_AM::rrx) {
4767 Loc = Parser.getTok().getLoc();
4768 // A '#' and a shift amount.
4769 const AsmToken &HashTok = Parser.getTok();
4770 if (HashTok.isNot(AsmToken::Hash) &&
4771 HashTok.isNot(AsmToken::Dollar))
4772 return Error(HashTok.getLoc(), "'#' expected");
4773 Parser.Lex(); // Eat hash token.
4776 if (getParser().parseExpression(Expr))
4778 // Range check the immediate.
4779 // lsl, ror: 0 <= imm <= 31
4780 // lsr, asr: 0 <= imm <= 32
4781 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4783 return Error(Loc, "shift amount must be an immediate");
4784 int64_t Imm = CE->getValue();
4786 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4787 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4788 return Error(Loc, "immediate shift value out of range");
4789 // If <ShiftTy> #0, turn it into a no_shift.
4792 // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4801 /// parseFPImm - A floating point immediate expression operand.
4802 ARMAsmParser::OperandMatchResultTy
4803 ARMAsmParser::parseFPImm(OperandVector &Operands) {
4804 // Anything that can accept a floating point constant as an operand
4805 // needs to go through here, as the regular parseExpression is
4808 // This routine still creates a generic Immediate operand, containing
4809 // a bitcast of the 64-bit floating point value. The various operands
4810 // that accept floats can check whether the value is valid for them
4811 // via the standard is*() predicates.
4813 SMLoc S = Parser.getTok().getLoc();
4815 if (Parser.getTok().isNot(AsmToken::Hash) &&
4816 Parser.getTok().isNot(AsmToken::Dollar))
4817 return MatchOperand_NoMatch;
4819 // Disambiguate the VMOV forms that can accept an FP immediate.
4820 // vmov.f32 <sreg>, #imm
4821 // vmov.f64 <dreg>, #imm
4822 // vmov.f32 <dreg>, #imm @ vector f32x2
4823 // vmov.f32 <qreg>, #imm @ vector f32x4
4825 // There are also the NEON VMOV instructions which expect an
4826 // integer constant. Make sure we don't try to parse an FPImm
4828 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4829 ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]);
4830 bool isVmovf = TyOp.isToken() &&
4831 (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64");
4832 ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]);
4833 bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" ||
4834 Mnemonic.getToken() == "fconsts");
4835 if (!(isVmovf || isFconst))
4836 return MatchOperand_NoMatch;
4838 Parser.Lex(); // Eat '#' or '$'.
4840 // Handle negation, as that still comes through as a separate token.
4841 bool isNegative = false;
4842 if (Parser.getTok().is(AsmToken::Minus)) {
4846 const AsmToken &Tok = Parser.getTok();
4847 SMLoc Loc = Tok.getLoc();
4848 if (Tok.is(AsmToken::Real) && isVmovf) {
4849 APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4850 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4851 // If we had a '-' in front, toggle the sign bit.
4852 IntVal ^= (uint64_t)isNegative << 31;
4853 Parser.Lex(); // Eat the token.
4854 Operands.push_back(ARMOperand::CreateImm(
4855 MCConstantExpr::Create(IntVal, getContext()),
4856 S, Parser.getTok().getLoc()));
4857 return MatchOperand_Success;
4859 // Also handle plain integers. Instructions which allow floating point
4860 // immediates also allow a raw encoded 8-bit value.
4861 if (Tok.is(AsmToken::Integer) && isFconst) {
4862 int64_t Val = Tok.getIntVal();
4863 Parser.Lex(); // Eat the token.
4864 if (Val > 255 || Val < 0) {
4865 Error(Loc, "encoded floating point value out of range");
4866 return MatchOperand_ParseFail;
4868 float RealVal = ARM_AM::getFPImmFloat(Val);
4869 Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
4871 Operands.push_back(ARMOperand::CreateImm(
4872 MCConstantExpr::Create(Val, getContext()), S,
4873 Parser.getTok().getLoc()));
4874 return MatchOperand_Success;
4877 Error(Loc, "invalid floating point immediate");
4878 return MatchOperand_ParseFail;
4881 /// Parse a arm instruction operand. For now this parses the operand regardless
4882 /// of the mnemonic.
4883 bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
4886 // Check if the current operand has a custom associated parser, if so, try to
4887 // custom parse the operand, or fallback to the general approach.
4888 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4889 if (ResTy == MatchOperand_Success)
4891 // If there wasn't a custom match, try the generic matcher below. Otherwise,
4892 // there was a match, but an error occurred, in which case, just return that
4893 // the operand parsing failed.
4894 if (ResTy == MatchOperand_ParseFail)
4897 switch (getLexer().getKind()) {
4899 Error(Parser.getTok().getLoc(), "unexpected token in operand");
4901 case AsmToken::Identifier: {
4902 // If we've seen a branch mnemonic, the next operand must be a label. This
4903 // is true even if the label is a register name. So "br r1" means branch to
4905 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
4907 if (!tryParseRegisterWithWriteBack(Operands))
4909 int Res = tryParseShiftRegister(Operands);
4910 if (Res == 0) // success
4912 else if (Res == -1) // irrecoverable error
4914 // If this is VMRS, check for the apsr_nzcv operand.
4915 if (Mnemonic == "vmrs" &&
4916 Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4917 S = Parser.getTok().getLoc();
4919 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4924 // Fall though for the Identifier case that is not a register or a
4927 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
4928 case AsmToken::Integer: // things like 1f and 2b as a branch targets
4929 case AsmToken::String: // quoted label names.
4930 case AsmToken::Dot: { // . as a branch target
4931 // This was not a register so parse other operands that start with an
4932 // identifier (like labels) as expressions and create them as immediates.
4933 const MCExpr *IdVal;
4934 S = Parser.getTok().getLoc();
4935 if (getParser().parseExpression(IdVal))
4937 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4938 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4941 case AsmToken::LBrac:
4942 return parseMemory(Operands);
4943 case AsmToken::LCurly:
4944 return parseRegisterList(Operands);
4945 case AsmToken::Dollar:
4946 case AsmToken::Hash: {
4947 // #42 -> immediate.
4948 S = Parser.getTok().getLoc();
4951 if (Parser.getTok().isNot(AsmToken::Colon)) {
4952 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4953 const MCExpr *ImmVal;
4954 if (getParser().parseExpression(ImmVal))
4956 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4958 int32_t Val = CE->getValue();
4959 if (isNegative && Val == 0)
4960 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4962 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4963 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4965 // There can be a trailing '!' on operands that we want as a separate
4966 // '!' Token operand. Handle that here. For example, the compatibility
4967 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
4968 if (Parser.getTok().is(AsmToken::Exclaim)) {
4969 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
4970 Parser.getTok().getLoc()));
4971 Parser.Lex(); // Eat exclaim token
4975 // w/ a ':' after the '#', it's just like a plain ':'.
4978 case AsmToken::Colon: {
4979 // ":lower16:" and ":upper16:" expression prefixes
4980 // FIXME: Check it's an expression prefix,
4981 // e.g. (FOO - :lower16:BAR) isn't legal.
4982 ARMMCExpr::VariantKind RefKind;
4983 if (parsePrefix(RefKind))
4986 const MCExpr *SubExprVal;
4987 if (getParser().parseExpression(SubExprVal))
4990 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4992 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4993 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4996 case AsmToken::Equal: {
4997 if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
4998 return Error(Parser.getTok().getLoc(), "unexpected token in operand");
5000 Parser.Lex(); // Eat '='
5001 const MCExpr *SubExprVal;
5002 if (getParser().parseExpression(SubExprVal))
5004 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5006 const MCExpr *CPLoc = getTargetStreamer().addConstantPoolEntry(SubExprVal);
5007 Operands.push_back(ARMOperand::CreateImm(CPLoc, S, E));
5013 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
5014 // :lower16: and :upper16:.
5015 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
5016 RefKind = ARMMCExpr::VK_ARM_None;
5018 // consume an optional '#' (GNU compatibility)
5019 if (getLexer().is(AsmToken::Hash))
5022 // :lower16: and :upper16: modifiers
5023 assert(getLexer().is(AsmToken::Colon) && "expected a :");
5024 Parser.Lex(); // Eat ':'
5026 if (getLexer().isNot(AsmToken::Identifier)) {
5027 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
5031 StringRef IDVal = Parser.getTok().getIdentifier();
5032 if (IDVal == "lower16") {
5033 RefKind = ARMMCExpr::VK_ARM_LO16;
5034 } else if (IDVal == "upper16") {
5035 RefKind = ARMMCExpr::VK_ARM_HI16;
5037 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
5042 if (getLexer().isNot(AsmToken::Colon)) {
5043 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
5046 Parser.Lex(); // Eat the last ':'
5050 /// \brief Given a mnemonic, split out possible predication code and carry
5051 /// setting letters to form a canonical mnemonic and flags.
5053 // FIXME: Would be nice to autogen this.
5054 // FIXME: This is a bit of a maze of special cases.
5055 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
5056 unsigned &PredicationCode,
5058 unsigned &ProcessorIMod,
5059 StringRef &ITMask) {
5060 PredicationCode = ARMCC::AL;
5061 CarrySetting = false;
5064 // Ignore some mnemonics we know aren't predicated forms.
5066 // FIXME: Would be nice to autogen this.
5067 if ((Mnemonic == "movs" && isThumb()) ||
5068 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
5069 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
5070 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
5071 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
5072 Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" ||
5073 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
5074 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
5075 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
5076 Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
5077 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" ||
5078 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
5079 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel"))
5082 // First, split out any predication code. Ignore mnemonics we know aren't
5083 // predicated but do have a carry-set and so weren't caught above.
5084 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
5085 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
5086 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
5087 Mnemonic != "sbcs" && Mnemonic != "rscs") {
5088 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
5089 .Case("eq", ARMCC::EQ)
5090 .Case("ne", ARMCC::NE)
5091 .Case("hs", ARMCC::HS)
5092 .Case("cs", ARMCC::HS)
5093 .Case("lo", ARMCC::LO)
5094 .Case("cc", ARMCC::LO)
5095 .Case("mi", ARMCC::MI)
5096 .Case("pl", ARMCC::PL)
5097 .Case("vs", ARMCC::VS)
5098 .Case("vc", ARMCC::VC)
5099 .Case("hi", ARMCC::HI)
5100 .Case("ls", ARMCC::LS)
5101 .Case("ge", ARMCC::GE)
5102 .Case("lt", ARMCC::LT)
5103 .Case("gt", ARMCC::GT)
5104 .Case("le", ARMCC::LE)
5105 .Case("al", ARMCC::AL)
5108 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
5109 PredicationCode = CC;
5113 // Next, determine if we have a carry setting bit. We explicitly ignore all
5114 // the instructions we know end in 's'.
5115 if (Mnemonic.endswith("s") &&
5116 !(Mnemonic == "cps" || Mnemonic == "mls" ||
5117 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
5118 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
5119 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
5120 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
5121 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
5122 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
5123 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
5124 Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
5125 (Mnemonic == "movs" && isThumb()))) {
5126 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
5127 CarrySetting = true;
5130 // The "cps" instruction can have a interrupt mode operand which is glued into
5131 // the mnemonic. Check if this is the case, split it and parse the imod op
5132 if (Mnemonic.startswith("cps")) {
5133 // Split out any imod code.
5135 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
5136 .Case("ie", ARM_PROC::IE)
5137 .Case("id", ARM_PROC::ID)
5140 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
5141 ProcessorIMod = IMod;
5145 // The "it" instruction has the condition mask on the end of the mnemonic.
5146 if (Mnemonic.startswith("it")) {
5147 ITMask = Mnemonic.slice(2, Mnemonic.size());
5148 Mnemonic = Mnemonic.slice(0, 2);
5154 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
5155 /// inclusion of carry set or predication code operands.
5157 // FIXME: It would be nice to autogen this.
5159 getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
5160 bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) {
5161 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5162 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
5163 Mnemonic == "add" || Mnemonic == "adc" ||
5164 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
5165 Mnemonic == "orr" || Mnemonic == "mvn" ||
5166 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
5167 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
5168 Mnemonic == "vfm" || Mnemonic == "vfnm" ||
5169 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
5170 Mnemonic == "mla" || Mnemonic == "smlal" ||
5171 Mnemonic == "umlal" || Mnemonic == "umull"))) {
5172 CanAcceptCarrySet = true;
5174 CanAcceptCarrySet = false;
5176 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
5177 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
5178 Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic == "udf" ||
5179 Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") ||
5180 Mnemonic.startswith("vsel") ||
5181 Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
5182 Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
5183 Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
5184 Mnemonic == "vrintm" || Mnemonic.startswith("aes") ||
5185 Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
5186 (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) {
5187 // These mnemonics are never predicable
5188 CanAcceptPredicationCode = false;
5189 } else if (!isThumb()) {
5190 // Some instructions are only predicable in Thumb mode
5191 CanAcceptPredicationCode
5192 = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
5193 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
5194 Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
5195 Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
5196 Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
5197 Mnemonic != "stc2" && Mnemonic != "stc2l" &&
5198 !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
5199 } else if (isThumbOne()) {
5201 CanAcceptPredicationCode = Mnemonic != "movs";
5203 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
5205 CanAcceptPredicationCode = true;
5208 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
5209 OperandVector &Operands) {
5210 // FIXME: This is all horribly hacky. We really need a better way to deal
5211 // with optional operands like this in the matcher table.
5213 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
5214 // another does not. Specifically, the MOVW instruction does not. So we
5215 // special case it here and remove the defaulted (non-setting) cc_out
5216 // operand if that's the instruction we're trying to match.
5218 // We do this as post-processing of the explicit operands rather than just
5219 // conditionally adding the cc_out in the first place because we need
5220 // to check the type of the parsed immediate operand.
5221 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
5222 !static_cast<ARMOperand &>(*Operands[4]).isARMSOImm() &&
5223 static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() &&
5224 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5227 // Register-register 'add' for thumb does not have a cc_out operand
5228 // when there are only two register operands.
5229 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
5230 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5231 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5232 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5234 // Register-register 'add' for thumb does not have a cc_out operand
5235 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
5236 // have to check the immediate range here since Thumb2 has a variant
5237 // that can handle a different range and has a cc_out operand.
5238 if (((isThumb() && Mnemonic == "add") ||
5239 (isThumbTwo() && Mnemonic == "sub")) &&
5240 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5241 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5242 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP &&
5243 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5244 ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) ||
5245 static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4()))
5247 // For Thumb2, add/sub immediate does not have a cc_out operand for the
5248 // imm0_4095 variant. That's the least-preferred variant when
5249 // selecting via the generic "add" mnemonic, so to know that we
5250 // should remove the cc_out operand, we have to explicitly check that
5251 // it's not one of the other variants. Ugh.
5252 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
5253 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5254 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5255 static_cast<ARMOperand &>(*Operands[5]).isImm()) {
5256 // Nest conditions rather than one big 'if' statement for readability.
5258 // If both registers are low, we're in an IT block, and the immediate is
5259 // in range, we should use encoding T1 instead, which has a cc_out.
5261 isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) &&
5262 isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) &&
5263 static_cast<ARMOperand &>(*Operands[5]).isImm0_7())
5265 // Check against T3. If the second register is the PC, this is an
5266 // alternate form of ADR, which uses encoding T4, so check for that too.
5267 if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC &&
5268 static_cast<ARMOperand &>(*Operands[5]).isT2SOImm())
5271 // Otherwise, we use encoding T4, which does not have a cc_out
5276 // The thumb2 multiply instruction doesn't have a CCOut register, so
5277 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
5278 // use the 16-bit encoding or not.
5279 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5280 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5281 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5282 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5283 static_cast<ARMOperand &>(*Operands[5]).isReg() &&
5284 // If the registers aren't low regs, the destination reg isn't the
5285 // same as one of the source regs, or the cc_out operand is zero
5286 // outside of an IT block, we have to use the 32-bit encoding, so
5287 // remove the cc_out operand.
5288 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5289 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5290 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) ||
5291 !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5292 static_cast<ARMOperand &>(*Operands[5]).getReg() &&
5293 static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5294 static_cast<ARMOperand &>(*Operands[4]).getReg())))
5297 // Also check the 'mul' syntax variant that doesn't specify an explicit
5298 // destination register.
5299 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5300 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5301 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5302 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5303 // If the registers aren't low regs or the cc_out operand is zero
5304 // outside of an IT block, we have to use the 32-bit encoding, so
5305 // remove the cc_out operand.
5306 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5307 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5313 // Register-register 'add/sub' for thumb does not have a cc_out operand
5314 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5315 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
5316 // right, this will result in better diagnostics (which operand is off)
5318 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
5319 (Operands.size() == 5 || Operands.size() == 6) &&
5320 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5321 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP &&
5322 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5323 (static_cast<ARMOperand &>(*Operands[4]).isImm() ||
5324 (Operands.size() == 6 &&
5325 static_cast<ARMOperand &>(*Operands[5]).isImm())))
5331 bool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic,
5332 OperandVector &Operands) {
5333 // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
5334 unsigned RegIdx = 3;
5335 if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
5336 static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32") {
5337 if (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
5338 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32")
5341 if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() &&
5342 (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
5343 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) ||
5344 ARMMCRegisterClasses[ARM::QPRRegClassID].contains(
5345 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg())))
5351 static bool isDataTypeToken(StringRef Tok) {
5352 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5353 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5354 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5355 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5356 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5357 Tok == ".f" || Tok == ".d";
5360 // FIXME: This bit should probably be handled via an explicit match class
5361 // in the .td files that matches the suffix instead of having it be
5362 // a literal string token the way it is now.
5363 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5364 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5366 static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features,
5367 unsigned VariantID);
5369 static bool RequiresVFPRegListValidation(StringRef Inst,
5370 bool &AcceptSinglePrecisionOnly,
5371 bool &AcceptDoublePrecisionOnly) {
5372 if (Inst.size() < 7)
5375 if (Inst.startswith("fldm") || Inst.startswith("fstm")) {
5376 StringRef AddressingMode = Inst.substr(4, 2);
5377 if (AddressingMode == "ia" || AddressingMode == "db" ||
5378 AddressingMode == "ea" || AddressingMode == "fd") {
5379 AcceptSinglePrecisionOnly = Inst[6] == 's';
5380 AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x';
5388 /// Parse an arm instruction mnemonic followed by its operands.
5389 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5390 SMLoc NameLoc, OperandVector &Operands) {
5391 // FIXME: Can this be done via tablegen in some fashion?
5392 bool RequireVFPRegisterListCheck;
5393 bool AcceptSinglePrecisionOnly;
5394 bool AcceptDoublePrecisionOnly;
5395 RequireVFPRegisterListCheck =
5396 RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly,
5397 AcceptDoublePrecisionOnly);
5399 // Apply mnemonic aliases before doing anything else, as the destination
5400 // mnemonic may include suffices and we want to handle them normally.
5401 // The generic tblgen'erated code does this later, at the start of
5402 // MatchInstructionImpl(), but that's too late for aliases that include
5403 // any sort of suffix.
5404 uint64_t AvailableFeatures = getAvailableFeatures();
5405 unsigned AssemblerDialect = getParser().getAssemblerDialect();
5406 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5408 // First check for the ARM-specific .req directive.
5409 if (Parser.getTok().is(AsmToken::Identifier) &&
5410 Parser.getTok().getIdentifier() == ".req") {
5411 parseDirectiveReq(Name, NameLoc);
5412 // We always return 'error' for this, as we're done with this
5413 // statement and don't need to match the 'instruction."
5417 // Create the leading tokens for the mnemonic, split by '.' characters.
5418 size_t Start = 0, Next = Name.find('.');
5419 StringRef Mnemonic = Name.slice(Start, Next);
5421 // Split out the predication code and carry setting flag from the mnemonic.
5422 unsigned PredicationCode;
5423 unsigned ProcessorIMod;
5426 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5427 ProcessorIMod, ITMask);
5429 // In Thumb1, only the branch (B) instruction can be predicated.
5430 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5431 Parser.eatToEndOfStatement();
5432 return Error(NameLoc, "conditional execution not supported in Thumb1");
5435 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5437 // Handle the IT instruction ITMask. Convert it to a bitmask. This
5438 // is the mask as it will be for the IT encoding if the conditional
5439 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5440 // where the conditional bit0 is zero, the instruction post-processing
5441 // will adjust the mask accordingly.
5442 if (Mnemonic == "it") {
5443 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5444 if (ITMask.size() > 3) {
5445 Parser.eatToEndOfStatement();
5446 return Error(Loc, "too many conditions on IT instruction");
5449 for (unsigned i = ITMask.size(); i != 0; --i) {
5450 char pos = ITMask[i - 1];
5451 if (pos != 't' && pos != 'e') {
5452 Parser.eatToEndOfStatement();
5453 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5456 if (ITMask[i - 1] == 't')
5459 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5462 // FIXME: This is all a pretty gross hack. We should automatically handle
5463 // optional operands like this via tblgen.
5465 // Next, add the CCOut and ConditionCode operands, if needed.
5467 // For mnemonics which can ever incorporate a carry setting bit or predication
5468 // code, our matching model involves us always generating CCOut and
5469 // ConditionCode operands to match the mnemonic "as written" and then we let
5470 // the matcher deal with finding the right instruction or generating an
5471 // appropriate error.
5472 bool CanAcceptCarrySet, CanAcceptPredicationCode;
5473 getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
5475 // If we had a carry-set on an instruction that can't do that, issue an
5477 if (!CanAcceptCarrySet && CarrySetting) {
5478 Parser.eatToEndOfStatement();
5479 return Error(NameLoc, "instruction '" + Mnemonic +
5480 "' can not set flags, but 's' suffix specified");
5482 // If we had a predication code on an instruction that can't do that, issue an
5484 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5485 Parser.eatToEndOfStatement();
5486 return Error(NameLoc, "instruction '" + Mnemonic +
5487 "' is not predicable, but condition code specified");
5490 // Add the carry setting operand, if necessary.
5491 if (CanAcceptCarrySet) {
5492 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5493 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5497 // Add the predication code operand, if necessary.
5498 if (CanAcceptPredicationCode) {
5499 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5501 Operands.push_back(ARMOperand::CreateCondCode(
5502 ARMCC::CondCodes(PredicationCode), Loc));
5505 // Add the processor imod operand, if necessary.
5506 if (ProcessorIMod) {
5507 Operands.push_back(ARMOperand::CreateImm(
5508 MCConstantExpr::Create(ProcessorIMod, getContext()),
5512 // Add the remaining tokens in the mnemonic.
5513 while (Next != StringRef::npos) {
5515 Next = Name.find('.', Start + 1);
5516 StringRef ExtraToken = Name.slice(Start, Next);
5518 // Some NEON instructions have an optional datatype suffix that is
5519 // completely ignored. Check for that.
5520 if (isDataTypeToken(ExtraToken) &&
5521 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5524 // For for ARM mode generate an error if the .n qualifier is used.
5525 if (ExtraToken == ".n" && !isThumb()) {
5526 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5527 Parser.eatToEndOfStatement();
5528 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5532 // The .n qualifier is always discarded as that is what the tables
5533 // and matcher expect. In ARM mode the .w qualifier has no effect,
5534 // so discard it to avoid errors that can be caused by the matcher.
5535 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5536 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5537 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5541 // Read the remaining operands.
5542 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5543 // Read the first operand.
5544 if (parseOperand(Operands, Mnemonic)) {
5545 Parser.eatToEndOfStatement();
5549 while (getLexer().is(AsmToken::Comma)) {
5550 Parser.Lex(); // Eat the comma.
5552 // Parse and remember the operand.
5553 if (parseOperand(Operands, Mnemonic)) {
5554 Parser.eatToEndOfStatement();
5560 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5561 SMLoc Loc = getLexer().getLoc();
5562 Parser.eatToEndOfStatement();
5563 return Error(Loc, "unexpected token in argument list");
5566 Parser.Lex(); // Consume the EndOfStatement
5568 if (RequireVFPRegisterListCheck) {
5569 ARMOperand &Op = static_cast<ARMOperand &>(*Operands.back());
5570 if (AcceptSinglePrecisionOnly && !Op.isSPRRegList())
5571 return Error(Op.getStartLoc(),
5572 "VFP/Neon single precision register expected");
5573 if (AcceptDoublePrecisionOnly && !Op.isDPRRegList())
5574 return Error(Op.getStartLoc(),
5575 "VFP/Neon double precision register expected");
5578 // Some instructions, mostly Thumb, have forms for the same mnemonic that
5579 // do and don't have a cc_out optional-def operand. With some spot-checks
5580 // of the operand list, we can figure out which variant we're trying to
5581 // parse and adjust accordingly before actually matching. We shouldn't ever
5582 // try to remove a cc_out operand that was explicitly set on the the
5583 // mnemonic, of course (CarrySetting == true). Reason number #317 the
5584 // table driven matcher doesn't fit well with the ARM instruction set.
5585 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands))
5586 Operands.erase(Operands.begin() + 1);
5588 // Some instructions have the same mnemonic, but don't always
5589 // have a predicate. Distinguish them here and delete the
5590 // predicate if needed.
5591 if (shouldOmitPredicateOperand(Mnemonic, Operands))
5592 Operands.erase(Operands.begin() + 1);
5594 // ARM mode 'blx' need special handling, as the register operand version
5595 // is predicable, but the label operand version is not. So, we can't rely
5596 // on the Mnemonic based checking to correctly figure out when to put
5597 // a k_CondCode operand in the list. If we're trying to match the label
5598 // version, remove the k_CondCode operand here.
5599 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5600 static_cast<ARMOperand &>(*Operands[2]).isImm())
5601 Operands.erase(Operands.begin() + 1);
5603 // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5604 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5605 // a single GPRPair reg operand is used in the .td file to replace the two
5606 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5607 // expressed as a GPRPair, so we have to manually merge them.
5608 // FIXME: We would really like to be able to tablegen'erate this.
5609 if (!isThumb() && Operands.size() > 4 &&
5610 (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
5611 Mnemonic == "stlexd")) {
5612 bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
5613 unsigned Idx = isLoad ? 2 : 3;
5614 ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]);
5615 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]);
5617 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5618 // Adjust only if Op1 and Op2 are GPRs.
5619 if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) &&
5620 MRC.contains(Op2.getReg())) {
5621 unsigned Reg1 = Op1.getReg();
5622 unsigned Reg2 = Op2.getReg();
5623 unsigned Rt = MRI->getEncodingValue(Reg1);
5624 unsigned Rt2 = MRI->getEncodingValue(Reg2);
5626 // Rt2 must be Rt + 1 and Rt must be even.
5627 if (Rt + 1 != Rt2 || (Rt & 1)) {
5628 Error(Op2.getStartLoc(), isLoad
5629 ? "destination operands must be sequential"
5630 : "source operands must be sequential");
5633 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5634 &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5636 ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc());
5637 Operands.erase(Operands.begin() + Idx + 1);
5641 // GNU Assembler extension (compatibility)
5642 if ((Mnemonic == "ldrd" || Mnemonic == "strd")) {
5643 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]);
5644 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
5646 assert(Op2.isReg() && "expected register argument");
5648 unsigned SuperReg = MRI->getMatchingSuperReg(
5649 Op2.getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID));
5651 assert(SuperReg && "expected register pair");
5653 unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1);
5656 Operands.begin() + 3,
5657 ARMOperand::CreateReg(PairedReg, Op2.getStartLoc(), Op2.getEndLoc()));
5661 // FIXME: As said above, this is all a pretty gross hack. This instruction
5662 // does not fit with other "subs" and tblgen.
5663 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
5664 // so the Mnemonic is the original name "subs" and delete the predicate
5665 // operand so it will match the table entry.
5666 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
5667 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5668 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC &&
5669 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5670 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR &&
5671 static_cast<ARMOperand &>(*Operands[5]).isImm()) {
5672 Operands.front() = ARMOperand::CreateToken(Name, NameLoc);
5673 Operands.erase(Operands.begin() + 1);
5678 // Validate context-sensitive operand constraints.
5680 // return 'true' if register list contains non-low GPR registers,
5681 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5682 // 'containsReg' to true.
5683 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5684 unsigned HiReg, bool &containsReg) {
5685 containsReg = false;
5686 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5687 unsigned OpReg = Inst.getOperand(i).getReg();
5690 // Anything other than a low register isn't legal here.
5691 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5697 // Check if the specified regisgter is in the register list of the inst,
5698 // starting at the indicated operand number.
5699 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5700 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5701 unsigned OpReg = Inst.getOperand(i).getReg();
5708 // Return true if instruction has the interesting property of being
5709 // allowed in IT blocks, but not being predicable.
5710 static bool instIsBreakpoint(const MCInst &Inst) {
5711 return Inst.getOpcode() == ARM::tBKPT ||
5712 Inst.getOpcode() == ARM::BKPT ||
5713 Inst.getOpcode() == ARM::tHLT ||
5714 Inst.getOpcode() == ARM::HLT;
5718 // FIXME: We would really like to be able to tablegen'erate this.
5719 bool ARMAsmParser::validateInstruction(MCInst &Inst,
5720 const OperandVector &Operands) {
5721 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
5722 SMLoc Loc = Operands[0]->getStartLoc();
5724 // Check the IT block state first.
5725 // NOTE: BKPT and HLT instructions have the interesting property of being
5726 // allowed in IT blocks, but not being predicable. They just always execute.
5727 if (inITBlock() && !instIsBreakpoint(Inst)) {
5729 if (ITState.FirstCond)
5730 ITState.FirstCond = false;
5732 Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5733 // The instruction must be predicable.
5734 if (!MCID.isPredicable())
5735 return Error(Loc, "instructions in IT block must be predicable");
5736 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5737 unsigned ITCond = Bit ? ITState.Cond :
5738 ARMCC::getOppositeCondition(ITState.Cond);
5739 if (Cond != ITCond) {
5740 // Find the condition code Operand to get its SMLoc information.
5742 for (unsigned I = 1; I < Operands.size(); ++I)
5743 if (static_cast<ARMOperand &>(*Operands[I]).isCondCode())
5744 CondLoc = Operands[I]->getStartLoc();
5745 return Error(CondLoc, "incorrect condition in IT block; got '" +
5746 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5747 "', but expected '" +
5748 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5750 // Check for non-'al' condition codes outside of the IT block.
5751 } else if (isThumbTwo() && MCID.isPredicable() &&
5752 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5753 ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
5754 Inst.getOpcode() != ARM::t2Bcc)
5755 return Error(Loc, "predicated instructions must be in IT block");
5757 const unsigned Opcode = Inst.getOpcode();
5761 case ARM::LDRD_POST: {
5762 const unsigned RtReg = Inst.getOperand(0).getReg();
5765 if (RtReg == ARM::LR)
5766 return Error(Operands[3]->getStartLoc(),
5769 const unsigned Rt = MRI->getEncodingValue(RtReg);
5770 // Rt must be even-numbered.
5772 return Error(Operands[3]->getStartLoc(),
5773 "Rt must be even-numbered");
5775 // Rt2 must be Rt + 1.
5776 const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5778 return Error(Operands[3]->getStartLoc(),
5779 "destination operands must be sequential");
5781 if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) {
5782 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
5783 // For addressing modes with writeback, the base register needs to be
5784 // different from the destination registers.
5785 if (Rn == Rt || Rn == Rt2)
5786 return Error(Operands[3]->getStartLoc(),
5787 "base register needs to be different from destination "
5794 case ARM::t2LDRD_PRE:
5795 case ARM::t2LDRD_POST: {
5796 // Rt2 must be different from Rt.
5797 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5798 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5800 return Error(Operands[3]->getStartLoc(),
5801 "destination operands can't be identical");
5805 // Rt2 must be Rt + 1.
5806 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5807 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5809 return Error(Operands[3]->getStartLoc(),
5810 "source operands must be sequential");
5814 case ARM::STRD_POST: {
5815 // Rt2 must be Rt + 1.
5816 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5817 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5819 return Error(Operands[3]->getStartLoc(),
5820 "source operands must be sequential");
5823 case ARM::STR_PRE_IMM:
5824 case ARM::STR_PRE_REG:
5825 case ARM::STR_POST_IMM:
5826 case ARM::STR_POST_REG:
5828 case ARM::STRH_POST:
5829 case ARM::STRB_PRE_IMM:
5830 case ARM::STRB_PRE_REG:
5831 case ARM::STRB_POST_IMM:
5832 case ARM::STRB_POST_REG: {
5833 // Rt must be different from Rn.
5834 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5835 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5838 return Error(Operands[3]->getStartLoc(),
5839 "source register and base register can't be identical");
5842 case ARM::LDR_PRE_IMM:
5843 case ARM::LDR_PRE_REG:
5844 case ARM::LDR_POST_IMM:
5845 case ARM::LDR_POST_REG:
5847 case ARM::LDRH_POST:
5848 case ARM::LDRSH_PRE:
5849 case ARM::LDRSH_POST:
5850 case ARM::LDRB_PRE_IMM:
5851 case ARM::LDRB_PRE_REG:
5852 case ARM::LDRB_POST_IMM:
5853 case ARM::LDRB_POST_REG:
5854 case ARM::LDRSB_PRE:
5855 case ARM::LDRSB_POST: {
5856 // Rt must be different from Rn.
5857 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5858 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5861 return Error(Operands[3]->getStartLoc(),
5862 "destination register and base register can't be identical");
5867 // Width must be in range [1, 32-lsb].
5868 unsigned LSB = Inst.getOperand(2).getImm();
5869 unsigned Widthm1 = Inst.getOperand(3).getImm();
5870 if (Widthm1 >= 32 - LSB)
5871 return Error(Operands[5]->getStartLoc(),
5872 "bitfield width must be in range [1,32-lsb]");
5875 // Notionally handles ARM::tLDMIA_UPD too.
5877 // If we're parsing Thumb2, the .w variant is available and handles
5878 // most cases that are normally illegal for a Thumb1 LDM instruction.
5879 // We'll make the transformation in processInstruction() if necessary.
5881 // Thumb LDM instructions are writeback iff the base register is not
5882 // in the register list.
5883 unsigned Rn = Inst.getOperand(0).getReg();
5884 bool HasWritebackToken =
5885 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
5886 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
5887 bool ListContainsBase;
5888 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
5889 return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
5890 "registers must be in range r0-r7");
5891 // If we should have writeback, then there should be a '!' token.
5892 if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
5893 return Error(Operands[2]->getStartLoc(),
5894 "writeback operator '!' expected");
5895 // If we should not have writeback, there must not be a '!'. This is
5896 // true even for the 32-bit wide encodings.
5897 if (ListContainsBase && HasWritebackToken)
5898 return Error(Operands[3]->getStartLoc(),
5899 "writeback operator '!' not allowed when base register "
5900 "in register list");
5904 case ARM::LDMIA_UPD:
5905 case ARM::LDMDB_UPD:
5906 case ARM::LDMIB_UPD:
5907 case ARM::LDMDA_UPD:
5908 // ARM variants loading and updating the same register are only officially
5909 // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
5913 case ARM::t2LDMIA_UPD:
5914 case ARM::t2LDMDB_UPD:
5915 case ARM::t2STMIA_UPD:
5916 case ARM::t2STMDB_UPD: {
5917 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5918 return Error(Operands.back()->getStartLoc(),
5919 "writeback register not allowed in register list");
5922 case ARM::sysLDMIA_UPD:
5923 case ARM::sysLDMDA_UPD:
5924 case ARM::sysLDMDB_UPD:
5925 case ARM::sysLDMIB_UPD:
5926 if (!listContainsReg(Inst, 3, ARM::PC))
5927 return Error(Operands[4]->getStartLoc(),
5928 "writeback register only allowed on system LDM "
5929 "if PC in register-list");
5931 case ARM::sysSTMIA_UPD:
5932 case ARM::sysSTMDA_UPD:
5933 case ARM::sysSTMDB_UPD:
5934 case ARM::sysSTMIB_UPD:
5935 return Error(Operands[2]->getStartLoc(),
5936 "system STM cannot have writeback register");
5938 // The second source operand must be the same register as the destination
5941 // In this case, we must directly check the parsed operands because the
5942 // cvtThumbMultiply() function is written in such a way that it guarantees
5943 // this first statement is always true for the new Inst. Essentially, the
5944 // destination is unconditionally copied into the second source operand
5945 // without checking to see if it matches what we actually parsed.
5946 if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() !=
5947 ((ARMOperand &)*Operands[5]).getReg()) &&
5948 (((ARMOperand &)*Operands[3]).getReg() !=
5949 ((ARMOperand &)*Operands[4]).getReg())) {
5950 return Error(Operands[3]->getStartLoc(),
5951 "destination register must match source register");
5955 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5956 // so only issue a diagnostic for thumb1. The instructions will be
5957 // switched to the t2 encodings in processInstruction() if necessary.
5959 bool ListContainsBase;
5960 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
5962 return Error(Operands[2]->getStartLoc(),
5963 "registers must be in range r0-r7 or pc");
5967 bool ListContainsBase;
5968 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
5970 return Error(Operands[2]->getStartLoc(),
5971 "registers must be in range r0-r7 or lr");
5974 case ARM::tSTMIA_UPD: {
5975 bool ListContainsBase, InvalidLowList;
5976 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
5977 0, ListContainsBase);
5978 if (InvalidLowList && !isThumbTwo())
5979 return Error(Operands[4]->getStartLoc(),
5980 "registers must be in range r0-r7");
5982 // This would be converted to a 32-bit stm, but that's not valid if the
5983 // writeback register is in the list.
5984 if (InvalidLowList && ListContainsBase)
5985 return Error(Operands[4]->getStartLoc(),
5986 "writeback operator '!' not allowed when base register "
5987 "in register list");
5990 case ARM::tADDrSP: {
5991 // If the non-SP source operand and the destination operand are not the
5992 // same, we need thumb2 (for the wide encoding), or we have an error.
5993 if (!isThumbTwo() &&
5994 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5995 return Error(Operands[4]->getStartLoc(),
5996 "source register must be the same as destination");
6000 // Final range checking for Thumb unconditional branch instructions.
6002 if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>())
6003 return Error(Operands[2]->getStartLoc(), "branch target out of range");
6006 int op = (Operands[2]->isImm()) ? 2 : 3;
6007 if (!static_cast<ARMOperand &>(*Operands[op]).isSignedOffset<24, 1>())
6008 return Error(Operands[op]->getStartLoc(), "branch target out of range");
6011 // Final range checking for Thumb conditional branch instructions.
6013 if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>())
6014 return Error(Operands[2]->getStartLoc(), "branch target out of range");
6017 int Op = (Operands[2]->isImm()) ? 2 : 3;
6018 if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>())
6019 return Error(Operands[Op]->getStartLoc(), "branch target out of range");
6024 case ARM::t2MOVTi16:
6026 // We want to avoid misleadingly allowing something like "mov r0, <symbol>"
6027 // especially when we turn it into a movw and the expression <symbol> does
6028 // not have a :lower16: or :upper16 as part of the expression. We don't
6029 // want the behavior of silently truncating, which can be unexpected and
6030 // lead to bugs that are difficult to find since this is an easy mistake
6032 int i = (Operands[3]->isImm()) ? 3 : 4;
6033 ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]);
6034 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm());
6036 const MCExpr *E = dyn_cast<MCExpr>(Op.getImm());
6038 const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E);
6039 if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
6040 ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16))
6043 "immediate expression for mov requires :lower16: or :upper16");
6051 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
6053 default: llvm_unreachable("unexpected opcode!");
6055 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
6056 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
6057 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
6058 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
6059 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
6060 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
6061 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
6062 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
6063 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
6066 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
6067 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
6068 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
6069 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
6070 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
6072 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
6073 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
6074 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
6075 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
6076 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
6078 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
6079 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
6080 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
6081 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
6082 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
6085 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
6086 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
6087 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
6088 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
6089 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
6090 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
6091 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
6092 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
6093 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
6094 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
6095 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
6096 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
6097 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
6098 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
6099 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
6102 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
6103 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6104 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6105 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
6106 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6107 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6108 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
6109 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6110 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6111 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
6112 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6113 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6114 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
6115 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
6116 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
6117 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
6118 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
6119 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
6122 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
6123 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6124 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6125 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
6126 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6127 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
6128 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6129 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6130 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
6131 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6132 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
6133 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
6134 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
6135 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
6136 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
6139 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
6140 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6141 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6142 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
6143 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6144 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6145 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
6146 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6147 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6148 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
6149 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6150 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6151 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
6152 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
6153 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
6154 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
6155 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
6156 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
6160 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
6162 default: llvm_unreachable("unexpected opcode!");
6164 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
6165 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6166 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6167 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
6168 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6169 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6170 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
6171 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
6172 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
6175 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
6176 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6177 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6178 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
6179 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6180 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
6181 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6182 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6183 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
6184 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6185 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
6186 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
6187 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
6188 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
6189 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
6192 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
6193 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6194 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6195 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
6196 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6197 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6198 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
6199 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6200 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6201 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
6202 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6203 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6204 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
6205 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
6206 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
6207 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
6208 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
6209 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
6212 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
6213 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6214 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6215 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
6216 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6217 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
6218 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6219 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6220 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
6221 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6222 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
6223 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
6224 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
6225 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
6226 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
6229 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
6230 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6231 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6232 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
6233 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6234 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6235 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
6236 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6237 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6238 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
6239 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6240 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6241 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
6242 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
6243 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
6244 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
6245 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
6246 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
6249 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
6250 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6251 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6252 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6253 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6254 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
6255 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6256 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6257 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6258 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6259 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
6260 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
6261 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
6262 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
6263 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
6266 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
6267 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6268 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6269 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
6270 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
6271 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6272 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
6273 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6274 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6275 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
6276 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
6277 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6278 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
6279 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
6280 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
6281 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
6282 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
6283 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
6286 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
6287 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6288 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6289 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
6290 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6291 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6292 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
6293 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6294 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6295 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
6296 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6297 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6298 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
6299 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
6300 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
6301 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
6302 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
6303 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
6307 bool ARMAsmParser::processInstruction(MCInst &Inst,
6308 const OperandVector &Operands) {
6309 switch (Inst.getOpcode()) {
6310 // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
6311 case ARM::LDRT_POST:
6312 case ARM::LDRBT_POST: {
6313 const unsigned Opcode =
6314 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
6315 : ARM::LDRBT_POST_IMM;
6317 TmpInst.setOpcode(Opcode);
6318 TmpInst.addOperand(Inst.getOperand(0));
6319 TmpInst.addOperand(Inst.getOperand(1));
6320 TmpInst.addOperand(Inst.getOperand(1));
6321 TmpInst.addOperand(MCOperand::CreateReg(0));
6322 TmpInst.addOperand(MCOperand::CreateImm(0));
6323 TmpInst.addOperand(Inst.getOperand(2));
6324 TmpInst.addOperand(Inst.getOperand(3));
6328 // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
6329 case ARM::STRT_POST:
6330 case ARM::STRBT_POST: {
6331 const unsigned Opcode =
6332 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
6333 : ARM::STRBT_POST_IMM;
6335 TmpInst.setOpcode(Opcode);
6336 TmpInst.addOperand(Inst.getOperand(1));
6337 TmpInst.addOperand(Inst.getOperand(0));
6338 TmpInst.addOperand(Inst.getOperand(1));
6339 TmpInst.addOperand(MCOperand::CreateReg(0));
6340 TmpInst.addOperand(MCOperand::CreateImm(0));
6341 TmpInst.addOperand(Inst.getOperand(2));
6342 TmpInst.addOperand(Inst.getOperand(3));
6346 // Alias for alternate form of 'ADR Rd, #imm' instruction.
6348 if (Inst.getOperand(1).getReg() != ARM::PC ||
6349 Inst.getOperand(5).getReg() != 0)
6352 TmpInst.setOpcode(ARM::ADR);
6353 TmpInst.addOperand(Inst.getOperand(0));
6354 TmpInst.addOperand(Inst.getOperand(2));
6355 TmpInst.addOperand(Inst.getOperand(3));
6356 TmpInst.addOperand(Inst.getOperand(4));
6360 // Aliases for alternate PC+imm syntax of LDR instructions.
6361 case ARM::t2LDRpcrel:
6362 // Select the narrow version if the immediate will fit.
6363 if (Inst.getOperand(1).getImm() > 0 &&
6364 Inst.getOperand(1).getImm() <= 0xff &&
6365 !(static_cast<ARMOperand &>(*Operands[2]).isToken() &&
6366 static_cast<ARMOperand &>(*Operands[2]).getToken() == ".w"))
6367 Inst.setOpcode(ARM::tLDRpci);
6369 Inst.setOpcode(ARM::t2LDRpci);
6371 case ARM::t2LDRBpcrel:
6372 Inst.setOpcode(ARM::t2LDRBpci);
6374 case ARM::t2LDRHpcrel:
6375 Inst.setOpcode(ARM::t2LDRHpci);
6377 case ARM::t2LDRSBpcrel:
6378 Inst.setOpcode(ARM::t2LDRSBpci);
6380 case ARM::t2LDRSHpcrel:
6381 Inst.setOpcode(ARM::t2LDRSHpci);
6383 // Handle NEON VST complex aliases.
6384 case ARM::VST1LNdWB_register_Asm_8:
6385 case ARM::VST1LNdWB_register_Asm_16:
6386 case ARM::VST1LNdWB_register_Asm_32: {
6388 // Shuffle the operands around so the lane index operand is in the
6391 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6392 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6393 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6394 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6395 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6396 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6397 TmpInst.addOperand(Inst.getOperand(1)); // lane
6398 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6399 TmpInst.addOperand(Inst.getOperand(6));
6404 case ARM::VST2LNdWB_register_Asm_8:
6405 case ARM::VST2LNdWB_register_Asm_16:
6406 case ARM::VST2LNdWB_register_Asm_32:
6407 case ARM::VST2LNqWB_register_Asm_16:
6408 case ARM::VST2LNqWB_register_Asm_32: {
6410 // Shuffle the operands around so the lane index operand is in the
6413 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6414 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6415 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6416 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6417 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6418 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6419 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6421 TmpInst.addOperand(Inst.getOperand(1)); // lane
6422 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6423 TmpInst.addOperand(Inst.getOperand(6));
6428 case ARM::VST3LNdWB_register_Asm_8:
6429 case ARM::VST3LNdWB_register_Asm_16:
6430 case ARM::VST3LNdWB_register_Asm_32:
6431 case ARM::VST3LNqWB_register_Asm_16:
6432 case ARM::VST3LNqWB_register_Asm_32: {
6434 // Shuffle the operands around so the lane index operand is in the
6437 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6438 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6439 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6440 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6441 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6442 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6443 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6445 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6447 TmpInst.addOperand(Inst.getOperand(1)); // lane
6448 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6449 TmpInst.addOperand(Inst.getOperand(6));
6454 case ARM::VST4LNdWB_register_Asm_8:
6455 case ARM::VST4LNdWB_register_Asm_16:
6456 case ARM::VST4LNdWB_register_Asm_32:
6457 case ARM::VST4LNqWB_register_Asm_16:
6458 case ARM::VST4LNqWB_register_Asm_32: {
6460 // Shuffle the operands around so the lane index operand is in the
6463 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6464 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6465 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6466 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6467 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6468 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6469 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6471 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6473 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6475 TmpInst.addOperand(Inst.getOperand(1)); // lane
6476 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6477 TmpInst.addOperand(Inst.getOperand(6));
6482 case ARM::VST1LNdWB_fixed_Asm_8:
6483 case ARM::VST1LNdWB_fixed_Asm_16:
6484 case ARM::VST1LNdWB_fixed_Asm_32: {
6486 // Shuffle the operands around so the lane index operand is in the
6489 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6490 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6491 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6492 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6493 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6494 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6495 TmpInst.addOperand(Inst.getOperand(1)); // lane
6496 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6497 TmpInst.addOperand(Inst.getOperand(5));
6502 case ARM::VST2LNdWB_fixed_Asm_8:
6503 case ARM::VST2LNdWB_fixed_Asm_16:
6504 case ARM::VST2LNdWB_fixed_Asm_32:
6505 case ARM::VST2LNqWB_fixed_Asm_16:
6506 case ARM::VST2LNqWB_fixed_Asm_32: {
6508 // Shuffle the operands around so the lane index operand is in the
6511 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6512 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6513 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6514 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6515 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6516 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6517 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6519 TmpInst.addOperand(Inst.getOperand(1)); // lane
6520 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6521 TmpInst.addOperand(Inst.getOperand(5));
6526 case ARM::VST3LNdWB_fixed_Asm_8:
6527 case ARM::VST3LNdWB_fixed_Asm_16:
6528 case ARM::VST3LNdWB_fixed_Asm_32:
6529 case ARM::VST3LNqWB_fixed_Asm_16:
6530 case ARM::VST3LNqWB_fixed_Asm_32: {
6532 // Shuffle the operands around so the lane index operand is in the
6535 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6536 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6537 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6538 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6539 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6540 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6541 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6543 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6545 TmpInst.addOperand(Inst.getOperand(1)); // lane
6546 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6547 TmpInst.addOperand(Inst.getOperand(5));
6552 case ARM::VST4LNdWB_fixed_Asm_8:
6553 case ARM::VST4LNdWB_fixed_Asm_16:
6554 case ARM::VST4LNdWB_fixed_Asm_32:
6555 case ARM::VST4LNqWB_fixed_Asm_16:
6556 case ARM::VST4LNqWB_fixed_Asm_32: {
6558 // Shuffle the operands around so the lane index operand is in the
6561 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6562 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6563 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6564 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6565 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6566 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6567 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6569 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6571 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6573 TmpInst.addOperand(Inst.getOperand(1)); // lane
6574 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6575 TmpInst.addOperand(Inst.getOperand(5));
6580 case ARM::VST1LNdAsm_8:
6581 case ARM::VST1LNdAsm_16:
6582 case ARM::VST1LNdAsm_32: {
6584 // Shuffle the operands around so the lane index operand is in the
6587 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6588 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6589 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6590 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6591 TmpInst.addOperand(Inst.getOperand(1)); // lane
6592 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6593 TmpInst.addOperand(Inst.getOperand(5));
6598 case ARM::VST2LNdAsm_8:
6599 case ARM::VST2LNdAsm_16:
6600 case ARM::VST2LNdAsm_32:
6601 case ARM::VST2LNqAsm_16:
6602 case ARM::VST2LNqAsm_32: {
6604 // Shuffle the operands around so the lane index operand is in the
6607 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6608 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6609 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6610 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6611 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6613 TmpInst.addOperand(Inst.getOperand(1)); // lane
6614 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6615 TmpInst.addOperand(Inst.getOperand(5));
6620 case ARM::VST3LNdAsm_8:
6621 case ARM::VST3LNdAsm_16:
6622 case ARM::VST3LNdAsm_32:
6623 case ARM::VST3LNqAsm_16:
6624 case ARM::VST3LNqAsm_32: {
6626 // Shuffle the operands around so the lane index operand is in the
6629 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6630 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6631 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6632 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6633 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6635 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6637 TmpInst.addOperand(Inst.getOperand(1)); // lane
6638 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6639 TmpInst.addOperand(Inst.getOperand(5));
6644 case ARM::VST4LNdAsm_8:
6645 case ARM::VST4LNdAsm_16:
6646 case ARM::VST4LNdAsm_32:
6647 case ARM::VST4LNqAsm_16:
6648 case ARM::VST4LNqAsm_32: {
6650 // Shuffle the operands around so the lane index operand is in the
6653 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6654 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6655 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6656 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6657 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6659 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6661 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6663 TmpInst.addOperand(Inst.getOperand(1)); // lane
6664 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6665 TmpInst.addOperand(Inst.getOperand(5));
6670 // Handle NEON VLD complex aliases.
6671 case ARM::VLD1LNdWB_register_Asm_8:
6672 case ARM::VLD1LNdWB_register_Asm_16:
6673 case ARM::VLD1LNdWB_register_Asm_32: {
6675 // Shuffle the operands around so the lane index operand is in the
6678 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6679 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6680 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6681 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6682 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6683 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6684 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6685 TmpInst.addOperand(Inst.getOperand(1)); // lane
6686 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6687 TmpInst.addOperand(Inst.getOperand(6));
6692 case ARM::VLD2LNdWB_register_Asm_8:
6693 case ARM::VLD2LNdWB_register_Asm_16:
6694 case ARM::VLD2LNdWB_register_Asm_32:
6695 case ARM::VLD2LNqWB_register_Asm_16:
6696 case ARM::VLD2LNqWB_register_Asm_32: {
6698 // Shuffle the operands around so the lane index operand is in the
6701 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6702 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6703 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6705 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6706 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6707 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6708 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6709 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6710 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6712 TmpInst.addOperand(Inst.getOperand(1)); // lane
6713 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6714 TmpInst.addOperand(Inst.getOperand(6));
6719 case ARM::VLD3LNdWB_register_Asm_8:
6720 case ARM::VLD3LNdWB_register_Asm_16:
6721 case ARM::VLD3LNdWB_register_Asm_32:
6722 case ARM::VLD3LNqWB_register_Asm_16:
6723 case ARM::VLD3LNqWB_register_Asm_32: {
6725 // Shuffle the operands around so the lane index operand is in the
6728 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6729 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6730 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6732 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6734 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6735 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6736 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6737 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6738 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6739 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6741 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6743 TmpInst.addOperand(Inst.getOperand(1)); // lane
6744 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6745 TmpInst.addOperand(Inst.getOperand(6));
6750 case ARM::VLD4LNdWB_register_Asm_8:
6751 case ARM::VLD4LNdWB_register_Asm_16:
6752 case ARM::VLD4LNdWB_register_Asm_32:
6753 case ARM::VLD4LNqWB_register_Asm_16:
6754 case ARM::VLD4LNqWB_register_Asm_32: {
6756 // Shuffle the operands around so the lane index operand is in the
6759 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6760 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6761 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6763 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6765 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6767 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6768 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6769 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6770 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6771 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6772 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6774 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6776 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6778 TmpInst.addOperand(Inst.getOperand(1)); // lane
6779 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6780 TmpInst.addOperand(Inst.getOperand(6));
6785 case ARM::VLD1LNdWB_fixed_Asm_8:
6786 case ARM::VLD1LNdWB_fixed_Asm_16:
6787 case ARM::VLD1LNdWB_fixed_Asm_32: {
6789 // Shuffle the operands around so the lane index operand is in the
6792 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6793 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6794 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6795 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6796 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6797 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6798 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6799 TmpInst.addOperand(Inst.getOperand(1)); // lane
6800 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6801 TmpInst.addOperand(Inst.getOperand(5));
6806 case ARM::VLD2LNdWB_fixed_Asm_8:
6807 case ARM::VLD2LNdWB_fixed_Asm_16:
6808 case ARM::VLD2LNdWB_fixed_Asm_32:
6809 case ARM::VLD2LNqWB_fixed_Asm_16:
6810 case ARM::VLD2LNqWB_fixed_Asm_32: {
6812 // Shuffle the operands around so the lane index operand is in the
6815 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6816 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6817 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6819 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6820 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6821 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6822 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6823 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6824 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6826 TmpInst.addOperand(Inst.getOperand(1)); // lane
6827 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6828 TmpInst.addOperand(Inst.getOperand(5));
6833 case ARM::VLD3LNdWB_fixed_Asm_8:
6834 case ARM::VLD3LNdWB_fixed_Asm_16:
6835 case ARM::VLD3LNdWB_fixed_Asm_32:
6836 case ARM::VLD3LNqWB_fixed_Asm_16:
6837 case ARM::VLD3LNqWB_fixed_Asm_32: {
6839 // Shuffle the operands around so the lane index operand is in the
6842 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6843 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6844 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6846 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6848 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6849 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6850 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6851 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6852 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6853 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6855 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6857 TmpInst.addOperand(Inst.getOperand(1)); // lane
6858 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6859 TmpInst.addOperand(Inst.getOperand(5));
6864 case ARM::VLD4LNdWB_fixed_Asm_8:
6865 case ARM::VLD4LNdWB_fixed_Asm_16:
6866 case ARM::VLD4LNdWB_fixed_Asm_32:
6867 case ARM::VLD4LNqWB_fixed_Asm_16:
6868 case ARM::VLD4LNqWB_fixed_Asm_32: {
6870 // Shuffle the operands around so the lane index operand is in the
6873 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6874 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6875 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6877 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6879 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6881 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6882 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6883 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6884 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6885 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6886 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6888 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6890 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6892 TmpInst.addOperand(Inst.getOperand(1)); // lane
6893 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6894 TmpInst.addOperand(Inst.getOperand(5));
6899 case ARM::VLD1LNdAsm_8:
6900 case ARM::VLD1LNdAsm_16:
6901 case ARM::VLD1LNdAsm_32: {
6903 // Shuffle the operands around so the lane index operand is in the
6906 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6907 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6908 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6909 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6910 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6911 TmpInst.addOperand(Inst.getOperand(1)); // lane
6912 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6913 TmpInst.addOperand(Inst.getOperand(5));
6918 case ARM::VLD2LNdAsm_8:
6919 case ARM::VLD2LNdAsm_16:
6920 case ARM::VLD2LNdAsm_32:
6921 case ARM::VLD2LNqAsm_16:
6922 case ARM::VLD2LNqAsm_32: {
6924 // Shuffle the operands around so the lane index operand is in the
6927 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6928 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6929 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6931 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6932 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6933 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6934 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6936 TmpInst.addOperand(Inst.getOperand(1)); // lane
6937 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6938 TmpInst.addOperand(Inst.getOperand(5));
6943 case ARM::VLD3LNdAsm_8:
6944 case ARM::VLD3LNdAsm_16:
6945 case ARM::VLD3LNdAsm_32:
6946 case ARM::VLD3LNqAsm_16:
6947 case ARM::VLD3LNqAsm_32: {
6949 // Shuffle the operands around so the lane index operand is in the
6952 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6953 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6954 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6956 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6958 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6959 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6960 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6961 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6963 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6965 TmpInst.addOperand(Inst.getOperand(1)); // lane
6966 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6967 TmpInst.addOperand(Inst.getOperand(5));
6972 case ARM::VLD4LNdAsm_8:
6973 case ARM::VLD4LNdAsm_16:
6974 case ARM::VLD4LNdAsm_32:
6975 case ARM::VLD4LNqAsm_16:
6976 case ARM::VLD4LNqAsm_32: {
6978 // Shuffle the operands around so the lane index operand is in the
6981 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6982 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6983 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6985 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6987 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6989 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6990 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6991 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6992 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6994 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6996 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6998 TmpInst.addOperand(Inst.getOperand(1)); // lane
6999 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7000 TmpInst.addOperand(Inst.getOperand(5));
7005 // VLD3DUP single 3-element structure to all lanes instructions.
7006 case ARM::VLD3DUPdAsm_8:
7007 case ARM::VLD3DUPdAsm_16:
7008 case ARM::VLD3DUPdAsm_32:
7009 case ARM::VLD3DUPqAsm_8:
7010 case ARM::VLD3DUPqAsm_16:
7011 case ARM::VLD3DUPqAsm_32: {
7014 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7015 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7016 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7018 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7020 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7021 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7022 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7023 TmpInst.addOperand(Inst.getOperand(4));
7028 case ARM::VLD3DUPdWB_fixed_Asm_8:
7029 case ARM::VLD3DUPdWB_fixed_Asm_16:
7030 case ARM::VLD3DUPdWB_fixed_Asm_32:
7031 case ARM::VLD3DUPqWB_fixed_Asm_8:
7032 case ARM::VLD3DUPqWB_fixed_Asm_16:
7033 case ARM::VLD3DUPqWB_fixed_Asm_32: {
7036 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7037 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7038 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7040 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7042 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7043 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7044 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7045 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7046 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7047 TmpInst.addOperand(Inst.getOperand(4));
7052 case ARM::VLD3DUPdWB_register_Asm_8:
7053 case ARM::VLD3DUPdWB_register_Asm_16:
7054 case ARM::VLD3DUPdWB_register_Asm_32:
7055 case ARM::VLD3DUPqWB_register_Asm_8:
7056 case ARM::VLD3DUPqWB_register_Asm_16:
7057 case ARM::VLD3DUPqWB_register_Asm_32: {
7060 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7061 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7062 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7064 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7066 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7067 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7068 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7069 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7070 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7071 TmpInst.addOperand(Inst.getOperand(5));
7076 // VLD3 multiple 3-element structure instructions.
7077 case ARM::VLD3dAsm_8:
7078 case ARM::VLD3dAsm_16:
7079 case ARM::VLD3dAsm_32:
7080 case ARM::VLD3qAsm_8:
7081 case ARM::VLD3qAsm_16:
7082 case ARM::VLD3qAsm_32: {
7085 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7086 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7087 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7089 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7091 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7092 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7093 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7094 TmpInst.addOperand(Inst.getOperand(4));
7099 case ARM::VLD3dWB_fixed_Asm_8:
7100 case ARM::VLD3dWB_fixed_Asm_16:
7101 case ARM::VLD3dWB_fixed_Asm_32:
7102 case ARM::VLD3qWB_fixed_Asm_8:
7103 case ARM::VLD3qWB_fixed_Asm_16:
7104 case ARM::VLD3qWB_fixed_Asm_32: {
7107 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7108 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7109 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7111 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7113 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7114 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7115 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7116 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7117 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7118 TmpInst.addOperand(Inst.getOperand(4));
7123 case ARM::VLD3dWB_register_Asm_8:
7124 case ARM::VLD3dWB_register_Asm_16:
7125 case ARM::VLD3dWB_register_Asm_32:
7126 case ARM::VLD3qWB_register_Asm_8:
7127 case ARM::VLD3qWB_register_Asm_16:
7128 case ARM::VLD3qWB_register_Asm_32: {
7131 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7132 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7133 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7135 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7137 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7138 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7139 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7140 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7141 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7142 TmpInst.addOperand(Inst.getOperand(5));
7147 // VLD4DUP single 3-element structure to all lanes instructions.
7148 case ARM::VLD4DUPdAsm_8:
7149 case ARM::VLD4DUPdAsm_16:
7150 case ARM::VLD4DUPdAsm_32:
7151 case ARM::VLD4DUPqAsm_8:
7152 case ARM::VLD4DUPqAsm_16:
7153 case ARM::VLD4DUPqAsm_32: {
7156 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7157 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7158 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7160 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7162 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7164 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7165 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7166 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7167 TmpInst.addOperand(Inst.getOperand(4));
7172 case ARM::VLD4DUPdWB_fixed_Asm_8:
7173 case ARM::VLD4DUPdWB_fixed_Asm_16:
7174 case ARM::VLD4DUPdWB_fixed_Asm_32:
7175 case ARM::VLD4DUPqWB_fixed_Asm_8:
7176 case ARM::VLD4DUPqWB_fixed_Asm_16:
7177 case ARM::VLD4DUPqWB_fixed_Asm_32: {
7180 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7181 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7182 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7184 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7186 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7188 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7189 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7190 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7191 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7192 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7193 TmpInst.addOperand(Inst.getOperand(4));
7198 case ARM::VLD4DUPdWB_register_Asm_8:
7199 case ARM::VLD4DUPdWB_register_Asm_16:
7200 case ARM::VLD4DUPdWB_register_Asm_32:
7201 case ARM::VLD4DUPqWB_register_Asm_8:
7202 case ARM::VLD4DUPqWB_register_Asm_16:
7203 case ARM::VLD4DUPqWB_register_Asm_32: {
7206 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7207 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7208 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7210 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7212 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7214 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7215 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7216 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7217 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7218 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7219 TmpInst.addOperand(Inst.getOperand(5));
7224 // VLD4 multiple 4-element structure instructions.
7225 case ARM::VLD4dAsm_8:
7226 case ARM::VLD4dAsm_16:
7227 case ARM::VLD4dAsm_32:
7228 case ARM::VLD4qAsm_8:
7229 case ARM::VLD4qAsm_16:
7230 case ARM::VLD4qAsm_32: {
7233 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7234 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7235 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7237 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7239 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7241 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7242 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7243 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7244 TmpInst.addOperand(Inst.getOperand(4));
7249 case ARM::VLD4dWB_fixed_Asm_8:
7250 case ARM::VLD4dWB_fixed_Asm_16:
7251 case ARM::VLD4dWB_fixed_Asm_32:
7252 case ARM::VLD4qWB_fixed_Asm_8:
7253 case ARM::VLD4qWB_fixed_Asm_16:
7254 case ARM::VLD4qWB_fixed_Asm_32: {
7257 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7258 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7259 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7261 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7263 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7265 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7266 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7267 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7268 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7269 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7270 TmpInst.addOperand(Inst.getOperand(4));
7275 case ARM::VLD4dWB_register_Asm_8:
7276 case ARM::VLD4dWB_register_Asm_16:
7277 case ARM::VLD4dWB_register_Asm_32:
7278 case ARM::VLD4qWB_register_Asm_8:
7279 case ARM::VLD4qWB_register_Asm_16:
7280 case ARM::VLD4qWB_register_Asm_32: {
7283 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7284 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7285 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7287 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7289 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7291 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7292 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7293 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7294 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7295 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7296 TmpInst.addOperand(Inst.getOperand(5));
7301 // VST3 multiple 3-element structure instructions.
7302 case ARM::VST3dAsm_8:
7303 case ARM::VST3dAsm_16:
7304 case ARM::VST3dAsm_32:
7305 case ARM::VST3qAsm_8:
7306 case ARM::VST3qAsm_16:
7307 case ARM::VST3qAsm_32: {
7310 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7311 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7312 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7313 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7314 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7316 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7318 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7319 TmpInst.addOperand(Inst.getOperand(4));
7324 case ARM::VST3dWB_fixed_Asm_8:
7325 case ARM::VST3dWB_fixed_Asm_16:
7326 case ARM::VST3dWB_fixed_Asm_32:
7327 case ARM::VST3qWB_fixed_Asm_8:
7328 case ARM::VST3qWB_fixed_Asm_16:
7329 case ARM::VST3qWB_fixed_Asm_32: {
7332 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7333 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7334 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7335 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7336 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7337 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7338 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7340 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7342 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7343 TmpInst.addOperand(Inst.getOperand(4));
7348 case ARM::VST3dWB_register_Asm_8:
7349 case ARM::VST3dWB_register_Asm_16:
7350 case ARM::VST3dWB_register_Asm_32:
7351 case ARM::VST3qWB_register_Asm_8:
7352 case ARM::VST3qWB_register_Asm_16:
7353 case ARM::VST3qWB_register_Asm_32: {
7356 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7357 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7358 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7359 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7360 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7361 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7362 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7364 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7366 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7367 TmpInst.addOperand(Inst.getOperand(5));
7372 // VST4 multiple 3-element structure instructions.
7373 case ARM::VST4dAsm_8:
7374 case ARM::VST4dAsm_16:
7375 case ARM::VST4dAsm_32:
7376 case ARM::VST4qAsm_8:
7377 case ARM::VST4qAsm_16:
7378 case ARM::VST4qAsm_32: {
7381 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7382 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7383 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7384 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7385 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7387 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7389 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7391 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7392 TmpInst.addOperand(Inst.getOperand(4));
7397 case ARM::VST4dWB_fixed_Asm_8:
7398 case ARM::VST4dWB_fixed_Asm_16:
7399 case ARM::VST4dWB_fixed_Asm_32:
7400 case ARM::VST4qWB_fixed_Asm_8:
7401 case ARM::VST4qWB_fixed_Asm_16:
7402 case ARM::VST4qWB_fixed_Asm_32: {
7405 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7406 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7407 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7408 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7409 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7410 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7411 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7413 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7415 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7417 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7418 TmpInst.addOperand(Inst.getOperand(4));
7423 case ARM::VST4dWB_register_Asm_8:
7424 case ARM::VST4dWB_register_Asm_16:
7425 case ARM::VST4dWB_register_Asm_32:
7426 case ARM::VST4qWB_register_Asm_8:
7427 case ARM::VST4qWB_register_Asm_16:
7428 case ARM::VST4qWB_register_Asm_32: {
7431 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7432 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7433 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7434 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7435 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7436 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7437 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7439 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7441 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7443 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7444 TmpInst.addOperand(Inst.getOperand(5));
7449 // Handle encoding choice for the shift-immediate instructions.
7452 case ARM::t2ASRri: {
7453 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7454 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7455 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
7456 !(static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7457 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w")) {
7459 switch (Inst.getOpcode()) {
7460 default: llvm_unreachable("unexpected opcode");
7461 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
7462 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
7463 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
7465 // The Thumb1 operands aren't in the same order. Awesome, eh?
7467 TmpInst.setOpcode(NewOpc);
7468 TmpInst.addOperand(Inst.getOperand(0));
7469 TmpInst.addOperand(Inst.getOperand(5));
7470 TmpInst.addOperand(Inst.getOperand(1));
7471 TmpInst.addOperand(Inst.getOperand(2));
7472 TmpInst.addOperand(Inst.getOperand(3));
7473 TmpInst.addOperand(Inst.getOperand(4));
7480 // Handle the Thumb2 mode MOV complex aliases.
7482 case ARM::t2MOVSsr: {
7483 // Which instruction to expand to depends on the CCOut operand and
7484 // whether we're in an IT block if the register operands are low
7486 bool isNarrow = false;
7487 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7488 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7489 isARMLowRegister(Inst.getOperand(2).getReg()) &&
7490 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7491 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
7495 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
7496 default: llvm_unreachable("unexpected opcode!");
7497 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7498 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7499 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7500 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
7502 TmpInst.setOpcode(newOpc);
7503 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7505 TmpInst.addOperand(MCOperand::CreateReg(
7506 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7507 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7508 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7509 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7510 TmpInst.addOperand(Inst.getOperand(5));
7512 TmpInst.addOperand(MCOperand::CreateReg(
7513 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7518 case ARM::t2MOVSsi: {
7519 // Which instruction to expand to depends on the CCOut operand and
7520 // whether we're in an IT block if the register operands are low
7522 bool isNarrow = false;
7523 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7524 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7525 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
7529 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
7530 default: llvm_unreachable("unexpected opcode!");
7531 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7532 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7533 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7534 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7535 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7537 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
7538 if (Amount == 32) Amount = 0;
7539 TmpInst.setOpcode(newOpc);
7540 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7542 TmpInst.addOperand(MCOperand::CreateReg(
7543 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7544 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7545 if (newOpc != ARM::t2RRX)
7546 TmpInst.addOperand(MCOperand::CreateImm(Amount));
7547 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7548 TmpInst.addOperand(Inst.getOperand(4));
7550 TmpInst.addOperand(MCOperand::CreateReg(
7551 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7555 // Handle the ARM mode MOV complex aliases.
7560 ARM_AM::ShiftOpc ShiftTy;
7561 switch(Inst.getOpcode()) {
7562 default: llvm_unreachable("unexpected opcode!");
7563 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
7564 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
7565 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
7566 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
7568 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
7570 TmpInst.setOpcode(ARM::MOVsr);
7571 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7572 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7573 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7574 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7575 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7576 TmpInst.addOperand(Inst.getOperand(4));
7577 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7585 ARM_AM::ShiftOpc ShiftTy;
7586 switch(Inst.getOpcode()) {
7587 default: llvm_unreachable("unexpected opcode!");
7588 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
7589 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
7590 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7591 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
7593 // A shift by zero is a plain MOVr, not a MOVsi.
7594 unsigned Amt = Inst.getOperand(2).getImm();
7595 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
7596 // A shift by 32 should be encoded as 0 when permitted
7597 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
7599 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
7601 TmpInst.setOpcode(Opc);
7602 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7603 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7604 if (Opc == ARM::MOVsi)
7605 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7606 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7607 TmpInst.addOperand(Inst.getOperand(4));
7608 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7613 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
7615 TmpInst.setOpcode(ARM::MOVsi);
7616 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7617 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7618 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7619 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7620 TmpInst.addOperand(Inst.getOperand(3));
7621 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7625 case ARM::t2LDMIA_UPD: {
7626 // If this is a load of a single register, then we should use
7627 // a post-indexed LDR instruction instead, per the ARM ARM.
7628 if (Inst.getNumOperands() != 5)
7631 TmpInst.setOpcode(ARM::t2LDR_POST);
7632 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7633 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7634 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7635 TmpInst.addOperand(MCOperand::CreateImm(4));
7636 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7637 TmpInst.addOperand(Inst.getOperand(3));
7641 case ARM::t2STMDB_UPD: {
7642 // If this is a store of a single register, then we should use
7643 // a pre-indexed STR instruction instead, per the ARM ARM.
7644 if (Inst.getNumOperands() != 5)
7647 TmpInst.setOpcode(ARM::t2STR_PRE);
7648 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7649 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7650 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7651 TmpInst.addOperand(MCOperand::CreateImm(-4));
7652 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7653 TmpInst.addOperand(Inst.getOperand(3));
7657 case ARM::LDMIA_UPD:
7658 // If this is a load of a single register via a 'pop', then we should use
7659 // a post-indexed LDR instruction instead, per the ARM ARM.
7660 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" &&
7661 Inst.getNumOperands() == 5) {
7663 TmpInst.setOpcode(ARM::LDR_POST_IMM);
7664 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7665 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7666 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7667 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
7668 TmpInst.addOperand(MCOperand::CreateImm(4));
7669 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7670 TmpInst.addOperand(Inst.getOperand(3));
7675 case ARM::STMDB_UPD:
7676 // If this is a store of a single register via a 'push', then we should use
7677 // a pre-indexed STR instruction instead, per the ARM ARM.
7678 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" &&
7679 Inst.getNumOperands() == 5) {
7681 TmpInst.setOpcode(ARM::STR_PRE_IMM);
7682 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7683 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7684 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7685 TmpInst.addOperand(MCOperand::CreateImm(-4));
7686 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7687 TmpInst.addOperand(Inst.getOperand(3));
7691 case ARM::t2ADDri12:
7692 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7693 // mnemonic was used (not "addw"), encoding T3 is preferred.
7694 if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "add" ||
7695 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7697 Inst.setOpcode(ARM::t2ADDri);
7698 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7700 case ARM::t2SUBri12:
7701 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7702 // mnemonic was used (not "subw"), encoding T3 is preferred.
7703 if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "sub" ||
7704 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7706 Inst.setOpcode(ARM::t2SUBri);
7707 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7710 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7711 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7712 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7713 // to encoding T1 if <Rd> is omitted."
7714 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7715 Inst.setOpcode(ARM::tADDi3);
7720 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7721 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7722 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7723 // to encoding T1 if <Rd> is omitted."
7724 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7725 Inst.setOpcode(ARM::tSUBi3);
7730 case ARM::t2SUBri: {
7731 // If the destination and first source operand are the same, and
7732 // the flags are compatible with the current IT status, use encoding T2
7733 // instead of T3. For compatibility with the system 'as'. Make sure the
7734 // wide encoding wasn't explicit.
7735 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7736 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7737 (unsigned)Inst.getOperand(2).getImm() > 255 ||
7738 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7739 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7740 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7741 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
7744 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7745 ARM::tADDi8 : ARM::tSUBi8);
7746 TmpInst.addOperand(Inst.getOperand(0));
7747 TmpInst.addOperand(Inst.getOperand(5));
7748 TmpInst.addOperand(Inst.getOperand(0));
7749 TmpInst.addOperand(Inst.getOperand(2));
7750 TmpInst.addOperand(Inst.getOperand(3));
7751 TmpInst.addOperand(Inst.getOperand(4));
7755 case ARM::t2ADDrr: {
7756 // If the destination and first source operand are the same, and
7757 // there's no setting of the flags, use encoding T2 instead of T3.
7758 // Note that this is only for ADD, not SUB. This mirrors the system
7759 // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7760 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7761 Inst.getOperand(5).getReg() != 0 ||
7762 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7763 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
7766 TmpInst.setOpcode(ARM::tADDhirr);
7767 TmpInst.addOperand(Inst.getOperand(0));
7768 TmpInst.addOperand(Inst.getOperand(0));
7769 TmpInst.addOperand(Inst.getOperand(2));
7770 TmpInst.addOperand(Inst.getOperand(3));
7771 TmpInst.addOperand(Inst.getOperand(4));
7775 case ARM::tADDrSP: {
7776 // If the non-SP source operand and the destination operand are not the
7777 // same, we need to use the 32-bit encoding if it's available.
7778 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7779 Inst.setOpcode(ARM::t2ADDrr);
7780 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7786 // A Thumb conditional branch outside of an IT block is a tBcc.
7787 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7788 Inst.setOpcode(ARM::tBcc);
7793 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7794 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7795 Inst.setOpcode(ARM::t2Bcc);
7800 // If the conditional is AL or we're in an IT block, we really want t2B.
7801 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7802 Inst.setOpcode(ARM::t2B);
7807 // If the conditional is AL, we really want tB.
7808 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7809 Inst.setOpcode(ARM::tB);
7814 // If the register list contains any high registers, or if the writeback
7815 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7816 // instead if we're in Thumb2. Otherwise, this should have generated
7817 // an error in validateInstruction().
7818 unsigned Rn = Inst.getOperand(0).getReg();
7819 bool hasWritebackToken =
7820 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7821 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
7822 bool listContainsBase;
7823 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7824 (!listContainsBase && !hasWritebackToken) ||
7825 (listContainsBase && hasWritebackToken)) {
7826 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7827 assert (isThumbTwo());
7828 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7829 // If we're switching to the updating version, we need to insert
7830 // the writeback tied operand.
7831 if (hasWritebackToken)
7832 Inst.insert(Inst.begin(),
7833 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7838 case ARM::tSTMIA_UPD: {
7839 // If the register list contains any high registers, we need to use
7840 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7841 // should have generated an error in validateInstruction().
7842 unsigned Rn = Inst.getOperand(0).getReg();
7843 bool listContainsBase;
7844 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7845 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7846 assert (isThumbTwo());
7847 Inst.setOpcode(ARM::t2STMIA_UPD);
7853 bool listContainsBase;
7854 // If the register list contains any high registers, we need to use
7855 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7856 // should have generated an error in validateInstruction().
7857 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7859 assert (isThumbTwo());
7860 Inst.setOpcode(ARM::t2LDMIA_UPD);
7861 // Add the base register and writeback operands.
7862 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7863 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7867 bool listContainsBase;
7868 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7870 assert (isThumbTwo());
7871 Inst.setOpcode(ARM::t2STMDB_UPD);
7872 // Add the base register and writeback operands.
7873 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7874 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7878 // If we can use the 16-bit encoding and the user didn't explicitly
7879 // request the 32-bit variant, transform it here.
7880 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7881 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7882 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7883 Inst.getOperand(4).getReg() == ARM::CPSR) ||
7884 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7885 (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
7886 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
7887 // The operands aren't in the same order for tMOVi8...
7889 TmpInst.setOpcode(ARM::tMOVi8);
7890 TmpInst.addOperand(Inst.getOperand(0));
7891 TmpInst.addOperand(Inst.getOperand(4));
7892 TmpInst.addOperand(Inst.getOperand(1));
7893 TmpInst.addOperand(Inst.getOperand(2));
7894 TmpInst.addOperand(Inst.getOperand(3));
7901 // If we can use the 16-bit encoding and the user didn't explicitly
7902 // request the 32-bit variant, transform it here.
7903 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7904 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7905 Inst.getOperand(2).getImm() == ARMCC::AL &&
7906 Inst.getOperand(4).getReg() == ARM::CPSR &&
7907 (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
7908 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
7909 // The operands aren't the same for tMOV[S]r... (no cc_out)
7911 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7912 TmpInst.addOperand(Inst.getOperand(0));
7913 TmpInst.addOperand(Inst.getOperand(1));
7914 TmpInst.addOperand(Inst.getOperand(2));
7915 TmpInst.addOperand(Inst.getOperand(3));
7925 // If we can use the 16-bit encoding and the user didn't explicitly
7926 // request the 32-bit variant, transform it here.
7927 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7928 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7929 Inst.getOperand(2).getImm() == 0 &&
7930 (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
7931 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
7933 switch (Inst.getOpcode()) {
7934 default: llvm_unreachable("Illegal opcode!");
7935 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7936 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7937 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7938 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7940 // The operands aren't the same for thumb1 (no rotate operand).
7942 TmpInst.setOpcode(NewOpc);
7943 TmpInst.addOperand(Inst.getOperand(0));
7944 TmpInst.addOperand(Inst.getOperand(1));
7945 TmpInst.addOperand(Inst.getOperand(3));
7946 TmpInst.addOperand(Inst.getOperand(4));
7953 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7954 // rrx shifts and asr/lsr of #32 is encoded as 0
7955 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7957 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7958 // Shifting by zero is accepted as a vanilla 'MOVr'
7960 TmpInst.setOpcode(ARM::MOVr);
7961 TmpInst.addOperand(Inst.getOperand(0));
7962 TmpInst.addOperand(Inst.getOperand(1));
7963 TmpInst.addOperand(Inst.getOperand(3));
7964 TmpInst.addOperand(Inst.getOperand(4));
7965 TmpInst.addOperand(Inst.getOperand(5));
7978 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7979 if (SOpc == ARM_AM::rrx) return false;
7980 switch (Inst.getOpcode()) {
7981 default: llvm_unreachable("unexpected opcode!");
7982 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7983 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7984 case ARM::EORrsi: newOpc = ARM::EORrr; break;
7985 case ARM::BICrsi: newOpc = ARM::BICrr; break;
7986 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7987 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7989 // If the shift is by zero, use the non-shifted instruction definition.
7990 // The exception is for right shifts, where 0 == 32
7991 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7992 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7994 TmpInst.setOpcode(newOpc);
7995 TmpInst.addOperand(Inst.getOperand(0));
7996 TmpInst.addOperand(Inst.getOperand(1));
7997 TmpInst.addOperand(Inst.getOperand(2));
7998 TmpInst.addOperand(Inst.getOperand(4));
7999 TmpInst.addOperand(Inst.getOperand(5));
8000 TmpInst.addOperand(Inst.getOperand(6));
8008 // The mask bits for all but the first condition are represented as
8009 // the low bit of the condition code value implies 't'. We currently
8010 // always have 1 implies 't', so XOR toggle the bits if the low bit
8011 // of the condition code is zero.
8012 MCOperand &MO = Inst.getOperand(1);
8013 unsigned Mask = MO.getImm();
8014 unsigned OrigMask = Mask;
8015 unsigned TZ = countTrailingZeros(Mask);
8016 if ((Inst.getOperand(0).getImm() & 1) == 0) {
8017 assert(Mask && TZ <= 3 && "illegal IT mask value!");
8018 Mask ^= (0xE << TZ) & 0xF;
8022 // Set up the IT block state according to the IT instruction we just
8024 assert(!inITBlock() && "nested IT blocks?!");
8025 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
8026 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
8027 ITState.CurPosition = 0;
8028 ITState.FirstCond = true;
8038 // Assemblers should use the narrow encodings of these instructions when permissible.
8039 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
8040 isARMLowRegister(Inst.getOperand(2).getReg())) &&
8041 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
8042 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
8043 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
8044 (!static_cast<ARMOperand &>(*Operands[3]).isToken() ||
8045 !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower(
8048 switch (Inst.getOpcode()) {
8049 default: llvm_unreachable("unexpected opcode");
8050 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
8051 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
8052 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
8053 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
8054 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
8055 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
8058 TmpInst.setOpcode(NewOpc);
8059 TmpInst.addOperand(Inst.getOperand(0));
8060 TmpInst.addOperand(Inst.getOperand(5));
8061 TmpInst.addOperand(Inst.getOperand(1));
8062 TmpInst.addOperand(Inst.getOperand(2));
8063 TmpInst.addOperand(Inst.getOperand(3));
8064 TmpInst.addOperand(Inst.getOperand(4));
8075 // Assemblers should use the narrow encodings of these instructions when permissible.
8076 // These instructions are special in that they are commutable, so shorter encodings
8077 // are available more often.
8078 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
8079 isARMLowRegister(Inst.getOperand(2).getReg())) &&
8080 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
8081 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
8082 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
8083 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
8084 (!static_cast<ARMOperand &>(*Operands[3]).isToken() ||
8085 !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower(
8088 switch (Inst.getOpcode()) {
8089 default: llvm_unreachable("unexpected opcode");
8090 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
8091 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
8092 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
8093 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
8096 TmpInst.setOpcode(NewOpc);
8097 TmpInst.addOperand(Inst.getOperand(0));
8098 TmpInst.addOperand(Inst.getOperand(5));
8099 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
8100 TmpInst.addOperand(Inst.getOperand(1));
8101 TmpInst.addOperand(Inst.getOperand(2));
8103 TmpInst.addOperand(Inst.getOperand(2));
8104 TmpInst.addOperand(Inst.getOperand(1));
8106 TmpInst.addOperand(Inst.getOperand(3));
8107 TmpInst.addOperand(Inst.getOperand(4));
8117 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
8118 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
8119 // suffix depending on whether they're in an IT block or not.
8120 unsigned Opc = Inst.getOpcode();
8121 const MCInstrDesc &MCID = MII.get(Opc);
8122 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
8123 assert(MCID.hasOptionalDef() &&
8124 "optionally flag setting instruction missing optional def operand");
8125 assert(MCID.NumOperands == Inst.getNumOperands() &&
8126 "operand count mismatch!");
8127 // Find the optional-def operand (cc_out).
8130 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
8133 // If we're parsing Thumb1, reject it completely.
8134 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
8135 return Match_MnemonicFail;
8136 // If we're parsing Thumb2, which form is legal depends on whether we're
8138 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
8140 return Match_RequiresITBlock;
8141 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
8143 return Match_RequiresNotITBlock;
8145 // Some high-register supporting Thumb1 encodings only allow both registers
8146 // to be from r0-r7 when in Thumb2.
8147 else if (Opc == ARM::tADDhirr && isThumbOne() &&
8148 isARMLowRegister(Inst.getOperand(1).getReg()) &&
8149 isARMLowRegister(Inst.getOperand(2).getReg()))
8150 return Match_RequiresThumb2;
8151 // Others only require ARMv6 or later.
8152 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
8153 isARMLowRegister(Inst.getOperand(0).getReg()) &&
8154 isARMLowRegister(Inst.getOperand(1).getReg()))
8155 return Match_RequiresV6;
8156 return Match_Success;
8160 template <> inline bool IsCPSRDead<MCInst>(MCInst *Instr) {
8161 return true; // In an assembly source, no need to second-guess
8165 static const char *getSubtargetFeatureName(uint64_t Val);
8166 bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
8167 OperandVector &Operands,
8168 MCStreamer &Out, uint64_t &ErrorInfo,
8169 bool MatchingInlineAsm) {
8171 unsigned MatchResult;
8173 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
8175 switch (MatchResult) {
8178 // Context sensitive operand constraints aren't handled by the matcher,
8179 // so check them here.
8180 if (validateInstruction(Inst, Operands)) {
8181 // Still progress the IT block, otherwise one wrong condition causes
8182 // nasty cascading errors.
8183 forwardITPosition();
8187 { // processInstruction() updates inITBlock state, we need to save it away
8188 bool wasInITBlock = inITBlock();
8190 // Some instructions need post-processing to, for example, tweak which
8191 // encoding is selected. Loop on it while changes happen so the
8192 // individual transformations can chain off each other. E.g.,
8193 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
8194 while (processInstruction(Inst, Operands))
8197 // Only after the instruction is fully processed, we can validate it
8198 if (wasInITBlock && hasV8Ops() && isThumb() &&
8199 !isV8EligibleForIT(&Inst)) {
8200 Warning(IDLoc, "deprecated instruction in IT block");
8204 // Only move forward at the very end so that everything in validate
8205 // and process gets a consistent answer about whether we're in an IT
8207 forwardITPosition();
8209 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
8210 // doesn't actually encode.
8211 if (Inst.getOpcode() == ARM::ITasm)
8215 Out.EmitInstruction(Inst, STI);
8217 case Match_MissingFeature: {
8218 assert(ErrorInfo && "Unknown missing feature!");
8219 // Special case the error message for the very common case where only
8220 // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
8221 std::string Msg = "instruction requires:";
8223 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
8224 if (ErrorInfo & Mask) {
8226 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
8230 return Error(IDLoc, Msg);
8232 case Match_InvalidOperand: {
8233 SMLoc ErrorLoc = IDLoc;
8234 if (ErrorInfo != ~0ULL) {
8235 if (ErrorInfo >= Operands.size())
8236 return Error(IDLoc, "too few operands for instruction");
8238 ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8239 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8242 return Error(ErrorLoc, "invalid operand for instruction");
8244 case Match_MnemonicFail:
8245 return Error(IDLoc, "invalid instruction",
8246 ((ARMOperand &)*Operands[0]).getLocRange());
8247 case Match_RequiresNotITBlock:
8248 return Error(IDLoc, "flag setting instruction only valid outside IT block");
8249 case Match_RequiresITBlock:
8250 return Error(IDLoc, "instruction only valid inside IT block");
8251 case Match_RequiresV6:
8252 return Error(IDLoc, "instruction variant requires ARMv6 or later");
8253 case Match_RequiresThumb2:
8254 return Error(IDLoc, "instruction variant requires Thumb2");
8255 case Match_ImmRange0_15: {
8256 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8257 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8258 return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
8260 case Match_ImmRange0_239: {
8261 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8262 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8263 return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
8265 case Match_AlignedMemoryRequiresNone:
8266 case Match_DupAlignedMemoryRequiresNone:
8267 case Match_AlignedMemoryRequires16:
8268 case Match_DupAlignedMemoryRequires16:
8269 case Match_AlignedMemoryRequires32:
8270 case Match_DupAlignedMemoryRequires32:
8271 case Match_AlignedMemoryRequires64:
8272 case Match_DupAlignedMemoryRequires64:
8273 case Match_AlignedMemoryRequires64or128:
8274 case Match_DupAlignedMemoryRequires64or128:
8275 case Match_AlignedMemoryRequires64or128or256:
8277 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getAlignmentLoc();
8278 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8279 switch (MatchResult) {
8281 llvm_unreachable("Missing Match_Aligned type");
8282 case Match_AlignedMemoryRequiresNone:
8283 case Match_DupAlignedMemoryRequiresNone:
8284 return Error(ErrorLoc, "alignment must be omitted");
8285 case Match_AlignedMemoryRequires16:
8286 case Match_DupAlignedMemoryRequires16:
8287 return Error(ErrorLoc, "alignment must be 16 or omitted");
8288 case Match_AlignedMemoryRequires32:
8289 case Match_DupAlignedMemoryRequires32:
8290 return Error(ErrorLoc, "alignment must be 32 or omitted");
8291 case Match_AlignedMemoryRequires64:
8292 case Match_DupAlignedMemoryRequires64:
8293 return Error(ErrorLoc, "alignment must be 64 or omitted");
8294 case Match_AlignedMemoryRequires64or128:
8295 case Match_DupAlignedMemoryRequires64or128:
8296 return Error(ErrorLoc, "alignment must be 64, 128 or omitted");
8297 case Match_AlignedMemoryRequires64or128or256:
8298 return Error(ErrorLoc, "alignment must be 64, 128, 256 or omitted");
8303 llvm_unreachable("Implement any new match types added!");
8306 /// parseDirective parses the arm specific directives
8307 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
8308 const MCObjectFileInfo::Environment Format =
8309 getContext().getObjectFileInfo()->getObjectFileType();
8310 bool IsMachO = Format == MCObjectFileInfo::IsMachO;
8312 StringRef IDVal = DirectiveID.getIdentifier();
8313 if (IDVal == ".word")
8314 return parseLiteralValues(4, DirectiveID.getLoc());
8315 else if (IDVal == ".short" || IDVal == ".hword")
8316 return parseLiteralValues(2, DirectiveID.getLoc());
8317 else if (IDVal == ".thumb")
8318 return parseDirectiveThumb(DirectiveID.getLoc());
8319 else if (IDVal == ".arm")
8320 return parseDirectiveARM(DirectiveID.getLoc());
8321 else if (IDVal == ".thumb_func")
8322 return parseDirectiveThumbFunc(DirectiveID.getLoc());
8323 else if (IDVal == ".code")
8324 return parseDirectiveCode(DirectiveID.getLoc());
8325 else if (IDVal == ".syntax")
8326 return parseDirectiveSyntax(DirectiveID.getLoc());
8327 else if (IDVal == ".unreq")
8328 return parseDirectiveUnreq(DirectiveID.getLoc());
8329 else if (IDVal == ".fnend")
8330 return parseDirectiveFnEnd(DirectiveID.getLoc());
8331 else if (IDVal == ".cantunwind")
8332 return parseDirectiveCantUnwind(DirectiveID.getLoc());
8333 else if (IDVal == ".personality")
8334 return parseDirectivePersonality(DirectiveID.getLoc());
8335 else if (IDVal == ".handlerdata")
8336 return parseDirectiveHandlerData(DirectiveID.getLoc());
8337 else if (IDVal == ".setfp")
8338 return parseDirectiveSetFP(DirectiveID.getLoc());
8339 else if (IDVal == ".pad")
8340 return parseDirectivePad(DirectiveID.getLoc());
8341 else if (IDVal == ".save")
8342 return parseDirectiveRegSave(DirectiveID.getLoc(), false);
8343 else if (IDVal == ".vsave")
8344 return parseDirectiveRegSave(DirectiveID.getLoc(), true);
8345 else if (IDVal == ".ltorg" || IDVal == ".pool")
8346 return parseDirectiveLtorg(DirectiveID.getLoc());
8347 else if (IDVal == ".even")
8348 return parseDirectiveEven(DirectiveID.getLoc());
8349 else if (IDVal == ".personalityindex")
8350 return parseDirectivePersonalityIndex(DirectiveID.getLoc());
8351 else if (IDVal == ".unwind_raw")
8352 return parseDirectiveUnwindRaw(DirectiveID.getLoc());
8353 else if (IDVal == ".movsp")
8354 return parseDirectiveMovSP(DirectiveID.getLoc());
8355 else if (IDVal == ".arch_extension")
8356 return parseDirectiveArchExtension(DirectiveID.getLoc());
8357 else if (IDVal == ".align")
8358 return parseDirectiveAlign(DirectiveID.getLoc());
8359 else if (IDVal == ".thumb_set")
8360 return parseDirectiveThumbSet(DirectiveID.getLoc());
8363 if (IDVal == ".arch")
8364 return parseDirectiveArch(DirectiveID.getLoc());
8365 else if (IDVal == ".cpu")
8366 return parseDirectiveCPU(DirectiveID.getLoc());
8367 else if (IDVal == ".eabi_attribute")
8368 return parseDirectiveEabiAttr(DirectiveID.getLoc());
8369 else if (IDVal == ".fpu")
8370 return parseDirectiveFPU(DirectiveID.getLoc());
8371 else if (IDVal == ".fnstart")
8372 return parseDirectiveFnStart(DirectiveID.getLoc());
8373 else if (IDVal == ".inst")
8374 return parseDirectiveInst(DirectiveID.getLoc());
8375 else if (IDVal == ".inst.n")
8376 return parseDirectiveInst(DirectiveID.getLoc(), 'n');
8377 else if (IDVal == ".inst.w")
8378 return parseDirectiveInst(DirectiveID.getLoc(), 'w');
8379 else if (IDVal == ".object_arch")
8380 return parseDirectiveObjectArch(DirectiveID.getLoc());
8381 else if (IDVal == ".tlsdescseq")
8382 return parseDirectiveTLSDescSeq(DirectiveID.getLoc());
8388 /// parseLiteralValues
8389 /// ::= .hword expression [, expression]*
8390 /// ::= .short expression [, expression]*
8391 /// ::= .word expression [, expression]*
8392 bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
8393 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8395 const MCExpr *Value;
8396 if (getParser().parseExpression(Value)) {
8397 Parser.eatToEndOfStatement();
8401 getParser().getStreamer().EmitValue(Value, Size);
8403 if (getLexer().is(AsmToken::EndOfStatement))
8406 // FIXME: Improve diagnostic.
8407 if (getLexer().isNot(AsmToken::Comma)) {
8408 Error(L, "unexpected token in directive");
8419 /// parseDirectiveThumb
8421 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
8422 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8423 Error(L, "unexpected token in directive");
8429 Error(L, "target does not support Thumb mode");
8436 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8440 /// parseDirectiveARM
8442 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
8443 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8444 Error(L, "unexpected token in directive");
8450 Error(L, "target does not support ARM mode");
8457 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8461 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
8462 if (NextSymbolIsThumb) {
8463 getParser().getStreamer().EmitThumbFunc(Symbol);
8464 NextSymbolIsThumb = false;
8468 /// parseDirectiveThumbFunc
8469 /// ::= .thumbfunc symbol_name
8470 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
8471 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
8472 bool isMachO = MAI->hasSubsectionsViaSymbols();
8474 // Darwin asm has (optionally) function name after .thumb_func direction
8477 const AsmToken &Tok = Parser.getTok();
8478 if (Tok.isNot(AsmToken::EndOfStatement)) {
8479 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) {
8480 Error(L, "unexpected token in .thumb_func directive");
8485 getParser().getContext().GetOrCreateSymbol(Tok.getIdentifier());
8486 getParser().getStreamer().EmitThumbFunc(Func);
8487 Parser.Lex(); // Consume the identifier token.
8492 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8493 Error(L, "unexpected token in directive");
8497 NextSymbolIsThumb = true;
8501 /// parseDirectiveSyntax
8502 /// ::= .syntax unified | divided
8503 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
8504 const AsmToken &Tok = Parser.getTok();
8505 if (Tok.isNot(AsmToken::Identifier)) {
8506 Error(L, "unexpected token in .syntax directive");
8510 StringRef Mode = Tok.getString();
8511 if (Mode == "unified" || Mode == "UNIFIED") {
8513 } else if (Mode == "divided" || Mode == "DIVIDED") {
8514 Error(L, "'.syntax divided' arm asssembly not supported");
8517 Error(L, "unrecognized syntax mode in .syntax directive");
8521 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8522 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8527 // TODO tell the MC streamer the mode
8528 // getParser().getStreamer().Emit???();
8532 /// parseDirectiveCode
8533 /// ::= .code 16 | 32
8534 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
8535 const AsmToken &Tok = Parser.getTok();
8536 if (Tok.isNot(AsmToken::Integer)) {
8537 Error(L, "unexpected token in .code directive");
8540 int64_t Val = Parser.getTok().getIntVal();
8541 if (Val != 16 && Val != 32) {
8542 Error(L, "invalid operand to .code directive");
8547 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8548 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8555 Error(L, "target does not support Thumb mode");
8561 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8564 Error(L, "target does not support ARM mode");
8570 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8576 /// parseDirectiveReq
8577 /// ::= name .req registername
8578 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
8579 Parser.Lex(); // Eat the '.req' token.
8581 SMLoc SRegLoc, ERegLoc;
8582 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
8583 Parser.eatToEndOfStatement();
8584 Error(SRegLoc, "register name expected");
8588 // Shouldn't be anything else.
8589 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
8590 Parser.eatToEndOfStatement();
8591 Error(Parser.getTok().getLoc(), "unexpected input in .req directive.");
8595 Parser.Lex(); // Consume the EndOfStatement
8597 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg) {
8598 Error(SRegLoc, "redefinition of '" + Name + "' does not match original.");
8605 /// parseDirectiveUneq
8606 /// ::= .unreq registername
8607 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
8608 if (Parser.getTok().isNot(AsmToken::Identifier)) {
8609 Parser.eatToEndOfStatement();
8610 Error(L, "unexpected input in .unreq directive.");
8613 RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
8614 Parser.Lex(); // Eat the identifier.
8618 /// parseDirectiveArch
8620 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
8621 StringRef Arch = getParser().parseStringToEndOfStatement().trim();
8623 unsigned ID = StringSwitch<unsigned>(Arch)
8624 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
8625 .Case(NAME, ARM::ID)
8626 #define ARM_ARCH_ALIAS(NAME, ID) \
8627 .Case(NAME, ARM::ID)
8628 #include "MCTargetDesc/ARMArchName.def"
8629 .Default(ARM::INVALID_ARCH);
8631 if (ID == ARM::INVALID_ARCH) {
8632 Error(L, "Unknown arch name");
8636 getTargetStreamer().emitArch(ID);
8640 /// parseDirectiveEabiAttr
8641 /// ::= .eabi_attribute int, int [, "str"]
8642 /// ::= .eabi_attribute Tag_name, int [, "str"]
8643 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
8646 TagLoc = Parser.getTok().getLoc();
8647 if (Parser.getTok().is(AsmToken::Identifier)) {
8648 StringRef Name = Parser.getTok().getIdentifier();
8649 Tag = ARMBuildAttrs::AttrTypeFromString(Name);
8651 Error(TagLoc, "attribute name not recognised: " + Name);
8652 Parser.eatToEndOfStatement();
8657 const MCExpr *AttrExpr;
8659 TagLoc = Parser.getTok().getLoc();
8660 if (Parser.parseExpression(AttrExpr)) {
8661 Parser.eatToEndOfStatement();
8665 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
8667 Error(TagLoc, "expected numeric constant");
8668 Parser.eatToEndOfStatement();
8672 Tag = CE->getValue();
8675 if (Parser.getTok().isNot(AsmToken::Comma)) {
8676 Error(Parser.getTok().getLoc(), "comma expected");
8677 Parser.eatToEndOfStatement();
8680 Parser.Lex(); // skip comma
8682 StringRef StringValue = "";
8683 bool IsStringValue = false;
8685 int64_t IntegerValue = 0;
8686 bool IsIntegerValue = false;
8688 if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
8689 IsStringValue = true;
8690 else if (Tag == ARMBuildAttrs::compatibility) {
8691 IsStringValue = true;
8692 IsIntegerValue = true;
8693 } else if (Tag < 32 || Tag % 2 == 0)
8694 IsIntegerValue = true;
8695 else if (Tag % 2 == 1)
8696 IsStringValue = true;
8698 llvm_unreachable("invalid tag type");
8700 if (IsIntegerValue) {
8701 const MCExpr *ValueExpr;
8702 SMLoc ValueExprLoc = Parser.getTok().getLoc();
8703 if (Parser.parseExpression(ValueExpr)) {
8704 Parser.eatToEndOfStatement();
8708 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
8710 Error(ValueExprLoc, "expected numeric constant");
8711 Parser.eatToEndOfStatement();
8715 IntegerValue = CE->getValue();
8718 if (Tag == ARMBuildAttrs::compatibility) {
8719 if (Parser.getTok().isNot(AsmToken::Comma))
8720 IsStringValue = false;
8725 if (IsStringValue) {
8726 if (Parser.getTok().isNot(AsmToken::String)) {
8727 Error(Parser.getTok().getLoc(), "bad string constant");
8728 Parser.eatToEndOfStatement();
8732 StringValue = Parser.getTok().getStringContents();
8736 if (IsIntegerValue && IsStringValue) {
8737 assert(Tag == ARMBuildAttrs::compatibility);
8738 getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
8739 } else if (IsIntegerValue)
8740 getTargetStreamer().emitAttribute(Tag, IntegerValue);
8741 else if (IsStringValue)
8742 getTargetStreamer().emitTextAttribute(Tag, StringValue);
8746 /// parseDirectiveCPU
8748 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
8749 StringRef CPU = getParser().parseStringToEndOfStatement().trim();
8750 getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
8754 // FIXME: This is duplicated in getARMFPUFeatures() in
8755 // tools/clang/lib/Driver/Tools.cpp
8756 static const struct {
8758 const uint64_t Enabled;
8759 const uint64_t Disabled;
8761 {ARM::VFP, ARM::FeatureVFP2, ARM::FeatureNEON},
8762 {ARM::VFPV2, ARM::FeatureVFP2, ARM::FeatureNEON},
8763 {ARM::VFPV3, ARM::FeatureVFP3, ARM::FeatureNEON},
8764 {ARM::VFPV3_D16, ARM::FeatureVFP3 | ARM::FeatureD16, ARM::FeatureNEON},
8765 {ARM::VFPV4, ARM::FeatureVFP4, ARM::FeatureNEON},
8766 {ARM::VFPV4_D16, ARM::FeatureVFP4 | ARM::FeatureD16, ARM::FeatureNEON},
8767 {ARM::FP_ARMV8, ARM::FeatureFPARMv8,
8768 ARM::FeatureNEON | ARM::FeatureCrypto},
8769 {ARM::NEON, ARM::FeatureNEON, 0},
8770 {ARM::NEON_VFPV4, ARM::FeatureVFP4 | ARM::FeatureNEON, 0},
8771 {ARM::NEON_FP_ARMV8, ARM::FeatureFPARMv8 | ARM::FeatureNEON,
8772 ARM::FeatureCrypto},
8773 {ARM::CRYPTO_NEON_FP_ARMV8,
8774 ARM::FeatureFPARMv8 | ARM::FeatureNEON | ARM::FeatureCrypto, 0},
8775 {ARM::SOFTVFP, 0, 0},
8778 /// parseDirectiveFPU
8780 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
8781 StringRef FPU = getParser().parseStringToEndOfStatement().trim();
8783 unsigned ID = StringSwitch<unsigned>(FPU)
8784 #define ARM_FPU_NAME(NAME, ID) .Case(NAME, ARM::ID)
8785 #include "ARMFPUName.def"
8786 .Default(ARM::INVALID_FPU);
8788 if (ID == ARM::INVALID_FPU) {
8789 Error(L, "Unknown FPU name");
8793 for (const auto &Fpu : Fpus) {
8797 // Need to toggle features that should be on but are off and that
8798 // should off but are on.
8799 uint64_t Toggle = (Fpu.Enabled & ~STI.getFeatureBits()) |
8800 (Fpu.Disabled & STI.getFeatureBits());
8801 setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature(Toggle)));
8805 getTargetStreamer().emitFPU(ID);
8809 /// parseDirectiveFnStart
8811 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
8812 if (UC.hasFnStart()) {
8813 Error(L, ".fnstart starts before the end of previous one");
8814 UC.emitFnStartLocNotes();
8818 // Reset the unwind directives parser state
8821 getTargetStreamer().emitFnStart();
8823 UC.recordFnStart(L);
8827 /// parseDirectiveFnEnd
8829 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
8830 // Check the ordering of unwind directives
8831 if (!UC.hasFnStart()) {
8832 Error(L, ".fnstart must precede .fnend directive");
8836 // Reset the unwind directives parser state
8837 getTargetStreamer().emitFnEnd();
8843 /// parseDirectiveCantUnwind
8845 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
8846 UC.recordCantUnwind(L);
8848 // Check the ordering of unwind directives
8849 if (!UC.hasFnStart()) {
8850 Error(L, ".fnstart must precede .cantunwind directive");
8853 if (UC.hasHandlerData()) {
8854 Error(L, ".cantunwind can't be used with .handlerdata directive");
8855 UC.emitHandlerDataLocNotes();
8858 if (UC.hasPersonality()) {
8859 Error(L, ".cantunwind can't be used with .personality directive");
8860 UC.emitPersonalityLocNotes();
8864 getTargetStreamer().emitCantUnwind();
8868 /// parseDirectivePersonality
8869 /// ::= .personality name
8870 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
8871 bool HasExistingPersonality = UC.hasPersonality();
8873 UC.recordPersonality(L);
8875 // Check the ordering of unwind directives
8876 if (!UC.hasFnStart()) {
8877 Error(L, ".fnstart must precede .personality directive");
8880 if (UC.cantUnwind()) {
8881 Error(L, ".personality can't be used with .cantunwind directive");
8882 UC.emitCantUnwindLocNotes();
8885 if (UC.hasHandlerData()) {
8886 Error(L, ".personality must precede .handlerdata directive");
8887 UC.emitHandlerDataLocNotes();
8890 if (HasExistingPersonality) {
8891 Parser.eatToEndOfStatement();
8892 Error(L, "multiple personality directives");
8893 UC.emitPersonalityLocNotes();
8897 // Parse the name of the personality routine
8898 if (Parser.getTok().isNot(AsmToken::Identifier)) {
8899 Parser.eatToEndOfStatement();
8900 Error(L, "unexpected input in .personality directive.");
8903 StringRef Name(Parser.getTok().getIdentifier());
8906 MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
8907 getTargetStreamer().emitPersonality(PR);
8911 /// parseDirectiveHandlerData
8912 /// ::= .handlerdata
8913 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
8914 UC.recordHandlerData(L);
8916 // Check the ordering of unwind directives
8917 if (!UC.hasFnStart()) {
8918 Error(L, ".fnstart must precede .personality directive");
8921 if (UC.cantUnwind()) {
8922 Error(L, ".handlerdata can't be used with .cantunwind directive");
8923 UC.emitCantUnwindLocNotes();
8927 getTargetStreamer().emitHandlerData();
8931 /// parseDirectiveSetFP
8932 /// ::= .setfp fpreg, spreg [, offset]
8933 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
8934 // Check the ordering of unwind directives
8935 if (!UC.hasFnStart()) {
8936 Error(L, ".fnstart must precede .setfp directive");
8939 if (UC.hasHandlerData()) {
8940 Error(L, ".setfp must precede .handlerdata directive");
8945 SMLoc FPRegLoc = Parser.getTok().getLoc();
8946 int FPReg = tryParseRegister();
8948 Error(FPRegLoc, "frame pointer register expected");
8953 if (Parser.getTok().isNot(AsmToken::Comma)) {
8954 Error(Parser.getTok().getLoc(), "comma expected");
8957 Parser.Lex(); // skip comma
8960 SMLoc SPRegLoc = Parser.getTok().getLoc();
8961 int SPReg = tryParseRegister();
8963 Error(SPRegLoc, "stack pointer register expected");
8967 if (SPReg != ARM::SP && SPReg != UC.getFPReg()) {
8968 Error(SPRegLoc, "register should be either $sp or the latest fp register");
8972 // Update the frame pointer register
8973 UC.saveFPReg(FPReg);
8977 if (Parser.getTok().is(AsmToken::Comma)) {
8978 Parser.Lex(); // skip comma
8980 if (Parser.getTok().isNot(AsmToken::Hash) &&
8981 Parser.getTok().isNot(AsmToken::Dollar)) {
8982 Error(Parser.getTok().getLoc(), "'#' expected");
8985 Parser.Lex(); // skip hash token.
8987 const MCExpr *OffsetExpr;
8988 SMLoc ExLoc = Parser.getTok().getLoc();
8990 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
8991 Error(ExLoc, "malformed setfp offset");
8994 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8996 Error(ExLoc, "setfp offset must be an immediate");
9000 Offset = CE->getValue();
9003 getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
9004 static_cast<unsigned>(SPReg), Offset);
9010 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
9011 // Check the ordering of unwind directives
9012 if (!UC.hasFnStart()) {
9013 Error(L, ".fnstart must precede .pad directive");
9016 if (UC.hasHandlerData()) {
9017 Error(L, ".pad must precede .handlerdata directive");
9022 if (Parser.getTok().isNot(AsmToken::Hash) &&
9023 Parser.getTok().isNot(AsmToken::Dollar)) {
9024 Error(Parser.getTok().getLoc(), "'#' expected");
9027 Parser.Lex(); // skip hash token.
9029 const MCExpr *OffsetExpr;
9030 SMLoc ExLoc = Parser.getTok().getLoc();
9032 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
9033 Error(ExLoc, "malformed pad offset");
9036 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9038 Error(ExLoc, "pad offset must be an immediate");
9042 getTargetStreamer().emitPad(CE->getValue());
9046 /// parseDirectiveRegSave
9047 /// ::= .save { registers }
9048 /// ::= .vsave { registers }
9049 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
9050 // Check the ordering of unwind directives
9051 if (!UC.hasFnStart()) {
9052 Error(L, ".fnstart must precede .save or .vsave directives");
9055 if (UC.hasHandlerData()) {
9056 Error(L, ".save or .vsave must precede .handlerdata directive");
9060 // RAII object to make sure parsed operands are deleted.
9061 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
9063 // Parse the register list
9064 if (parseRegisterList(Operands))
9066 ARMOperand &Op = (ARMOperand &)*Operands[0];
9067 if (!IsVector && !Op.isRegList()) {
9068 Error(L, ".save expects GPR registers");
9071 if (IsVector && !Op.isDPRRegList()) {
9072 Error(L, ".vsave expects DPR registers");
9076 getTargetStreamer().emitRegSave(Op.getRegList(), IsVector);
9080 /// parseDirectiveInst
9081 /// ::= .inst opcode [, ...]
9082 /// ::= .inst.n opcode [, ...]
9083 /// ::= .inst.w opcode [, ...]
9084 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
9096 Parser.eatToEndOfStatement();
9097 Error(Loc, "cannot determine Thumb instruction size, "
9098 "use inst.n/inst.w instead");
9103 Parser.eatToEndOfStatement();
9104 Error(Loc, "width suffixes are invalid in ARM mode");
9110 if (getLexer().is(AsmToken::EndOfStatement)) {
9111 Parser.eatToEndOfStatement();
9112 Error(Loc, "expected expression following directive");
9119 if (getParser().parseExpression(Expr)) {
9120 Error(Loc, "expected expression");
9124 const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
9126 Error(Loc, "expected constant expression");
9132 if (Value->getValue() > 0xffff) {
9133 Error(Loc, "inst.n operand is too big, use inst.w instead");
9138 if (Value->getValue() > 0xffffffff) {
9140 StringRef(Suffix ? "inst.w" : "inst") + " operand is too big");
9145 llvm_unreachable("only supported widths are 2 and 4");
9148 getTargetStreamer().emitInst(Value->getValue(), Suffix);
9150 if (getLexer().is(AsmToken::EndOfStatement))
9153 if (getLexer().isNot(AsmToken::Comma)) {
9154 Error(Loc, "unexpected token in directive");
9165 /// parseDirectiveLtorg
9166 /// ::= .ltorg | .pool
9167 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
9168 getTargetStreamer().emitCurrentConstantPool();
9172 bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
9173 const MCSection *Section = getStreamer().getCurrentSection().first;
9175 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9176 TokError("unexpected token in directive");
9181 getStreamer().InitSections();
9182 Section = getStreamer().getCurrentSection().first;
9185 assert(Section && "must have section to emit alignment");
9186 if (Section->UseCodeAlign())
9187 getStreamer().EmitCodeAlignment(2);
9189 getStreamer().EmitValueToAlignment(2);
9194 /// parseDirectivePersonalityIndex
9195 /// ::= .personalityindex index
9196 bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) {
9197 bool HasExistingPersonality = UC.hasPersonality();
9199 UC.recordPersonalityIndex(L);
9201 if (!UC.hasFnStart()) {
9202 Parser.eatToEndOfStatement();
9203 Error(L, ".fnstart must precede .personalityindex directive");
9206 if (UC.cantUnwind()) {
9207 Parser.eatToEndOfStatement();
9208 Error(L, ".personalityindex cannot be used with .cantunwind");
9209 UC.emitCantUnwindLocNotes();
9212 if (UC.hasHandlerData()) {
9213 Parser.eatToEndOfStatement();
9214 Error(L, ".personalityindex must precede .handlerdata directive");
9215 UC.emitHandlerDataLocNotes();
9218 if (HasExistingPersonality) {
9219 Parser.eatToEndOfStatement();
9220 Error(L, "multiple personality directives");
9221 UC.emitPersonalityLocNotes();
9225 const MCExpr *IndexExpression;
9226 SMLoc IndexLoc = Parser.getTok().getLoc();
9227 if (Parser.parseExpression(IndexExpression)) {
9228 Parser.eatToEndOfStatement();
9232 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
9234 Parser.eatToEndOfStatement();
9235 Error(IndexLoc, "index must be a constant number");
9238 if (CE->getValue() < 0 ||
9239 CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) {
9240 Parser.eatToEndOfStatement();
9241 Error(IndexLoc, "personality routine index should be in range [0-3]");
9245 getTargetStreamer().emitPersonalityIndex(CE->getValue());
9249 /// parseDirectiveUnwindRaw
9250 /// ::= .unwind_raw offset, opcode [, opcode...]
9251 bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
9252 if (!UC.hasFnStart()) {
9253 Parser.eatToEndOfStatement();
9254 Error(L, ".fnstart must precede .unwind_raw directives");
9258 int64_t StackOffset;
9260 const MCExpr *OffsetExpr;
9261 SMLoc OffsetLoc = getLexer().getLoc();
9262 if (getLexer().is(AsmToken::EndOfStatement) ||
9263 getParser().parseExpression(OffsetExpr)) {
9264 Error(OffsetLoc, "expected expression");
9265 Parser.eatToEndOfStatement();
9269 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9271 Error(OffsetLoc, "offset must be a constant");
9272 Parser.eatToEndOfStatement();
9276 StackOffset = CE->getValue();
9278 if (getLexer().isNot(AsmToken::Comma)) {
9279 Error(getLexer().getLoc(), "expected comma");
9280 Parser.eatToEndOfStatement();
9285 SmallVector<uint8_t, 16> Opcodes;
9289 SMLoc OpcodeLoc = getLexer().getLoc();
9290 if (getLexer().is(AsmToken::EndOfStatement) || Parser.parseExpression(OE)) {
9291 Error(OpcodeLoc, "expected opcode expression");
9292 Parser.eatToEndOfStatement();
9296 const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
9298 Error(OpcodeLoc, "opcode value must be a constant");
9299 Parser.eatToEndOfStatement();
9303 const int64_t Opcode = OC->getValue();
9304 if (Opcode & ~0xff) {
9305 Error(OpcodeLoc, "invalid opcode");
9306 Parser.eatToEndOfStatement();
9310 Opcodes.push_back(uint8_t(Opcode));
9312 if (getLexer().is(AsmToken::EndOfStatement))
9315 if (getLexer().isNot(AsmToken::Comma)) {
9316 Error(getLexer().getLoc(), "unexpected token in directive");
9317 Parser.eatToEndOfStatement();
9324 getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes);
9330 /// parseDirectiveTLSDescSeq
9331 /// ::= .tlsdescseq tls-variable
9332 bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) {
9333 if (getLexer().isNot(AsmToken::Identifier)) {
9334 TokError("expected variable after '.tlsdescseq' directive");
9335 Parser.eatToEndOfStatement();
9339 const MCSymbolRefExpr *SRE =
9340 MCSymbolRefExpr::Create(Parser.getTok().getIdentifier(),
9341 MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext());
9344 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9345 Error(Parser.getTok().getLoc(), "unexpected token");
9346 Parser.eatToEndOfStatement();
9350 getTargetStreamer().AnnotateTLSDescriptorSequence(SRE);
9354 /// parseDirectiveMovSP
9355 /// ::= .movsp reg [, #offset]
9356 bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) {
9357 if (!UC.hasFnStart()) {
9358 Parser.eatToEndOfStatement();
9359 Error(L, ".fnstart must precede .movsp directives");
9362 if (UC.getFPReg() != ARM::SP) {
9363 Parser.eatToEndOfStatement();
9364 Error(L, "unexpected .movsp directive");
9368 SMLoc SPRegLoc = Parser.getTok().getLoc();
9369 int SPReg = tryParseRegister();
9371 Parser.eatToEndOfStatement();
9372 Error(SPRegLoc, "register expected");
9376 if (SPReg == ARM::SP || SPReg == ARM::PC) {
9377 Parser.eatToEndOfStatement();
9378 Error(SPRegLoc, "sp and pc are not permitted in .movsp directive");
9383 if (Parser.getTok().is(AsmToken::Comma)) {
9386 if (Parser.getTok().isNot(AsmToken::Hash)) {
9387 Error(Parser.getTok().getLoc(), "expected #constant");
9388 Parser.eatToEndOfStatement();
9393 const MCExpr *OffsetExpr;
9394 SMLoc OffsetLoc = Parser.getTok().getLoc();
9395 if (Parser.parseExpression(OffsetExpr)) {
9396 Parser.eatToEndOfStatement();
9397 Error(OffsetLoc, "malformed offset expression");
9401 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9403 Parser.eatToEndOfStatement();
9404 Error(OffsetLoc, "offset must be an immediate constant");
9408 Offset = CE->getValue();
9411 getTargetStreamer().emitMovSP(SPReg, Offset);
9412 UC.saveFPReg(SPReg);
9417 /// parseDirectiveObjectArch
9418 /// ::= .object_arch name
9419 bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
9420 if (getLexer().isNot(AsmToken::Identifier)) {
9421 Error(getLexer().getLoc(), "unexpected token");
9422 Parser.eatToEndOfStatement();
9426 StringRef Arch = Parser.getTok().getString();
9427 SMLoc ArchLoc = Parser.getTok().getLoc();
9430 unsigned ID = StringSwitch<unsigned>(Arch)
9431 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
9432 .Case(NAME, ARM::ID)
9433 #define ARM_ARCH_ALIAS(NAME, ID) \
9434 .Case(NAME, ARM::ID)
9435 #include "MCTargetDesc/ARMArchName.def"
9436 #undef ARM_ARCH_NAME
9437 #undef ARM_ARCH_ALIAS
9438 .Default(ARM::INVALID_ARCH);
9440 if (ID == ARM::INVALID_ARCH) {
9441 Error(ArchLoc, "unknown architecture '" + Arch + "'");
9442 Parser.eatToEndOfStatement();
9446 getTargetStreamer().emitObjectArch(ID);
9448 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9449 Error(getLexer().getLoc(), "unexpected token");
9450 Parser.eatToEndOfStatement();
9456 /// parseDirectiveAlign
9458 bool ARMAsmParser::parseDirectiveAlign(SMLoc L) {
9459 // NOTE: if this is not the end of the statement, fall back to the target
9460 // agnostic handling for this directive which will correctly handle this.
9461 if (getLexer().isNot(AsmToken::EndOfStatement))
9464 // '.align' is target specifically handled to mean 2**2 byte alignment.
9465 if (getStreamer().getCurrentSection().first->UseCodeAlign())
9466 getStreamer().EmitCodeAlignment(4, 0);
9468 getStreamer().EmitValueToAlignment(4, 0, 1, 0);
9473 /// parseDirectiveThumbSet
9474 /// ::= .thumb_set name, value
9475 bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) {
9477 if (Parser.parseIdentifier(Name)) {
9478 TokError("expected identifier after '.thumb_set'");
9479 Parser.eatToEndOfStatement();
9483 if (getLexer().isNot(AsmToken::Comma)) {
9484 TokError("expected comma after name '" + Name + "'");
9485 Parser.eatToEndOfStatement();
9490 const MCExpr *Value;
9491 if (Parser.parseExpression(Value)) {
9492 TokError("missing expression");
9493 Parser.eatToEndOfStatement();
9497 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9498 TokError("unexpected token");
9499 Parser.eatToEndOfStatement();
9504 MCSymbol *Alias = getContext().GetOrCreateSymbol(Name);
9505 getTargetStreamer().emitThumbSet(Alias, Value);
9509 /// Force static initialization.
9510 extern "C" void LLVMInitializeARMAsmParser() {
9511 RegisterMCAsmParser<ARMAsmParser> X(TheARMLETarget);
9512 RegisterMCAsmParser<ARMAsmParser> Y(TheARMBETarget);
9513 RegisterMCAsmParser<ARMAsmParser> A(TheThumbLETarget);
9514 RegisterMCAsmParser<ARMAsmParser> B(TheThumbBETarget);
9517 #define GET_REGISTER_MATCHER
9518 #define GET_SUBTARGET_FEATURE_NAME
9519 #define GET_MATCHER_IMPLEMENTATION
9520 #include "ARMGenAsmMatcher.inc"
9522 static const struct {
9524 const unsigned ArchCheck;
9525 const uint64_t Features;
9527 { "crc", Feature_HasV8, ARM::FeatureCRC },
9528 { "crypto", Feature_HasV8,
9529 ARM::FeatureCrypto | ARM::FeatureNEON | ARM::FeatureFPARMv8 },
9530 { "fp", Feature_HasV8, ARM::FeatureFPARMv8 },
9531 { "idiv", Feature_HasV7 | Feature_IsNotMClass,
9532 ARM::FeatureHWDiv | ARM::FeatureHWDivARM },
9533 // FIXME: iWMMXT not supported
9534 { "iwmmxt", Feature_None, 0 },
9535 // FIXME: iWMMXT2 not supported
9536 { "iwmmxt2", Feature_None, 0 },
9537 // FIXME: Maverick not supported
9538 { "maverick", Feature_None, 0 },
9539 { "mp", Feature_HasV7 | Feature_IsNotMClass, ARM::FeatureMP },
9540 // FIXME: ARMv6-m OS Extensions feature not checked
9541 { "os", Feature_None, 0 },
9542 // FIXME: Also available in ARMv6-K
9543 { "sec", Feature_HasV7, ARM::FeatureTrustZone },
9544 { "simd", Feature_HasV8, ARM::FeatureNEON | ARM::FeatureFPARMv8 },
9545 // FIXME: Only available in A-class, isel not predicated
9546 { "virt", Feature_HasV7, ARM::FeatureVirtualization },
9547 // FIXME: xscale not supported
9548 { "xscale", Feature_None, 0 },
9551 /// parseDirectiveArchExtension
9552 /// ::= .arch_extension [no]feature
9553 bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
9554 if (getLexer().isNot(AsmToken::Identifier)) {
9555 Error(getLexer().getLoc(), "unexpected token");
9556 Parser.eatToEndOfStatement();
9560 StringRef Name = Parser.getTok().getString();
9561 SMLoc ExtLoc = Parser.getTok().getLoc();
9564 bool EnableFeature = true;
9565 if (Name.startswith_lower("no")) {
9566 EnableFeature = false;
9567 Name = Name.substr(2);
9570 for (const auto &Extension : Extensions) {
9571 if (Extension.Name != Name)
9574 if (!Extension.Features)
9575 report_fatal_error("unsupported architectural extension: " + Name);
9577 if ((getAvailableFeatures() & Extension.ArchCheck) != Extension.ArchCheck) {
9578 Error(ExtLoc, "architectural extension '" + Name + "' is not "
9579 "allowed for the current base architecture");
9583 uint64_t ToggleFeatures = EnableFeature
9584 ? (~STI.getFeatureBits() & Extension.Features)
9585 : ( STI.getFeatureBits() & Extension.Features);
9587 ComputeAvailableFeatures(STI.ToggleFeature(ToggleFeatures));
9588 setAvailableFeatures(Features);
9592 Error(ExtLoc, "unknown architectural extension: " + Name);
9593 Parser.eatToEndOfStatement();
9597 // Define this matcher function after the auto-generated include so we
9598 // have the match class enum definitions.
9599 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
9601 ARMOperand &Op = static_cast<ARMOperand &>(AsmOp);
9602 // If the kind is a token for a literal immediate, check if our asm
9603 // operand matches. This is for InstAliases which have a fixed-value
9604 // immediate in the syntax.
9609 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
9610 if (CE->getValue() == 0)
9611 return Match_Success;
9615 const MCExpr *SOExpr = Op.getImm();
9617 if (!SOExpr->EvaluateAsAbsolute(Value))
9618 return Match_Success;
9619 assert((Value >= INT32_MIN && Value <= UINT32_MAX) &&
9620 "expression value must be representable in 32 bits");
9625 MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg()))
9626 return Match_Success;
9629 return Match_InvalidOperand;