1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMSubtarget.h"
12 #include "llvm/MC/MCParser/MCAsmLexer.h"
13 #include "llvm/MC/MCParser/MCAsmParser.h"
14 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
15 #include "llvm/MC/MCStreamer.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/Target/TargetRegistry.h"
19 #include "llvm/Target/TargetAsmParser.h"
20 #include "llvm/Support/SourceMgr.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/StringSwitch.h"
24 #include "llvm/ADT/Twine.h"
27 // The shift types for register controlled shifts in arm memory addressing
39 class ARMAsmParser : public TargetAsmParser {
44 MCAsmParser &getParser() const { return Parser; }
46 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
48 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
50 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
52 ARMOperand *MaybeParseRegister(bool ParseWriteBack);
53 ARMOperand *ParseRegisterList();
54 ARMOperand *ParseMemory();
56 bool ParseMemoryOffsetReg(bool &Negative,
57 bool &OffsetRegShifted,
58 enum ShiftType &ShiftType,
59 const MCExpr *&ShiftAmount,
60 const MCExpr *&Offset,
65 bool ParseShift(enum ShiftType &St, const MCExpr *&ShiftAmount, SMLoc &E);
67 ARMOperand *ParseOperand();
69 bool ParseDirectiveWord(unsigned Size, SMLoc L);
71 bool ParseDirectiveThumb(SMLoc L);
73 bool ParseDirectiveThumbFunc(SMLoc L);
75 bool ParseDirectiveCode(SMLoc L);
77 bool ParseDirectiveSyntax(SMLoc L);
79 bool MatchAndEmitInstruction(SMLoc IDLoc,
80 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
83 /// @name Auto-generated Match Functions
86 #define GET_ASSEMBLER_HEADER
87 #include "ARMGenAsmMatcher.inc"
93 ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
94 : TargetAsmParser(T), Parser(_Parser), TM(_TM) {}
96 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
97 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
99 virtual bool ParseDirective(AsmToken DirectiveID);
101 } // end anonymous namespace
105 /// ARMOperand - Instances of this class represent a parsed ARM machine
107 struct ARMOperand : public MCParsedAsmOperand {
117 SMLoc StartLoc, EndLoc;
121 ARMCC::CondCodes Val;
138 // This is for all forms of ARM address expressions
141 unsigned OffsetRegNum; // used when OffsetIsReg is true
142 const MCExpr *Offset; // used when OffsetIsReg is false
143 const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
144 enum ShiftType ShiftType; // used when OffsetRegShifted is true
146 OffsetRegShifted : 1, // only used when OffsetIsReg is true
150 Negative : 1, // only used when OffsetIsReg is true
156 //ARMOperand(KindTy K, SMLoc S, SMLoc E)
157 // : Kind(K), StartLoc(S), EndLoc(E) {}
159 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
161 StartLoc = o.StartLoc;
182 /// getStartLoc - Get the location of the first token of this operand.
183 SMLoc getStartLoc() const { return StartLoc; }
184 /// getEndLoc - Get the location of the last token of this operand.
185 SMLoc getEndLoc() const { return EndLoc; }
187 ARMCC::CondCodes getCondCode() const {
188 assert(Kind == CondCode && "Invalid access!");
192 StringRef getToken() const {
193 assert(Kind == Token && "Invalid access!");
194 return StringRef(Tok.Data, Tok.Length);
197 unsigned getReg() const {
198 assert(Kind == Register && "Invalid access!");
202 const MCExpr *getImm() const {
203 assert(Kind == Immediate && "Invalid access!");
207 bool isCondCode() const { return Kind == CondCode; }
209 bool isImm() const { return Kind == Immediate; }
211 bool isReg() const { return Kind == Register; }
213 bool isToken() const {return Kind == Token; }
215 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
216 // Add as immediates when possible.
217 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
218 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
220 Inst.addOperand(MCOperand::CreateExpr(Expr));
223 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
224 assert(N == 2 && "Invalid number of operands!");
225 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
226 // FIXME: What belongs here?
227 Inst.addOperand(MCOperand::CreateReg(0));
230 void addRegOperands(MCInst &Inst, unsigned N) const {
231 assert(N == 1 && "Invalid number of operands!");
232 Inst.addOperand(MCOperand::CreateReg(getReg()));
235 void addImmOperands(MCInst &Inst, unsigned N) const {
236 assert(N == 1 && "Invalid number of operands!");
237 addExpr(Inst, getImm());
240 virtual void dump(raw_ostream &OS) const;
242 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
243 ARMOperand *Op = new ARMOperand(CondCode);
250 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
251 ARMOperand *Op = new ARMOperand(Token);
252 Op->Tok.Data = Str.data();
253 Op->Tok.Length = Str.size();
259 static ARMOperand *CreateReg(unsigned RegNum, bool Writeback, SMLoc S,
261 ARMOperand *Op = new ARMOperand(Register);
262 Op->Reg.RegNum = RegNum;
263 Op->Reg.Writeback = Writeback;
269 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
270 ARMOperand *Op = new ARMOperand(Immediate);
277 static ARMOperand *CreateMem(unsigned BaseRegNum, bool OffsetIsReg,
278 const MCExpr *Offset, unsigned OffsetRegNum,
279 bool OffsetRegShifted, enum ShiftType ShiftType,
280 const MCExpr *ShiftAmount, bool Preindexed,
281 bool Postindexed, bool Negative, bool Writeback,
283 ARMOperand *Op = new ARMOperand(Memory);
284 Op->Mem.BaseRegNum = BaseRegNum;
285 Op->Mem.OffsetIsReg = OffsetIsReg;
286 Op->Mem.Offset = Offset;
287 Op->Mem.OffsetRegNum = OffsetRegNum;
288 Op->Mem.OffsetRegShifted = OffsetRegShifted;
289 Op->Mem.ShiftType = ShiftType;
290 Op->Mem.ShiftAmount = ShiftAmount;
291 Op->Mem.Preindexed = Preindexed;
292 Op->Mem.Postindexed = Postindexed;
293 Op->Mem.Negative = Negative;
294 Op->Mem.Writeback = Writeback;
302 ARMOperand(KindTy K) : Kind(K) {}
305 } // end anonymous namespace.
307 void ARMOperand::dump(raw_ostream &OS) const {
310 OS << ARMCondCodeToString(getCondCode());
319 OS << "<register " << getReg() << ">";
322 OS << "'" << getToken() << "'";
327 /// @name Auto-generated Match Functions
330 static unsigned MatchRegisterName(StringRef Name);
334 /// Try to parse a register name. The token must be an Identifier when called,
335 /// and if it is a register name the token is eaten and a Reg operand is created
336 /// and returned. Otherwise return null.
338 /// TODO this is likely to change to allow different register types and or to
339 /// parse for a specific register type.
340 ARMOperand *ARMAsmParser::MaybeParseRegister(bool ParseWriteBack) {
342 const AsmToken &Tok = Parser.getTok();
343 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
345 // FIXME: Validate register for the current architecture; we have to do
346 // validation later, so maybe there is no need for this here.
349 RegNum = MatchRegisterName(Tok.getString());
355 Parser.Lex(); // Eat identifier token.
357 E = Parser.getTok().getLoc();
359 bool Writeback = false;
360 if (ParseWriteBack) {
361 const AsmToken &ExclaimTok = Parser.getTok();
362 if (ExclaimTok.is(AsmToken::Exclaim)) {
363 E = ExclaimTok.getLoc();
365 Parser.Lex(); // Eat exclaim token
369 return ARMOperand::CreateReg(RegNum, Writeback, S, E);
372 /// Parse a register list, return it if successful else return null. The first
373 /// token must be a '{' when called.
374 ARMOperand *ARMAsmParser::ParseRegisterList() {
376 assert(Parser.getTok().is(AsmToken::LCurly) &&
377 "Token is not an Left Curly Brace");
378 S = Parser.getTok().getLoc();
379 Parser.Lex(); // Eat left curly brace token.
381 const AsmToken &RegTok = Parser.getTok();
382 SMLoc RegLoc = RegTok.getLoc();
383 if (RegTok.isNot(AsmToken::Identifier)) {
384 Error(RegLoc, "register expected");
387 int RegNum = MatchRegisterName(RegTok.getString());
389 Error(RegLoc, "register expected");
393 Parser.Lex(); // Eat identifier token.
394 unsigned RegList = 1 << RegNum;
396 int HighRegNum = RegNum;
397 // TODO ranges like "{Rn-Rm}"
398 while (Parser.getTok().is(AsmToken::Comma)) {
399 Parser.Lex(); // Eat comma token.
401 const AsmToken &RegTok = Parser.getTok();
402 SMLoc RegLoc = RegTok.getLoc();
403 if (RegTok.isNot(AsmToken::Identifier)) {
404 Error(RegLoc, "register expected");
407 int RegNum = MatchRegisterName(RegTok.getString());
409 Error(RegLoc, "register expected");
413 if (RegList & (1 << RegNum))
414 Warning(RegLoc, "register duplicated in register list");
415 else if (RegNum <= HighRegNum)
416 Warning(RegLoc, "register not in ascending order in register list");
417 RegList |= 1 << RegNum;
420 Parser.Lex(); // Eat identifier token.
422 const AsmToken &RCurlyTok = Parser.getTok();
423 if (RCurlyTok.isNot(AsmToken::RCurly)) {
424 Error(RCurlyTok.getLoc(), "'}' expected");
427 E = RCurlyTok.getLoc();
428 Parser.Lex(); // Eat left curly brace token.
430 // FIXME: Need to return an operand!
431 Error(E, "FIXME: register list parsing not implemented");
435 /// Parse an arm memory expression, return false if successful else return true
436 /// or an error. The first token must be a '[' when called.
437 /// TODO Only preindexing and postindexing addressing are started, unindexed
438 /// with option, etc are still to do.
439 ARMOperand *ARMAsmParser::ParseMemory() {
441 assert(Parser.getTok().is(AsmToken::LBrac) &&
442 "Token is not an Left Bracket");
443 S = Parser.getTok().getLoc();
444 Parser.Lex(); // Eat left bracket token.
446 const AsmToken &BaseRegTok = Parser.getTok();
447 if (BaseRegTok.isNot(AsmToken::Identifier)) {
448 Error(BaseRegTok.getLoc(), "register expected");
452 if (ARMOperand *Op = MaybeParseRegister(false))
453 BaseRegNum = Op->getReg();
455 Error(BaseRegTok.getLoc(), "register expected");
459 bool Preindexed = false;
460 bool Postindexed = false;
461 bool OffsetIsReg = false;
462 bool Negative = false;
463 bool Writeback = false;
465 // First look for preindexed address forms, that is after the "[Rn" we now
466 // have to see if the next token is a comma.
467 const AsmToken &Tok = Parser.getTok();
468 if (Tok.is(AsmToken::Comma)) {
470 Parser.Lex(); // Eat comma token.
472 bool OffsetRegShifted;
473 enum ShiftType ShiftType;
474 const MCExpr *ShiftAmount;
475 const MCExpr *Offset;
476 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
477 Offset, OffsetIsReg, OffsetRegNum, E))
479 const AsmToken &RBracTok = Parser.getTok();
480 if (RBracTok.isNot(AsmToken::RBrac)) {
481 Error(RBracTok.getLoc(), "']' expected");
484 E = RBracTok.getLoc();
485 Parser.Lex(); // Eat right bracket token.
487 const AsmToken &ExclaimTok = Parser.getTok();
488 if (ExclaimTok.is(AsmToken::Exclaim)) {
489 E = ExclaimTok.getLoc();
491 Parser.Lex(); // Eat exclaim token
493 return ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
494 OffsetRegShifted, ShiftType, ShiftAmount,
495 Preindexed, Postindexed, Negative, Writeback,
498 // The "[Rn" we have so far was not followed by a comma.
499 else if (Tok.is(AsmToken::RBrac)) {
500 // This is a post indexing addressing forms, that is a ']' follows after
505 Parser.Lex(); // Eat right bracket token.
507 int OffsetRegNum = 0;
508 bool OffsetRegShifted = false;
509 enum ShiftType ShiftType;
510 const MCExpr *ShiftAmount;
511 const MCExpr *Offset;
513 const AsmToken &NextTok = Parser.getTok();
514 if (NextTok.isNot(AsmToken::EndOfStatement)) {
515 if (NextTok.isNot(AsmToken::Comma)) {
516 Error(NextTok.getLoc(), "',' expected");
519 Parser.Lex(); // Eat comma token.
520 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
521 ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
526 return ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
527 OffsetRegShifted, ShiftType, ShiftAmount,
528 Preindexed, Postindexed, Negative, Writeback,
535 /// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
536 /// we will parse the following (were +/- means that a plus or minus is
541 /// we return false on success or an error otherwise.
542 bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
543 bool &OffsetRegShifted,
544 enum ShiftType &ShiftType,
545 const MCExpr *&ShiftAmount,
546 const MCExpr *&Offset,
551 OffsetRegShifted = false;
554 const AsmToken &NextTok = Parser.getTok();
555 E = NextTok.getLoc();
556 if (NextTok.is(AsmToken::Plus))
557 Parser.Lex(); // Eat plus token.
558 else if (NextTok.is(AsmToken::Minus)) {
560 Parser.Lex(); // Eat minus token
562 // See if there is a register following the "[Rn," or "[Rn]," we have so far.
563 const AsmToken &OffsetRegTok = Parser.getTok();
564 if (OffsetRegTok.is(AsmToken::Identifier)) {
565 if (ARMOperand *Op = MaybeParseRegister(false)) {
568 OffsetRegNum = Op->getReg();
572 // If we parsed a register as the offset then their can be a shift after that
573 if (OffsetRegNum != -1) {
574 // Look for a comma then a shift
575 const AsmToken &Tok = Parser.getTok();
576 if (Tok.is(AsmToken::Comma)) {
577 Parser.Lex(); // Eat comma token.
579 const AsmToken &Tok = Parser.getTok();
580 if (ParseShift(ShiftType, ShiftAmount, E))
581 return Error(Tok.getLoc(), "shift expected");
582 OffsetRegShifted = true;
585 else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
586 // Look for #offset following the "[Rn," or "[Rn],"
587 const AsmToken &HashTok = Parser.getTok();
588 if (HashTok.isNot(AsmToken::Hash))
589 return Error(HashTok.getLoc(), "'#' expected");
591 Parser.Lex(); // Eat hash token.
593 if (getParser().ParseExpression(Offset))
595 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
600 /// ParseShift as one of these two:
601 /// ( lsl | lsr | asr | ror ) , # shift_amount
603 /// and returns true if it parses a shift otherwise it returns false.
604 bool ARMAsmParser::ParseShift(ShiftType &St, const MCExpr *&ShiftAmount,
606 const AsmToken &Tok = Parser.getTok();
607 if (Tok.isNot(AsmToken::Identifier))
609 StringRef ShiftName = Tok.getString();
610 if (ShiftName == "lsl" || ShiftName == "LSL")
612 else if (ShiftName == "lsr" || ShiftName == "LSR")
614 else if (ShiftName == "asr" || ShiftName == "ASR")
616 else if (ShiftName == "ror" || ShiftName == "ROR")
618 else if (ShiftName == "rrx" || ShiftName == "RRX")
622 Parser.Lex(); // Eat shift type token.
628 // Otherwise, there must be a '#' and a shift amount.
629 const AsmToken &HashTok = Parser.getTok();
630 if (HashTok.isNot(AsmToken::Hash))
631 return Error(HashTok.getLoc(), "'#' expected");
632 Parser.Lex(); // Eat hash token.
634 if (getParser().ParseExpression(ShiftAmount))
640 /// Parse a arm instruction operand. For now this parses the operand regardless
642 ARMOperand *ARMAsmParser::ParseOperand() {
645 switch (getLexer().getKind()) {
646 case AsmToken::Identifier:
647 if (ARMOperand *Op = MaybeParseRegister(true))
650 // This was not a register so parse other operands that start with an
651 // identifier (like labels) as expressions and create them as immediates.
653 S = Parser.getTok().getLoc();
654 if (getParser().ParseExpression(IdVal))
656 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
657 return ARMOperand::CreateImm(IdVal, S, E);
658 case AsmToken::LBrac:
659 return ParseMemory();
660 case AsmToken::LCurly:
661 return ParseRegisterList();
664 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
665 S = Parser.getTok().getLoc();
667 const MCExpr *ImmVal;
668 if (getParser().ParseExpression(ImmVal))
670 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
671 return ARMOperand::CreateImm(ImmVal, S, E);
673 Error(Parser.getTok().getLoc(), "unexpected token in operand");
678 /// Parse an arm instruction mnemonic followed by its operands.
679 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
680 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
681 // Create the leading tokens for the mnemonic, split by '.' characters.
682 size_t Start = 0, Next = Name.find('.');
683 StringRef Head = Name.slice(Start, Next);
685 // Determine the predicate, if any.
687 // FIXME: We need a way to check whether a prefix supports predication,
688 // otherwise we will end up with an ambiguity for instructions that happen to
689 // end with a predicate name.
690 unsigned CC = StringSwitch<unsigned>(Head.substr(Head.size()-2))
691 .Case("eq", ARMCC::EQ)
692 .Case("ne", ARMCC::NE)
693 .Case("hs", ARMCC::HS)
694 .Case("lo", ARMCC::LO)
695 .Case("mi", ARMCC::MI)
696 .Case("pl", ARMCC::PL)
697 .Case("vs", ARMCC::VS)
698 .Case("vc", ARMCC::VC)
699 .Case("hi", ARMCC::HI)
700 .Case("ls", ARMCC::LS)
701 .Case("ge", ARMCC::GE)
702 .Case("lt", ARMCC::LT)
703 .Case("gt", ARMCC::GT)
704 .Case("le", ARMCC::LE)
705 .Case("al", ARMCC::AL)
709 Head = Head.slice(0, Head.size() - 2);
713 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
714 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), NameLoc));
716 // Add the remaining tokens in the mnemonic.
717 while (Next != StringRef::npos) {
719 Next = Name.find('.', Start + 1);
720 Head = Name.slice(Start, Next);
722 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
725 // Read the remaining operands.
726 if (getLexer().isNot(AsmToken::EndOfStatement)) {
727 // Read the first operand.
728 if (ARMOperand *Op = ParseOperand())
729 Operands.push_back(Op);
731 Parser.EatToEndOfStatement();
735 while (getLexer().is(AsmToken::Comma)) {
736 Parser.Lex(); // Eat the comma.
738 // Parse and remember the operand.
739 if (ARMOperand *Op = ParseOperand())
740 Operands.push_back(Op);
742 Parser.EatToEndOfStatement();
748 if (getLexer().isNot(AsmToken::EndOfStatement)) {
749 Parser.EatToEndOfStatement();
750 return TokError("unexpected token in argument list");
752 Parser.Lex(); // Consume the EndOfStatement
757 MatchAndEmitInstruction(SMLoc IDLoc,
758 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
762 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo)) {
764 Out.EmitInstruction(Inst);
767 case Match_MissingFeature:
768 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
770 case Match_InvalidOperand: {
771 SMLoc ErrorLoc = IDLoc;
772 if (ErrorInfo != ~0U) {
773 if (ErrorInfo >= Operands.size())
774 return Error(IDLoc, "too few operands for instruction");
776 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
777 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
780 return Error(ErrorLoc, "invalid operand for instruction");
782 case Match_MnemonicFail:
783 return Error(IDLoc, "unrecognized instruction mnemonic");
789 /// ParseDirective parses the arm specific directives
790 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
791 StringRef IDVal = DirectiveID.getIdentifier();
792 if (IDVal == ".word")
793 return ParseDirectiveWord(4, DirectiveID.getLoc());
794 else if (IDVal == ".thumb")
795 return ParseDirectiveThumb(DirectiveID.getLoc());
796 else if (IDVal == ".thumb_func")
797 return ParseDirectiveThumbFunc(DirectiveID.getLoc());
798 else if (IDVal == ".code")
799 return ParseDirectiveCode(DirectiveID.getLoc());
800 else if (IDVal == ".syntax")
801 return ParseDirectiveSyntax(DirectiveID.getLoc());
805 /// ParseDirectiveWord
806 /// ::= .word [ expression (, expression)* ]
807 bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
808 if (getLexer().isNot(AsmToken::EndOfStatement)) {
811 if (getParser().ParseExpression(Value))
814 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
816 if (getLexer().is(AsmToken::EndOfStatement))
819 // FIXME: Improve diagnostic.
820 if (getLexer().isNot(AsmToken::Comma))
821 return Error(L, "unexpected token in directive");
830 /// ParseDirectiveThumb
832 bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
833 if (getLexer().isNot(AsmToken::EndOfStatement))
834 return Error(L, "unexpected token in directive");
837 // TODO: set thumb mode
838 // TODO: tell the MC streamer the mode
839 // getParser().getStreamer().Emit???();
843 /// ParseDirectiveThumbFunc
844 /// ::= .thumbfunc symbol_name
845 bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
846 const AsmToken &Tok = Parser.getTok();
847 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
848 return Error(L, "unexpected token in .syntax directive");
849 Parser.Lex(); // Consume the identifier token.
851 if (getLexer().isNot(AsmToken::EndOfStatement))
852 return Error(L, "unexpected token in directive");
855 // TODO: mark symbol as a thumb symbol
856 // getParser().getStreamer().Emit???();
860 /// ParseDirectiveSyntax
861 /// ::= .syntax unified | divided
862 bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
863 const AsmToken &Tok = Parser.getTok();
864 if (Tok.isNot(AsmToken::Identifier))
865 return Error(L, "unexpected token in .syntax directive");
866 StringRef Mode = Tok.getString();
867 if (Mode == "unified" || Mode == "UNIFIED")
869 else if (Mode == "divided" || Mode == "DIVIDED")
872 return Error(L, "unrecognized syntax mode in .syntax directive");
874 if (getLexer().isNot(AsmToken::EndOfStatement))
875 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
878 // TODO tell the MC streamer the mode
879 // getParser().getStreamer().Emit???();
883 /// ParseDirectiveCode
884 /// ::= .code 16 | 32
885 bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
886 const AsmToken &Tok = Parser.getTok();
887 if (Tok.isNot(AsmToken::Integer))
888 return Error(L, "unexpected token in .code directive");
889 int64_t Val = Parser.getTok().getIntVal();
895 return Error(L, "invalid operand to .code directive");
897 if (getLexer().isNot(AsmToken::EndOfStatement))
898 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
901 // TODO tell the MC streamer the mode
902 // getParser().getStreamer().Emit???();
906 extern "C" void LLVMInitializeARMAsmLexer();
908 /// Force static initialization.
909 extern "C" void LLVMInitializeARMAsmParser() {
910 RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
911 RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
912 LLVMInitializeARMAsmLexer();
915 #define GET_REGISTER_MATCHER
916 #define GET_MATCHER_IMPLEMENTATION
917 #include "ARMGenAsmMatcher.inc"