1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMAddressingModes.h"
12 #include "ARMSubtarget.h"
13 #include "llvm/MC/MCParser/MCAsmLexer.h"
14 #include "llvm/MC/MCParser/MCAsmParser.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/Target/TargetRegistry.h"
21 #include "llvm/Target/TargetAsmParser.h"
22 #include "llvm/Support/SourceMgr.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/ADT/StringSwitch.h"
26 #include "llvm/ADT/Twine.h"
29 // The shift types for register controlled shifts in arm memory addressing
41 class ARMAsmParser : public TargetAsmParser {
46 MCAsmParser &getParser() const { return Parser; }
48 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
50 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
52 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
54 int TryParseRegister();
55 ARMOperand *TryParseRegisterWithWriteBack();
56 ARMOperand *ParseRegisterList();
57 ARMOperand *ParseMemory();
59 bool ParseMemoryOffsetReg(bool &Negative,
60 bool &OffsetRegShifted,
61 enum ShiftType &ShiftType,
62 const MCExpr *&ShiftAmount,
63 const MCExpr *&Offset,
68 bool ParseShift(enum ShiftType &St, const MCExpr *&ShiftAmount, SMLoc &E);
70 ARMOperand *ParseOperand();
72 bool ParseDirectiveWord(unsigned Size, SMLoc L);
74 bool ParseDirectiveThumb(SMLoc L);
76 bool ParseDirectiveThumbFunc(SMLoc L);
78 bool ParseDirectiveCode(SMLoc L);
80 bool ParseDirectiveSyntax(SMLoc L);
82 bool MatchAndEmitInstruction(SMLoc IDLoc,
83 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
86 /// @name Auto-generated Match Functions
89 #define GET_ASSEMBLER_HEADER
90 #include "ARMGenAsmMatcher.inc"
96 ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
97 : TargetAsmParser(T), Parser(_Parser), TM(_TM) {
98 // Initialize the set of available features.
99 setAvailableFeatures(ComputeAvailableFeatures(
100 &TM.getSubtarget<ARMSubtarget>()));
103 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
104 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
106 virtual bool ParseDirective(AsmToken DirectiveID);
108 } // end anonymous namespace
112 /// ARMOperand - Instances of this class represent a parsed ARM machine
114 struct ARMOperand : public MCParsedAsmOperand {
124 SMLoc StartLoc, EndLoc;
128 ARMCC::CondCodes Val;
145 // This is for all forms of ARM address expressions
148 unsigned OffsetRegNum; // used when OffsetIsReg is true
149 const MCExpr *Offset; // used when OffsetIsReg is false
150 const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
151 enum ShiftType ShiftType; // used when OffsetRegShifted is true
153 OffsetRegShifted : 1, // only used when OffsetIsReg is true
157 Negative : 1, // only used when OffsetIsReg is true
163 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
165 StartLoc = o.StartLoc;
186 /// getStartLoc - Get the location of the first token of this operand.
187 SMLoc getStartLoc() const { return StartLoc; }
188 /// getEndLoc - Get the location of the last token of this operand.
189 SMLoc getEndLoc() const { return EndLoc; }
191 ARMCC::CondCodes getCondCode() const {
192 assert(Kind == CondCode && "Invalid access!");
196 StringRef getToken() const {
197 assert(Kind == Token && "Invalid access!");
198 return StringRef(Tok.Data, Tok.Length);
201 unsigned getReg() const {
202 assert(Kind == Register && "Invalid access!");
206 const MCExpr *getImm() const {
207 assert(Kind == Immediate && "Invalid access!");
211 bool isCondCode() const { return Kind == CondCode; }
212 bool isImm() const { return Kind == Immediate; }
213 bool isReg() const { return Kind == Register; }
214 bool isToken() const { return Kind == Token; }
215 bool isMemory() const { return Kind == Memory; }
217 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
218 // Add as immediates when possible. Null MCExpr = 0.
220 Inst.addOperand(MCOperand::CreateImm(0));
221 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
222 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
224 Inst.addOperand(MCOperand::CreateExpr(Expr));
227 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
228 assert(N == 2 && "Invalid number of operands!");
229 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
230 // FIXME: What belongs here?
231 Inst.addOperand(MCOperand::CreateReg(0));
234 void addRegOperands(MCInst &Inst, unsigned N) const {
235 assert(N == 1 && "Invalid number of operands!");
236 Inst.addOperand(MCOperand::CreateReg(getReg()));
239 void addImmOperands(MCInst &Inst, unsigned N) const {
240 assert(N == 1 && "Invalid number of operands!");
241 addExpr(Inst, getImm());
245 bool isMemMode5() const {
246 if (!isMemory() || Mem.OffsetIsReg || Mem.OffsetRegShifted ||
247 Mem.Writeback || Mem.Negative)
249 // If there is an offset expression, make sure it's valid.
252 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
255 // The offset must be a multiple of 4 in the range 0-1020.
256 int64_t Value = CE->getValue();
257 return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020);
260 void addMemMode5Operands(MCInst &Inst, unsigned N) const {
261 assert(N == 2 && isMemMode5() && "Invalid number of operands!");
263 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
264 assert(!Mem.OffsetIsReg && "Invalid mode 5 operand");
266 // FIXME: #-0 is encoded differently than #0. Does the parser preserve
269 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
270 assert(CE && "Non-constant mode 5 offset operand!");
272 // The MCInst offset operand doesn't include the low two bits (like
273 // the instruction encoding).
274 int64_t Offset = CE->getValue() / 4;
276 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add,
279 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub,
282 Inst.addOperand(MCOperand::CreateImm(0));
286 virtual void dump(raw_ostream &OS) const;
288 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
289 ARMOperand *Op = new ARMOperand(CondCode);
296 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
297 ARMOperand *Op = new ARMOperand(Token);
298 Op->Tok.Data = Str.data();
299 Op->Tok.Length = Str.size();
305 static ARMOperand *CreateReg(unsigned RegNum, bool Writeback, SMLoc S,
307 ARMOperand *Op = new ARMOperand(Register);
308 Op->Reg.RegNum = RegNum;
309 Op->Reg.Writeback = Writeback;
315 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
316 ARMOperand *Op = new ARMOperand(Immediate);
323 static ARMOperand *CreateMem(unsigned BaseRegNum, bool OffsetIsReg,
324 const MCExpr *Offset, unsigned OffsetRegNum,
325 bool OffsetRegShifted, enum ShiftType ShiftType,
326 const MCExpr *ShiftAmount, bool Preindexed,
327 bool Postindexed, bool Negative, bool Writeback,
329 ARMOperand *Op = new ARMOperand(Memory);
330 Op->Mem.BaseRegNum = BaseRegNum;
331 Op->Mem.OffsetIsReg = OffsetIsReg;
332 Op->Mem.Offset = Offset;
333 Op->Mem.OffsetRegNum = OffsetRegNum;
334 Op->Mem.OffsetRegShifted = OffsetRegShifted;
335 Op->Mem.ShiftType = ShiftType;
336 Op->Mem.ShiftAmount = ShiftAmount;
337 Op->Mem.Preindexed = Preindexed;
338 Op->Mem.Postindexed = Postindexed;
339 Op->Mem.Negative = Negative;
340 Op->Mem.Writeback = Writeback;
348 ARMOperand(KindTy K) : Kind(K) {}
351 } // end anonymous namespace.
353 void ARMOperand::dump(raw_ostream &OS) const {
356 OS << ARMCondCodeToString(getCondCode());
365 OS << "<register " << getReg() << ">";
368 OS << "'" << getToken() << "'";
373 /// @name Auto-generated Match Functions
376 static unsigned MatchRegisterName(StringRef Name);
380 /// Try to parse a register name. The token must be an Identifier when called,
381 /// and if it is a register name the token is eaten and the register number is
382 /// returned. Otherwise return -1.
384 int ARMAsmParser::TryParseRegister() {
385 const AsmToken &Tok = Parser.getTok();
386 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
388 // FIXME: Validate register for the current architecture; we have to do
389 // validation later, so maybe there is no need for this here.
390 unsigned RegNum = MatchRegisterName(Tok.getString());
393 Parser.Lex(); // Eat identifier token.
398 /// Try to parse a register name. The token must be an Identifier when called,
399 /// and if it is a register name the token is eaten and the register number is
400 /// returned. Otherwise return -1.
402 /// TODO this is likely to change to allow different register types and or to
403 /// parse for a specific register type.
404 ARMOperand *ARMAsmParser::TryParseRegisterWithWriteBack() {
405 SMLoc S = Parser.getTok().getLoc();
406 int RegNo = TryParseRegister();
407 if (RegNo == -1) return 0;
409 SMLoc E = Parser.getTok().getLoc();
411 bool Writeback = false;
412 const AsmToken &ExclaimTok = Parser.getTok();
413 if (ExclaimTok.is(AsmToken::Exclaim)) {
414 E = ExclaimTok.getLoc();
416 Parser.Lex(); // Eat exclaim token
419 return ARMOperand::CreateReg(RegNo, Writeback, S, E);
422 /// Parse a register list, return it if successful else return null. The first
423 /// token must be a '{' when called.
424 ARMOperand *ARMAsmParser::ParseRegisterList() {
426 assert(Parser.getTok().is(AsmToken::LCurly) &&
427 "Token is not a Left Curly Brace");
428 S = Parser.getTok().getLoc();
429 Parser.Lex(); // Eat left curly brace token.
431 const AsmToken &RegTok = Parser.getTok();
432 SMLoc RegLoc = RegTok.getLoc();
433 if (RegTok.isNot(AsmToken::Identifier)) {
434 Error(RegLoc, "register expected");
437 int RegNum = TryParseRegister();
439 Error(RegLoc, "register expected");
443 unsigned RegList = 1 << RegNum;
445 int HighRegNum = RegNum;
446 // TODO ranges like "{Rn-Rm}"
447 while (Parser.getTok().is(AsmToken::Comma)) {
448 Parser.Lex(); // Eat comma token.
450 const AsmToken &RegTok = Parser.getTok();
451 SMLoc RegLoc = RegTok.getLoc();
452 if (RegTok.isNot(AsmToken::Identifier)) {
453 Error(RegLoc, "register expected");
456 int RegNum = TryParseRegister();
458 Error(RegLoc, "register expected");
462 if (RegList & (1 << RegNum))
463 Warning(RegLoc, "register duplicated in register list");
464 else if (RegNum <= HighRegNum)
465 Warning(RegLoc, "register not in ascending order in register list");
466 RegList |= 1 << RegNum;
469 const AsmToken &RCurlyTok = Parser.getTok();
470 if (RCurlyTok.isNot(AsmToken::RCurly)) {
471 Error(RCurlyTok.getLoc(), "'}' expected");
474 E = RCurlyTok.getLoc();
475 Parser.Lex(); // Eat left curly brace token.
477 // FIXME: Need to return an operand!
478 Error(E, "FIXME: register list parsing not implemented");
482 /// Parse an arm memory expression, return false if successful else return true
483 /// or an error. The first token must be a '[' when called.
484 /// TODO Only preindexing and postindexing addressing are started, unindexed
485 /// with option, etc are still to do.
486 ARMOperand *ARMAsmParser::ParseMemory() {
488 assert(Parser.getTok().is(AsmToken::LBrac) &&
489 "Token is not a Left Bracket");
490 S = Parser.getTok().getLoc();
491 Parser.Lex(); // Eat left bracket token.
493 const AsmToken &BaseRegTok = Parser.getTok();
494 if (BaseRegTok.isNot(AsmToken::Identifier)) {
495 Error(BaseRegTok.getLoc(), "register expected");
498 int BaseRegNum = TryParseRegister();
499 if (BaseRegNum == -1) {
500 Error(BaseRegTok.getLoc(), "register expected");
504 bool Preindexed = false;
505 bool Postindexed = false;
506 bool OffsetIsReg = false;
507 bool Negative = false;
508 bool Writeback = false;
510 // First look for preindexed address forms, that is after the "[Rn" we now
511 // have to see if the next token is a comma.
512 const AsmToken &Tok = Parser.getTok();
513 if (Tok.is(AsmToken::Comma)) {
515 Parser.Lex(); // Eat comma token.
517 bool OffsetRegShifted;
518 enum ShiftType ShiftType;
519 const MCExpr *ShiftAmount;
520 const MCExpr *Offset;
521 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
522 Offset, OffsetIsReg, OffsetRegNum, E))
524 const AsmToken &RBracTok = Parser.getTok();
525 if (RBracTok.isNot(AsmToken::RBrac)) {
526 Error(RBracTok.getLoc(), "']' expected");
529 E = RBracTok.getLoc();
530 Parser.Lex(); // Eat right bracket token.
532 const AsmToken &ExclaimTok = Parser.getTok();
533 if (ExclaimTok.is(AsmToken::Exclaim)) {
534 E = ExclaimTok.getLoc();
536 Parser.Lex(); // Eat exclaim token
538 return ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
539 OffsetRegShifted, ShiftType, ShiftAmount,
540 Preindexed, Postindexed, Negative, Writeback,
543 // The "[Rn" we have so far was not followed by a comma.
544 else if (Tok.is(AsmToken::RBrac)) {
545 // If there's anything other than the right brace, this is a post indexing
548 Parser.Lex(); // Eat right bracket token.
550 int OffsetRegNum = 0;
551 bool OffsetRegShifted = false;
552 enum ShiftType ShiftType;
553 const MCExpr *ShiftAmount;
554 const MCExpr *Offset = 0;
556 const AsmToken &NextTok = Parser.getTok();
557 if (NextTok.isNot(AsmToken::EndOfStatement)) {
560 if (NextTok.isNot(AsmToken::Comma)) {
561 Error(NextTok.getLoc(), "',' expected");
564 Parser.Lex(); // Eat comma token.
565 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
566 ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
571 return ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
572 OffsetRegShifted, ShiftType, ShiftAmount,
573 Preindexed, Postindexed, Negative, Writeback,
580 /// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
581 /// we will parse the following (were +/- means that a plus or minus is
586 /// we return false on success or an error otherwise.
587 bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
588 bool &OffsetRegShifted,
589 enum ShiftType &ShiftType,
590 const MCExpr *&ShiftAmount,
591 const MCExpr *&Offset,
596 OffsetRegShifted = false;
599 const AsmToken &NextTok = Parser.getTok();
600 E = NextTok.getLoc();
601 if (NextTok.is(AsmToken::Plus))
602 Parser.Lex(); // Eat plus token.
603 else if (NextTok.is(AsmToken::Minus)) {
605 Parser.Lex(); // Eat minus token
607 // See if there is a register following the "[Rn," or "[Rn]," we have so far.
608 const AsmToken &OffsetRegTok = Parser.getTok();
609 if (OffsetRegTok.is(AsmToken::Identifier)) {
610 SMLoc CurLoc = OffsetRegTok.getLoc();
611 OffsetRegNum = TryParseRegister();
612 if (OffsetRegNum != -1) {
618 // If we parsed a register as the offset then there can be a shift after that.
619 if (OffsetRegNum != -1) {
620 // Look for a comma then a shift
621 const AsmToken &Tok = Parser.getTok();
622 if (Tok.is(AsmToken::Comma)) {
623 Parser.Lex(); // Eat comma token.
625 const AsmToken &Tok = Parser.getTok();
626 if (ParseShift(ShiftType, ShiftAmount, E))
627 return Error(Tok.getLoc(), "shift expected");
628 OffsetRegShifted = true;
631 else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
632 // Look for #offset following the "[Rn," or "[Rn],"
633 const AsmToken &HashTok = Parser.getTok();
634 if (HashTok.isNot(AsmToken::Hash))
635 return Error(HashTok.getLoc(), "'#' expected");
637 Parser.Lex(); // Eat hash token.
639 if (getParser().ParseExpression(Offset))
641 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
646 /// ParseShift as one of these two:
647 /// ( lsl | lsr | asr | ror ) , # shift_amount
649 /// and returns true if it parses a shift otherwise it returns false.
650 bool ARMAsmParser::ParseShift(ShiftType &St, const MCExpr *&ShiftAmount,
652 const AsmToken &Tok = Parser.getTok();
653 if (Tok.isNot(AsmToken::Identifier))
655 StringRef ShiftName = Tok.getString();
656 if (ShiftName == "lsl" || ShiftName == "LSL")
658 else if (ShiftName == "lsr" || ShiftName == "LSR")
660 else if (ShiftName == "asr" || ShiftName == "ASR")
662 else if (ShiftName == "ror" || ShiftName == "ROR")
664 else if (ShiftName == "rrx" || ShiftName == "RRX")
668 Parser.Lex(); // Eat shift type token.
674 // Otherwise, there must be a '#' and a shift amount.
675 const AsmToken &HashTok = Parser.getTok();
676 if (HashTok.isNot(AsmToken::Hash))
677 return Error(HashTok.getLoc(), "'#' expected");
678 Parser.Lex(); // Eat hash token.
680 if (getParser().ParseExpression(ShiftAmount))
686 /// Parse a arm instruction operand. For now this parses the operand regardless
688 ARMOperand *ARMAsmParser::ParseOperand() {
691 switch (getLexer().getKind()) {
692 case AsmToken::Identifier:
693 if (ARMOperand *Op = TryParseRegisterWithWriteBack())
696 // This was not a register so parse other operands that start with an
697 // identifier (like labels) as expressions and create them as immediates.
699 S = Parser.getTok().getLoc();
700 if (getParser().ParseExpression(IdVal))
702 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
703 return ARMOperand::CreateImm(IdVal, S, E);
704 case AsmToken::LBrac:
705 return ParseMemory();
706 case AsmToken::LCurly:
707 return ParseRegisterList();
710 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
711 S = Parser.getTok().getLoc();
713 const MCExpr *ImmVal;
714 if (getParser().ParseExpression(ImmVal))
716 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
717 return ARMOperand::CreateImm(ImmVal, S, E);
719 Error(Parser.getTok().getLoc(), "unexpected token in operand");
724 /// Parse an arm instruction mnemonic followed by its operands.
725 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
726 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
727 // Create the leading tokens for the mnemonic, split by '.' characters.
728 size_t Start = 0, Next = Name.find('.');
729 StringRef Head = Name.slice(Start, Next);
731 // Determine the predicate, if any.
733 // FIXME: We need a way to check whether a prefix supports predication,
734 // otherwise we will end up with an ambiguity for instructions that happen to
735 // end with a predicate name.
736 // FIXME: Likewise, some arithmetic instructions have an 's' prefix which
737 // indicates to update the condition codes. Those instructions have an
738 // additional immediate operand which encodes the prefix as reg0 or CPSR.
739 // Just checking for a suffix of 's' definitely creates ambiguities; e.g,
740 // the SMMLS instruction.
741 unsigned CC = StringSwitch<unsigned>(Head.substr(Head.size()-2))
742 .Case("eq", ARMCC::EQ)
743 .Case("ne", ARMCC::NE)
744 .Case("hs", ARMCC::HS)
745 .Case("lo", ARMCC::LO)
746 .Case("mi", ARMCC::MI)
747 .Case("pl", ARMCC::PL)
748 .Case("vs", ARMCC::VS)
749 .Case("vc", ARMCC::VC)
750 .Case("hi", ARMCC::HI)
751 .Case("ls", ARMCC::LS)
752 .Case("ge", ARMCC::GE)
753 .Case("lt", ARMCC::LT)
754 .Case("gt", ARMCC::GT)
755 .Case("le", ARMCC::LE)
756 .Case("al", ARMCC::AL)
760 (CC == ARMCC::LS && (Head == "vmls" || Head == "vnmls"))) {
763 Head = Head.slice(0, Head.size() - 2);
766 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
767 // FIXME: Should only add this operand for predicated instructions
768 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), NameLoc));
770 // Add the remaining tokens in the mnemonic.
771 while (Next != StringRef::npos) {
773 Next = Name.find('.', Start + 1);
774 Head = Name.slice(Start, Next);
776 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
779 // Read the remaining operands.
780 if (getLexer().isNot(AsmToken::EndOfStatement)) {
781 // Read the first operand.
782 if (ARMOperand *Op = ParseOperand())
783 Operands.push_back(Op);
785 Parser.EatToEndOfStatement();
789 while (getLexer().is(AsmToken::Comma)) {
790 Parser.Lex(); // Eat the comma.
792 // Parse and remember the operand.
793 if (ARMOperand *Op = ParseOperand())
794 Operands.push_back(Op);
796 Parser.EatToEndOfStatement();
802 if (getLexer().isNot(AsmToken::EndOfStatement)) {
803 Parser.EatToEndOfStatement();
804 return TokError("unexpected token in argument list");
806 Parser.Lex(); // Consume the EndOfStatement
811 MatchAndEmitInstruction(SMLoc IDLoc,
812 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
816 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo)) {
818 Out.EmitInstruction(Inst);
821 case Match_MissingFeature:
822 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
824 case Match_InvalidOperand: {
825 SMLoc ErrorLoc = IDLoc;
826 if (ErrorInfo != ~0U) {
827 if (ErrorInfo >= Operands.size())
828 return Error(IDLoc, "too few operands for instruction");
830 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
831 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
834 return Error(ErrorLoc, "invalid operand for instruction");
836 case Match_MnemonicFail:
837 return Error(IDLoc, "unrecognized instruction mnemonic");
840 llvm_unreachable("Implement any new match types added!");
845 /// ParseDirective parses the arm specific directives
846 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
847 StringRef IDVal = DirectiveID.getIdentifier();
848 if (IDVal == ".word")
849 return ParseDirectiveWord(4, DirectiveID.getLoc());
850 else if (IDVal == ".thumb")
851 return ParseDirectiveThumb(DirectiveID.getLoc());
852 else if (IDVal == ".thumb_func")
853 return ParseDirectiveThumbFunc(DirectiveID.getLoc());
854 else if (IDVal == ".code")
855 return ParseDirectiveCode(DirectiveID.getLoc());
856 else if (IDVal == ".syntax")
857 return ParseDirectiveSyntax(DirectiveID.getLoc());
861 /// ParseDirectiveWord
862 /// ::= .word [ expression (, expression)* ]
863 bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
864 if (getLexer().isNot(AsmToken::EndOfStatement)) {
867 if (getParser().ParseExpression(Value))
870 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
872 if (getLexer().is(AsmToken::EndOfStatement))
875 // FIXME: Improve diagnostic.
876 if (getLexer().isNot(AsmToken::Comma))
877 return Error(L, "unexpected token in directive");
886 /// ParseDirectiveThumb
888 bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
889 if (getLexer().isNot(AsmToken::EndOfStatement))
890 return Error(L, "unexpected token in directive");
893 // TODO: set thumb mode
894 // TODO: tell the MC streamer the mode
895 // getParser().getStreamer().Emit???();
899 /// ParseDirectiveThumbFunc
900 /// ::= .thumbfunc symbol_name
901 bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
902 const AsmToken &Tok = Parser.getTok();
903 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
904 return Error(L, "unexpected token in .thumb_func directive");
905 StringRef Name = Tok.getString();
906 Parser.Lex(); // Consume the identifier token.
907 if (getLexer().isNot(AsmToken::EndOfStatement))
908 return Error(L, "unexpected token in directive");
911 // Mark symbol as a thumb symbol.
912 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
913 getParser().getStreamer().EmitThumbFunc(Func);
917 /// ParseDirectiveSyntax
918 /// ::= .syntax unified | divided
919 bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
920 const AsmToken &Tok = Parser.getTok();
921 if (Tok.isNot(AsmToken::Identifier))
922 return Error(L, "unexpected token in .syntax directive");
923 StringRef Mode = Tok.getString();
924 if (Mode == "unified" || Mode == "UNIFIED")
926 else if (Mode == "divided" || Mode == "DIVIDED")
929 return Error(L, "unrecognized syntax mode in .syntax directive");
931 if (getLexer().isNot(AsmToken::EndOfStatement))
932 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
935 // TODO tell the MC streamer the mode
936 // getParser().getStreamer().Emit???();
940 /// ParseDirectiveCode
941 /// ::= .code 16 | 32
942 bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
943 const AsmToken &Tok = Parser.getTok();
944 if (Tok.isNot(AsmToken::Integer))
945 return Error(L, "unexpected token in .code directive");
946 int64_t Val = Parser.getTok().getIntVal();
952 return Error(L, "invalid operand to .code directive");
954 if (getLexer().isNot(AsmToken::EndOfStatement))
955 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
959 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
961 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
966 extern "C" void LLVMInitializeARMAsmLexer();
968 /// Force static initialization.
969 extern "C" void LLVMInitializeARMAsmParser() {
970 RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
971 RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
972 LLVMInitializeARMAsmLexer();
975 #define GET_REGISTER_MATCHER
976 #define GET_MATCHER_IMPLEMENTATION
977 #include "ARMGenAsmMatcher.inc"