1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMBaseInfo.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMMCExpr.h"
13 #include "llvm/MC/MCParser/MCAsmLexer.h"
14 #include "llvm/MC/MCParser/MCAsmParser.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCAsmInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCTargetAsmParser.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/SourceMgr.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/ADT/BitVector.h"
30 #include "llvm/ADT/OwningPtr.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/StringExtras.h"
34 #include "llvm/ADT/StringSwitch.h"
35 #include "llvm/ADT/Twine.h"
43 class ARMAsmParser : public MCTargetAsmParser {
48 ARMCC::CondCodes Cond; // Condition for IT block.
49 unsigned Mask:4; // Condition mask for instructions.
50 // Starting at first 1 (from lsb).
51 // '1' condition as indicated in IT.
52 // '0' inverse of condition (else).
53 // Count of instructions in IT block is
54 // 4 - trailingzeroes(mask)
56 bool FirstCond; // Explicit flag for when we're parsing the
57 // First instruction in the IT block. It's
58 // implied in the mask, so needs special
61 unsigned CurPosition; // Current position in parsing of IT
62 // block. In range [0,3]. Initialized
63 // according to count of instructions in block.
64 // ~0U if no active IT block.
66 bool inITBlock() { return ITState.CurPosition != ~0U;}
67 void forwardITPosition() {
68 if (!inITBlock()) return;
69 // Move to the next instruction in the IT block, if there is one. If not,
70 // mark the block as done.
71 unsigned TZ = CountTrailingZeros_32(ITState.Mask);
72 if (++ITState.CurPosition == 5 - TZ)
73 ITState.CurPosition = ~0U; // Done with the IT block after this.
77 MCAsmParser &getParser() const { return Parser; }
78 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
80 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
81 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
83 int tryParseRegister();
84 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
85 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
86 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
87 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
88 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
89 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
90 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
91 unsigned &ShiftAmount);
92 bool parseDirectiveWord(unsigned Size, SMLoc L);
93 bool parseDirectiveThumb(SMLoc L);
94 bool parseDirectiveThumbFunc(SMLoc L);
95 bool parseDirectiveCode(SMLoc L);
96 bool parseDirectiveSyntax(SMLoc L);
98 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
99 bool &CarrySetting, unsigned &ProcessorIMod,
101 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
102 bool &CanAcceptPredicationCode);
104 bool isThumb() const {
105 // FIXME: Can tablegen auto-generate this?
106 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
108 bool isThumbOne() const {
109 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
111 bool isThumbTwo() const {
112 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
114 bool hasV6Ops() const {
115 return STI.getFeatureBits() & ARM::HasV6Ops;
117 bool hasV7Ops() const {
118 return STI.getFeatureBits() & ARM::HasV7Ops;
121 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
122 setAvailableFeatures(FB);
124 bool isMClass() const {
125 return STI.getFeatureBits() & ARM::FeatureMClass;
128 /// @name Auto-generated Match Functions
131 #define GET_ASSEMBLER_HEADER
132 #include "ARMGenAsmMatcher.inc"
136 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
137 OperandMatchResultTy parseCoprocNumOperand(
138 SmallVectorImpl<MCParsedAsmOperand*>&);
139 OperandMatchResultTy parseCoprocRegOperand(
140 SmallVectorImpl<MCParsedAsmOperand*>&);
141 OperandMatchResultTy parseMemBarrierOptOperand(
142 SmallVectorImpl<MCParsedAsmOperand*>&);
143 OperandMatchResultTy parseProcIFlagsOperand(
144 SmallVectorImpl<MCParsedAsmOperand*>&);
145 OperandMatchResultTy parseMSRMaskOperand(
146 SmallVectorImpl<MCParsedAsmOperand*>&);
147 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
148 StringRef Op, int Low, int High);
149 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
150 return parsePKHImm(O, "lsl", 0, 31);
152 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
153 return parsePKHImm(O, "asr", 1, 32);
155 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
156 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
157 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
158 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
159 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
160 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
162 // Asm Match Converter Methods
163 bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
164 const SmallVectorImpl<MCParsedAsmOperand*> &);
165 bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
166 const SmallVectorImpl<MCParsedAsmOperand*> &);
167 bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
168 const SmallVectorImpl<MCParsedAsmOperand*> &);
169 bool cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
170 const SmallVectorImpl<MCParsedAsmOperand*> &);
171 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
172 const SmallVectorImpl<MCParsedAsmOperand*> &);
173 bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
174 const SmallVectorImpl<MCParsedAsmOperand*> &);
175 bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
176 const SmallVectorImpl<MCParsedAsmOperand*> &);
177 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
178 const SmallVectorImpl<MCParsedAsmOperand*> &);
179 bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
180 const SmallVectorImpl<MCParsedAsmOperand*> &);
181 bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
182 const SmallVectorImpl<MCParsedAsmOperand*> &);
183 bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
184 const SmallVectorImpl<MCParsedAsmOperand*> &);
185 bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
186 const SmallVectorImpl<MCParsedAsmOperand*> &);
187 bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
188 const SmallVectorImpl<MCParsedAsmOperand*> &);
189 bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
190 const SmallVectorImpl<MCParsedAsmOperand*> &);
191 bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
192 const SmallVectorImpl<MCParsedAsmOperand*> &);
193 bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
194 const SmallVectorImpl<MCParsedAsmOperand*> &);
195 bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
196 const SmallVectorImpl<MCParsedAsmOperand*> &);
198 bool validateInstruction(MCInst &Inst,
199 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
200 void processInstruction(MCInst &Inst,
201 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
202 bool shouldOmitCCOutOperand(StringRef Mnemonic,
203 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
206 enum ARMMatchResultTy {
207 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
208 Match_RequiresNotITBlock,
213 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
214 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
215 MCAsmParserExtension::Initialize(_Parser);
217 // Initialize the set of available features.
218 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
220 // Not in an ITBlock to start with.
221 ITState.CurPosition = ~0U;
224 // Implementation of the MCTargetAsmParser interface:
225 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
226 bool ParseInstruction(StringRef Name, SMLoc NameLoc,
227 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
228 bool ParseDirective(AsmToken DirectiveID);
230 unsigned checkTargetMatchPredicate(MCInst &Inst);
232 bool MatchAndEmitInstruction(SMLoc IDLoc,
233 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
236 } // end anonymous namespace
240 /// ARMOperand - Instances of this class represent a parsed ARM machine
242 class ARMOperand : public MCParsedAsmOperand {
267 SMLoc StartLoc, EndLoc;
268 SmallVector<unsigned, 8> Registers;
272 ARMCC::CondCodes Val;
288 ARM_PROC::IFlags Val;
308 /// Combined record for all forms of ARM address expressions.
311 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
313 const MCConstantExpr *OffsetImm; // Offset immediate value
314 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
315 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
316 unsigned ShiftImm; // shift for OffsetReg.
317 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
323 ARM_AM::ShiftOpc ShiftTy;
332 ARM_AM::ShiftOpc ShiftTy;
338 ARM_AM::ShiftOpc ShiftTy;
351 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
353 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
355 StartLoc = o.StartLoc;
372 case DPRRegisterList:
373 case SPRRegisterList:
374 Registers = o.Registers;
389 case PostIndexRegister:
390 PostIdxReg = o.PostIdxReg;
398 case ShifterImmediate:
399 ShifterImm = o.ShifterImm;
401 case ShiftedRegister:
402 RegShiftedReg = o.RegShiftedReg;
404 case ShiftedImmediate:
405 RegShiftedImm = o.RegShiftedImm;
407 case RotateImmediate:
410 case BitfieldDescriptor:
411 Bitfield = o.Bitfield;
416 /// getStartLoc - Get the location of the first token of this operand.
417 SMLoc getStartLoc() const { return StartLoc; }
418 /// getEndLoc - Get the location of the last token of this operand.
419 SMLoc getEndLoc() const { return EndLoc; }
421 ARMCC::CondCodes getCondCode() const {
422 assert(Kind == CondCode && "Invalid access!");
426 unsigned getCoproc() const {
427 assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
431 StringRef getToken() const {
432 assert(Kind == Token && "Invalid access!");
433 return StringRef(Tok.Data, Tok.Length);
436 unsigned getReg() const {
437 assert((Kind == Register || Kind == CCOut) && "Invalid access!");
441 const SmallVectorImpl<unsigned> &getRegList() const {
442 assert((Kind == RegisterList || Kind == DPRRegisterList ||
443 Kind == SPRRegisterList) && "Invalid access!");
447 const MCExpr *getImm() const {
448 assert(Kind == Immediate && "Invalid access!");
452 ARM_MB::MemBOpt getMemBarrierOpt() const {
453 assert(Kind == MemBarrierOpt && "Invalid access!");
457 ARM_PROC::IFlags getProcIFlags() const {
458 assert(Kind == ProcIFlags && "Invalid access!");
462 unsigned getMSRMask() const {
463 assert(Kind == MSRMask && "Invalid access!");
467 bool isCoprocNum() const { return Kind == CoprocNum; }
468 bool isCoprocReg() const { return Kind == CoprocReg; }
469 bool isCondCode() const { return Kind == CondCode; }
470 bool isCCOut() const { return Kind == CCOut; }
471 bool isITMask() const { return Kind == ITCondMask; }
472 bool isITCondCode() const { return Kind == CondCode; }
473 bool isImm() const { return Kind == Immediate; }
474 bool isImm8s4() const {
475 if (Kind != Immediate)
477 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
478 if (!CE) return false;
479 int64_t Value = CE->getValue();
480 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
482 bool isImm0_1020s4() const {
483 if (Kind != Immediate)
485 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
486 if (!CE) return false;
487 int64_t Value = CE->getValue();
488 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
490 bool isImm0_508s4() const {
491 if (Kind != Immediate)
493 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
494 if (!CE) return false;
495 int64_t Value = CE->getValue();
496 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
498 bool isImm0_255() const {
499 if (Kind != Immediate)
501 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
502 if (!CE) return false;
503 int64_t Value = CE->getValue();
504 return Value >= 0 && Value < 256;
506 bool isImm0_7() const {
507 if (Kind != Immediate)
509 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
510 if (!CE) return false;
511 int64_t Value = CE->getValue();
512 return Value >= 0 && Value < 8;
514 bool isImm0_15() const {
515 if (Kind != Immediate)
517 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
518 if (!CE) return false;
519 int64_t Value = CE->getValue();
520 return Value >= 0 && Value < 16;
522 bool isImm0_31() const {
523 if (Kind != Immediate)
525 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
526 if (!CE) return false;
527 int64_t Value = CE->getValue();
528 return Value >= 0 && Value < 32;
530 bool isImm1_16() const {
531 if (Kind != Immediate)
533 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
534 if (!CE) return false;
535 int64_t Value = CE->getValue();
536 return Value > 0 && Value < 17;
538 bool isImm1_32() const {
539 if (Kind != Immediate)
541 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
542 if (!CE) return false;
543 int64_t Value = CE->getValue();
544 return Value > 0 && Value < 33;
546 bool isImm0_65535() const {
547 if (Kind != Immediate)
549 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
550 if (!CE) return false;
551 int64_t Value = CE->getValue();
552 return Value >= 0 && Value < 65536;
554 bool isImm0_65535Expr() const {
555 if (Kind != Immediate)
557 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
558 // If it's not a constant expression, it'll generate a fixup and be
560 if (!CE) return true;
561 int64_t Value = CE->getValue();
562 return Value >= 0 && Value < 65536;
564 bool isImm24bit() const {
565 if (Kind != Immediate)
567 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
568 if (!CE) return false;
569 int64_t Value = CE->getValue();
570 return Value >= 0 && Value <= 0xffffff;
572 bool isImmThumbSR() const {
573 if (Kind != Immediate)
575 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
576 if (!CE) return false;
577 int64_t Value = CE->getValue();
578 return Value > 0 && Value < 33;
580 bool isPKHLSLImm() const {
581 if (Kind != Immediate)
583 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
584 if (!CE) return false;
585 int64_t Value = CE->getValue();
586 return Value >= 0 && Value < 32;
588 bool isPKHASRImm() const {
589 if (Kind != Immediate)
591 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
592 if (!CE) return false;
593 int64_t Value = CE->getValue();
594 return Value > 0 && Value <= 32;
596 bool isARMSOImm() const {
597 if (Kind != Immediate)
599 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
600 if (!CE) return false;
601 int64_t Value = CE->getValue();
602 return ARM_AM::getSOImmVal(Value) != -1;
604 bool isT2SOImm() const {
605 if (Kind != Immediate)
607 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
608 if (!CE) return false;
609 int64_t Value = CE->getValue();
610 return ARM_AM::getT2SOImmVal(Value) != -1;
612 bool isSetEndImm() const {
613 if (Kind != Immediate)
615 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
616 if (!CE) return false;
617 int64_t Value = CE->getValue();
618 return Value == 1 || Value == 0;
620 bool isReg() const { return Kind == Register; }
621 bool isRegList() const { return Kind == RegisterList; }
622 bool isDPRRegList() const { return Kind == DPRRegisterList; }
623 bool isSPRRegList() const { return Kind == SPRRegisterList; }
624 bool isToken() const { return Kind == Token; }
625 bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
626 bool isMemory() const { return Kind == Memory; }
627 bool isShifterImm() const { return Kind == ShifterImmediate; }
628 bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
629 bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
630 bool isRotImm() const { return Kind == RotateImmediate; }
631 bool isBitfield() const { return Kind == BitfieldDescriptor; }
632 bool isPostIdxRegShifted() const { return Kind == PostIndexRegister; }
633 bool isPostIdxReg() const {
634 return Kind == PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
636 bool isMemNoOffset() const {
639 // No offset of any kind.
640 return Mem.OffsetRegNum == 0 && Mem.OffsetImm == 0;
642 bool isAddrMode2() const {
645 // Check for register offset.
646 if (Mem.OffsetRegNum) return true;
647 // Immediate offset in range [-4095, 4095].
648 if (!Mem.OffsetImm) return true;
649 int64_t Val = Mem.OffsetImm->getValue();
650 return Val > -4096 && Val < 4096;
652 bool isAM2OffsetImm() const {
653 if (Kind != Immediate)
655 // Immediate offset in range [-4095, 4095].
656 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
657 if (!CE) return false;
658 int64_t Val = CE->getValue();
659 return Val > -4096 && Val < 4096;
661 bool isAddrMode3() const {
664 // No shifts are legal for AM3.
665 if (Mem.ShiftType != ARM_AM::no_shift) return false;
666 // Check for register offset.
667 if (Mem.OffsetRegNum) return true;
668 // Immediate offset in range [-255, 255].
669 if (!Mem.OffsetImm) return true;
670 int64_t Val = Mem.OffsetImm->getValue();
671 return Val > -256 && Val < 256;
673 bool isAM3Offset() const {
674 if (Kind != Immediate && Kind != PostIndexRegister)
676 if (Kind == PostIndexRegister)
677 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
678 // Immediate offset in range [-255, 255].
679 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
680 if (!CE) return false;
681 int64_t Val = CE->getValue();
682 // Special case, #-0 is INT32_MIN.
683 return (Val > -256 && Val < 256) || Val == INT32_MIN;
685 bool isAddrMode5() const {
688 // Check for register offset.
689 if (Mem.OffsetRegNum) return false;
690 // Immediate offset in range [-1020, 1020] and a multiple of 4.
691 if (!Mem.OffsetImm) return true;
692 int64_t Val = Mem.OffsetImm->getValue();
693 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
696 bool isMemTBB() const {
697 if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative ||
698 Mem.ShiftType != ARM_AM::no_shift)
702 bool isMemTBH() const {
703 if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative ||
704 Mem.ShiftType != ARM_AM::lsl || Mem.ShiftImm != 1)
708 bool isMemRegOffset() const {
709 if (Kind != Memory || !Mem.OffsetRegNum)
713 bool isT2MemRegOffset() const {
714 if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative)
716 // Only lsl #{0, 1, 2, 3} allowed.
717 if (Mem.ShiftType == ARM_AM::no_shift)
719 if (Mem.ShiftType != ARM_AM::lsl || Mem.ShiftImm > 3)
723 bool isMemThumbRR() const {
724 // Thumb reg+reg addressing is simple. Just two registers, a base and
725 // an offset. No shifts, negations or any other complicating factors.
726 if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative ||
727 Mem.ShiftType != ARM_AM::no_shift)
729 return isARMLowRegister(Mem.BaseRegNum) &&
730 (!Mem.OffsetRegNum || isARMLowRegister(Mem.OffsetRegNum));
732 bool isMemThumbRIs4() const {
733 if (Kind != Memory || Mem.OffsetRegNum != 0 ||
734 !isARMLowRegister(Mem.BaseRegNum))
736 // Immediate offset, multiple of 4 in range [0, 124].
737 if (!Mem.OffsetImm) return true;
738 int64_t Val = Mem.OffsetImm->getValue();
739 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
741 bool isMemThumbRIs2() const {
742 if (Kind != Memory || Mem.OffsetRegNum != 0 ||
743 !isARMLowRegister(Mem.BaseRegNum))
745 // Immediate offset, multiple of 4 in range [0, 62].
746 if (!Mem.OffsetImm) return true;
747 int64_t Val = Mem.OffsetImm->getValue();
748 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
750 bool isMemThumbRIs1() const {
751 if (Kind != Memory || Mem.OffsetRegNum != 0 ||
752 !isARMLowRegister(Mem.BaseRegNum))
754 // Immediate offset in range [0, 31].
755 if (!Mem.OffsetImm) return true;
756 int64_t Val = Mem.OffsetImm->getValue();
757 return Val >= 0 && Val <= 31;
759 bool isMemThumbSPI() const {
760 if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP)
762 // Immediate offset, multiple of 4 in range [0, 1020].
763 if (!Mem.OffsetImm) return true;
764 int64_t Val = Mem.OffsetImm->getValue();
765 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
767 bool isMemImm8s4Offset() const {
768 if (Kind != Memory || Mem.OffsetRegNum != 0)
770 // Immediate offset a multiple of 4 in range [-1020, 1020].
771 if (!Mem.OffsetImm) return true;
772 int64_t Val = Mem.OffsetImm->getValue();
773 return Val >= -1020 && Val <= 1020 && (Val & 3) == 0;
775 bool isMemImm0_1020s4Offset() const {
776 if (Kind != Memory || Mem.OffsetRegNum != 0)
778 // Immediate offset a multiple of 4 in range [0, 1020].
779 if (!Mem.OffsetImm) return true;
780 int64_t Val = Mem.OffsetImm->getValue();
781 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
783 bool isMemImm8Offset() const {
784 if (Kind != Memory || Mem.OffsetRegNum != 0)
786 // Immediate offset in range [-255, 255].
787 if (!Mem.OffsetImm) return true;
788 int64_t Val = Mem.OffsetImm->getValue();
789 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
791 bool isMemPosImm8Offset() const {
792 if (Kind != Memory || Mem.OffsetRegNum != 0)
794 // Immediate offset in range [0, 255].
795 if (!Mem.OffsetImm) return true;
796 int64_t Val = Mem.OffsetImm->getValue();
797 return Val >= 0 && Val < 256;
799 bool isMemNegImm8Offset() const {
800 if (Kind != Memory || Mem.OffsetRegNum != 0)
802 // Immediate offset in range [-255, -1].
803 if (!Mem.OffsetImm) return true;
804 int64_t Val = Mem.OffsetImm->getValue();
805 return Val > -256 && Val < 0;
807 bool isMemUImm12Offset() const {
808 // If we have an immediate that's not a constant, treat it as a label
809 // reference needing a fixup. If it is a constant, it's something else
811 if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
814 if (Kind != Memory || Mem.OffsetRegNum != 0)
816 // Immediate offset in range [0, 4095].
817 if (!Mem.OffsetImm) return true;
818 int64_t Val = Mem.OffsetImm->getValue();
819 return (Val >= 0 && Val < 4096);
821 bool isMemImm12Offset() const {
822 // If we have an immediate that's not a constant, treat it as a label
823 // reference needing a fixup. If it is a constant, it's something else
825 if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
828 if (Kind != Memory || Mem.OffsetRegNum != 0)
830 // Immediate offset in range [-4095, 4095].
831 if (!Mem.OffsetImm) return true;
832 int64_t Val = Mem.OffsetImm->getValue();
833 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
835 bool isPostIdxImm8() const {
836 if (Kind != Immediate)
838 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
839 if (!CE) return false;
840 int64_t Val = CE->getValue();
841 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
844 bool isMSRMask() const { return Kind == MSRMask; }
845 bool isProcIFlags() const { return Kind == ProcIFlags; }
847 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
848 // Add as immediates when possible. Null MCExpr = 0.
850 Inst.addOperand(MCOperand::CreateImm(0));
851 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
852 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
854 Inst.addOperand(MCOperand::CreateExpr(Expr));
857 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
858 assert(N == 2 && "Invalid number of operands!");
859 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
860 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
861 Inst.addOperand(MCOperand::CreateReg(RegNum));
864 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
865 assert(N == 1 && "Invalid number of operands!");
866 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
869 void addITMaskOperands(MCInst &Inst, unsigned N) const {
870 assert(N == 1 && "Invalid number of operands!");
871 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
874 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
875 assert(N == 1 && "Invalid number of operands!");
876 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
879 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
880 assert(N == 1 && "Invalid number of operands!");
881 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
884 void addCCOutOperands(MCInst &Inst, unsigned N) const {
885 assert(N == 1 && "Invalid number of operands!");
886 Inst.addOperand(MCOperand::CreateReg(getReg()));
889 void addRegOperands(MCInst &Inst, unsigned N) const {
890 assert(N == 1 && "Invalid number of operands!");
891 Inst.addOperand(MCOperand::CreateReg(getReg()));
894 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
895 assert(N == 3 && "Invalid number of operands!");
896 assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
897 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
898 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
899 Inst.addOperand(MCOperand::CreateImm(
900 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
903 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
904 assert(N == 2 && "Invalid number of operands!");
905 assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
906 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
907 Inst.addOperand(MCOperand::CreateImm(
908 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
911 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
912 assert(N == 1 && "Invalid number of operands!");
913 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
917 void addRegListOperands(MCInst &Inst, unsigned N) const {
918 assert(N == 1 && "Invalid number of operands!");
919 const SmallVectorImpl<unsigned> &RegList = getRegList();
920 for (SmallVectorImpl<unsigned>::const_iterator
921 I = RegList.begin(), E = RegList.end(); I != E; ++I)
922 Inst.addOperand(MCOperand::CreateReg(*I));
925 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
926 addRegListOperands(Inst, N);
929 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
930 addRegListOperands(Inst, N);
933 void addRotImmOperands(MCInst &Inst, unsigned N) const {
934 assert(N == 1 && "Invalid number of operands!");
935 // Encoded as val>>3. The printer handles display as 8, 16, 24.
936 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
939 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
940 assert(N == 1 && "Invalid number of operands!");
941 // Munge the lsb/width into a bitfield mask.
942 unsigned lsb = Bitfield.LSB;
943 unsigned width = Bitfield.Width;
944 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
945 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
946 (32 - (lsb + width)));
947 Inst.addOperand(MCOperand::CreateImm(Mask));
950 void addImmOperands(MCInst &Inst, unsigned N) const {
951 assert(N == 1 && "Invalid number of operands!");
952 addExpr(Inst, getImm());
955 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
956 assert(N == 1 && "Invalid number of operands!");
957 // FIXME: We really want to scale the value here, but the LDRD/STRD
958 // instruction don't encode operands that way yet.
959 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
960 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
963 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
964 assert(N == 1 && "Invalid number of operands!");
965 // The immediate is scaled by four in the encoding and is stored
966 // in the MCInst as such. Lop off the low two bits here.
967 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
968 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
971 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
972 assert(N == 1 && "Invalid number of operands!");
973 // The immediate is scaled by four in the encoding and is stored
974 // in the MCInst as such. Lop off the low two bits here.
975 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
976 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
979 void addImm0_255Operands(MCInst &Inst, unsigned N) const {
980 assert(N == 1 && "Invalid number of operands!");
981 addExpr(Inst, getImm());
984 void addImm0_7Operands(MCInst &Inst, unsigned N) const {
985 assert(N == 1 && "Invalid number of operands!");
986 addExpr(Inst, getImm());
989 void addImm0_15Operands(MCInst &Inst, unsigned N) const {
990 assert(N == 1 && "Invalid number of operands!");
991 addExpr(Inst, getImm());
994 void addImm0_31Operands(MCInst &Inst, unsigned N) const {
995 assert(N == 1 && "Invalid number of operands!");
996 addExpr(Inst, getImm());
999 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1000 assert(N == 1 && "Invalid number of operands!");
1001 // The constant encodes as the immediate-1, and we store in the instruction
1002 // the bits as encoded, so subtract off one here.
1003 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1004 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1007 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1008 assert(N == 1 && "Invalid number of operands!");
1009 // The constant encodes as the immediate-1, and we store in the instruction
1010 // the bits as encoded, so subtract off one here.
1011 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1012 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1015 void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
1016 assert(N == 1 && "Invalid number of operands!");
1017 addExpr(Inst, getImm());
1020 void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
1021 assert(N == 1 && "Invalid number of operands!");
1022 addExpr(Inst, getImm());
1025 void addImm24bitOperands(MCInst &Inst, unsigned N) const {
1026 assert(N == 1 && "Invalid number of operands!");
1027 addExpr(Inst, getImm());
1030 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1031 assert(N == 1 && "Invalid number of operands!");
1032 // The constant encodes as the immediate, except for 32, which encodes as
1034 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1035 unsigned Imm = CE->getValue();
1036 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1039 void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
1040 assert(N == 1 && "Invalid number of operands!");
1041 addExpr(Inst, getImm());
1044 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1045 assert(N == 1 && "Invalid number of operands!");
1046 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1047 // the instruction as well.
1048 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1049 int Val = CE->getValue();
1050 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1053 void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
1054 assert(N == 1 && "Invalid number of operands!");
1055 addExpr(Inst, getImm());
1058 void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
1059 assert(N == 1 && "Invalid number of operands!");
1060 addExpr(Inst, getImm());
1063 void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
1064 assert(N == 1 && "Invalid number of operands!");
1065 addExpr(Inst, getImm());
1068 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1069 assert(N == 1 && "Invalid number of operands!");
1070 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1073 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1074 assert(N == 1 && "Invalid number of operands!");
1075 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1078 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1079 assert(N == 3 && "Invalid number of operands!");
1080 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1081 if (!Mem.OffsetRegNum) {
1082 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1083 // Special case for #-0
1084 if (Val == INT32_MIN) Val = 0;
1085 if (Val < 0) Val = -Val;
1086 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1088 // For register offset, we encode the shift type and negation flag
1090 Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
1091 Mem.ShiftImm, Mem.ShiftType);
1093 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1094 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1095 Inst.addOperand(MCOperand::CreateImm(Val));
1098 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1099 assert(N == 2 && "Invalid number of operands!");
1100 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1101 assert(CE && "non-constant AM2OffsetImm operand!");
1102 int32_t Val = CE->getValue();
1103 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1104 // Special case for #-0
1105 if (Val == INT32_MIN) Val = 0;
1106 if (Val < 0) Val = -Val;
1107 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1108 Inst.addOperand(MCOperand::CreateReg(0));
1109 Inst.addOperand(MCOperand::CreateImm(Val));
1112 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1113 assert(N == 3 && "Invalid number of operands!");
1114 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1115 if (!Mem.OffsetRegNum) {
1116 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1117 // Special case for #-0
1118 if (Val == INT32_MIN) Val = 0;
1119 if (Val < 0) Val = -Val;
1120 Val = ARM_AM::getAM3Opc(AddSub, Val);
1122 // For register offset, we encode the shift type and negation flag
1124 Val = ARM_AM::getAM3Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1126 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1127 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1128 Inst.addOperand(MCOperand::CreateImm(Val));
1131 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1132 assert(N == 2 && "Invalid number of operands!");
1133 if (Kind == PostIndexRegister) {
1135 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1136 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1137 Inst.addOperand(MCOperand::CreateImm(Val));
1142 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1143 int32_t Val = CE->getValue();
1144 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1145 // Special case for #-0
1146 if (Val == INT32_MIN) Val = 0;
1147 if (Val < 0) Val = -Val;
1148 Val = ARM_AM::getAM3Opc(AddSub, Val);
1149 Inst.addOperand(MCOperand::CreateReg(0));
1150 Inst.addOperand(MCOperand::CreateImm(Val));
1153 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1154 assert(N == 2 && "Invalid number of operands!");
1155 // The lower two bits are always zero and as such are not encoded.
1156 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0;
1157 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1158 // Special case for #-0
1159 if (Val == INT32_MIN) Val = 0;
1160 if (Val < 0) Val = -Val;
1161 Val = ARM_AM::getAM5Opc(AddSub, Val);
1162 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1163 Inst.addOperand(MCOperand::CreateImm(Val));
1166 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1167 assert(N == 2 && "Invalid number of operands!");
1168 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1169 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1170 Inst.addOperand(MCOperand::CreateImm(Val));
1173 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1174 assert(N == 2 && "Invalid number of operands!");
1175 // The lower two bits are always zero and as such are not encoded.
1176 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0;
1177 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1178 Inst.addOperand(MCOperand::CreateImm(Val));
1181 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1182 assert(N == 2 && "Invalid number of operands!");
1183 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1184 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1185 Inst.addOperand(MCOperand::CreateImm(Val));
1188 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1189 addMemImm8OffsetOperands(Inst, N);
1192 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1193 addMemImm8OffsetOperands(Inst, N);
1196 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1197 assert(N == 2 && "Invalid number of operands!");
1198 // If this is an immediate, it's a label reference.
1199 if (Kind == Immediate) {
1200 addExpr(Inst, getImm());
1201 Inst.addOperand(MCOperand::CreateImm(0));
1205 // Otherwise, it's a normal memory reg+offset.
1206 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1207 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1208 Inst.addOperand(MCOperand::CreateImm(Val));
1211 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1212 assert(N == 2 && "Invalid number of operands!");
1213 // If this is an immediate, it's a label reference.
1214 if (Kind == Immediate) {
1215 addExpr(Inst, getImm());
1216 Inst.addOperand(MCOperand::CreateImm(0));
1220 // Otherwise, it's a normal memory reg+offset.
1221 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1222 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1223 Inst.addOperand(MCOperand::CreateImm(Val));
1226 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1227 assert(N == 2 && "Invalid number of operands!");
1228 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1229 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1232 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
1233 assert(N == 2 && "Invalid number of operands!");
1234 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1235 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1238 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1239 assert(N == 3 && "Invalid number of operands!");
1240 unsigned Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
1241 Mem.ShiftImm, Mem.ShiftType);
1242 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1243 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1244 Inst.addOperand(MCOperand::CreateImm(Val));
1247 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1248 assert(N == 3 && "Invalid number of operands!");
1249 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1250 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1251 Inst.addOperand(MCOperand::CreateImm(Mem.ShiftImm));
1254 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1255 assert(N == 2 && "Invalid number of operands!");
1256 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1257 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1260 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1261 assert(N == 2 && "Invalid number of operands!");
1262 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1263 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1264 Inst.addOperand(MCOperand::CreateImm(Val));
1267 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1268 assert(N == 2 && "Invalid number of operands!");
1269 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 2) : 0;
1270 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1271 Inst.addOperand(MCOperand::CreateImm(Val));
1274 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1275 assert(N == 2 && "Invalid number of operands!");
1276 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue()) : 0;
1277 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1278 Inst.addOperand(MCOperand::CreateImm(Val));
1281 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1282 assert(N == 2 && "Invalid number of operands!");
1283 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1284 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1285 Inst.addOperand(MCOperand::CreateImm(Val));
1288 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1289 assert(N == 1 && "Invalid number of operands!");
1290 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1291 assert(CE && "non-constant post-idx-imm8 operand!");
1292 int Imm = CE->getValue();
1293 bool isAdd = Imm >= 0;
1294 if (Imm == INT32_MIN) Imm = 0;
1295 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1296 Inst.addOperand(MCOperand::CreateImm(Imm));
1299 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1300 assert(N == 2 && "Invalid number of operands!");
1301 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1302 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1305 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1306 assert(N == 2 && "Invalid number of operands!");
1307 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1308 // The sign, shift type, and shift amount are encoded in a single operand
1309 // using the AM2 encoding helpers.
1310 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1311 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1312 PostIdxReg.ShiftTy);
1313 Inst.addOperand(MCOperand::CreateImm(Imm));
1316 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1317 assert(N == 1 && "Invalid number of operands!");
1318 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1321 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1322 assert(N == 1 && "Invalid number of operands!");
1323 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1326 virtual void print(raw_ostream &OS) const;
1328 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
1329 ARMOperand *Op = new ARMOperand(ITCondMask);
1330 Op->ITMask.Mask = Mask;
1336 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1337 ARMOperand *Op = new ARMOperand(CondCode);
1344 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1345 ARMOperand *Op = new ARMOperand(CoprocNum);
1346 Op->Cop.Val = CopVal;
1352 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1353 ARMOperand *Op = new ARMOperand(CoprocReg);
1354 Op->Cop.Val = CopVal;
1360 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1361 ARMOperand *Op = new ARMOperand(CCOut);
1362 Op->Reg.RegNum = RegNum;
1368 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1369 ARMOperand *Op = new ARMOperand(Token);
1370 Op->Tok.Data = Str.data();
1371 Op->Tok.Length = Str.size();
1377 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1378 ARMOperand *Op = new ARMOperand(Register);
1379 Op->Reg.RegNum = RegNum;
1385 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1390 ARMOperand *Op = new ARMOperand(ShiftedRegister);
1391 Op->RegShiftedReg.ShiftTy = ShTy;
1392 Op->RegShiftedReg.SrcReg = SrcReg;
1393 Op->RegShiftedReg.ShiftReg = ShiftReg;
1394 Op->RegShiftedReg.ShiftImm = ShiftImm;
1400 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1404 ARMOperand *Op = new ARMOperand(ShiftedImmediate);
1405 Op->RegShiftedImm.ShiftTy = ShTy;
1406 Op->RegShiftedImm.SrcReg = SrcReg;
1407 Op->RegShiftedImm.ShiftImm = ShiftImm;
1413 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1415 ARMOperand *Op = new ARMOperand(ShifterImmediate);
1416 Op->ShifterImm.isASR = isASR;
1417 Op->ShifterImm.Imm = Imm;
1423 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1424 ARMOperand *Op = new ARMOperand(RotateImmediate);
1425 Op->RotImm.Imm = Imm;
1431 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1433 ARMOperand *Op = new ARMOperand(BitfieldDescriptor);
1434 Op->Bitfield.LSB = LSB;
1435 Op->Bitfield.Width = Width;
1442 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1443 SMLoc StartLoc, SMLoc EndLoc) {
1444 KindTy Kind = RegisterList;
1446 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
1447 Kind = DPRRegisterList;
1448 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
1449 contains(Regs.front().first))
1450 Kind = SPRRegisterList;
1452 ARMOperand *Op = new ARMOperand(Kind);
1453 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1454 I = Regs.begin(), E = Regs.end(); I != E; ++I)
1455 Op->Registers.push_back(I->first);
1456 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1457 Op->StartLoc = StartLoc;
1458 Op->EndLoc = EndLoc;
1462 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1463 ARMOperand *Op = new ARMOperand(Immediate);
1470 static ARMOperand *CreateMem(unsigned BaseRegNum,
1471 const MCConstantExpr *OffsetImm,
1472 unsigned OffsetRegNum,
1473 ARM_AM::ShiftOpc ShiftType,
1477 ARMOperand *Op = new ARMOperand(Memory);
1478 Op->Mem.BaseRegNum = BaseRegNum;
1479 Op->Mem.OffsetImm = OffsetImm;
1480 Op->Mem.OffsetRegNum = OffsetRegNum;
1481 Op->Mem.ShiftType = ShiftType;
1482 Op->Mem.ShiftImm = ShiftImm;
1483 Op->Mem.isNegative = isNegative;
1489 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1490 ARM_AM::ShiftOpc ShiftTy,
1493 ARMOperand *Op = new ARMOperand(PostIndexRegister);
1494 Op->PostIdxReg.RegNum = RegNum;
1495 Op->PostIdxReg.isAdd = isAdd;
1496 Op->PostIdxReg.ShiftTy = ShiftTy;
1497 Op->PostIdxReg.ShiftImm = ShiftImm;
1503 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1504 ARMOperand *Op = new ARMOperand(MemBarrierOpt);
1505 Op->MBOpt.Val = Opt;
1511 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1512 ARMOperand *Op = new ARMOperand(ProcIFlags);
1513 Op->IFlags.Val = IFlags;
1519 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1520 ARMOperand *Op = new ARMOperand(MSRMask);
1521 Op->MMask.Val = MMask;
1528 } // end anonymous namespace.
1530 void ARMOperand::print(raw_ostream &OS) const {
1533 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1536 OS << "<ccout " << getReg() << ">";
1539 static char MaskStr[][6] = { "()", "(t)", "(e)", "(tt)", "(et)", "(te)",
1540 "(ee)", "(ttt)", "(ett)", "(tet)", "(eet)", "(tte)", "(ete)",
1542 assert((ITMask.Mask & 0xf) == ITMask.Mask);
1543 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
1547 OS << "<coprocessor number: " << getCoproc() << ">";
1550 OS << "<coprocessor register: " << getCoproc() << ">";
1553 OS << "<mask: " << getMSRMask() << ">";
1556 getImm()->print(OS);
1559 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1563 << " base:" << Mem.BaseRegNum;
1566 case PostIndexRegister:
1567 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
1568 << PostIdxReg.RegNum;
1569 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1570 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1571 << PostIdxReg.ShiftImm;
1575 OS << "<ARM_PROC::";
1576 unsigned IFlags = getProcIFlags();
1577 for (int i=2; i >= 0; --i)
1578 if (IFlags & (1 << i))
1579 OS << ARM_PROC::IFlagsToString(1 << i);
1584 OS << "<register " << getReg() << ">";
1586 case ShifterImmediate:
1587 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1588 << " #" << ShifterImm.Imm << ">";
1590 case ShiftedRegister:
1591 OS << "<so_reg_reg "
1592 << RegShiftedReg.SrcReg
1593 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1594 << ", " << RegShiftedReg.ShiftReg << ", "
1595 << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1598 case ShiftedImmediate:
1599 OS << "<so_reg_imm "
1600 << RegShiftedImm.SrcReg
1601 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1602 << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
1605 case RotateImmediate:
1606 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
1608 case BitfieldDescriptor:
1609 OS << "<bitfield " << "lsb: " << Bitfield.LSB
1610 << ", width: " << Bitfield.Width << ">";
1613 case DPRRegisterList:
1614 case SPRRegisterList: {
1615 OS << "<register_list ";
1617 const SmallVectorImpl<unsigned> &RegList = getRegList();
1618 for (SmallVectorImpl<unsigned>::const_iterator
1619 I = RegList.begin(), E = RegList.end(); I != E; ) {
1621 if (++I < E) OS << ", ";
1628 OS << "'" << getToken() << "'";
1633 /// @name Auto-generated Match Functions
1636 static unsigned MatchRegisterName(StringRef Name);
1640 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
1641 SMLoc &StartLoc, SMLoc &EndLoc) {
1642 RegNo = tryParseRegister();
1644 return (RegNo == (unsigned)-1);
1647 /// Try to parse a register name. The token must be an Identifier when called,
1648 /// and if it is a register name the token is eaten and the register number is
1649 /// returned. Otherwise return -1.
1651 int ARMAsmParser::tryParseRegister() {
1652 const AsmToken &Tok = Parser.getTok();
1653 if (Tok.isNot(AsmToken::Identifier)) return -1;
1655 // FIXME: Validate register for the current architecture; we have to do
1656 // validation later, so maybe there is no need for this here.
1657 std::string upperCase = Tok.getString().str();
1658 std::string lowerCase = LowercaseString(upperCase);
1659 unsigned RegNum = MatchRegisterName(lowerCase);
1661 RegNum = StringSwitch<unsigned>(lowerCase)
1662 .Case("r13", ARM::SP)
1663 .Case("r14", ARM::LR)
1664 .Case("r15", ARM::PC)
1665 .Case("ip", ARM::R12)
1668 if (!RegNum) return -1;
1670 Parser.Lex(); // Eat identifier token.
1674 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
1675 // If a recoverable error occurs, return 1. If an irrecoverable error
1676 // occurs, return -1. An irrecoverable error is one where tokens have been
1677 // consumed in the process of trying to parse the shifter (i.e., when it is
1678 // indeed a shifter operand, but malformed).
1679 int ARMAsmParser::tryParseShiftRegister(
1680 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1681 SMLoc S = Parser.getTok().getLoc();
1682 const AsmToken &Tok = Parser.getTok();
1683 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1685 std::string upperCase = Tok.getString().str();
1686 std::string lowerCase = LowercaseString(upperCase);
1687 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
1688 .Case("lsl", ARM_AM::lsl)
1689 .Case("lsr", ARM_AM::lsr)
1690 .Case("asr", ARM_AM::asr)
1691 .Case("ror", ARM_AM::ror)
1692 .Case("rrx", ARM_AM::rrx)
1693 .Default(ARM_AM::no_shift);
1695 if (ShiftTy == ARM_AM::no_shift)
1698 Parser.Lex(); // Eat the operator.
1700 // The source register for the shift has already been added to the
1701 // operand list, so we need to pop it off and combine it into the shifted
1702 // register operand instead.
1703 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
1704 if (!PrevOp->isReg())
1705 return Error(PrevOp->getStartLoc(), "shift must be of a register");
1706 int SrcReg = PrevOp->getReg();
1709 if (ShiftTy == ARM_AM::rrx) {
1710 // RRX Doesn't have an explicit shift amount. The encoder expects
1711 // the shift register to be the same as the source register. Seems odd,
1715 // Figure out if this is shifted by a constant or a register (for non-RRX).
1716 if (Parser.getTok().is(AsmToken::Hash)) {
1717 Parser.Lex(); // Eat hash.
1718 SMLoc ImmLoc = Parser.getTok().getLoc();
1719 const MCExpr *ShiftExpr = 0;
1720 if (getParser().ParseExpression(ShiftExpr)) {
1721 Error(ImmLoc, "invalid immediate shift value");
1724 // The expression must be evaluatable as an immediate.
1725 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
1727 Error(ImmLoc, "invalid immediate shift value");
1730 // Range check the immediate.
1731 // lsl, ror: 0 <= imm <= 31
1732 // lsr, asr: 0 <= imm <= 32
1733 Imm = CE->getValue();
1735 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
1736 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
1737 Error(ImmLoc, "immediate shift value out of range");
1740 } else if (Parser.getTok().is(AsmToken::Identifier)) {
1741 ShiftReg = tryParseRegister();
1742 SMLoc L = Parser.getTok().getLoc();
1743 if (ShiftReg == -1) {
1744 Error (L, "expected immediate or register in shift operand");
1748 Error (Parser.getTok().getLoc(),
1749 "expected immediate or register in shift operand");
1754 if (ShiftReg && ShiftTy != ARM_AM::rrx)
1755 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
1757 S, Parser.getTok().getLoc()));
1759 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
1760 S, Parser.getTok().getLoc()));
1766 /// Try to parse a register name. The token must be an Identifier when called.
1767 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
1768 /// if there is a "writeback". 'true' if it's not a register.
1770 /// TODO this is likely to change to allow different register types and or to
1771 /// parse for a specific register type.
1773 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1774 SMLoc S = Parser.getTok().getLoc();
1775 int RegNo = tryParseRegister();
1779 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1781 const AsmToken &ExclaimTok = Parser.getTok();
1782 if (ExclaimTok.is(AsmToken::Exclaim)) {
1783 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
1784 ExclaimTok.getLoc()));
1785 Parser.Lex(); // Eat exclaim token
1791 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
1792 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
1794 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
1795 // Use the same layout as the tablegen'erated register name matcher. Ugly,
1797 switch (Name.size()) {
1800 if (Name[0] != CoprocOp)
1817 if (Name[0] != CoprocOp || Name[1] != '1')
1821 case '0': return 10;
1822 case '1': return 11;
1823 case '2': return 12;
1824 case '3': return 13;
1825 case '4': return 14;
1826 case '5': return 15;
1834 /// parseITCondCode - Try to parse a condition code for an IT instruction.
1835 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1836 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1837 SMLoc S = Parser.getTok().getLoc();
1838 const AsmToken &Tok = Parser.getTok();
1839 if (!Tok.is(AsmToken::Identifier))
1840 return MatchOperand_NoMatch;
1841 unsigned CC = StringSwitch<unsigned>(Tok.getString())
1842 .Case("eq", ARMCC::EQ)
1843 .Case("ne", ARMCC::NE)
1844 .Case("hs", ARMCC::HS)
1845 .Case("cs", ARMCC::HS)
1846 .Case("lo", ARMCC::LO)
1847 .Case("cc", ARMCC::LO)
1848 .Case("mi", ARMCC::MI)
1849 .Case("pl", ARMCC::PL)
1850 .Case("vs", ARMCC::VS)
1851 .Case("vc", ARMCC::VC)
1852 .Case("hi", ARMCC::HI)
1853 .Case("ls", ARMCC::LS)
1854 .Case("ge", ARMCC::GE)
1855 .Case("lt", ARMCC::LT)
1856 .Case("gt", ARMCC::GT)
1857 .Case("le", ARMCC::LE)
1858 .Case("al", ARMCC::AL)
1861 return MatchOperand_NoMatch;
1862 Parser.Lex(); // Eat the token.
1864 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
1866 return MatchOperand_Success;
1869 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
1870 /// token must be an Identifier when called, and if it is a coprocessor
1871 /// number, the token is eaten and the operand is added to the operand list.
1872 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1873 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1874 SMLoc S = Parser.getTok().getLoc();
1875 const AsmToken &Tok = Parser.getTok();
1876 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1878 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
1880 return MatchOperand_NoMatch;
1882 Parser.Lex(); // Eat identifier token.
1883 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
1884 return MatchOperand_Success;
1887 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
1888 /// token must be an Identifier when called, and if it is a coprocessor
1889 /// number, the token is eaten and the operand is added to the operand list.
1890 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1891 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1892 SMLoc S = Parser.getTok().getLoc();
1893 const AsmToken &Tok = Parser.getTok();
1894 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1896 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
1898 return MatchOperand_NoMatch;
1900 Parser.Lex(); // Eat identifier token.
1901 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
1902 return MatchOperand_Success;
1905 // For register list parsing, we need to map from raw GPR register numbering
1906 // to the enumeration values. The enumeration values aren't sorted by
1907 // register number due to our using "sp", "lr" and "pc" as canonical names.
1908 static unsigned getNextRegister(unsigned Reg) {
1909 // If this is a GPR, we need to do it manually, otherwise we can rely
1910 // on the sort ordering of the enumeration since the other reg-classes
1912 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
1915 default: assert(0 && "Invalid GPR number!");
1916 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
1917 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
1918 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
1919 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
1920 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
1921 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
1922 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
1923 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
1927 /// Parse a register list.
1929 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1930 assert(Parser.getTok().is(AsmToken::LCurly) &&
1931 "Token is not a Left Curly Brace");
1932 SMLoc S = Parser.getTok().getLoc();
1933 Parser.Lex(); // Eat '{' token.
1934 SMLoc RegLoc = Parser.getTok().getLoc();
1936 // Check the first register in the list to see what register class
1937 // this is a list of.
1938 int Reg = tryParseRegister();
1940 return Error(RegLoc, "register expected");
1942 MCRegisterClass *RC;
1943 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
1944 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
1945 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
1946 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
1947 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
1948 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
1950 return Error(RegLoc, "invalid register in register list");
1952 // The reglist instructions have at most 16 registers, so reserve
1953 // space for that many.
1954 SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
1955 // Store the first register.
1956 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
1958 // This starts immediately after the first register token in the list,
1959 // so we can see either a comma or a minus (range separator) as a legal
1961 while (Parser.getTok().is(AsmToken::Comma) ||
1962 Parser.getTok().is(AsmToken::Minus)) {
1963 if (Parser.getTok().is(AsmToken::Minus)) {
1964 Parser.Lex(); // Eat the comma.
1965 SMLoc EndLoc = Parser.getTok().getLoc();
1966 int EndReg = tryParseRegister();
1968 return Error(EndLoc, "register expected");
1969 // If the register is the same as the start reg, there's nothing
1973 // The register must be in the same register class as the first.
1974 if (!RC->contains(EndReg))
1975 return Error(EndLoc, "invalid register in register list");
1976 // Ranges must go from low to high.
1977 if (getARMRegisterNumbering(Reg) > getARMRegisterNumbering(EndReg))
1978 return Error(EndLoc, "bad range in register list");
1980 // Add all the registers in the range to the register list.
1981 while (Reg != EndReg) {
1982 Reg = getNextRegister(Reg);
1983 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
1987 Parser.Lex(); // Eat the comma.
1988 RegLoc = Parser.getTok().getLoc();
1990 Reg = tryParseRegister();
1992 return Error(RegLoc, "register expected");
1993 // The register must be in the same register class as the first.
1994 if (!RC->contains(Reg))
1995 return Error(RegLoc, "invalid register in register list");
1996 // List must be monotonically increasing.
1997 if (getARMRegisterNumbering(Reg) <= getARMRegisterNumbering(OldReg))
1998 return Error(RegLoc, "register list not in ascending order");
1999 // VFP register lists must also be contiguous.
2000 // It's OK to use the enumeration values directly here rather, as the
2001 // VFP register classes have the enum sorted properly.
2002 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
2004 return Error(RegLoc, "non-contiguous register range");
2005 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2008 SMLoc E = Parser.getTok().getLoc();
2009 if (Parser.getTok().isNot(AsmToken::RCurly))
2010 return Error(E, "'}' expected");
2011 Parser.Lex(); // Eat '}' token.
2013 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
2017 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
2018 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2019 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2020 SMLoc S = Parser.getTok().getLoc();
2021 const AsmToken &Tok = Parser.getTok();
2022 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2023 StringRef OptStr = Tok.getString();
2025 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
2026 .Case("sy", ARM_MB::SY)
2027 .Case("st", ARM_MB::ST)
2028 .Case("sh", ARM_MB::ISH)
2029 .Case("ish", ARM_MB::ISH)
2030 .Case("shst", ARM_MB::ISHST)
2031 .Case("ishst", ARM_MB::ISHST)
2032 .Case("nsh", ARM_MB::NSH)
2033 .Case("un", ARM_MB::NSH)
2034 .Case("nshst", ARM_MB::NSHST)
2035 .Case("unst", ARM_MB::NSHST)
2036 .Case("osh", ARM_MB::OSH)
2037 .Case("oshst", ARM_MB::OSHST)
2041 return MatchOperand_NoMatch;
2043 Parser.Lex(); // Eat identifier token.
2044 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
2045 return MatchOperand_Success;
2048 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
2049 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2050 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2051 SMLoc S = Parser.getTok().getLoc();
2052 const AsmToken &Tok = Parser.getTok();
2053 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2054 StringRef IFlagsStr = Tok.getString();
2056 unsigned IFlags = 0;
2057 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
2058 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
2059 .Case("a", ARM_PROC::A)
2060 .Case("i", ARM_PROC::I)
2061 .Case("f", ARM_PROC::F)
2064 // If some specific iflag is already set, it means that some letter is
2065 // present more than once, this is not acceptable.
2066 if (Flag == ~0U || (IFlags & Flag))
2067 return MatchOperand_NoMatch;
2072 Parser.Lex(); // Eat identifier token.
2073 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
2074 return MatchOperand_Success;
2077 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
2078 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2079 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2080 SMLoc S = Parser.getTok().getLoc();
2081 const AsmToken &Tok = Parser.getTok();
2082 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2083 StringRef Mask = Tok.getString();
2086 // See ARMv6-M 10.1.1
2087 unsigned FlagsVal = StringSwitch<unsigned>(Mask)
2097 .Case("primask", 16)
2098 .Case("basepri", 17)
2099 .Case("basepri_max", 18)
2100 .Case("faultmask", 19)
2101 .Case("control", 20)
2104 if (FlagsVal == ~0U)
2105 return MatchOperand_NoMatch;
2107 if (!hasV7Ops() && FlagsVal >= 17 && FlagsVal <= 19)
2108 // basepri, basepri_max and faultmask only valid for V7m.
2109 return MatchOperand_NoMatch;
2111 Parser.Lex(); // Eat identifier token.
2112 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
2113 return MatchOperand_Success;
2116 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
2117 size_t Start = 0, Next = Mask.find('_');
2118 StringRef Flags = "";
2119 std::string SpecReg = LowercaseString(Mask.slice(Start, Next));
2120 if (Next != StringRef::npos)
2121 Flags = Mask.slice(Next+1, Mask.size());
2123 // FlagsVal contains the complete mask:
2125 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
2126 unsigned FlagsVal = 0;
2128 if (SpecReg == "apsr") {
2129 FlagsVal = StringSwitch<unsigned>(Flags)
2130 .Case("nzcvq", 0x8) // same as CPSR_f
2131 .Case("g", 0x4) // same as CPSR_s
2132 .Case("nzcvqg", 0xc) // same as CPSR_fs
2135 if (FlagsVal == ~0U) {
2137 return MatchOperand_NoMatch;
2139 FlagsVal = 8; // No flag
2141 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
2142 if (Flags == "all") // cpsr_all is an alias for cpsr_fc
2144 for (int i = 0, e = Flags.size(); i != e; ++i) {
2145 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
2152 // If some specific flag is already set, it means that some letter is
2153 // present more than once, this is not acceptable.
2154 if (FlagsVal == ~0U || (FlagsVal & Flag))
2155 return MatchOperand_NoMatch;
2158 } else // No match for special register.
2159 return MatchOperand_NoMatch;
2161 // Special register without flags are equivalent to "fc" flags.
2165 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
2166 if (SpecReg == "spsr")
2169 Parser.Lex(); // Eat identifier token.
2170 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
2171 return MatchOperand_Success;
2174 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2175 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
2176 int Low, int High) {
2177 const AsmToken &Tok = Parser.getTok();
2178 if (Tok.isNot(AsmToken::Identifier)) {
2179 Error(Parser.getTok().getLoc(), Op + " operand expected.");
2180 return MatchOperand_ParseFail;
2182 StringRef ShiftName = Tok.getString();
2183 std::string LowerOp = LowercaseString(Op);
2184 std::string UpperOp = UppercaseString(Op);
2185 if (ShiftName != LowerOp && ShiftName != UpperOp) {
2186 Error(Parser.getTok().getLoc(), Op + " operand expected.");
2187 return MatchOperand_ParseFail;
2189 Parser.Lex(); // Eat shift type token.
2191 // There must be a '#' and a shift amount.
2192 if (Parser.getTok().isNot(AsmToken::Hash)) {
2193 Error(Parser.getTok().getLoc(), "'#' expected");
2194 return MatchOperand_ParseFail;
2196 Parser.Lex(); // Eat hash token.
2198 const MCExpr *ShiftAmount;
2199 SMLoc Loc = Parser.getTok().getLoc();
2200 if (getParser().ParseExpression(ShiftAmount)) {
2201 Error(Loc, "illegal expression");
2202 return MatchOperand_ParseFail;
2204 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2206 Error(Loc, "constant expression expected");
2207 return MatchOperand_ParseFail;
2209 int Val = CE->getValue();
2210 if (Val < Low || Val > High) {
2211 Error(Loc, "immediate value out of range");
2212 return MatchOperand_ParseFail;
2215 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
2217 return MatchOperand_Success;
2220 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2221 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2222 const AsmToken &Tok = Parser.getTok();
2223 SMLoc S = Tok.getLoc();
2224 if (Tok.isNot(AsmToken::Identifier)) {
2225 Error(Tok.getLoc(), "'be' or 'le' operand expected");
2226 return MatchOperand_ParseFail;
2228 int Val = StringSwitch<int>(Tok.getString())
2232 Parser.Lex(); // Eat the token.
2235 Error(Tok.getLoc(), "'be' or 'le' operand expected");
2236 return MatchOperand_ParseFail;
2238 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
2240 S, Parser.getTok().getLoc()));
2241 return MatchOperand_Success;
2244 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
2245 /// instructions. Legal values are:
2246 /// lsl #n 'n' in [0,31]
2247 /// asr #n 'n' in [1,32]
2248 /// n == 32 encoded as n == 0.
2249 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2250 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2251 const AsmToken &Tok = Parser.getTok();
2252 SMLoc S = Tok.getLoc();
2253 if (Tok.isNot(AsmToken::Identifier)) {
2254 Error(S, "shift operator 'asr' or 'lsl' expected");
2255 return MatchOperand_ParseFail;
2257 StringRef ShiftName = Tok.getString();
2259 if (ShiftName == "lsl" || ShiftName == "LSL")
2261 else if (ShiftName == "asr" || ShiftName == "ASR")
2264 Error(S, "shift operator 'asr' or 'lsl' expected");
2265 return MatchOperand_ParseFail;
2267 Parser.Lex(); // Eat the operator.
2269 // A '#' and a shift amount.
2270 if (Parser.getTok().isNot(AsmToken::Hash)) {
2271 Error(Parser.getTok().getLoc(), "'#' expected");
2272 return MatchOperand_ParseFail;
2274 Parser.Lex(); // Eat hash token.
2276 const MCExpr *ShiftAmount;
2277 SMLoc E = Parser.getTok().getLoc();
2278 if (getParser().ParseExpression(ShiftAmount)) {
2279 Error(E, "malformed shift expression");
2280 return MatchOperand_ParseFail;
2282 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2284 Error(E, "shift amount must be an immediate");
2285 return MatchOperand_ParseFail;
2288 int64_t Val = CE->getValue();
2290 // Shift amount must be in [1,32]
2291 if (Val < 1 || Val > 32) {
2292 Error(E, "'asr' shift amount must be in range [1,32]");
2293 return MatchOperand_ParseFail;
2295 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
2296 if (isThumb() && Val == 32) {
2297 Error(E, "'asr #32' shift amount not allowed in Thumb mode");
2298 return MatchOperand_ParseFail;
2300 if (Val == 32) Val = 0;
2302 // Shift amount must be in [1,32]
2303 if (Val < 0 || Val > 31) {
2304 Error(E, "'lsr' shift amount must be in range [0,31]");
2305 return MatchOperand_ParseFail;
2309 E = Parser.getTok().getLoc();
2310 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
2312 return MatchOperand_Success;
2315 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
2316 /// of instructions. Legal values are:
2317 /// ror #n 'n' in {0, 8, 16, 24}
2318 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2319 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2320 const AsmToken &Tok = Parser.getTok();
2321 SMLoc S = Tok.getLoc();
2322 if (Tok.isNot(AsmToken::Identifier))
2323 return MatchOperand_NoMatch;
2324 StringRef ShiftName = Tok.getString();
2325 if (ShiftName != "ror" && ShiftName != "ROR")
2326 return MatchOperand_NoMatch;
2327 Parser.Lex(); // Eat the operator.
2329 // A '#' and a rotate amount.
2330 if (Parser.getTok().isNot(AsmToken::Hash)) {
2331 Error(Parser.getTok().getLoc(), "'#' expected");
2332 return MatchOperand_ParseFail;
2334 Parser.Lex(); // Eat hash token.
2336 const MCExpr *ShiftAmount;
2337 SMLoc E = Parser.getTok().getLoc();
2338 if (getParser().ParseExpression(ShiftAmount)) {
2339 Error(E, "malformed rotate expression");
2340 return MatchOperand_ParseFail;
2342 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2344 Error(E, "rotate amount must be an immediate");
2345 return MatchOperand_ParseFail;
2348 int64_t Val = CE->getValue();
2349 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
2350 // normally, zero is represented in asm by omitting the rotate operand
2352 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
2353 Error(E, "'ror' rotate amount must be 8, 16, or 24");
2354 return MatchOperand_ParseFail;
2357 E = Parser.getTok().getLoc();
2358 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
2360 return MatchOperand_Success;
2363 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2364 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2365 SMLoc S = Parser.getTok().getLoc();
2366 // The bitfield descriptor is really two operands, the LSB and the width.
2367 if (Parser.getTok().isNot(AsmToken::Hash)) {
2368 Error(Parser.getTok().getLoc(), "'#' expected");
2369 return MatchOperand_ParseFail;
2371 Parser.Lex(); // Eat hash token.
2373 const MCExpr *LSBExpr;
2374 SMLoc E = Parser.getTok().getLoc();
2375 if (getParser().ParseExpression(LSBExpr)) {
2376 Error(E, "malformed immediate expression");
2377 return MatchOperand_ParseFail;
2379 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
2381 Error(E, "'lsb' operand must be an immediate");
2382 return MatchOperand_ParseFail;
2385 int64_t LSB = CE->getValue();
2386 // The LSB must be in the range [0,31]
2387 if (LSB < 0 || LSB > 31) {
2388 Error(E, "'lsb' operand must be in the range [0,31]");
2389 return MatchOperand_ParseFail;
2391 E = Parser.getTok().getLoc();
2393 // Expect another immediate operand.
2394 if (Parser.getTok().isNot(AsmToken::Comma)) {
2395 Error(Parser.getTok().getLoc(), "too few operands");
2396 return MatchOperand_ParseFail;
2398 Parser.Lex(); // Eat hash token.
2399 if (Parser.getTok().isNot(AsmToken::Hash)) {
2400 Error(Parser.getTok().getLoc(), "'#' expected");
2401 return MatchOperand_ParseFail;
2403 Parser.Lex(); // Eat hash token.
2405 const MCExpr *WidthExpr;
2406 if (getParser().ParseExpression(WidthExpr)) {
2407 Error(E, "malformed immediate expression");
2408 return MatchOperand_ParseFail;
2410 CE = dyn_cast<MCConstantExpr>(WidthExpr);
2412 Error(E, "'width' operand must be an immediate");
2413 return MatchOperand_ParseFail;
2416 int64_t Width = CE->getValue();
2417 // The LSB must be in the range [1,32-lsb]
2418 if (Width < 1 || Width > 32 - LSB) {
2419 Error(E, "'width' operand must be in the range [1,32-lsb]");
2420 return MatchOperand_ParseFail;
2422 E = Parser.getTok().getLoc();
2424 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
2426 return MatchOperand_Success;
2429 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2430 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2431 // Check for a post-index addressing register operand. Specifically:
2432 // postidx_reg := '+' register {, shift}
2433 // | '-' register {, shift}
2434 // | register {, shift}
2436 // This method must return MatchOperand_NoMatch without consuming any tokens
2437 // in the case where there is no match, as other alternatives take other
2439 AsmToken Tok = Parser.getTok();
2440 SMLoc S = Tok.getLoc();
2441 bool haveEaten = false;
2444 if (Tok.is(AsmToken::Plus)) {
2445 Parser.Lex(); // Eat the '+' token.
2447 } else if (Tok.is(AsmToken::Minus)) {
2448 Parser.Lex(); // Eat the '-' token.
2452 if (Parser.getTok().is(AsmToken::Identifier))
2453 Reg = tryParseRegister();
2456 return MatchOperand_NoMatch;
2457 Error(Parser.getTok().getLoc(), "register expected");
2458 return MatchOperand_ParseFail;
2460 SMLoc E = Parser.getTok().getLoc();
2462 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
2463 unsigned ShiftImm = 0;
2464 if (Parser.getTok().is(AsmToken::Comma)) {
2465 Parser.Lex(); // Eat the ','.
2466 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
2467 return MatchOperand_ParseFail;
2470 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
2473 return MatchOperand_Success;
2476 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2477 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2478 // Check for a post-index addressing register operand. Specifically:
2479 // am3offset := '+' register
2486 // This method must return MatchOperand_NoMatch without consuming any tokens
2487 // in the case where there is no match, as other alternatives take other
2489 AsmToken Tok = Parser.getTok();
2490 SMLoc S = Tok.getLoc();
2492 // Do immediates first, as we always parse those if we have a '#'.
2493 if (Parser.getTok().is(AsmToken::Hash)) {
2494 Parser.Lex(); // Eat the '#'.
2495 // Explicitly look for a '-', as we need to encode negative zero
2497 bool isNegative = Parser.getTok().is(AsmToken::Minus);
2498 const MCExpr *Offset;
2499 if (getParser().ParseExpression(Offset))
2500 return MatchOperand_ParseFail;
2501 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2503 Error(S, "constant expression expected");
2504 return MatchOperand_ParseFail;
2506 SMLoc E = Tok.getLoc();
2507 // Negative zero is encoded as the flag value INT32_MIN.
2508 int32_t Val = CE->getValue();
2509 if (isNegative && Val == 0)
2513 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
2515 return MatchOperand_Success;
2519 bool haveEaten = false;
2522 if (Tok.is(AsmToken::Plus)) {
2523 Parser.Lex(); // Eat the '+' token.
2525 } else if (Tok.is(AsmToken::Minus)) {
2526 Parser.Lex(); // Eat the '-' token.
2530 if (Parser.getTok().is(AsmToken::Identifier))
2531 Reg = tryParseRegister();
2534 return MatchOperand_NoMatch;
2535 Error(Parser.getTok().getLoc(), "register expected");
2536 return MatchOperand_ParseFail;
2538 SMLoc E = Parser.getTok().getLoc();
2540 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
2543 return MatchOperand_Success;
2546 /// cvtT2LdrdPre - Convert parsed operands to MCInst.
2547 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2548 /// when they refer multiple MIOperands inside a single one.
2550 cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
2551 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2553 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2554 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2555 // Create a writeback register dummy placeholder.
2556 Inst.addOperand(MCOperand::CreateReg(0));
2558 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
2560 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2564 /// cvtT2StrdPre - Convert parsed operands to MCInst.
2565 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2566 /// when they refer multiple MIOperands inside a single one.
2568 cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
2569 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2570 // Create a writeback register dummy placeholder.
2571 Inst.addOperand(MCOperand::CreateReg(0));
2573 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2574 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2576 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
2578 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2582 /// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
2583 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2584 /// when they refer multiple MIOperands inside a single one.
2586 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
2587 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2588 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2590 // Create a writeback register dummy placeholder.
2591 Inst.addOperand(MCOperand::CreateImm(0));
2593 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
2594 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2598 /// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
2599 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2600 /// when they refer multiple MIOperands inside a single one.
2602 cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
2603 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2604 // Create a writeback register dummy placeholder.
2605 Inst.addOperand(MCOperand::CreateImm(0));
2606 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2607 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
2608 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2612 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2613 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2614 /// when they refer multiple MIOperands inside a single one.
2616 cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2617 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2618 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2620 // Create a writeback register dummy placeholder.
2621 Inst.addOperand(MCOperand::CreateImm(0));
2623 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2624 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2628 /// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2629 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2630 /// when they refer multiple MIOperands inside a single one.
2632 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2633 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2634 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2636 // Create a writeback register dummy placeholder.
2637 Inst.addOperand(MCOperand::CreateImm(0));
2639 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2640 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2645 /// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2646 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2647 /// when they refer multiple MIOperands inside a single one.
2649 cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2650 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2651 // Create a writeback register dummy placeholder.
2652 Inst.addOperand(MCOperand::CreateImm(0));
2653 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2654 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2655 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2659 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2660 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2661 /// when they refer multiple MIOperands inside a single one.
2663 cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2664 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2665 // Create a writeback register dummy placeholder.
2666 Inst.addOperand(MCOperand::CreateImm(0));
2667 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2668 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2669 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2673 /// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2674 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2675 /// when they refer multiple MIOperands inside a single one.
2677 cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2678 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2679 // Create a writeback register dummy placeholder.
2680 Inst.addOperand(MCOperand::CreateImm(0));
2681 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2682 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2683 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2687 /// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
2688 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2689 /// when they refer multiple MIOperands inside a single one.
2691 cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2692 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2694 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2695 // Create a writeback register dummy placeholder.
2696 Inst.addOperand(MCOperand::CreateImm(0));
2698 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2700 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2702 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2706 /// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
2707 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2708 /// when they refer multiple MIOperands inside a single one.
2710 cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2711 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2713 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2714 // Create a writeback register dummy placeholder.
2715 Inst.addOperand(MCOperand::CreateImm(0));
2717 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2719 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2721 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2725 /// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
2726 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2727 /// when they refer multiple MIOperands inside a single one.
2729 cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2730 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2731 // Create a writeback register dummy placeholder.
2732 Inst.addOperand(MCOperand::CreateImm(0));
2734 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2736 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2738 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2740 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2744 /// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
2745 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2746 /// when they refer multiple MIOperands inside a single one.
2748 cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2749 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2750 // Create a writeback register dummy placeholder.
2751 Inst.addOperand(MCOperand::CreateImm(0));
2753 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2755 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2757 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2759 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2763 /// cvtLdrdPre - Convert parsed operands to MCInst.
2764 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2765 /// when they refer multiple MIOperands inside a single one.
2767 cvtLdrdPre(MCInst &Inst, unsigned Opcode,
2768 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2770 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2771 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2772 // Create a writeback register dummy placeholder.
2773 Inst.addOperand(MCOperand::CreateImm(0));
2775 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2777 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2781 /// cvtStrdPre - Convert parsed operands to MCInst.
2782 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2783 /// when they refer multiple MIOperands inside a single one.
2785 cvtStrdPre(MCInst &Inst, unsigned Opcode,
2786 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2787 // Create a writeback register dummy placeholder.
2788 Inst.addOperand(MCOperand::CreateImm(0));
2790 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2791 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2793 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2795 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2799 /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2800 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2801 /// when they refer multiple MIOperands inside a single one.
2803 cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2804 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2805 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2806 // Create a writeback register dummy placeholder.
2807 Inst.addOperand(MCOperand::CreateImm(0));
2808 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2809 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2813 /// cvtThumbMultiple- Convert parsed operands to MCInst.
2814 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2815 /// when they refer multiple MIOperands inside a single one.
2817 cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
2818 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2819 // The second source operand must be the same register as the destination
2821 if (Operands.size() == 6 &&
2822 (((ARMOperand*)Operands[3])->getReg() !=
2823 ((ARMOperand*)Operands[5])->getReg()) &&
2824 (((ARMOperand*)Operands[3])->getReg() !=
2825 ((ARMOperand*)Operands[4])->getReg())) {
2826 Error(Operands[3]->getStartLoc(),
2827 "destination register must match source register");
2830 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2831 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
2832 ((ARMOperand*)Operands[4])->addRegOperands(Inst, 1);
2833 // If we have a three-operand form, use that, else the second source operand
2834 // is just the destination operand again.
2835 if (Operands.size() == 6)
2836 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
2838 Inst.addOperand(Inst.getOperand(0));
2839 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
2844 /// Parse an ARM memory expression, return false if successful else return true
2845 /// or an error. The first token must be a '[' when called.
2847 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2849 assert(Parser.getTok().is(AsmToken::LBrac) &&
2850 "Token is not a Left Bracket");
2851 S = Parser.getTok().getLoc();
2852 Parser.Lex(); // Eat left bracket token.
2854 const AsmToken &BaseRegTok = Parser.getTok();
2855 int BaseRegNum = tryParseRegister();
2856 if (BaseRegNum == -1)
2857 return Error(BaseRegTok.getLoc(), "register expected");
2859 // The next token must either be a comma or a closing bracket.
2860 const AsmToken &Tok = Parser.getTok();
2861 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
2862 return Error(Tok.getLoc(), "malformed memory operand");
2864 if (Tok.is(AsmToken::RBrac)) {
2866 Parser.Lex(); // Eat right bracket token.
2868 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
2871 // If there's a pre-indexing writeback marker, '!', just add it as a token
2872 // operand. It's rather odd, but syntactically valid.
2873 if (Parser.getTok().is(AsmToken::Exclaim)) {
2874 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2875 Parser.Lex(); // Eat the '!'.
2881 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
2882 Parser.Lex(); // Eat the comma.
2884 // If we have a '#' it's an immediate offset, else assume it's a register
2886 if (Parser.getTok().is(AsmToken::Hash)) {
2887 Parser.Lex(); // Eat the '#'.
2888 E = Parser.getTok().getLoc();
2890 bool isNegative = getParser().getTok().is(AsmToken::Minus);
2891 const MCExpr *Offset;
2892 if (getParser().ParseExpression(Offset))
2895 // The expression has to be a constant. Memory references with relocations
2896 // don't come through here, as they use the <label> forms of the relevant
2898 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2900 return Error (E, "constant expression expected");
2902 // If the constant was #-0, represent it as INT32_MIN.
2903 int32_t Val = CE->getValue();
2904 if (isNegative && Val == 0)
2905 CE = MCConstantExpr::Create(INT32_MIN, getContext());
2907 // Now we should have the closing ']'
2908 E = Parser.getTok().getLoc();
2909 if (Parser.getTok().isNot(AsmToken::RBrac))
2910 return Error(E, "']' expected");
2911 Parser.Lex(); // Eat right bracket token.
2913 // Don't worry about range checking the value here. That's handled by
2914 // the is*() predicates.
2915 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
2916 ARM_AM::no_shift, 0, false, S,E));
2918 // If there's a pre-indexing writeback marker, '!', just add it as a token
2920 if (Parser.getTok().is(AsmToken::Exclaim)) {
2921 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2922 Parser.Lex(); // Eat the '!'.
2928 // The register offset is optionally preceded by a '+' or '-'
2929 bool isNegative = false;
2930 if (Parser.getTok().is(AsmToken::Minus)) {
2932 Parser.Lex(); // Eat the '-'.
2933 } else if (Parser.getTok().is(AsmToken::Plus)) {
2935 Parser.Lex(); // Eat the '+'.
2938 E = Parser.getTok().getLoc();
2939 int OffsetRegNum = tryParseRegister();
2940 if (OffsetRegNum == -1)
2941 return Error(E, "register expected");
2943 // If there's a shift operator, handle it.
2944 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
2945 unsigned ShiftImm = 0;
2946 if (Parser.getTok().is(AsmToken::Comma)) {
2947 Parser.Lex(); // Eat the ','.
2948 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
2952 // Now we should have the closing ']'
2953 E = Parser.getTok().getLoc();
2954 if (Parser.getTok().isNot(AsmToken::RBrac))
2955 return Error(E, "']' expected");
2956 Parser.Lex(); // Eat right bracket token.
2958 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
2959 ShiftType, ShiftImm, isNegative,
2962 // If there's a pre-indexing writeback marker, '!', just add it as a token
2964 if (Parser.getTok().is(AsmToken::Exclaim)) {
2965 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2966 Parser.Lex(); // Eat the '!'.
2972 /// parseMemRegOffsetShift - one of these two:
2973 /// ( lsl | lsr | asr | ror ) , # shift_amount
2975 /// return true if it parses a shift otherwise it returns false.
2976 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
2978 SMLoc Loc = Parser.getTok().getLoc();
2979 const AsmToken &Tok = Parser.getTok();
2980 if (Tok.isNot(AsmToken::Identifier))
2982 StringRef ShiftName = Tok.getString();
2983 if (ShiftName == "lsl" || ShiftName == "LSL")
2985 else if (ShiftName == "lsr" || ShiftName == "LSR")
2987 else if (ShiftName == "asr" || ShiftName == "ASR")
2989 else if (ShiftName == "ror" || ShiftName == "ROR")
2991 else if (ShiftName == "rrx" || ShiftName == "RRX")
2994 return Error(Loc, "illegal shift operator");
2995 Parser.Lex(); // Eat shift type token.
2997 // rrx stands alone.
2999 if (St != ARM_AM::rrx) {
3000 Loc = Parser.getTok().getLoc();
3001 // A '#' and a shift amount.
3002 const AsmToken &HashTok = Parser.getTok();
3003 if (HashTok.isNot(AsmToken::Hash))
3004 return Error(HashTok.getLoc(), "'#' expected");
3005 Parser.Lex(); // Eat hash token.
3008 if (getParser().ParseExpression(Expr))
3010 // Range check the immediate.
3011 // lsl, ror: 0 <= imm <= 31
3012 // lsr, asr: 0 <= imm <= 32
3013 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3015 return Error(Loc, "shift amount must be an immediate");
3016 int64_t Imm = CE->getValue();
3018 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
3019 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
3020 return Error(Loc, "immediate shift value out of range");
3027 /// Parse a arm instruction operand. For now this parses the operand regardless
3028 /// of the mnemonic.
3029 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
3030 StringRef Mnemonic) {
3033 // Check if the current operand has a custom associated parser, if so, try to
3034 // custom parse the operand, or fallback to the general approach.
3035 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
3036 if (ResTy == MatchOperand_Success)
3038 // If there wasn't a custom match, try the generic matcher below. Otherwise,
3039 // there was a match, but an error occurred, in which case, just return that
3040 // the operand parsing failed.
3041 if (ResTy == MatchOperand_ParseFail)
3044 switch (getLexer().getKind()) {
3046 Error(Parser.getTok().getLoc(), "unexpected token in operand");
3048 case AsmToken::Identifier: {
3049 // If this is VMRS, check for the apsr_nzcv operand.
3050 if (!tryParseRegisterWithWriteBack(Operands))
3052 int Res = tryParseShiftRegister(Operands);
3053 if (Res == 0) // success
3055 else if (Res == -1) // irrecoverable error
3057 if (Mnemonic == "vmrs" && Parser.getTok().getString() == "apsr_nzcv") {
3058 S = Parser.getTok().getLoc();
3060 Operands.push_back(ARMOperand::CreateToken("apsr_nzcv", S));
3064 // Fall though for the Identifier case that is not a register or a
3067 case AsmToken::Integer: // things like 1f and 2b as a branch targets
3068 case AsmToken::Dot: { // . as a branch target
3069 // This was not a register so parse other operands that start with an
3070 // identifier (like labels) as expressions and create them as immediates.
3071 const MCExpr *IdVal;
3072 S = Parser.getTok().getLoc();
3073 if (getParser().ParseExpression(IdVal))
3075 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3076 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
3079 case AsmToken::LBrac:
3080 return parseMemory(Operands);
3081 case AsmToken::LCurly:
3082 return parseRegisterList(Operands);
3083 case AsmToken::Hash: {
3084 // #42 -> immediate.
3085 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
3086 S = Parser.getTok().getLoc();
3088 bool isNegative = Parser.getTok().is(AsmToken::Minus);
3089 const MCExpr *ImmVal;
3090 if (getParser().ParseExpression(ImmVal))
3092 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
3094 Error(S, "constant expression expected");
3095 return MatchOperand_ParseFail;
3097 int32_t Val = CE->getValue();
3098 if (isNegative && Val == 0)
3099 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
3100 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3101 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
3104 case AsmToken::Colon: {
3105 // ":lower16:" and ":upper16:" expression prefixes
3106 // FIXME: Check it's an expression prefix,
3107 // e.g. (FOO - :lower16:BAR) isn't legal.
3108 ARMMCExpr::VariantKind RefKind;
3109 if (parsePrefix(RefKind))
3112 const MCExpr *SubExprVal;
3113 if (getParser().ParseExpression(SubExprVal))
3116 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
3118 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3119 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
3125 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
3126 // :lower16: and :upper16:.
3127 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
3128 RefKind = ARMMCExpr::VK_ARM_None;
3130 // :lower16: and :upper16: modifiers
3131 assert(getLexer().is(AsmToken::Colon) && "expected a :");
3132 Parser.Lex(); // Eat ':'
3134 if (getLexer().isNot(AsmToken::Identifier)) {
3135 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
3139 StringRef IDVal = Parser.getTok().getIdentifier();
3140 if (IDVal == "lower16") {
3141 RefKind = ARMMCExpr::VK_ARM_LO16;
3142 } else if (IDVal == "upper16") {
3143 RefKind = ARMMCExpr::VK_ARM_HI16;
3145 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
3150 if (getLexer().isNot(AsmToken::Colon)) {
3151 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
3154 Parser.Lex(); // Eat the last ':'
3158 /// \brief Given a mnemonic, split out possible predication code and carry
3159 /// setting letters to form a canonical mnemonic and flags.
3161 // FIXME: Would be nice to autogen this.
3162 // FIXME: This is a bit of a maze of special cases.
3163 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
3164 unsigned &PredicationCode,
3166 unsigned &ProcessorIMod,
3167 StringRef &ITMask) {
3168 PredicationCode = ARMCC::AL;
3169 CarrySetting = false;
3172 // Ignore some mnemonics we know aren't predicated forms.
3174 // FIXME: Would be nice to autogen this.
3175 if ((Mnemonic == "movs" && isThumb()) ||
3176 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
3177 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
3178 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
3179 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
3180 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
3181 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
3182 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
3185 // First, split out any predication code. Ignore mnemonics we know aren't
3186 // predicated but do have a carry-set and so weren't caught above.
3187 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
3188 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
3189 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
3190 Mnemonic != "sbcs" && Mnemonic != "rscs") {
3191 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
3192 .Case("eq", ARMCC::EQ)
3193 .Case("ne", ARMCC::NE)
3194 .Case("hs", ARMCC::HS)
3195 .Case("cs", ARMCC::HS)
3196 .Case("lo", ARMCC::LO)
3197 .Case("cc", ARMCC::LO)
3198 .Case("mi", ARMCC::MI)
3199 .Case("pl", ARMCC::PL)
3200 .Case("vs", ARMCC::VS)
3201 .Case("vc", ARMCC::VC)
3202 .Case("hi", ARMCC::HI)
3203 .Case("ls", ARMCC::LS)
3204 .Case("ge", ARMCC::GE)
3205 .Case("lt", ARMCC::LT)
3206 .Case("gt", ARMCC::GT)
3207 .Case("le", ARMCC::LE)
3208 .Case("al", ARMCC::AL)
3211 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
3212 PredicationCode = CC;
3216 // Next, determine if we have a carry setting bit. We explicitly ignore all
3217 // the instructions we know end in 's'.
3218 if (Mnemonic.endswith("s") &&
3219 !(Mnemonic == "cps" || Mnemonic == "mls" ||
3220 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
3221 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
3222 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
3223 Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
3224 (Mnemonic == "movs" && isThumb()))) {
3225 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
3226 CarrySetting = true;
3229 // The "cps" instruction can have a interrupt mode operand which is glued into
3230 // the mnemonic. Check if this is the case, split it and parse the imod op
3231 if (Mnemonic.startswith("cps")) {
3232 // Split out any imod code.
3234 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
3235 .Case("ie", ARM_PROC::IE)
3236 .Case("id", ARM_PROC::ID)
3239 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
3240 ProcessorIMod = IMod;
3244 // The "it" instruction has the condition mask on the end of the mnemonic.
3245 if (Mnemonic.startswith("it")) {
3246 ITMask = Mnemonic.slice(2, Mnemonic.size());
3247 Mnemonic = Mnemonic.slice(0, 2);
3253 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
3254 /// inclusion of carry set or predication code operands.
3256 // FIXME: It would be nice to autogen this.
3258 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
3259 bool &CanAcceptPredicationCode) {
3260 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
3261 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
3262 Mnemonic == "add" || Mnemonic == "adc" ||
3263 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
3264 Mnemonic == "orr" || Mnemonic == "mvn" ||
3265 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
3266 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
3267 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
3268 Mnemonic == "mla" || Mnemonic == "smlal" ||
3269 Mnemonic == "umlal" || Mnemonic == "umull"))) {
3270 CanAcceptCarrySet = true;
3272 CanAcceptCarrySet = false;
3274 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
3275 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
3276 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
3277 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
3278 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
3279 (Mnemonic == "clrex" && !isThumb()) ||
3280 (Mnemonic == "nop" && isThumbOne()) ||
3281 ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw") &&
3283 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
3285 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
3286 CanAcceptPredicationCode = false;
3288 CanAcceptPredicationCode = true;
3291 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
3292 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
3293 CanAcceptPredicationCode = false;
3297 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
3298 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3299 // FIXME: This is all horribly hacky. We really need a better way to deal
3300 // with optional operands like this in the matcher table.
3302 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
3303 // another does not. Specifically, the MOVW instruction does not. So we
3304 // special case it here and remove the defaulted (non-setting) cc_out
3305 // operand if that's the instruction we're trying to match.
3307 // We do this as post-processing of the explicit operands rather than just
3308 // conditionally adding the cc_out in the first place because we need
3309 // to check the type of the parsed immediate operand.
3310 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
3311 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
3312 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
3313 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3316 // Register-register 'add' for thumb does not have a cc_out operand
3317 // when there are only two register operands.
3318 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
3319 static_cast<ARMOperand*>(Operands[3])->isReg() &&
3320 static_cast<ARMOperand*>(Operands[4])->isReg() &&
3321 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3323 // Register-register 'add' for thumb does not have a cc_out operand
3324 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
3325 // have to check the immediate range here since Thumb2 has a variant
3326 // that can handle a different range and has a cc_out operand.
3327 if (((isThumb() && Mnemonic == "add") ||
3328 (isThumbTwo() && Mnemonic == "sub")) &&
3329 Operands.size() == 6 &&
3330 static_cast<ARMOperand*>(Operands[3])->isReg() &&
3331 static_cast<ARMOperand*>(Operands[4])->isReg() &&
3332 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
3333 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
3334 (static_cast<ARMOperand*>(Operands[5])->isReg() ||
3335 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
3337 // For Thumb2, add/sub immediate does not have a cc_out operand for the
3338 // imm0_4095 variant. That's the least-preferred variant when
3339 // selecting via the generic "add" mnemonic, so to know that we
3340 // should remove the cc_out operand, we have to explicitly check that
3341 // it's not one of the other variants. Ugh.
3342 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
3343 Operands.size() == 6 &&
3344 static_cast<ARMOperand*>(Operands[3])->isReg() &&
3345 static_cast<ARMOperand*>(Operands[4])->isReg() &&
3346 static_cast<ARMOperand*>(Operands[5])->isImm()) {
3347 // Nest conditions rather than one big 'if' statement for readability.
3349 // If either register is a high reg, it's either one of the SP
3350 // variants (handled above) or a 32-bit encoding, so we just
3351 // check against T3.
3352 if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
3353 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
3354 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
3356 // If both registers are low, we're in an IT block, and the immediate is
3357 // in range, we should use encoding T1 instead, which has a cc_out.
3359 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
3360 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
3361 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
3364 // Otherwise, we use encoding T4, which does not have a cc_out
3369 // The thumb2 multiply instruction doesn't have a CCOut register, so
3370 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
3371 // use the 16-bit encoding or not.
3372 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
3373 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
3374 static_cast<ARMOperand*>(Operands[3])->isReg() &&
3375 static_cast<ARMOperand*>(Operands[4])->isReg() &&
3376 static_cast<ARMOperand*>(Operands[5])->isReg() &&
3377 // If the registers aren't low regs, the destination reg isn't the
3378 // same as one of the source regs, or the cc_out operand is zero
3379 // outside of an IT block, we have to use the 32-bit encoding, so
3380 // remove the cc_out operand.
3381 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
3382 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
3384 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
3385 static_cast<ARMOperand*>(Operands[5])->getReg() &&
3386 static_cast<ARMOperand*>(Operands[3])->getReg() !=
3387 static_cast<ARMOperand*>(Operands[4])->getReg())))
3392 // Register-register 'add/sub' for thumb does not have a cc_out operand
3393 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
3394 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
3395 // right, this will result in better diagnostics (which operand is off)
3397 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
3398 (Operands.size() == 5 || Operands.size() == 6) &&
3399 static_cast<ARMOperand*>(Operands[3])->isReg() &&
3400 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
3401 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3407 /// Parse an arm instruction mnemonic followed by its operands.
3408 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
3409 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3410 // Create the leading tokens for the mnemonic, split by '.' characters.
3411 size_t Start = 0, Next = Name.find('.');
3412 StringRef Mnemonic = Name.slice(Start, Next);
3414 // Split out the predication code and carry setting flag from the mnemonic.
3415 unsigned PredicationCode;
3416 unsigned ProcessorIMod;
3419 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
3420 ProcessorIMod, ITMask);
3422 // In Thumb1, only the branch (B) instruction can be predicated.
3423 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
3424 Parser.EatToEndOfStatement();
3425 return Error(NameLoc, "conditional execution not supported in Thumb1");
3428 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
3430 // Handle the IT instruction ITMask. Convert it to a bitmask. This
3431 // is the mask as it will be for the IT encoding if the conditional
3432 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
3433 // where the conditional bit0 is zero, the instruction post-processing
3434 // will adjust the mask accordingly.
3435 if (Mnemonic == "it") {
3436 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
3437 if (ITMask.size() > 3) {
3438 Parser.EatToEndOfStatement();
3439 return Error(Loc, "too many conditions on IT instruction");
3442 for (unsigned i = ITMask.size(); i != 0; --i) {
3443 char pos = ITMask[i - 1];
3444 if (pos != 't' && pos != 'e') {
3445 Parser.EatToEndOfStatement();
3446 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
3449 if (ITMask[i - 1] == 't')
3452 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
3455 // FIXME: This is all a pretty gross hack. We should automatically handle
3456 // optional operands like this via tblgen.
3458 // Next, add the CCOut and ConditionCode operands, if needed.
3460 // For mnemonics which can ever incorporate a carry setting bit or predication
3461 // code, our matching model involves us always generating CCOut and
3462 // ConditionCode operands to match the mnemonic "as written" and then we let
3463 // the matcher deal with finding the right instruction or generating an
3464 // appropriate error.
3465 bool CanAcceptCarrySet, CanAcceptPredicationCode;
3466 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
3468 // If we had a carry-set on an instruction that can't do that, issue an
3470 if (!CanAcceptCarrySet && CarrySetting) {
3471 Parser.EatToEndOfStatement();
3472 return Error(NameLoc, "instruction '" + Mnemonic +
3473 "' can not set flags, but 's' suffix specified");
3475 // If we had a predication code on an instruction that can't do that, issue an
3477 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
3478 Parser.EatToEndOfStatement();
3479 return Error(NameLoc, "instruction '" + Mnemonic +
3480 "' is not predicable, but condition code specified");
3483 // Add the carry setting operand, if necessary.
3484 if (CanAcceptCarrySet) {
3485 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
3486 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
3490 // Add the predication code operand, if necessary.
3491 if (CanAcceptPredicationCode) {
3492 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
3494 Operands.push_back(ARMOperand::CreateCondCode(
3495 ARMCC::CondCodes(PredicationCode), Loc));
3498 // Add the processor imod operand, if necessary.
3499 if (ProcessorIMod) {
3500 Operands.push_back(ARMOperand::CreateImm(
3501 MCConstantExpr::Create(ProcessorIMod, getContext()),
3505 // Add the remaining tokens in the mnemonic.
3506 while (Next != StringRef::npos) {
3508 Next = Name.find('.', Start + 1);
3509 StringRef ExtraToken = Name.slice(Start, Next);
3511 // For now, we're only parsing Thumb1 (for the most part), so
3512 // just ignore ".n" qualifiers. We'll use them to restrict
3513 // matching when we do Thumb2.
3514 if (ExtraToken != ".n") {
3515 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
3516 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
3520 // Read the remaining operands.
3521 if (getLexer().isNot(AsmToken::EndOfStatement)) {
3522 // Read the first operand.
3523 if (parseOperand(Operands, Mnemonic)) {
3524 Parser.EatToEndOfStatement();
3528 while (getLexer().is(AsmToken::Comma)) {
3529 Parser.Lex(); // Eat the comma.
3531 // Parse and remember the operand.
3532 if (parseOperand(Operands, Mnemonic)) {
3533 Parser.EatToEndOfStatement();
3539 if (getLexer().isNot(AsmToken::EndOfStatement)) {
3540 Parser.EatToEndOfStatement();
3541 return TokError("unexpected token in argument list");
3544 Parser.Lex(); // Consume the EndOfStatement
3546 // Some instructions, mostly Thumb, have forms for the same mnemonic that
3547 // do and don't have a cc_out optional-def operand. With some spot-checks
3548 // of the operand list, we can figure out which variant we're trying to
3549 // parse and adjust accordingly before actually matching. We shouldn't ever
3550 // try to remove a cc_out operand that was explicitly set on the the
3551 // mnemonic, of course (CarrySetting == true). Reason number #317 the
3552 // table driven matcher doesn't fit well with the ARM instruction set.
3553 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
3554 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3555 Operands.erase(Operands.begin() + 1);
3559 // ARM mode 'blx' need special handling, as the register operand version
3560 // is predicable, but the label operand version is not. So, we can't rely
3561 // on the Mnemonic based checking to correctly figure out when to put
3562 // a CondCode operand in the list. If we're trying to match the label
3563 // version, remove the CondCode operand here.
3564 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
3565 static_cast<ARMOperand*>(Operands[2])->isImm()) {
3566 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3567 Operands.erase(Operands.begin() + 1);
3571 // The vector-compare-to-zero instructions have a literal token "#0" at
3572 // the end that comes to here as an immediate operand. Convert it to a
3573 // token to play nicely with the matcher.
3574 if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
3575 Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
3576 static_cast<ARMOperand*>(Operands[5])->isImm()) {
3577 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
3578 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
3579 if (CE && CE->getValue() == 0) {
3580 Operands.erase(Operands.begin() + 5);
3581 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3585 // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
3586 // end. Convert it to a token here.
3587 if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
3588 static_cast<ARMOperand*>(Operands[5])->isImm()) {
3589 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
3590 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
3591 if (CE && CE->getValue() == 0) {
3592 Operands.erase(Operands.begin() + 5);
3593 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3601 // Validate context-sensitive operand constraints.
3603 // return 'true' if register list contains non-low GPR registers,
3604 // 'false' otherwise. If Reg is in the register list or is HiReg, set
3605 // 'containsReg' to true.
3606 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
3607 unsigned HiReg, bool &containsReg) {
3608 containsReg = false;
3609 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
3610 unsigned OpReg = Inst.getOperand(i).getReg();
3613 // Anything other than a low register isn't legal here.
3614 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
3620 // Check if the specified regisgter is in the register list of the inst,
3621 // starting at the indicated operand number.
3622 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
3623 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
3624 unsigned OpReg = Inst.getOperand(i).getReg();
3631 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around
3632 // the ARMInsts array) instead. Getting that here requires awkward
3633 // API changes, though. Better way?
3635 extern MCInstrDesc ARMInsts[];
3637 static MCInstrDesc &getInstDesc(unsigned Opcode) {
3638 return ARMInsts[Opcode];
3641 // FIXME: We would really like to be able to tablegen'erate this.
3643 validateInstruction(MCInst &Inst,
3644 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3645 MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
3646 SMLoc Loc = Operands[0]->getStartLoc();
3647 // Check the IT block state first.
3648 // NOTE: In Thumb mode, the BKPT instruction has the interesting property of
3649 // being allowed in IT blocks, but not being predicable. It just always
3651 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT) {
3653 if (ITState.FirstCond)
3654 ITState.FirstCond = false;
3656 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
3657 // The instruction must be predicable.
3658 if (!MCID.isPredicable())
3659 return Error(Loc, "instructions in IT block must be predicable");
3660 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
3661 unsigned ITCond = bit ? ITState.Cond :
3662 ARMCC::getOppositeCondition(ITState.Cond);
3663 if (Cond != ITCond) {
3664 // Find the condition code Operand to get its SMLoc information.
3666 for (unsigned i = 1; i < Operands.size(); ++i)
3667 if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
3668 CondLoc = Operands[i]->getStartLoc();
3669 return Error(CondLoc, "incorrect condition in IT block; got '" +
3670 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
3671 "', but expected '" +
3672 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
3674 // Check for non-'al' condition codes outside of the IT block.
3675 } else if (isThumbTwo() && MCID.isPredicable() &&
3676 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
3677 ARMCC::AL && Inst.getOpcode() != ARM::tB &&
3678 Inst.getOpcode() != ARM::t2B)
3679 return Error(Loc, "predicated instructions must be in IT block");
3681 switch (Inst.getOpcode()) {
3684 case ARM::LDRD_POST:
3686 // Rt2 must be Rt + 1.
3687 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3688 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3690 return Error(Operands[3]->getStartLoc(),
3691 "destination operands must be sequential");
3695 // Rt2 must be Rt + 1.
3696 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3697 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3699 return Error(Operands[3]->getStartLoc(),
3700 "source operands must be sequential");
3704 case ARM::STRD_POST:
3706 // Rt2 must be Rt + 1.
3707 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3708 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
3710 return Error(Operands[3]->getStartLoc(),
3711 "source operands must be sequential");
3716 // width must be in range [1, 32-lsb]
3717 unsigned lsb = Inst.getOperand(2).getImm();
3718 unsigned widthm1 = Inst.getOperand(3).getImm();
3719 if (widthm1 >= 32 - lsb)
3720 return Error(Operands[5]->getStartLoc(),
3721 "bitfield width must be in range [1,32-lsb]");
3725 // If we're parsing Thumb2, the .w variant is available and handles
3726 // most cases that are normally illegal for a Thumb1 LDM
3727 // instruction. We'll make the transformation in processInstruction()
3730 // Thumb LDM instructions are writeback iff the base register is not
3731 // in the register list.
3732 unsigned Rn = Inst.getOperand(0).getReg();
3733 bool hasWritebackToken =
3734 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
3735 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
3736 bool listContainsBase;
3737 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
3738 return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
3739 "registers must be in range r0-r7");
3740 // If we should have writeback, then there should be a '!' token.
3741 if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
3742 return Error(Operands[2]->getStartLoc(),
3743 "writeback operator '!' expected");
3744 // If we should not have writeback, there must not be a '!'. This is
3745 // true even for the 32-bit wide encodings.
3746 if (listContainsBase && hasWritebackToken)
3747 return Error(Operands[3]->getStartLoc(),
3748 "writeback operator '!' not allowed when base register "
3749 "in register list");
3753 case ARM::t2LDMIA_UPD: {
3754 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
3755 return Error(Operands[4]->getStartLoc(),
3756 "writeback operator '!' not allowed when base register "
3757 "in register list");
3761 bool listContainsBase;
3762 if (checkLowRegisterList(Inst, 3, 0, ARM::PC, listContainsBase))
3763 return Error(Operands[2]->getStartLoc(),
3764 "registers must be in range r0-r7 or pc");
3768 bool listContainsBase;
3769 if (checkLowRegisterList(Inst, 3, 0, ARM::LR, listContainsBase))
3770 return Error(Operands[2]->getStartLoc(),
3771 "registers must be in range r0-r7 or lr");
3774 case ARM::tSTMIA_UPD: {
3775 bool listContainsBase;
3776 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
3777 return Error(Operands[4]->getStartLoc(),
3778 "registers must be in range r0-r7");
3787 processInstruction(MCInst &Inst,
3788 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3789 switch (Inst.getOpcode()) {
3790 case ARM::LDMIA_UPD:
3791 // If this is a load of a single register via a 'pop', then we should use
3792 // a post-indexed LDR instruction instead, per the ARM ARM.
3793 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
3794 Inst.getNumOperands() == 5) {
3796 TmpInst.setOpcode(ARM::LDR_POST_IMM);
3797 TmpInst.addOperand(Inst.getOperand(4)); // Rt
3798 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3799 TmpInst.addOperand(Inst.getOperand(1)); // Rn
3800 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
3801 TmpInst.addOperand(MCOperand::CreateImm(4));
3802 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3803 TmpInst.addOperand(Inst.getOperand(3));
3807 case ARM::STMDB_UPD:
3808 // If this is a store of a single register via a 'push', then we should use
3809 // a pre-indexed STR instruction instead, per the ARM ARM.
3810 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
3811 Inst.getNumOperands() == 5) {
3813 TmpInst.setOpcode(ARM::STR_PRE_IMM);
3814 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3815 TmpInst.addOperand(Inst.getOperand(4)); // Rt
3816 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
3817 TmpInst.addOperand(MCOperand::CreateImm(-4));
3818 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3819 TmpInst.addOperand(Inst.getOperand(3));
3824 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
3825 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
3826 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
3827 // to encoding T1 if <Rd> is omitted."
3828 if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6)
3829 Inst.setOpcode(ARM::tADDi3);
3832 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
3833 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
3834 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
3835 // to encoding T1 if <Rd> is omitted."
3836 if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6)
3837 Inst.setOpcode(ARM::tSUBi3);
3840 // A Thumb conditional branch outside of an IT block is a tBcc.
3841 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock())
3842 Inst.setOpcode(ARM::tBcc);
3845 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
3846 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock())
3847 Inst.setOpcode(ARM::t2Bcc);
3850 // If the conditional is AL or we're in an IT block, we really want t2B.
3851 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock())
3852 Inst.setOpcode(ARM::t2B);
3855 // If the conditional is AL, we really want tB.
3856 if (Inst.getOperand(1).getImm() == ARMCC::AL)
3857 Inst.setOpcode(ARM::tB);
3860 // If the register list contains any high registers, or if the writeback
3861 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
3862 // instead if we're in Thumb2. Otherwise, this should have generated
3863 // an error in validateInstruction().
3864 unsigned Rn = Inst.getOperand(0).getReg();
3865 bool hasWritebackToken =
3866 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
3867 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
3868 bool listContainsBase;
3869 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
3870 (!listContainsBase && !hasWritebackToken) ||
3871 (listContainsBase && hasWritebackToken)) {
3872 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
3873 assert (isThumbTwo());
3874 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
3875 // If we're switching to the updating version, we need to insert
3876 // the writeback tied operand.
3877 if (hasWritebackToken)
3878 Inst.insert(Inst.begin(),
3879 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
3883 case ARM::tSTMIA_UPD: {
3884 // If the register list contains any high registers, we need to use
3885 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
3886 // should have generated an error in validateInstruction().
3887 unsigned Rn = Inst.getOperand(0).getReg();
3888 bool listContainsBase;
3889 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
3890 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
3891 assert (isThumbTwo());
3892 Inst.setOpcode(ARM::t2STMIA_UPD);
3897 // If we can use the 16-bit encoding and the user didn't explicitly
3898 // request the 32-bit variant, transform it here.
3899 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
3900 Inst.getOperand(1).getImm() <= 255 &&
3901 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
3902 Inst.getOperand(4).getReg() == ARM::CPSR) ||
3903 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
3904 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
3905 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
3906 // The operands aren't in the same order for tMOVi8...
3908 TmpInst.setOpcode(ARM::tMOVi8);
3909 TmpInst.addOperand(Inst.getOperand(0));
3910 TmpInst.addOperand(Inst.getOperand(4));
3911 TmpInst.addOperand(Inst.getOperand(1));
3912 TmpInst.addOperand(Inst.getOperand(2));
3913 TmpInst.addOperand(Inst.getOperand(3));
3919 // If we can use the 16-bit encoding and the user didn't explicitly
3920 // request the 32-bit variant, transform it here.
3921 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
3922 isARMLowRegister(Inst.getOperand(1).getReg()) &&
3923 Inst.getOperand(2).getImm() == ARMCC::AL &&
3924 Inst.getOperand(4).getReg() == ARM::CPSR &&
3925 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
3926 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
3927 // The operands aren't the same for tMOV[S]r... (no cc_out)
3929 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
3930 TmpInst.addOperand(Inst.getOperand(0));
3931 TmpInst.addOperand(Inst.getOperand(1));
3932 TmpInst.addOperand(Inst.getOperand(2));
3933 TmpInst.addOperand(Inst.getOperand(3));
3942 // If we can use the 16-bit encoding and the user didn't explicitly
3943 // request the 32-bit variant, transform it here.
3944 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
3945 isARMLowRegister(Inst.getOperand(1).getReg()) &&
3946 Inst.getOperand(2).getImm() == 0 &&
3947 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
3948 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
3950 switch (Inst.getOpcode()) {
3951 default: llvm_unreachable("Illegal opcode!");
3952 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
3953 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
3954 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
3955 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
3957 // The operands aren't the same for thumb1 (no rotate operand).
3959 TmpInst.setOpcode(NewOpc);
3960 TmpInst.addOperand(Inst.getOperand(0));
3961 TmpInst.addOperand(Inst.getOperand(1));
3962 TmpInst.addOperand(Inst.getOperand(3));
3963 TmpInst.addOperand(Inst.getOperand(4));
3969 // The mask bits for all but the first condition are represented as
3970 // the low bit of the condition code value implies 't'. We currently
3971 // always have 1 implies 't', so XOR toggle the bits if the low bit
3972 // of the condition code is zero. The encoding also expects the low
3973 // bit of the condition to be encoded as bit 4 of the mask operand,
3974 // so mask that in if needed
3975 MCOperand &MO = Inst.getOperand(1);
3976 unsigned Mask = MO.getImm();
3977 unsigned OrigMask = Mask;
3978 unsigned TZ = CountTrailingZeros_32(Mask);
3979 if ((Inst.getOperand(0).getImm() & 1) == 0) {
3980 assert(Mask && TZ <= 3 && "illegal IT mask value!");
3981 for (unsigned i = 3; i != TZ; --i)
3987 // Set up the IT block state according to the IT instruction we just
3989 assert(!inITBlock() && "nested IT blocks?!");
3990 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
3991 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
3992 ITState.CurPosition = 0;
3993 ITState.FirstCond = true;
3999 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
4000 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
4001 // suffix depending on whether they're in an IT block or not.
4002 unsigned Opc = Inst.getOpcode();
4003 MCInstrDesc &MCID = getInstDesc(Opc);
4004 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
4005 assert(MCID.hasOptionalDef() &&
4006 "optionally flag setting instruction missing optional def operand");
4007 assert(MCID.NumOperands == Inst.getNumOperands() &&
4008 "operand count mismatch!");
4009 // Find the optional-def operand (cc_out).
4012 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
4015 // If we're parsing Thumb1, reject it completely.
4016 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
4017 return Match_MnemonicFail;
4018 // If we're parsing Thumb2, which form is legal depends on whether we're
4020 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
4022 return Match_RequiresITBlock;
4023 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
4025 return Match_RequiresNotITBlock;
4027 // Some high-register supporting Thumb1 encodings only allow both registers
4028 // to be from r0-r7 when in Thumb2.
4029 else if (Opc == ARM::tADDhirr && isThumbOne() &&
4030 isARMLowRegister(Inst.getOperand(1).getReg()) &&
4031 isARMLowRegister(Inst.getOperand(2).getReg()))
4032 return Match_RequiresThumb2;
4033 // Others only require ARMv6 or later.
4034 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
4035 isARMLowRegister(Inst.getOperand(0).getReg()) &&
4036 isARMLowRegister(Inst.getOperand(1).getReg()))
4037 return Match_RequiresV6;
4038 return Match_Success;
4042 MatchAndEmitInstruction(SMLoc IDLoc,
4043 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4047 unsigned MatchResult;
4048 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
4049 switch (MatchResult) {
4052 // Context sensitive operand constraints aren't handled by the matcher,
4053 // so check them here.
4054 if (validateInstruction(Inst, Operands)) {
4055 // Still progress the IT block, otherwise one wrong condition causes
4056 // nasty cascading errors.
4057 forwardITPosition();
4061 // Some instructions need post-processing to, for example, tweak which
4062 // encoding is selected.
4063 processInstruction(Inst, Operands);
4065 // Only move forward at the very end so that everything in validate
4066 // and process gets a consistent answer about whether we're in an IT
4068 forwardITPosition();
4070 Out.EmitInstruction(Inst);
4072 case Match_MissingFeature:
4073 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
4075 case Match_InvalidOperand: {
4076 SMLoc ErrorLoc = IDLoc;
4077 if (ErrorInfo != ~0U) {
4078 if (ErrorInfo >= Operands.size())
4079 return Error(IDLoc, "too few operands for instruction");
4081 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
4082 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
4085 return Error(ErrorLoc, "invalid operand for instruction");
4087 case Match_MnemonicFail:
4088 return Error(IDLoc, "invalid instruction");
4089 case Match_ConversionFail:
4090 // The converter function will have already emited a diagnostic.
4092 case Match_RequiresNotITBlock:
4093 return Error(IDLoc, "flag setting instruction only valid outside IT block");
4094 case Match_RequiresITBlock:
4095 return Error(IDLoc, "instruction only valid inside IT block");
4096 case Match_RequiresV6:
4097 return Error(IDLoc, "instruction variant requires ARMv6 or later");
4098 case Match_RequiresThumb2:
4099 return Error(IDLoc, "instruction variant requires Thumb2");
4102 llvm_unreachable("Implement any new match types added!");
4106 /// parseDirective parses the arm specific directives
4107 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
4108 StringRef IDVal = DirectiveID.getIdentifier();
4109 if (IDVal == ".word")
4110 return parseDirectiveWord(4, DirectiveID.getLoc());
4111 else if (IDVal == ".thumb")
4112 return parseDirectiveThumb(DirectiveID.getLoc());
4113 else if (IDVal == ".thumb_func")
4114 return parseDirectiveThumbFunc(DirectiveID.getLoc());
4115 else if (IDVal == ".code")
4116 return parseDirectiveCode(DirectiveID.getLoc());
4117 else if (IDVal == ".syntax")
4118 return parseDirectiveSyntax(DirectiveID.getLoc());
4122 /// parseDirectiveWord
4123 /// ::= .word [ expression (, expression)* ]
4124 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
4125 if (getLexer().isNot(AsmToken::EndOfStatement)) {
4127 const MCExpr *Value;
4128 if (getParser().ParseExpression(Value))
4131 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
4133 if (getLexer().is(AsmToken::EndOfStatement))
4136 // FIXME: Improve diagnostic.
4137 if (getLexer().isNot(AsmToken::Comma))
4138 return Error(L, "unexpected token in directive");
4147 /// parseDirectiveThumb
4149 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
4150 if (getLexer().isNot(AsmToken::EndOfStatement))
4151 return Error(L, "unexpected token in directive");
4154 // TODO: set thumb mode
4155 // TODO: tell the MC streamer the mode
4156 // getParser().getStreamer().Emit???();
4160 /// parseDirectiveThumbFunc
4161 /// ::= .thumbfunc symbol_name
4162 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
4163 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
4164 bool isMachO = MAI.hasSubsectionsViaSymbols();
4167 // Darwin asm has function name after .thumb_func direction
4170 const AsmToken &Tok = Parser.getTok();
4171 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
4172 return Error(L, "unexpected token in .thumb_func directive");
4173 Name = Tok.getString();
4174 Parser.Lex(); // Consume the identifier token.
4177 if (getLexer().isNot(AsmToken::EndOfStatement))
4178 return Error(L, "unexpected token in directive");
4181 // FIXME: assuming function name will be the line following .thumb_func
4183 Name = Parser.getTok().getString();
4186 // Mark symbol as a thumb symbol.
4187 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
4188 getParser().getStreamer().EmitThumbFunc(Func);
4192 /// parseDirectiveSyntax
4193 /// ::= .syntax unified | divided
4194 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
4195 const AsmToken &Tok = Parser.getTok();
4196 if (Tok.isNot(AsmToken::Identifier))
4197 return Error(L, "unexpected token in .syntax directive");
4198 StringRef Mode = Tok.getString();
4199 if (Mode == "unified" || Mode == "UNIFIED")
4201 else if (Mode == "divided" || Mode == "DIVIDED")
4202 return Error(L, "'.syntax divided' arm asssembly not supported");
4204 return Error(L, "unrecognized syntax mode in .syntax directive");
4206 if (getLexer().isNot(AsmToken::EndOfStatement))
4207 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
4210 // TODO tell the MC streamer the mode
4211 // getParser().getStreamer().Emit???();
4215 /// parseDirectiveCode
4216 /// ::= .code 16 | 32
4217 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
4218 const AsmToken &Tok = Parser.getTok();
4219 if (Tok.isNot(AsmToken::Integer))
4220 return Error(L, "unexpected token in .code directive");
4221 int64_t Val = Parser.getTok().getIntVal();
4227 return Error(L, "invalid operand to .code directive");
4229 if (getLexer().isNot(AsmToken::EndOfStatement))
4230 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
4236 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
4240 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
4246 extern "C" void LLVMInitializeARMAsmLexer();
4248 /// Force static initialization.
4249 extern "C" void LLVMInitializeARMAsmParser() {
4250 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
4251 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
4252 LLVMInitializeARMAsmLexer();
4255 #define GET_REGISTER_MATCHER
4256 #define GET_MATCHER_IMPLEMENTATION
4257 #include "ARMGenAsmMatcher.inc"