1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "ARMFPUName.h"
11 #include "ARMFeatures.h"
12 #include "MCTargetDesc/ARMAddressingModes.h"
13 #include "MCTargetDesc/ARMArchName.h"
14 #include "MCTargetDesc/ARMBaseInfo.h"
15 #include "MCTargetDesc/ARMMCExpr.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/ADT/Twine.h"
21 #include "llvm/MC/MCAsmInfo.h"
22 #include "llvm/MC/MCAssembler.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCDisassembler.h"
25 #include "llvm/MC/MCELFStreamer.h"
26 #include "llvm/MC/MCExpr.h"
27 #include "llvm/MC/MCInst.h"
28 #include "llvm/MC/MCInstrDesc.h"
29 #include "llvm/MC/MCInstrInfo.h"
30 #include "llvm/MC/MCObjectFileInfo.h"
31 #include "llvm/MC/MCParser/MCAsmLexer.h"
32 #include "llvm/MC/MCParser/MCAsmParser.h"
33 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
34 #include "llvm/MC/MCRegisterInfo.h"
35 #include "llvm/MC/MCSection.h"
36 #include "llvm/MC/MCStreamer.h"
37 #include "llvm/MC/MCSubtargetInfo.h"
38 #include "llvm/MC/MCSymbol.h"
39 #include "llvm/MC/MCTargetAsmParser.h"
40 #include "llvm/Support/ARMBuildAttributes.h"
41 #include "llvm/Support/ARMEHABI.h"
42 #include "llvm/Support/COFF.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/ELF.h"
45 #include "llvm/Support/MathExtras.h"
46 #include "llvm/Support/SourceMgr.h"
47 #include "llvm/Support/TargetRegistry.h"
48 #include "llvm/Support/raw_ostream.h"
56 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
61 typedef SmallVector<SMLoc, 4> Locs;
66 Locs PersonalityIndexLocs;
71 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
73 bool hasFnStart() const { return !FnStartLocs.empty(); }
74 bool cantUnwind() const { return !CantUnwindLocs.empty(); }
75 bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
76 bool hasPersonality() const {
77 return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
80 void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
81 void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
82 void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
83 void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
84 void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
86 void saveFPReg(int Reg) { FPReg = Reg; }
87 int getFPReg() const { return FPReg; }
89 void emitFnStartLocNotes() const {
90 for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
92 Parser.Note(*FI, ".fnstart was specified here");
94 void emitCantUnwindLocNotes() const {
95 for (Locs::const_iterator UI = CantUnwindLocs.begin(),
96 UE = CantUnwindLocs.end(); UI != UE; ++UI)
97 Parser.Note(*UI, ".cantunwind was specified here");
99 void emitHandlerDataLocNotes() const {
100 for (Locs::const_iterator HI = HandlerDataLocs.begin(),
101 HE = HandlerDataLocs.end(); HI != HE; ++HI)
102 Parser.Note(*HI, ".handlerdata was specified here");
104 void emitPersonalityLocNotes() const {
105 for (Locs::const_iterator PI = PersonalityLocs.begin(),
106 PE = PersonalityLocs.end(),
107 PII = PersonalityIndexLocs.begin(),
108 PIE = PersonalityIndexLocs.end();
109 PI != PE || PII != PIE;) {
110 if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
111 Parser.Note(*PI++, ".personality was specified here");
112 else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
113 Parser.Note(*PII++, ".personalityindex was specified here");
115 llvm_unreachable(".personality and .personalityindex cannot be "
116 "at the same location");
121 FnStartLocs = Locs();
122 CantUnwindLocs = Locs();
123 PersonalityLocs = Locs();
124 HandlerDataLocs = Locs();
125 PersonalityIndexLocs = Locs();
130 class ARMAsmParser : public MCTargetAsmParser {
131 MCSubtargetInfo &STI;
133 const MCInstrInfo &MII;
134 const MCRegisterInfo *MRI;
137 ARMTargetStreamer &getTargetStreamer() {
138 MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
139 return static_cast<ARMTargetStreamer &>(TS);
142 // Map of register aliases registers via the .req directive.
143 StringMap<unsigned> RegisterReqs;
145 bool NextSymbolIsThumb;
148 ARMCC::CondCodes Cond; // Condition for IT block.
149 unsigned Mask:4; // Condition mask for instructions.
150 // Starting at first 1 (from lsb).
151 // '1' condition as indicated in IT.
152 // '0' inverse of condition (else).
153 // Count of instructions in IT block is
154 // 4 - trailingzeroes(mask)
156 bool FirstCond; // Explicit flag for when we're parsing the
157 // First instruction in the IT block. It's
158 // implied in the mask, so needs special
161 unsigned CurPosition; // Current position in parsing of IT
162 // block. In range [0,3]. Initialized
163 // according to count of instructions in block.
164 // ~0U if no active IT block.
166 bool inITBlock() { return ITState.CurPosition != ~0U;}
167 void forwardITPosition() {
168 if (!inITBlock()) return;
169 // Move to the next instruction in the IT block, if there is one. If not,
170 // mark the block as done.
171 unsigned TZ = countTrailingZeros(ITState.Mask);
172 if (++ITState.CurPosition == 5 - TZ)
173 ITState.CurPosition = ~0U; // Done with the IT block after this.
177 MCAsmParser &getParser() const { return Parser; }
178 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
180 void Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges = None) {
181 return Parser.Note(L, Msg, Ranges);
183 bool Warning(SMLoc L, const Twine &Msg,
184 ArrayRef<SMRange> Ranges = None) {
185 return Parser.Warning(L, Msg, Ranges);
187 bool Error(SMLoc L, const Twine &Msg,
188 ArrayRef<SMRange> Ranges = None) {
189 return Parser.Error(L, Msg, Ranges);
192 int tryParseRegister();
193 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
194 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
195 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
196 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
197 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
198 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
199 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
200 unsigned &ShiftAmount);
201 bool parseLiteralValues(unsigned Size, SMLoc L);
202 bool parseDirectiveThumb(SMLoc L);
203 bool parseDirectiveARM(SMLoc L);
204 bool parseDirectiveThumbFunc(SMLoc L);
205 bool parseDirectiveCode(SMLoc L);
206 bool parseDirectiveSyntax(SMLoc L);
207 bool parseDirectiveReq(StringRef Name, SMLoc L);
208 bool parseDirectiveUnreq(SMLoc L);
209 bool parseDirectiveArch(SMLoc L);
210 bool parseDirectiveEabiAttr(SMLoc L);
211 bool parseDirectiveCPU(SMLoc L);
212 bool parseDirectiveFPU(SMLoc L);
213 bool parseDirectiveFnStart(SMLoc L);
214 bool parseDirectiveFnEnd(SMLoc L);
215 bool parseDirectiveCantUnwind(SMLoc L);
216 bool parseDirectivePersonality(SMLoc L);
217 bool parseDirectiveHandlerData(SMLoc L);
218 bool parseDirectiveSetFP(SMLoc L);
219 bool parseDirectivePad(SMLoc L);
220 bool parseDirectiveRegSave(SMLoc L, bool IsVector);
221 bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
222 bool parseDirectiveLtorg(SMLoc L);
223 bool parseDirectiveEven(SMLoc L);
224 bool parseDirectivePersonalityIndex(SMLoc L);
225 bool parseDirectiveUnwindRaw(SMLoc L);
226 bool parseDirectiveTLSDescSeq(SMLoc L);
227 bool parseDirectiveMovSP(SMLoc L);
228 bool parseDirectiveObjectArch(SMLoc L);
229 bool parseDirectiveArchExtension(SMLoc L);
230 bool parseDirectiveAlign(SMLoc L);
231 bool parseDirectiveThumbSet(SMLoc L);
233 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
234 bool &CarrySetting, unsigned &ProcessorIMod,
236 void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
237 bool &CanAcceptCarrySet,
238 bool &CanAcceptPredicationCode);
240 bool isThumb() const {
241 // FIXME: Can tablegen auto-generate this?
242 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
244 bool isThumbOne() const {
245 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
247 bool isThumbTwo() const {
248 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
250 bool hasThumb() const {
251 return STI.getFeatureBits() & ARM::HasV4TOps;
253 bool hasV6Ops() const {
254 return STI.getFeatureBits() & ARM::HasV6Ops;
256 bool hasV6MOps() const {
257 return STI.getFeatureBits() & ARM::HasV6MOps;
259 bool hasV7Ops() const {
260 return STI.getFeatureBits() & ARM::HasV7Ops;
262 bool hasV8Ops() const {
263 return STI.getFeatureBits() & ARM::HasV8Ops;
265 bool hasARM() const {
266 return !(STI.getFeatureBits() & ARM::FeatureNoARM);
270 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
271 setAvailableFeatures(FB);
273 bool isMClass() const {
274 return STI.getFeatureBits() & ARM::FeatureMClass;
277 /// @name Auto-generated Match Functions
280 #define GET_ASSEMBLER_HEADER
281 #include "ARMGenAsmMatcher.inc"
285 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
286 OperandMatchResultTy parseCoprocNumOperand(
287 SmallVectorImpl<MCParsedAsmOperand*>&);
288 OperandMatchResultTy parseCoprocRegOperand(
289 SmallVectorImpl<MCParsedAsmOperand*>&);
290 OperandMatchResultTy parseCoprocOptionOperand(
291 SmallVectorImpl<MCParsedAsmOperand*>&);
292 OperandMatchResultTy parseMemBarrierOptOperand(
293 SmallVectorImpl<MCParsedAsmOperand*>&);
294 OperandMatchResultTy parseInstSyncBarrierOptOperand(
295 SmallVectorImpl<MCParsedAsmOperand*>&);
296 OperandMatchResultTy parseProcIFlagsOperand(
297 SmallVectorImpl<MCParsedAsmOperand*>&);
298 OperandMatchResultTy parseMSRMaskOperand(
299 SmallVectorImpl<MCParsedAsmOperand*>&);
300 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
301 StringRef Op, int Low, int High);
302 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
303 return parsePKHImm(O, "lsl", 0, 31);
305 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
306 return parsePKHImm(O, "asr", 1, 32);
308 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
309 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
310 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
311 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
312 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
313 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
314 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
315 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
316 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
319 // Asm Match Converter Methods
320 void cvtThumbMultiply(MCInst &Inst,
321 const SmallVectorImpl<MCParsedAsmOperand*> &);
322 void cvtThumbBranches(MCInst &Inst,
323 const SmallVectorImpl<MCParsedAsmOperand*> &);
325 bool validateInstruction(MCInst &Inst,
326 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
327 bool processInstruction(MCInst &Inst,
328 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
329 bool shouldOmitCCOutOperand(StringRef Mnemonic,
330 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
331 bool shouldOmitPredicateOperand(StringRef Mnemonic,
332 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
334 enum ARMMatchResultTy {
335 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
336 Match_RequiresNotITBlock,
338 Match_RequiresThumb2,
339 #define GET_OPERAND_DIAGNOSTIC_TYPES
340 #include "ARMGenAsmMatcher.inc"
344 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
345 const MCInstrInfo &MII,
346 const MCTargetOptions &Options)
347 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(MII), UC(_Parser) {
348 MCAsmParserExtension::Initialize(_Parser);
350 // Cache the MCRegisterInfo.
351 MRI = getContext().getRegisterInfo();
353 // Initialize the set of available features.
354 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
356 // Not in an ITBlock to start with.
357 ITState.CurPosition = ~0U;
359 NextSymbolIsThumb = false;
362 // Implementation of the MCTargetAsmParser interface:
363 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
365 ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
367 SmallVectorImpl<MCParsedAsmOperand*> &Operands) override;
368 bool ParseDirective(AsmToken DirectiveID) override;
370 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op,
371 unsigned Kind) override;
372 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
374 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
375 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
376 MCStreamer &Out, unsigned &ErrorInfo,
377 bool MatchingInlineAsm) override;
378 void onLabelParsed(MCSymbol *Symbol) override;
380 } // end anonymous namespace
384 /// ARMOperand - Instances of this class represent a parsed ARM machine
386 class ARMOperand : public MCParsedAsmOperand {
396 k_InstSyncBarrierOpt,
407 k_VectorListAllLanes,
413 k_BitfieldDescriptor,
417 SMLoc StartLoc, EndLoc, AlignmentLoc;
418 SmallVector<unsigned, 8> Registers;
421 ARMCC::CondCodes Val;
428 struct CoprocOptionOp {
441 ARM_ISB::InstSyncBOpt Val;
445 ARM_PROC::IFlags Val;
461 // A vector register list is a sequential list of 1 to 4 registers.
462 struct VectorListOp {
469 struct VectorIndexOp {
477 /// Combined record for all forms of ARM address expressions.
480 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
482 const MCConstantExpr *OffsetImm; // Offset immediate value
483 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
484 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
485 unsigned ShiftImm; // shift for OffsetReg.
486 unsigned Alignment; // 0 = no alignment specified
487 // n = alignment in bytes (2, 4, 8, 16, or 32)
488 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
491 struct PostIdxRegOp {
494 ARM_AM::ShiftOpc ShiftTy;
498 struct ShifterImmOp {
503 struct RegShiftedRegOp {
504 ARM_AM::ShiftOpc ShiftTy;
510 struct RegShiftedImmOp {
511 ARM_AM::ShiftOpc ShiftTy;
528 struct CoprocOptionOp CoprocOption;
529 struct MBOptOp MBOpt;
530 struct ISBOptOp ISBOpt;
531 struct ITMaskOp ITMask;
532 struct IFlagsOp IFlags;
533 struct MMaskOp MMask;
536 struct VectorListOp VectorList;
537 struct VectorIndexOp VectorIndex;
539 struct MemoryOp Memory;
540 struct PostIdxRegOp PostIdxReg;
541 struct ShifterImmOp ShifterImm;
542 struct RegShiftedRegOp RegShiftedReg;
543 struct RegShiftedImmOp RegShiftedImm;
544 struct RotImmOp RotImm;
545 struct BitfieldOp Bitfield;
548 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
550 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
552 StartLoc = o.StartLoc;
569 case k_DPRRegisterList:
570 case k_SPRRegisterList:
571 Registers = o.Registers;
574 case k_VectorListAllLanes:
575 case k_VectorListIndexed:
576 VectorList = o.VectorList;
583 CoprocOption = o.CoprocOption;
588 case k_MemBarrierOpt:
591 case k_InstSyncBarrierOpt:
596 case k_PostIndexRegister:
597 PostIdxReg = o.PostIdxReg;
605 case k_ShifterImmediate:
606 ShifterImm = o.ShifterImm;
608 case k_ShiftedRegister:
609 RegShiftedReg = o.RegShiftedReg;
611 case k_ShiftedImmediate:
612 RegShiftedImm = o.RegShiftedImm;
614 case k_RotateImmediate:
617 case k_BitfieldDescriptor:
618 Bitfield = o.Bitfield;
621 VectorIndex = o.VectorIndex;
626 /// getStartLoc - Get the location of the first token of this operand.
627 SMLoc getStartLoc() const override { return StartLoc; }
628 /// getEndLoc - Get the location of the last token of this operand.
629 SMLoc getEndLoc() const override { return EndLoc; }
630 /// getLocRange - Get the range between the first and last token of this
632 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
634 /// getAlignmentLoc - Get the location of the Alignment token of this operand.
635 SMLoc getAlignmentLoc() const {
636 assert(Kind == k_Memory && "Invalid access!");
640 ARMCC::CondCodes getCondCode() const {
641 assert(Kind == k_CondCode && "Invalid access!");
645 unsigned getCoproc() const {
646 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
650 StringRef getToken() const {
651 assert(Kind == k_Token && "Invalid access!");
652 return StringRef(Tok.Data, Tok.Length);
655 unsigned getReg() const override {
656 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
660 const SmallVectorImpl<unsigned> &getRegList() const {
661 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
662 Kind == k_SPRRegisterList) && "Invalid access!");
666 const MCExpr *getImm() const {
667 assert(isImm() && "Invalid access!");
671 unsigned getVectorIndex() const {
672 assert(Kind == k_VectorIndex && "Invalid access!");
673 return VectorIndex.Val;
676 ARM_MB::MemBOpt getMemBarrierOpt() const {
677 assert(Kind == k_MemBarrierOpt && "Invalid access!");
681 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
682 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
686 ARM_PROC::IFlags getProcIFlags() const {
687 assert(Kind == k_ProcIFlags && "Invalid access!");
691 unsigned getMSRMask() const {
692 assert(Kind == k_MSRMask && "Invalid access!");
696 bool isCoprocNum() const { return Kind == k_CoprocNum; }
697 bool isCoprocReg() const { return Kind == k_CoprocReg; }
698 bool isCoprocOption() const { return Kind == k_CoprocOption; }
699 bool isCondCode() const { return Kind == k_CondCode; }
700 bool isCCOut() const { return Kind == k_CCOut; }
701 bool isITMask() const { return Kind == k_ITCondMask; }
702 bool isITCondCode() const { return Kind == k_CondCode; }
703 bool isImm() const override { return Kind == k_Immediate; }
704 // checks whether this operand is an unsigned offset which fits is a field
705 // of specified width and scaled by a specific number of bits
706 template<unsigned width, unsigned scale>
707 bool isUnsignedOffset() const {
708 if (!isImm()) return false;
709 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
710 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
711 int64_t Val = CE->getValue();
712 int64_t Align = 1LL << scale;
713 int64_t Max = Align * ((1LL << width) - 1);
714 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
718 // checks whether this operand is an signed offset which fits is a field
719 // of specified width and scaled by a specific number of bits
720 template<unsigned width, unsigned scale>
721 bool isSignedOffset() const {
722 if (!isImm()) return false;
723 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
724 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
725 int64_t Val = CE->getValue();
726 int64_t Align = 1LL << scale;
727 int64_t Max = Align * ((1LL << (width-1)) - 1);
728 int64_t Min = -Align * (1LL << (width-1));
729 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
734 // checks whether this operand is a memory operand computed as an offset
735 // applied to PC. the offset may have 8 bits of magnitude and is represented
736 // with two bits of shift. textually it may be either [pc, #imm], #imm or
737 // relocable expression...
738 bool isThumbMemPC() const {
741 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
742 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
743 if (!CE) return false;
744 Val = CE->getValue();
747 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
748 if(Memory.BaseRegNum != ARM::PC) return false;
749 Val = Memory.OffsetImm->getValue();
752 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
754 bool isFPImm() const {
755 if (!isImm()) return false;
756 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
757 if (!CE) return false;
758 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
761 bool isFBits16() const {
762 if (!isImm()) return false;
763 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
764 if (!CE) return false;
765 int64_t Value = CE->getValue();
766 return Value >= 0 && Value <= 16;
768 bool isFBits32() const {
769 if (!isImm()) return false;
770 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
771 if (!CE) return false;
772 int64_t Value = CE->getValue();
773 return Value >= 1 && Value <= 32;
775 bool isImm8s4() const {
776 if (!isImm()) return false;
777 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
778 if (!CE) return false;
779 int64_t Value = CE->getValue();
780 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
782 bool isImm0_1020s4() const {
783 if (!isImm()) return false;
784 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
785 if (!CE) return false;
786 int64_t Value = CE->getValue();
787 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
789 bool isImm0_508s4() const {
790 if (!isImm()) return false;
791 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
792 if (!CE) return false;
793 int64_t Value = CE->getValue();
794 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
796 bool isImm0_508s4Neg() const {
797 if (!isImm()) return false;
798 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
799 if (!CE) return false;
800 int64_t Value = -CE->getValue();
801 // explicitly exclude zero. we want that to use the normal 0_508 version.
802 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
804 bool isImm0_239() const {
805 if (!isImm()) return false;
806 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
807 if (!CE) return false;
808 int64_t Value = CE->getValue();
809 return Value >= 0 && Value < 240;
811 bool isImm0_255() const {
812 if (!isImm()) return false;
813 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
814 if (!CE) return false;
815 int64_t Value = CE->getValue();
816 return Value >= 0 && Value < 256;
818 bool isImm0_4095() const {
819 if (!isImm()) return false;
820 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
821 if (!CE) return false;
822 int64_t Value = CE->getValue();
823 return Value >= 0 && Value < 4096;
825 bool isImm0_4095Neg() const {
826 if (!isImm()) return false;
827 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
828 if (!CE) return false;
829 int64_t Value = -CE->getValue();
830 return Value > 0 && Value < 4096;
832 bool isImm0_1() const {
833 if (!isImm()) return false;
834 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
835 if (!CE) return false;
836 int64_t Value = CE->getValue();
837 return Value >= 0 && Value < 2;
839 bool isImm0_3() const {
840 if (!isImm()) return false;
841 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
842 if (!CE) return false;
843 int64_t Value = CE->getValue();
844 return Value >= 0 && Value < 4;
846 bool isImm0_7() const {
847 if (!isImm()) return false;
848 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
849 if (!CE) return false;
850 int64_t Value = CE->getValue();
851 return Value >= 0 && Value < 8;
853 bool isImm0_15() const {
854 if (!isImm()) return false;
855 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
856 if (!CE) return false;
857 int64_t Value = CE->getValue();
858 return Value >= 0 && Value < 16;
860 bool isImm0_31() const {
861 if (!isImm()) return false;
862 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
863 if (!CE) return false;
864 int64_t Value = CE->getValue();
865 return Value >= 0 && Value < 32;
867 bool isImm0_63() const {
868 if (!isImm()) return false;
869 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
870 if (!CE) return false;
871 int64_t Value = CE->getValue();
872 return Value >= 0 && Value < 64;
874 bool isImm8() const {
875 if (!isImm()) return false;
876 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
877 if (!CE) return false;
878 int64_t Value = CE->getValue();
881 bool isImm16() const {
882 if (!isImm()) return false;
883 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
884 if (!CE) return false;
885 int64_t Value = CE->getValue();
888 bool isImm32() const {
889 if (!isImm()) return false;
890 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
891 if (!CE) return false;
892 int64_t Value = CE->getValue();
895 bool isShrImm8() const {
896 if (!isImm()) return false;
897 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
898 if (!CE) return false;
899 int64_t Value = CE->getValue();
900 return Value > 0 && Value <= 8;
902 bool isShrImm16() const {
903 if (!isImm()) return false;
904 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
905 if (!CE) return false;
906 int64_t Value = CE->getValue();
907 return Value > 0 && Value <= 16;
909 bool isShrImm32() const {
910 if (!isImm()) return false;
911 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
912 if (!CE) return false;
913 int64_t Value = CE->getValue();
914 return Value > 0 && Value <= 32;
916 bool isShrImm64() const {
917 if (!isImm()) return false;
918 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
919 if (!CE) return false;
920 int64_t Value = CE->getValue();
921 return Value > 0 && Value <= 64;
923 bool isImm1_7() const {
924 if (!isImm()) return false;
925 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
926 if (!CE) return false;
927 int64_t Value = CE->getValue();
928 return Value > 0 && Value < 8;
930 bool isImm1_15() const {
931 if (!isImm()) return false;
932 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
933 if (!CE) return false;
934 int64_t Value = CE->getValue();
935 return Value > 0 && Value < 16;
937 bool isImm1_31() const {
938 if (!isImm()) return false;
939 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
940 if (!CE) return false;
941 int64_t Value = CE->getValue();
942 return Value > 0 && Value < 32;
944 bool isImm1_16() const {
945 if (!isImm()) return false;
946 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
947 if (!CE) return false;
948 int64_t Value = CE->getValue();
949 return Value > 0 && Value < 17;
951 bool isImm1_32() const {
952 if (!isImm()) return false;
953 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
954 if (!CE) return false;
955 int64_t Value = CE->getValue();
956 return Value > 0 && Value < 33;
958 bool isImm0_32() const {
959 if (!isImm()) return false;
960 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
961 if (!CE) return false;
962 int64_t Value = CE->getValue();
963 return Value >= 0 && Value < 33;
965 bool isImm0_65535() const {
966 if (!isImm()) return false;
967 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
968 if (!CE) return false;
969 int64_t Value = CE->getValue();
970 return Value >= 0 && Value < 65536;
972 bool isImm256_65535Expr() const {
973 if (!isImm()) return false;
974 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
975 // If it's not a constant expression, it'll generate a fixup and be
977 if (!CE) return true;
978 int64_t Value = CE->getValue();
979 return Value >= 256 && Value < 65536;
981 bool isImm0_65535Expr() const {
982 if (!isImm()) return false;
983 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
984 // If it's not a constant expression, it'll generate a fixup and be
986 if (!CE) return true;
987 int64_t Value = CE->getValue();
988 return Value >= 0 && Value < 65536;
990 bool isImm24bit() const {
991 if (!isImm()) return false;
992 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
993 if (!CE) return false;
994 int64_t Value = CE->getValue();
995 return Value >= 0 && Value <= 0xffffff;
997 bool isImmThumbSR() const {
998 if (!isImm()) return false;
999 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1000 if (!CE) return false;
1001 int64_t Value = CE->getValue();
1002 return Value > 0 && Value < 33;
1004 bool isPKHLSLImm() const {
1005 if (!isImm()) return false;
1006 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1007 if (!CE) return false;
1008 int64_t Value = CE->getValue();
1009 return Value >= 0 && Value < 32;
1011 bool isPKHASRImm() const {
1012 if (!isImm()) return false;
1013 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1014 if (!CE) return false;
1015 int64_t Value = CE->getValue();
1016 return Value > 0 && Value <= 32;
1018 bool isAdrLabel() const {
1019 // If we have an immediate that's not a constant, treat it as a label
1020 // reference needing a fixup. If it is a constant, but it can't fit
1021 // into shift immediate encoding, we reject it.
1022 if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
1023 else return (isARMSOImm() || isARMSOImmNeg());
1025 bool isARMSOImm() const {
1026 if (!isImm()) return false;
1027 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1028 if (!CE) return false;
1029 int64_t Value = CE->getValue();
1030 return ARM_AM::getSOImmVal(Value) != -1;
1032 bool isARMSOImmNot() const {
1033 if (!isImm()) return false;
1034 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1035 if (!CE) return false;
1036 int64_t Value = CE->getValue();
1037 return ARM_AM::getSOImmVal(~Value) != -1;
1039 bool isARMSOImmNeg() const {
1040 if (!isImm()) return false;
1041 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1042 if (!CE) return false;
1043 int64_t Value = CE->getValue();
1044 // Only use this when not representable as a plain so_imm.
1045 return ARM_AM::getSOImmVal(Value) == -1 &&
1046 ARM_AM::getSOImmVal(-Value) != -1;
1048 bool isT2SOImm() const {
1049 if (!isImm()) return false;
1050 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1051 if (!CE) return false;
1052 int64_t Value = CE->getValue();
1053 return ARM_AM::getT2SOImmVal(Value) != -1;
1055 bool isT2SOImmNot() const {
1056 if (!isImm()) return false;
1057 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1058 if (!CE) return false;
1059 int64_t Value = CE->getValue();
1060 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1061 ARM_AM::getT2SOImmVal(~Value) != -1;
1063 bool isT2SOImmNeg() const {
1064 if (!isImm()) return false;
1065 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1066 if (!CE) return false;
1067 int64_t Value = CE->getValue();
1068 // Only use this when not representable as a plain so_imm.
1069 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1070 ARM_AM::getT2SOImmVal(-Value) != -1;
1072 bool isSetEndImm() const {
1073 if (!isImm()) return false;
1074 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1075 if (!CE) return false;
1076 int64_t Value = CE->getValue();
1077 return Value == 1 || Value == 0;
1079 bool isReg() const override { return Kind == k_Register; }
1080 bool isRegList() const { return Kind == k_RegisterList; }
1081 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1082 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1083 bool isToken() const override { return Kind == k_Token; }
1084 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1085 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1086 bool isMem() const override { return Kind == k_Memory; }
1087 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1088 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
1089 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
1090 bool isRotImm() const { return Kind == k_RotateImmediate; }
1091 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1092 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
1093 bool isPostIdxReg() const {
1094 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
1096 bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1099 // No offset of any kind.
1100 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1101 (alignOK || Memory.Alignment == Alignment);
1103 bool isMemPCRelImm12() const {
1104 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1106 // Base register must be PC.
1107 if (Memory.BaseRegNum != ARM::PC)
1109 // Immediate offset in range [-4095, 4095].
1110 if (!Memory.OffsetImm) return true;
1111 int64_t Val = Memory.OffsetImm->getValue();
1112 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1114 bool isAlignedMemory() const {
1115 return isMemNoOffset(true);
1117 bool isAlignedMemoryNone() const {
1118 return isMemNoOffset(false, 0);
1120 bool isDupAlignedMemoryNone() const {
1121 return isMemNoOffset(false, 0);
1123 bool isAlignedMemory16() const {
1124 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1126 return isMemNoOffset(false, 0);
1128 bool isDupAlignedMemory16() const {
1129 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1131 return isMemNoOffset(false, 0);
1133 bool isAlignedMemory32() const {
1134 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1136 return isMemNoOffset(false, 0);
1138 bool isDupAlignedMemory32() const {
1139 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1141 return isMemNoOffset(false, 0);
1143 bool isAlignedMemory64() const {
1144 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1146 return isMemNoOffset(false, 0);
1148 bool isDupAlignedMemory64() const {
1149 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1151 return isMemNoOffset(false, 0);
1153 bool isAlignedMemory64or128() const {
1154 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1156 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1158 return isMemNoOffset(false, 0);
1160 bool isDupAlignedMemory64or128() const {
1161 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1163 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1165 return isMemNoOffset(false, 0);
1167 bool isAlignedMemory64or128or256() const {
1168 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1170 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1172 if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
1174 return isMemNoOffset(false, 0);
1176 bool isAddrMode2() const {
1177 if (!isMem() || Memory.Alignment != 0) return false;
1178 // Check for register offset.
1179 if (Memory.OffsetRegNum) return true;
1180 // Immediate offset in range [-4095, 4095].
1181 if (!Memory.OffsetImm) return true;
1182 int64_t Val = Memory.OffsetImm->getValue();
1183 return Val > -4096 && Val < 4096;
1185 bool isAM2OffsetImm() const {
1186 if (!isImm()) return false;
1187 // Immediate offset in range [-4095, 4095].
1188 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1189 if (!CE) return false;
1190 int64_t Val = CE->getValue();
1191 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1193 bool isAddrMode3() const {
1194 // If we have an immediate that's not a constant, treat it as a label
1195 // reference needing a fixup. If it is a constant, it's something else
1196 // and we reject it.
1197 if (isImm() && !isa<MCConstantExpr>(getImm()))
1199 if (!isMem() || Memory.Alignment != 0) return false;
1200 // No shifts are legal for AM3.
1201 if (Memory.ShiftType != ARM_AM::no_shift) return false;
1202 // Check for register offset.
1203 if (Memory.OffsetRegNum) return true;
1204 // Immediate offset in range [-255, 255].
1205 if (!Memory.OffsetImm) return true;
1206 int64_t Val = Memory.OffsetImm->getValue();
1207 // The #-0 offset is encoded as INT32_MIN, and we have to check
1209 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1211 bool isAM3Offset() const {
1212 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1214 if (Kind == k_PostIndexRegister)
1215 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1216 // Immediate offset in range [-255, 255].
1217 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1218 if (!CE) return false;
1219 int64_t Val = CE->getValue();
1220 // Special case, #-0 is INT32_MIN.
1221 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1223 bool isAddrMode5() const {
1224 // If we have an immediate that's not a constant, treat it as a label
1225 // reference needing a fixup. If it is a constant, it's something else
1226 // and we reject it.
1227 if (isImm() && !isa<MCConstantExpr>(getImm()))
1229 if (!isMem() || Memory.Alignment != 0) return false;
1230 // Check for register offset.
1231 if (Memory.OffsetRegNum) return false;
1232 // Immediate offset in range [-1020, 1020] and a multiple of 4.
1233 if (!Memory.OffsetImm) return true;
1234 int64_t Val = Memory.OffsetImm->getValue();
1235 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1238 bool isMemTBB() const {
1239 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1240 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1244 bool isMemTBH() const {
1245 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1246 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1247 Memory.Alignment != 0 )
1251 bool isMemRegOffset() const {
1252 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1256 bool isT2MemRegOffset() const {
1257 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1258 Memory.Alignment != 0)
1260 // Only lsl #{0, 1, 2, 3} allowed.
1261 if (Memory.ShiftType == ARM_AM::no_shift)
1263 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1267 bool isMemThumbRR() const {
1268 // Thumb reg+reg addressing is simple. Just two registers, a base and
1269 // an offset. No shifts, negations or any other complicating factors.
1270 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1271 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1273 return isARMLowRegister(Memory.BaseRegNum) &&
1274 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1276 bool isMemThumbRIs4() const {
1277 if (!isMem() || Memory.OffsetRegNum != 0 ||
1278 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1280 // Immediate offset, multiple of 4 in range [0, 124].
1281 if (!Memory.OffsetImm) return true;
1282 int64_t Val = Memory.OffsetImm->getValue();
1283 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1285 bool isMemThumbRIs2() const {
1286 if (!isMem() || Memory.OffsetRegNum != 0 ||
1287 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1289 // Immediate offset, multiple of 4 in range [0, 62].
1290 if (!Memory.OffsetImm) return true;
1291 int64_t Val = Memory.OffsetImm->getValue();
1292 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1294 bool isMemThumbRIs1() const {
1295 if (!isMem() || Memory.OffsetRegNum != 0 ||
1296 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1298 // Immediate offset in range [0, 31].
1299 if (!Memory.OffsetImm) return true;
1300 int64_t Val = Memory.OffsetImm->getValue();
1301 return Val >= 0 && Val <= 31;
1303 bool isMemThumbSPI() const {
1304 if (!isMem() || Memory.OffsetRegNum != 0 ||
1305 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1307 // Immediate offset, multiple of 4 in range [0, 1020].
1308 if (!Memory.OffsetImm) return true;
1309 int64_t Val = Memory.OffsetImm->getValue();
1310 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1312 bool isMemImm8s4Offset() const {
1313 // If we have an immediate that's not a constant, treat it as a label
1314 // reference needing a fixup. If it is a constant, it's something else
1315 // and we reject it.
1316 if (isImm() && !isa<MCConstantExpr>(getImm()))
1318 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1320 // Immediate offset a multiple of 4 in range [-1020, 1020].
1321 if (!Memory.OffsetImm) return true;
1322 int64_t Val = Memory.OffsetImm->getValue();
1323 // Special case, #-0 is INT32_MIN.
1324 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1326 bool isMemImm0_1020s4Offset() const {
1327 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1329 // Immediate offset a multiple of 4 in range [0, 1020].
1330 if (!Memory.OffsetImm) return true;
1331 int64_t Val = Memory.OffsetImm->getValue();
1332 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1334 bool isMemImm8Offset() const {
1335 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1337 // Base reg of PC isn't allowed for these encodings.
1338 if (Memory.BaseRegNum == ARM::PC) return false;
1339 // Immediate offset in range [-255, 255].
1340 if (!Memory.OffsetImm) return true;
1341 int64_t Val = Memory.OffsetImm->getValue();
1342 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1344 bool isMemPosImm8Offset() const {
1345 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1347 // Immediate offset in range [0, 255].
1348 if (!Memory.OffsetImm) return true;
1349 int64_t Val = Memory.OffsetImm->getValue();
1350 return Val >= 0 && Val < 256;
1352 bool isMemNegImm8Offset() const {
1353 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1355 // Base reg of PC isn't allowed for these encodings.
1356 if (Memory.BaseRegNum == ARM::PC) return false;
1357 // Immediate offset in range [-255, -1].
1358 if (!Memory.OffsetImm) return false;
1359 int64_t Val = Memory.OffsetImm->getValue();
1360 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1362 bool isMemUImm12Offset() const {
1363 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1365 // Immediate offset in range [0, 4095].
1366 if (!Memory.OffsetImm) return true;
1367 int64_t Val = Memory.OffsetImm->getValue();
1368 return (Val >= 0 && Val < 4096);
1370 bool isMemImm12Offset() const {
1371 // If we have an immediate that's not a constant, treat it as a label
1372 // reference needing a fixup. If it is a constant, it's something else
1373 // and we reject it.
1374 if (isImm() && !isa<MCConstantExpr>(getImm()))
1377 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1379 // Immediate offset in range [-4095, 4095].
1380 if (!Memory.OffsetImm) return true;
1381 int64_t Val = Memory.OffsetImm->getValue();
1382 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1384 bool isPostIdxImm8() const {
1385 if (!isImm()) return false;
1386 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1387 if (!CE) return false;
1388 int64_t Val = CE->getValue();
1389 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1391 bool isPostIdxImm8s4() const {
1392 if (!isImm()) return false;
1393 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1394 if (!CE) return false;
1395 int64_t Val = CE->getValue();
1396 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1400 bool isMSRMask() const { return Kind == k_MSRMask; }
1401 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1404 bool isSingleSpacedVectorList() const {
1405 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1407 bool isDoubleSpacedVectorList() const {
1408 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1410 bool isVecListOneD() const {
1411 if (!isSingleSpacedVectorList()) return false;
1412 return VectorList.Count == 1;
1415 bool isVecListDPair() const {
1416 if (!isSingleSpacedVectorList()) return false;
1417 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1418 .contains(VectorList.RegNum));
1421 bool isVecListThreeD() const {
1422 if (!isSingleSpacedVectorList()) return false;
1423 return VectorList.Count == 3;
1426 bool isVecListFourD() const {
1427 if (!isSingleSpacedVectorList()) return false;
1428 return VectorList.Count == 4;
1431 bool isVecListDPairSpaced() const {
1432 if (Kind != k_VectorList) return false;
1433 if (isSingleSpacedVectorList()) return false;
1434 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1435 .contains(VectorList.RegNum));
1438 bool isVecListThreeQ() const {
1439 if (!isDoubleSpacedVectorList()) return false;
1440 return VectorList.Count == 3;
1443 bool isVecListFourQ() const {
1444 if (!isDoubleSpacedVectorList()) return false;
1445 return VectorList.Count == 4;
1448 bool isSingleSpacedVectorAllLanes() const {
1449 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1451 bool isDoubleSpacedVectorAllLanes() const {
1452 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1454 bool isVecListOneDAllLanes() const {
1455 if (!isSingleSpacedVectorAllLanes()) return false;
1456 return VectorList.Count == 1;
1459 bool isVecListDPairAllLanes() const {
1460 if (!isSingleSpacedVectorAllLanes()) return false;
1461 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1462 .contains(VectorList.RegNum));
1465 bool isVecListDPairSpacedAllLanes() const {
1466 if (!isDoubleSpacedVectorAllLanes()) return false;
1467 return VectorList.Count == 2;
1470 bool isVecListThreeDAllLanes() const {
1471 if (!isSingleSpacedVectorAllLanes()) return false;
1472 return VectorList.Count == 3;
1475 bool isVecListThreeQAllLanes() const {
1476 if (!isDoubleSpacedVectorAllLanes()) return false;
1477 return VectorList.Count == 3;
1480 bool isVecListFourDAllLanes() const {
1481 if (!isSingleSpacedVectorAllLanes()) return false;
1482 return VectorList.Count == 4;
1485 bool isVecListFourQAllLanes() const {
1486 if (!isDoubleSpacedVectorAllLanes()) return false;
1487 return VectorList.Count == 4;
1490 bool isSingleSpacedVectorIndexed() const {
1491 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1493 bool isDoubleSpacedVectorIndexed() const {
1494 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1496 bool isVecListOneDByteIndexed() const {
1497 if (!isSingleSpacedVectorIndexed()) return false;
1498 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1501 bool isVecListOneDHWordIndexed() const {
1502 if (!isSingleSpacedVectorIndexed()) return false;
1503 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1506 bool isVecListOneDWordIndexed() const {
1507 if (!isSingleSpacedVectorIndexed()) return false;
1508 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1511 bool isVecListTwoDByteIndexed() const {
1512 if (!isSingleSpacedVectorIndexed()) return false;
1513 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1516 bool isVecListTwoDHWordIndexed() const {
1517 if (!isSingleSpacedVectorIndexed()) return false;
1518 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1521 bool isVecListTwoQWordIndexed() const {
1522 if (!isDoubleSpacedVectorIndexed()) return false;
1523 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1526 bool isVecListTwoQHWordIndexed() const {
1527 if (!isDoubleSpacedVectorIndexed()) return false;
1528 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1531 bool isVecListTwoDWordIndexed() const {
1532 if (!isSingleSpacedVectorIndexed()) return false;
1533 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1536 bool isVecListThreeDByteIndexed() const {
1537 if (!isSingleSpacedVectorIndexed()) return false;
1538 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1541 bool isVecListThreeDHWordIndexed() const {
1542 if (!isSingleSpacedVectorIndexed()) return false;
1543 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1546 bool isVecListThreeQWordIndexed() const {
1547 if (!isDoubleSpacedVectorIndexed()) return false;
1548 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1551 bool isVecListThreeQHWordIndexed() const {
1552 if (!isDoubleSpacedVectorIndexed()) return false;
1553 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1556 bool isVecListThreeDWordIndexed() const {
1557 if (!isSingleSpacedVectorIndexed()) return false;
1558 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1561 bool isVecListFourDByteIndexed() const {
1562 if (!isSingleSpacedVectorIndexed()) return false;
1563 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1566 bool isVecListFourDHWordIndexed() const {
1567 if (!isSingleSpacedVectorIndexed()) return false;
1568 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1571 bool isVecListFourQWordIndexed() const {
1572 if (!isDoubleSpacedVectorIndexed()) return false;
1573 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1576 bool isVecListFourQHWordIndexed() const {
1577 if (!isDoubleSpacedVectorIndexed()) return false;
1578 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1581 bool isVecListFourDWordIndexed() const {
1582 if (!isSingleSpacedVectorIndexed()) return false;
1583 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1586 bool isVectorIndex8() const {
1587 if (Kind != k_VectorIndex) return false;
1588 return VectorIndex.Val < 8;
1590 bool isVectorIndex16() const {
1591 if (Kind != k_VectorIndex) return false;
1592 return VectorIndex.Val < 4;
1594 bool isVectorIndex32() const {
1595 if (Kind != k_VectorIndex) return false;
1596 return VectorIndex.Val < 2;
1599 bool isNEONi8splat() const {
1600 if (!isImm()) return false;
1601 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1602 // Must be a constant.
1603 if (!CE) return false;
1604 int64_t Value = CE->getValue();
1605 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1607 return Value >= 0 && Value < 256;
1610 bool isNEONi16splat() const {
1611 if (isNEONByteReplicate(2))
1612 return false; // Leave that for bytes replication and forbid by default.
1615 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1616 // Must be a constant.
1617 if (!CE) return false;
1618 int64_t Value = CE->getValue();
1619 // i16 value in the range [0,255] or [0x0100, 0xff00]
1620 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1623 bool isNEONi32splat() const {
1624 if (isNEONByteReplicate(4))
1625 return false; // Leave that for bytes replication and forbid by default.
1628 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1629 // Must be a constant.
1630 if (!CE) return false;
1631 int64_t Value = CE->getValue();
1632 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1633 return (Value >= 0 && Value < 256) ||
1634 (Value >= 0x0100 && Value <= 0xff00) ||
1635 (Value >= 0x010000 && Value <= 0xff0000) ||
1636 (Value >= 0x01000000 && Value <= 0xff000000);
1639 bool isNEONByteReplicate(unsigned NumBytes) const {
1642 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1643 // Must be a constant.
1646 int64_t Value = CE->getValue();
1648 return false; // Don't bother with zero.
1650 unsigned char B = Value & 0xff;
1651 for (unsigned i = 1; i < NumBytes; ++i) {
1653 if ((Value & 0xff) != B)
1658 bool isNEONi16ByteReplicate() const { return isNEONByteReplicate(2); }
1659 bool isNEONi32ByteReplicate() const { return isNEONByteReplicate(4); }
1660 bool isNEONi32vmov() const {
1661 if (isNEONByteReplicate(4))
1662 return false; // Let it to be classified as byte-replicate case.
1665 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1666 // Must be a constant.
1669 int64_t Value = CE->getValue();
1670 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1671 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1672 return (Value >= 0 && Value < 256) ||
1673 (Value >= 0x0100 && Value <= 0xff00) ||
1674 (Value >= 0x010000 && Value <= 0xff0000) ||
1675 (Value >= 0x01000000 && Value <= 0xff000000) ||
1676 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1677 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1679 bool isNEONi32vmovNeg() const {
1680 if (!isImm()) return false;
1681 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1682 // Must be a constant.
1683 if (!CE) return false;
1684 int64_t Value = ~CE->getValue();
1685 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1686 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1687 return (Value >= 0 && Value < 256) ||
1688 (Value >= 0x0100 && Value <= 0xff00) ||
1689 (Value >= 0x010000 && Value <= 0xff0000) ||
1690 (Value >= 0x01000000 && Value <= 0xff000000) ||
1691 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1692 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1695 bool isNEONi64splat() const {
1696 if (!isImm()) return false;
1697 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1698 // Must be a constant.
1699 if (!CE) return false;
1700 uint64_t Value = CE->getValue();
1701 // i64 value with each byte being either 0 or 0xff.
1702 for (unsigned i = 0; i < 8; ++i)
1703 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1707 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1708 // Add as immediates when possible. Null MCExpr = 0.
1710 Inst.addOperand(MCOperand::CreateImm(0));
1711 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1712 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1714 Inst.addOperand(MCOperand::CreateExpr(Expr));
1717 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1718 assert(N == 2 && "Invalid number of operands!");
1719 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1720 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1721 Inst.addOperand(MCOperand::CreateReg(RegNum));
1724 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1725 assert(N == 1 && "Invalid number of operands!");
1726 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1729 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1730 assert(N == 1 && "Invalid number of operands!");
1731 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1734 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1735 assert(N == 1 && "Invalid number of operands!");
1736 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1739 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1740 assert(N == 1 && "Invalid number of operands!");
1741 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1744 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1745 assert(N == 1 && "Invalid number of operands!");
1746 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1749 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1750 assert(N == 1 && "Invalid number of operands!");
1751 Inst.addOperand(MCOperand::CreateReg(getReg()));
1754 void addRegOperands(MCInst &Inst, unsigned N) const {
1755 assert(N == 1 && "Invalid number of operands!");
1756 Inst.addOperand(MCOperand::CreateReg(getReg()));
1759 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1760 assert(N == 3 && "Invalid number of operands!");
1761 assert(isRegShiftedReg() &&
1762 "addRegShiftedRegOperands() on non-RegShiftedReg!");
1763 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1764 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1765 Inst.addOperand(MCOperand::CreateImm(
1766 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1769 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1770 assert(N == 2 && "Invalid number of operands!");
1771 assert(isRegShiftedImm() &&
1772 "addRegShiftedImmOperands() on non-RegShiftedImm!");
1773 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1774 // Shift of #32 is encoded as 0 where permitted
1775 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1776 Inst.addOperand(MCOperand::CreateImm(
1777 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1780 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1781 assert(N == 1 && "Invalid number of operands!");
1782 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1786 void addRegListOperands(MCInst &Inst, unsigned N) const {
1787 assert(N == 1 && "Invalid number of operands!");
1788 const SmallVectorImpl<unsigned> &RegList = getRegList();
1789 for (SmallVectorImpl<unsigned>::const_iterator
1790 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1791 Inst.addOperand(MCOperand::CreateReg(*I));
1794 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1795 addRegListOperands(Inst, N);
1798 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1799 addRegListOperands(Inst, N);
1802 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1803 assert(N == 1 && "Invalid number of operands!");
1804 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1805 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1808 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1809 assert(N == 1 && "Invalid number of operands!");
1810 // Munge the lsb/width into a bitfield mask.
1811 unsigned lsb = Bitfield.LSB;
1812 unsigned width = Bitfield.Width;
1813 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1814 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1815 (32 - (lsb + width)));
1816 Inst.addOperand(MCOperand::CreateImm(Mask));
1819 void addImmOperands(MCInst &Inst, unsigned N) const {
1820 assert(N == 1 && "Invalid number of operands!");
1821 addExpr(Inst, getImm());
1824 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1825 assert(N == 1 && "Invalid number of operands!");
1826 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1827 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1830 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1831 assert(N == 1 && "Invalid number of operands!");
1832 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1833 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1836 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1837 assert(N == 1 && "Invalid number of operands!");
1838 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1839 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1840 Inst.addOperand(MCOperand::CreateImm(Val));
1843 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1844 assert(N == 1 && "Invalid number of operands!");
1845 // FIXME: We really want to scale the value here, but the LDRD/STRD
1846 // instruction don't encode operands that way yet.
1847 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1848 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1851 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1852 assert(N == 1 && "Invalid number of operands!");
1853 // The immediate is scaled by four in the encoding and is stored
1854 // in the MCInst as such. Lop off the low two bits here.
1855 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1856 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1859 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1860 assert(N == 1 && "Invalid number of operands!");
1861 // The immediate is scaled by four in the encoding and is stored
1862 // in the MCInst as such. Lop off the low two bits here.
1863 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1864 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1867 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1868 assert(N == 1 && "Invalid number of operands!");
1869 // The immediate is scaled by four in the encoding and is stored
1870 // in the MCInst as such. Lop off the low two bits here.
1871 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1872 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1875 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1876 assert(N == 1 && "Invalid number of operands!");
1877 // The constant encodes as the immediate-1, and we store in the instruction
1878 // the bits as encoded, so subtract off one here.
1879 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1880 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1883 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1884 assert(N == 1 && "Invalid number of operands!");
1885 // The constant encodes as the immediate-1, and we store in the instruction
1886 // the bits as encoded, so subtract off one here.
1887 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1888 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1891 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1892 assert(N == 1 && "Invalid number of operands!");
1893 // The constant encodes as the immediate, except for 32, which encodes as
1895 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1896 unsigned Imm = CE->getValue();
1897 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1900 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1901 assert(N == 1 && "Invalid number of operands!");
1902 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1903 // the instruction as well.
1904 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1905 int Val = CE->getValue();
1906 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1909 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1910 assert(N == 1 && "Invalid number of operands!");
1911 // The operand is actually a t2_so_imm, but we have its bitwise
1912 // negation in the assembly source, so twiddle it here.
1913 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1914 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1917 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1918 assert(N == 1 && "Invalid number of operands!");
1919 // The operand is actually a t2_so_imm, but we have its
1920 // negation in the assembly source, so twiddle it here.
1921 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1922 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1925 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1926 assert(N == 1 && "Invalid number of operands!");
1927 // The operand is actually an imm0_4095, but we have its
1928 // negation in the assembly source, so twiddle it here.
1929 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1930 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1933 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1934 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1935 Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
1939 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1940 assert(SR && "Unknown value type!");
1941 Inst.addOperand(MCOperand::CreateExpr(SR));
1944 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
1945 assert(N == 1 && "Invalid number of operands!");
1947 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1949 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1953 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1954 assert(SR && "Unknown value type!");
1955 Inst.addOperand(MCOperand::CreateExpr(SR));
1959 assert(isMem() && "Unknown value type!");
1960 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
1961 Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
1964 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1965 assert(N == 1 && "Invalid number of operands!");
1966 // The operand is actually a so_imm, but we have its bitwise
1967 // negation in the assembly source, so twiddle it here.
1968 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1969 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1972 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1973 assert(N == 1 && "Invalid number of operands!");
1974 // The operand is actually a so_imm, but we have its
1975 // negation in the assembly source, so twiddle it here.
1976 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1977 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1980 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1981 assert(N == 1 && "Invalid number of operands!");
1982 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1985 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
1986 assert(N == 1 && "Invalid number of operands!");
1987 Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
1990 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1991 assert(N == 1 && "Invalid number of operands!");
1992 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1995 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1996 assert(N == 1 && "Invalid number of operands!");
1997 int32_t Imm = Memory.OffsetImm->getValue();
1998 Inst.addOperand(MCOperand::CreateImm(Imm));
2001 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
2002 assert(N == 1 && "Invalid number of operands!");
2003 assert(isImm() && "Not an immediate!");
2005 // If we have an immediate that's not a constant, treat it as a label
2006 // reference needing a fixup.
2007 if (!isa<MCConstantExpr>(getImm())) {
2008 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2012 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2013 int Val = CE->getValue();
2014 Inst.addOperand(MCOperand::CreateImm(Val));
2017 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
2018 assert(N == 2 && "Invalid number of operands!");
2019 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2020 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
2023 void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2024 addAlignedMemoryOperands(Inst, N);
2027 void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2028 addAlignedMemoryOperands(Inst, N);
2031 void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2032 addAlignedMemoryOperands(Inst, N);
2035 void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2036 addAlignedMemoryOperands(Inst, N);
2039 void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2040 addAlignedMemoryOperands(Inst, N);
2043 void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2044 addAlignedMemoryOperands(Inst, N);
2047 void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2048 addAlignedMemoryOperands(Inst, N);
2051 void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2052 addAlignedMemoryOperands(Inst, N);
2055 void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2056 addAlignedMemoryOperands(Inst, N);
2059 void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2060 addAlignedMemoryOperands(Inst, N);
2063 void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2064 addAlignedMemoryOperands(Inst, N);
2067 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
2068 assert(N == 3 && "Invalid number of operands!");
2069 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2070 if (!Memory.OffsetRegNum) {
2071 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2072 // Special case for #-0
2073 if (Val == INT32_MIN) Val = 0;
2074 if (Val < 0) Val = -Val;
2075 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2077 // For register offset, we encode the shift type and negation flag
2079 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2080 Memory.ShiftImm, Memory.ShiftType);
2082 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2083 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2084 Inst.addOperand(MCOperand::CreateImm(Val));
2087 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2088 assert(N == 2 && "Invalid number of operands!");
2089 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2090 assert(CE && "non-constant AM2OffsetImm operand!");
2091 int32_t Val = CE->getValue();
2092 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2093 // Special case for #-0
2094 if (Val == INT32_MIN) Val = 0;
2095 if (Val < 0) Val = -Val;
2096 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2097 Inst.addOperand(MCOperand::CreateReg(0));
2098 Inst.addOperand(MCOperand::CreateImm(Val));
2101 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2102 assert(N == 3 && "Invalid number of operands!");
2103 // If we have an immediate that's not a constant, treat it as a label
2104 // reference needing a fixup. If it is a constant, it's something else
2105 // and we reject it.
2107 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2108 Inst.addOperand(MCOperand::CreateReg(0));
2109 Inst.addOperand(MCOperand::CreateImm(0));
2113 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2114 if (!Memory.OffsetRegNum) {
2115 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2116 // Special case for #-0
2117 if (Val == INT32_MIN) Val = 0;
2118 if (Val < 0) Val = -Val;
2119 Val = ARM_AM::getAM3Opc(AddSub, Val);
2121 // For register offset, we encode the shift type and negation flag
2123 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
2125 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2126 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2127 Inst.addOperand(MCOperand::CreateImm(Val));
2130 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
2131 assert(N == 2 && "Invalid number of operands!");
2132 if (Kind == k_PostIndexRegister) {
2134 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
2135 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2136 Inst.addOperand(MCOperand::CreateImm(Val));
2141 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
2142 int32_t Val = CE->getValue();
2143 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2144 // Special case for #-0
2145 if (Val == INT32_MIN) Val = 0;
2146 if (Val < 0) Val = -Val;
2147 Val = ARM_AM::getAM3Opc(AddSub, Val);
2148 Inst.addOperand(MCOperand::CreateReg(0));
2149 Inst.addOperand(MCOperand::CreateImm(Val));
2152 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2153 assert(N == 2 && "Invalid number of operands!");
2154 // If we have an immediate that's not a constant, treat it as a label
2155 // reference needing a fixup. If it is a constant, it's something else
2156 // and we reject it.
2158 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2159 Inst.addOperand(MCOperand::CreateImm(0));
2163 // The lower two bits are always zero and as such are not encoded.
2164 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2165 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2166 // Special case for #-0
2167 if (Val == INT32_MIN) Val = 0;
2168 if (Val < 0) Val = -Val;
2169 Val = ARM_AM::getAM5Opc(AddSub, Val);
2170 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2171 Inst.addOperand(MCOperand::CreateImm(Val));
2174 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2175 assert(N == 2 && "Invalid number of operands!");
2176 // If we have an immediate that's not a constant, treat it as a label
2177 // reference needing a fixup. If it is a constant, it's something else
2178 // and we reject it.
2180 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2181 Inst.addOperand(MCOperand::CreateImm(0));
2185 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2186 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2187 Inst.addOperand(MCOperand::CreateImm(Val));
2190 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2191 assert(N == 2 && "Invalid number of operands!");
2192 // The lower two bits are always zero and as such are not encoded.
2193 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2194 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2195 Inst.addOperand(MCOperand::CreateImm(Val));
2198 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2199 assert(N == 2 && "Invalid number of operands!");
2200 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2201 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2202 Inst.addOperand(MCOperand::CreateImm(Val));
2205 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2206 addMemImm8OffsetOperands(Inst, N);
2209 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2210 addMemImm8OffsetOperands(Inst, N);
2213 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2214 assert(N == 2 && "Invalid number of operands!");
2215 // If this is an immediate, it's a label reference.
2217 addExpr(Inst, getImm());
2218 Inst.addOperand(MCOperand::CreateImm(0));
2222 // Otherwise, it's a normal memory reg+offset.
2223 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2224 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2225 Inst.addOperand(MCOperand::CreateImm(Val));
2228 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2229 assert(N == 2 && "Invalid number of operands!");
2230 // If this is an immediate, it's a label reference.
2232 addExpr(Inst, getImm());
2233 Inst.addOperand(MCOperand::CreateImm(0));
2237 // Otherwise, it's a normal memory reg+offset.
2238 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2239 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2240 Inst.addOperand(MCOperand::CreateImm(Val));
2243 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2244 assert(N == 2 && "Invalid number of operands!");
2245 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2246 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2249 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2250 assert(N == 2 && "Invalid number of operands!");
2251 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2252 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2255 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2256 assert(N == 3 && "Invalid number of operands!");
2258 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2259 Memory.ShiftImm, Memory.ShiftType);
2260 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2261 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2262 Inst.addOperand(MCOperand::CreateImm(Val));
2265 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2266 assert(N == 3 && "Invalid number of operands!");
2267 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2268 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2269 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
2272 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2273 assert(N == 2 && "Invalid number of operands!");
2274 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2275 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2278 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2279 assert(N == 2 && "Invalid number of operands!");
2280 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2281 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2282 Inst.addOperand(MCOperand::CreateImm(Val));
2285 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2286 assert(N == 2 && "Invalid number of operands!");
2287 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2288 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2289 Inst.addOperand(MCOperand::CreateImm(Val));
2292 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2293 assert(N == 2 && "Invalid number of operands!");
2294 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2295 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2296 Inst.addOperand(MCOperand::CreateImm(Val));
2299 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2300 assert(N == 2 && "Invalid number of operands!");
2301 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2302 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2303 Inst.addOperand(MCOperand::CreateImm(Val));
2306 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2307 assert(N == 1 && "Invalid number of operands!");
2308 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2309 assert(CE && "non-constant post-idx-imm8 operand!");
2310 int Imm = CE->getValue();
2311 bool isAdd = Imm >= 0;
2312 if (Imm == INT32_MIN) Imm = 0;
2313 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2314 Inst.addOperand(MCOperand::CreateImm(Imm));
2317 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2318 assert(N == 1 && "Invalid number of operands!");
2319 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2320 assert(CE && "non-constant post-idx-imm8s4 operand!");
2321 int Imm = CE->getValue();
2322 bool isAdd = Imm >= 0;
2323 if (Imm == INT32_MIN) Imm = 0;
2324 // Immediate is scaled by 4.
2325 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2326 Inst.addOperand(MCOperand::CreateImm(Imm));
2329 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2330 assert(N == 2 && "Invalid number of operands!");
2331 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2332 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2335 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2336 assert(N == 2 && "Invalid number of operands!");
2337 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2338 // The sign, shift type, and shift amount are encoded in a single operand
2339 // using the AM2 encoding helpers.
2340 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2341 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2342 PostIdxReg.ShiftTy);
2343 Inst.addOperand(MCOperand::CreateImm(Imm));
2346 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2347 assert(N == 1 && "Invalid number of operands!");
2348 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2351 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2352 assert(N == 1 && "Invalid number of operands!");
2353 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2356 void addVecListOperands(MCInst &Inst, unsigned N) const {
2357 assert(N == 1 && "Invalid number of operands!");
2358 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2361 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2362 assert(N == 2 && "Invalid number of operands!");
2363 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2364 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2367 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2368 assert(N == 1 && "Invalid number of operands!");
2369 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2372 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2373 assert(N == 1 && "Invalid number of operands!");
2374 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2377 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2378 assert(N == 1 && "Invalid number of operands!");
2379 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2382 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2383 assert(N == 1 && "Invalid number of operands!");
2384 // The immediate encodes the type of constant as well as the value.
2385 // Mask in that this is an i8 splat.
2386 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2387 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2390 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2391 assert(N == 1 && "Invalid number of operands!");
2392 // The immediate encodes the type of constant as well as the value.
2393 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2394 unsigned Value = CE->getValue();
2396 Value = (Value >> 8) | 0xa00;
2399 Inst.addOperand(MCOperand::CreateImm(Value));
2402 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2403 assert(N == 1 && "Invalid number of operands!");
2404 // The immediate encodes the type of constant as well as the value.
2405 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2406 unsigned Value = CE->getValue();
2407 if (Value >= 256 && Value <= 0xff00)
2408 Value = (Value >> 8) | 0x200;
2409 else if (Value > 0xffff && Value <= 0xff0000)
2410 Value = (Value >> 16) | 0x400;
2411 else if (Value > 0xffffff)
2412 Value = (Value >> 24) | 0x600;
2413 Inst.addOperand(MCOperand::CreateImm(Value));
2416 void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const {
2417 assert(N == 1 && "Invalid number of operands!");
2418 // The immediate encodes the type of constant as well as the value.
2419 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2420 unsigned Value = CE->getValue();
2421 assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2422 Inst.getOpcode() == ARM::VMOVv16i8) &&
2423 "All vmvn instructions that wants to replicate non-zero byte "
2424 "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2425 unsigned B = ((~Value) & 0xff);
2426 B |= 0xe00; // cmode = 0b1110
2427 Inst.addOperand(MCOperand::CreateImm(B));
2429 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2430 assert(N == 1 && "Invalid number of operands!");
2431 // The immediate encodes the type of constant as well as the value.
2432 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2433 unsigned Value = CE->getValue();
2434 if (Value >= 256 && Value <= 0xffff)
2435 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2436 else if (Value > 0xffff && Value <= 0xffffff)
2437 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2438 else if (Value > 0xffffff)
2439 Value = (Value >> 24) | 0x600;
2440 Inst.addOperand(MCOperand::CreateImm(Value));
2443 void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const {
2444 assert(N == 1 && "Invalid number of operands!");
2445 // The immediate encodes the type of constant as well as the value.
2446 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2447 unsigned Value = CE->getValue();
2448 assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2449 Inst.getOpcode() == ARM::VMOVv16i8) &&
2450 "All instructions that wants to replicate non-zero byte "
2451 "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2452 unsigned B = Value & 0xff;
2453 B |= 0xe00; // cmode = 0b1110
2454 Inst.addOperand(MCOperand::CreateImm(B));
2456 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2457 assert(N == 1 && "Invalid number of operands!");
2458 // The immediate encodes the type of constant as well as the value.
2459 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2460 unsigned Value = ~CE->getValue();
2461 if (Value >= 256 && Value <= 0xffff)
2462 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2463 else if (Value > 0xffff && Value <= 0xffffff)
2464 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2465 else if (Value > 0xffffff)
2466 Value = (Value >> 24) | 0x600;
2467 Inst.addOperand(MCOperand::CreateImm(Value));
2470 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2471 assert(N == 1 && "Invalid number of operands!");
2472 // The immediate encodes the type of constant as well as the value.
2473 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2474 uint64_t Value = CE->getValue();
2476 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2477 Imm |= (Value & 1) << i;
2479 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2482 void print(raw_ostream &OS) const override;
2484 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2485 ARMOperand *Op = new ARMOperand(k_ITCondMask);
2486 Op->ITMask.Mask = Mask;
2492 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2493 ARMOperand *Op = new ARMOperand(k_CondCode);
2500 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2501 ARMOperand *Op = new ARMOperand(k_CoprocNum);
2502 Op->Cop.Val = CopVal;
2508 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2509 ARMOperand *Op = new ARMOperand(k_CoprocReg);
2510 Op->Cop.Val = CopVal;
2516 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2517 ARMOperand *Op = new ARMOperand(k_CoprocOption);
2524 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2525 ARMOperand *Op = new ARMOperand(k_CCOut);
2526 Op->Reg.RegNum = RegNum;
2532 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2533 ARMOperand *Op = new ARMOperand(k_Token);
2534 Op->Tok.Data = Str.data();
2535 Op->Tok.Length = Str.size();
2541 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2542 ARMOperand *Op = new ARMOperand(k_Register);
2543 Op->Reg.RegNum = RegNum;
2549 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2554 ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2555 Op->RegShiftedReg.ShiftTy = ShTy;
2556 Op->RegShiftedReg.SrcReg = SrcReg;
2557 Op->RegShiftedReg.ShiftReg = ShiftReg;
2558 Op->RegShiftedReg.ShiftImm = ShiftImm;
2564 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2568 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2569 Op->RegShiftedImm.ShiftTy = ShTy;
2570 Op->RegShiftedImm.SrcReg = SrcReg;
2571 Op->RegShiftedImm.ShiftImm = ShiftImm;
2577 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2579 ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2580 Op->ShifterImm.isASR = isASR;
2581 Op->ShifterImm.Imm = Imm;
2587 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2588 ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2589 Op->RotImm.Imm = Imm;
2595 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2597 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2598 Op->Bitfield.LSB = LSB;
2599 Op->Bitfield.Width = Width;
2606 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned> > &Regs,
2607 SMLoc StartLoc, SMLoc EndLoc) {
2608 assert (Regs.size() > 0 && "RegList contains no registers?");
2609 KindTy Kind = k_RegisterList;
2611 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2612 Kind = k_DPRRegisterList;
2613 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2614 contains(Regs.front().second))
2615 Kind = k_SPRRegisterList;
2617 // Sort based on the register encoding values.
2618 array_pod_sort(Regs.begin(), Regs.end());
2620 ARMOperand *Op = new ARMOperand(Kind);
2621 for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2622 I = Regs.begin(), E = Regs.end(); I != E; ++I)
2623 Op->Registers.push_back(I->second);
2624 Op->StartLoc = StartLoc;
2625 Op->EndLoc = EndLoc;
2629 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2630 bool isDoubleSpaced, SMLoc S, SMLoc E) {
2631 ARMOperand *Op = new ARMOperand(k_VectorList);
2632 Op->VectorList.RegNum = RegNum;
2633 Op->VectorList.Count = Count;
2634 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2640 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2641 bool isDoubleSpaced,
2643 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2644 Op->VectorList.RegNum = RegNum;
2645 Op->VectorList.Count = Count;
2646 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2652 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2654 bool isDoubleSpaced,
2656 ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2657 Op->VectorList.RegNum = RegNum;
2658 Op->VectorList.Count = Count;
2659 Op->VectorList.LaneIndex = Index;
2660 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2666 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2668 ARMOperand *Op = new ARMOperand(k_VectorIndex);
2669 Op->VectorIndex.Val = Idx;
2675 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2676 ARMOperand *Op = new ARMOperand(k_Immediate);
2683 static ARMOperand *CreateMem(unsigned BaseRegNum,
2684 const MCConstantExpr *OffsetImm,
2685 unsigned OffsetRegNum,
2686 ARM_AM::ShiftOpc ShiftType,
2691 SMLoc AlignmentLoc = SMLoc()) {
2692 ARMOperand *Op = new ARMOperand(k_Memory);
2693 Op->Memory.BaseRegNum = BaseRegNum;
2694 Op->Memory.OffsetImm = OffsetImm;
2695 Op->Memory.OffsetRegNum = OffsetRegNum;
2696 Op->Memory.ShiftType = ShiftType;
2697 Op->Memory.ShiftImm = ShiftImm;
2698 Op->Memory.Alignment = Alignment;
2699 Op->Memory.isNegative = isNegative;
2702 Op->AlignmentLoc = AlignmentLoc;
2706 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2707 ARM_AM::ShiftOpc ShiftTy,
2710 ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2711 Op->PostIdxReg.RegNum = RegNum;
2712 Op->PostIdxReg.isAdd = isAdd;
2713 Op->PostIdxReg.ShiftTy = ShiftTy;
2714 Op->PostIdxReg.ShiftImm = ShiftImm;
2720 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2721 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2722 Op->MBOpt.Val = Opt;
2728 static ARMOperand *CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt,
2730 ARMOperand *Op = new ARMOperand(k_InstSyncBarrierOpt);
2731 Op->ISBOpt.Val = Opt;
2737 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2738 ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2739 Op->IFlags.Val = IFlags;
2745 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2746 ARMOperand *Op = new ARMOperand(k_MSRMask);
2747 Op->MMask.Val = MMask;
2754 } // end anonymous namespace.
2756 void ARMOperand::print(raw_ostream &OS) const {
2759 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2762 OS << "<ccout " << getReg() << ">";
2764 case k_ITCondMask: {
2765 static const char *const MaskStr[] = {
2766 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2767 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2769 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2770 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2774 OS << "<coprocessor number: " << getCoproc() << ">";
2777 OS << "<coprocessor register: " << getCoproc() << ">";
2779 case k_CoprocOption:
2780 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2783 OS << "<mask: " << getMSRMask() << ">";
2786 getImm()->print(OS);
2788 case k_MemBarrierOpt:
2789 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
2791 case k_InstSyncBarrierOpt:
2792 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2796 << " base:" << Memory.BaseRegNum;
2799 case k_PostIndexRegister:
2800 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2801 << PostIdxReg.RegNum;
2802 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2803 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2804 << PostIdxReg.ShiftImm;
2807 case k_ProcIFlags: {
2808 OS << "<ARM_PROC::";
2809 unsigned IFlags = getProcIFlags();
2810 for (int i=2; i >= 0; --i)
2811 if (IFlags & (1 << i))
2812 OS << ARM_PROC::IFlagsToString(1 << i);
2817 OS << "<register " << getReg() << ">";
2819 case k_ShifterImmediate:
2820 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2821 << " #" << ShifterImm.Imm << ">";
2823 case k_ShiftedRegister:
2824 OS << "<so_reg_reg "
2825 << RegShiftedReg.SrcReg << " "
2826 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2827 << " " << RegShiftedReg.ShiftReg << ">";
2829 case k_ShiftedImmediate:
2830 OS << "<so_reg_imm "
2831 << RegShiftedImm.SrcReg << " "
2832 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2833 << " #" << RegShiftedImm.ShiftImm << ">";
2835 case k_RotateImmediate:
2836 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2838 case k_BitfieldDescriptor:
2839 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2840 << ", width: " << Bitfield.Width << ">";
2842 case k_RegisterList:
2843 case k_DPRRegisterList:
2844 case k_SPRRegisterList: {
2845 OS << "<register_list ";
2847 const SmallVectorImpl<unsigned> &RegList = getRegList();
2848 for (SmallVectorImpl<unsigned>::const_iterator
2849 I = RegList.begin(), E = RegList.end(); I != E; ) {
2851 if (++I < E) OS << ", ";
2858 OS << "<vector_list " << VectorList.Count << " * "
2859 << VectorList.RegNum << ">";
2861 case k_VectorListAllLanes:
2862 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2863 << VectorList.RegNum << ">";
2865 case k_VectorListIndexed:
2866 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2867 << VectorList.Count << " * " << VectorList.RegNum << ">";
2870 OS << "'" << getToken() << "'";
2873 OS << "<vectorindex " << getVectorIndex() << ">";
2878 /// @name Auto-generated Match Functions
2881 static unsigned MatchRegisterName(StringRef Name);
2885 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2886 SMLoc &StartLoc, SMLoc &EndLoc) {
2887 StartLoc = Parser.getTok().getLoc();
2888 EndLoc = Parser.getTok().getEndLoc();
2889 RegNo = tryParseRegister();
2891 return (RegNo == (unsigned)-1);
2894 /// Try to parse a register name. The token must be an Identifier when called,
2895 /// and if it is a register name the token is eaten and the register number is
2896 /// returned. Otherwise return -1.
2898 int ARMAsmParser::tryParseRegister() {
2899 const AsmToken &Tok = Parser.getTok();
2900 if (Tok.isNot(AsmToken::Identifier)) return -1;
2902 std::string lowerCase = Tok.getString().lower();
2903 unsigned RegNum = MatchRegisterName(lowerCase);
2905 RegNum = StringSwitch<unsigned>(lowerCase)
2906 .Case("r13", ARM::SP)
2907 .Case("r14", ARM::LR)
2908 .Case("r15", ARM::PC)
2909 .Case("ip", ARM::R12)
2910 // Additional register name aliases for 'gas' compatibility.
2911 .Case("a1", ARM::R0)
2912 .Case("a2", ARM::R1)
2913 .Case("a3", ARM::R2)
2914 .Case("a4", ARM::R3)
2915 .Case("v1", ARM::R4)
2916 .Case("v2", ARM::R5)
2917 .Case("v3", ARM::R6)
2918 .Case("v4", ARM::R7)
2919 .Case("v5", ARM::R8)
2920 .Case("v6", ARM::R9)
2921 .Case("v7", ARM::R10)
2922 .Case("v8", ARM::R11)
2923 .Case("sb", ARM::R9)
2924 .Case("sl", ARM::R10)
2925 .Case("fp", ARM::R11)
2929 // Check for aliases registered via .req. Canonicalize to lower case.
2930 // That's more consistent since register names are case insensitive, and
2931 // it's how the original entry was passed in from MC/MCParser/AsmParser.
2932 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2933 // If no match, return failure.
2934 if (Entry == RegisterReqs.end())
2936 Parser.Lex(); // Eat identifier token.
2937 return Entry->getValue();
2940 Parser.Lex(); // Eat identifier token.
2945 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
2946 // If a recoverable error occurs, return 1. If an irrecoverable error
2947 // occurs, return -1. An irrecoverable error is one where tokens have been
2948 // consumed in the process of trying to parse the shifter (i.e., when it is
2949 // indeed a shifter operand, but malformed).
2950 int ARMAsmParser::tryParseShiftRegister(
2951 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2952 SMLoc S = Parser.getTok().getLoc();
2953 const AsmToken &Tok = Parser.getTok();
2954 if (Tok.isNot(AsmToken::Identifier))
2957 std::string lowerCase = Tok.getString().lower();
2958 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2959 .Case("asl", ARM_AM::lsl)
2960 .Case("lsl", ARM_AM::lsl)
2961 .Case("lsr", ARM_AM::lsr)
2962 .Case("asr", ARM_AM::asr)
2963 .Case("ror", ARM_AM::ror)
2964 .Case("rrx", ARM_AM::rrx)
2965 .Default(ARM_AM::no_shift);
2967 if (ShiftTy == ARM_AM::no_shift)
2970 Parser.Lex(); // Eat the operator.
2972 // The source register for the shift has already been added to the
2973 // operand list, so we need to pop it off and combine it into the shifted
2974 // register operand instead.
2975 std::unique_ptr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2976 if (!PrevOp->isReg())
2977 return Error(PrevOp->getStartLoc(), "shift must be of a register");
2978 int SrcReg = PrevOp->getReg();
2983 if (ShiftTy == ARM_AM::rrx) {
2984 // RRX Doesn't have an explicit shift amount. The encoder expects
2985 // the shift register to be the same as the source register. Seems odd,
2989 // Figure out if this is shifted by a constant or a register (for non-RRX).
2990 if (Parser.getTok().is(AsmToken::Hash) ||
2991 Parser.getTok().is(AsmToken::Dollar)) {
2992 Parser.Lex(); // Eat hash.
2993 SMLoc ImmLoc = Parser.getTok().getLoc();
2994 const MCExpr *ShiftExpr = nullptr;
2995 if (getParser().parseExpression(ShiftExpr, EndLoc)) {
2996 Error(ImmLoc, "invalid immediate shift value");
2999 // The expression must be evaluatable as an immediate.
3000 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
3002 Error(ImmLoc, "invalid immediate shift value");
3005 // Range check the immediate.
3006 // lsl, ror: 0 <= imm <= 31
3007 // lsr, asr: 0 <= imm <= 32
3008 Imm = CE->getValue();
3010 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
3011 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
3012 Error(ImmLoc, "immediate shift value out of range");
3015 // shift by zero is a nop. Always send it through as lsl.
3016 // ('as' compatibility)
3018 ShiftTy = ARM_AM::lsl;
3019 } else if (Parser.getTok().is(AsmToken::Identifier)) {
3020 SMLoc L = Parser.getTok().getLoc();
3021 EndLoc = Parser.getTok().getEndLoc();
3022 ShiftReg = tryParseRegister();
3023 if (ShiftReg == -1) {
3024 Error (L, "expected immediate or register in shift operand");
3028 Error (Parser.getTok().getLoc(),
3029 "expected immediate or register in shift operand");
3034 if (ShiftReg && ShiftTy != ARM_AM::rrx)
3035 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
3039 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
3046 /// Try to parse a register name. The token must be an Identifier when called.
3047 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
3048 /// if there is a "writeback". 'true' if it's not a register.
3050 /// TODO this is likely to change to allow different register types and or to
3051 /// parse for a specific register type.
3053 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3054 const AsmToken &RegTok = Parser.getTok();
3055 int RegNo = tryParseRegister();
3059 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
3060 RegTok.getEndLoc()));
3062 const AsmToken &ExclaimTok = Parser.getTok();
3063 if (ExclaimTok.is(AsmToken::Exclaim)) {
3064 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
3065 ExclaimTok.getLoc()));
3066 Parser.Lex(); // Eat exclaim token
3070 // Also check for an index operand. This is only legal for vector registers,
3071 // but that'll get caught OK in operand matching, so we don't need to
3072 // explicitly filter everything else out here.
3073 if (Parser.getTok().is(AsmToken::LBrac)) {
3074 SMLoc SIdx = Parser.getTok().getLoc();
3075 Parser.Lex(); // Eat left bracket token.
3077 const MCExpr *ImmVal;
3078 if (getParser().parseExpression(ImmVal))
3080 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
3082 return TokError("immediate value expected for vector index");
3084 if (Parser.getTok().isNot(AsmToken::RBrac))
3085 return Error(Parser.getTok().getLoc(), "']' expected");
3087 SMLoc E = Parser.getTok().getEndLoc();
3088 Parser.Lex(); // Eat right bracket token.
3090 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
3098 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
3099 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
3101 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
3102 // Use the same layout as the tablegen'erated register name matcher. Ugly,
3104 switch (Name.size()) {
3107 if (Name[0] != CoprocOp)
3123 if (Name[0] != CoprocOp || Name[1] != '1')
3127 // p10 and p11 are invalid for coproc instructions (reserved for FP/NEON)
3128 case '0': return CoprocOp == 'p'? -1: 10;
3129 case '1': return CoprocOp == 'p'? -1: 11;
3130 case '2': return 12;
3131 case '3': return 13;
3132 case '4': return 14;
3133 case '5': return 15;
3138 /// parseITCondCode - Try to parse a condition code for an IT instruction.
3139 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3140 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3141 SMLoc S = Parser.getTok().getLoc();
3142 const AsmToken &Tok = Parser.getTok();
3143 if (!Tok.is(AsmToken::Identifier))
3144 return MatchOperand_NoMatch;
3145 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
3146 .Case("eq", ARMCC::EQ)
3147 .Case("ne", ARMCC::NE)
3148 .Case("hs", ARMCC::HS)
3149 .Case("cs", ARMCC::HS)
3150 .Case("lo", ARMCC::LO)
3151 .Case("cc", ARMCC::LO)
3152 .Case("mi", ARMCC::MI)
3153 .Case("pl", ARMCC::PL)
3154 .Case("vs", ARMCC::VS)
3155 .Case("vc", ARMCC::VC)
3156 .Case("hi", ARMCC::HI)
3157 .Case("ls", ARMCC::LS)
3158 .Case("ge", ARMCC::GE)
3159 .Case("lt", ARMCC::LT)
3160 .Case("gt", ARMCC::GT)
3161 .Case("le", ARMCC::LE)
3162 .Case("al", ARMCC::AL)
3165 return MatchOperand_NoMatch;
3166 Parser.Lex(); // Eat the token.
3168 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
3170 return MatchOperand_Success;
3173 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
3174 /// token must be an Identifier when called, and if it is a coprocessor
3175 /// number, the token is eaten and the operand is added to the operand list.
3176 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3177 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3178 SMLoc S = Parser.getTok().getLoc();
3179 const AsmToken &Tok = Parser.getTok();
3180 if (Tok.isNot(AsmToken::Identifier))
3181 return MatchOperand_NoMatch;
3183 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
3185 return MatchOperand_NoMatch;
3187 Parser.Lex(); // Eat identifier token.
3188 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
3189 return MatchOperand_Success;
3192 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
3193 /// token must be an Identifier when called, and if it is a coprocessor
3194 /// number, the token is eaten and the operand is added to the operand list.
3195 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3196 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3197 SMLoc S = Parser.getTok().getLoc();
3198 const AsmToken &Tok = Parser.getTok();
3199 if (Tok.isNot(AsmToken::Identifier))
3200 return MatchOperand_NoMatch;
3202 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
3204 return MatchOperand_NoMatch;
3206 Parser.Lex(); // Eat identifier token.
3207 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
3208 return MatchOperand_Success;
3211 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
3212 /// coproc_option : '{' imm0_255 '}'
3213 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3214 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3215 SMLoc S = Parser.getTok().getLoc();
3217 // If this isn't a '{', this isn't a coprocessor immediate operand.
3218 if (Parser.getTok().isNot(AsmToken::LCurly))
3219 return MatchOperand_NoMatch;
3220 Parser.Lex(); // Eat the '{'
3223 SMLoc Loc = Parser.getTok().getLoc();
3224 if (getParser().parseExpression(Expr)) {
3225 Error(Loc, "illegal expression");
3226 return MatchOperand_ParseFail;
3228 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3229 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
3230 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
3231 return MatchOperand_ParseFail;
3233 int Val = CE->getValue();
3235 // Check for and consume the closing '}'
3236 if (Parser.getTok().isNot(AsmToken::RCurly))
3237 return MatchOperand_ParseFail;
3238 SMLoc E = Parser.getTok().getEndLoc();
3239 Parser.Lex(); // Eat the '}'
3241 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
3242 return MatchOperand_Success;
3245 // For register list parsing, we need to map from raw GPR register numbering
3246 // to the enumeration values. The enumeration values aren't sorted by
3247 // register number due to our using "sp", "lr" and "pc" as canonical names.
3248 static unsigned getNextRegister(unsigned Reg) {
3249 // If this is a GPR, we need to do it manually, otherwise we can rely
3250 // on the sort ordering of the enumeration since the other reg-classes
3252 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3255 default: llvm_unreachable("Invalid GPR number!");
3256 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
3257 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
3258 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
3259 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
3260 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
3261 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3262 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
3263 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
3267 // Return the low-subreg of a given Q register.
3268 static unsigned getDRegFromQReg(unsigned QReg) {
3270 default: llvm_unreachable("expected a Q register!");
3271 case ARM::Q0: return ARM::D0;
3272 case ARM::Q1: return ARM::D2;
3273 case ARM::Q2: return ARM::D4;
3274 case ARM::Q3: return ARM::D6;
3275 case ARM::Q4: return ARM::D8;
3276 case ARM::Q5: return ARM::D10;
3277 case ARM::Q6: return ARM::D12;
3278 case ARM::Q7: return ARM::D14;
3279 case ARM::Q8: return ARM::D16;
3280 case ARM::Q9: return ARM::D18;
3281 case ARM::Q10: return ARM::D20;
3282 case ARM::Q11: return ARM::D22;
3283 case ARM::Q12: return ARM::D24;
3284 case ARM::Q13: return ARM::D26;
3285 case ARM::Q14: return ARM::D28;
3286 case ARM::Q15: return ARM::D30;
3290 /// Parse a register list.
3292 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3293 assert(Parser.getTok().is(AsmToken::LCurly) &&
3294 "Token is not a Left Curly Brace");
3295 SMLoc S = Parser.getTok().getLoc();
3296 Parser.Lex(); // Eat '{' token.
3297 SMLoc RegLoc = Parser.getTok().getLoc();
3299 // Check the first register in the list to see what register class
3300 // this is a list of.
3301 int Reg = tryParseRegister();
3303 return Error(RegLoc, "register expected");
3305 // The reglist instructions have at most 16 registers, so reserve
3306 // space for that many.
3308 SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3310 // Allow Q regs and just interpret them as the two D sub-registers.
3311 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3312 Reg = getDRegFromQReg(Reg);
3313 EReg = MRI->getEncodingValue(Reg);
3314 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3317 const MCRegisterClass *RC;
3318 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3319 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3320 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3321 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3322 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3323 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3325 return Error(RegLoc, "invalid register in register list");
3327 // Store the register.
3328 EReg = MRI->getEncodingValue(Reg);
3329 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3331 // This starts immediately after the first register token in the list,
3332 // so we can see either a comma or a minus (range separator) as a legal
3334 while (Parser.getTok().is(AsmToken::Comma) ||
3335 Parser.getTok().is(AsmToken::Minus)) {
3336 if (Parser.getTok().is(AsmToken::Minus)) {
3337 Parser.Lex(); // Eat the minus.
3338 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3339 int EndReg = tryParseRegister();
3341 return Error(AfterMinusLoc, "register expected");
3342 // Allow Q regs and just interpret them as the two D sub-registers.
3343 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3344 EndReg = getDRegFromQReg(EndReg) + 1;
3345 // If the register is the same as the start reg, there's nothing
3349 // The register must be in the same register class as the first.
3350 if (!RC->contains(EndReg))
3351 return Error(AfterMinusLoc, "invalid register in register list");
3352 // Ranges must go from low to high.
3353 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3354 return Error(AfterMinusLoc, "bad range in register list");
3356 // Add all the registers in the range to the register list.
3357 while (Reg != EndReg) {
3358 Reg = getNextRegister(Reg);
3359 EReg = MRI->getEncodingValue(Reg);
3360 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3364 Parser.Lex(); // Eat the comma.
3365 RegLoc = Parser.getTok().getLoc();
3367 const AsmToken RegTok = Parser.getTok();
3368 Reg = tryParseRegister();
3370 return Error(RegLoc, "register expected");
3371 // Allow Q regs and just interpret them as the two D sub-registers.
3372 bool isQReg = false;
3373 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3374 Reg = getDRegFromQReg(Reg);
3377 // The register must be in the same register class as the first.
3378 if (!RC->contains(Reg))
3379 return Error(RegLoc, "invalid register in register list");
3380 // List must be monotonically increasing.
3381 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3382 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3383 Warning(RegLoc, "register list not in ascending order");
3385 return Error(RegLoc, "register list not in ascending order");
3387 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3388 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3389 ") in register list");
3392 // VFP register lists must also be contiguous.
3393 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3395 return Error(RegLoc, "non-contiguous register range");
3396 EReg = MRI->getEncodingValue(Reg);
3397 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3399 EReg = MRI->getEncodingValue(++Reg);
3400 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3404 if (Parser.getTok().isNot(AsmToken::RCurly))
3405 return Error(Parser.getTok().getLoc(), "'}' expected");
3406 SMLoc E = Parser.getTok().getEndLoc();
3407 Parser.Lex(); // Eat '}' token.
3409 // Push the register list operand.
3410 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3412 // The ARM system instruction variants for LDM/STM have a '^' token here.
3413 if (Parser.getTok().is(AsmToken::Caret)) {
3414 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3415 Parser.Lex(); // Eat '^' token.
3421 // Helper function to parse the lane index for vector lists.
3422 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3423 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3424 Index = 0; // Always return a defined index value.
3425 if (Parser.getTok().is(AsmToken::LBrac)) {
3426 Parser.Lex(); // Eat the '['.
3427 if (Parser.getTok().is(AsmToken::RBrac)) {
3428 // "Dn[]" is the 'all lanes' syntax.
3429 LaneKind = AllLanes;
3430 EndLoc = Parser.getTok().getEndLoc();
3431 Parser.Lex(); // Eat the ']'.
3432 return MatchOperand_Success;
3435 // There's an optional '#' token here. Normally there wouldn't be, but
3436 // inline assemble puts one in, and it's friendly to accept that.
3437 if (Parser.getTok().is(AsmToken::Hash))
3438 Parser.Lex(); // Eat '#' or '$'.
3440 const MCExpr *LaneIndex;
3441 SMLoc Loc = Parser.getTok().getLoc();
3442 if (getParser().parseExpression(LaneIndex)) {
3443 Error(Loc, "illegal expression");
3444 return MatchOperand_ParseFail;
3446 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3448 Error(Loc, "lane index must be empty or an integer");
3449 return MatchOperand_ParseFail;
3451 if (Parser.getTok().isNot(AsmToken::RBrac)) {
3452 Error(Parser.getTok().getLoc(), "']' expected");
3453 return MatchOperand_ParseFail;
3455 EndLoc = Parser.getTok().getEndLoc();
3456 Parser.Lex(); // Eat the ']'.
3457 int64_t Val = CE->getValue();
3459 // FIXME: Make this range check context sensitive for .8, .16, .32.
3460 if (Val < 0 || Val > 7) {
3461 Error(Parser.getTok().getLoc(), "lane index out of range");
3462 return MatchOperand_ParseFail;
3465 LaneKind = IndexedLane;
3466 return MatchOperand_Success;
3469 return MatchOperand_Success;
3472 // parse a vector register list
3473 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3474 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3475 VectorLaneTy LaneKind;
3477 SMLoc S = Parser.getTok().getLoc();
3478 // As an extension (to match gas), support a plain D register or Q register
3479 // (without encosing curly braces) as a single or double entry list,
3481 if (Parser.getTok().is(AsmToken::Identifier)) {
3482 SMLoc E = Parser.getTok().getEndLoc();
3483 int Reg = tryParseRegister();
3485 return MatchOperand_NoMatch;
3486 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3487 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3488 if (Res != MatchOperand_Success)
3492 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3495 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3499 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3504 return MatchOperand_Success;
3506 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3507 Reg = getDRegFromQReg(Reg);
3508 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3509 if (Res != MatchOperand_Success)
3513 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3514 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3515 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3518 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3519 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3520 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3524 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3529 return MatchOperand_Success;
3531 Error(S, "vector register expected");
3532 return MatchOperand_ParseFail;
3535 if (Parser.getTok().isNot(AsmToken::LCurly))
3536 return MatchOperand_NoMatch;
3538 Parser.Lex(); // Eat '{' token.
3539 SMLoc RegLoc = Parser.getTok().getLoc();
3541 int Reg = tryParseRegister();
3543 Error(RegLoc, "register expected");
3544 return MatchOperand_ParseFail;
3548 unsigned FirstReg = Reg;
3549 // The list is of D registers, but we also allow Q regs and just interpret
3550 // them as the two D sub-registers.
3551 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3552 FirstReg = Reg = getDRegFromQReg(Reg);
3553 Spacing = 1; // double-spacing requires explicit D registers, otherwise
3554 // it's ambiguous with four-register single spaced.
3560 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3561 return MatchOperand_ParseFail;
3563 while (Parser.getTok().is(AsmToken::Comma) ||
3564 Parser.getTok().is(AsmToken::Minus)) {
3565 if (Parser.getTok().is(AsmToken::Minus)) {
3567 Spacing = 1; // Register range implies a single spaced list.
3568 else if (Spacing == 2) {
3569 Error(Parser.getTok().getLoc(),
3570 "sequential registers in double spaced list");
3571 return MatchOperand_ParseFail;
3573 Parser.Lex(); // Eat the minus.
3574 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3575 int EndReg = tryParseRegister();
3577 Error(AfterMinusLoc, "register expected");
3578 return MatchOperand_ParseFail;
3580 // Allow Q regs and just interpret them as the two D sub-registers.
3581 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3582 EndReg = getDRegFromQReg(EndReg) + 1;
3583 // If the register is the same as the start reg, there's nothing
3587 // The register must be in the same register class as the first.
3588 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3589 Error(AfterMinusLoc, "invalid register in register list");
3590 return MatchOperand_ParseFail;
3592 // Ranges must go from low to high.
3594 Error(AfterMinusLoc, "bad range in register list");
3595 return MatchOperand_ParseFail;
3597 // Parse the lane specifier if present.
3598 VectorLaneTy NextLaneKind;
3599 unsigned NextLaneIndex;
3600 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3601 MatchOperand_Success)
3602 return MatchOperand_ParseFail;
3603 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3604 Error(AfterMinusLoc, "mismatched lane index in register list");
3605 return MatchOperand_ParseFail;
3608 // Add all the registers in the range to the register list.
3609 Count += EndReg - Reg;
3613 Parser.Lex(); // Eat the comma.
3614 RegLoc = Parser.getTok().getLoc();
3616 Reg = tryParseRegister();
3618 Error(RegLoc, "register expected");
3619 return MatchOperand_ParseFail;
3621 // vector register lists must be contiguous.
3622 // It's OK to use the enumeration values directly here rather, as the
3623 // VFP register classes have the enum sorted properly.
3625 // The list is of D registers, but we also allow Q regs and just interpret
3626 // them as the two D sub-registers.
3627 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3629 Spacing = 1; // Register range implies a single spaced list.
3630 else if (Spacing == 2) {
3632 "invalid register in double-spaced list (must be 'D' register')");
3633 return MatchOperand_ParseFail;
3635 Reg = getDRegFromQReg(Reg);
3636 if (Reg != OldReg + 1) {
3637 Error(RegLoc, "non-contiguous register range");
3638 return MatchOperand_ParseFail;
3642 // Parse the lane specifier if present.
3643 VectorLaneTy NextLaneKind;
3644 unsigned NextLaneIndex;
3645 SMLoc LaneLoc = Parser.getTok().getLoc();
3646 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3647 MatchOperand_Success)
3648 return MatchOperand_ParseFail;
3649 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3650 Error(LaneLoc, "mismatched lane index in register list");
3651 return MatchOperand_ParseFail;
3655 // Normal D register.
3656 // Figure out the register spacing (single or double) of the list if
3657 // we don't know it already.
3659 Spacing = 1 + (Reg == OldReg + 2);
3661 // Just check that it's contiguous and keep going.
3662 if (Reg != OldReg + Spacing) {
3663 Error(RegLoc, "non-contiguous register range");
3664 return MatchOperand_ParseFail;
3667 // Parse the lane specifier if present.
3668 VectorLaneTy NextLaneKind;
3669 unsigned NextLaneIndex;
3670 SMLoc EndLoc = Parser.getTok().getLoc();
3671 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3672 return MatchOperand_ParseFail;
3673 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3674 Error(EndLoc, "mismatched lane index in register list");
3675 return MatchOperand_ParseFail;
3679 if (Parser.getTok().isNot(AsmToken::RCurly)) {
3680 Error(Parser.getTok().getLoc(), "'}' expected");
3681 return MatchOperand_ParseFail;
3683 E = Parser.getTok().getEndLoc();
3684 Parser.Lex(); // Eat '}' token.
3688 // Two-register operands have been converted to the
3689 // composite register classes.
3691 const MCRegisterClass *RC = (Spacing == 1) ?
3692 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3693 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3694 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3697 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3698 (Spacing == 2), S, E));
3701 // Two-register operands have been converted to the
3702 // composite register classes.
3704 const MCRegisterClass *RC = (Spacing == 1) ?
3705 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3706 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3707 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3709 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3714 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3720 return MatchOperand_Success;
3723 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3724 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3725 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3726 SMLoc S = Parser.getTok().getLoc();
3727 const AsmToken &Tok = Parser.getTok();
3730 if (Tok.is(AsmToken::Identifier)) {
3731 StringRef OptStr = Tok.getString();
3733 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3734 .Case("sy", ARM_MB::SY)
3735 .Case("st", ARM_MB::ST)
3736 .Case("ld", ARM_MB::LD)
3737 .Case("sh", ARM_MB::ISH)
3738 .Case("ish", ARM_MB::ISH)
3739 .Case("shst", ARM_MB::ISHST)
3740 .Case("ishst", ARM_MB::ISHST)
3741 .Case("ishld", ARM_MB::ISHLD)
3742 .Case("nsh", ARM_MB::NSH)
3743 .Case("un", ARM_MB::NSH)
3744 .Case("nshst", ARM_MB::NSHST)
3745 .Case("nshld", ARM_MB::NSHLD)
3746 .Case("unst", ARM_MB::NSHST)
3747 .Case("osh", ARM_MB::OSH)
3748 .Case("oshst", ARM_MB::OSHST)
3749 .Case("oshld", ARM_MB::OSHLD)
3752 // ishld, oshld, nshld and ld are only available from ARMv8.
3753 if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
3754 Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
3758 return MatchOperand_NoMatch;
3760 Parser.Lex(); // Eat identifier token.
3761 } else if (Tok.is(AsmToken::Hash) ||
3762 Tok.is(AsmToken::Dollar) ||
3763 Tok.is(AsmToken::Integer)) {
3764 if (Parser.getTok().isNot(AsmToken::Integer))
3765 Parser.Lex(); // Eat '#' or '$'.
3766 SMLoc Loc = Parser.getTok().getLoc();
3768 const MCExpr *MemBarrierID;
3769 if (getParser().parseExpression(MemBarrierID)) {
3770 Error(Loc, "illegal expression");
3771 return MatchOperand_ParseFail;
3774 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3776 Error(Loc, "constant expression expected");
3777 return MatchOperand_ParseFail;
3780 int Val = CE->getValue();
3782 Error(Loc, "immediate value out of range");
3783 return MatchOperand_ParseFail;
3786 Opt = ARM_MB::RESERVED_0 + Val;
3788 return MatchOperand_ParseFail;
3790 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3791 return MatchOperand_Success;
3794 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3795 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3796 parseInstSyncBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3797 SMLoc S = Parser.getTok().getLoc();
3798 const AsmToken &Tok = Parser.getTok();
3801 if (Tok.is(AsmToken::Identifier)) {
3802 StringRef OptStr = Tok.getString();
3804 if (OptStr.equals_lower("sy"))
3807 return MatchOperand_NoMatch;
3809 Parser.Lex(); // Eat identifier token.
3810 } else if (Tok.is(AsmToken::Hash) ||
3811 Tok.is(AsmToken::Dollar) ||
3812 Tok.is(AsmToken::Integer)) {
3813 if (Parser.getTok().isNot(AsmToken::Integer))
3814 Parser.Lex(); // Eat '#' or '$'.
3815 SMLoc Loc = Parser.getTok().getLoc();
3817 const MCExpr *ISBarrierID;
3818 if (getParser().parseExpression(ISBarrierID)) {
3819 Error(Loc, "illegal expression");
3820 return MatchOperand_ParseFail;
3823 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3825 Error(Loc, "constant expression expected");
3826 return MatchOperand_ParseFail;
3829 int Val = CE->getValue();
3831 Error(Loc, "immediate value out of range");
3832 return MatchOperand_ParseFail;
3835 Opt = ARM_ISB::RESERVED_0 + Val;
3837 return MatchOperand_ParseFail;
3839 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3840 (ARM_ISB::InstSyncBOpt)Opt, S));
3841 return MatchOperand_Success;
3845 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3846 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3847 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3848 SMLoc S = Parser.getTok().getLoc();
3849 const AsmToken &Tok = Parser.getTok();
3850 if (!Tok.is(AsmToken::Identifier))
3851 return MatchOperand_NoMatch;
3852 StringRef IFlagsStr = Tok.getString();
3854 // An iflags string of "none" is interpreted to mean that none of the AIF
3855 // bits are set. Not a terribly useful instruction, but a valid encoding.
3856 unsigned IFlags = 0;
3857 if (IFlagsStr != "none") {
3858 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3859 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3860 .Case("a", ARM_PROC::A)
3861 .Case("i", ARM_PROC::I)
3862 .Case("f", ARM_PROC::F)
3865 // If some specific iflag is already set, it means that some letter is
3866 // present more than once, this is not acceptable.
3867 if (Flag == ~0U || (IFlags & Flag))
3868 return MatchOperand_NoMatch;
3874 Parser.Lex(); // Eat identifier token.
3875 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3876 return MatchOperand_Success;
3879 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3880 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3881 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3882 SMLoc S = Parser.getTok().getLoc();
3883 const AsmToken &Tok = Parser.getTok();
3884 if (!Tok.is(AsmToken::Identifier))
3885 return MatchOperand_NoMatch;
3886 StringRef Mask = Tok.getString();
3889 // See ARMv6-M 10.1.1
3890 std::string Name = Mask.lower();
3891 unsigned FlagsVal = StringSwitch<unsigned>(Name)
3892 // Note: in the documentation:
3893 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3894 // for MSR APSR_nzcvq.
3895 // but we do make it an alias here. This is so to get the "mask encoding"
3896 // bits correct on MSR APSR writes.
3898 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3899 // should really only be allowed when writing a special register. Note
3900 // they get dropped in the MRS instruction reading a special register as
3901 // the SYSm field is only 8 bits.
3903 // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3904 // includes the DSP extension but that is not checked.
3905 .Case("apsr", 0x800)
3906 .Case("apsr_nzcvq", 0x800)
3907 .Case("apsr_g", 0x400)
3908 .Case("apsr_nzcvqg", 0xc00)
3909 .Case("iapsr", 0x801)
3910 .Case("iapsr_nzcvq", 0x801)
3911 .Case("iapsr_g", 0x401)
3912 .Case("iapsr_nzcvqg", 0xc01)
3913 .Case("eapsr", 0x802)
3914 .Case("eapsr_nzcvq", 0x802)
3915 .Case("eapsr_g", 0x402)
3916 .Case("eapsr_nzcvqg", 0xc02)
3917 .Case("xpsr", 0x803)
3918 .Case("xpsr_nzcvq", 0x803)
3919 .Case("xpsr_g", 0x403)
3920 .Case("xpsr_nzcvqg", 0xc03)
3921 .Case("ipsr", 0x805)
3922 .Case("epsr", 0x806)
3923 .Case("iepsr", 0x807)
3926 .Case("primask", 0x810)
3927 .Case("basepri", 0x811)
3928 .Case("basepri_max", 0x812)
3929 .Case("faultmask", 0x813)
3930 .Case("control", 0x814)
3933 if (FlagsVal == ~0U)
3934 return MatchOperand_NoMatch;
3936 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3937 // basepri, basepri_max and faultmask only valid for V7m.
3938 return MatchOperand_NoMatch;
3940 Parser.Lex(); // Eat identifier token.
3941 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3942 return MatchOperand_Success;
3945 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3946 size_t Start = 0, Next = Mask.find('_');
3947 StringRef Flags = "";
3948 std::string SpecReg = Mask.slice(Start, Next).lower();
3949 if (Next != StringRef::npos)
3950 Flags = Mask.slice(Next+1, Mask.size());
3952 // FlagsVal contains the complete mask:
3954 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3955 unsigned FlagsVal = 0;
3957 if (SpecReg == "apsr") {
3958 FlagsVal = StringSwitch<unsigned>(Flags)
3959 .Case("nzcvq", 0x8) // same as CPSR_f
3960 .Case("g", 0x4) // same as CPSR_s
3961 .Case("nzcvqg", 0xc) // same as CPSR_fs
3964 if (FlagsVal == ~0U) {
3966 return MatchOperand_NoMatch;
3968 FlagsVal = 8; // No flag
3970 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3971 // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3972 if (Flags == "all" || Flags == "")
3974 for (int i = 0, e = Flags.size(); i != e; ++i) {
3975 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3982 // If some specific flag is already set, it means that some letter is
3983 // present more than once, this is not acceptable.
3984 if (FlagsVal == ~0U || (FlagsVal & Flag))
3985 return MatchOperand_NoMatch;
3988 } else // No match for special register.
3989 return MatchOperand_NoMatch;
3991 // Special register without flags is NOT equivalent to "fc" flags.
3992 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
3993 // two lines would enable gas compatibility at the expense of breaking
3999 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4000 if (SpecReg == "spsr")
4003 Parser.Lex(); // Eat identifier token.
4004 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
4005 return MatchOperand_Success;
4008 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4009 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
4010 int Low, int High) {
4011 const AsmToken &Tok = Parser.getTok();
4012 if (Tok.isNot(AsmToken::Identifier)) {
4013 Error(Parser.getTok().getLoc(), Op + " operand expected.");
4014 return MatchOperand_ParseFail;
4016 StringRef ShiftName = Tok.getString();
4017 std::string LowerOp = Op.lower();
4018 std::string UpperOp = Op.upper();
4019 if (ShiftName != LowerOp && ShiftName != UpperOp) {
4020 Error(Parser.getTok().getLoc(), Op + " operand expected.");
4021 return MatchOperand_ParseFail;
4023 Parser.Lex(); // Eat shift type token.
4025 // There must be a '#' and a shift amount.
4026 if (Parser.getTok().isNot(AsmToken::Hash) &&
4027 Parser.getTok().isNot(AsmToken::Dollar)) {
4028 Error(Parser.getTok().getLoc(), "'#' expected");
4029 return MatchOperand_ParseFail;
4031 Parser.Lex(); // Eat hash token.
4033 const MCExpr *ShiftAmount;
4034 SMLoc Loc = Parser.getTok().getLoc();
4036 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4037 Error(Loc, "illegal expression");
4038 return MatchOperand_ParseFail;
4040 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4042 Error(Loc, "constant expression expected");
4043 return MatchOperand_ParseFail;
4045 int Val = CE->getValue();
4046 if (Val < Low || Val > High) {
4047 Error(Loc, "immediate value out of range");
4048 return MatchOperand_ParseFail;
4051 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
4053 return MatchOperand_Success;
4056 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4057 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4058 const AsmToken &Tok = Parser.getTok();
4059 SMLoc S = Tok.getLoc();
4060 if (Tok.isNot(AsmToken::Identifier)) {
4061 Error(S, "'be' or 'le' operand expected");
4062 return MatchOperand_ParseFail;
4064 int Val = StringSwitch<int>(Tok.getString().lower())
4068 Parser.Lex(); // Eat the token.
4071 Error(S, "'be' or 'le' operand expected");
4072 return MatchOperand_ParseFail;
4074 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
4076 S, Tok.getEndLoc()));
4077 return MatchOperand_Success;
4080 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
4081 /// instructions. Legal values are:
4082 /// lsl #n 'n' in [0,31]
4083 /// asr #n 'n' in [1,32]
4084 /// n == 32 encoded as n == 0.
4085 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4086 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4087 const AsmToken &Tok = Parser.getTok();
4088 SMLoc S = Tok.getLoc();
4089 if (Tok.isNot(AsmToken::Identifier)) {
4090 Error(S, "shift operator 'asr' or 'lsl' expected");
4091 return MatchOperand_ParseFail;
4093 StringRef ShiftName = Tok.getString();
4095 if (ShiftName == "lsl" || ShiftName == "LSL")
4097 else if (ShiftName == "asr" || ShiftName == "ASR")
4100 Error(S, "shift operator 'asr' or 'lsl' expected");
4101 return MatchOperand_ParseFail;
4103 Parser.Lex(); // Eat the operator.
4105 // A '#' and a shift amount.
4106 if (Parser.getTok().isNot(AsmToken::Hash) &&
4107 Parser.getTok().isNot(AsmToken::Dollar)) {
4108 Error(Parser.getTok().getLoc(), "'#' expected");
4109 return MatchOperand_ParseFail;
4111 Parser.Lex(); // Eat hash token.
4112 SMLoc ExLoc = Parser.getTok().getLoc();
4114 const MCExpr *ShiftAmount;
4116 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4117 Error(ExLoc, "malformed shift expression");
4118 return MatchOperand_ParseFail;
4120 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4122 Error(ExLoc, "shift amount must be an immediate");
4123 return MatchOperand_ParseFail;
4126 int64_t Val = CE->getValue();
4128 // Shift amount must be in [1,32]
4129 if (Val < 1 || Val > 32) {
4130 Error(ExLoc, "'asr' shift amount must be in range [1,32]");
4131 return MatchOperand_ParseFail;
4133 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
4134 if (isThumb() && Val == 32) {
4135 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
4136 return MatchOperand_ParseFail;
4138 if (Val == 32) Val = 0;
4140 // Shift amount must be in [1,32]
4141 if (Val < 0 || Val > 31) {
4142 Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
4143 return MatchOperand_ParseFail;
4147 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
4149 return MatchOperand_Success;
4152 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
4153 /// of instructions. Legal values are:
4154 /// ror #n 'n' in {0, 8, 16, 24}
4155 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4156 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4157 const AsmToken &Tok = Parser.getTok();
4158 SMLoc S = Tok.getLoc();
4159 if (Tok.isNot(AsmToken::Identifier))
4160 return MatchOperand_NoMatch;
4161 StringRef ShiftName = Tok.getString();
4162 if (ShiftName != "ror" && ShiftName != "ROR")
4163 return MatchOperand_NoMatch;
4164 Parser.Lex(); // Eat the operator.
4166 // A '#' and a rotate amount.
4167 if (Parser.getTok().isNot(AsmToken::Hash) &&
4168 Parser.getTok().isNot(AsmToken::Dollar)) {
4169 Error(Parser.getTok().getLoc(), "'#' expected");
4170 return MatchOperand_ParseFail;
4172 Parser.Lex(); // Eat hash token.
4173 SMLoc ExLoc = Parser.getTok().getLoc();
4175 const MCExpr *ShiftAmount;
4177 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4178 Error(ExLoc, "malformed rotate expression");
4179 return MatchOperand_ParseFail;
4181 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4183 Error(ExLoc, "rotate amount must be an immediate");
4184 return MatchOperand_ParseFail;
4187 int64_t Val = CE->getValue();
4188 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
4189 // normally, zero is represented in asm by omitting the rotate operand
4191 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
4192 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
4193 return MatchOperand_ParseFail;
4196 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
4198 return MatchOperand_Success;
4201 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4202 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4203 SMLoc S = Parser.getTok().getLoc();
4204 // The bitfield descriptor is really two operands, the LSB and the width.
4205 if (Parser.getTok().isNot(AsmToken::Hash) &&
4206 Parser.getTok().isNot(AsmToken::Dollar)) {
4207 Error(Parser.getTok().getLoc(), "'#' expected");
4208 return MatchOperand_ParseFail;
4210 Parser.Lex(); // Eat hash token.
4212 const MCExpr *LSBExpr;
4213 SMLoc E = Parser.getTok().getLoc();
4214 if (getParser().parseExpression(LSBExpr)) {
4215 Error(E, "malformed immediate expression");
4216 return MatchOperand_ParseFail;
4218 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
4220 Error(E, "'lsb' operand must be an immediate");
4221 return MatchOperand_ParseFail;
4224 int64_t LSB = CE->getValue();
4225 // The LSB must be in the range [0,31]
4226 if (LSB < 0 || LSB > 31) {
4227 Error(E, "'lsb' operand must be in the range [0,31]");
4228 return MatchOperand_ParseFail;
4230 E = Parser.getTok().getLoc();
4232 // Expect another immediate operand.
4233 if (Parser.getTok().isNot(AsmToken::Comma)) {
4234 Error(Parser.getTok().getLoc(), "too few operands");
4235 return MatchOperand_ParseFail;
4237 Parser.Lex(); // Eat hash token.
4238 if (Parser.getTok().isNot(AsmToken::Hash) &&
4239 Parser.getTok().isNot(AsmToken::Dollar)) {
4240 Error(Parser.getTok().getLoc(), "'#' expected");
4241 return MatchOperand_ParseFail;
4243 Parser.Lex(); // Eat hash token.
4245 const MCExpr *WidthExpr;
4247 if (getParser().parseExpression(WidthExpr, EndLoc)) {
4248 Error(E, "malformed immediate expression");
4249 return MatchOperand_ParseFail;
4251 CE = dyn_cast<MCConstantExpr>(WidthExpr);
4253 Error(E, "'width' operand must be an immediate");
4254 return MatchOperand_ParseFail;
4257 int64_t Width = CE->getValue();
4258 // The LSB must be in the range [1,32-lsb]
4259 if (Width < 1 || Width > 32 - LSB) {
4260 Error(E, "'width' operand must be in the range [1,32-lsb]");
4261 return MatchOperand_ParseFail;
4264 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4266 return MatchOperand_Success;
4269 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4270 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4271 // Check for a post-index addressing register operand. Specifically:
4272 // postidx_reg := '+' register {, shift}
4273 // | '-' register {, shift}
4274 // | register {, shift}
4276 // This method must return MatchOperand_NoMatch without consuming any tokens
4277 // in the case where there is no match, as other alternatives take other
4279 AsmToken Tok = Parser.getTok();
4280 SMLoc S = Tok.getLoc();
4281 bool haveEaten = false;
4283 if (Tok.is(AsmToken::Plus)) {
4284 Parser.Lex(); // Eat the '+' token.
4286 } else if (Tok.is(AsmToken::Minus)) {
4287 Parser.Lex(); // Eat the '-' token.
4292 SMLoc E = Parser.getTok().getEndLoc();
4293 int Reg = tryParseRegister();
4296 return MatchOperand_NoMatch;
4297 Error(Parser.getTok().getLoc(), "register expected");
4298 return MatchOperand_ParseFail;
4301 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4302 unsigned ShiftImm = 0;
4303 if (Parser.getTok().is(AsmToken::Comma)) {
4304 Parser.Lex(); // Eat the ','.
4305 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4306 return MatchOperand_ParseFail;
4308 // FIXME: Only approximates end...may include intervening whitespace.
4309 E = Parser.getTok().getLoc();
4312 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4315 return MatchOperand_Success;
4318 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4319 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4320 // Check for a post-index addressing register operand. Specifically:
4321 // am3offset := '+' register
4328 // This method must return MatchOperand_NoMatch without consuming any tokens
4329 // in the case where there is no match, as other alternatives take other
4331 AsmToken Tok = Parser.getTok();
4332 SMLoc S = Tok.getLoc();
4334 // Do immediates first, as we always parse those if we have a '#'.
4335 if (Parser.getTok().is(AsmToken::Hash) ||
4336 Parser.getTok().is(AsmToken::Dollar)) {
4337 Parser.Lex(); // Eat '#' or '$'.
4338 // Explicitly look for a '-', as we need to encode negative zero
4340 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4341 const MCExpr *Offset;
4343 if (getParser().parseExpression(Offset, E))
4344 return MatchOperand_ParseFail;
4345 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4347 Error(S, "constant expression expected");
4348 return MatchOperand_ParseFail;
4350 // Negative zero is encoded as the flag value INT32_MIN.
4351 int32_t Val = CE->getValue();
4352 if (isNegative && Val == 0)
4356 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4358 return MatchOperand_Success;
4362 bool haveEaten = false;
4364 if (Tok.is(AsmToken::Plus)) {
4365 Parser.Lex(); // Eat the '+' token.
4367 } else if (Tok.is(AsmToken::Minus)) {
4368 Parser.Lex(); // Eat the '-' token.
4373 Tok = Parser.getTok();
4374 int Reg = tryParseRegister();
4377 return MatchOperand_NoMatch;
4378 Error(Tok.getLoc(), "register expected");
4379 return MatchOperand_ParseFail;
4382 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4383 0, S, Tok.getEndLoc()));
4385 return MatchOperand_Success;
4388 /// Convert parsed operands to MCInst. Needed here because this instruction
4389 /// only has two register operands, but multiplication is commutative so
4390 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4392 cvtThumbMultiply(MCInst &Inst,
4393 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4394 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4395 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4396 // If we have a three-operand form, make sure to set Rn to be the operand
4397 // that isn't the same as Rd.
4399 if (Operands.size() == 6 &&
4400 ((ARMOperand*)Operands[4])->getReg() ==
4401 ((ARMOperand*)Operands[3])->getReg())
4403 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4404 Inst.addOperand(Inst.getOperand(0));
4405 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4409 cvtThumbBranches(MCInst &Inst,
4410 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4411 int CondOp = -1, ImmOp = -1;
4412 switch(Inst.getOpcode()) {
4414 case ARM::tBcc: CondOp = 1; ImmOp = 2; break;
4417 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4419 default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4421 // first decide whether or not the branch should be conditional
4422 // by looking at it's location relative to an IT block
4424 // inside an IT block we cannot have any conditional branches. any
4425 // such instructions needs to be converted to unconditional form
4426 switch(Inst.getOpcode()) {
4427 case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4428 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4431 // outside IT blocks we can only have unconditional branches with AL
4432 // condition code or conditional branches with non-AL condition code
4433 unsigned Cond = static_cast<ARMOperand*>(Operands[CondOp])->getCondCode();
4434 switch(Inst.getOpcode()) {
4437 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4441 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4446 // now decide on encoding size based on branch target range
4447 switch(Inst.getOpcode()) {
4448 // classify tB as either t2B or t1B based on range of immediate operand
4450 ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4451 if(!op->isSignedOffset<11, 1>() && isThumbTwo())
4452 Inst.setOpcode(ARM::t2B);
4455 // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4457 ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4458 if(!op->isSignedOffset<8, 1>() && isThumbTwo())
4459 Inst.setOpcode(ARM::t2Bcc);
4463 ((ARMOperand*)Operands[ImmOp])->addImmOperands(Inst, 1);
4464 ((ARMOperand*)Operands[CondOp])->addCondCodeOperands(Inst, 2);
4467 /// Parse an ARM memory expression, return false if successful else return true
4468 /// or an error. The first token must be a '[' when called.
4470 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4472 assert(Parser.getTok().is(AsmToken::LBrac) &&
4473 "Token is not a Left Bracket");
4474 S = Parser.getTok().getLoc();
4475 Parser.Lex(); // Eat left bracket token.
4477 const AsmToken &BaseRegTok = Parser.getTok();
4478 int BaseRegNum = tryParseRegister();
4479 if (BaseRegNum == -1)
4480 return Error(BaseRegTok.getLoc(), "register expected");
4482 // The next token must either be a comma, a colon or a closing bracket.
4483 const AsmToken &Tok = Parser.getTok();
4484 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4485 !Tok.is(AsmToken::RBrac))
4486 return Error(Tok.getLoc(), "malformed memory operand");
4488 if (Tok.is(AsmToken::RBrac)) {
4489 E = Tok.getEndLoc();
4490 Parser.Lex(); // Eat right bracket token.
4492 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4493 ARM_AM::no_shift, 0, 0, false,
4496 // If there's a pre-indexing writeback marker, '!', just add it as a token
4497 // operand. It's rather odd, but syntactically valid.
4498 if (Parser.getTok().is(AsmToken::Exclaim)) {
4499 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4500 Parser.Lex(); // Eat the '!'.
4506 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4507 "Lost colon or comma in memory operand?!");
4508 if (Tok.is(AsmToken::Comma)) {
4509 Parser.Lex(); // Eat the comma.
4512 // If we have a ':', it's an alignment specifier.
4513 if (Parser.getTok().is(AsmToken::Colon)) {
4514 Parser.Lex(); // Eat the ':'.
4515 E = Parser.getTok().getLoc();
4516 SMLoc AlignmentLoc = Tok.getLoc();
4519 if (getParser().parseExpression(Expr))
4522 // The expression has to be a constant. Memory references with relocations
4523 // don't come through here, as they use the <label> forms of the relevant
4525 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4527 return Error (E, "constant expression expected");
4530 switch (CE->getValue()) {
4533 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4534 case 16: Align = 2; break;
4535 case 32: Align = 4; break;
4536 case 64: Align = 8; break;
4537 case 128: Align = 16; break;
4538 case 256: Align = 32; break;
4541 // Now we should have the closing ']'
4542 if (Parser.getTok().isNot(AsmToken::RBrac))
4543 return Error(Parser.getTok().getLoc(), "']' expected");
4544 E = Parser.getTok().getEndLoc();
4545 Parser.Lex(); // Eat right bracket token.
4547 // Don't worry about range checking the value here. That's handled by
4548 // the is*() predicates.
4549 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4550 ARM_AM::no_shift, 0, Align,
4551 false, S, E, AlignmentLoc));
4553 // If there's a pre-indexing writeback marker, '!', just add it as a token
4555 if (Parser.getTok().is(AsmToken::Exclaim)) {
4556 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4557 Parser.Lex(); // Eat the '!'.
4563 // If we have a '#', it's an immediate offset, else assume it's a register
4564 // offset. Be friendly and also accept a plain integer (without a leading
4565 // hash) for gas compatibility.
4566 if (Parser.getTok().is(AsmToken::Hash) ||
4567 Parser.getTok().is(AsmToken::Dollar) ||
4568 Parser.getTok().is(AsmToken::Integer)) {
4569 if (Parser.getTok().isNot(AsmToken::Integer))
4570 Parser.Lex(); // Eat '#' or '$'.
4571 E = Parser.getTok().getLoc();
4573 bool isNegative = getParser().getTok().is(AsmToken::Minus);
4574 const MCExpr *Offset;
4575 if (getParser().parseExpression(Offset))
4578 // The expression has to be a constant. Memory references with relocations
4579 // don't come through here, as they use the <label> forms of the relevant
4581 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4583 return Error (E, "constant expression expected");
4585 // If the constant was #-0, represent it as INT32_MIN.
4586 int32_t Val = CE->getValue();
4587 if (isNegative && Val == 0)
4588 CE = MCConstantExpr::Create(INT32_MIN, getContext());
4590 // Now we should have the closing ']'
4591 if (Parser.getTok().isNot(AsmToken::RBrac))
4592 return Error(Parser.getTok().getLoc(), "']' expected");
4593 E = Parser.getTok().getEndLoc();
4594 Parser.Lex(); // Eat right bracket token.
4596 // Don't worry about range checking the value here. That's handled by
4597 // the is*() predicates.
4598 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4599 ARM_AM::no_shift, 0, 0,
4602 // If there's a pre-indexing writeback marker, '!', just add it as a token
4604 if (Parser.getTok().is(AsmToken::Exclaim)) {
4605 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4606 Parser.Lex(); // Eat the '!'.
4612 // The register offset is optionally preceded by a '+' or '-'
4613 bool isNegative = false;
4614 if (Parser.getTok().is(AsmToken::Minus)) {
4616 Parser.Lex(); // Eat the '-'.
4617 } else if (Parser.getTok().is(AsmToken::Plus)) {
4619 Parser.Lex(); // Eat the '+'.
4622 E = Parser.getTok().getLoc();
4623 int OffsetRegNum = tryParseRegister();
4624 if (OffsetRegNum == -1)
4625 return Error(E, "register expected");
4627 // If there's a shift operator, handle it.
4628 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4629 unsigned ShiftImm = 0;
4630 if (Parser.getTok().is(AsmToken::Comma)) {
4631 Parser.Lex(); // Eat the ','.
4632 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4636 // Now we should have the closing ']'
4637 if (Parser.getTok().isNot(AsmToken::RBrac))
4638 return Error(Parser.getTok().getLoc(), "']' expected");
4639 E = Parser.getTok().getEndLoc();
4640 Parser.Lex(); // Eat right bracket token.
4642 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum,
4643 ShiftType, ShiftImm, 0, isNegative,
4646 // If there's a pre-indexing writeback marker, '!', just add it as a token
4648 if (Parser.getTok().is(AsmToken::Exclaim)) {
4649 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4650 Parser.Lex(); // Eat the '!'.
4656 /// parseMemRegOffsetShift - one of these two:
4657 /// ( lsl | lsr | asr | ror ) , # shift_amount
4659 /// return true if it parses a shift otherwise it returns false.
4660 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4662 SMLoc Loc = Parser.getTok().getLoc();
4663 const AsmToken &Tok = Parser.getTok();
4664 if (Tok.isNot(AsmToken::Identifier))
4666 StringRef ShiftName = Tok.getString();
4667 if (ShiftName == "lsl" || ShiftName == "LSL" ||
4668 ShiftName == "asl" || ShiftName == "ASL")
4670 else if (ShiftName == "lsr" || ShiftName == "LSR")
4672 else if (ShiftName == "asr" || ShiftName == "ASR")
4674 else if (ShiftName == "ror" || ShiftName == "ROR")
4676 else if (ShiftName == "rrx" || ShiftName == "RRX")
4679 return Error(Loc, "illegal shift operator");
4680 Parser.Lex(); // Eat shift type token.
4682 // rrx stands alone.
4684 if (St != ARM_AM::rrx) {
4685 Loc = Parser.getTok().getLoc();
4686 // A '#' and a shift amount.
4687 const AsmToken &HashTok = Parser.getTok();
4688 if (HashTok.isNot(AsmToken::Hash) &&
4689 HashTok.isNot(AsmToken::Dollar))
4690 return Error(HashTok.getLoc(), "'#' expected");
4691 Parser.Lex(); // Eat hash token.
4694 if (getParser().parseExpression(Expr))
4696 // Range check the immediate.
4697 // lsl, ror: 0 <= imm <= 31
4698 // lsr, asr: 0 <= imm <= 32
4699 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4701 return Error(Loc, "shift amount must be an immediate");
4702 int64_t Imm = CE->getValue();
4704 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4705 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4706 return Error(Loc, "immediate shift value out of range");
4707 // If <ShiftTy> #0, turn it into a no_shift.
4710 // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4719 /// parseFPImm - A floating point immediate expression operand.
4720 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4721 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4722 // Anything that can accept a floating point constant as an operand
4723 // needs to go through here, as the regular parseExpression is
4726 // This routine still creates a generic Immediate operand, containing
4727 // a bitcast of the 64-bit floating point value. The various operands
4728 // that accept floats can check whether the value is valid for them
4729 // via the standard is*() predicates.
4731 SMLoc S = Parser.getTok().getLoc();
4733 if (Parser.getTok().isNot(AsmToken::Hash) &&
4734 Parser.getTok().isNot(AsmToken::Dollar))
4735 return MatchOperand_NoMatch;
4737 // Disambiguate the VMOV forms that can accept an FP immediate.
4738 // vmov.f32 <sreg>, #imm
4739 // vmov.f64 <dreg>, #imm
4740 // vmov.f32 <dreg>, #imm @ vector f32x2
4741 // vmov.f32 <qreg>, #imm @ vector f32x4
4743 // There are also the NEON VMOV instructions which expect an
4744 // integer constant. Make sure we don't try to parse an FPImm
4746 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4747 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4748 bool isVmovf = TyOp->isToken() && (TyOp->getToken() == ".f32" ||
4749 TyOp->getToken() == ".f64");
4750 ARMOperand *Mnemonic = static_cast<ARMOperand*>(Operands[0]);
4751 bool isFconst = Mnemonic->isToken() && (Mnemonic->getToken() == "fconstd" ||
4752 Mnemonic->getToken() == "fconsts");
4753 if (!(isVmovf || isFconst))
4754 return MatchOperand_NoMatch;
4756 Parser.Lex(); // Eat '#' or '$'.
4758 // Handle negation, as that still comes through as a separate token.
4759 bool isNegative = false;
4760 if (Parser.getTok().is(AsmToken::Minus)) {
4764 const AsmToken &Tok = Parser.getTok();
4765 SMLoc Loc = Tok.getLoc();
4766 if (Tok.is(AsmToken::Real) && isVmovf) {
4767 APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4768 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4769 // If we had a '-' in front, toggle the sign bit.
4770 IntVal ^= (uint64_t)isNegative << 31;
4771 Parser.Lex(); // Eat the token.
4772 Operands.push_back(ARMOperand::CreateImm(
4773 MCConstantExpr::Create(IntVal, getContext()),
4774 S, Parser.getTok().getLoc()));
4775 return MatchOperand_Success;
4777 // Also handle plain integers. Instructions which allow floating point
4778 // immediates also allow a raw encoded 8-bit value.
4779 if (Tok.is(AsmToken::Integer) && isFconst) {
4780 int64_t Val = Tok.getIntVal();
4781 Parser.Lex(); // Eat the token.
4782 if (Val > 255 || Val < 0) {
4783 Error(Loc, "encoded floating point value out of range");
4784 return MatchOperand_ParseFail;
4786 float RealVal = ARM_AM::getFPImmFloat(Val);
4787 Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
4789 Operands.push_back(ARMOperand::CreateImm(
4790 MCConstantExpr::Create(Val, getContext()), S,
4791 Parser.getTok().getLoc()));
4792 return MatchOperand_Success;
4795 Error(Loc, "invalid floating point immediate");
4796 return MatchOperand_ParseFail;
4799 /// Parse a arm instruction operand. For now this parses the operand regardless
4800 /// of the mnemonic.
4801 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4802 StringRef Mnemonic) {
4805 // Check if the current operand has a custom associated parser, if so, try to
4806 // custom parse the operand, or fallback to the general approach.
4807 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4808 if (ResTy == MatchOperand_Success)
4810 // If there wasn't a custom match, try the generic matcher below. Otherwise,
4811 // there was a match, but an error occurred, in which case, just return that
4812 // the operand parsing failed.
4813 if (ResTy == MatchOperand_ParseFail)
4816 switch (getLexer().getKind()) {
4818 Error(Parser.getTok().getLoc(), "unexpected token in operand");
4820 case AsmToken::Identifier: {
4821 // If we've seen a branch mnemonic, the next operand must be a label. This
4822 // is true even if the label is a register name. So "br r1" means branch to
4824 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
4826 if (!tryParseRegisterWithWriteBack(Operands))
4828 int Res = tryParseShiftRegister(Operands);
4829 if (Res == 0) // success
4831 else if (Res == -1) // irrecoverable error
4833 // If this is VMRS, check for the apsr_nzcv operand.
4834 if (Mnemonic == "vmrs" &&
4835 Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4836 S = Parser.getTok().getLoc();
4838 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4843 // Fall though for the Identifier case that is not a register or a
4846 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
4847 case AsmToken::Integer: // things like 1f and 2b as a branch targets
4848 case AsmToken::String: // quoted label names.
4849 case AsmToken::Dot: { // . as a branch target
4850 // This was not a register so parse other operands that start with an
4851 // identifier (like labels) as expressions and create them as immediates.
4852 const MCExpr *IdVal;
4853 S = Parser.getTok().getLoc();
4854 if (getParser().parseExpression(IdVal))
4856 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4857 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4860 case AsmToken::LBrac:
4861 return parseMemory(Operands);
4862 case AsmToken::LCurly:
4863 return parseRegisterList(Operands);
4864 case AsmToken::Dollar:
4865 case AsmToken::Hash: {
4866 // #42 -> immediate.
4867 S = Parser.getTok().getLoc();
4870 if (Parser.getTok().isNot(AsmToken::Colon)) {
4871 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4872 const MCExpr *ImmVal;
4873 if (getParser().parseExpression(ImmVal))
4875 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4877 int32_t Val = CE->getValue();
4878 if (isNegative && Val == 0)
4879 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4881 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4882 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4884 // There can be a trailing '!' on operands that we want as a separate
4885 // '!' Token operand. Handle that here. For example, the compatibility
4886 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
4887 if (Parser.getTok().is(AsmToken::Exclaim)) {
4888 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
4889 Parser.getTok().getLoc()));
4890 Parser.Lex(); // Eat exclaim token
4894 // w/ a ':' after the '#', it's just like a plain ':'.
4897 case AsmToken::Colon: {
4898 // ":lower16:" and ":upper16:" expression prefixes
4899 // FIXME: Check it's an expression prefix,
4900 // e.g. (FOO - :lower16:BAR) isn't legal.
4901 ARMMCExpr::VariantKind RefKind;
4902 if (parsePrefix(RefKind))
4905 const MCExpr *SubExprVal;
4906 if (getParser().parseExpression(SubExprVal))
4909 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4911 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4912 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4915 case AsmToken::Equal: {
4916 if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
4917 return Error(Parser.getTok().getLoc(), "unexpected token in operand");
4919 Parser.Lex(); // Eat '='
4920 const MCExpr *SubExprVal;
4921 if (getParser().parseExpression(SubExprVal))
4923 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4925 const MCExpr *CPLoc = getTargetStreamer().addConstantPoolEntry(SubExprVal);
4926 Operands.push_back(ARMOperand::CreateImm(CPLoc, S, E));
4932 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4933 // :lower16: and :upper16:.
4934 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4935 RefKind = ARMMCExpr::VK_ARM_None;
4937 // consume an optional '#' (GNU compatibility)
4938 if (getLexer().is(AsmToken::Hash))
4941 // :lower16: and :upper16: modifiers
4942 assert(getLexer().is(AsmToken::Colon) && "expected a :");
4943 Parser.Lex(); // Eat ':'
4945 if (getLexer().isNot(AsmToken::Identifier)) {
4946 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4950 StringRef IDVal = Parser.getTok().getIdentifier();
4951 if (IDVal == "lower16") {
4952 RefKind = ARMMCExpr::VK_ARM_LO16;
4953 } else if (IDVal == "upper16") {
4954 RefKind = ARMMCExpr::VK_ARM_HI16;
4956 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4961 if (getLexer().isNot(AsmToken::Colon)) {
4962 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4965 Parser.Lex(); // Eat the last ':'
4969 /// \brief Given a mnemonic, split out possible predication code and carry
4970 /// setting letters to form a canonical mnemonic and flags.
4972 // FIXME: Would be nice to autogen this.
4973 // FIXME: This is a bit of a maze of special cases.
4974 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4975 unsigned &PredicationCode,
4977 unsigned &ProcessorIMod,
4978 StringRef &ITMask) {
4979 PredicationCode = ARMCC::AL;
4980 CarrySetting = false;
4983 // Ignore some mnemonics we know aren't predicated forms.
4985 // FIXME: Would be nice to autogen this.
4986 if ((Mnemonic == "movs" && isThumb()) ||
4987 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
4988 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
4989 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
4990 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
4991 Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" ||
4992 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
4993 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
4994 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4995 Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
4996 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" ||
4997 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
4998 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel"))
5001 // First, split out any predication code. Ignore mnemonics we know aren't
5002 // predicated but do have a carry-set and so weren't caught above.
5003 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
5004 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
5005 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
5006 Mnemonic != "sbcs" && Mnemonic != "rscs") {
5007 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
5008 .Case("eq", ARMCC::EQ)
5009 .Case("ne", ARMCC::NE)
5010 .Case("hs", ARMCC::HS)
5011 .Case("cs", ARMCC::HS)
5012 .Case("lo", ARMCC::LO)
5013 .Case("cc", ARMCC::LO)
5014 .Case("mi", ARMCC::MI)
5015 .Case("pl", ARMCC::PL)
5016 .Case("vs", ARMCC::VS)
5017 .Case("vc", ARMCC::VC)
5018 .Case("hi", ARMCC::HI)
5019 .Case("ls", ARMCC::LS)
5020 .Case("ge", ARMCC::GE)
5021 .Case("lt", ARMCC::LT)
5022 .Case("gt", ARMCC::GT)
5023 .Case("le", ARMCC::LE)
5024 .Case("al", ARMCC::AL)
5027 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
5028 PredicationCode = CC;
5032 // Next, determine if we have a carry setting bit. We explicitly ignore all
5033 // the instructions we know end in 's'.
5034 if (Mnemonic.endswith("s") &&
5035 !(Mnemonic == "cps" || Mnemonic == "mls" ||
5036 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
5037 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
5038 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
5039 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
5040 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
5041 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
5042 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
5043 Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
5044 (Mnemonic == "movs" && isThumb()))) {
5045 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
5046 CarrySetting = true;
5049 // The "cps" instruction can have a interrupt mode operand which is glued into
5050 // the mnemonic. Check if this is the case, split it and parse the imod op
5051 if (Mnemonic.startswith("cps")) {
5052 // Split out any imod code.
5054 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
5055 .Case("ie", ARM_PROC::IE)
5056 .Case("id", ARM_PROC::ID)
5059 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
5060 ProcessorIMod = IMod;
5064 // The "it" instruction has the condition mask on the end of the mnemonic.
5065 if (Mnemonic.startswith("it")) {
5066 ITMask = Mnemonic.slice(2, Mnemonic.size());
5067 Mnemonic = Mnemonic.slice(0, 2);
5073 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
5074 /// inclusion of carry set or predication code operands.
5076 // FIXME: It would be nice to autogen this.
5078 getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
5079 bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) {
5080 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5081 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
5082 Mnemonic == "add" || Mnemonic == "adc" ||
5083 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
5084 Mnemonic == "orr" || Mnemonic == "mvn" ||
5085 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
5086 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
5087 Mnemonic == "vfm" || Mnemonic == "vfnm" ||
5088 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
5089 Mnemonic == "mla" || Mnemonic == "smlal" ||
5090 Mnemonic == "umlal" || Mnemonic == "umull"))) {
5091 CanAcceptCarrySet = true;
5093 CanAcceptCarrySet = false;
5095 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
5096 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
5097 Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic.startswith("crc32") ||
5098 Mnemonic.startswith("cps") || Mnemonic.startswith("vsel") ||
5099 Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
5100 Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
5101 Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
5102 Mnemonic == "vrintm" || Mnemonic.startswith("aes") ||
5103 Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
5104 (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) {
5105 // These mnemonics are never predicable
5106 CanAcceptPredicationCode = false;
5107 } else if (!isThumb()) {
5108 // Some instructions are only predicable in Thumb mode
5109 CanAcceptPredicationCode
5110 = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
5111 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
5112 Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
5113 Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
5114 Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
5115 Mnemonic != "stc2" && Mnemonic != "stc2l" &&
5116 !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
5117 } else if (isThumbOne()) {
5119 CanAcceptPredicationCode = Mnemonic != "movs";
5121 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
5123 CanAcceptPredicationCode = true;
5126 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
5127 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5128 // FIXME: This is all horribly hacky. We really need a better way to deal
5129 // with optional operands like this in the matcher table.
5131 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
5132 // another does not. Specifically, the MOVW instruction does not. So we
5133 // special case it here and remove the defaulted (non-setting) cc_out
5134 // operand if that's the instruction we're trying to match.
5136 // We do this as post-processing of the explicit operands rather than just
5137 // conditionally adding the cc_out in the first place because we need
5138 // to check the type of the parsed immediate operand.
5139 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
5140 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
5141 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
5142 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
5145 // Register-register 'add' for thumb does not have a cc_out operand
5146 // when there are only two register operands.
5147 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
5148 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5149 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5150 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
5152 // Register-register 'add' for thumb does not have a cc_out operand
5153 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
5154 // have to check the immediate range here since Thumb2 has a variant
5155 // that can handle a different range and has a cc_out operand.
5156 if (((isThumb() && Mnemonic == "add") ||
5157 (isThumbTwo() && Mnemonic == "sub")) &&
5158 Operands.size() == 6 &&
5159 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5160 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5161 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
5162 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5163 ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
5164 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
5166 // For Thumb2, add/sub immediate does not have a cc_out operand for the
5167 // imm0_4095 variant. That's the least-preferred variant when
5168 // selecting via the generic "add" mnemonic, so to know that we
5169 // should remove the cc_out operand, we have to explicitly check that
5170 // it's not one of the other variants. Ugh.
5171 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
5172 Operands.size() == 6 &&
5173 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5174 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5175 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5176 // Nest conditions rather than one big 'if' statement for readability.
5178 // If both registers are low, we're in an IT block, and the immediate is
5179 // in range, we should use encoding T1 instead, which has a cc_out.
5181 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
5182 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
5183 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
5185 // Check against T3. If the second register is the PC, this is an
5186 // alternate form of ADR, which uses encoding T4, so check for that too.
5187 if (static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
5188 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
5191 // Otherwise, we use encoding T4, which does not have a cc_out
5196 // The thumb2 multiply instruction doesn't have a CCOut register, so
5197 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
5198 // use the 16-bit encoding or not.
5199 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5200 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5201 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5202 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5203 static_cast<ARMOperand*>(Operands[5])->isReg() &&
5204 // If the registers aren't low regs, the destination reg isn't the
5205 // same as one of the source regs, or the cc_out operand is zero
5206 // outside of an IT block, we have to use the 32-bit encoding, so
5207 // remove the cc_out operand.
5208 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
5209 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
5210 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
5212 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
5213 static_cast<ARMOperand*>(Operands[5])->getReg() &&
5214 static_cast<ARMOperand*>(Operands[3])->getReg() !=
5215 static_cast<ARMOperand*>(Operands[4])->getReg())))
5218 // Also check the 'mul' syntax variant that doesn't specify an explicit
5219 // destination register.
5220 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5221 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5222 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5223 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5224 // If the registers aren't low regs or the cc_out operand is zero
5225 // outside of an IT block, we have to use the 32-bit encoding, so
5226 // remove the cc_out operand.
5227 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
5228 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
5234 // Register-register 'add/sub' for thumb does not have a cc_out operand
5235 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5236 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
5237 // right, this will result in better diagnostics (which operand is off)
5239 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
5240 (Operands.size() == 5 || Operands.size() == 6) &&
5241 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5242 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
5243 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5244 (static_cast<ARMOperand*>(Operands[4])->isImm() ||
5245 (Operands.size() == 6 &&
5246 static_cast<ARMOperand*>(Operands[5])->isImm())))
5252 bool ARMAsmParser::shouldOmitPredicateOperand(
5253 StringRef Mnemonic, SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
5254 // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
5255 unsigned RegIdx = 3;
5256 if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
5257 static_cast<ARMOperand *>(Operands[2])->getToken() == ".f32") {
5258 if (static_cast<ARMOperand *>(Operands[3])->isToken() &&
5259 static_cast<ARMOperand *>(Operands[3])->getToken() == ".f32")
5262 if (static_cast<ARMOperand *>(Operands[RegIdx])->isReg() &&
5263 (ARMMCRegisterClasses[ARM::DPRRegClassID]
5264 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg()) ||
5265 ARMMCRegisterClasses[ARM::QPRRegClassID]
5266 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg())))
5272 static bool isDataTypeToken(StringRef Tok) {
5273 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5274 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5275 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5276 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5277 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5278 Tok == ".f" || Tok == ".d";
5281 // FIXME: This bit should probably be handled via an explicit match class
5282 // in the .td files that matches the suffix instead of having it be
5283 // a literal string token the way it is now.
5284 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5285 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5287 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
5288 unsigned VariantID);
5290 static bool RequiresVFPRegListValidation(StringRef Inst,
5291 bool &AcceptSinglePrecisionOnly,
5292 bool &AcceptDoublePrecisionOnly) {
5293 if (Inst.size() < 7)
5296 if (Inst.startswith("fldm") || Inst.startswith("fstm")) {
5297 StringRef AddressingMode = Inst.substr(4, 2);
5298 if (AddressingMode == "ia" || AddressingMode == "db" ||
5299 AddressingMode == "ea" || AddressingMode == "fd") {
5300 AcceptSinglePrecisionOnly = Inst[6] == 's';
5301 AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x';
5309 /// Parse an arm instruction mnemonic followed by its operands.
5310 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5312 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5313 // FIXME: Can this be done via tablegen in some fashion?
5314 bool RequireVFPRegisterListCheck;
5315 bool AcceptSinglePrecisionOnly;
5316 bool AcceptDoublePrecisionOnly;
5317 RequireVFPRegisterListCheck =
5318 RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly,
5319 AcceptDoublePrecisionOnly);
5321 // Apply mnemonic aliases before doing anything else, as the destination
5322 // mnemonic may include suffices and we want to handle them normally.
5323 // The generic tblgen'erated code does this later, at the start of
5324 // MatchInstructionImpl(), but that's too late for aliases that include
5325 // any sort of suffix.
5326 unsigned AvailableFeatures = getAvailableFeatures();
5327 unsigned AssemblerDialect = getParser().getAssemblerDialect();
5328 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5330 // First check for the ARM-specific .req directive.
5331 if (Parser.getTok().is(AsmToken::Identifier) &&
5332 Parser.getTok().getIdentifier() == ".req") {
5333 parseDirectiveReq(Name, NameLoc);
5334 // We always return 'error' for this, as we're done with this
5335 // statement and don't need to match the 'instruction."
5339 // Create the leading tokens for the mnemonic, split by '.' characters.
5340 size_t Start = 0, Next = Name.find('.');
5341 StringRef Mnemonic = Name.slice(Start, Next);
5343 // Split out the predication code and carry setting flag from the mnemonic.
5344 unsigned PredicationCode;
5345 unsigned ProcessorIMod;
5348 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5349 ProcessorIMod, ITMask);
5351 // In Thumb1, only the branch (B) instruction can be predicated.
5352 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5353 Parser.eatToEndOfStatement();
5354 return Error(NameLoc, "conditional execution not supported in Thumb1");
5357 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5359 // Handle the IT instruction ITMask. Convert it to a bitmask. This
5360 // is the mask as it will be for the IT encoding if the conditional
5361 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5362 // where the conditional bit0 is zero, the instruction post-processing
5363 // will adjust the mask accordingly.
5364 if (Mnemonic == "it") {
5365 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5366 if (ITMask.size() > 3) {
5367 Parser.eatToEndOfStatement();
5368 return Error(Loc, "too many conditions on IT instruction");
5371 for (unsigned i = ITMask.size(); i != 0; --i) {
5372 char pos = ITMask[i - 1];
5373 if (pos != 't' && pos != 'e') {
5374 Parser.eatToEndOfStatement();
5375 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5378 if (ITMask[i - 1] == 't')
5381 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5384 // FIXME: This is all a pretty gross hack. We should automatically handle
5385 // optional operands like this via tblgen.
5387 // Next, add the CCOut and ConditionCode operands, if needed.
5389 // For mnemonics which can ever incorporate a carry setting bit or predication
5390 // code, our matching model involves us always generating CCOut and
5391 // ConditionCode operands to match the mnemonic "as written" and then we let
5392 // the matcher deal with finding the right instruction or generating an
5393 // appropriate error.
5394 bool CanAcceptCarrySet, CanAcceptPredicationCode;
5395 getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
5397 // If we had a carry-set on an instruction that can't do that, issue an
5399 if (!CanAcceptCarrySet && CarrySetting) {
5400 Parser.eatToEndOfStatement();
5401 return Error(NameLoc, "instruction '" + Mnemonic +
5402 "' can not set flags, but 's' suffix specified");
5404 // If we had a predication code on an instruction that can't do that, issue an
5406 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5407 Parser.eatToEndOfStatement();
5408 return Error(NameLoc, "instruction '" + Mnemonic +
5409 "' is not predicable, but condition code specified");
5412 // Add the carry setting operand, if necessary.
5413 if (CanAcceptCarrySet) {
5414 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5415 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5419 // Add the predication code operand, if necessary.
5420 if (CanAcceptPredicationCode) {
5421 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5423 Operands.push_back(ARMOperand::CreateCondCode(
5424 ARMCC::CondCodes(PredicationCode), Loc));
5427 // Add the processor imod operand, if necessary.
5428 if (ProcessorIMod) {
5429 Operands.push_back(ARMOperand::CreateImm(
5430 MCConstantExpr::Create(ProcessorIMod, getContext()),
5434 // Add the remaining tokens in the mnemonic.
5435 while (Next != StringRef::npos) {
5437 Next = Name.find('.', Start + 1);
5438 StringRef ExtraToken = Name.slice(Start, Next);
5440 // Some NEON instructions have an optional datatype suffix that is
5441 // completely ignored. Check for that.
5442 if (isDataTypeToken(ExtraToken) &&
5443 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5446 // For for ARM mode generate an error if the .n qualifier is used.
5447 if (ExtraToken == ".n" && !isThumb()) {
5448 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5449 Parser.eatToEndOfStatement();
5450 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5454 // The .n qualifier is always discarded as that is what the tables
5455 // and matcher expect. In ARM mode the .w qualifier has no effect,
5456 // so discard it to avoid errors that can be caused by the matcher.
5457 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5458 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5459 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5463 // Read the remaining operands.
5464 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5465 // Read the first operand.
5466 if (parseOperand(Operands, Mnemonic)) {
5467 Parser.eatToEndOfStatement();
5471 while (getLexer().is(AsmToken::Comma)) {
5472 Parser.Lex(); // Eat the comma.
5474 // Parse and remember the operand.
5475 if (parseOperand(Operands, Mnemonic)) {
5476 Parser.eatToEndOfStatement();
5482 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5483 SMLoc Loc = getLexer().getLoc();
5484 Parser.eatToEndOfStatement();
5485 return Error(Loc, "unexpected token in argument list");
5488 Parser.Lex(); // Consume the EndOfStatement
5490 if (RequireVFPRegisterListCheck) {
5491 ARMOperand *Op = static_cast<ARMOperand*>(Operands.back());
5492 if (AcceptSinglePrecisionOnly && !Op->isSPRRegList())
5493 return Error(Op->getStartLoc(),
5494 "VFP/Neon single precision register expected");
5495 if (AcceptDoublePrecisionOnly && !Op->isDPRRegList())
5496 return Error(Op->getStartLoc(),
5497 "VFP/Neon double precision register expected");
5500 // Some instructions, mostly Thumb, have forms for the same mnemonic that
5501 // do and don't have a cc_out optional-def operand. With some spot-checks
5502 // of the operand list, we can figure out which variant we're trying to
5503 // parse and adjust accordingly before actually matching. We shouldn't ever
5504 // try to remove a cc_out operand that was explicitly set on the the
5505 // mnemonic, of course (CarrySetting == true). Reason number #317 the
5506 // table driven matcher doesn't fit well with the ARM instruction set.
5507 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5508 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5509 Operands.erase(Operands.begin() + 1);
5513 // Some instructions have the same mnemonic, but don't always
5514 // have a predicate. Distinguish them here and delete the
5515 // predicate if needed.
5516 if (shouldOmitPredicateOperand(Mnemonic, Operands)) {
5517 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5518 Operands.erase(Operands.begin() + 1);
5522 // ARM mode 'blx' need special handling, as the register operand version
5523 // is predicable, but the label operand version is not. So, we can't rely
5524 // on the Mnemonic based checking to correctly figure out when to put
5525 // a k_CondCode operand in the list. If we're trying to match the label
5526 // version, remove the k_CondCode operand here.
5527 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5528 static_cast<ARMOperand*>(Operands[2])->isImm()) {
5529 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5530 Operands.erase(Operands.begin() + 1);
5534 // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5535 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5536 // a single GPRPair reg operand is used in the .td file to replace the two
5537 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5538 // expressed as a GPRPair, so we have to manually merge them.
5539 // FIXME: We would really like to be able to tablegen'erate this.
5540 if (!isThumb() && Operands.size() > 4 &&
5541 (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
5542 Mnemonic == "stlexd")) {
5543 bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
5544 unsigned Idx = isLoad ? 2 : 3;
5545 ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]);
5546 ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]);
5548 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5549 // Adjust only if Op1 and Op2 are GPRs.
5550 if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) &&
5551 MRC.contains(Op2->getReg())) {
5552 unsigned Reg1 = Op1->getReg();
5553 unsigned Reg2 = Op2->getReg();
5554 unsigned Rt = MRI->getEncodingValue(Reg1);
5555 unsigned Rt2 = MRI->getEncodingValue(Reg2);
5557 // Rt2 must be Rt + 1 and Rt must be even.
5558 if (Rt + 1 != Rt2 || (Rt & 1)) {
5559 Error(Op2->getStartLoc(), isLoad ?
5560 "destination operands must be sequential" :
5561 "source operands must be sequential");
5564 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5565 &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5566 Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2);
5567 Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg(
5568 NewReg, Op1->getStartLoc(), Op2->getEndLoc()));
5574 // GNU Assembler extension (compatibility)
5575 if ((Mnemonic == "ldrd" || Mnemonic == "strd")) {
5576 ARMOperand *Op2 = static_cast<ARMOperand *>(Operands[2]);
5577 ARMOperand *Op3 = static_cast<ARMOperand *>(Operands[3]);
5579 assert(Op2->isReg() && "expected register argument");
5581 unsigned SuperReg = MRI->getMatchingSuperReg(
5582 Op2->getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID));
5584 assert(SuperReg && "expected register pair");
5586 unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1);
5588 Operands.insert(Operands.begin() + 3,
5589 ARMOperand::CreateReg(PairedReg,
5595 // FIXME: As said above, this is all a pretty gross hack. This instruction
5596 // does not fit with other "subs" and tblgen.
5597 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
5598 // so the Mnemonic is the original name "subs" and delete the predicate
5599 // operand so it will match the table entry.
5600 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
5601 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5602 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::PC &&
5603 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5604 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::LR &&
5605 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5606 ARMOperand *Op0 = static_cast<ARMOperand*>(Operands[0]);
5607 Operands.erase(Operands.begin());
5609 Operands.insert(Operands.begin(), ARMOperand::CreateToken(Name, NameLoc));
5611 ARMOperand *Op1 = static_cast<ARMOperand*>(Operands[1]);
5612 Operands.erase(Operands.begin() + 1);
5618 // Validate context-sensitive operand constraints.
5620 // return 'true' if register list contains non-low GPR registers,
5621 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5622 // 'containsReg' to true.
5623 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5624 unsigned HiReg, bool &containsReg) {
5625 containsReg = false;
5626 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5627 unsigned OpReg = Inst.getOperand(i).getReg();
5630 // Anything other than a low register isn't legal here.
5631 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5637 // Check if the specified regisgter is in the register list of the inst,
5638 // starting at the indicated operand number.
5639 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5640 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5641 unsigned OpReg = Inst.getOperand(i).getReg();
5648 // Return true if instruction has the interesting property of being
5649 // allowed in IT blocks, but not being predicable.
5650 static bool instIsBreakpoint(const MCInst &Inst) {
5651 return Inst.getOpcode() == ARM::tBKPT ||
5652 Inst.getOpcode() == ARM::BKPT ||
5653 Inst.getOpcode() == ARM::tHLT ||
5654 Inst.getOpcode() == ARM::HLT;
5658 // FIXME: We would really like to be able to tablegen'erate this.
5660 validateInstruction(MCInst &Inst,
5661 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5662 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
5663 SMLoc Loc = Operands[0]->getStartLoc();
5665 // Check the IT block state first.
5666 // NOTE: BKPT and HLT instructions have the interesting property of being
5667 // allowed in IT blocks, but not being predicable. They just always execute.
5668 if (inITBlock() && !instIsBreakpoint(Inst)) {
5670 if (ITState.FirstCond)
5671 ITState.FirstCond = false;
5673 Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5674 // The instruction must be predicable.
5675 if (!MCID.isPredicable())
5676 return Error(Loc, "instructions in IT block must be predicable");
5677 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5678 unsigned ITCond = Bit ? ITState.Cond :
5679 ARMCC::getOppositeCondition(ITState.Cond);
5680 if (Cond != ITCond) {
5681 // Find the condition code Operand to get its SMLoc information.
5683 for (unsigned I = 1; I < Operands.size(); ++I)
5684 if (static_cast<ARMOperand*>(Operands[I])->isCondCode())
5685 CondLoc = Operands[I]->getStartLoc();
5686 return Error(CondLoc, "incorrect condition in IT block; got '" +
5687 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5688 "', but expected '" +
5689 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5691 // Check for non-'al' condition codes outside of the IT block.
5692 } else if (isThumbTwo() && MCID.isPredicable() &&
5693 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5694 ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
5695 Inst.getOpcode() != ARM::t2Bcc)
5696 return Error(Loc, "predicated instructions must be in IT block");
5698 const unsigned Opcode = Inst.getOpcode();
5702 case ARM::LDRD_POST: {
5703 const unsigned RtReg = Inst.getOperand(0).getReg();
5706 if (RtReg == ARM::LR)
5707 return Error(Operands[3]->getStartLoc(),
5710 const unsigned Rt = MRI->getEncodingValue(RtReg);
5711 // Rt must be even-numbered.
5713 return Error(Operands[3]->getStartLoc(),
5714 "Rt must be even-numbered");
5716 // Rt2 must be Rt + 1.
5717 const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5719 return Error(Operands[3]->getStartLoc(),
5720 "destination operands must be sequential");
5722 if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) {
5723 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
5724 // For addressing modes with writeback, the base register needs to be
5725 // different from the destination registers.
5726 if (Rn == Rt || Rn == Rt2)
5727 return Error(Operands[3]->getStartLoc(),
5728 "base register needs to be different from destination "
5735 case ARM::t2LDRD_PRE:
5736 case ARM::t2LDRD_POST: {
5737 // Rt2 must be different from Rt.
5738 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5739 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5741 return Error(Operands[3]->getStartLoc(),
5742 "destination operands can't be identical");
5746 // Rt2 must be Rt + 1.
5747 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5748 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5750 return Error(Operands[3]->getStartLoc(),
5751 "source operands must be sequential");
5755 case ARM::STRD_POST: {
5756 // Rt2 must be Rt + 1.
5757 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5758 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5760 return Error(Operands[3]->getStartLoc(),
5761 "source operands must be sequential");
5766 // Width must be in range [1, 32-lsb].
5767 unsigned LSB = Inst.getOperand(2).getImm();
5768 unsigned Widthm1 = Inst.getOperand(3).getImm();
5769 if (Widthm1 >= 32 - LSB)
5770 return Error(Operands[5]->getStartLoc(),
5771 "bitfield width must be in range [1,32-lsb]");
5774 // Notionally handles ARM::tLDMIA_UPD too.
5776 // If we're parsing Thumb2, the .w variant is available and handles
5777 // most cases that are normally illegal for a Thumb1 LDM instruction.
5778 // We'll make the transformation in processInstruction() if necessary.
5780 // Thumb LDM instructions are writeback iff the base register is not
5781 // in the register list.
5782 unsigned Rn = Inst.getOperand(0).getReg();
5783 bool HasWritebackToken =
5784 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5785 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5786 bool ListContainsBase;
5787 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
5788 return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
5789 "registers must be in range r0-r7");
5790 // If we should have writeback, then there should be a '!' token.
5791 if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
5792 return Error(Operands[2]->getStartLoc(),
5793 "writeback operator '!' expected");
5794 // If we should not have writeback, there must not be a '!'. This is
5795 // true even for the 32-bit wide encodings.
5796 if (ListContainsBase && HasWritebackToken)
5797 return Error(Operands[3]->getStartLoc(),
5798 "writeback operator '!' not allowed when base register "
5799 "in register list");
5803 case ARM::LDMIA_UPD:
5804 case ARM::LDMDB_UPD:
5805 case ARM::LDMIB_UPD:
5806 case ARM::LDMDA_UPD:
5807 // ARM variants loading and updating the same register are only officially
5808 // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
5812 case ARM::t2LDMIA_UPD:
5813 case ARM::t2LDMDB_UPD:
5814 case ARM::t2STMIA_UPD:
5815 case ARM::t2STMDB_UPD: {
5816 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5817 return Error(Operands.back()->getStartLoc(),
5818 "writeback register not allowed in register list");
5821 case ARM::sysLDMIA_UPD:
5822 case ARM::sysLDMDA_UPD:
5823 case ARM::sysLDMDB_UPD:
5824 case ARM::sysLDMIB_UPD:
5825 if (!listContainsReg(Inst, 3, ARM::PC))
5826 return Error(Operands[4]->getStartLoc(),
5827 "writeback register only allowed on system LDM "
5828 "if PC in register-list");
5830 case ARM::sysSTMIA_UPD:
5831 case ARM::sysSTMDA_UPD:
5832 case ARM::sysSTMDB_UPD:
5833 case ARM::sysSTMIB_UPD:
5834 return Error(Operands[2]->getStartLoc(),
5835 "system STM cannot have writeback register");
5837 // The second source operand must be the same register as the destination
5840 // In this case, we must directly check the parsed operands because the
5841 // cvtThumbMultiply() function is written in such a way that it guarantees
5842 // this first statement is always true for the new Inst. Essentially, the
5843 // destination is unconditionally copied into the second source operand
5844 // without checking to see if it matches what we actually parsed.
5845 if (Operands.size() == 6 &&
5846 (((ARMOperand*)Operands[3])->getReg() !=
5847 ((ARMOperand*)Operands[5])->getReg()) &&
5848 (((ARMOperand*)Operands[3])->getReg() !=
5849 ((ARMOperand*)Operands[4])->getReg())) {
5850 return Error(Operands[3]->getStartLoc(),
5851 "destination register must match source register");
5855 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5856 // so only issue a diagnostic for thumb1. The instructions will be
5857 // switched to the t2 encodings in processInstruction() if necessary.
5859 bool ListContainsBase;
5860 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
5862 return Error(Operands[2]->getStartLoc(),
5863 "registers must be in range r0-r7 or pc");
5867 bool ListContainsBase;
5868 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
5870 return Error(Operands[2]->getStartLoc(),
5871 "registers must be in range r0-r7 or lr");
5874 case ARM::tSTMIA_UPD: {
5875 bool ListContainsBase, InvalidLowList;
5876 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
5877 0, ListContainsBase);
5878 if (InvalidLowList && !isThumbTwo())
5879 return Error(Operands[4]->getStartLoc(),
5880 "registers must be in range r0-r7");
5882 // This would be converted to a 32-bit stm, but that's not valid if the
5883 // writeback register is in the list.
5884 if (InvalidLowList && ListContainsBase)
5885 return Error(Operands[4]->getStartLoc(),
5886 "writeback operator '!' not allowed when base register "
5887 "in register list");
5890 case ARM::tADDrSP: {
5891 // If the non-SP source operand and the destination operand are not the
5892 // same, we need thumb2 (for the wide encoding), or we have an error.
5893 if (!isThumbTwo() &&
5894 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5895 return Error(Operands[4]->getStartLoc(),
5896 "source register must be the same as destination");
5900 // Final range checking for Thumb unconditional branch instructions.
5902 if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<11, 1>())
5903 return Error(Operands[2]->getStartLoc(), "branch target out of range");
5906 int op = (Operands[2]->isImm()) ? 2 : 3;
5907 if (!(static_cast<ARMOperand*>(Operands[op]))->isSignedOffset<24, 1>())
5908 return Error(Operands[op]->getStartLoc(), "branch target out of range");
5911 // Final range checking for Thumb conditional branch instructions.
5913 if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<8, 1>())
5914 return Error(Operands[2]->getStartLoc(), "branch target out of range");
5917 int Op = (Operands[2]->isImm()) ? 2 : 3;
5918 if (!(static_cast<ARMOperand*>(Operands[Op]))->isSignedOffset<20, 1>())
5919 return Error(Operands[Op]->getStartLoc(), "branch target out of range");
5924 case ARM::t2MOVTi16:
5926 // We want to avoid misleadingly allowing something like "mov r0, <symbol>"
5927 // especially when we turn it into a movw and the expression <symbol> does
5928 // not have a :lower16: or :upper16 as part of the expression. We don't
5929 // want the behavior of silently truncating, which can be unexpected and
5930 // lead to bugs that are difficult to find since this is an easy mistake
5932 int i = (Operands[3]->isImm()) ? 3 : 4;
5933 ARMOperand *Op = static_cast<ARMOperand*>(Operands[i]);
5934 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5936 const MCExpr *E = dyn_cast<MCExpr>(Op->getImm());
5938 const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E);
5939 if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
5940 ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16)) {
5941 return Error(Op->getStartLoc(),
5942 "immediate expression for mov requires :lower16: or :upper16");
5951 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5953 default: llvm_unreachable("unexpected opcode!");
5955 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5956 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5957 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5958 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5959 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5960 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5961 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
5962 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5963 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5966 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5967 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5968 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5969 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5970 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5972 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5973 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5974 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5975 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5976 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5978 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
5979 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5980 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5981 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5982 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5985 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5986 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5987 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5988 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5989 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5990 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5991 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5992 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5993 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5994 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5995 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
5996 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5997 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5998 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5999 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
6002 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
6003 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6004 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6005 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
6006 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6007 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6008 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
6009 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6010 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6011 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
6012 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6013 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6014 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
6015 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
6016 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
6017 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
6018 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
6019 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
6022 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
6023 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6024 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6025 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
6026 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6027 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
6028 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6029 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6030 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
6031 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6032 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
6033 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
6034 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
6035 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
6036 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
6039 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
6040 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6041 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6042 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
6043 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6044 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6045 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
6046 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6047 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6048 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
6049 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6050 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6051 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
6052 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
6053 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
6054 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
6055 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
6056 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
6060 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
6062 default: llvm_unreachable("unexpected opcode!");
6064 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
6065 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6066 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6067 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
6068 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6069 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6070 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
6071 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
6072 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
6075 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
6076 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6077 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6078 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
6079 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6080 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
6081 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6082 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6083 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
6084 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6085 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
6086 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
6087 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
6088 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
6089 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
6092 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
6093 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6094 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6095 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
6096 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6097 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6098 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
6099 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6100 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6101 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
6102 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6103 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6104 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
6105 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
6106 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
6107 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
6108 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
6109 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
6112 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
6113 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6114 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6115 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
6116 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6117 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
6118 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6119 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6120 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
6121 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6122 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
6123 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
6124 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
6125 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
6126 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
6129 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
6130 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6131 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6132 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
6133 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6134 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6135 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
6136 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6137 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6138 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
6139 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6140 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6141 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
6142 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
6143 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
6144 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
6145 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
6146 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
6149 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
6150 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6151 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6152 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6153 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6154 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
6155 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6156 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6157 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6158 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6159 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
6160 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
6161 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
6162 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
6163 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
6166 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
6167 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6168 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6169 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
6170 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
6171 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6172 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
6173 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6174 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6175 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
6176 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
6177 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6178 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
6179 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
6180 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
6181 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
6182 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
6183 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
6186 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
6187 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6188 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6189 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
6190 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6191 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6192 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
6193 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6194 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6195 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
6196 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6197 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6198 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
6199 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
6200 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
6201 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
6202 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
6203 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
6208 processInstruction(MCInst &Inst,
6209 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
6210 switch (Inst.getOpcode()) {
6211 // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
6212 case ARM::LDRT_POST:
6213 case ARM::LDRBT_POST: {
6214 const unsigned Opcode =
6215 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
6216 : ARM::LDRBT_POST_IMM;
6218 TmpInst.setOpcode(Opcode);
6219 TmpInst.addOperand(Inst.getOperand(0));
6220 TmpInst.addOperand(Inst.getOperand(1));
6221 TmpInst.addOperand(Inst.getOperand(1));
6222 TmpInst.addOperand(MCOperand::CreateReg(0));
6223 TmpInst.addOperand(MCOperand::CreateImm(0));
6224 TmpInst.addOperand(Inst.getOperand(2));
6225 TmpInst.addOperand(Inst.getOperand(3));
6229 // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
6230 case ARM::STRT_POST:
6231 case ARM::STRBT_POST: {
6232 const unsigned Opcode =
6233 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
6234 : ARM::STRBT_POST_IMM;
6236 TmpInst.setOpcode(Opcode);
6237 TmpInst.addOperand(Inst.getOperand(1));
6238 TmpInst.addOperand(Inst.getOperand(0));
6239 TmpInst.addOperand(Inst.getOperand(1));
6240 TmpInst.addOperand(MCOperand::CreateReg(0));
6241 TmpInst.addOperand(MCOperand::CreateImm(0));
6242 TmpInst.addOperand(Inst.getOperand(2));
6243 TmpInst.addOperand(Inst.getOperand(3));
6247 // Alias for alternate form of 'ADR Rd, #imm' instruction.
6249 if (Inst.getOperand(1).getReg() != ARM::PC ||
6250 Inst.getOperand(5).getReg() != 0)
6253 TmpInst.setOpcode(ARM::ADR);
6254 TmpInst.addOperand(Inst.getOperand(0));
6255 TmpInst.addOperand(Inst.getOperand(2));
6256 TmpInst.addOperand(Inst.getOperand(3));
6257 TmpInst.addOperand(Inst.getOperand(4));
6261 // Aliases for alternate PC+imm syntax of LDR instructions.
6262 case ARM::t2LDRpcrel:
6263 // Select the narrow version if the immediate will fit.
6264 if (Inst.getOperand(1).getImm() > 0 &&
6265 Inst.getOperand(1).getImm() <= 0xff &&
6266 !(static_cast<ARMOperand*>(Operands[2])->isToken() &&
6267 static_cast<ARMOperand*>(Operands[2])->getToken() == ".w"))
6268 Inst.setOpcode(ARM::tLDRpci);
6270 Inst.setOpcode(ARM::t2LDRpci);
6272 case ARM::t2LDRBpcrel:
6273 Inst.setOpcode(ARM::t2LDRBpci);
6275 case ARM::t2LDRHpcrel:
6276 Inst.setOpcode(ARM::t2LDRHpci);
6278 case ARM::t2LDRSBpcrel:
6279 Inst.setOpcode(ARM::t2LDRSBpci);
6281 case ARM::t2LDRSHpcrel:
6282 Inst.setOpcode(ARM::t2LDRSHpci);
6284 // Handle NEON VST complex aliases.
6285 case ARM::VST1LNdWB_register_Asm_8:
6286 case ARM::VST1LNdWB_register_Asm_16:
6287 case ARM::VST1LNdWB_register_Asm_32: {
6289 // Shuffle the operands around so the lane index operand is in the
6292 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6293 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6294 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6295 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6296 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6297 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6298 TmpInst.addOperand(Inst.getOperand(1)); // lane
6299 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6300 TmpInst.addOperand(Inst.getOperand(6));
6305 case ARM::VST2LNdWB_register_Asm_8:
6306 case ARM::VST2LNdWB_register_Asm_16:
6307 case ARM::VST2LNdWB_register_Asm_32:
6308 case ARM::VST2LNqWB_register_Asm_16:
6309 case ARM::VST2LNqWB_register_Asm_32: {
6311 // Shuffle the operands around so the lane index operand is in the
6314 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6315 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6316 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6317 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6318 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6319 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6320 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6322 TmpInst.addOperand(Inst.getOperand(1)); // lane
6323 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6324 TmpInst.addOperand(Inst.getOperand(6));
6329 case ARM::VST3LNdWB_register_Asm_8:
6330 case ARM::VST3LNdWB_register_Asm_16:
6331 case ARM::VST3LNdWB_register_Asm_32:
6332 case ARM::VST3LNqWB_register_Asm_16:
6333 case ARM::VST3LNqWB_register_Asm_32: {
6335 // Shuffle the operands around so the lane index operand is in the
6338 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6339 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6340 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6341 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6342 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6343 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6344 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6346 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6348 TmpInst.addOperand(Inst.getOperand(1)); // lane
6349 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6350 TmpInst.addOperand(Inst.getOperand(6));
6355 case ARM::VST4LNdWB_register_Asm_8:
6356 case ARM::VST4LNdWB_register_Asm_16:
6357 case ARM::VST4LNdWB_register_Asm_32:
6358 case ARM::VST4LNqWB_register_Asm_16:
6359 case ARM::VST4LNqWB_register_Asm_32: {
6361 // Shuffle the operands around so the lane index operand is in the
6364 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6365 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6366 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6367 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6368 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6369 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6370 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6372 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6374 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6376 TmpInst.addOperand(Inst.getOperand(1)); // lane
6377 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6378 TmpInst.addOperand(Inst.getOperand(6));
6383 case ARM::VST1LNdWB_fixed_Asm_8:
6384 case ARM::VST1LNdWB_fixed_Asm_16:
6385 case ARM::VST1LNdWB_fixed_Asm_32: {
6387 // Shuffle the operands around so the lane index operand is in the
6390 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6391 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6392 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6393 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6394 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6395 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6396 TmpInst.addOperand(Inst.getOperand(1)); // lane
6397 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6398 TmpInst.addOperand(Inst.getOperand(5));
6403 case ARM::VST2LNdWB_fixed_Asm_8:
6404 case ARM::VST2LNdWB_fixed_Asm_16:
6405 case ARM::VST2LNdWB_fixed_Asm_32:
6406 case ARM::VST2LNqWB_fixed_Asm_16:
6407 case ARM::VST2LNqWB_fixed_Asm_32: {
6409 // Shuffle the operands around so the lane index operand is in the
6412 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6413 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6414 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6415 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6416 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6417 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6418 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6420 TmpInst.addOperand(Inst.getOperand(1)); // lane
6421 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6422 TmpInst.addOperand(Inst.getOperand(5));
6427 case ARM::VST3LNdWB_fixed_Asm_8:
6428 case ARM::VST3LNdWB_fixed_Asm_16:
6429 case ARM::VST3LNdWB_fixed_Asm_32:
6430 case ARM::VST3LNqWB_fixed_Asm_16:
6431 case ARM::VST3LNqWB_fixed_Asm_32: {
6433 // Shuffle the operands around so the lane index operand is in the
6436 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6437 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6438 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6439 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6440 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6441 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6442 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6444 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6446 TmpInst.addOperand(Inst.getOperand(1)); // lane
6447 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6448 TmpInst.addOperand(Inst.getOperand(5));
6453 case ARM::VST4LNdWB_fixed_Asm_8:
6454 case ARM::VST4LNdWB_fixed_Asm_16:
6455 case ARM::VST4LNdWB_fixed_Asm_32:
6456 case ARM::VST4LNqWB_fixed_Asm_16:
6457 case ARM::VST4LNqWB_fixed_Asm_32: {
6459 // Shuffle the operands around so the lane index operand is in the
6462 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6463 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6464 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6465 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6466 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6467 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6468 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6470 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6472 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6474 TmpInst.addOperand(Inst.getOperand(1)); // lane
6475 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6476 TmpInst.addOperand(Inst.getOperand(5));
6481 case ARM::VST1LNdAsm_8:
6482 case ARM::VST1LNdAsm_16:
6483 case ARM::VST1LNdAsm_32: {
6485 // Shuffle the operands around so the lane index operand is in the
6488 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6489 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6490 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6491 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6492 TmpInst.addOperand(Inst.getOperand(1)); // lane
6493 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6494 TmpInst.addOperand(Inst.getOperand(5));
6499 case ARM::VST2LNdAsm_8:
6500 case ARM::VST2LNdAsm_16:
6501 case ARM::VST2LNdAsm_32:
6502 case ARM::VST2LNqAsm_16:
6503 case ARM::VST2LNqAsm_32: {
6505 // Shuffle the operands around so the lane index operand is in the
6508 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6509 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6510 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6511 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6512 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6514 TmpInst.addOperand(Inst.getOperand(1)); // lane
6515 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6516 TmpInst.addOperand(Inst.getOperand(5));
6521 case ARM::VST3LNdAsm_8:
6522 case ARM::VST3LNdAsm_16:
6523 case ARM::VST3LNdAsm_32:
6524 case ARM::VST3LNqAsm_16:
6525 case ARM::VST3LNqAsm_32: {
6527 // Shuffle the operands around so the lane index operand is in the
6530 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6531 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6532 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6533 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6534 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6536 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6538 TmpInst.addOperand(Inst.getOperand(1)); // lane
6539 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6540 TmpInst.addOperand(Inst.getOperand(5));
6545 case ARM::VST4LNdAsm_8:
6546 case ARM::VST4LNdAsm_16:
6547 case ARM::VST4LNdAsm_32:
6548 case ARM::VST4LNqAsm_16:
6549 case ARM::VST4LNqAsm_32: {
6551 // Shuffle the operands around so the lane index operand is in the
6554 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6555 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6556 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6557 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6558 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6560 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6562 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6564 TmpInst.addOperand(Inst.getOperand(1)); // lane
6565 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6566 TmpInst.addOperand(Inst.getOperand(5));
6571 // Handle NEON VLD complex aliases.
6572 case ARM::VLD1LNdWB_register_Asm_8:
6573 case ARM::VLD1LNdWB_register_Asm_16:
6574 case ARM::VLD1LNdWB_register_Asm_32: {
6576 // Shuffle the operands around so the lane index operand is in the
6579 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6580 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6581 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6582 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6583 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6584 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6585 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6586 TmpInst.addOperand(Inst.getOperand(1)); // lane
6587 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6588 TmpInst.addOperand(Inst.getOperand(6));
6593 case ARM::VLD2LNdWB_register_Asm_8:
6594 case ARM::VLD2LNdWB_register_Asm_16:
6595 case ARM::VLD2LNdWB_register_Asm_32:
6596 case ARM::VLD2LNqWB_register_Asm_16:
6597 case ARM::VLD2LNqWB_register_Asm_32: {
6599 // Shuffle the operands around so the lane index operand is in the
6602 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6603 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6604 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6606 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6607 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6608 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6609 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6610 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6611 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6613 TmpInst.addOperand(Inst.getOperand(1)); // lane
6614 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6615 TmpInst.addOperand(Inst.getOperand(6));
6620 case ARM::VLD3LNdWB_register_Asm_8:
6621 case ARM::VLD3LNdWB_register_Asm_16:
6622 case ARM::VLD3LNdWB_register_Asm_32:
6623 case ARM::VLD3LNqWB_register_Asm_16:
6624 case ARM::VLD3LNqWB_register_Asm_32: {
6626 // Shuffle the operands around so the lane index operand is in the
6629 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6630 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6631 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6633 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6635 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6636 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6637 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6638 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6639 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6640 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6642 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6644 TmpInst.addOperand(Inst.getOperand(1)); // lane
6645 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6646 TmpInst.addOperand(Inst.getOperand(6));
6651 case ARM::VLD4LNdWB_register_Asm_8:
6652 case ARM::VLD4LNdWB_register_Asm_16:
6653 case ARM::VLD4LNdWB_register_Asm_32:
6654 case ARM::VLD4LNqWB_register_Asm_16:
6655 case ARM::VLD4LNqWB_register_Asm_32: {
6657 // Shuffle the operands around so the lane index operand is in the
6660 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6661 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6662 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6664 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6666 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6668 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6669 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6670 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6671 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6672 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6673 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6675 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6677 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6679 TmpInst.addOperand(Inst.getOperand(1)); // lane
6680 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6681 TmpInst.addOperand(Inst.getOperand(6));
6686 case ARM::VLD1LNdWB_fixed_Asm_8:
6687 case ARM::VLD1LNdWB_fixed_Asm_16:
6688 case ARM::VLD1LNdWB_fixed_Asm_32: {
6690 // Shuffle the operands around so the lane index operand is in the
6693 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6694 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6695 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6696 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6697 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6698 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6699 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6700 TmpInst.addOperand(Inst.getOperand(1)); // lane
6701 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6702 TmpInst.addOperand(Inst.getOperand(5));
6707 case ARM::VLD2LNdWB_fixed_Asm_8:
6708 case ARM::VLD2LNdWB_fixed_Asm_16:
6709 case ARM::VLD2LNdWB_fixed_Asm_32:
6710 case ARM::VLD2LNqWB_fixed_Asm_16:
6711 case ARM::VLD2LNqWB_fixed_Asm_32: {
6713 // Shuffle the operands around so the lane index operand is in the
6716 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6717 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6718 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6720 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6721 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6722 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6723 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6724 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6725 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6727 TmpInst.addOperand(Inst.getOperand(1)); // lane
6728 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6729 TmpInst.addOperand(Inst.getOperand(5));
6734 case ARM::VLD3LNdWB_fixed_Asm_8:
6735 case ARM::VLD3LNdWB_fixed_Asm_16:
6736 case ARM::VLD3LNdWB_fixed_Asm_32:
6737 case ARM::VLD3LNqWB_fixed_Asm_16:
6738 case ARM::VLD3LNqWB_fixed_Asm_32: {
6740 // Shuffle the operands around so the lane index operand is in the
6743 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6744 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6745 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6747 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6749 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6750 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6751 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6752 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6753 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6754 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6756 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6758 TmpInst.addOperand(Inst.getOperand(1)); // lane
6759 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6760 TmpInst.addOperand(Inst.getOperand(5));
6765 case ARM::VLD4LNdWB_fixed_Asm_8:
6766 case ARM::VLD4LNdWB_fixed_Asm_16:
6767 case ARM::VLD4LNdWB_fixed_Asm_32:
6768 case ARM::VLD4LNqWB_fixed_Asm_16:
6769 case ARM::VLD4LNqWB_fixed_Asm_32: {
6771 // Shuffle the operands around so the lane index operand is in the
6774 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6775 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6776 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6778 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6780 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6782 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6783 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6784 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6785 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6786 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6787 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6789 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6791 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6793 TmpInst.addOperand(Inst.getOperand(1)); // lane
6794 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6795 TmpInst.addOperand(Inst.getOperand(5));
6800 case ARM::VLD1LNdAsm_8:
6801 case ARM::VLD1LNdAsm_16:
6802 case ARM::VLD1LNdAsm_32: {
6804 // Shuffle the operands around so the lane index operand is in the
6807 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6808 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6809 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6810 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6811 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6812 TmpInst.addOperand(Inst.getOperand(1)); // lane
6813 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6814 TmpInst.addOperand(Inst.getOperand(5));
6819 case ARM::VLD2LNdAsm_8:
6820 case ARM::VLD2LNdAsm_16:
6821 case ARM::VLD2LNdAsm_32:
6822 case ARM::VLD2LNqAsm_16:
6823 case ARM::VLD2LNqAsm_32: {
6825 // Shuffle the operands around so the lane index operand is in the
6828 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6829 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6830 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6832 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6833 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6834 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6835 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6837 TmpInst.addOperand(Inst.getOperand(1)); // lane
6838 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6839 TmpInst.addOperand(Inst.getOperand(5));
6844 case ARM::VLD3LNdAsm_8:
6845 case ARM::VLD3LNdAsm_16:
6846 case ARM::VLD3LNdAsm_32:
6847 case ARM::VLD3LNqAsm_16:
6848 case ARM::VLD3LNqAsm_32: {
6850 // Shuffle the operands around so the lane index operand is in the
6853 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6854 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6855 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6857 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6859 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6860 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6861 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6862 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6864 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6866 TmpInst.addOperand(Inst.getOperand(1)); // lane
6867 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6868 TmpInst.addOperand(Inst.getOperand(5));
6873 case ARM::VLD4LNdAsm_8:
6874 case ARM::VLD4LNdAsm_16:
6875 case ARM::VLD4LNdAsm_32:
6876 case ARM::VLD4LNqAsm_16:
6877 case ARM::VLD4LNqAsm_32: {
6879 // Shuffle the operands around so the lane index operand is in the
6882 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6883 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6884 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6886 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6888 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6890 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6891 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6892 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6893 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6895 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6897 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6899 TmpInst.addOperand(Inst.getOperand(1)); // lane
6900 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6901 TmpInst.addOperand(Inst.getOperand(5));
6906 // VLD3DUP single 3-element structure to all lanes instructions.
6907 case ARM::VLD3DUPdAsm_8:
6908 case ARM::VLD3DUPdAsm_16:
6909 case ARM::VLD3DUPdAsm_32:
6910 case ARM::VLD3DUPqAsm_8:
6911 case ARM::VLD3DUPqAsm_16:
6912 case ARM::VLD3DUPqAsm_32: {
6915 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6916 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6917 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6919 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6921 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6922 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6923 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6924 TmpInst.addOperand(Inst.getOperand(4));
6929 case ARM::VLD3DUPdWB_fixed_Asm_8:
6930 case ARM::VLD3DUPdWB_fixed_Asm_16:
6931 case ARM::VLD3DUPdWB_fixed_Asm_32:
6932 case ARM::VLD3DUPqWB_fixed_Asm_8:
6933 case ARM::VLD3DUPqWB_fixed_Asm_16:
6934 case ARM::VLD3DUPqWB_fixed_Asm_32: {
6937 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6938 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6939 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6941 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6943 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6944 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6945 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6946 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6947 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6948 TmpInst.addOperand(Inst.getOperand(4));
6953 case ARM::VLD3DUPdWB_register_Asm_8:
6954 case ARM::VLD3DUPdWB_register_Asm_16:
6955 case ARM::VLD3DUPdWB_register_Asm_32:
6956 case ARM::VLD3DUPqWB_register_Asm_8:
6957 case ARM::VLD3DUPqWB_register_Asm_16:
6958 case ARM::VLD3DUPqWB_register_Asm_32: {
6961 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6962 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6963 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6965 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6967 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6968 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6969 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6970 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6971 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6972 TmpInst.addOperand(Inst.getOperand(5));
6977 // VLD3 multiple 3-element structure instructions.
6978 case ARM::VLD3dAsm_8:
6979 case ARM::VLD3dAsm_16:
6980 case ARM::VLD3dAsm_32:
6981 case ARM::VLD3qAsm_8:
6982 case ARM::VLD3qAsm_16:
6983 case ARM::VLD3qAsm_32: {
6986 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6987 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6988 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6990 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6992 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6993 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6994 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6995 TmpInst.addOperand(Inst.getOperand(4));
7000 case ARM::VLD3dWB_fixed_Asm_8:
7001 case ARM::VLD3dWB_fixed_Asm_16:
7002 case ARM::VLD3dWB_fixed_Asm_32:
7003 case ARM::VLD3qWB_fixed_Asm_8:
7004 case ARM::VLD3qWB_fixed_Asm_16:
7005 case ARM::VLD3qWB_fixed_Asm_32: {
7008 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7009 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7010 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7012 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7014 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7015 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7016 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7017 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7018 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7019 TmpInst.addOperand(Inst.getOperand(4));
7024 case ARM::VLD3dWB_register_Asm_8:
7025 case ARM::VLD3dWB_register_Asm_16:
7026 case ARM::VLD3dWB_register_Asm_32:
7027 case ARM::VLD3qWB_register_Asm_8:
7028 case ARM::VLD3qWB_register_Asm_16:
7029 case ARM::VLD3qWB_register_Asm_32: {
7032 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7033 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7034 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7036 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7038 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7039 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7040 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7041 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7042 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7043 TmpInst.addOperand(Inst.getOperand(5));
7048 // VLD4DUP single 3-element structure to all lanes instructions.
7049 case ARM::VLD4DUPdAsm_8:
7050 case ARM::VLD4DUPdAsm_16:
7051 case ARM::VLD4DUPdAsm_32:
7052 case ARM::VLD4DUPqAsm_8:
7053 case ARM::VLD4DUPqAsm_16:
7054 case ARM::VLD4DUPqAsm_32: {
7057 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7058 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7059 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7061 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7063 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7065 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7066 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7067 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7068 TmpInst.addOperand(Inst.getOperand(4));
7073 case ARM::VLD4DUPdWB_fixed_Asm_8:
7074 case ARM::VLD4DUPdWB_fixed_Asm_16:
7075 case ARM::VLD4DUPdWB_fixed_Asm_32:
7076 case ARM::VLD4DUPqWB_fixed_Asm_8:
7077 case ARM::VLD4DUPqWB_fixed_Asm_16:
7078 case ARM::VLD4DUPqWB_fixed_Asm_32: {
7081 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7082 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7083 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7085 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7087 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7089 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7090 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7091 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7092 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7093 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7094 TmpInst.addOperand(Inst.getOperand(4));
7099 case ARM::VLD4DUPdWB_register_Asm_8:
7100 case ARM::VLD4DUPdWB_register_Asm_16:
7101 case ARM::VLD4DUPdWB_register_Asm_32:
7102 case ARM::VLD4DUPqWB_register_Asm_8:
7103 case ARM::VLD4DUPqWB_register_Asm_16:
7104 case ARM::VLD4DUPqWB_register_Asm_32: {
7107 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7108 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7109 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7111 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7113 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7115 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7116 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7117 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7118 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7119 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7120 TmpInst.addOperand(Inst.getOperand(5));
7125 // VLD4 multiple 4-element structure instructions.
7126 case ARM::VLD4dAsm_8:
7127 case ARM::VLD4dAsm_16:
7128 case ARM::VLD4dAsm_32:
7129 case ARM::VLD4qAsm_8:
7130 case ARM::VLD4qAsm_16:
7131 case ARM::VLD4qAsm_32: {
7134 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7135 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7136 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7138 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7140 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7142 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7143 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7144 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7145 TmpInst.addOperand(Inst.getOperand(4));
7150 case ARM::VLD4dWB_fixed_Asm_8:
7151 case ARM::VLD4dWB_fixed_Asm_16:
7152 case ARM::VLD4dWB_fixed_Asm_32:
7153 case ARM::VLD4qWB_fixed_Asm_8:
7154 case ARM::VLD4qWB_fixed_Asm_16:
7155 case ARM::VLD4qWB_fixed_Asm_32: {
7158 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7159 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7160 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7162 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7164 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7166 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7167 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7168 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7169 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7170 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7171 TmpInst.addOperand(Inst.getOperand(4));
7176 case ARM::VLD4dWB_register_Asm_8:
7177 case ARM::VLD4dWB_register_Asm_16:
7178 case ARM::VLD4dWB_register_Asm_32:
7179 case ARM::VLD4qWB_register_Asm_8:
7180 case ARM::VLD4qWB_register_Asm_16:
7181 case ARM::VLD4qWB_register_Asm_32: {
7184 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7185 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7186 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7188 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7190 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7192 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7193 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7194 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7195 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7196 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7197 TmpInst.addOperand(Inst.getOperand(5));
7202 // VST3 multiple 3-element structure instructions.
7203 case ARM::VST3dAsm_8:
7204 case ARM::VST3dAsm_16:
7205 case ARM::VST3dAsm_32:
7206 case ARM::VST3qAsm_8:
7207 case ARM::VST3qAsm_16:
7208 case ARM::VST3qAsm_32: {
7211 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7212 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7213 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7214 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7215 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7217 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7219 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7220 TmpInst.addOperand(Inst.getOperand(4));
7225 case ARM::VST3dWB_fixed_Asm_8:
7226 case ARM::VST3dWB_fixed_Asm_16:
7227 case ARM::VST3dWB_fixed_Asm_32:
7228 case ARM::VST3qWB_fixed_Asm_8:
7229 case ARM::VST3qWB_fixed_Asm_16:
7230 case ARM::VST3qWB_fixed_Asm_32: {
7233 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7234 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7235 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7236 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7237 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7238 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7239 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7241 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7243 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7244 TmpInst.addOperand(Inst.getOperand(4));
7249 case ARM::VST3dWB_register_Asm_8:
7250 case ARM::VST3dWB_register_Asm_16:
7251 case ARM::VST3dWB_register_Asm_32:
7252 case ARM::VST3qWB_register_Asm_8:
7253 case ARM::VST3qWB_register_Asm_16:
7254 case ARM::VST3qWB_register_Asm_32: {
7257 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7258 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7259 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7260 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7261 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7262 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7263 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7265 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7267 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7268 TmpInst.addOperand(Inst.getOperand(5));
7273 // VST4 multiple 3-element structure instructions.
7274 case ARM::VST4dAsm_8:
7275 case ARM::VST4dAsm_16:
7276 case ARM::VST4dAsm_32:
7277 case ARM::VST4qAsm_8:
7278 case ARM::VST4qAsm_16:
7279 case ARM::VST4qAsm_32: {
7282 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7283 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7284 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7285 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7286 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7288 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7290 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7292 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7293 TmpInst.addOperand(Inst.getOperand(4));
7298 case ARM::VST4dWB_fixed_Asm_8:
7299 case ARM::VST4dWB_fixed_Asm_16:
7300 case ARM::VST4dWB_fixed_Asm_32:
7301 case ARM::VST4qWB_fixed_Asm_8:
7302 case ARM::VST4qWB_fixed_Asm_16:
7303 case ARM::VST4qWB_fixed_Asm_32: {
7306 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7307 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7308 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7309 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7310 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7311 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7312 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7314 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7316 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7318 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7319 TmpInst.addOperand(Inst.getOperand(4));
7324 case ARM::VST4dWB_register_Asm_8:
7325 case ARM::VST4dWB_register_Asm_16:
7326 case ARM::VST4dWB_register_Asm_32:
7327 case ARM::VST4qWB_register_Asm_8:
7328 case ARM::VST4qWB_register_Asm_16:
7329 case ARM::VST4qWB_register_Asm_32: {
7332 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7333 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7334 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7335 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7336 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7337 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7338 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7340 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7342 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7344 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7345 TmpInst.addOperand(Inst.getOperand(5));
7350 // Handle encoding choice for the shift-immediate instructions.
7353 case ARM::t2ASRri: {
7354 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7355 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7356 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
7357 !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
7358 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
7360 switch (Inst.getOpcode()) {
7361 default: llvm_unreachable("unexpected opcode");
7362 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
7363 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
7364 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
7366 // The Thumb1 operands aren't in the same order. Awesome, eh?
7368 TmpInst.setOpcode(NewOpc);
7369 TmpInst.addOperand(Inst.getOperand(0));
7370 TmpInst.addOperand(Inst.getOperand(5));
7371 TmpInst.addOperand(Inst.getOperand(1));
7372 TmpInst.addOperand(Inst.getOperand(2));
7373 TmpInst.addOperand(Inst.getOperand(3));
7374 TmpInst.addOperand(Inst.getOperand(4));
7381 // Handle the Thumb2 mode MOV complex aliases.
7383 case ARM::t2MOVSsr: {
7384 // Which instruction to expand to depends on the CCOut operand and
7385 // whether we're in an IT block if the register operands are low
7387 bool isNarrow = false;
7388 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7389 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7390 isARMLowRegister(Inst.getOperand(2).getReg()) &&
7391 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7392 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
7396 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
7397 default: llvm_unreachable("unexpected opcode!");
7398 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7399 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7400 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7401 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
7403 TmpInst.setOpcode(newOpc);
7404 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7406 TmpInst.addOperand(MCOperand::CreateReg(
7407 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7408 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7409 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7410 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7411 TmpInst.addOperand(Inst.getOperand(5));
7413 TmpInst.addOperand(MCOperand::CreateReg(
7414 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7419 case ARM::t2MOVSsi: {
7420 // Which instruction to expand to depends on the CCOut operand and
7421 // whether we're in an IT block if the register operands are low
7423 bool isNarrow = false;
7424 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7425 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7426 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
7430 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
7431 default: llvm_unreachable("unexpected opcode!");
7432 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7433 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7434 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7435 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7436 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7438 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
7439 if (Amount == 32) Amount = 0;
7440 TmpInst.setOpcode(newOpc);
7441 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7443 TmpInst.addOperand(MCOperand::CreateReg(
7444 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7445 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7446 if (newOpc != ARM::t2RRX)
7447 TmpInst.addOperand(MCOperand::CreateImm(Amount));
7448 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7449 TmpInst.addOperand(Inst.getOperand(4));
7451 TmpInst.addOperand(MCOperand::CreateReg(
7452 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7456 // Handle the ARM mode MOV complex aliases.
7461 ARM_AM::ShiftOpc ShiftTy;
7462 switch(Inst.getOpcode()) {
7463 default: llvm_unreachable("unexpected opcode!");
7464 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
7465 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
7466 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
7467 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
7469 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
7471 TmpInst.setOpcode(ARM::MOVsr);
7472 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7473 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7474 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7475 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7476 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7477 TmpInst.addOperand(Inst.getOperand(4));
7478 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7486 ARM_AM::ShiftOpc ShiftTy;
7487 switch(Inst.getOpcode()) {
7488 default: llvm_unreachable("unexpected opcode!");
7489 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
7490 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
7491 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7492 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
7494 // A shift by zero is a plain MOVr, not a MOVsi.
7495 unsigned Amt = Inst.getOperand(2).getImm();
7496 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
7497 // A shift by 32 should be encoded as 0 when permitted
7498 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
7500 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
7502 TmpInst.setOpcode(Opc);
7503 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7504 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7505 if (Opc == ARM::MOVsi)
7506 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7507 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7508 TmpInst.addOperand(Inst.getOperand(4));
7509 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7514 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
7516 TmpInst.setOpcode(ARM::MOVsi);
7517 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7518 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7519 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7520 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7521 TmpInst.addOperand(Inst.getOperand(3));
7522 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7526 case ARM::t2LDMIA_UPD: {
7527 // If this is a load of a single register, then we should use
7528 // a post-indexed LDR instruction instead, per the ARM ARM.
7529 if (Inst.getNumOperands() != 5)
7532 TmpInst.setOpcode(ARM::t2LDR_POST);
7533 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7534 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7535 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7536 TmpInst.addOperand(MCOperand::CreateImm(4));
7537 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7538 TmpInst.addOperand(Inst.getOperand(3));
7542 case ARM::t2STMDB_UPD: {
7543 // If this is a store of a single register, then we should use
7544 // a pre-indexed STR instruction instead, per the ARM ARM.
7545 if (Inst.getNumOperands() != 5)
7548 TmpInst.setOpcode(ARM::t2STR_PRE);
7549 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7550 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7551 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7552 TmpInst.addOperand(MCOperand::CreateImm(-4));
7553 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7554 TmpInst.addOperand(Inst.getOperand(3));
7558 case ARM::LDMIA_UPD:
7559 // If this is a load of a single register via a 'pop', then we should use
7560 // a post-indexed LDR instruction instead, per the ARM ARM.
7561 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
7562 Inst.getNumOperands() == 5) {
7564 TmpInst.setOpcode(ARM::LDR_POST_IMM);
7565 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7566 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7567 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7568 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
7569 TmpInst.addOperand(MCOperand::CreateImm(4));
7570 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7571 TmpInst.addOperand(Inst.getOperand(3));
7576 case ARM::STMDB_UPD:
7577 // If this is a store of a single register via a 'push', then we should use
7578 // a pre-indexed STR instruction instead, per the ARM ARM.
7579 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
7580 Inst.getNumOperands() == 5) {
7582 TmpInst.setOpcode(ARM::STR_PRE_IMM);
7583 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7584 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7585 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7586 TmpInst.addOperand(MCOperand::CreateImm(-4));
7587 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7588 TmpInst.addOperand(Inst.getOperand(3));
7592 case ARM::t2ADDri12:
7593 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7594 // mnemonic was used (not "addw"), encoding T3 is preferred.
7595 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
7596 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7598 Inst.setOpcode(ARM::t2ADDri);
7599 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7601 case ARM::t2SUBri12:
7602 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7603 // mnemonic was used (not "subw"), encoding T3 is preferred.
7604 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7605 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7607 Inst.setOpcode(ARM::t2SUBri);
7608 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7611 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7612 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7613 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7614 // to encoding T1 if <Rd> is omitted."
7615 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7616 Inst.setOpcode(ARM::tADDi3);
7621 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7622 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7623 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7624 // to encoding T1 if <Rd> is omitted."
7625 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7626 Inst.setOpcode(ARM::tSUBi3);
7631 case ARM::t2SUBri: {
7632 // If the destination and first source operand are the same, and
7633 // the flags are compatible with the current IT status, use encoding T2
7634 // instead of T3. For compatibility with the system 'as'. Make sure the
7635 // wide encoding wasn't explicit.
7636 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7637 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7638 (unsigned)Inst.getOperand(2).getImm() > 255 ||
7639 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7640 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7641 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7642 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7645 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7646 ARM::tADDi8 : ARM::tSUBi8);
7647 TmpInst.addOperand(Inst.getOperand(0));
7648 TmpInst.addOperand(Inst.getOperand(5));
7649 TmpInst.addOperand(Inst.getOperand(0));
7650 TmpInst.addOperand(Inst.getOperand(2));
7651 TmpInst.addOperand(Inst.getOperand(3));
7652 TmpInst.addOperand(Inst.getOperand(4));
7656 case ARM::t2ADDrr: {
7657 // If the destination and first source operand are the same, and
7658 // there's no setting of the flags, use encoding T2 instead of T3.
7659 // Note that this is only for ADD, not SUB. This mirrors the system
7660 // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7661 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7662 Inst.getOperand(5).getReg() != 0 ||
7663 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7664 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7667 TmpInst.setOpcode(ARM::tADDhirr);
7668 TmpInst.addOperand(Inst.getOperand(0));
7669 TmpInst.addOperand(Inst.getOperand(0));
7670 TmpInst.addOperand(Inst.getOperand(2));
7671 TmpInst.addOperand(Inst.getOperand(3));
7672 TmpInst.addOperand(Inst.getOperand(4));
7676 case ARM::tADDrSP: {
7677 // If the non-SP source operand and the destination operand are not the
7678 // same, we need to use the 32-bit encoding if it's available.
7679 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7680 Inst.setOpcode(ARM::t2ADDrr);
7681 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7687 // A Thumb conditional branch outside of an IT block is a tBcc.
7688 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7689 Inst.setOpcode(ARM::tBcc);
7694 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7695 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7696 Inst.setOpcode(ARM::t2Bcc);
7701 // If the conditional is AL or we're in an IT block, we really want t2B.
7702 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7703 Inst.setOpcode(ARM::t2B);
7708 // If the conditional is AL, we really want tB.
7709 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7710 Inst.setOpcode(ARM::tB);
7715 // If the register list contains any high registers, or if the writeback
7716 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7717 // instead if we're in Thumb2. Otherwise, this should have generated
7718 // an error in validateInstruction().
7719 unsigned Rn = Inst.getOperand(0).getReg();
7720 bool hasWritebackToken =
7721 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7722 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7723 bool listContainsBase;
7724 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7725 (!listContainsBase && !hasWritebackToken) ||
7726 (listContainsBase && hasWritebackToken)) {
7727 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7728 assert (isThumbTwo());
7729 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7730 // If we're switching to the updating version, we need to insert
7731 // the writeback tied operand.
7732 if (hasWritebackToken)
7733 Inst.insert(Inst.begin(),
7734 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7739 case ARM::tSTMIA_UPD: {
7740 // If the register list contains any high registers, we need to use
7741 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7742 // should have generated an error in validateInstruction().
7743 unsigned Rn = Inst.getOperand(0).getReg();
7744 bool listContainsBase;
7745 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7746 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7747 assert (isThumbTwo());
7748 Inst.setOpcode(ARM::t2STMIA_UPD);
7754 bool listContainsBase;
7755 // If the register list contains any high registers, we need to use
7756 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7757 // should have generated an error in validateInstruction().
7758 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7760 assert (isThumbTwo());
7761 Inst.setOpcode(ARM::t2LDMIA_UPD);
7762 // Add the base register and writeback operands.
7763 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7764 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7768 bool listContainsBase;
7769 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7771 assert (isThumbTwo());
7772 Inst.setOpcode(ARM::t2STMDB_UPD);
7773 // Add the base register and writeback operands.
7774 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7775 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7779 // If we can use the 16-bit encoding and the user didn't explicitly
7780 // request the 32-bit variant, transform it here.
7781 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7782 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7783 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7784 Inst.getOperand(4).getReg() == ARM::CPSR) ||
7785 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7786 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7787 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7788 // The operands aren't in the same order for tMOVi8...
7790 TmpInst.setOpcode(ARM::tMOVi8);
7791 TmpInst.addOperand(Inst.getOperand(0));
7792 TmpInst.addOperand(Inst.getOperand(4));
7793 TmpInst.addOperand(Inst.getOperand(1));
7794 TmpInst.addOperand(Inst.getOperand(2));
7795 TmpInst.addOperand(Inst.getOperand(3));
7802 // If we can use the 16-bit encoding and the user didn't explicitly
7803 // request the 32-bit variant, transform it here.
7804 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7805 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7806 Inst.getOperand(2).getImm() == ARMCC::AL &&
7807 Inst.getOperand(4).getReg() == ARM::CPSR &&
7808 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7809 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7810 // The operands aren't the same for tMOV[S]r... (no cc_out)
7812 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7813 TmpInst.addOperand(Inst.getOperand(0));
7814 TmpInst.addOperand(Inst.getOperand(1));
7815 TmpInst.addOperand(Inst.getOperand(2));
7816 TmpInst.addOperand(Inst.getOperand(3));
7826 // If we can use the 16-bit encoding and the user didn't explicitly
7827 // request the 32-bit variant, transform it here.
7828 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7829 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7830 Inst.getOperand(2).getImm() == 0 &&
7831 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7832 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7834 switch (Inst.getOpcode()) {
7835 default: llvm_unreachable("Illegal opcode!");
7836 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7837 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7838 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7839 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7841 // The operands aren't the same for thumb1 (no rotate operand).
7843 TmpInst.setOpcode(NewOpc);
7844 TmpInst.addOperand(Inst.getOperand(0));
7845 TmpInst.addOperand(Inst.getOperand(1));
7846 TmpInst.addOperand(Inst.getOperand(3));
7847 TmpInst.addOperand(Inst.getOperand(4));
7854 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7855 // rrx shifts and asr/lsr of #32 is encoded as 0
7856 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7858 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7859 // Shifting by zero is accepted as a vanilla 'MOVr'
7861 TmpInst.setOpcode(ARM::MOVr);
7862 TmpInst.addOperand(Inst.getOperand(0));
7863 TmpInst.addOperand(Inst.getOperand(1));
7864 TmpInst.addOperand(Inst.getOperand(3));
7865 TmpInst.addOperand(Inst.getOperand(4));
7866 TmpInst.addOperand(Inst.getOperand(5));
7879 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7880 if (SOpc == ARM_AM::rrx) return false;
7881 switch (Inst.getOpcode()) {
7882 default: llvm_unreachable("unexpected opcode!");
7883 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7884 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7885 case ARM::EORrsi: newOpc = ARM::EORrr; break;
7886 case ARM::BICrsi: newOpc = ARM::BICrr; break;
7887 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7888 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7890 // If the shift is by zero, use the non-shifted instruction definition.
7891 // The exception is for right shifts, where 0 == 32
7892 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7893 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7895 TmpInst.setOpcode(newOpc);
7896 TmpInst.addOperand(Inst.getOperand(0));
7897 TmpInst.addOperand(Inst.getOperand(1));
7898 TmpInst.addOperand(Inst.getOperand(2));
7899 TmpInst.addOperand(Inst.getOperand(4));
7900 TmpInst.addOperand(Inst.getOperand(5));
7901 TmpInst.addOperand(Inst.getOperand(6));
7909 // The mask bits for all but the first condition are represented as
7910 // the low bit of the condition code value implies 't'. We currently
7911 // always have 1 implies 't', so XOR toggle the bits if the low bit
7912 // of the condition code is zero.
7913 MCOperand &MO = Inst.getOperand(1);
7914 unsigned Mask = MO.getImm();
7915 unsigned OrigMask = Mask;
7916 unsigned TZ = countTrailingZeros(Mask);
7917 if ((Inst.getOperand(0).getImm() & 1) == 0) {
7918 assert(Mask && TZ <= 3 && "illegal IT mask value!");
7919 Mask ^= (0xE << TZ) & 0xF;
7923 // Set up the IT block state according to the IT instruction we just
7925 assert(!inITBlock() && "nested IT blocks?!");
7926 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7927 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7928 ITState.CurPosition = 0;
7929 ITState.FirstCond = true;
7939 // Assemblers should use the narrow encodings of these instructions when permissible.
7940 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7941 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7942 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7943 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7944 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7945 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7946 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7948 switch (Inst.getOpcode()) {
7949 default: llvm_unreachable("unexpected opcode");
7950 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7951 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7952 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7953 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7954 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7955 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7958 TmpInst.setOpcode(NewOpc);
7959 TmpInst.addOperand(Inst.getOperand(0));
7960 TmpInst.addOperand(Inst.getOperand(5));
7961 TmpInst.addOperand(Inst.getOperand(1));
7962 TmpInst.addOperand(Inst.getOperand(2));
7963 TmpInst.addOperand(Inst.getOperand(3));
7964 TmpInst.addOperand(Inst.getOperand(4));
7975 // Assemblers should use the narrow encodings of these instructions when permissible.
7976 // These instructions are special in that they are commutable, so shorter encodings
7977 // are available more often.
7978 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7979 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7980 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7981 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7982 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7983 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7984 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7985 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7987 switch (Inst.getOpcode()) {
7988 default: llvm_unreachable("unexpected opcode");
7989 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7990 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7991 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7992 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7995 TmpInst.setOpcode(NewOpc);
7996 TmpInst.addOperand(Inst.getOperand(0));
7997 TmpInst.addOperand(Inst.getOperand(5));
7998 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7999 TmpInst.addOperand(Inst.getOperand(1));
8000 TmpInst.addOperand(Inst.getOperand(2));
8002 TmpInst.addOperand(Inst.getOperand(2));
8003 TmpInst.addOperand(Inst.getOperand(1));
8005 TmpInst.addOperand(Inst.getOperand(3));
8006 TmpInst.addOperand(Inst.getOperand(4));
8016 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
8017 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
8018 // suffix depending on whether they're in an IT block or not.
8019 unsigned Opc = Inst.getOpcode();
8020 const MCInstrDesc &MCID = MII.get(Opc);
8021 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
8022 assert(MCID.hasOptionalDef() &&
8023 "optionally flag setting instruction missing optional def operand");
8024 assert(MCID.NumOperands == Inst.getNumOperands() &&
8025 "operand count mismatch!");
8026 // Find the optional-def operand (cc_out).
8029 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
8032 // If we're parsing Thumb1, reject it completely.
8033 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
8034 return Match_MnemonicFail;
8035 // If we're parsing Thumb2, which form is legal depends on whether we're
8037 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
8039 return Match_RequiresITBlock;
8040 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
8042 return Match_RequiresNotITBlock;
8044 // Some high-register supporting Thumb1 encodings only allow both registers
8045 // to be from r0-r7 when in Thumb2.
8046 else if (Opc == ARM::tADDhirr && isThumbOne() &&
8047 isARMLowRegister(Inst.getOperand(1).getReg()) &&
8048 isARMLowRegister(Inst.getOperand(2).getReg()))
8049 return Match_RequiresThumb2;
8050 // Others only require ARMv6 or later.
8051 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
8052 isARMLowRegister(Inst.getOperand(0).getReg()) &&
8053 isARMLowRegister(Inst.getOperand(1).getReg()))
8054 return Match_RequiresV6;
8055 return Match_Success;
8059 template <> inline bool IsCPSRDead<MCInst>(MCInst *Instr) {
8060 return true; // In an assembly source, no need to second-guess
8064 static const char *getSubtargetFeatureName(unsigned Val);
8066 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
8067 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
8068 MCStreamer &Out, unsigned &ErrorInfo,
8069 bool MatchingInlineAsm) {
8071 unsigned MatchResult;
8073 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
8075 switch (MatchResult) {
8078 // Context sensitive operand constraints aren't handled by the matcher,
8079 // so check them here.
8080 if (validateInstruction(Inst, Operands)) {
8081 // Still progress the IT block, otherwise one wrong condition causes
8082 // nasty cascading errors.
8083 forwardITPosition();
8087 { // processInstruction() updates inITBlock state, we need to save it away
8088 bool wasInITBlock = inITBlock();
8090 // Some instructions need post-processing to, for example, tweak which
8091 // encoding is selected. Loop on it while changes happen so the
8092 // individual transformations can chain off each other. E.g.,
8093 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
8094 while (processInstruction(Inst, Operands))
8097 // Only after the instruction is fully processed, we can validate it
8098 if (wasInITBlock && hasV8Ops() && isThumb() &&
8099 !isV8EligibleForIT(&Inst)) {
8100 Warning(IDLoc, "deprecated instruction in IT block");
8104 // Only move forward at the very end so that everything in validate
8105 // and process gets a consistent answer about whether we're in an IT
8107 forwardITPosition();
8109 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
8110 // doesn't actually encode.
8111 if (Inst.getOpcode() == ARM::ITasm)
8115 Out.EmitInstruction(Inst, STI);
8117 case Match_MissingFeature: {
8118 assert(ErrorInfo && "Unknown missing feature!");
8119 // Special case the error message for the very common case where only
8120 // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
8121 std::string Msg = "instruction requires:";
8123 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
8124 if (ErrorInfo & Mask) {
8126 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
8130 return Error(IDLoc, Msg);
8132 case Match_InvalidOperand: {
8133 SMLoc ErrorLoc = IDLoc;
8134 if (ErrorInfo != ~0U) {
8135 if (ErrorInfo >= Operands.size())
8136 return Error(IDLoc, "too few operands for instruction");
8138 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
8139 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8142 return Error(ErrorLoc, "invalid operand for instruction");
8144 case Match_MnemonicFail:
8145 return Error(IDLoc, "invalid instruction",
8146 ((ARMOperand*)Operands[0])->getLocRange());
8147 case Match_RequiresNotITBlock:
8148 return Error(IDLoc, "flag setting instruction only valid outside IT block");
8149 case Match_RequiresITBlock:
8150 return Error(IDLoc, "instruction only valid inside IT block");
8151 case Match_RequiresV6:
8152 return Error(IDLoc, "instruction variant requires ARMv6 or later");
8153 case Match_RequiresThumb2:
8154 return Error(IDLoc, "instruction variant requires Thumb2");
8155 case Match_ImmRange0_15: {
8156 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
8157 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8158 return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
8160 case Match_ImmRange0_239: {
8161 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
8162 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8163 return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
8165 case Match_AlignedMemoryRequiresNone:
8166 case Match_DupAlignedMemoryRequiresNone:
8167 case Match_AlignedMemoryRequires16:
8168 case Match_DupAlignedMemoryRequires16:
8169 case Match_AlignedMemoryRequires32:
8170 case Match_DupAlignedMemoryRequires32:
8171 case Match_AlignedMemoryRequires64:
8172 case Match_DupAlignedMemoryRequires64:
8173 case Match_AlignedMemoryRequires64or128:
8174 case Match_DupAlignedMemoryRequires64or128:
8175 case Match_AlignedMemoryRequires64or128or256:
8177 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getAlignmentLoc();
8178 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8179 switch (MatchResult) {
8181 llvm_unreachable("Missing Match_Aligned type");
8182 case Match_AlignedMemoryRequiresNone:
8183 case Match_DupAlignedMemoryRequiresNone:
8184 return Error(ErrorLoc, "alignment must be omitted");
8185 case Match_AlignedMemoryRequires16:
8186 case Match_DupAlignedMemoryRequires16:
8187 return Error(ErrorLoc, "alignment must be 16 or omitted");
8188 case Match_AlignedMemoryRequires32:
8189 case Match_DupAlignedMemoryRequires32:
8190 return Error(ErrorLoc, "alignment must be 32 or omitted");
8191 case Match_AlignedMemoryRequires64:
8192 case Match_DupAlignedMemoryRequires64:
8193 return Error(ErrorLoc, "alignment must be 64 or omitted");
8194 case Match_AlignedMemoryRequires64or128:
8195 case Match_DupAlignedMemoryRequires64or128:
8196 return Error(ErrorLoc, "alignment must be 64, 128 or omitted");
8197 case Match_AlignedMemoryRequires64or128or256:
8198 return Error(ErrorLoc, "alignment must be 64, 128, 256 or omitted");
8203 llvm_unreachable("Implement any new match types added!");
8206 /// parseDirective parses the arm specific directives
8207 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
8208 const MCObjectFileInfo::Environment Format =
8209 getContext().getObjectFileInfo()->getObjectFileType();
8210 bool IsMachO = Format == MCObjectFileInfo::IsMachO;
8212 StringRef IDVal = DirectiveID.getIdentifier();
8213 if (IDVal == ".word")
8214 return parseLiteralValues(4, DirectiveID.getLoc());
8215 else if (IDVal == ".short" || IDVal == ".hword")
8216 return parseLiteralValues(2, DirectiveID.getLoc());
8217 else if (IDVal == ".thumb")
8218 return parseDirectiveThumb(DirectiveID.getLoc());
8219 else if (IDVal == ".arm")
8220 return parseDirectiveARM(DirectiveID.getLoc());
8221 else if (IDVal == ".thumb_func")
8222 return parseDirectiveThumbFunc(DirectiveID.getLoc());
8223 else if (IDVal == ".code")
8224 return parseDirectiveCode(DirectiveID.getLoc());
8225 else if (IDVal == ".syntax")
8226 return parseDirectiveSyntax(DirectiveID.getLoc());
8227 else if (IDVal == ".unreq")
8228 return parseDirectiveUnreq(DirectiveID.getLoc());
8229 else if (IDVal == ".fnend")
8230 return parseDirectiveFnEnd(DirectiveID.getLoc());
8231 else if (IDVal == ".cantunwind")
8232 return parseDirectiveCantUnwind(DirectiveID.getLoc());
8233 else if (IDVal == ".personality")
8234 return parseDirectivePersonality(DirectiveID.getLoc());
8235 else if (IDVal == ".handlerdata")
8236 return parseDirectiveHandlerData(DirectiveID.getLoc());
8237 else if (IDVal == ".setfp")
8238 return parseDirectiveSetFP(DirectiveID.getLoc());
8239 else if (IDVal == ".pad")
8240 return parseDirectivePad(DirectiveID.getLoc());
8241 else if (IDVal == ".save")
8242 return parseDirectiveRegSave(DirectiveID.getLoc(), false);
8243 else if (IDVal == ".vsave")
8244 return parseDirectiveRegSave(DirectiveID.getLoc(), true);
8245 else if (IDVal == ".ltorg" || IDVal == ".pool")
8246 return parseDirectiveLtorg(DirectiveID.getLoc());
8247 else if (IDVal == ".even")
8248 return parseDirectiveEven(DirectiveID.getLoc());
8249 else if (IDVal == ".personalityindex")
8250 return parseDirectivePersonalityIndex(DirectiveID.getLoc());
8251 else if (IDVal == ".unwind_raw")
8252 return parseDirectiveUnwindRaw(DirectiveID.getLoc());
8253 else if (IDVal == ".movsp")
8254 return parseDirectiveMovSP(DirectiveID.getLoc());
8255 else if (IDVal == ".arch_extension")
8256 return parseDirectiveArchExtension(DirectiveID.getLoc());
8257 else if (IDVal == ".align")
8258 return parseDirectiveAlign(DirectiveID.getLoc());
8259 else if (IDVal == ".thumb_set")
8260 return parseDirectiveThumbSet(DirectiveID.getLoc());
8263 if (IDVal == ".arch")
8264 return parseDirectiveArch(DirectiveID.getLoc());
8265 else if (IDVal == ".cpu")
8266 return parseDirectiveCPU(DirectiveID.getLoc());
8267 else if (IDVal == ".eabi_attribute")
8268 return parseDirectiveEabiAttr(DirectiveID.getLoc());
8269 else if (IDVal == ".fpu")
8270 return parseDirectiveFPU(DirectiveID.getLoc());
8271 else if (IDVal == ".fnstart")
8272 return parseDirectiveFnStart(DirectiveID.getLoc());
8273 else if (IDVal == ".inst")
8274 return parseDirectiveInst(DirectiveID.getLoc());
8275 else if (IDVal == ".inst.n")
8276 return parseDirectiveInst(DirectiveID.getLoc(), 'n');
8277 else if (IDVal == ".inst.w")
8278 return parseDirectiveInst(DirectiveID.getLoc(), 'w');
8279 else if (IDVal == ".object_arch")
8280 return parseDirectiveObjectArch(DirectiveID.getLoc());
8281 else if (IDVal == ".tlsdescseq")
8282 return parseDirectiveTLSDescSeq(DirectiveID.getLoc());
8288 /// parseLiteralValues
8289 /// ::= .hword expression [, expression]*
8290 /// ::= .short expression [, expression]*
8291 /// ::= .word expression [, expression]*
8292 bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
8293 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8295 const MCExpr *Value;
8296 if (getParser().parseExpression(Value)) {
8297 Parser.eatToEndOfStatement();
8301 getParser().getStreamer().EmitValue(Value, Size);
8303 if (getLexer().is(AsmToken::EndOfStatement))
8306 // FIXME: Improve diagnostic.
8307 if (getLexer().isNot(AsmToken::Comma)) {
8308 Error(L, "unexpected token in directive");
8319 /// parseDirectiveThumb
8321 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
8322 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8323 Error(L, "unexpected token in directive");
8329 Error(L, "target does not support Thumb mode");
8336 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8340 /// parseDirectiveARM
8342 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
8343 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8344 Error(L, "unexpected token in directive");
8350 Error(L, "target does not support ARM mode");
8357 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8361 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
8362 if (NextSymbolIsThumb) {
8363 getParser().getStreamer().EmitThumbFunc(Symbol);
8364 NextSymbolIsThumb = false;
8368 /// parseDirectiveThumbFunc
8369 /// ::= .thumbfunc symbol_name
8370 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
8371 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
8372 bool isMachO = MAI->hasSubsectionsViaSymbols();
8374 // Darwin asm has (optionally) function name after .thumb_func direction
8377 const AsmToken &Tok = Parser.getTok();
8378 if (Tok.isNot(AsmToken::EndOfStatement)) {
8379 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) {
8380 Error(L, "unexpected token in .thumb_func directive");
8385 getParser().getContext().GetOrCreateSymbol(Tok.getIdentifier());
8386 getParser().getStreamer().EmitThumbFunc(Func);
8387 Parser.Lex(); // Consume the identifier token.
8392 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8393 Error(L, "unexpected token in directive");
8397 NextSymbolIsThumb = true;
8401 /// parseDirectiveSyntax
8402 /// ::= .syntax unified | divided
8403 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
8404 const AsmToken &Tok = Parser.getTok();
8405 if (Tok.isNot(AsmToken::Identifier)) {
8406 Error(L, "unexpected token in .syntax directive");
8410 StringRef Mode = Tok.getString();
8411 if (Mode == "unified" || Mode == "UNIFIED") {
8413 } else if (Mode == "divided" || Mode == "DIVIDED") {
8414 Error(L, "'.syntax divided' arm asssembly not supported");
8417 Error(L, "unrecognized syntax mode in .syntax directive");
8421 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8422 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8427 // TODO tell the MC streamer the mode
8428 // getParser().getStreamer().Emit???();
8432 /// parseDirectiveCode
8433 /// ::= .code 16 | 32
8434 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
8435 const AsmToken &Tok = Parser.getTok();
8436 if (Tok.isNot(AsmToken::Integer)) {
8437 Error(L, "unexpected token in .code directive");
8440 int64_t Val = Parser.getTok().getIntVal();
8441 if (Val != 16 && Val != 32) {
8442 Error(L, "invalid operand to .code directive");
8447 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8448 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8455 Error(L, "target does not support Thumb mode");
8461 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8464 Error(L, "target does not support ARM mode");
8470 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8476 /// parseDirectiveReq
8477 /// ::= name .req registername
8478 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
8479 Parser.Lex(); // Eat the '.req' token.
8481 SMLoc SRegLoc, ERegLoc;
8482 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
8483 Parser.eatToEndOfStatement();
8484 Error(SRegLoc, "register name expected");
8488 // Shouldn't be anything else.
8489 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
8490 Parser.eatToEndOfStatement();
8491 Error(Parser.getTok().getLoc(), "unexpected input in .req directive.");
8495 Parser.Lex(); // Consume the EndOfStatement
8497 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg) {
8498 Error(SRegLoc, "redefinition of '" + Name + "' does not match original.");
8505 /// parseDirectiveUneq
8506 /// ::= .unreq registername
8507 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
8508 if (Parser.getTok().isNot(AsmToken::Identifier)) {
8509 Parser.eatToEndOfStatement();
8510 Error(L, "unexpected input in .unreq directive.");
8513 RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
8514 Parser.Lex(); // Eat the identifier.
8518 /// parseDirectiveArch
8520 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
8521 StringRef Arch = getParser().parseStringToEndOfStatement().trim();
8523 unsigned ID = StringSwitch<unsigned>(Arch)
8524 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
8525 .Case(NAME, ARM::ID)
8526 #define ARM_ARCH_ALIAS(NAME, ID) \
8527 .Case(NAME, ARM::ID)
8528 #include "MCTargetDesc/ARMArchName.def"
8529 .Default(ARM::INVALID_ARCH);
8531 if (ID == ARM::INVALID_ARCH) {
8532 Error(L, "Unknown arch name");
8536 getTargetStreamer().emitArch(ID);
8540 /// parseDirectiveEabiAttr
8541 /// ::= .eabi_attribute int, int [, "str"]
8542 /// ::= .eabi_attribute Tag_name, int [, "str"]
8543 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
8546 TagLoc = Parser.getTok().getLoc();
8547 if (Parser.getTok().is(AsmToken::Identifier)) {
8548 StringRef Name = Parser.getTok().getIdentifier();
8549 Tag = ARMBuildAttrs::AttrTypeFromString(Name);
8551 Error(TagLoc, "attribute name not recognised: " + Name);
8552 Parser.eatToEndOfStatement();
8557 const MCExpr *AttrExpr;
8559 TagLoc = Parser.getTok().getLoc();
8560 if (Parser.parseExpression(AttrExpr)) {
8561 Parser.eatToEndOfStatement();
8565 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
8567 Error(TagLoc, "expected numeric constant");
8568 Parser.eatToEndOfStatement();
8572 Tag = CE->getValue();
8575 if (Parser.getTok().isNot(AsmToken::Comma)) {
8576 Error(Parser.getTok().getLoc(), "comma expected");
8577 Parser.eatToEndOfStatement();
8580 Parser.Lex(); // skip comma
8582 StringRef StringValue = "";
8583 bool IsStringValue = false;
8585 int64_t IntegerValue = 0;
8586 bool IsIntegerValue = false;
8588 if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
8589 IsStringValue = true;
8590 else if (Tag == ARMBuildAttrs::compatibility) {
8591 IsStringValue = true;
8592 IsIntegerValue = true;
8593 } else if (Tag < 32 || Tag % 2 == 0)
8594 IsIntegerValue = true;
8595 else if (Tag % 2 == 1)
8596 IsStringValue = true;
8598 llvm_unreachable("invalid tag type");
8600 if (IsIntegerValue) {
8601 const MCExpr *ValueExpr;
8602 SMLoc ValueExprLoc = Parser.getTok().getLoc();
8603 if (Parser.parseExpression(ValueExpr)) {
8604 Parser.eatToEndOfStatement();
8608 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
8610 Error(ValueExprLoc, "expected numeric constant");
8611 Parser.eatToEndOfStatement();
8615 IntegerValue = CE->getValue();
8618 if (Tag == ARMBuildAttrs::compatibility) {
8619 if (Parser.getTok().isNot(AsmToken::Comma))
8620 IsStringValue = false;
8625 if (IsStringValue) {
8626 if (Parser.getTok().isNot(AsmToken::String)) {
8627 Error(Parser.getTok().getLoc(), "bad string constant");
8628 Parser.eatToEndOfStatement();
8632 StringValue = Parser.getTok().getStringContents();
8636 if (IsIntegerValue && IsStringValue) {
8637 assert(Tag == ARMBuildAttrs::compatibility);
8638 getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
8639 } else if (IsIntegerValue)
8640 getTargetStreamer().emitAttribute(Tag, IntegerValue);
8641 else if (IsStringValue)
8642 getTargetStreamer().emitTextAttribute(Tag, StringValue);
8646 /// parseDirectiveCPU
8648 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
8649 StringRef CPU = getParser().parseStringToEndOfStatement().trim();
8650 getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
8654 /// parseDirectiveFPU
8656 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
8657 StringRef FPU = getParser().parseStringToEndOfStatement().trim();
8659 unsigned ID = StringSwitch<unsigned>(FPU)
8660 #define ARM_FPU_NAME(NAME, ID) .Case(NAME, ARM::ID)
8661 #include "ARMFPUName.def"
8662 .Default(ARM::INVALID_FPU);
8664 if (ID == ARM::INVALID_FPU) {
8665 Error(L, "Unknown FPU name");
8669 getTargetStreamer().emitFPU(ID);
8673 /// parseDirectiveFnStart
8675 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
8676 if (UC.hasFnStart()) {
8677 Error(L, ".fnstart starts before the end of previous one");
8678 UC.emitFnStartLocNotes();
8682 // Reset the unwind directives parser state
8685 getTargetStreamer().emitFnStart();
8687 UC.recordFnStart(L);
8691 /// parseDirectiveFnEnd
8693 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
8694 // Check the ordering of unwind directives
8695 if (!UC.hasFnStart()) {
8696 Error(L, ".fnstart must precede .fnend directive");
8700 // Reset the unwind directives parser state
8701 getTargetStreamer().emitFnEnd();
8707 /// parseDirectiveCantUnwind
8709 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
8710 UC.recordCantUnwind(L);
8712 // Check the ordering of unwind directives
8713 if (!UC.hasFnStart()) {
8714 Error(L, ".fnstart must precede .cantunwind directive");
8717 if (UC.hasHandlerData()) {
8718 Error(L, ".cantunwind can't be used with .handlerdata directive");
8719 UC.emitHandlerDataLocNotes();
8722 if (UC.hasPersonality()) {
8723 Error(L, ".cantunwind can't be used with .personality directive");
8724 UC.emitPersonalityLocNotes();
8728 getTargetStreamer().emitCantUnwind();
8732 /// parseDirectivePersonality
8733 /// ::= .personality name
8734 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
8735 bool HasExistingPersonality = UC.hasPersonality();
8737 UC.recordPersonality(L);
8739 // Check the ordering of unwind directives
8740 if (!UC.hasFnStart()) {
8741 Error(L, ".fnstart must precede .personality directive");
8744 if (UC.cantUnwind()) {
8745 Error(L, ".personality can't be used with .cantunwind directive");
8746 UC.emitCantUnwindLocNotes();
8749 if (UC.hasHandlerData()) {
8750 Error(L, ".personality must precede .handlerdata directive");
8751 UC.emitHandlerDataLocNotes();
8754 if (HasExistingPersonality) {
8755 Parser.eatToEndOfStatement();
8756 Error(L, "multiple personality directives");
8757 UC.emitPersonalityLocNotes();
8761 // Parse the name of the personality routine
8762 if (Parser.getTok().isNot(AsmToken::Identifier)) {
8763 Parser.eatToEndOfStatement();
8764 Error(L, "unexpected input in .personality directive.");
8767 StringRef Name(Parser.getTok().getIdentifier());
8770 MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
8771 getTargetStreamer().emitPersonality(PR);
8775 /// parseDirectiveHandlerData
8776 /// ::= .handlerdata
8777 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
8778 UC.recordHandlerData(L);
8780 // Check the ordering of unwind directives
8781 if (!UC.hasFnStart()) {
8782 Error(L, ".fnstart must precede .personality directive");
8785 if (UC.cantUnwind()) {
8786 Error(L, ".handlerdata can't be used with .cantunwind directive");
8787 UC.emitCantUnwindLocNotes();
8791 getTargetStreamer().emitHandlerData();
8795 /// parseDirectiveSetFP
8796 /// ::= .setfp fpreg, spreg [, offset]
8797 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
8798 // Check the ordering of unwind directives
8799 if (!UC.hasFnStart()) {
8800 Error(L, ".fnstart must precede .setfp directive");
8803 if (UC.hasHandlerData()) {
8804 Error(L, ".setfp must precede .handlerdata directive");
8809 SMLoc FPRegLoc = Parser.getTok().getLoc();
8810 int FPReg = tryParseRegister();
8812 Error(FPRegLoc, "frame pointer register expected");
8817 if (Parser.getTok().isNot(AsmToken::Comma)) {
8818 Error(Parser.getTok().getLoc(), "comma expected");
8821 Parser.Lex(); // skip comma
8824 SMLoc SPRegLoc = Parser.getTok().getLoc();
8825 int SPReg = tryParseRegister();
8827 Error(SPRegLoc, "stack pointer register expected");
8831 if (SPReg != ARM::SP && SPReg != UC.getFPReg()) {
8832 Error(SPRegLoc, "register should be either $sp or the latest fp register");
8836 // Update the frame pointer register
8837 UC.saveFPReg(FPReg);
8841 if (Parser.getTok().is(AsmToken::Comma)) {
8842 Parser.Lex(); // skip comma
8844 if (Parser.getTok().isNot(AsmToken::Hash) &&
8845 Parser.getTok().isNot(AsmToken::Dollar)) {
8846 Error(Parser.getTok().getLoc(), "'#' expected");
8849 Parser.Lex(); // skip hash token.
8851 const MCExpr *OffsetExpr;
8852 SMLoc ExLoc = Parser.getTok().getLoc();
8854 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
8855 Error(ExLoc, "malformed setfp offset");
8858 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8860 Error(ExLoc, "setfp offset must be an immediate");
8864 Offset = CE->getValue();
8867 getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
8868 static_cast<unsigned>(SPReg), Offset);
8874 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
8875 // Check the ordering of unwind directives
8876 if (!UC.hasFnStart()) {
8877 Error(L, ".fnstart must precede .pad directive");
8880 if (UC.hasHandlerData()) {
8881 Error(L, ".pad must precede .handlerdata directive");
8886 if (Parser.getTok().isNot(AsmToken::Hash) &&
8887 Parser.getTok().isNot(AsmToken::Dollar)) {
8888 Error(Parser.getTok().getLoc(), "'#' expected");
8891 Parser.Lex(); // skip hash token.
8893 const MCExpr *OffsetExpr;
8894 SMLoc ExLoc = Parser.getTok().getLoc();
8896 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
8897 Error(ExLoc, "malformed pad offset");
8900 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8902 Error(ExLoc, "pad offset must be an immediate");
8906 getTargetStreamer().emitPad(CE->getValue());
8910 /// parseDirectiveRegSave
8911 /// ::= .save { registers }
8912 /// ::= .vsave { registers }
8913 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
8914 // Check the ordering of unwind directives
8915 if (!UC.hasFnStart()) {
8916 Error(L, ".fnstart must precede .save or .vsave directives");
8919 if (UC.hasHandlerData()) {
8920 Error(L, ".save or .vsave must precede .handlerdata directive");
8924 // RAII object to make sure parsed operands are deleted.
8925 struct CleanupObject {
8926 SmallVector<MCParsedAsmOperand *, 1> Operands;
8928 for (unsigned I = 0, E = Operands.size(); I != E; ++I)
8933 // Parse the register list
8934 if (parseRegisterList(CO.Operands))
8936 ARMOperand *Op = (ARMOperand*)CO.Operands[0];
8937 if (!IsVector && !Op->isRegList()) {
8938 Error(L, ".save expects GPR registers");
8941 if (IsVector && !Op->isDPRRegList()) {
8942 Error(L, ".vsave expects DPR registers");
8946 getTargetStreamer().emitRegSave(Op->getRegList(), IsVector);
8950 /// parseDirectiveInst
8951 /// ::= .inst opcode [, ...]
8952 /// ::= .inst.n opcode [, ...]
8953 /// ::= .inst.w opcode [, ...]
8954 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
8966 Parser.eatToEndOfStatement();
8967 Error(Loc, "cannot determine Thumb instruction size, "
8968 "use inst.n/inst.w instead");
8973 Parser.eatToEndOfStatement();
8974 Error(Loc, "width suffixes are invalid in ARM mode");
8980 if (getLexer().is(AsmToken::EndOfStatement)) {
8981 Parser.eatToEndOfStatement();
8982 Error(Loc, "expected expression following directive");
8989 if (getParser().parseExpression(Expr)) {
8990 Error(Loc, "expected expression");
8994 const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
8996 Error(Loc, "expected constant expression");
9002 if (Value->getValue() > 0xffff) {
9003 Error(Loc, "inst.n operand is too big, use inst.w instead");
9008 if (Value->getValue() > 0xffffffff) {
9010 StringRef(Suffix ? "inst.w" : "inst") + " operand is too big");
9015 llvm_unreachable("only supported widths are 2 and 4");
9018 getTargetStreamer().emitInst(Value->getValue(), Suffix);
9020 if (getLexer().is(AsmToken::EndOfStatement))
9023 if (getLexer().isNot(AsmToken::Comma)) {
9024 Error(Loc, "unexpected token in directive");
9035 /// parseDirectiveLtorg
9036 /// ::= .ltorg | .pool
9037 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
9038 getTargetStreamer().emitCurrentConstantPool();
9042 bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
9043 const MCSection *Section = getStreamer().getCurrentSection().first;
9045 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9046 TokError("unexpected token in directive");
9051 getStreamer().InitSections();
9052 Section = getStreamer().getCurrentSection().first;
9055 assert(Section && "must have section to emit alignment");
9056 if (Section->UseCodeAlign())
9057 getStreamer().EmitCodeAlignment(2);
9059 getStreamer().EmitValueToAlignment(2);
9064 /// parseDirectivePersonalityIndex
9065 /// ::= .personalityindex index
9066 bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) {
9067 bool HasExistingPersonality = UC.hasPersonality();
9069 UC.recordPersonalityIndex(L);
9071 if (!UC.hasFnStart()) {
9072 Parser.eatToEndOfStatement();
9073 Error(L, ".fnstart must precede .personalityindex directive");
9076 if (UC.cantUnwind()) {
9077 Parser.eatToEndOfStatement();
9078 Error(L, ".personalityindex cannot be used with .cantunwind");
9079 UC.emitCantUnwindLocNotes();
9082 if (UC.hasHandlerData()) {
9083 Parser.eatToEndOfStatement();
9084 Error(L, ".personalityindex must precede .handlerdata directive");
9085 UC.emitHandlerDataLocNotes();
9088 if (HasExistingPersonality) {
9089 Parser.eatToEndOfStatement();
9090 Error(L, "multiple personality directives");
9091 UC.emitPersonalityLocNotes();
9095 const MCExpr *IndexExpression;
9096 SMLoc IndexLoc = Parser.getTok().getLoc();
9097 if (Parser.parseExpression(IndexExpression)) {
9098 Parser.eatToEndOfStatement();
9102 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
9104 Parser.eatToEndOfStatement();
9105 Error(IndexLoc, "index must be a constant number");
9108 if (CE->getValue() < 0 ||
9109 CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) {
9110 Parser.eatToEndOfStatement();
9111 Error(IndexLoc, "personality routine index should be in range [0-3]");
9115 getTargetStreamer().emitPersonalityIndex(CE->getValue());
9119 /// parseDirectiveUnwindRaw
9120 /// ::= .unwind_raw offset, opcode [, opcode...]
9121 bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
9122 if (!UC.hasFnStart()) {
9123 Parser.eatToEndOfStatement();
9124 Error(L, ".fnstart must precede .unwind_raw directives");
9128 int64_t StackOffset;
9130 const MCExpr *OffsetExpr;
9131 SMLoc OffsetLoc = getLexer().getLoc();
9132 if (getLexer().is(AsmToken::EndOfStatement) ||
9133 getParser().parseExpression(OffsetExpr)) {
9134 Error(OffsetLoc, "expected expression");
9135 Parser.eatToEndOfStatement();
9139 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9141 Error(OffsetLoc, "offset must be a constant");
9142 Parser.eatToEndOfStatement();
9146 StackOffset = CE->getValue();
9148 if (getLexer().isNot(AsmToken::Comma)) {
9149 Error(getLexer().getLoc(), "expected comma");
9150 Parser.eatToEndOfStatement();
9155 SmallVector<uint8_t, 16> Opcodes;
9159 SMLoc OpcodeLoc = getLexer().getLoc();
9160 if (getLexer().is(AsmToken::EndOfStatement) || Parser.parseExpression(OE)) {
9161 Error(OpcodeLoc, "expected opcode expression");
9162 Parser.eatToEndOfStatement();
9166 const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
9168 Error(OpcodeLoc, "opcode value must be a constant");
9169 Parser.eatToEndOfStatement();
9173 const int64_t Opcode = OC->getValue();
9174 if (Opcode & ~0xff) {
9175 Error(OpcodeLoc, "invalid opcode");
9176 Parser.eatToEndOfStatement();
9180 Opcodes.push_back(uint8_t(Opcode));
9182 if (getLexer().is(AsmToken::EndOfStatement))
9185 if (getLexer().isNot(AsmToken::Comma)) {
9186 Error(getLexer().getLoc(), "unexpected token in directive");
9187 Parser.eatToEndOfStatement();
9194 getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes);
9200 /// parseDirectiveTLSDescSeq
9201 /// ::= .tlsdescseq tls-variable
9202 bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) {
9203 if (getLexer().isNot(AsmToken::Identifier)) {
9204 TokError("expected variable after '.tlsdescseq' directive");
9205 Parser.eatToEndOfStatement();
9209 const MCSymbolRefExpr *SRE =
9210 MCSymbolRefExpr::Create(Parser.getTok().getIdentifier(),
9211 MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext());
9214 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9215 Error(Parser.getTok().getLoc(), "unexpected token");
9216 Parser.eatToEndOfStatement();
9220 getTargetStreamer().AnnotateTLSDescriptorSequence(SRE);
9224 /// parseDirectiveMovSP
9225 /// ::= .movsp reg [, #offset]
9226 bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) {
9227 if (!UC.hasFnStart()) {
9228 Parser.eatToEndOfStatement();
9229 Error(L, ".fnstart must precede .movsp directives");
9232 if (UC.getFPReg() != ARM::SP) {
9233 Parser.eatToEndOfStatement();
9234 Error(L, "unexpected .movsp directive");
9238 SMLoc SPRegLoc = Parser.getTok().getLoc();
9239 int SPReg = tryParseRegister();
9241 Parser.eatToEndOfStatement();
9242 Error(SPRegLoc, "register expected");
9246 if (SPReg == ARM::SP || SPReg == ARM::PC) {
9247 Parser.eatToEndOfStatement();
9248 Error(SPRegLoc, "sp and pc are not permitted in .movsp directive");
9253 if (Parser.getTok().is(AsmToken::Comma)) {
9256 if (Parser.getTok().isNot(AsmToken::Hash)) {
9257 Error(Parser.getTok().getLoc(), "expected #constant");
9258 Parser.eatToEndOfStatement();
9263 const MCExpr *OffsetExpr;
9264 SMLoc OffsetLoc = Parser.getTok().getLoc();
9265 if (Parser.parseExpression(OffsetExpr)) {
9266 Parser.eatToEndOfStatement();
9267 Error(OffsetLoc, "malformed offset expression");
9271 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9273 Parser.eatToEndOfStatement();
9274 Error(OffsetLoc, "offset must be an immediate constant");
9278 Offset = CE->getValue();
9281 getTargetStreamer().emitMovSP(SPReg, Offset);
9282 UC.saveFPReg(SPReg);
9287 /// parseDirectiveObjectArch
9288 /// ::= .object_arch name
9289 bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
9290 if (getLexer().isNot(AsmToken::Identifier)) {
9291 Error(getLexer().getLoc(), "unexpected token");
9292 Parser.eatToEndOfStatement();
9296 StringRef Arch = Parser.getTok().getString();
9297 SMLoc ArchLoc = Parser.getTok().getLoc();
9300 unsigned ID = StringSwitch<unsigned>(Arch)
9301 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
9302 .Case(NAME, ARM::ID)
9303 #define ARM_ARCH_ALIAS(NAME, ID) \
9304 .Case(NAME, ARM::ID)
9305 #include "MCTargetDesc/ARMArchName.def"
9306 #undef ARM_ARCH_NAME
9307 #undef ARM_ARCH_ALIAS
9308 .Default(ARM::INVALID_ARCH);
9310 if (ID == ARM::INVALID_ARCH) {
9311 Error(ArchLoc, "unknown architecture '" + Arch + "'");
9312 Parser.eatToEndOfStatement();
9316 getTargetStreamer().emitObjectArch(ID);
9318 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9319 Error(getLexer().getLoc(), "unexpected token");
9320 Parser.eatToEndOfStatement();
9326 /// parseDirectiveAlign
9328 bool ARMAsmParser::parseDirectiveAlign(SMLoc L) {
9329 // NOTE: if this is not the end of the statement, fall back to the target
9330 // agnostic handling for this directive which will correctly handle this.
9331 if (getLexer().isNot(AsmToken::EndOfStatement))
9334 // '.align' is target specifically handled to mean 2**2 byte alignment.
9335 if (getStreamer().getCurrentSection().first->UseCodeAlign())
9336 getStreamer().EmitCodeAlignment(4, 0);
9338 getStreamer().EmitValueToAlignment(4, 0, 1, 0);
9343 /// parseDirectiveThumbSet
9344 /// ::= .thumb_set name, value
9345 bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) {
9347 if (Parser.parseIdentifier(Name)) {
9348 TokError("expected identifier after '.thumb_set'");
9349 Parser.eatToEndOfStatement();
9353 if (getLexer().isNot(AsmToken::Comma)) {
9354 TokError("expected comma after name '" + Name + "'");
9355 Parser.eatToEndOfStatement();
9360 const MCExpr *Value;
9361 if (Parser.parseExpression(Value)) {
9362 TokError("missing expression");
9363 Parser.eatToEndOfStatement();
9367 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9368 TokError("unexpected token");
9369 Parser.eatToEndOfStatement();
9374 MCSymbol *Alias = getContext().GetOrCreateSymbol(Name);
9375 getTargetStreamer().emitThumbSet(Alias, Value);
9379 /// Force static initialization.
9380 extern "C" void LLVMInitializeARMAsmParser() {
9381 RegisterMCAsmParser<ARMAsmParser> X(TheARMLETarget);
9382 RegisterMCAsmParser<ARMAsmParser> Y(TheARMBETarget);
9383 RegisterMCAsmParser<ARMAsmParser> A(TheThumbLETarget);
9384 RegisterMCAsmParser<ARMAsmParser> B(TheThumbBETarget);
9387 #define GET_REGISTER_MATCHER
9388 #define GET_SUBTARGET_FEATURE_NAME
9389 #define GET_MATCHER_IMPLEMENTATION
9390 #include "ARMGenAsmMatcher.inc"
9392 static const struct ExtMapEntry {
9393 const char *Extension;
9394 const unsigned ArchCheck;
9395 const uint64_t Features;
9397 { "crc", Feature_HasV8, ARM::FeatureCRC },
9398 { "crypto", Feature_HasV8,
9399 ARM::FeatureCrypto | ARM::FeatureNEON | ARM::FeatureFPARMv8 },
9400 { "fp", Feature_HasV8, ARM::FeatureFPARMv8 },
9401 { "idiv", Feature_HasV7 | Feature_IsNotMClass,
9402 ARM::FeatureHWDiv | ARM::FeatureHWDivARM },
9403 // FIXME: iWMMXT not supported
9404 { "iwmmxt", Feature_None, 0 },
9405 // FIXME: iWMMXT2 not supported
9406 { "iwmmxt2", Feature_None, 0 },
9407 // FIXME: Maverick not supported
9408 { "maverick", Feature_None, 0 },
9409 { "mp", Feature_HasV7 | Feature_IsNotMClass, ARM::FeatureMP },
9410 // FIXME: ARMv6-m OS Extensions feature not checked
9411 { "os", Feature_None, 0 },
9412 // FIXME: Also available in ARMv6-K
9413 { "sec", Feature_HasV7, ARM::FeatureTrustZone },
9414 { "simd", Feature_HasV8, ARM::FeatureNEON | ARM::FeatureFPARMv8 },
9415 // FIXME: Only available in A-class, isel not predicated
9416 { "virt", Feature_HasV7, ARM::FeatureVirtualization },
9417 // FIXME: xscale not supported
9418 { "xscale", Feature_None, 0 },
9421 /// parseDirectiveArchExtension
9422 /// ::= .arch_extension [no]feature
9423 bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
9424 if (getLexer().isNot(AsmToken::Identifier)) {
9425 Error(getLexer().getLoc(), "unexpected token");
9426 Parser.eatToEndOfStatement();
9430 StringRef Extension = Parser.getTok().getString();
9431 SMLoc ExtLoc = Parser.getTok().getLoc();
9434 bool EnableFeature = true;
9435 if (Extension.startswith_lower("no")) {
9436 EnableFeature = false;
9437 Extension = Extension.substr(2);
9440 for (unsigned EI = 0, EE = array_lengthof(Extensions); EI != EE; ++EI) {
9441 if (Extensions[EI].Extension != Extension)
9444 unsigned FB = getAvailableFeatures();
9445 if ((FB & Extensions[EI].ArchCheck) != Extensions[EI].ArchCheck) {
9446 Error(ExtLoc, "architectural extension '" + Extension + "' is not "
9447 "allowed for the current base architecture");
9451 if (!Extensions[EI].Features)
9452 report_fatal_error("unsupported architectural extension: " + Extension);
9455 FB |= ComputeAvailableFeatures(Extensions[EI].Features);
9457 FB &= ~ComputeAvailableFeatures(Extensions[EI].Features);
9459 setAvailableFeatures(FB);
9463 Error(ExtLoc, "unknown architectural extension: " + Extension);
9464 Parser.eatToEndOfStatement();
9468 // Define this matcher function after the auto-generated include so we
9469 // have the match class enum definitions.
9470 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
9472 ARMOperand *Op = static_cast<ARMOperand*>(AsmOp);
9473 // If the kind is a token for a literal immediate, check if our asm
9474 // operand matches. This is for InstAliases which have a fixed-value
9475 // immediate in the syntax.
9480 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()))
9481 if (CE->getValue() == 0)
9482 return Match_Success;
9486 const MCExpr *SOExpr = Op->getImm();
9488 if (!SOExpr->EvaluateAsAbsolute(Value))
9489 return Match_Success;
9490 assert((Value >= INT32_MIN && Value <= INT32_MAX) &&
9491 "expression value must be representiable in 32 bits");
9496 MRI->getRegClass(ARM::GPRRegClassID).contains(Op->getReg()))
9497 return Match_Success;
9500 return Match_InvalidOperand;