1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMBaseInfo.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMMCExpr.h"
13 #include "llvm/MC/MCParser/MCAsmLexer.h"
14 #include "llvm/MC/MCParser/MCAsmParser.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCAsmInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCTargetAsmParser.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/SourceMgr.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/ADT/BitVector.h"
30 #include "llvm/ADT/OwningPtr.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/StringSwitch.h"
34 #include "llvm/ADT/Twine.h"
42 enum VectorLaneTy { NoLanes, AllLanes };
44 class ARMAsmParser : public MCTargetAsmParser {
49 ARMCC::CondCodes Cond; // Condition for IT block.
50 unsigned Mask:4; // Condition mask for instructions.
51 // Starting at first 1 (from lsb).
52 // '1' condition as indicated in IT.
53 // '0' inverse of condition (else).
54 // Count of instructions in IT block is
55 // 4 - trailingzeroes(mask)
57 bool FirstCond; // Explicit flag for when we're parsing the
58 // First instruction in the IT block. It's
59 // implied in the mask, so needs special
62 unsigned CurPosition; // Current position in parsing of IT
63 // block. In range [0,3]. Initialized
64 // according to count of instructions in block.
65 // ~0U if no active IT block.
67 bool inITBlock() { return ITState.CurPosition != ~0U;}
68 void forwardITPosition() {
69 if (!inITBlock()) return;
70 // Move to the next instruction in the IT block, if there is one. If not,
71 // mark the block as done.
72 unsigned TZ = CountTrailingZeros_32(ITState.Mask);
73 if (++ITState.CurPosition == 5 - TZ)
74 ITState.CurPosition = ~0U; // Done with the IT block after this.
78 MCAsmParser &getParser() const { return Parser; }
79 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
81 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
82 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
84 int tryParseRegister();
85 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
86 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
87 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
88 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
89 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
90 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
91 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
92 unsigned &ShiftAmount);
93 bool parseDirectiveWord(unsigned Size, SMLoc L);
94 bool parseDirectiveThumb(SMLoc L);
95 bool parseDirectiveThumbFunc(SMLoc L);
96 bool parseDirectiveCode(SMLoc L);
97 bool parseDirectiveSyntax(SMLoc L);
99 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
100 bool &CarrySetting, unsigned &ProcessorIMod,
102 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
103 bool &CanAcceptPredicationCode);
105 bool isThumb() const {
106 // FIXME: Can tablegen auto-generate this?
107 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
109 bool isThumbOne() const {
110 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
112 bool isThumbTwo() const {
113 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
115 bool hasV6Ops() const {
116 return STI.getFeatureBits() & ARM::HasV6Ops;
118 bool hasV7Ops() const {
119 return STI.getFeatureBits() & ARM::HasV7Ops;
122 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
123 setAvailableFeatures(FB);
125 bool isMClass() const {
126 return STI.getFeatureBits() & ARM::FeatureMClass;
129 /// @name Auto-generated Match Functions
132 #define GET_ASSEMBLER_HEADER
133 #include "ARMGenAsmMatcher.inc"
137 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
138 OperandMatchResultTy parseCoprocNumOperand(
139 SmallVectorImpl<MCParsedAsmOperand*>&);
140 OperandMatchResultTy parseCoprocRegOperand(
141 SmallVectorImpl<MCParsedAsmOperand*>&);
142 OperandMatchResultTy parseCoprocOptionOperand(
143 SmallVectorImpl<MCParsedAsmOperand*>&);
144 OperandMatchResultTy parseMemBarrierOptOperand(
145 SmallVectorImpl<MCParsedAsmOperand*>&);
146 OperandMatchResultTy parseProcIFlagsOperand(
147 SmallVectorImpl<MCParsedAsmOperand*>&);
148 OperandMatchResultTy parseMSRMaskOperand(
149 SmallVectorImpl<MCParsedAsmOperand*>&);
150 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
151 StringRef Op, int Low, int High);
152 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
153 return parsePKHImm(O, "lsl", 0, 31);
155 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
156 return parsePKHImm(O, "asr", 1, 32);
158 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
159 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
160 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
161 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
162 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
163 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
164 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
165 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
166 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind);
168 // Asm Match Converter Methods
169 bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
170 const SmallVectorImpl<MCParsedAsmOperand*> &);
171 bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
172 const SmallVectorImpl<MCParsedAsmOperand*> &);
173 bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
174 const SmallVectorImpl<MCParsedAsmOperand*> &);
175 bool cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
176 const SmallVectorImpl<MCParsedAsmOperand*> &);
177 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
178 const SmallVectorImpl<MCParsedAsmOperand*> &);
179 bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
180 const SmallVectorImpl<MCParsedAsmOperand*> &);
181 bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
182 const SmallVectorImpl<MCParsedAsmOperand*> &);
183 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
184 const SmallVectorImpl<MCParsedAsmOperand*> &);
185 bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
186 const SmallVectorImpl<MCParsedAsmOperand*> &);
187 bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
188 const SmallVectorImpl<MCParsedAsmOperand*> &);
189 bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
190 const SmallVectorImpl<MCParsedAsmOperand*> &);
191 bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
192 const SmallVectorImpl<MCParsedAsmOperand*> &);
193 bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
194 const SmallVectorImpl<MCParsedAsmOperand*> &);
195 bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
196 const SmallVectorImpl<MCParsedAsmOperand*> &);
197 bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
198 const SmallVectorImpl<MCParsedAsmOperand*> &);
199 bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
200 const SmallVectorImpl<MCParsedAsmOperand*> &);
201 bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
202 const SmallVectorImpl<MCParsedAsmOperand*> &);
203 bool cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
204 const SmallVectorImpl<MCParsedAsmOperand*> &);
205 bool cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
206 const SmallVectorImpl<MCParsedAsmOperand*> &);
207 bool cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
208 const SmallVectorImpl<MCParsedAsmOperand*> &);
209 bool cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
210 const SmallVectorImpl<MCParsedAsmOperand*> &);
212 bool validateInstruction(MCInst &Inst,
213 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
214 bool processInstruction(MCInst &Inst,
215 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
216 bool shouldOmitCCOutOperand(StringRef Mnemonic,
217 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
220 enum ARMMatchResultTy {
221 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
222 Match_RequiresNotITBlock,
227 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
228 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
229 MCAsmParserExtension::Initialize(_Parser);
231 // Initialize the set of available features.
232 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
234 // Not in an ITBlock to start with.
235 ITState.CurPosition = ~0U;
238 // Implementation of the MCTargetAsmParser interface:
239 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
240 bool ParseInstruction(StringRef Name, SMLoc NameLoc,
241 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
242 bool ParseDirective(AsmToken DirectiveID);
244 unsigned checkTargetMatchPredicate(MCInst &Inst);
246 bool MatchAndEmitInstruction(SMLoc IDLoc,
247 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
250 } // end anonymous namespace
254 /// ARMOperand - Instances of this class represent a parsed ARM machine
256 class ARMOperand : public MCParsedAsmOperand {
277 k_VectorListAllLanes,
282 k_BitfieldDescriptor,
286 SMLoc StartLoc, EndLoc;
287 SmallVector<unsigned, 8> Registers;
291 ARMCC::CondCodes Val;
311 ARM_PROC::IFlags Val;
327 // A vector register list is a sequential list of 1 to 4 registers.
342 unsigned Val; // encoded 8-bit representation
345 /// Combined record for all forms of ARM address expressions.
348 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
350 const MCConstantExpr *OffsetImm; // Offset immediate value
351 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
352 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
353 unsigned ShiftImm; // shift for OffsetReg.
354 unsigned Alignment; // 0 = no alignment specified
355 // n = alignment in bytes (8, 16, or 32)
356 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
362 ARM_AM::ShiftOpc ShiftTy;
371 ARM_AM::ShiftOpc ShiftTy;
377 ARM_AM::ShiftOpc ShiftTy;
390 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
392 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
394 StartLoc = o.StartLoc;
411 case k_DPRRegisterList:
412 case k_SPRRegisterList:
413 Registers = o.Registers;
416 case k_VectorListAllLanes:
417 VectorList = o.VectorList;
424 CoprocOption = o.CoprocOption;
432 case k_MemBarrierOpt:
438 case k_PostIndexRegister:
439 PostIdxReg = o.PostIdxReg;
447 case k_ShifterImmediate:
448 ShifterImm = o.ShifterImm;
450 case k_ShiftedRegister:
451 RegShiftedReg = o.RegShiftedReg;
453 case k_ShiftedImmediate:
454 RegShiftedImm = o.RegShiftedImm;
456 case k_RotateImmediate:
459 case k_BitfieldDescriptor:
460 Bitfield = o.Bitfield;
463 VectorIndex = o.VectorIndex;
468 /// getStartLoc - Get the location of the first token of this operand.
469 SMLoc getStartLoc() const { return StartLoc; }
470 /// getEndLoc - Get the location of the last token of this operand.
471 SMLoc getEndLoc() const { return EndLoc; }
473 ARMCC::CondCodes getCondCode() const {
474 assert(Kind == k_CondCode && "Invalid access!");
478 unsigned getCoproc() const {
479 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
483 StringRef getToken() const {
484 assert(Kind == k_Token && "Invalid access!");
485 return StringRef(Tok.Data, Tok.Length);
488 unsigned getReg() const {
489 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
493 const SmallVectorImpl<unsigned> &getRegList() const {
494 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
495 Kind == k_SPRRegisterList) && "Invalid access!");
499 const MCExpr *getImm() const {
500 assert(Kind == k_Immediate && "Invalid access!");
504 unsigned getFPImm() const {
505 assert(Kind == k_FPImmediate && "Invalid access!");
509 unsigned getVectorIndex() const {
510 assert(Kind == k_VectorIndex && "Invalid access!");
511 return VectorIndex.Val;
514 ARM_MB::MemBOpt getMemBarrierOpt() const {
515 assert(Kind == k_MemBarrierOpt && "Invalid access!");
519 ARM_PROC::IFlags getProcIFlags() const {
520 assert(Kind == k_ProcIFlags && "Invalid access!");
524 unsigned getMSRMask() const {
525 assert(Kind == k_MSRMask && "Invalid access!");
529 bool isCoprocNum() const { return Kind == k_CoprocNum; }
530 bool isCoprocReg() const { return Kind == k_CoprocReg; }
531 bool isCoprocOption() const { return Kind == k_CoprocOption; }
532 bool isCondCode() const { return Kind == k_CondCode; }
533 bool isCCOut() const { return Kind == k_CCOut; }
534 bool isITMask() const { return Kind == k_ITCondMask; }
535 bool isITCondCode() const { return Kind == k_CondCode; }
536 bool isImm() const { return Kind == k_Immediate; }
537 bool isFPImm() const { return Kind == k_FPImmediate; }
538 bool isImm8s4() const {
539 if (Kind != k_Immediate)
541 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
542 if (!CE) return false;
543 int64_t Value = CE->getValue();
544 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
546 bool isImm0_1020s4() const {
547 if (Kind != k_Immediate)
549 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
550 if (!CE) return false;
551 int64_t Value = CE->getValue();
552 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
554 bool isImm0_508s4() const {
555 if (Kind != k_Immediate)
557 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
558 if (!CE) return false;
559 int64_t Value = CE->getValue();
560 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
562 bool isImm0_255() const {
563 if (Kind != k_Immediate)
565 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
566 if (!CE) return false;
567 int64_t Value = CE->getValue();
568 return Value >= 0 && Value < 256;
570 bool isImm0_7() const {
571 if (Kind != k_Immediate)
573 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
574 if (!CE) return false;
575 int64_t Value = CE->getValue();
576 return Value >= 0 && Value < 8;
578 bool isImm0_15() const {
579 if (Kind != k_Immediate)
581 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
582 if (!CE) return false;
583 int64_t Value = CE->getValue();
584 return Value >= 0 && Value < 16;
586 bool isImm0_31() const {
587 if (Kind != k_Immediate)
589 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
590 if (!CE) return false;
591 int64_t Value = CE->getValue();
592 return Value >= 0 && Value < 32;
594 bool isImm1_16() const {
595 if (Kind != k_Immediate)
597 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
598 if (!CE) return false;
599 int64_t Value = CE->getValue();
600 return Value > 0 && Value < 17;
602 bool isImm1_32() const {
603 if (Kind != k_Immediate)
605 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
606 if (!CE) return false;
607 int64_t Value = CE->getValue();
608 return Value > 0 && Value < 33;
610 bool isImm0_32() const {
611 if (Kind != k_Immediate)
613 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
614 if (!CE) return false;
615 int64_t Value = CE->getValue();
616 return Value >= 0 && Value < 33;
618 bool isImm0_65535() const {
619 if (Kind != k_Immediate)
621 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
622 if (!CE) return false;
623 int64_t Value = CE->getValue();
624 return Value >= 0 && Value < 65536;
626 bool isImm0_65535Expr() const {
627 if (Kind != k_Immediate)
629 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
630 // If it's not a constant expression, it'll generate a fixup and be
632 if (!CE) return true;
633 int64_t Value = CE->getValue();
634 return Value >= 0 && Value < 65536;
636 bool isImm24bit() const {
637 if (Kind != k_Immediate)
639 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
640 if (!CE) return false;
641 int64_t Value = CE->getValue();
642 return Value >= 0 && Value <= 0xffffff;
644 bool isImmThumbSR() const {
645 if (Kind != k_Immediate)
647 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
648 if (!CE) return false;
649 int64_t Value = CE->getValue();
650 return Value > 0 && Value < 33;
652 bool isPKHLSLImm() const {
653 if (Kind != k_Immediate)
655 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
656 if (!CE) return false;
657 int64_t Value = CE->getValue();
658 return Value >= 0 && Value < 32;
660 bool isPKHASRImm() const {
661 if (Kind != k_Immediate)
663 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
664 if (!CE) return false;
665 int64_t Value = CE->getValue();
666 return Value > 0 && Value <= 32;
668 bool isARMSOImm() const {
669 if (Kind != k_Immediate)
671 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
672 if (!CE) return false;
673 int64_t Value = CE->getValue();
674 return ARM_AM::getSOImmVal(Value) != -1;
676 bool isARMSOImmNot() const {
677 if (Kind != k_Immediate)
679 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
680 if (!CE) return false;
681 int64_t Value = CE->getValue();
682 return ARM_AM::getSOImmVal(~Value) != -1;
684 bool isT2SOImm() const {
685 if (Kind != k_Immediate)
687 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
688 if (!CE) return false;
689 int64_t Value = CE->getValue();
690 return ARM_AM::getT2SOImmVal(Value) != -1;
692 bool isT2SOImmNot() const {
693 if (Kind != k_Immediate)
695 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
696 if (!CE) return false;
697 int64_t Value = CE->getValue();
698 return ARM_AM::getT2SOImmVal(~Value) != -1;
700 bool isSetEndImm() const {
701 if (Kind != k_Immediate)
703 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
704 if (!CE) return false;
705 int64_t Value = CE->getValue();
706 return Value == 1 || Value == 0;
708 bool isReg() const { return Kind == k_Register; }
709 bool isRegList() const { return Kind == k_RegisterList; }
710 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
711 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
712 bool isToken() const { return Kind == k_Token; }
713 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
714 bool isMemory() const { return Kind == k_Memory; }
715 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
716 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
717 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
718 bool isRotImm() const { return Kind == k_RotateImmediate; }
719 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
720 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
721 bool isPostIdxReg() const {
722 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
724 bool isMemNoOffset(bool alignOK = false) const {
727 // No offset of any kind.
728 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
729 (alignOK || Memory.Alignment == 0);
731 bool isAlignedMemory() const {
732 return isMemNoOffset(true);
734 bool isAddrMode2() const {
735 if (!isMemory() || Memory.Alignment != 0) return false;
736 // Check for register offset.
737 if (Memory.OffsetRegNum) return true;
738 // Immediate offset in range [-4095, 4095].
739 if (!Memory.OffsetImm) return true;
740 int64_t Val = Memory.OffsetImm->getValue();
741 return Val > -4096 && Val < 4096;
743 bool isAM2OffsetImm() const {
744 if (Kind != k_Immediate)
746 // Immediate offset in range [-4095, 4095].
747 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
748 if (!CE) return false;
749 int64_t Val = CE->getValue();
750 return Val > -4096 && Val < 4096;
752 bool isAddrMode3() const {
753 if (!isMemory() || Memory.Alignment != 0) return false;
754 // No shifts are legal for AM3.
755 if (Memory.ShiftType != ARM_AM::no_shift) return false;
756 // Check for register offset.
757 if (Memory.OffsetRegNum) return true;
758 // Immediate offset in range [-255, 255].
759 if (!Memory.OffsetImm) return true;
760 int64_t Val = Memory.OffsetImm->getValue();
761 return Val > -256 && Val < 256;
763 bool isAM3Offset() const {
764 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
766 if (Kind == k_PostIndexRegister)
767 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
768 // Immediate offset in range [-255, 255].
769 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
770 if (!CE) return false;
771 int64_t Val = CE->getValue();
772 // Special case, #-0 is INT32_MIN.
773 return (Val > -256 && Val < 256) || Val == INT32_MIN;
775 bool isAddrMode5() const {
776 // If we have an immediate that's not a constant, treat it as a label
777 // reference needing a fixup. If it is a constant, it's something else
779 if (Kind == k_Immediate && !isa<MCConstantExpr>(getImm()))
781 if (!isMemory() || Memory.Alignment != 0) return false;
782 // Check for register offset.
783 if (Memory.OffsetRegNum) return false;
784 // Immediate offset in range [-1020, 1020] and a multiple of 4.
785 if (!Memory.OffsetImm) return true;
786 int64_t Val = Memory.OffsetImm->getValue();
787 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
790 bool isMemTBB() const {
791 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
792 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
796 bool isMemTBH() const {
797 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
798 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
799 Memory.Alignment != 0 )
803 bool isMemRegOffset() const {
804 if (!isMemory() || !Memory.OffsetRegNum || Memory.Alignment != 0)
808 bool isT2MemRegOffset() const {
809 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
810 Memory.Alignment != 0)
812 // Only lsl #{0, 1, 2, 3} allowed.
813 if (Memory.ShiftType == ARM_AM::no_shift)
815 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
819 bool isMemThumbRR() const {
820 // Thumb reg+reg addressing is simple. Just two registers, a base and
821 // an offset. No shifts, negations or any other complicating factors.
822 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
823 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
825 return isARMLowRegister(Memory.BaseRegNum) &&
826 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
828 bool isMemThumbRIs4() const {
829 if (!isMemory() || Memory.OffsetRegNum != 0 ||
830 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
832 // Immediate offset, multiple of 4 in range [0, 124].
833 if (!Memory.OffsetImm) return true;
834 int64_t Val = Memory.OffsetImm->getValue();
835 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
837 bool isMemThumbRIs2() const {
838 if (!isMemory() || Memory.OffsetRegNum != 0 ||
839 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
841 // Immediate offset, multiple of 4 in range [0, 62].
842 if (!Memory.OffsetImm) return true;
843 int64_t Val = Memory.OffsetImm->getValue();
844 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
846 bool isMemThumbRIs1() const {
847 if (!isMemory() || Memory.OffsetRegNum != 0 ||
848 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
850 // Immediate offset in range [0, 31].
851 if (!Memory.OffsetImm) return true;
852 int64_t Val = Memory.OffsetImm->getValue();
853 return Val >= 0 && Val <= 31;
855 bool isMemThumbSPI() const {
856 if (!isMemory() || Memory.OffsetRegNum != 0 ||
857 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
859 // Immediate offset, multiple of 4 in range [0, 1020].
860 if (!Memory.OffsetImm) return true;
861 int64_t Val = Memory.OffsetImm->getValue();
862 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
864 bool isMemImm8s4Offset() const {
865 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
867 // Immediate offset a multiple of 4 in range [-1020, 1020].
868 if (!Memory.OffsetImm) return true;
869 int64_t Val = Memory.OffsetImm->getValue();
870 return Val >= -1020 && Val <= 1020 && (Val & 3) == 0;
872 bool isMemImm0_1020s4Offset() const {
873 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
875 // Immediate offset a multiple of 4 in range [0, 1020].
876 if (!Memory.OffsetImm) return true;
877 int64_t Val = Memory.OffsetImm->getValue();
878 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
880 bool isMemImm8Offset() const {
881 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
883 // Immediate offset in range [-255, 255].
884 if (!Memory.OffsetImm) return true;
885 int64_t Val = Memory.OffsetImm->getValue();
886 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
888 bool isMemPosImm8Offset() const {
889 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
891 // Immediate offset in range [0, 255].
892 if (!Memory.OffsetImm) return true;
893 int64_t Val = Memory.OffsetImm->getValue();
894 return Val >= 0 && Val < 256;
896 bool isMemNegImm8Offset() const {
897 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
899 // Immediate offset in range [-255, -1].
900 if (!Memory.OffsetImm) return true;
901 int64_t Val = Memory.OffsetImm->getValue();
902 return Val > -256 && Val < 0;
904 bool isMemUImm12Offset() const {
905 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
907 // Immediate offset in range [0, 4095].
908 if (!Memory.OffsetImm) return true;
909 int64_t Val = Memory.OffsetImm->getValue();
910 return (Val >= 0 && Val < 4096);
912 bool isMemImm12Offset() const {
913 // If we have an immediate that's not a constant, treat it as a label
914 // reference needing a fixup. If it is a constant, it's something else
916 if (Kind == k_Immediate && !isa<MCConstantExpr>(getImm()))
919 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
921 // Immediate offset in range [-4095, 4095].
922 if (!Memory.OffsetImm) return true;
923 int64_t Val = Memory.OffsetImm->getValue();
924 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
926 bool isPostIdxImm8() const {
927 if (Kind != k_Immediate)
929 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
930 if (!CE) return false;
931 int64_t Val = CE->getValue();
932 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
934 bool isPostIdxImm8s4() const {
935 if (Kind != k_Immediate)
937 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
938 if (!CE) return false;
939 int64_t Val = CE->getValue();
940 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
944 bool isMSRMask() const { return Kind == k_MSRMask; }
945 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
948 bool isVecListOneD() const {
949 if (Kind != k_VectorList) return false;
950 return VectorList.Count == 1;
953 bool isVecListTwoD() const {
954 if (Kind != k_VectorList) return false;
955 return VectorList.Count == 2;
958 bool isVecListThreeD() const {
959 if (Kind != k_VectorList) return false;
960 return VectorList.Count == 3;
963 bool isVecListFourD() const {
964 if (Kind != k_VectorList) return false;
965 return VectorList.Count == 4;
968 bool isVecListTwoQ() const {
969 if (Kind != k_VectorList) return false;
970 //FIXME: We haven't taught the parser to handle by-two register lists
971 // yet, so don't pretend to know one.
972 return VectorList.Count == 2 && false;
975 bool isVecListOneDAllLanes() const {
976 if (Kind != k_VectorListAllLanes) return false;
977 return VectorList.Count == 1;
980 bool isVecListTwoDAllLanes() const {
981 if (Kind != k_VectorListAllLanes) return false;
982 return VectorList.Count == 2;
985 bool isVectorIndex8() const {
986 if (Kind != k_VectorIndex) return false;
987 return VectorIndex.Val < 8;
989 bool isVectorIndex16() const {
990 if (Kind != k_VectorIndex) return false;
991 return VectorIndex.Val < 4;
993 bool isVectorIndex32() const {
994 if (Kind != k_VectorIndex) return false;
995 return VectorIndex.Val < 2;
998 bool isNEONi8splat() const {
999 if (Kind != k_Immediate)
1001 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1002 // Must be a constant.
1003 if (!CE) return false;
1004 int64_t Value = CE->getValue();
1005 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1007 return Value >= 0 && Value < 256;
1010 bool isNEONi16splat() const {
1011 if (Kind != k_Immediate)
1013 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1014 // Must be a constant.
1015 if (!CE) return false;
1016 int64_t Value = CE->getValue();
1017 // i16 value in the range [0,255] or [0x0100, 0xff00]
1018 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1021 bool isNEONi32splat() const {
1022 if (Kind != k_Immediate)
1024 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1025 // Must be a constant.
1026 if (!CE) return false;
1027 int64_t Value = CE->getValue();
1028 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1029 return (Value >= 0 && Value < 256) ||
1030 (Value >= 0x0100 && Value <= 0xff00) ||
1031 (Value >= 0x010000 && Value <= 0xff0000) ||
1032 (Value >= 0x01000000 && Value <= 0xff000000);
1035 bool isNEONi32vmov() const {
1036 if (Kind != k_Immediate)
1038 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1039 // Must be a constant.
1040 if (!CE) return false;
1041 int64_t Value = CE->getValue();
1042 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1043 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1044 return (Value >= 0 && Value < 256) ||
1045 (Value >= 0x0100 && Value <= 0xff00) ||
1046 (Value >= 0x010000 && Value <= 0xff0000) ||
1047 (Value >= 0x01000000 && Value <= 0xff000000) ||
1048 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1049 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1052 bool isNEONi64splat() const {
1053 if (Kind != k_Immediate)
1055 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1056 // Must be a constant.
1057 if (!CE) return false;
1058 uint64_t Value = CE->getValue();
1059 // i64 value with each byte being either 0 or 0xff.
1060 for (unsigned i = 0; i < 8; ++i)
1061 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1065 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1066 // Add as immediates when possible. Null MCExpr = 0.
1068 Inst.addOperand(MCOperand::CreateImm(0));
1069 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1070 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1072 Inst.addOperand(MCOperand::CreateExpr(Expr));
1075 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1076 assert(N == 2 && "Invalid number of operands!");
1077 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1078 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1079 Inst.addOperand(MCOperand::CreateReg(RegNum));
1082 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1083 assert(N == 1 && "Invalid number of operands!");
1084 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1087 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1088 assert(N == 1 && "Invalid number of operands!");
1089 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1092 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1093 assert(N == 1 && "Invalid number of operands!");
1094 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1097 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1098 assert(N == 1 && "Invalid number of operands!");
1099 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1102 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1103 assert(N == 1 && "Invalid number of operands!");
1104 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1107 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1108 assert(N == 1 && "Invalid number of operands!");
1109 Inst.addOperand(MCOperand::CreateReg(getReg()));
1112 void addRegOperands(MCInst &Inst, unsigned N) const {
1113 assert(N == 1 && "Invalid number of operands!");
1114 Inst.addOperand(MCOperand::CreateReg(getReg()));
1117 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1118 assert(N == 3 && "Invalid number of operands!");
1119 assert(isRegShiftedReg() &&
1120 "addRegShiftedRegOperands() on non RegShiftedReg!");
1121 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1122 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1123 Inst.addOperand(MCOperand::CreateImm(
1124 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1127 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1128 assert(N == 2 && "Invalid number of operands!");
1129 assert(isRegShiftedImm() &&
1130 "addRegShiftedImmOperands() on non RegShiftedImm!");
1131 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1132 Inst.addOperand(MCOperand::CreateImm(
1133 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
1136 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1137 assert(N == 1 && "Invalid number of operands!");
1138 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1142 void addRegListOperands(MCInst &Inst, unsigned N) const {
1143 assert(N == 1 && "Invalid number of operands!");
1144 const SmallVectorImpl<unsigned> &RegList = getRegList();
1145 for (SmallVectorImpl<unsigned>::const_iterator
1146 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1147 Inst.addOperand(MCOperand::CreateReg(*I));
1150 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1151 addRegListOperands(Inst, N);
1154 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1155 addRegListOperands(Inst, N);
1158 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1159 assert(N == 1 && "Invalid number of operands!");
1160 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1161 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1164 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1165 assert(N == 1 && "Invalid number of operands!");
1166 // Munge the lsb/width into a bitfield mask.
1167 unsigned lsb = Bitfield.LSB;
1168 unsigned width = Bitfield.Width;
1169 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1170 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1171 (32 - (lsb + width)));
1172 Inst.addOperand(MCOperand::CreateImm(Mask));
1175 void addImmOperands(MCInst &Inst, unsigned N) const {
1176 assert(N == 1 && "Invalid number of operands!");
1177 addExpr(Inst, getImm());
1180 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1181 assert(N == 1 && "Invalid number of operands!");
1182 Inst.addOperand(MCOperand::CreateImm(getFPImm()));
1185 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1186 assert(N == 1 && "Invalid number of operands!");
1187 // FIXME: We really want to scale the value here, but the LDRD/STRD
1188 // instruction don't encode operands that way yet.
1189 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1190 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1193 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1194 assert(N == 1 && "Invalid number of operands!");
1195 // The immediate is scaled by four in the encoding and is stored
1196 // in the MCInst as such. Lop off the low two bits here.
1197 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1198 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1201 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1202 assert(N == 1 && "Invalid number of operands!");
1203 // The immediate is scaled by four in the encoding and is stored
1204 // in the MCInst as such. Lop off the low two bits here.
1205 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1206 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1209 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1210 assert(N == 1 && "Invalid number of operands!");
1211 // The constant encodes as the immediate-1, and we store in the instruction
1212 // the bits as encoded, so subtract off one here.
1213 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1214 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1217 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1218 assert(N == 1 && "Invalid number of operands!");
1219 // The constant encodes as the immediate-1, and we store in the instruction
1220 // the bits as encoded, so subtract off one here.
1221 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1222 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1225 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1226 assert(N == 1 && "Invalid number of operands!");
1227 // The constant encodes as the immediate, except for 32, which encodes as
1229 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1230 unsigned Imm = CE->getValue();
1231 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1234 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1235 assert(N == 1 && "Invalid number of operands!");
1236 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1237 // the instruction as well.
1238 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1239 int Val = CE->getValue();
1240 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1243 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1244 assert(N == 1 && "Invalid number of operands!");
1245 // The operand is actually a t2_so_imm, but we have its bitwise
1246 // negation in the assembly source, so twiddle it here.
1247 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1248 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1251 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1252 assert(N == 1 && "Invalid number of operands!");
1253 // The operand is actually a so_imm, but we have its bitwise
1254 // negation in the assembly source, so twiddle it here.
1255 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1256 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1259 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1260 assert(N == 1 && "Invalid number of operands!");
1261 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1264 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1265 assert(N == 1 && "Invalid number of operands!");
1266 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1269 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1270 assert(N == 2 && "Invalid number of operands!");
1271 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1272 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1275 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1276 assert(N == 3 && "Invalid number of operands!");
1277 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1278 if (!Memory.OffsetRegNum) {
1279 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1280 // Special case for #-0
1281 if (Val == INT32_MIN) Val = 0;
1282 if (Val < 0) Val = -Val;
1283 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1285 // For register offset, we encode the shift type and negation flag
1287 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1288 Memory.ShiftImm, Memory.ShiftType);
1290 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1291 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1292 Inst.addOperand(MCOperand::CreateImm(Val));
1295 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1296 assert(N == 2 && "Invalid number of operands!");
1297 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1298 assert(CE && "non-constant AM2OffsetImm operand!");
1299 int32_t Val = CE->getValue();
1300 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1301 // Special case for #-0
1302 if (Val == INT32_MIN) Val = 0;
1303 if (Val < 0) Val = -Val;
1304 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1305 Inst.addOperand(MCOperand::CreateReg(0));
1306 Inst.addOperand(MCOperand::CreateImm(Val));
1309 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1310 assert(N == 3 && "Invalid number of operands!");
1311 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1312 if (!Memory.OffsetRegNum) {
1313 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1314 // Special case for #-0
1315 if (Val == INT32_MIN) Val = 0;
1316 if (Val < 0) Val = -Val;
1317 Val = ARM_AM::getAM3Opc(AddSub, Val);
1319 // For register offset, we encode the shift type and negation flag
1321 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1323 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1324 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1325 Inst.addOperand(MCOperand::CreateImm(Val));
1328 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1329 assert(N == 2 && "Invalid number of operands!");
1330 if (Kind == k_PostIndexRegister) {
1332 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1333 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1334 Inst.addOperand(MCOperand::CreateImm(Val));
1339 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1340 int32_t Val = CE->getValue();
1341 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1342 // Special case for #-0
1343 if (Val == INT32_MIN) Val = 0;
1344 if (Val < 0) Val = -Val;
1345 Val = ARM_AM::getAM3Opc(AddSub, Val);
1346 Inst.addOperand(MCOperand::CreateReg(0));
1347 Inst.addOperand(MCOperand::CreateImm(Val));
1350 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1351 assert(N == 2 && "Invalid number of operands!");
1352 // If we have an immediate that's not a constant, treat it as a label
1353 // reference needing a fixup. If it is a constant, it's something else
1354 // and we reject it.
1356 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1357 Inst.addOperand(MCOperand::CreateImm(0));
1361 // The lower two bits are always zero and as such are not encoded.
1362 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1363 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1364 // Special case for #-0
1365 if (Val == INT32_MIN) Val = 0;
1366 if (Val < 0) Val = -Val;
1367 Val = ARM_AM::getAM5Opc(AddSub, Val);
1368 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1369 Inst.addOperand(MCOperand::CreateImm(Val));
1372 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1373 assert(N == 2 && "Invalid number of operands!");
1374 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1375 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1376 Inst.addOperand(MCOperand::CreateImm(Val));
1379 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1380 assert(N == 2 && "Invalid number of operands!");
1381 // The lower two bits are always zero and as such are not encoded.
1382 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1383 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1384 Inst.addOperand(MCOperand::CreateImm(Val));
1387 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1388 assert(N == 2 && "Invalid number of operands!");
1389 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1390 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1391 Inst.addOperand(MCOperand::CreateImm(Val));
1394 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1395 addMemImm8OffsetOperands(Inst, N);
1398 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1399 addMemImm8OffsetOperands(Inst, N);
1402 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1403 assert(N == 2 && "Invalid number of operands!");
1404 // If this is an immediate, it's a label reference.
1405 if (Kind == k_Immediate) {
1406 addExpr(Inst, getImm());
1407 Inst.addOperand(MCOperand::CreateImm(0));
1411 // Otherwise, it's a normal memory reg+offset.
1412 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1413 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1414 Inst.addOperand(MCOperand::CreateImm(Val));
1417 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1418 assert(N == 2 && "Invalid number of operands!");
1419 // If this is an immediate, it's a label reference.
1420 if (Kind == k_Immediate) {
1421 addExpr(Inst, getImm());
1422 Inst.addOperand(MCOperand::CreateImm(0));
1426 // Otherwise, it's a normal memory reg+offset.
1427 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1428 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1429 Inst.addOperand(MCOperand::CreateImm(Val));
1432 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1433 assert(N == 2 && "Invalid number of operands!");
1434 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1435 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1438 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
1439 assert(N == 2 && "Invalid number of operands!");
1440 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1441 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1444 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1445 assert(N == 3 && "Invalid number of operands!");
1447 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1448 Memory.ShiftImm, Memory.ShiftType);
1449 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1450 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1451 Inst.addOperand(MCOperand::CreateImm(Val));
1454 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1455 assert(N == 3 && "Invalid number of operands!");
1456 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1457 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1458 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
1461 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1462 assert(N == 2 && "Invalid number of operands!");
1463 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1464 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1467 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1468 assert(N == 2 && "Invalid number of operands!");
1469 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1470 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1471 Inst.addOperand(MCOperand::CreateImm(Val));
1474 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1475 assert(N == 2 && "Invalid number of operands!");
1476 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
1477 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1478 Inst.addOperand(MCOperand::CreateImm(Val));
1481 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1482 assert(N == 2 && "Invalid number of operands!");
1483 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
1484 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1485 Inst.addOperand(MCOperand::CreateImm(Val));
1488 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1489 assert(N == 2 && "Invalid number of operands!");
1490 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1491 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1492 Inst.addOperand(MCOperand::CreateImm(Val));
1495 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1496 assert(N == 1 && "Invalid number of operands!");
1497 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1498 assert(CE && "non-constant post-idx-imm8 operand!");
1499 int Imm = CE->getValue();
1500 bool isAdd = Imm >= 0;
1501 if (Imm == INT32_MIN) Imm = 0;
1502 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1503 Inst.addOperand(MCOperand::CreateImm(Imm));
1506 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
1507 assert(N == 1 && "Invalid number of operands!");
1508 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1509 assert(CE && "non-constant post-idx-imm8s4 operand!");
1510 int Imm = CE->getValue();
1511 bool isAdd = Imm >= 0;
1512 if (Imm == INT32_MIN) Imm = 0;
1513 // Immediate is scaled by 4.
1514 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
1515 Inst.addOperand(MCOperand::CreateImm(Imm));
1518 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1519 assert(N == 2 && "Invalid number of operands!");
1520 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1521 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1524 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1525 assert(N == 2 && "Invalid number of operands!");
1526 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1527 // The sign, shift type, and shift amount are encoded in a single operand
1528 // using the AM2 encoding helpers.
1529 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1530 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1531 PostIdxReg.ShiftTy);
1532 Inst.addOperand(MCOperand::CreateImm(Imm));
1535 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1536 assert(N == 1 && "Invalid number of operands!");
1537 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1540 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1541 assert(N == 1 && "Invalid number of operands!");
1542 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1545 void addVecListOperands(MCInst &Inst, unsigned N) const {
1546 assert(N == 1 && "Invalid number of operands!");
1547 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1550 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
1551 assert(N == 1 && "Invalid number of operands!");
1552 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1555 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
1556 assert(N == 1 && "Invalid number of operands!");
1557 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1560 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
1561 assert(N == 1 && "Invalid number of operands!");
1562 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1565 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
1566 assert(N == 1 && "Invalid number of operands!");
1567 // The immediate encodes the type of constant as well as the value.
1568 // Mask in that this is an i8 splat.
1569 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1570 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
1573 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
1574 assert(N == 1 && "Invalid number of operands!");
1575 // The immediate encodes the type of constant as well as the value.
1576 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1577 unsigned Value = CE->getValue();
1579 Value = (Value >> 8) | 0xa00;
1582 Inst.addOperand(MCOperand::CreateImm(Value));
1585 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
1586 assert(N == 1 && "Invalid number of operands!");
1587 // The immediate encodes the type of constant as well as the value.
1588 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1589 unsigned Value = CE->getValue();
1590 if (Value >= 256 && Value <= 0xff00)
1591 Value = (Value >> 8) | 0x200;
1592 else if (Value > 0xffff && Value <= 0xff0000)
1593 Value = (Value >> 16) | 0x400;
1594 else if (Value > 0xffffff)
1595 Value = (Value >> 24) | 0x600;
1596 Inst.addOperand(MCOperand::CreateImm(Value));
1599 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
1600 assert(N == 1 && "Invalid number of operands!");
1601 // The immediate encodes the type of constant as well as the value.
1602 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1603 unsigned Value = CE->getValue();
1604 if (Value >= 256 && Value <= 0xffff)
1605 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
1606 else if (Value > 0xffff && Value <= 0xffffff)
1607 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
1608 else if (Value > 0xffffff)
1609 Value = (Value >> 24) | 0x600;
1610 Inst.addOperand(MCOperand::CreateImm(Value));
1613 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
1614 assert(N == 1 && "Invalid number of operands!");
1615 // The immediate encodes the type of constant as well as the value.
1616 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1617 uint64_t Value = CE->getValue();
1619 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
1620 Imm |= (Value & 1) << i;
1622 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
1625 virtual void print(raw_ostream &OS) const;
1627 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
1628 ARMOperand *Op = new ARMOperand(k_ITCondMask);
1629 Op->ITMask.Mask = Mask;
1635 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1636 ARMOperand *Op = new ARMOperand(k_CondCode);
1643 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1644 ARMOperand *Op = new ARMOperand(k_CoprocNum);
1645 Op->Cop.Val = CopVal;
1651 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1652 ARMOperand *Op = new ARMOperand(k_CoprocReg);
1653 Op->Cop.Val = CopVal;
1659 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
1660 ARMOperand *Op = new ARMOperand(k_CoprocOption);
1667 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1668 ARMOperand *Op = new ARMOperand(k_CCOut);
1669 Op->Reg.RegNum = RegNum;
1675 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1676 ARMOperand *Op = new ARMOperand(k_Token);
1677 Op->Tok.Data = Str.data();
1678 Op->Tok.Length = Str.size();
1684 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1685 ARMOperand *Op = new ARMOperand(k_Register);
1686 Op->Reg.RegNum = RegNum;
1692 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1697 ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
1698 Op->RegShiftedReg.ShiftTy = ShTy;
1699 Op->RegShiftedReg.SrcReg = SrcReg;
1700 Op->RegShiftedReg.ShiftReg = ShiftReg;
1701 Op->RegShiftedReg.ShiftImm = ShiftImm;
1707 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1711 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
1712 Op->RegShiftedImm.ShiftTy = ShTy;
1713 Op->RegShiftedImm.SrcReg = SrcReg;
1714 Op->RegShiftedImm.ShiftImm = ShiftImm;
1720 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1722 ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
1723 Op->ShifterImm.isASR = isASR;
1724 Op->ShifterImm.Imm = Imm;
1730 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1731 ARMOperand *Op = new ARMOperand(k_RotateImmediate);
1732 Op->RotImm.Imm = Imm;
1738 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1740 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
1741 Op->Bitfield.LSB = LSB;
1742 Op->Bitfield.Width = Width;
1749 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1750 SMLoc StartLoc, SMLoc EndLoc) {
1751 KindTy Kind = k_RegisterList;
1753 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
1754 Kind = k_DPRRegisterList;
1755 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
1756 contains(Regs.front().first))
1757 Kind = k_SPRRegisterList;
1759 ARMOperand *Op = new ARMOperand(Kind);
1760 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1761 I = Regs.begin(), E = Regs.end(); I != E; ++I)
1762 Op->Registers.push_back(I->first);
1763 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1764 Op->StartLoc = StartLoc;
1765 Op->EndLoc = EndLoc;
1769 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
1771 ARMOperand *Op = new ARMOperand(k_VectorList);
1772 Op->VectorList.RegNum = RegNum;
1773 Op->VectorList.Count = Count;
1779 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
1781 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
1782 Op->VectorList.RegNum = RegNum;
1783 Op->VectorList.Count = Count;
1789 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
1791 ARMOperand *Op = new ARMOperand(k_VectorIndex);
1792 Op->VectorIndex.Val = Idx;
1798 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1799 ARMOperand *Op = new ARMOperand(k_Immediate);
1806 static ARMOperand *CreateFPImm(unsigned Val, SMLoc S, MCContext &Ctx) {
1807 ARMOperand *Op = new ARMOperand(k_FPImmediate);
1808 Op->FPImm.Val = Val;
1814 static ARMOperand *CreateMem(unsigned BaseRegNum,
1815 const MCConstantExpr *OffsetImm,
1816 unsigned OffsetRegNum,
1817 ARM_AM::ShiftOpc ShiftType,
1822 ARMOperand *Op = new ARMOperand(k_Memory);
1823 Op->Memory.BaseRegNum = BaseRegNum;
1824 Op->Memory.OffsetImm = OffsetImm;
1825 Op->Memory.OffsetRegNum = OffsetRegNum;
1826 Op->Memory.ShiftType = ShiftType;
1827 Op->Memory.ShiftImm = ShiftImm;
1828 Op->Memory.Alignment = Alignment;
1829 Op->Memory.isNegative = isNegative;
1835 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1836 ARM_AM::ShiftOpc ShiftTy,
1839 ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
1840 Op->PostIdxReg.RegNum = RegNum;
1841 Op->PostIdxReg.isAdd = isAdd;
1842 Op->PostIdxReg.ShiftTy = ShiftTy;
1843 Op->PostIdxReg.ShiftImm = ShiftImm;
1849 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1850 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
1851 Op->MBOpt.Val = Opt;
1857 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1858 ARMOperand *Op = new ARMOperand(k_ProcIFlags);
1859 Op->IFlags.Val = IFlags;
1865 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1866 ARMOperand *Op = new ARMOperand(k_MSRMask);
1867 Op->MMask.Val = MMask;
1874 } // end anonymous namespace.
1876 void ARMOperand::print(raw_ostream &OS) const {
1879 OS << "<fpimm " << getFPImm() << "(" << ARM_AM::getFPImmFloat(getFPImm())
1883 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1886 OS << "<ccout " << getReg() << ">";
1888 case k_ITCondMask: {
1889 static const char *MaskStr[] = {
1890 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
1891 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
1893 assert((ITMask.Mask & 0xf) == ITMask.Mask);
1894 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
1898 OS << "<coprocessor number: " << getCoproc() << ">";
1901 OS << "<coprocessor register: " << getCoproc() << ">";
1903 case k_CoprocOption:
1904 OS << "<coprocessor option: " << CoprocOption.Val << ">";
1907 OS << "<mask: " << getMSRMask() << ">";
1910 getImm()->print(OS);
1912 case k_MemBarrierOpt:
1913 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1917 << " base:" << Memory.BaseRegNum;
1920 case k_PostIndexRegister:
1921 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
1922 << PostIdxReg.RegNum;
1923 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1924 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1925 << PostIdxReg.ShiftImm;
1928 case k_ProcIFlags: {
1929 OS << "<ARM_PROC::";
1930 unsigned IFlags = getProcIFlags();
1931 for (int i=2; i >= 0; --i)
1932 if (IFlags & (1 << i))
1933 OS << ARM_PROC::IFlagsToString(1 << i);
1938 OS << "<register " << getReg() << ">";
1940 case k_ShifterImmediate:
1941 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1942 << " #" << ShifterImm.Imm << ">";
1944 case k_ShiftedRegister:
1945 OS << "<so_reg_reg "
1946 << RegShiftedReg.SrcReg << " "
1947 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
1948 << " " << RegShiftedReg.ShiftReg << ">";
1950 case k_ShiftedImmediate:
1951 OS << "<so_reg_imm "
1952 << RegShiftedImm.SrcReg << " "
1953 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
1954 << " #" << RegShiftedImm.ShiftImm << ">";
1956 case k_RotateImmediate:
1957 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
1959 case k_BitfieldDescriptor:
1960 OS << "<bitfield " << "lsb: " << Bitfield.LSB
1961 << ", width: " << Bitfield.Width << ">";
1963 case k_RegisterList:
1964 case k_DPRRegisterList:
1965 case k_SPRRegisterList: {
1966 OS << "<register_list ";
1968 const SmallVectorImpl<unsigned> &RegList = getRegList();
1969 for (SmallVectorImpl<unsigned>::const_iterator
1970 I = RegList.begin(), E = RegList.end(); I != E; ) {
1972 if (++I < E) OS << ", ";
1979 OS << "<vector_list " << VectorList.Count << " * "
1980 << VectorList.RegNum << ">";
1982 case k_VectorListAllLanes:
1983 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
1984 << VectorList.RegNum << ">";
1987 OS << "'" << getToken() << "'";
1990 OS << "<vectorindex " << getVectorIndex() << ">";
1995 /// @name Auto-generated Match Functions
1998 static unsigned MatchRegisterName(StringRef Name);
2002 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2003 SMLoc &StartLoc, SMLoc &EndLoc) {
2004 RegNo = tryParseRegister();
2006 return (RegNo == (unsigned)-1);
2009 /// Try to parse a register name. The token must be an Identifier when called,
2010 /// and if it is a register name the token is eaten and the register number is
2011 /// returned. Otherwise return -1.
2013 int ARMAsmParser::tryParseRegister() {
2014 const AsmToken &Tok = Parser.getTok();
2015 if (Tok.isNot(AsmToken::Identifier)) return -1;
2017 // FIXME: Validate register for the current architecture; we have to do
2018 // validation later, so maybe there is no need for this here.
2019 std::string lowerCase = Tok.getString().lower();
2020 unsigned RegNum = MatchRegisterName(lowerCase);
2022 RegNum = StringSwitch<unsigned>(lowerCase)
2023 .Case("r13", ARM::SP)
2024 .Case("r14", ARM::LR)
2025 .Case("r15", ARM::PC)
2026 .Case("ip", ARM::R12)
2029 if (!RegNum) return -1;
2031 Parser.Lex(); // Eat identifier token.
2036 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
2037 // If a recoverable error occurs, return 1. If an irrecoverable error
2038 // occurs, return -1. An irrecoverable error is one where tokens have been
2039 // consumed in the process of trying to parse the shifter (i.e., when it is
2040 // indeed a shifter operand, but malformed).
2041 int ARMAsmParser::tryParseShiftRegister(
2042 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2043 SMLoc S = Parser.getTok().getLoc();
2044 const AsmToken &Tok = Parser.getTok();
2045 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2047 std::string lowerCase = Tok.getString().lower();
2048 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2049 .Case("lsl", ARM_AM::lsl)
2050 .Case("lsr", ARM_AM::lsr)
2051 .Case("asr", ARM_AM::asr)
2052 .Case("ror", ARM_AM::ror)
2053 .Case("rrx", ARM_AM::rrx)
2054 .Default(ARM_AM::no_shift);
2056 if (ShiftTy == ARM_AM::no_shift)
2059 Parser.Lex(); // Eat the operator.
2061 // The source register for the shift has already been added to the
2062 // operand list, so we need to pop it off and combine it into the shifted
2063 // register operand instead.
2064 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2065 if (!PrevOp->isReg())
2066 return Error(PrevOp->getStartLoc(), "shift must be of a register");
2067 int SrcReg = PrevOp->getReg();
2070 if (ShiftTy == ARM_AM::rrx) {
2071 // RRX Doesn't have an explicit shift amount. The encoder expects
2072 // the shift register to be the same as the source register. Seems odd,
2076 // Figure out if this is shifted by a constant or a register (for non-RRX).
2077 if (Parser.getTok().is(AsmToken::Hash)) {
2078 Parser.Lex(); // Eat hash.
2079 SMLoc ImmLoc = Parser.getTok().getLoc();
2080 const MCExpr *ShiftExpr = 0;
2081 if (getParser().ParseExpression(ShiftExpr)) {
2082 Error(ImmLoc, "invalid immediate shift value");
2085 // The expression must be evaluatable as an immediate.
2086 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2088 Error(ImmLoc, "invalid immediate shift value");
2091 // Range check the immediate.
2092 // lsl, ror: 0 <= imm <= 31
2093 // lsr, asr: 0 <= imm <= 32
2094 Imm = CE->getValue();
2096 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2097 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2098 Error(ImmLoc, "immediate shift value out of range");
2101 } else if (Parser.getTok().is(AsmToken::Identifier)) {
2102 ShiftReg = tryParseRegister();
2103 SMLoc L = Parser.getTok().getLoc();
2104 if (ShiftReg == -1) {
2105 Error (L, "expected immediate or register in shift operand");
2109 Error (Parser.getTok().getLoc(),
2110 "expected immediate or register in shift operand");
2115 if (ShiftReg && ShiftTy != ARM_AM::rrx)
2116 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2118 S, Parser.getTok().getLoc()));
2120 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2121 S, Parser.getTok().getLoc()));
2127 /// Try to parse a register name. The token must be an Identifier when called.
2128 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
2129 /// if there is a "writeback". 'true' if it's not a register.
2131 /// TODO this is likely to change to allow different register types and or to
2132 /// parse for a specific register type.
2134 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2135 SMLoc S = Parser.getTok().getLoc();
2136 int RegNo = tryParseRegister();
2140 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
2142 const AsmToken &ExclaimTok = Parser.getTok();
2143 if (ExclaimTok.is(AsmToken::Exclaim)) {
2144 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2145 ExclaimTok.getLoc()));
2146 Parser.Lex(); // Eat exclaim token
2150 // Also check for an index operand. This is only legal for vector registers,
2151 // but that'll get caught OK in operand matching, so we don't need to
2152 // explicitly filter everything else out here.
2153 if (Parser.getTok().is(AsmToken::LBrac)) {
2154 SMLoc SIdx = Parser.getTok().getLoc();
2155 Parser.Lex(); // Eat left bracket token.
2157 const MCExpr *ImmVal;
2158 if (getParser().ParseExpression(ImmVal))
2159 return MatchOperand_ParseFail;
2160 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2162 TokError("immediate value expected for vector index");
2163 return MatchOperand_ParseFail;
2166 SMLoc E = Parser.getTok().getLoc();
2167 if (Parser.getTok().isNot(AsmToken::RBrac)) {
2168 Error(E, "']' expected");
2169 return MatchOperand_ParseFail;
2172 Parser.Lex(); // Eat right bracket token.
2174 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2182 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
2183 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2185 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2186 // Use the same layout as the tablegen'erated register name matcher. Ugly,
2188 switch (Name.size()) {
2191 if (Name[0] != CoprocOp)
2208 if (Name[0] != CoprocOp || Name[1] != '1')
2212 case '0': return 10;
2213 case '1': return 11;
2214 case '2': return 12;
2215 case '3': return 13;
2216 case '4': return 14;
2217 case '5': return 15;
2225 /// parseITCondCode - Try to parse a condition code for an IT instruction.
2226 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2227 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2228 SMLoc S = Parser.getTok().getLoc();
2229 const AsmToken &Tok = Parser.getTok();
2230 if (!Tok.is(AsmToken::Identifier))
2231 return MatchOperand_NoMatch;
2232 unsigned CC = StringSwitch<unsigned>(Tok.getString())
2233 .Case("eq", ARMCC::EQ)
2234 .Case("ne", ARMCC::NE)
2235 .Case("hs", ARMCC::HS)
2236 .Case("cs", ARMCC::HS)
2237 .Case("lo", ARMCC::LO)
2238 .Case("cc", ARMCC::LO)
2239 .Case("mi", ARMCC::MI)
2240 .Case("pl", ARMCC::PL)
2241 .Case("vs", ARMCC::VS)
2242 .Case("vc", ARMCC::VC)
2243 .Case("hi", ARMCC::HI)
2244 .Case("ls", ARMCC::LS)
2245 .Case("ge", ARMCC::GE)
2246 .Case("lt", ARMCC::LT)
2247 .Case("gt", ARMCC::GT)
2248 .Case("le", ARMCC::LE)
2249 .Case("al", ARMCC::AL)
2252 return MatchOperand_NoMatch;
2253 Parser.Lex(); // Eat the token.
2255 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2257 return MatchOperand_Success;
2260 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2261 /// token must be an Identifier when called, and if it is a coprocessor
2262 /// number, the token is eaten and the operand is added to the operand list.
2263 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2264 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2265 SMLoc S = Parser.getTok().getLoc();
2266 const AsmToken &Tok = Parser.getTok();
2267 if (Tok.isNot(AsmToken::Identifier))
2268 return MatchOperand_NoMatch;
2270 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2272 return MatchOperand_NoMatch;
2274 Parser.Lex(); // Eat identifier token.
2275 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2276 return MatchOperand_Success;
2279 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2280 /// token must be an Identifier when called, and if it is a coprocessor
2281 /// number, the token is eaten and the operand is added to the operand list.
2282 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2283 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2284 SMLoc S = Parser.getTok().getLoc();
2285 const AsmToken &Tok = Parser.getTok();
2286 if (Tok.isNot(AsmToken::Identifier))
2287 return MatchOperand_NoMatch;
2289 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2291 return MatchOperand_NoMatch;
2293 Parser.Lex(); // Eat identifier token.
2294 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2295 return MatchOperand_Success;
2298 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2299 /// coproc_option : '{' imm0_255 '}'
2300 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2301 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2302 SMLoc S = Parser.getTok().getLoc();
2304 // If this isn't a '{', this isn't a coprocessor immediate operand.
2305 if (Parser.getTok().isNot(AsmToken::LCurly))
2306 return MatchOperand_NoMatch;
2307 Parser.Lex(); // Eat the '{'
2310 SMLoc Loc = Parser.getTok().getLoc();
2311 if (getParser().ParseExpression(Expr)) {
2312 Error(Loc, "illegal expression");
2313 return MatchOperand_ParseFail;
2315 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2316 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2317 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2318 return MatchOperand_ParseFail;
2320 int Val = CE->getValue();
2322 // Check for and consume the closing '}'
2323 if (Parser.getTok().isNot(AsmToken::RCurly))
2324 return MatchOperand_ParseFail;
2325 SMLoc E = Parser.getTok().getLoc();
2326 Parser.Lex(); // Eat the '}'
2328 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2329 return MatchOperand_Success;
2332 // For register list parsing, we need to map from raw GPR register numbering
2333 // to the enumeration values. The enumeration values aren't sorted by
2334 // register number due to our using "sp", "lr" and "pc" as canonical names.
2335 static unsigned getNextRegister(unsigned Reg) {
2336 // If this is a GPR, we need to do it manually, otherwise we can rely
2337 // on the sort ordering of the enumeration since the other reg-classes
2339 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2342 default: assert(0 && "Invalid GPR number!");
2343 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
2344 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
2345 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
2346 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
2347 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
2348 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2349 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
2350 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
2354 // Return the low-subreg of a given Q register.
2355 static unsigned getDRegFromQReg(unsigned QReg) {
2357 default: llvm_unreachable("expected a Q register!");
2358 case ARM::Q0: return ARM::D0;
2359 case ARM::Q1: return ARM::D2;
2360 case ARM::Q2: return ARM::D4;
2361 case ARM::Q3: return ARM::D6;
2362 case ARM::Q4: return ARM::D8;
2363 case ARM::Q5: return ARM::D10;
2364 case ARM::Q6: return ARM::D12;
2365 case ARM::Q7: return ARM::D14;
2366 case ARM::Q8: return ARM::D16;
2367 case ARM::Q9: return ARM::D18;
2368 case ARM::Q10: return ARM::D20;
2369 case ARM::Q11: return ARM::D22;
2370 case ARM::Q12: return ARM::D24;
2371 case ARM::Q13: return ARM::D26;
2372 case ARM::Q14: return ARM::D28;
2373 case ARM::Q15: return ARM::D30;
2377 /// Parse a register list.
2379 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2380 assert(Parser.getTok().is(AsmToken::LCurly) &&
2381 "Token is not a Left Curly Brace");
2382 SMLoc S = Parser.getTok().getLoc();
2383 Parser.Lex(); // Eat '{' token.
2384 SMLoc RegLoc = Parser.getTok().getLoc();
2386 // Check the first register in the list to see what register class
2387 // this is a list of.
2388 int Reg = tryParseRegister();
2390 return Error(RegLoc, "register expected");
2392 // The reglist instructions have at most 16 registers, so reserve
2393 // space for that many.
2394 SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
2396 // Allow Q regs and just interpret them as the two D sub-registers.
2397 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2398 Reg = getDRegFromQReg(Reg);
2399 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2402 const MCRegisterClass *RC;
2403 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2404 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
2405 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
2406 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
2407 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
2408 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
2410 return Error(RegLoc, "invalid register in register list");
2412 // Store the register.
2413 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2415 // This starts immediately after the first register token in the list,
2416 // so we can see either a comma or a minus (range separator) as a legal
2418 while (Parser.getTok().is(AsmToken::Comma) ||
2419 Parser.getTok().is(AsmToken::Minus)) {
2420 if (Parser.getTok().is(AsmToken::Minus)) {
2421 Parser.Lex(); // Eat the minus.
2422 SMLoc EndLoc = Parser.getTok().getLoc();
2423 int EndReg = tryParseRegister();
2425 return Error(EndLoc, "register expected");
2426 // Allow Q regs and just interpret them as the two D sub-registers.
2427 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
2428 EndReg = getDRegFromQReg(EndReg) + 1;
2429 // If the register is the same as the start reg, there's nothing
2433 // The register must be in the same register class as the first.
2434 if (!RC->contains(EndReg))
2435 return Error(EndLoc, "invalid register in register list");
2436 // Ranges must go from low to high.
2437 if (getARMRegisterNumbering(Reg) > getARMRegisterNumbering(EndReg))
2438 return Error(EndLoc, "bad range in register list");
2440 // Add all the registers in the range to the register list.
2441 while (Reg != EndReg) {
2442 Reg = getNextRegister(Reg);
2443 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2447 Parser.Lex(); // Eat the comma.
2448 RegLoc = Parser.getTok().getLoc();
2450 Reg = tryParseRegister();
2452 return Error(RegLoc, "register expected");
2453 // Allow Q regs and just interpret them as the two D sub-registers.
2454 bool isQReg = false;
2455 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2456 Reg = getDRegFromQReg(Reg);
2459 // The register must be in the same register class as the first.
2460 if (!RC->contains(Reg))
2461 return Error(RegLoc, "invalid register in register list");
2462 // List must be monotonically increasing.
2463 if (getARMRegisterNumbering(Reg) <= getARMRegisterNumbering(OldReg))
2464 return Error(RegLoc, "register list not in ascending order");
2465 // VFP register lists must also be contiguous.
2466 // It's OK to use the enumeration values directly here rather, as the
2467 // VFP register classes have the enum sorted properly.
2468 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
2470 return Error(RegLoc, "non-contiguous register range");
2471 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2473 Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc));
2476 SMLoc E = Parser.getTok().getLoc();
2477 if (Parser.getTok().isNot(AsmToken::RCurly))
2478 return Error(E, "'}' expected");
2479 Parser.Lex(); // Eat '}' token.
2481 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
2485 // Helper function to parse the lane index for vector lists.
2486 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2487 parseVectorLane(VectorLaneTy &LaneKind) {
2488 if (Parser.getTok().is(AsmToken::LBrac)) {
2489 Parser.Lex(); // Eat the '['.
2490 if (Parser.getTok().is(AsmToken::RBrac)) {
2491 // "Dn[]" is the 'all lanes' syntax.
2492 LaneKind = AllLanes;
2493 Parser.Lex(); // Eat the ']'.
2494 return MatchOperand_Success;
2496 // FIXME: Other lane kinds as we add them.
2497 Error(Parser.getTok().getLoc(), "FIXME: Unexpected lane kind.");
2498 return MatchOperand_ParseFail;
2501 return MatchOperand_Success;
2504 // parse a vector register list
2505 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2506 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2507 VectorLaneTy LaneKind;
2508 SMLoc S = Parser.getTok().getLoc();
2509 // As an extension (to match gas), support a plain D register or Q register
2510 // (without encosing curly braces) as a single or double entry list,
2512 if (Parser.getTok().is(AsmToken::Identifier)) {
2513 int Reg = tryParseRegister();
2515 return MatchOperand_NoMatch;
2516 SMLoc E = Parser.getTok().getLoc();
2517 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
2518 OperandMatchResultTy Res = parseVectorLane(LaneKind);
2519 if (Res != MatchOperand_Success)
2523 assert(0 && "unexpected lane kind!");
2525 E = Parser.getTok().getLoc();
2526 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, S, E));
2529 E = Parser.getTok().getLoc();
2530 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, S, E));
2533 return MatchOperand_Success;
2535 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2536 Reg = getDRegFromQReg(Reg);
2537 OperandMatchResultTy Res = parseVectorLane(LaneKind);
2538 if (Res != MatchOperand_Success)
2542 assert(0 && "unexpected lane kind!");
2544 E = Parser.getTok().getLoc();
2545 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, S, E));
2548 E = Parser.getTok().getLoc();
2549 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, S, E));
2552 return MatchOperand_Success;
2554 Error(S, "vector register expected");
2555 return MatchOperand_ParseFail;
2558 if (Parser.getTok().isNot(AsmToken::LCurly))
2559 return MatchOperand_NoMatch;
2561 Parser.Lex(); // Eat '{' token.
2562 SMLoc RegLoc = Parser.getTok().getLoc();
2564 int Reg = tryParseRegister();
2566 Error(RegLoc, "register expected");
2567 return MatchOperand_ParseFail;
2570 unsigned FirstReg = Reg;
2571 // The list is of D registers, but we also allow Q regs and just interpret
2572 // them as the two D sub-registers.
2573 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2574 FirstReg = Reg = getDRegFromQReg(Reg);
2578 if (parseVectorLane(LaneKind) != MatchOperand_Success)
2579 return MatchOperand_ParseFail;
2581 while (Parser.getTok().is(AsmToken::Comma) ||
2582 Parser.getTok().is(AsmToken::Minus)) {
2583 if (Parser.getTok().is(AsmToken::Minus)) {
2584 Parser.Lex(); // Eat the minus.
2585 SMLoc EndLoc = Parser.getTok().getLoc();
2586 int EndReg = tryParseRegister();
2588 Error(EndLoc, "register expected");
2589 return MatchOperand_ParseFail;
2591 // Allow Q regs and just interpret them as the two D sub-registers.
2592 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
2593 EndReg = getDRegFromQReg(EndReg) + 1;
2594 // If the register is the same as the start reg, there's nothing
2598 // The register must be in the same register class as the first.
2599 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
2600 Error(EndLoc, "invalid register in register list");
2601 return MatchOperand_ParseFail;
2603 // Ranges must go from low to high.
2605 Error(EndLoc, "bad range in register list");
2606 return MatchOperand_ParseFail;
2608 // Parse the lane specifier if present.
2609 VectorLaneTy NextLaneKind;
2610 if (parseVectorLane(NextLaneKind) != MatchOperand_Success)
2611 return MatchOperand_ParseFail;
2612 if (NextLaneKind != LaneKind) {
2613 Error(EndLoc, "mismatched lane index in register list");
2614 return MatchOperand_ParseFail;
2616 EndLoc = Parser.getTok().getLoc();
2618 // Add all the registers in the range to the register list.
2619 Count += EndReg - Reg;
2623 Parser.Lex(); // Eat the comma.
2624 RegLoc = Parser.getTok().getLoc();
2626 Reg = tryParseRegister();
2628 Error(RegLoc, "register expected");
2629 return MatchOperand_ParseFail;
2631 // vector register lists must be contiguous.
2632 // It's OK to use the enumeration values directly here rather, as the
2633 // VFP register classes have the enum sorted properly.
2635 // The list is of D registers, but we also allow Q regs and just interpret
2636 // them as the two D sub-registers.
2637 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2638 Reg = getDRegFromQReg(Reg);
2639 if (Reg != OldReg + 1) {
2640 Error(RegLoc, "non-contiguous register range");
2641 return MatchOperand_ParseFail;
2645 // Parse the lane specifier if present.
2646 VectorLaneTy NextLaneKind;
2647 SMLoc EndLoc = Parser.getTok().getLoc();
2648 if (parseVectorLane(NextLaneKind) != MatchOperand_Success)
2649 return MatchOperand_ParseFail;
2650 if (NextLaneKind != LaneKind) {
2651 Error(EndLoc, "mismatched lane index in register list");
2652 return MatchOperand_ParseFail;
2656 // Normal D register. Just check that it's contiguous and keep going.
2657 if (Reg != OldReg + 1) {
2658 Error(RegLoc, "non-contiguous register range");
2659 return MatchOperand_ParseFail;
2662 // Parse the lane specifier if present.
2663 VectorLaneTy NextLaneKind;
2664 SMLoc EndLoc = Parser.getTok().getLoc();
2665 if (parseVectorLane(NextLaneKind) != MatchOperand_Success)
2666 return MatchOperand_ParseFail;
2667 if (NextLaneKind != LaneKind) {
2668 Error(EndLoc, "mismatched lane index in register list");
2669 return MatchOperand_ParseFail;
2673 SMLoc E = Parser.getTok().getLoc();
2674 if (Parser.getTok().isNot(AsmToken::RCurly)) {
2675 Error(E, "'}' expected");
2676 return MatchOperand_ParseFail;
2678 Parser.Lex(); // Eat '}' token.
2682 assert(0 && "unexpected lane kind in register list.");
2684 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, S, E));
2687 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
2691 return MatchOperand_Success;
2694 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
2695 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2696 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2697 SMLoc S = Parser.getTok().getLoc();
2698 const AsmToken &Tok = Parser.getTok();
2699 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2700 StringRef OptStr = Tok.getString();
2702 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
2703 .Case("sy", ARM_MB::SY)
2704 .Case("st", ARM_MB::ST)
2705 .Case("sh", ARM_MB::ISH)
2706 .Case("ish", ARM_MB::ISH)
2707 .Case("shst", ARM_MB::ISHST)
2708 .Case("ishst", ARM_MB::ISHST)
2709 .Case("nsh", ARM_MB::NSH)
2710 .Case("un", ARM_MB::NSH)
2711 .Case("nshst", ARM_MB::NSHST)
2712 .Case("unst", ARM_MB::NSHST)
2713 .Case("osh", ARM_MB::OSH)
2714 .Case("oshst", ARM_MB::OSHST)
2718 return MatchOperand_NoMatch;
2720 Parser.Lex(); // Eat identifier token.
2721 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
2722 return MatchOperand_Success;
2725 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
2726 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2727 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2728 SMLoc S = Parser.getTok().getLoc();
2729 const AsmToken &Tok = Parser.getTok();
2730 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2731 StringRef IFlagsStr = Tok.getString();
2733 // An iflags string of "none" is interpreted to mean that none of the AIF
2734 // bits are set. Not a terribly useful instruction, but a valid encoding.
2735 unsigned IFlags = 0;
2736 if (IFlagsStr != "none") {
2737 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
2738 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
2739 .Case("a", ARM_PROC::A)
2740 .Case("i", ARM_PROC::I)
2741 .Case("f", ARM_PROC::F)
2744 // If some specific iflag is already set, it means that some letter is
2745 // present more than once, this is not acceptable.
2746 if (Flag == ~0U || (IFlags & Flag))
2747 return MatchOperand_NoMatch;
2753 Parser.Lex(); // Eat identifier token.
2754 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
2755 return MatchOperand_Success;
2758 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
2759 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2760 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2761 SMLoc S = Parser.getTok().getLoc();
2762 const AsmToken &Tok = Parser.getTok();
2763 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2764 StringRef Mask = Tok.getString();
2767 // See ARMv6-M 10.1.1
2768 unsigned FlagsVal = StringSwitch<unsigned>(Mask)
2778 .Case("primask", 16)
2779 .Case("basepri", 17)
2780 .Case("basepri_max", 18)
2781 .Case("faultmask", 19)
2782 .Case("control", 20)
2785 if (FlagsVal == ~0U)
2786 return MatchOperand_NoMatch;
2788 if (!hasV7Ops() && FlagsVal >= 17 && FlagsVal <= 19)
2789 // basepri, basepri_max and faultmask only valid for V7m.
2790 return MatchOperand_NoMatch;
2792 Parser.Lex(); // Eat identifier token.
2793 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
2794 return MatchOperand_Success;
2797 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
2798 size_t Start = 0, Next = Mask.find('_');
2799 StringRef Flags = "";
2800 std::string SpecReg = Mask.slice(Start, Next).lower();
2801 if (Next != StringRef::npos)
2802 Flags = Mask.slice(Next+1, Mask.size());
2804 // FlagsVal contains the complete mask:
2806 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
2807 unsigned FlagsVal = 0;
2809 if (SpecReg == "apsr") {
2810 FlagsVal = StringSwitch<unsigned>(Flags)
2811 .Case("nzcvq", 0x8) // same as CPSR_f
2812 .Case("g", 0x4) // same as CPSR_s
2813 .Case("nzcvqg", 0xc) // same as CPSR_fs
2816 if (FlagsVal == ~0U) {
2818 return MatchOperand_NoMatch;
2820 FlagsVal = 8; // No flag
2822 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
2823 if (Flags == "all") // cpsr_all is an alias for cpsr_fc
2825 for (int i = 0, e = Flags.size(); i != e; ++i) {
2826 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
2833 // If some specific flag is already set, it means that some letter is
2834 // present more than once, this is not acceptable.
2835 if (FlagsVal == ~0U || (FlagsVal & Flag))
2836 return MatchOperand_NoMatch;
2839 } else // No match for special register.
2840 return MatchOperand_NoMatch;
2842 // Special register without flags is NOT equivalent to "fc" flags.
2843 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
2844 // two lines would enable gas compatibility at the expense of breaking
2850 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
2851 if (SpecReg == "spsr")
2854 Parser.Lex(); // Eat identifier token.
2855 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
2856 return MatchOperand_Success;
2859 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2860 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
2861 int Low, int High) {
2862 const AsmToken &Tok = Parser.getTok();
2863 if (Tok.isNot(AsmToken::Identifier)) {
2864 Error(Parser.getTok().getLoc(), Op + " operand expected.");
2865 return MatchOperand_ParseFail;
2867 StringRef ShiftName = Tok.getString();
2868 std::string LowerOp = Op.lower();
2869 std::string UpperOp = Op.upper();
2870 if (ShiftName != LowerOp && ShiftName != UpperOp) {
2871 Error(Parser.getTok().getLoc(), Op + " operand expected.");
2872 return MatchOperand_ParseFail;
2874 Parser.Lex(); // Eat shift type token.
2876 // There must be a '#' and a shift amount.
2877 if (Parser.getTok().isNot(AsmToken::Hash)) {
2878 Error(Parser.getTok().getLoc(), "'#' expected");
2879 return MatchOperand_ParseFail;
2881 Parser.Lex(); // Eat hash token.
2883 const MCExpr *ShiftAmount;
2884 SMLoc Loc = Parser.getTok().getLoc();
2885 if (getParser().ParseExpression(ShiftAmount)) {
2886 Error(Loc, "illegal expression");
2887 return MatchOperand_ParseFail;
2889 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2891 Error(Loc, "constant expression expected");
2892 return MatchOperand_ParseFail;
2894 int Val = CE->getValue();
2895 if (Val < Low || Val > High) {
2896 Error(Loc, "immediate value out of range");
2897 return MatchOperand_ParseFail;
2900 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
2902 return MatchOperand_Success;
2905 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2906 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2907 const AsmToken &Tok = Parser.getTok();
2908 SMLoc S = Tok.getLoc();
2909 if (Tok.isNot(AsmToken::Identifier)) {
2910 Error(Tok.getLoc(), "'be' or 'le' operand expected");
2911 return MatchOperand_ParseFail;
2913 int Val = StringSwitch<int>(Tok.getString())
2917 Parser.Lex(); // Eat the token.
2920 Error(Tok.getLoc(), "'be' or 'le' operand expected");
2921 return MatchOperand_ParseFail;
2923 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
2925 S, Parser.getTok().getLoc()));
2926 return MatchOperand_Success;
2929 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
2930 /// instructions. Legal values are:
2931 /// lsl #n 'n' in [0,31]
2932 /// asr #n 'n' in [1,32]
2933 /// n == 32 encoded as n == 0.
2934 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2935 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2936 const AsmToken &Tok = Parser.getTok();
2937 SMLoc S = Tok.getLoc();
2938 if (Tok.isNot(AsmToken::Identifier)) {
2939 Error(S, "shift operator 'asr' or 'lsl' expected");
2940 return MatchOperand_ParseFail;
2942 StringRef ShiftName = Tok.getString();
2944 if (ShiftName == "lsl" || ShiftName == "LSL")
2946 else if (ShiftName == "asr" || ShiftName == "ASR")
2949 Error(S, "shift operator 'asr' or 'lsl' expected");
2950 return MatchOperand_ParseFail;
2952 Parser.Lex(); // Eat the operator.
2954 // A '#' and a shift amount.
2955 if (Parser.getTok().isNot(AsmToken::Hash)) {
2956 Error(Parser.getTok().getLoc(), "'#' expected");
2957 return MatchOperand_ParseFail;
2959 Parser.Lex(); // Eat hash token.
2961 const MCExpr *ShiftAmount;
2962 SMLoc E = Parser.getTok().getLoc();
2963 if (getParser().ParseExpression(ShiftAmount)) {
2964 Error(E, "malformed shift expression");
2965 return MatchOperand_ParseFail;
2967 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2969 Error(E, "shift amount must be an immediate");
2970 return MatchOperand_ParseFail;
2973 int64_t Val = CE->getValue();
2975 // Shift amount must be in [1,32]
2976 if (Val < 1 || Val > 32) {
2977 Error(E, "'asr' shift amount must be in range [1,32]");
2978 return MatchOperand_ParseFail;
2980 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
2981 if (isThumb() && Val == 32) {
2982 Error(E, "'asr #32' shift amount not allowed in Thumb mode");
2983 return MatchOperand_ParseFail;
2985 if (Val == 32) Val = 0;
2987 // Shift amount must be in [1,32]
2988 if (Val < 0 || Val > 31) {
2989 Error(E, "'lsr' shift amount must be in range [0,31]");
2990 return MatchOperand_ParseFail;
2994 E = Parser.getTok().getLoc();
2995 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
2997 return MatchOperand_Success;
3000 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3001 /// of instructions. Legal values are:
3002 /// ror #n 'n' in {0, 8, 16, 24}
3003 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3004 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3005 const AsmToken &Tok = Parser.getTok();
3006 SMLoc S = Tok.getLoc();
3007 if (Tok.isNot(AsmToken::Identifier))
3008 return MatchOperand_NoMatch;
3009 StringRef ShiftName = Tok.getString();
3010 if (ShiftName != "ror" && ShiftName != "ROR")
3011 return MatchOperand_NoMatch;
3012 Parser.Lex(); // Eat the operator.
3014 // A '#' and a rotate amount.
3015 if (Parser.getTok().isNot(AsmToken::Hash)) {
3016 Error(Parser.getTok().getLoc(), "'#' expected");
3017 return MatchOperand_ParseFail;
3019 Parser.Lex(); // Eat hash token.
3021 const MCExpr *ShiftAmount;
3022 SMLoc E = Parser.getTok().getLoc();
3023 if (getParser().ParseExpression(ShiftAmount)) {
3024 Error(E, "malformed rotate expression");
3025 return MatchOperand_ParseFail;
3027 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3029 Error(E, "rotate amount must be an immediate");
3030 return MatchOperand_ParseFail;
3033 int64_t Val = CE->getValue();
3034 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
3035 // normally, zero is represented in asm by omitting the rotate operand
3037 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
3038 Error(E, "'ror' rotate amount must be 8, 16, or 24");
3039 return MatchOperand_ParseFail;
3042 E = Parser.getTok().getLoc();
3043 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
3045 return MatchOperand_Success;
3048 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3049 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3050 SMLoc S = Parser.getTok().getLoc();
3051 // The bitfield descriptor is really two operands, the LSB and the width.
3052 if (Parser.getTok().isNot(AsmToken::Hash)) {
3053 Error(Parser.getTok().getLoc(), "'#' expected");
3054 return MatchOperand_ParseFail;
3056 Parser.Lex(); // Eat hash token.
3058 const MCExpr *LSBExpr;
3059 SMLoc E = Parser.getTok().getLoc();
3060 if (getParser().ParseExpression(LSBExpr)) {
3061 Error(E, "malformed immediate expression");
3062 return MatchOperand_ParseFail;
3064 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
3066 Error(E, "'lsb' operand must be an immediate");
3067 return MatchOperand_ParseFail;
3070 int64_t LSB = CE->getValue();
3071 // The LSB must be in the range [0,31]
3072 if (LSB < 0 || LSB > 31) {
3073 Error(E, "'lsb' operand must be in the range [0,31]");
3074 return MatchOperand_ParseFail;
3076 E = Parser.getTok().getLoc();
3078 // Expect another immediate operand.
3079 if (Parser.getTok().isNot(AsmToken::Comma)) {
3080 Error(Parser.getTok().getLoc(), "too few operands");
3081 return MatchOperand_ParseFail;
3083 Parser.Lex(); // Eat hash token.
3084 if (Parser.getTok().isNot(AsmToken::Hash)) {
3085 Error(Parser.getTok().getLoc(), "'#' expected");
3086 return MatchOperand_ParseFail;
3088 Parser.Lex(); // Eat hash token.
3090 const MCExpr *WidthExpr;
3091 if (getParser().ParseExpression(WidthExpr)) {
3092 Error(E, "malformed immediate expression");
3093 return MatchOperand_ParseFail;
3095 CE = dyn_cast<MCConstantExpr>(WidthExpr);
3097 Error(E, "'width' operand must be an immediate");
3098 return MatchOperand_ParseFail;
3101 int64_t Width = CE->getValue();
3102 // The LSB must be in the range [1,32-lsb]
3103 if (Width < 1 || Width > 32 - LSB) {
3104 Error(E, "'width' operand must be in the range [1,32-lsb]");
3105 return MatchOperand_ParseFail;
3107 E = Parser.getTok().getLoc();
3109 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
3111 return MatchOperand_Success;
3114 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3115 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3116 // Check for a post-index addressing register operand. Specifically:
3117 // postidx_reg := '+' register {, shift}
3118 // | '-' register {, shift}
3119 // | register {, shift}
3121 // This method must return MatchOperand_NoMatch without consuming any tokens
3122 // in the case where there is no match, as other alternatives take other
3124 AsmToken Tok = Parser.getTok();
3125 SMLoc S = Tok.getLoc();
3126 bool haveEaten = false;
3129 if (Tok.is(AsmToken::Plus)) {
3130 Parser.Lex(); // Eat the '+' token.
3132 } else if (Tok.is(AsmToken::Minus)) {
3133 Parser.Lex(); // Eat the '-' token.
3137 if (Parser.getTok().is(AsmToken::Identifier))
3138 Reg = tryParseRegister();
3141 return MatchOperand_NoMatch;
3142 Error(Parser.getTok().getLoc(), "register expected");
3143 return MatchOperand_ParseFail;
3145 SMLoc E = Parser.getTok().getLoc();
3147 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
3148 unsigned ShiftImm = 0;
3149 if (Parser.getTok().is(AsmToken::Comma)) {
3150 Parser.Lex(); // Eat the ','.
3151 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
3152 return MatchOperand_ParseFail;
3155 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
3158 return MatchOperand_Success;
3161 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3162 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3163 // Check for a post-index addressing register operand. Specifically:
3164 // am3offset := '+' register
3171 // This method must return MatchOperand_NoMatch without consuming any tokens
3172 // in the case where there is no match, as other alternatives take other
3174 AsmToken Tok = Parser.getTok();
3175 SMLoc S = Tok.getLoc();
3177 // Do immediates first, as we always parse those if we have a '#'.
3178 if (Parser.getTok().is(AsmToken::Hash)) {
3179 Parser.Lex(); // Eat the '#'.
3180 // Explicitly look for a '-', as we need to encode negative zero
3182 bool isNegative = Parser.getTok().is(AsmToken::Minus);
3183 const MCExpr *Offset;
3184 if (getParser().ParseExpression(Offset))
3185 return MatchOperand_ParseFail;
3186 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
3188 Error(S, "constant expression expected");
3189 return MatchOperand_ParseFail;
3191 SMLoc E = Tok.getLoc();
3192 // Negative zero is encoded as the flag value INT32_MIN.
3193 int32_t Val = CE->getValue();
3194 if (isNegative && Val == 0)
3198 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
3200 return MatchOperand_Success;
3204 bool haveEaten = false;
3207 if (Tok.is(AsmToken::Plus)) {
3208 Parser.Lex(); // Eat the '+' token.
3210 } else if (Tok.is(AsmToken::Minus)) {
3211 Parser.Lex(); // Eat the '-' token.
3215 if (Parser.getTok().is(AsmToken::Identifier))
3216 Reg = tryParseRegister();
3219 return MatchOperand_NoMatch;
3220 Error(Parser.getTok().getLoc(), "register expected");
3221 return MatchOperand_ParseFail;
3223 SMLoc E = Parser.getTok().getLoc();
3225 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
3228 return MatchOperand_Success;
3231 /// cvtT2LdrdPre - Convert parsed operands to MCInst.
3232 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3233 /// when they refer multiple MIOperands inside a single one.
3235 cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
3236 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3238 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3239 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3240 // Create a writeback register dummy placeholder.
3241 Inst.addOperand(MCOperand::CreateReg(0));
3243 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3245 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3249 /// cvtT2StrdPre - Convert parsed operands to MCInst.
3250 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3251 /// when they refer multiple MIOperands inside a single one.
3253 cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
3254 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3255 // Create a writeback register dummy placeholder.
3256 Inst.addOperand(MCOperand::CreateReg(0));
3258 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3259 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3261 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3263 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3267 /// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3268 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3269 /// when they refer multiple MIOperands inside a single one.
3271 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3272 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3273 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3275 // Create a writeback register dummy placeholder.
3276 Inst.addOperand(MCOperand::CreateImm(0));
3278 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3279 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3283 /// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3284 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3285 /// when they refer multiple MIOperands inside a single one.
3287 cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3288 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3289 // Create a writeback register dummy placeholder.
3290 Inst.addOperand(MCOperand::CreateImm(0));
3291 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3292 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3293 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3297 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3298 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3299 /// when they refer multiple MIOperands inside a single one.
3301 cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3302 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3303 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3305 // Create a writeback register dummy placeholder.
3306 Inst.addOperand(MCOperand::CreateImm(0));
3308 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3309 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3313 /// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3314 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3315 /// when they refer multiple MIOperands inside a single one.
3317 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3318 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3319 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3321 // Create a writeback register dummy placeholder.
3322 Inst.addOperand(MCOperand::CreateImm(0));
3324 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3325 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3330 /// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3331 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3332 /// when they refer multiple MIOperands inside a single one.
3334 cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3335 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3336 // Create a writeback register dummy placeholder.
3337 Inst.addOperand(MCOperand::CreateImm(0));
3338 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3339 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3340 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3344 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3345 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3346 /// when they refer multiple MIOperands inside a single one.
3348 cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3349 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3350 // Create a writeback register dummy placeholder.
3351 Inst.addOperand(MCOperand::CreateImm(0));
3352 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3353 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3354 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3358 /// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
3359 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3360 /// when they refer multiple MIOperands inside a single one.
3362 cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
3363 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3364 // Create a writeback register dummy placeholder.
3365 Inst.addOperand(MCOperand::CreateImm(0));
3366 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3367 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
3368 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3372 /// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
3373 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3374 /// when they refer multiple MIOperands inside a single one.
3376 cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
3377 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3379 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3380 // Create a writeback register dummy placeholder.
3381 Inst.addOperand(MCOperand::CreateImm(0));
3383 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3385 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
3387 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3391 /// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
3392 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3393 /// when they refer multiple MIOperands inside a single one.
3395 cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
3396 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3398 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3399 // Create a writeback register dummy placeholder.
3400 Inst.addOperand(MCOperand::CreateImm(0));
3402 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3404 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
3406 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3410 /// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
3411 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3412 /// when they refer multiple MIOperands inside a single one.
3414 cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
3415 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3416 // Create a writeback register dummy placeholder.
3417 Inst.addOperand(MCOperand::CreateImm(0));
3419 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3421 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3423 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
3425 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3429 /// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
3430 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3431 /// when they refer multiple MIOperands inside a single one.
3433 cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
3434 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3435 // Create a writeback register dummy placeholder.
3436 Inst.addOperand(MCOperand::CreateImm(0));
3438 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3440 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3442 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
3444 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3448 /// cvtLdrdPre - Convert parsed operands to MCInst.
3449 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3450 /// when they refer multiple MIOperands inside a single one.
3452 cvtLdrdPre(MCInst &Inst, unsigned Opcode,
3453 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3455 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3456 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3457 // Create a writeback register dummy placeholder.
3458 Inst.addOperand(MCOperand::CreateImm(0));
3460 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
3462 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3466 /// cvtStrdPre - Convert parsed operands to MCInst.
3467 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3468 /// when they refer multiple MIOperands inside a single one.
3470 cvtStrdPre(MCInst &Inst, unsigned Opcode,
3471 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3472 // Create a writeback register dummy placeholder.
3473 Inst.addOperand(MCOperand::CreateImm(0));
3475 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3476 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3478 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
3480 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3484 /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
3485 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3486 /// when they refer multiple MIOperands inside a single one.
3488 cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
3489 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3490 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3491 // Create a writeback register dummy placeholder.
3492 Inst.addOperand(MCOperand::CreateImm(0));
3493 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
3494 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3498 /// cvtThumbMultiple- Convert parsed operands to MCInst.
3499 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3500 /// when they refer multiple MIOperands inside a single one.
3502 cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
3503 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3504 // The second source operand must be the same register as the destination
3506 if (Operands.size() == 6 &&
3507 (((ARMOperand*)Operands[3])->getReg() !=
3508 ((ARMOperand*)Operands[5])->getReg()) &&
3509 (((ARMOperand*)Operands[3])->getReg() !=
3510 ((ARMOperand*)Operands[4])->getReg())) {
3511 Error(Operands[3]->getStartLoc(),
3512 "destination register must match source register");
3515 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3516 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
3517 // If we have a three-operand form, make sure to set Rn to be the operand
3518 // that isn't the same as Rd.
3520 if (Operands.size() == 6 &&
3521 ((ARMOperand*)Operands[4])->getReg() ==
3522 ((ARMOperand*)Operands[3])->getReg())
3524 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
3525 Inst.addOperand(Inst.getOperand(0));
3526 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
3532 cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
3533 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3535 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
3536 // Create a writeback register dummy placeholder.
3537 Inst.addOperand(MCOperand::CreateImm(0));
3539 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3541 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3546 cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
3547 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3549 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
3550 // Create a writeback register dummy placeholder.
3551 Inst.addOperand(MCOperand::CreateImm(0));
3553 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3555 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
3557 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3562 cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
3563 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3564 // Create a writeback register dummy placeholder.
3565 Inst.addOperand(MCOperand::CreateImm(0));
3567 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3569 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
3571 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3576 cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
3577 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3578 // Create a writeback register dummy placeholder.
3579 Inst.addOperand(MCOperand::CreateImm(0));
3581 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3583 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
3585 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
3587 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3591 /// Parse an ARM memory expression, return false if successful else return true
3592 /// or an error. The first token must be a '[' when called.
3594 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3596 assert(Parser.getTok().is(AsmToken::LBrac) &&
3597 "Token is not a Left Bracket");
3598 S = Parser.getTok().getLoc();
3599 Parser.Lex(); // Eat left bracket token.
3601 const AsmToken &BaseRegTok = Parser.getTok();
3602 int BaseRegNum = tryParseRegister();
3603 if (BaseRegNum == -1)
3604 return Error(BaseRegTok.getLoc(), "register expected");
3606 // The next token must either be a comma or a closing bracket.
3607 const AsmToken &Tok = Parser.getTok();
3608 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
3609 return Error(Tok.getLoc(), "malformed memory operand");
3611 if (Tok.is(AsmToken::RBrac)) {
3613 Parser.Lex(); // Eat right bracket token.
3615 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
3616 0, 0, false, S, E));
3618 // If there's a pre-indexing writeback marker, '!', just add it as a token
3619 // operand. It's rather odd, but syntactically valid.
3620 if (Parser.getTok().is(AsmToken::Exclaim)) {
3621 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3622 Parser.Lex(); // Eat the '!'.
3628 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
3629 Parser.Lex(); // Eat the comma.
3631 // If we have a ':', it's an alignment specifier.
3632 if (Parser.getTok().is(AsmToken::Colon)) {
3633 Parser.Lex(); // Eat the ':'.
3634 E = Parser.getTok().getLoc();
3637 if (getParser().ParseExpression(Expr))
3640 // The expression has to be a constant. Memory references with relocations
3641 // don't come through here, as they use the <label> forms of the relevant
3643 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3645 return Error (E, "constant expression expected");
3648 switch (CE->getValue()) {
3650 return Error(E, "alignment specifier must be 64, 128, or 256 bits");
3651 case 64: Align = 8; break;
3652 case 128: Align = 16; break;
3653 case 256: Align = 32; break;
3656 // Now we should have the closing ']'
3657 E = Parser.getTok().getLoc();
3658 if (Parser.getTok().isNot(AsmToken::RBrac))
3659 return Error(E, "']' expected");
3660 Parser.Lex(); // Eat right bracket token.
3662 // Don't worry about range checking the value here. That's handled by
3663 // the is*() predicates.
3664 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
3665 ARM_AM::no_shift, 0, Align,
3668 // If there's a pre-indexing writeback marker, '!', just add it as a token
3670 if (Parser.getTok().is(AsmToken::Exclaim)) {
3671 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3672 Parser.Lex(); // Eat the '!'.
3678 // If we have a '#', it's an immediate offset, else assume it's a register
3679 // offset. Be friendly and also accept a plain integer (without a leading
3680 // hash) for gas compatibility.
3681 if (Parser.getTok().is(AsmToken::Hash) ||
3682 Parser.getTok().is(AsmToken::Integer)) {
3683 if (Parser.getTok().is(AsmToken::Hash))
3684 Parser.Lex(); // Eat the '#'.
3685 E = Parser.getTok().getLoc();
3687 bool isNegative = getParser().getTok().is(AsmToken::Minus);
3688 const MCExpr *Offset;
3689 if (getParser().ParseExpression(Offset))
3692 // The expression has to be a constant. Memory references with relocations
3693 // don't come through here, as they use the <label> forms of the relevant
3695 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
3697 return Error (E, "constant expression expected");
3699 // If the constant was #-0, represent it as INT32_MIN.
3700 int32_t Val = CE->getValue();
3701 if (isNegative && Val == 0)
3702 CE = MCConstantExpr::Create(INT32_MIN, getContext());
3704 // Now we should have the closing ']'
3705 E = Parser.getTok().getLoc();
3706 if (Parser.getTok().isNot(AsmToken::RBrac))
3707 return Error(E, "']' expected");
3708 Parser.Lex(); // Eat right bracket token.
3710 // Don't worry about range checking the value here. That's handled by
3711 // the is*() predicates.
3712 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
3713 ARM_AM::no_shift, 0, 0,
3716 // If there's a pre-indexing writeback marker, '!', just add it as a token
3718 if (Parser.getTok().is(AsmToken::Exclaim)) {
3719 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3720 Parser.Lex(); // Eat the '!'.
3726 // The register offset is optionally preceded by a '+' or '-'
3727 bool isNegative = false;
3728 if (Parser.getTok().is(AsmToken::Minus)) {
3730 Parser.Lex(); // Eat the '-'.
3731 } else if (Parser.getTok().is(AsmToken::Plus)) {
3733 Parser.Lex(); // Eat the '+'.
3736 E = Parser.getTok().getLoc();
3737 int OffsetRegNum = tryParseRegister();
3738 if (OffsetRegNum == -1)
3739 return Error(E, "register expected");
3741 // If there's a shift operator, handle it.
3742 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
3743 unsigned ShiftImm = 0;
3744 if (Parser.getTok().is(AsmToken::Comma)) {
3745 Parser.Lex(); // Eat the ','.
3746 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
3750 // Now we should have the closing ']'
3751 E = Parser.getTok().getLoc();
3752 if (Parser.getTok().isNot(AsmToken::RBrac))
3753 return Error(E, "']' expected");
3754 Parser.Lex(); // Eat right bracket token.
3756 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
3757 ShiftType, ShiftImm, 0, isNegative,
3760 // If there's a pre-indexing writeback marker, '!', just add it as a token
3762 if (Parser.getTok().is(AsmToken::Exclaim)) {
3763 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3764 Parser.Lex(); // Eat the '!'.
3770 /// parseMemRegOffsetShift - one of these two:
3771 /// ( lsl | lsr | asr | ror ) , # shift_amount
3773 /// return true if it parses a shift otherwise it returns false.
3774 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
3776 SMLoc Loc = Parser.getTok().getLoc();
3777 const AsmToken &Tok = Parser.getTok();
3778 if (Tok.isNot(AsmToken::Identifier))
3780 StringRef ShiftName = Tok.getString();
3781 if (ShiftName == "lsl" || ShiftName == "LSL")
3783 else if (ShiftName == "lsr" || ShiftName == "LSR")
3785 else if (ShiftName == "asr" || ShiftName == "ASR")
3787 else if (ShiftName == "ror" || ShiftName == "ROR")
3789 else if (ShiftName == "rrx" || ShiftName == "RRX")
3792 return Error(Loc, "illegal shift operator");
3793 Parser.Lex(); // Eat shift type token.
3795 // rrx stands alone.
3797 if (St != ARM_AM::rrx) {
3798 Loc = Parser.getTok().getLoc();
3799 // A '#' and a shift amount.
3800 const AsmToken &HashTok = Parser.getTok();
3801 if (HashTok.isNot(AsmToken::Hash))
3802 return Error(HashTok.getLoc(), "'#' expected");
3803 Parser.Lex(); // Eat hash token.
3806 if (getParser().ParseExpression(Expr))
3808 // Range check the immediate.
3809 // lsl, ror: 0 <= imm <= 31
3810 // lsr, asr: 0 <= imm <= 32
3811 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3813 return Error(Loc, "shift amount must be an immediate");
3814 int64_t Imm = CE->getValue();
3816 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
3817 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
3818 return Error(Loc, "immediate shift value out of range");
3825 /// parseFPImm - A floating point immediate expression operand.
3826 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3827 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3828 SMLoc S = Parser.getTok().getLoc();
3830 if (Parser.getTok().isNot(AsmToken::Hash))
3831 return MatchOperand_NoMatch;
3833 // Disambiguate the VMOV forms that can accept an FP immediate.
3834 // vmov.f32 <sreg>, #imm
3835 // vmov.f64 <dreg>, #imm
3836 // vmov.f32 <dreg>, #imm @ vector f32x2
3837 // vmov.f32 <qreg>, #imm @ vector f32x4
3839 // There are also the NEON VMOV instructions which expect an
3840 // integer constant. Make sure we don't try to parse an FPImm
3842 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
3843 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
3844 if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
3845 TyOp->getToken() != ".f64"))
3846 return MatchOperand_NoMatch;
3848 Parser.Lex(); // Eat the '#'.
3850 // Handle negation, as that still comes through as a separate token.
3851 bool isNegative = false;
3852 if (Parser.getTok().is(AsmToken::Minus)) {
3856 const AsmToken &Tok = Parser.getTok();
3857 if (Tok.is(AsmToken::Real)) {
3858 APFloat RealVal(APFloat::IEEEdouble, Tok.getString());
3859 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
3860 // If we had a '-' in front, toggle the sign bit.
3861 IntVal ^= (uint64_t)isNegative << 63;
3862 int Val = ARM_AM::getFP64Imm(APInt(64, IntVal));
3863 Parser.Lex(); // Eat the token.
3865 TokError("floating point value out of range");
3866 return MatchOperand_ParseFail;
3868 Operands.push_back(ARMOperand::CreateFPImm(Val, S, getContext()));
3869 return MatchOperand_Success;
3871 if (Tok.is(AsmToken::Integer)) {
3872 int64_t Val = Tok.getIntVal();
3873 Parser.Lex(); // Eat the token.
3874 if (Val > 255 || Val < 0) {
3875 TokError("encoded floating point value out of range");
3876 return MatchOperand_ParseFail;
3878 Operands.push_back(ARMOperand::CreateFPImm(Val, S, getContext()));
3879 return MatchOperand_Success;
3882 TokError("invalid floating point immediate");
3883 return MatchOperand_ParseFail;
3885 /// Parse a arm instruction operand. For now this parses the operand regardless
3886 /// of the mnemonic.
3887 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
3888 StringRef Mnemonic) {
3891 // Check if the current operand has a custom associated parser, if so, try to
3892 // custom parse the operand, or fallback to the general approach.
3893 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
3894 if (ResTy == MatchOperand_Success)
3896 // If there wasn't a custom match, try the generic matcher below. Otherwise,
3897 // there was a match, but an error occurred, in which case, just return that
3898 // the operand parsing failed.
3899 if (ResTy == MatchOperand_ParseFail)
3902 switch (getLexer().getKind()) {
3904 Error(Parser.getTok().getLoc(), "unexpected token in operand");
3906 case AsmToken::Identifier: {
3907 // If this is VMRS, check for the apsr_nzcv operand.
3908 if (!tryParseRegisterWithWriteBack(Operands))
3910 int Res = tryParseShiftRegister(Operands);
3911 if (Res == 0) // success
3913 else if (Res == -1) // irrecoverable error
3915 if (Mnemonic == "vmrs" && Parser.getTok().getString() == "apsr_nzcv") {
3916 S = Parser.getTok().getLoc();
3918 Operands.push_back(ARMOperand::CreateToken("apsr_nzcv", S));
3922 // Fall though for the Identifier case that is not a register or a
3925 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
3926 case AsmToken::Integer: // things like 1f and 2b as a branch targets
3927 case AsmToken::String: // quoted label names.
3928 case AsmToken::Dot: { // . as a branch target
3929 // This was not a register so parse other operands that start with an
3930 // identifier (like labels) as expressions and create them as immediates.
3931 const MCExpr *IdVal;
3932 S = Parser.getTok().getLoc();
3933 if (getParser().ParseExpression(IdVal))
3935 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3936 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
3939 case AsmToken::LBrac:
3940 return parseMemory(Operands);
3941 case AsmToken::LCurly:
3942 return parseRegisterList(Operands);
3943 case AsmToken::Hash: {
3944 // #42 -> immediate.
3945 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
3946 S = Parser.getTok().getLoc();
3948 bool isNegative = Parser.getTok().is(AsmToken::Minus);
3949 const MCExpr *ImmVal;
3950 if (getParser().ParseExpression(ImmVal))
3952 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
3954 int32_t Val = CE->getValue();
3955 if (isNegative && Val == 0)
3956 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
3958 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3959 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
3962 case AsmToken::Colon: {
3963 // ":lower16:" and ":upper16:" expression prefixes
3964 // FIXME: Check it's an expression prefix,
3965 // e.g. (FOO - :lower16:BAR) isn't legal.
3966 ARMMCExpr::VariantKind RefKind;
3967 if (parsePrefix(RefKind))
3970 const MCExpr *SubExprVal;
3971 if (getParser().ParseExpression(SubExprVal))
3974 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
3976 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3977 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
3983 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
3984 // :lower16: and :upper16:.
3985 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
3986 RefKind = ARMMCExpr::VK_ARM_None;
3988 // :lower16: and :upper16: modifiers
3989 assert(getLexer().is(AsmToken::Colon) && "expected a :");
3990 Parser.Lex(); // Eat ':'
3992 if (getLexer().isNot(AsmToken::Identifier)) {
3993 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
3997 StringRef IDVal = Parser.getTok().getIdentifier();
3998 if (IDVal == "lower16") {
3999 RefKind = ARMMCExpr::VK_ARM_LO16;
4000 } else if (IDVal == "upper16") {
4001 RefKind = ARMMCExpr::VK_ARM_HI16;
4003 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4008 if (getLexer().isNot(AsmToken::Colon)) {
4009 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4012 Parser.Lex(); // Eat the last ':'
4016 /// \brief Given a mnemonic, split out possible predication code and carry
4017 /// setting letters to form a canonical mnemonic and flags.
4019 // FIXME: Would be nice to autogen this.
4020 // FIXME: This is a bit of a maze of special cases.
4021 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4022 unsigned &PredicationCode,
4024 unsigned &ProcessorIMod,
4025 StringRef &ITMask) {
4026 PredicationCode = ARMCC::AL;
4027 CarrySetting = false;
4030 // Ignore some mnemonics we know aren't predicated forms.
4032 // FIXME: Would be nice to autogen this.
4033 if ((Mnemonic == "movs" && isThumb()) ||
4034 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
4035 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
4036 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
4037 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
4038 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
4039 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
4040 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
4043 // First, split out any predication code. Ignore mnemonics we know aren't
4044 // predicated but do have a carry-set and so weren't caught above.
4045 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4046 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4047 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4048 Mnemonic != "sbcs" && Mnemonic != "rscs") {
4049 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4050 .Case("eq", ARMCC::EQ)
4051 .Case("ne", ARMCC::NE)
4052 .Case("hs", ARMCC::HS)
4053 .Case("cs", ARMCC::HS)
4054 .Case("lo", ARMCC::LO)
4055 .Case("cc", ARMCC::LO)
4056 .Case("mi", ARMCC::MI)
4057 .Case("pl", ARMCC::PL)
4058 .Case("vs", ARMCC::VS)
4059 .Case("vc", ARMCC::VC)
4060 .Case("hi", ARMCC::HI)
4061 .Case("ls", ARMCC::LS)
4062 .Case("ge", ARMCC::GE)
4063 .Case("lt", ARMCC::LT)
4064 .Case("gt", ARMCC::GT)
4065 .Case("le", ARMCC::LE)
4066 .Case("al", ARMCC::AL)
4069 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4070 PredicationCode = CC;
4074 // Next, determine if we have a carry setting bit. We explicitly ignore all
4075 // the instructions we know end in 's'.
4076 if (Mnemonic.endswith("s") &&
4077 !(Mnemonic == "cps" || Mnemonic == "mls" ||
4078 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4079 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4080 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4081 Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
4082 (Mnemonic == "movs" && isThumb()))) {
4083 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4084 CarrySetting = true;
4087 // The "cps" instruction can have a interrupt mode operand which is glued into
4088 // the mnemonic. Check if this is the case, split it and parse the imod op
4089 if (Mnemonic.startswith("cps")) {
4090 // Split out any imod code.
4092 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4093 .Case("ie", ARM_PROC::IE)
4094 .Case("id", ARM_PROC::ID)
4097 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4098 ProcessorIMod = IMod;
4102 // The "it" instruction has the condition mask on the end of the mnemonic.
4103 if (Mnemonic.startswith("it")) {
4104 ITMask = Mnemonic.slice(2, Mnemonic.size());
4105 Mnemonic = Mnemonic.slice(0, 2);
4111 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
4112 /// inclusion of carry set or predication code operands.
4114 // FIXME: It would be nice to autogen this.
4116 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
4117 bool &CanAcceptPredicationCode) {
4118 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4119 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4120 Mnemonic == "add" || Mnemonic == "adc" ||
4121 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4122 Mnemonic == "orr" || Mnemonic == "mvn" ||
4123 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4124 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4125 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4126 Mnemonic == "mla" || Mnemonic == "smlal" ||
4127 Mnemonic == "umlal" || Mnemonic == "umull"))) {
4128 CanAcceptCarrySet = true;
4130 CanAcceptCarrySet = false;
4132 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
4133 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
4134 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
4135 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
4136 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
4137 (Mnemonic == "clrex" && !isThumb()) ||
4138 (Mnemonic == "nop" && isThumbOne()) ||
4139 ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" ||
4140 Mnemonic == "ldc2" || Mnemonic == "ldc2l" ||
4141 Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) ||
4142 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
4144 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
4145 CanAcceptPredicationCode = false;
4147 CanAcceptPredicationCode = true;
4150 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
4151 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
4152 CanAcceptPredicationCode = false;
4156 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4157 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4158 // FIXME: This is all horribly hacky. We really need a better way to deal
4159 // with optional operands like this in the matcher table.
4161 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4162 // another does not. Specifically, the MOVW instruction does not. So we
4163 // special case it here and remove the defaulted (non-setting) cc_out
4164 // operand if that's the instruction we're trying to match.
4166 // We do this as post-processing of the explicit operands rather than just
4167 // conditionally adding the cc_out in the first place because we need
4168 // to check the type of the parsed immediate operand.
4169 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4170 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4171 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4172 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4175 // Register-register 'add' for thumb does not have a cc_out operand
4176 // when there are only two register operands.
4177 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4178 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4179 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4180 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4182 // Register-register 'add' for thumb does not have a cc_out operand
4183 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4184 // have to check the immediate range here since Thumb2 has a variant
4185 // that can handle a different range and has a cc_out operand.
4186 if (((isThumb() && Mnemonic == "add") ||
4187 (isThumbTwo() && Mnemonic == "sub")) &&
4188 Operands.size() == 6 &&
4189 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4190 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4191 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4192 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4193 (static_cast<ARMOperand*>(Operands[5])->isReg() ||
4194 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4196 // For Thumb2, add/sub immediate does not have a cc_out operand for the
4197 // imm0_4095 variant. That's the least-preferred variant when
4198 // selecting via the generic "add" mnemonic, so to know that we
4199 // should remove the cc_out operand, we have to explicitly check that
4200 // it's not one of the other variants. Ugh.
4201 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4202 Operands.size() == 6 &&
4203 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4204 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4205 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4206 // Nest conditions rather than one big 'if' statement for readability.
4208 // If either register is a high reg, it's either one of the SP
4209 // variants (handled above) or a 32-bit encoding, so we just
4210 // check against T3.
4211 if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4212 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
4213 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
4215 // If both registers are low, we're in an IT block, and the immediate is
4216 // in range, we should use encoding T1 instead, which has a cc_out.
4218 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4219 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4220 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
4223 // Otherwise, we use encoding T4, which does not have a cc_out
4228 // The thumb2 multiply instruction doesn't have a CCOut register, so
4229 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
4230 // use the 16-bit encoding or not.
4231 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
4232 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4233 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4234 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4235 static_cast<ARMOperand*>(Operands[5])->isReg() &&
4236 // If the registers aren't low regs, the destination reg isn't the
4237 // same as one of the source regs, or the cc_out operand is zero
4238 // outside of an IT block, we have to use the 32-bit encoding, so
4239 // remove the cc_out operand.
4240 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4241 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4242 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
4244 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4245 static_cast<ARMOperand*>(Operands[5])->getReg() &&
4246 static_cast<ARMOperand*>(Operands[3])->getReg() !=
4247 static_cast<ARMOperand*>(Operands[4])->getReg())))
4250 // Also check the 'mul' syntax variant that doesn't specify an explicit
4251 // destination register.
4252 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
4253 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4254 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4255 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4256 // If the registers aren't low regs or the cc_out operand is zero
4257 // outside of an IT block, we have to use the 32-bit encoding, so
4258 // remove the cc_out operand.
4259 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4260 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4266 // Register-register 'add/sub' for thumb does not have a cc_out operand
4267 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
4268 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
4269 // right, this will result in better diagnostics (which operand is off)
4271 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
4272 (Operands.size() == 5 || Operands.size() == 6) &&
4273 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4274 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4275 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4281 static bool isDataTypeToken(StringRef Tok) {
4282 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
4283 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
4284 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
4285 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
4286 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
4287 Tok == ".f" || Tok == ".d";
4290 // FIXME: This bit should probably be handled via an explicit match class
4291 // in the .td files that matches the suffix instead of having it be
4292 // a literal string token the way it is now.
4293 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
4294 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
4297 /// Parse an arm instruction mnemonic followed by its operands.
4298 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
4299 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4300 // Create the leading tokens for the mnemonic, split by '.' characters.
4301 size_t Start = 0, Next = Name.find('.');
4302 StringRef Mnemonic = Name.slice(Start, Next);
4304 // Split out the predication code and carry setting flag from the mnemonic.
4305 unsigned PredicationCode;
4306 unsigned ProcessorIMod;
4309 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
4310 ProcessorIMod, ITMask);
4312 // In Thumb1, only the branch (B) instruction can be predicated.
4313 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
4314 Parser.EatToEndOfStatement();
4315 return Error(NameLoc, "conditional execution not supported in Thumb1");
4318 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
4320 // Handle the IT instruction ITMask. Convert it to a bitmask. This
4321 // is the mask as it will be for the IT encoding if the conditional
4322 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
4323 // where the conditional bit0 is zero, the instruction post-processing
4324 // will adjust the mask accordingly.
4325 if (Mnemonic == "it") {
4326 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
4327 if (ITMask.size() > 3) {
4328 Parser.EatToEndOfStatement();
4329 return Error(Loc, "too many conditions on IT instruction");
4332 for (unsigned i = ITMask.size(); i != 0; --i) {
4333 char pos = ITMask[i - 1];
4334 if (pos != 't' && pos != 'e') {
4335 Parser.EatToEndOfStatement();
4336 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
4339 if (ITMask[i - 1] == 't')
4342 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
4345 // FIXME: This is all a pretty gross hack. We should automatically handle
4346 // optional operands like this via tblgen.
4348 // Next, add the CCOut and ConditionCode operands, if needed.
4350 // For mnemonics which can ever incorporate a carry setting bit or predication
4351 // code, our matching model involves us always generating CCOut and
4352 // ConditionCode operands to match the mnemonic "as written" and then we let
4353 // the matcher deal with finding the right instruction or generating an
4354 // appropriate error.
4355 bool CanAcceptCarrySet, CanAcceptPredicationCode;
4356 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
4358 // If we had a carry-set on an instruction that can't do that, issue an
4360 if (!CanAcceptCarrySet && CarrySetting) {
4361 Parser.EatToEndOfStatement();
4362 return Error(NameLoc, "instruction '" + Mnemonic +
4363 "' can not set flags, but 's' suffix specified");
4365 // If we had a predication code on an instruction that can't do that, issue an
4367 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
4368 Parser.EatToEndOfStatement();
4369 return Error(NameLoc, "instruction '" + Mnemonic +
4370 "' is not predicable, but condition code specified");
4373 // Add the carry setting operand, if necessary.
4374 if (CanAcceptCarrySet) {
4375 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
4376 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
4380 // Add the predication code operand, if necessary.
4381 if (CanAcceptPredicationCode) {
4382 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
4384 Operands.push_back(ARMOperand::CreateCondCode(
4385 ARMCC::CondCodes(PredicationCode), Loc));
4388 // Add the processor imod operand, if necessary.
4389 if (ProcessorIMod) {
4390 Operands.push_back(ARMOperand::CreateImm(
4391 MCConstantExpr::Create(ProcessorIMod, getContext()),
4395 // Add the remaining tokens in the mnemonic.
4396 while (Next != StringRef::npos) {
4398 Next = Name.find('.', Start + 1);
4399 StringRef ExtraToken = Name.slice(Start, Next);
4401 // Some NEON instructions have an optional datatype suffix that is
4402 // completely ignored. Check for that.
4403 if (isDataTypeToken(ExtraToken) &&
4404 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
4407 if (ExtraToken != ".n") {
4408 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
4409 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
4413 // Read the remaining operands.
4414 if (getLexer().isNot(AsmToken::EndOfStatement)) {
4415 // Read the first operand.
4416 if (parseOperand(Operands, Mnemonic)) {
4417 Parser.EatToEndOfStatement();
4421 while (getLexer().is(AsmToken::Comma)) {
4422 Parser.Lex(); // Eat the comma.
4424 // Parse and remember the operand.
4425 if (parseOperand(Operands, Mnemonic)) {
4426 Parser.EatToEndOfStatement();
4432 if (getLexer().isNot(AsmToken::EndOfStatement)) {
4433 SMLoc Loc = getLexer().getLoc();
4434 Parser.EatToEndOfStatement();
4435 return Error(Loc, "unexpected token in argument list");
4438 Parser.Lex(); // Consume the EndOfStatement
4440 // Some instructions, mostly Thumb, have forms for the same mnemonic that
4441 // do and don't have a cc_out optional-def operand. With some spot-checks
4442 // of the operand list, we can figure out which variant we're trying to
4443 // parse and adjust accordingly before actually matching. We shouldn't ever
4444 // try to remove a cc_out operand that was explicitly set on the the
4445 // mnemonic, of course (CarrySetting == true). Reason number #317 the
4446 // table driven matcher doesn't fit well with the ARM instruction set.
4447 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
4448 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
4449 Operands.erase(Operands.begin() + 1);
4453 // ARM mode 'blx' need special handling, as the register operand version
4454 // is predicable, but the label operand version is not. So, we can't rely
4455 // on the Mnemonic based checking to correctly figure out when to put
4456 // a k_CondCode operand in the list. If we're trying to match the label
4457 // version, remove the k_CondCode operand here.
4458 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
4459 static_cast<ARMOperand*>(Operands[2])->isImm()) {
4460 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
4461 Operands.erase(Operands.begin() + 1);
4465 // The vector-compare-to-zero instructions have a literal token "#0" at
4466 // the end that comes to here as an immediate operand. Convert it to a
4467 // token to play nicely with the matcher.
4468 if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
4469 Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
4470 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4471 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
4472 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4473 if (CE && CE->getValue() == 0) {
4474 Operands.erase(Operands.begin() + 5);
4475 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4479 // VCMP{E} does the same thing, but with a different operand count.
4480 if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 &&
4481 static_cast<ARMOperand*>(Operands[4])->isImm()) {
4482 ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]);
4483 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4484 if (CE && CE->getValue() == 0) {
4485 Operands.erase(Operands.begin() + 4);
4486 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4490 // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
4491 // end. Convert it to a token here.
4492 if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
4493 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4494 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
4495 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4496 if (CE && CE->getValue() == 0) {
4497 Operands.erase(Operands.begin() + 5);
4498 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4506 // Validate context-sensitive operand constraints.
4508 // return 'true' if register list contains non-low GPR registers,
4509 // 'false' otherwise. If Reg is in the register list or is HiReg, set
4510 // 'containsReg' to true.
4511 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
4512 unsigned HiReg, bool &containsReg) {
4513 containsReg = false;
4514 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
4515 unsigned OpReg = Inst.getOperand(i).getReg();
4518 // Anything other than a low register isn't legal here.
4519 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
4525 // Check if the specified regisgter is in the register list of the inst,
4526 // starting at the indicated operand number.
4527 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
4528 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
4529 unsigned OpReg = Inst.getOperand(i).getReg();
4536 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around
4537 // the ARMInsts array) instead. Getting that here requires awkward
4538 // API changes, though. Better way?
4540 extern const MCInstrDesc ARMInsts[];
4542 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
4543 return ARMInsts[Opcode];
4546 // FIXME: We would really like to be able to tablegen'erate this.
4548 validateInstruction(MCInst &Inst,
4549 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4550 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
4551 SMLoc Loc = Operands[0]->getStartLoc();
4552 // Check the IT block state first.
4553 // NOTE: In Thumb mode, the BKPT instruction has the interesting property of
4554 // being allowed in IT blocks, but not being predicable. It just always
4556 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT) {
4558 if (ITState.FirstCond)
4559 ITState.FirstCond = false;
4561 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
4562 // The instruction must be predicable.
4563 if (!MCID.isPredicable())
4564 return Error(Loc, "instructions in IT block must be predicable");
4565 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
4566 unsigned ITCond = bit ? ITState.Cond :
4567 ARMCC::getOppositeCondition(ITState.Cond);
4568 if (Cond != ITCond) {
4569 // Find the condition code Operand to get its SMLoc information.
4571 for (unsigned i = 1; i < Operands.size(); ++i)
4572 if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
4573 CondLoc = Operands[i]->getStartLoc();
4574 return Error(CondLoc, "incorrect condition in IT block; got '" +
4575 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
4576 "', but expected '" +
4577 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
4579 // Check for non-'al' condition codes outside of the IT block.
4580 } else if (isThumbTwo() && MCID.isPredicable() &&
4581 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
4582 ARMCC::AL && Inst.getOpcode() != ARM::tB &&
4583 Inst.getOpcode() != ARM::t2B)
4584 return Error(Loc, "predicated instructions must be in IT block");
4586 switch (Inst.getOpcode()) {
4589 case ARM::LDRD_POST:
4591 // Rt2 must be Rt + 1.
4592 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
4593 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
4595 return Error(Operands[3]->getStartLoc(),
4596 "destination operands must be sequential");
4600 // Rt2 must be Rt + 1.
4601 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
4602 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
4604 return Error(Operands[3]->getStartLoc(),
4605 "source operands must be sequential");
4609 case ARM::STRD_POST:
4611 // Rt2 must be Rt + 1.
4612 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
4613 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
4615 return Error(Operands[3]->getStartLoc(),
4616 "source operands must be sequential");
4621 // width must be in range [1, 32-lsb]
4622 unsigned lsb = Inst.getOperand(2).getImm();
4623 unsigned widthm1 = Inst.getOperand(3).getImm();
4624 if (widthm1 >= 32 - lsb)
4625 return Error(Operands[5]->getStartLoc(),
4626 "bitfield width must be in range [1,32-lsb]");
4630 // If we're parsing Thumb2, the .w variant is available and handles
4631 // most cases that are normally illegal for a Thumb1 LDM
4632 // instruction. We'll make the transformation in processInstruction()
4635 // Thumb LDM instructions are writeback iff the base register is not
4636 // in the register list.
4637 unsigned Rn = Inst.getOperand(0).getReg();
4638 bool hasWritebackToken =
4639 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
4640 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
4641 bool listContainsBase;
4642 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
4643 return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
4644 "registers must be in range r0-r7");
4645 // If we should have writeback, then there should be a '!' token.
4646 if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
4647 return Error(Operands[2]->getStartLoc(),
4648 "writeback operator '!' expected");
4649 // If we should not have writeback, there must not be a '!'. This is
4650 // true even for the 32-bit wide encodings.
4651 if (listContainsBase && hasWritebackToken)
4652 return Error(Operands[3]->getStartLoc(),
4653 "writeback operator '!' not allowed when base register "
4654 "in register list");
4658 case ARM::t2LDMIA_UPD: {
4659 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
4660 return Error(Operands[4]->getStartLoc(),
4661 "writeback operator '!' not allowed when base register "
4662 "in register list");
4665 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
4666 // so only issue a diagnostic for thumb1. The instructions will be
4667 // switched to the t2 encodings in processInstruction() if necessary.
4669 bool listContainsBase;
4670 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
4672 return Error(Operands[2]->getStartLoc(),
4673 "registers must be in range r0-r7 or pc");
4677 bool listContainsBase;
4678 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
4680 return Error(Operands[2]->getStartLoc(),
4681 "registers must be in range r0-r7 or lr");
4684 case ARM::tSTMIA_UPD: {
4685 bool listContainsBase;
4686 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
4687 return Error(Operands[4]->getStartLoc(),
4688 "registers must be in range r0-r7");
4697 processInstruction(MCInst &Inst,
4698 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4699 switch (Inst.getOpcode()) {
4700 // Handle the MOV complex aliases.
4705 ARM_AM::ShiftOpc ShiftTy;
4706 switch(Inst.getOpcode()) {
4707 default: llvm_unreachable("unexpected opcode!");
4708 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
4709 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
4710 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
4711 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
4713 // A shift by zero is a plain MOVr, not a MOVsi.
4714 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
4716 TmpInst.setOpcode(ARM::MOVsr);
4717 TmpInst.addOperand(Inst.getOperand(0)); // Rd
4718 TmpInst.addOperand(Inst.getOperand(1)); // Rn
4719 TmpInst.addOperand(Inst.getOperand(2)); // Rm
4720 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
4721 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
4722 TmpInst.addOperand(Inst.getOperand(4));
4723 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
4731 ARM_AM::ShiftOpc ShiftTy;
4732 switch(Inst.getOpcode()) {
4733 default: llvm_unreachable("unexpected opcode!");
4734 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
4735 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
4736 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
4737 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
4739 // A shift by zero is a plain MOVr, not a MOVsi.
4740 unsigned Amt = Inst.getOperand(2).getImm();
4741 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
4742 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
4744 TmpInst.setOpcode(Opc);
4745 TmpInst.addOperand(Inst.getOperand(0)); // Rd
4746 TmpInst.addOperand(Inst.getOperand(1)); // Rn
4747 if (Opc == ARM::MOVsi)
4748 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
4749 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
4750 TmpInst.addOperand(Inst.getOperand(4));
4751 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
4756 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
4758 TmpInst.setOpcode(ARM::MOVsi);
4759 TmpInst.addOperand(Inst.getOperand(0)); // Rd
4760 TmpInst.addOperand(Inst.getOperand(1)); // Rn
4761 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
4762 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
4763 TmpInst.addOperand(Inst.getOperand(3));
4764 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
4768 case ARM::t2LDMIA_UPD: {
4769 // If this is a load of a single register, then we should use
4770 // a post-indexed LDR instruction instead, per the ARM ARM.
4771 if (Inst.getNumOperands() != 5)
4774 TmpInst.setOpcode(ARM::t2LDR_POST);
4775 TmpInst.addOperand(Inst.getOperand(4)); // Rt
4776 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
4777 TmpInst.addOperand(Inst.getOperand(1)); // Rn
4778 TmpInst.addOperand(MCOperand::CreateImm(4));
4779 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
4780 TmpInst.addOperand(Inst.getOperand(3));
4784 case ARM::t2STMDB_UPD: {
4785 // If this is a store of a single register, then we should use
4786 // a pre-indexed STR instruction instead, per the ARM ARM.
4787 if (Inst.getNumOperands() != 5)
4790 TmpInst.setOpcode(ARM::t2STR_PRE);
4791 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
4792 TmpInst.addOperand(Inst.getOperand(4)); // Rt
4793 TmpInst.addOperand(Inst.getOperand(1)); // Rn
4794 TmpInst.addOperand(MCOperand::CreateImm(-4));
4795 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
4796 TmpInst.addOperand(Inst.getOperand(3));
4800 case ARM::LDMIA_UPD:
4801 // If this is a load of a single register via a 'pop', then we should use
4802 // a post-indexed LDR instruction instead, per the ARM ARM.
4803 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
4804 Inst.getNumOperands() == 5) {
4806 TmpInst.setOpcode(ARM::LDR_POST_IMM);
4807 TmpInst.addOperand(Inst.getOperand(4)); // Rt
4808 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
4809 TmpInst.addOperand(Inst.getOperand(1)); // Rn
4810 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
4811 TmpInst.addOperand(MCOperand::CreateImm(4));
4812 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
4813 TmpInst.addOperand(Inst.getOperand(3));
4818 case ARM::STMDB_UPD:
4819 // If this is a store of a single register via a 'push', then we should use
4820 // a pre-indexed STR instruction instead, per the ARM ARM.
4821 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
4822 Inst.getNumOperands() == 5) {
4824 TmpInst.setOpcode(ARM::STR_PRE_IMM);
4825 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
4826 TmpInst.addOperand(Inst.getOperand(4)); // Rt
4827 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
4828 TmpInst.addOperand(MCOperand::CreateImm(-4));
4829 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
4830 TmpInst.addOperand(Inst.getOperand(3));
4835 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
4836 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
4837 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
4838 // to encoding T1 if <Rd> is omitted."
4839 if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
4840 Inst.setOpcode(ARM::tADDi3);
4845 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
4846 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
4847 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
4848 // to encoding T1 if <Rd> is omitted."
4849 if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
4850 Inst.setOpcode(ARM::tSUBi3);
4855 // A Thumb conditional branch outside of an IT block is a tBcc.
4856 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
4857 Inst.setOpcode(ARM::tBcc);
4862 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
4863 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
4864 Inst.setOpcode(ARM::t2Bcc);
4869 // If the conditional is AL or we're in an IT block, we really want t2B.
4870 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
4871 Inst.setOpcode(ARM::t2B);
4876 // If the conditional is AL, we really want tB.
4877 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
4878 Inst.setOpcode(ARM::tB);
4883 // If the register list contains any high registers, or if the writeback
4884 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
4885 // instead if we're in Thumb2. Otherwise, this should have generated
4886 // an error in validateInstruction().
4887 unsigned Rn = Inst.getOperand(0).getReg();
4888 bool hasWritebackToken =
4889 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
4890 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
4891 bool listContainsBase;
4892 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
4893 (!listContainsBase && !hasWritebackToken) ||
4894 (listContainsBase && hasWritebackToken)) {
4895 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
4896 assert (isThumbTwo());
4897 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
4898 // If we're switching to the updating version, we need to insert
4899 // the writeback tied operand.
4900 if (hasWritebackToken)
4901 Inst.insert(Inst.begin(),
4902 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
4907 case ARM::tSTMIA_UPD: {
4908 // If the register list contains any high registers, we need to use
4909 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
4910 // should have generated an error in validateInstruction().
4911 unsigned Rn = Inst.getOperand(0).getReg();
4912 bool listContainsBase;
4913 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
4914 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
4915 assert (isThumbTwo());
4916 Inst.setOpcode(ARM::t2STMIA_UPD);
4922 bool listContainsBase;
4923 // If the register list contains any high registers, we need to use
4924 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
4925 // should have generated an error in validateInstruction().
4926 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
4928 assert (isThumbTwo());
4929 Inst.setOpcode(ARM::t2LDMIA_UPD);
4930 // Add the base register and writeback operands.
4931 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
4932 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
4936 bool listContainsBase;
4937 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
4939 assert (isThumbTwo());
4940 Inst.setOpcode(ARM::t2STMDB_UPD);
4941 // Add the base register and writeback operands.
4942 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
4943 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
4947 // If we can use the 16-bit encoding and the user didn't explicitly
4948 // request the 32-bit variant, transform it here.
4949 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
4950 Inst.getOperand(1).getImm() <= 255 &&
4951 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
4952 Inst.getOperand(4).getReg() == ARM::CPSR) ||
4953 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
4954 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
4955 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
4956 // The operands aren't in the same order for tMOVi8...
4958 TmpInst.setOpcode(ARM::tMOVi8);
4959 TmpInst.addOperand(Inst.getOperand(0));
4960 TmpInst.addOperand(Inst.getOperand(4));
4961 TmpInst.addOperand(Inst.getOperand(1));
4962 TmpInst.addOperand(Inst.getOperand(2));
4963 TmpInst.addOperand(Inst.getOperand(3));
4970 // If we can use the 16-bit encoding and the user didn't explicitly
4971 // request the 32-bit variant, transform it here.
4972 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
4973 isARMLowRegister(Inst.getOperand(1).getReg()) &&
4974 Inst.getOperand(2).getImm() == ARMCC::AL &&
4975 Inst.getOperand(4).getReg() == ARM::CPSR &&
4976 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
4977 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
4978 // The operands aren't the same for tMOV[S]r... (no cc_out)
4980 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
4981 TmpInst.addOperand(Inst.getOperand(0));
4982 TmpInst.addOperand(Inst.getOperand(1));
4983 TmpInst.addOperand(Inst.getOperand(2));
4984 TmpInst.addOperand(Inst.getOperand(3));
4994 // If we can use the 16-bit encoding and the user didn't explicitly
4995 // request the 32-bit variant, transform it here.
4996 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
4997 isARMLowRegister(Inst.getOperand(1).getReg()) &&
4998 Inst.getOperand(2).getImm() == 0 &&
4999 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
5000 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
5002 switch (Inst.getOpcode()) {
5003 default: llvm_unreachable("Illegal opcode!");
5004 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
5005 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
5006 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
5007 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
5009 // The operands aren't the same for thumb1 (no rotate operand).
5011 TmpInst.setOpcode(NewOpc);
5012 TmpInst.addOperand(Inst.getOperand(0));
5013 TmpInst.addOperand(Inst.getOperand(1));
5014 TmpInst.addOperand(Inst.getOperand(3));
5015 TmpInst.addOperand(Inst.getOperand(4));
5022 // The mask bits for all but the first condition are represented as
5023 // the low bit of the condition code value implies 't'. We currently
5024 // always have 1 implies 't', so XOR toggle the bits if the low bit
5025 // of the condition code is zero. The encoding also expects the low
5026 // bit of the condition to be encoded as bit 4 of the mask operand,
5027 // so mask that in if needed
5028 MCOperand &MO = Inst.getOperand(1);
5029 unsigned Mask = MO.getImm();
5030 unsigned OrigMask = Mask;
5031 unsigned TZ = CountTrailingZeros_32(Mask);
5032 if ((Inst.getOperand(0).getImm() & 1) == 0) {
5033 assert(Mask && TZ <= 3 && "illegal IT mask value!");
5034 for (unsigned i = 3; i != TZ; --i)
5040 // Set up the IT block state according to the IT instruction we just
5042 assert(!inITBlock() && "nested IT blocks?!");
5043 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
5044 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
5045 ITState.CurPosition = 0;
5046 ITState.FirstCond = true;
5053 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
5054 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
5055 // suffix depending on whether they're in an IT block or not.
5056 unsigned Opc = Inst.getOpcode();
5057 const MCInstrDesc &MCID = getInstDesc(Opc);
5058 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
5059 assert(MCID.hasOptionalDef() &&
5060 "optionally flag setting instruction missing optional def operand");
5061 assert(MCID.NumOperands == Inst.getNumOperands() &&
5062 "operand count mismatch!");
5063 // Find the optional-def operand (cc_out).
5066 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
5069 // If we're parsing Thumb1, reject it completely.
5070 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
5071 return Match_MnemonicFail;
5072 // If we're parsing Thumb2, which form is legal depends on whether we're
5074 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
5076 return Match_RequiresITBlock;
5077 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
5079 return Match_RequiresNotITBlock;
5081 // Some high-register supporting Thumb1 encodings only allow both registers
5082 // to be from r0-r7 when in Thumb2.
5083 else if (Opc == ARM::tADDhirr && isThumbOne() &&
5084 isARMLowRegister(Inst.getOperand(1).getReg()) &&
5085 isARMLowRegister(Inst.getOperand(2).getReg()))
5086 return Match_RequiresThumb2;
5087 // Others only require ARMv6 or later.
5088 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
5089 isARMLowRegister(Inst.getOperand(0).getReg()) &&
5090 isARMLowRegister(Inst.getOperand(1).getReg()))
5091 return Match_RequiresV6;
5092 return Match_Success;
5096 MatchAndEmitInstruction(SMLoc IDLoc,
5097 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
5101 unsigned MatchResult;
5102 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
5103 switch (MatchResult) {
5106 // Context sensitive operand constraints aren't handled by the matcher,
5107 // so check them here.
5108 if (validateInstruction(Inst, Operands)) {
5109 // Still progress the IT block, otherwise one wrong condition causes
5110 // nasty cascading errors.
5111 forwardITPosition();
5115 // Some instructions need post-processing to, for example, tweak which
5116 // encoding is selected. Loop on it while changes happen so the
5117 // individual transformations can chain off each other. E.g.,
5118 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
5119 while (processInstruction(Inst, Operands))
5122 // Only move forward at the very end so that everything in validate
5123 // and process gets a consistent answer about whether we're in an IT
5125 forwardITPosition();
5127 Out.EmitInstruction(Inst);
5129 case Match_MissingFeature:
5130 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
5132 case Match_InvalidOperand: {
5133 SMLoc ErrorLoc = IDLoc;
5134 if (ErrorInfo != ~0U) {
5135 if (ErrorInfo >= Operands.size())
5136 return Error(IDLoc, "too few operands for instruction");
5138 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
5139 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
5142 return Error(ErrorLoc, "invalid operand for instruction");
5144 case Match_MnemonicFail:
5145 return Error(IDLoc, "invalid instruction");
5146 case Match_ConversionFail:
5147 // The converter function will have already emited a diagnostic.
5149 case Match_RequiresNotITBlock:
5150 return Error(IDLoc, "flag setting instruction only valid outside IT block");
5151 case Match_RequiresITBlock:
5152 return Error(IDLoc, "instruction only valid inside IT block");
5153 case Match_RequiresV6:
5154 return Error(IDLoc, "instruction variant requires ARMv6 or later");
5155 case Match_RequiresThumb2:
5156 return Error(IDLoc, "instruction variant requires Thumb2");
5159 llvm_unreachable("Implement any new match types added!");
5163 /// parseDirective parses the arm specific directives
5164 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
5165 StringRef IDVal = DirectiveID.getIdentifier();
5166 if (IDVal == ".word")
5167 return parseDirectiveWord(4, DirectiveID.getLoc());
5168 else if (IDVal == ".thumb")
5169 return parseDirectiveThumb(DirectiveID.getLoc());
5170 else if (IDVal == ".thumb_func")
5171 return parseDirectiveThumbFunc(DirectiveID.getLoc());
5172 else if (IDVal == ".code")
5173 return parseDirectiveCode(DirectiveID.getLoc());
5174 else if (IDVal == ".syntax")
5175 return parseDirectiveSyntax(DirectiveID.getLoc());
5179 /// parseDirectiveWord
5180 /// ::= .word [ expression (, expression)* ]
5181 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
5182 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5184 const MCExpr *Value;
5185 if (getParser().ParseExpression(Value))
5188 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
5190 if (getLexer().is(AsmToken::EndOfStatement))
5193 // FIXME: Improve diagnostic.
5194 if (getLexer().isNot(AsmToken::Comma))
5195 return Error(L, "unexpected token in directive");
5204 /// parseDirectiveThumb
5206 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
5207 if (getLexer().isNot(AsmToken::EndOfStatement))
5208 return Error(L, "unexpected token in directive");
5211 // TODO: set thumb mode
5212 // TODO: tell the MC streamer the mode
5213 // getParser().getStreamer().Emit???();
5217 /// parseDirectiveThumbFunc
5218 /// ::= .thumbfunc symbol_name
5219 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
5220 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
5221 bool isMachO = MAI.hasSubsectionsViaSymbols();
5224 // Darwin asm has function name after .thumb_func direction
5227 const AsmToken &Tok = Parser.getTok();
5228 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
5229 return Error(L, "unexpected token in .thumb_func directive");
5230 Name = Tok.getIdentifier();
5231 Parser.Lex(); // Consume the identifier token.
5234 if (getLexer().isNot(AsmToken::EndOfStatement))
5235 return Error(L, "unexpected token in directive");
5238 // FIXME: assuming function name will be the line following .thumb_func
5240 Name = Parser.getTok().getIdentifier();
5243 // Mark symbol as a thumb symbol.
5244 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
5245 getParser().getStreamer().EmitThumbFunc(Func);
5249 /// parseDirectiveSyntax
5250 /// ::= .syntax unified | divided
5251 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
5252 const AsmToken &Tok = Parser.getTok();
5253 if (Tok.isNot(AsmToken::Identifier))
5254 return Error(L, "unexpected token in .syntax directive");
5255 StringRef Mode = Tok.getString();
5256 if (Mode == "unified" || Mode == "UNIFIED")
5258 else if (Mode == "divided" || Mode == "DIVIDED")
5259 return Error(L, "'.syntax divided' arm asssembly not supported");
5261 return Error(L, "unrecognized syntax mode in .syntax directive");
5263 if (getLexer().isNot(AsmToken::EndOfStatement))
5264 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
5267 // TODO tell the MC streamer the mode
5268 // getParser().getStreamer().Emit???();
5272 /// parseDirectiveCode
5273 /// ::= .code 16 | 32
5274 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
5275 const AsmToken &Tok = Parser.getTok();
5276 if (Tok.isNot(AsmToken::Integer))
5277 return Error(L, "unexpected token in .code directive");
5278 int64_t Val = Parser.getTok().getIntVal();
5284 return Error(L, "invalid operand to .code directive");
5286 if (getLexer().isNot(AsmToken::EndOfStatement))
5287 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
5293 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
5297 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
5303 extern "C" void LLVMInitializeARMAsmLexer();
5305 /// Force static initialization.
5306 extern "C" void LLVMInitializeARMAsmParser() {
5307 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
5308 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
5309 LLVMInitializeARMAsmLexer();
5312 #define GET_REGISTER_MATCHER
5313 #define GET_MATCHER_IMPLEMENTATION
5314 #include "ARMGenAsmMatcher.inc"