1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "llvm/ADT/SmallVector.h"
12 #include "llvm/ADT/Twine.h"
13 #include "llvm/MC/MCAsmLexer.h"
14 #include "llvm/MC/MCAsmParser.h"
15 #include "llvm/MC/MCStreamer.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/Support/SourceMgr.h"
19 #include "llvm/Target/TargetRegistry.h"
20 #include "llvm/Target/TargetAsmParser.h"
26 // The shift types for register controlled shifts in arm memory addressing
35 class ARMAsmParser : public TargetAsmParser {
39 MCAsmParser &getParser() const { return Parser; }
41 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
43 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
45 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
47 bool ParseRegister(ARMOperand &Op);
49 bool ParseMemory(ARMOperand &Op);
51 bool ParseShift(enum ShiftType *St, const MCExpr *ShiftAmount);
53 bool ParseOperand(ARMOperand &Op);
55 bool ParseDirectiveWord(unsigned Size, SMLoc L);
57 // TODO - For now hacked versions of the next two are in here in this file to
58 // allow some parser testing until the table gen versions are implemented.
60 /// @name Auto-generated Match Functions
62 bool MatchInstruction(SmallVectorImpl<ARMOperand> &Operands,
65 /// MatchRegisterName - Match the given string to a register name, or 0 if
66 /// there is no match.
67 unsigned MatchRegisterName(const StringRef &Name);
73 ARMAsmParser(const Target &T, MCAsmParser &_Parser)
74 : TargetAsmParser(T), Parser(_Parser) {}
76 virtual bool ParseInstruction(const StringRef &Name, MCInst &Inst);
78 virtual bool ParseDirective(AsmToken DirectiveID);
81 } // end anonymous namespace
85 /// ARMOperand - Instances of this class represent a parsed ARM machine
106 // This is for all forms of ARM address expressions
110 const MCExpr *Offset; // used when OffsetIsReg is false
111 unsigned OffsetRegNum; // used when OffsetIsReg is true
112 bool OffsetRegShifted; // only used when OffsetIsReg is true
113 enum ShiftType ShiftType; // used when OffsetRegShifted is true
114 const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
117 bool Negative; // only used when OffsetIsReg is true
123 StringRef getToken() const {
124 assert(Kind == Token && "Invalid access!");
125 return StringRef(Tok.Data, Tok.Length);
128 unsigned getReg() const {
129 assert(Kind == Register && "Invalid access!");
133 bool isToken() const {return Kind == Token; }
135 bool isReg() const { return Kind == Register; }
137 void addRegOperands(MCInst &Inst, unsigned N) const {
138 assert(N == 1 && "Invalid number of operands!");
139 Inst.addOperand(MCOperand::CreateReg(getReg()));
142 static ARMOperand CreateToken(StringRef Str) {
145 Res.Tok.Data = Str.data();
146 Res.Tok.Length = Str.size();
150 static ARMOperand CreateReg(unsigned RegNum, bool Writeback) {
153 Res.Reg.RegNum = RegNum;
154 Res.Reg.Writeback = Writeback;
158 static ARMOperand CreateMem(unsigned BaseRegNum, bool OffsetIsReg,
159 const MCExpr *Offset, unsigned OffsetRegNum,
160 bool OffsetRegShifted, enum ShiftType ShiftType,
161 const MCExpr *ShiftAmount, bool Preindexed,
162 bool Postindexed, bool Negative, bool Writeback) {
165 Res.Mem.BaseRegNum = BaseRegNum;
166 Res.Mem.OffsetIsReg = OffsetIsReg;
167 Res.Mem.Offset = Offset;
168 Res.Mem.OffsetRegNum = OffsetRegNum;
169 Res.Mem.OffsetRegShifted = OffsetRegShifted;
170 Res.Mem.ShiftType = ShiftType;
171 Res.Mem.ShiftAmount = ShiftAmount;
172 Res.Mem.Preindexed = Preindexed;
173 Res.Mem.Postindexed = Postindexed;
174 Res.Mem.Negative = Negative;
175 Res.Mem.Writeback = Writeback;
180 } // end anonymous namespace.
182 // Try to parse a register name. The token must be an Identifier when called,
183 // and if it is a register name a Reg operand is created, the token is eaten
184 // and false is returned. Else true is returned and no token is eaten.
185 // TODO this is likely to change to allow different register types and or to
186 // parse for a specific register type.
187 bool ARMAsmParser::ParseRegister(ARMOperand &Op) {
188 const AsmToken &Tok = getLexer().getTok();
189 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
191 // FIXME: Validate register for the current architecture; we have to do
192 // validation later, so maybe there is no need for this here.
195 RegNum = MatchRegisterName(Tok.getString());
198 getLexer().Lex(); // Eat identifier token.
200 bool Writeback = false;
201 const AsmToken &ExclaimTok = getLexer().getTok();
202 if (ExclaimTok.is(AsmToken::Exclaim)) {
204 getLexer().Lex(); // Eat exclaim token
207 Op = ARMOperand::CreateReg(RegNum, Writeback);
212 // Try to parse an arm memory expression. It must start with a '[' token.
213 // TODO Only preindexing and postindexing addressing are started, unindexed
214 // with option, etc are still to do.
215 bool ARMAsmParser::ParseMemory(ARMOperand &Op) {
216 const AsmToken &LBracTok = getLexer().getTok();
217 assert(LBracTok.is(AsmToken::LBrac) && "Token is not an Left Bracket");
218 getLexer().Lex(); // Eat left bracket token.
220 const AsmToken &BaseRegTok = getLexer().getTok();
221 if (BaseRegTok.isNot(AsmToken::Identifier))
222 return Error(BaseRegTok.getLoc(), "register expected");
223 unsigned BaseRegNum = MatchRegisterName(BaseRegTok.getString());
225 return Error(BaseRegTok.getLoc(), "register expected");
226 getLexer().Lex(); // Eat identifier token.
228 bool Preindexed = false;
229 bool Postindexed = false;
230 bool OffsetIsReg = false;
231 bool Negative = false;
232 bool Writeback = false;
234 // First look for preindexed address forms:
237 // [Rn, +/-Rm, shift]
238 // that is after the "[Rn" we now have see if the next token is a comma.
239 const AsmToken &Tok = getLexer().getTok();
240 if (Tok.is(AsmToken::Comma)) {
242 getLexer().Lex(); // Eat comma token.
244 const AsmToken &NextTok = getLexer().getTok();
245 if (NextTok.is(AsmToken::Plus))
246 getLexer().Lex(); // Eat plus token.
247 else if (NextTok.is(AsmToken::Minus)) {
249 getLexer().Lex(); // Eat minus token
252 // See if there is a register following the "[Rn," we have so far.
253 const AsmToken &OffsetRegTok = getLexer().getTok();
254 unsigned OffsetRegNum = MatchRegisterName(OffsetRegTok.getString());
255 bool OffsetRegShifted = false;
256 enum ShiftType ShiftType;
257 const MCExpr *ShiftAmount;
258 const MCExpr *Offset;
259 if (OffsetRegNum != 0) {
261 getLexer().Lex(); // Eat identifier token for the offset register.
262 // Look for a comma then a shift
263 const AsmToken &Tok = getLexer().getTok();
264 if (Tok.is(AsmToken::Comma)) {
265 getLexer().Lex(); // Eat comma token.
267 const AsmToken &Tok = getLexer().getTok();
268 if (ParseShift(&ShiftType, ShiftAmount))
269 return Error(Tok.getLoc(), "shift expected");
270 OffsetRegShifted = true;
273 else { // "[Rn," we have so far was not followed by "Rm"
274 // Look for #offset following the "[Rn,"
275 const AsmToken &HashTok = getLexer().getTok();
276 if (HashTok.isNot(AsmToken::Hash))
277 return Error(HashTok.getLoc(), "'#' expected");
278 getLexer().Lex(); // Eat hash token.
280 if (getParser().ParseExpression(Offset))
283 const AsmToken &RBracTok = getLexer().getTok();
284 if (RBracTok.isNot(AsmToken::RBrac))
285 return Error(RBracTok.getLoc(), "']' expected");
286 getLexer().Lex(); // Eat right bracket token.
288 const AsmToken &ExclaimTok = getLexer().getTok();
289 if (ExclaimTok.is(AsmToken::Exclaim)) {
291 getLexer().Lex(); // Eat exclaim token
293 Op = ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
294 OffsetRegShifted, ShiftType, ShiftAmount,
295 Preindexed, Postindexed, Negative, Writeback);
298 // The "[Rn" we have so far was not followed by a comma.
299 else if (Tok.is(AsmToken::RBrac)) {
300 // This is a post indexing addressing forms:
303 // [Rn], +/-Rm, shift
304 // that is a ']' follows after the "[Rn".
307 getLexer().Lex(); // Eat right bracket token.
309 const AsmToken &CommaTok = getLexer().getTok();
310 if (CommaTok.isNot(AsmToken::Comma))
311 return Error(CommaTok.getLoc(), "',' expected");
312 getLexer().Lex(); // Eat comma token.
314 const AsmToken &NextTok = getLexer().getTok();
315 if (NextTok.is(AsmToken::Plus))
316 getLexer().Lex(); // Eat plus token.
317 else if (NextTok.is(AsmToken::Minus)) {
319 getLexer().Lex(); // Eat minus token
322 // See if there is a register following the "[Rn]," we have so far.
323 const AsmToken &OffsetRegTok = getLexer().getTok();
324 unsigned OffsetRegNum = MatchRegisterName(OffsetRegTok.getString());
325 bool OffsetRegShifted = false;
326 enum ShiftType ShiftType;
327 const MCExpr *ShiftAmount;
328 const MCExpr *Offset;
329 if (OffsetRegNum != 0) {
331 getLexer().Lex(); // Eat identifier token for the offset register.
332 // Look for a comma then a shift
333 const AsmToken &Tok = getLexer().getTok();
334 if (Tok.is(AsmToken::Comma)) {
335 getLexer().Lex(); // Eat comma token.
337 const AsmToken &Tok = getLexer().getTok();
338 if (ParseShift(&ShiftType, ShiftAmount))
339 return Error(Tok.getLoc(), "shift expected");
340 OffsetRegShifted = true;
343 else { // "[Rn]," we have so far was not followed by "Rm"
344 // Look for #offset following the "[Rn],"
345 const AsmToken &HashTok = getLexer().getTok();
346 if (HashTok.isNot(AsmToken::Hash))
347 return Error(HashTok.getLoc(), "'#' expected");
348 getLexer().Lex(); // Eat hash token.
350 if (getParser().ParseExpression(Offset))
353 Op = ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
354 OffsetRegShifted, ShiftType, ShiftAmount,
355 Preindexed, Postindexed, Negative, Writeback);
362 /// ParseShift as one of these two:
363 /// ( lsl | lsr | asr | ror ) , # shift_amount
365 /// and returns true if it parses a shift otherwise it returns false.
366 bool ARMAsmParser::ParseShift(ShiftType *St, const MCExpr *ShiftAmount) {
367 const AsmToken &Tok = getLexer().getTok();
368 if (Tok.isNot(AsmToken::Identifier))
370 const StringRef &ShiftName = Tok.getString();
371 if (ShiftName == "lsl" || ShiftName == "LSL")
373 else if (ShiftName == "lsr" || ShiftName == "LSR")
375 else if (ShiftName == "asr" || ShiftName == "ASR")
377 else if (ShiftName == "ror" || ShiftName == "ROR")
379 else if (ShiftName == "rrx" || ShiftName == "RRX")
383 getLexer().Lex(); // Eat shift type token.
385 // For all but a Rotate right there must be a '#' and a shift amount
387 // Look for # following the shift type
388 const AsmToken &HashTok = getLexer().getTok();
389 if (HashTok.isNot(AsmToken::Hash))
390 return Error(HashTok.getLoc(), "'#' expected");
391 getLexer().Lex(); // Eat hash token.
393 if (getParser().ParseExpression(ShiftAmount))
400 // A hack to allow some testing
401 unsigned ARMAsmParser::MatchRegisterName(const StringRef &Name) {
404 else if (Name == "r2")
406 else if (Name == "r3")
408 else if (Name == "sp")
413 // A hack to allow some testing
414 bool ARMAsmParser::MatchInstruction(SmallVectorImpl<ARMOperand> &Operands,
416 struct ARMOperand Op0 = Operands[0];
417 assert(Op0.Kind == ARMOperand::Token && "First operand not a Token");
418 const StringRef &Mnemonic = Op0.getToken();
419 if (Mnemonic == "add" ||
420 Mnemonic == "stmfd" ||
422 Mnemonic == "ldmfd" ||
429 // TODO - this is a work in progress
430 bool ARMAsmParser::ParseOperand(ARMOperand &Op) {
431 switch (getLexer().getKind()) {
432 case AsmToken::Identifier:
433 if (!ParseRegister(Op))
435 // TODO parse other operands that start with an identifier
437 case AsmToken::LBrac:
438 if (!ParseMemory(Op))
445 bool ARMAsmParser::ParseInstruction(const StringRef &Name, MCInst &Inst) {
446 SmallVector<ARMOperand, 7> Operands;
448 Operands.push_back(ARMOperand::CreateToken(Name));
450 SMLoc Loc = getLexer().getTok().getLoc();
451 if (getLexer().isNot(AsmToken::EndOfStatement)) {
453 // Read the first operand.
454 Operands.push_back(ARMOperand());
455 if (ParseOperand(Operands.back()))
458 while (getLexer().is(AsmToken::Comma)) {
459 getLexer().Lex(); // Eat the comma.
461 // Parse and remember the operand.
462 Operands.push_back(ARMOperand());
463 if (ParseOperand(Operands.back()))
467 if (!MatchInstruction(Operands, Inst))
470 Error(Loc, "ARMAsmParser::ParseInstruction only partly implemented");
474 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
475 StringRef IDVal = DirectiveID.getIdentifier();
476 if (IDVal == ".word")
477 return ParseDirectiveWord(4, DirectiveID.getLoc());
481 /// ParseDirectiveWord
482 /// ::= .word [ expression (, expression)* ]
483 bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
484 if (getLexer().isNot(AsmToken::EndOfStatement)) {
487 if (getParser().ParseExpression(Value))
490 getParser().getStreamer().EmitValue(Value, Size);
492 if (getLexer().is(AsmToken::EndOfStatement))
495 // FIXME: Improve diagnostic.
496 if (getLexer().isNot(AsmToken::Comma))
497 return Error(L, "unexpected token in directive");
506 // Force static initialization.
507 extern "C" void LLVMInitializeARMAsmParser() {
508 RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
509 RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);