1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "llvm/ADT/SmallVector.h"
12 #include "llvm/ADT/Twine.h"
13 #include "llvm/MC/MCAsmLexer.h"
14 #include "llvm/MC/MCAsmParser.h"
15 #include "llvm/MC/MCStreamer.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/Support/SourceMgr.h"
19 #include "llvm/Target/TargetRegistry.h"
20 #include "llvm/Target/TargetAsmParser.h"
26 // The shift types for register controlled shifts in arm memory addressing
35 class ARMAsmParser : public TargetAsmParser {
39 MCAsmParser &getParser() const { return Parser; }
41 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
43 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
45 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
47 bool ParseRegister(ARMOperand &Op);
49 bool ParseRegisterList(ARMOperand &Op);
51 bool ParseMemory(ARMOperand &Op);
53 bool ParseShift(enum ShiftType *St, const MCExpr *&ShiftAmount);
55 bool ParseOperand(ARMOperand &Op);
57 bool ParseDirectiveWord(unsigned Size, SMLoc L);
59 // TODO - For now hacked versions of the next two are in here in this file to
60 // allow some parser testing until the table gen versions are implemented.
62 /// @name Auto-generated Match Functions
64 bool MatchInstruction(SmallVectorImpl<ARMOperand> &Operands,
67 /// MatchRegisterName - Match the given string to a register name and return
68 /// its register number, or -1 if there is no match. To allow return values
69 /// to be used directly in register lists, arm registers have values between
71 int MatchRegisterName(const StringRef &Name);
77 ARMAsmParser(const Target &T, MCAsmParser &_Parser)
78 : TargetAsmParser(T), Parser(_Parser) {}
80 virtual bool ParseInstruction(const StringRef &Name, MCInst &Inst);
82 virtual bool ParseDirective(AsmToken DirectiveID);
85 } // end anonymous namespace
89 /// ARMOperand - Instances of this class represent a parsed ARM machine
115 // This is for all forms of ARM address expressions
119 const MCExpr *Offset; // used when OffsetIsReg is false
120 unsigned OffsetRegNum; // used when OffsetIsReg is true
121 bool OffsetRegShifted; // only used when OffsetIsReg is true
122 enum ShiftType ShiftType; // used when OffsetRegShifted is true
123 const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
126 bool Negative; // only used when OffsetIsReg is true
132 StringRef getToken() const {
133 assert(Kind == Token && "Invalid access!");
134 return StringRef(Tok.Data, Tok.Length);
137 unsigned getReg() const {
138 assert(Kind == Register && "Invalid access!");
142 const MCExpr *getImm() const {
143 assert(Kind == Immediate && "Invalid access!");
147 bool isToken() const {return Kind == Token; }
149 bool isReg() const { return Kind == Register; }
151 void addRegOperands(MCInst &Inst, unsigned N) const {
152 assert(N == 1 && "Invalid number of operands!");
153 Inst.addOperand(MCOperand::CreateReg(getReg()));
156 static ARMOperand CreateToken(StringRef Str) {
159 Res.Tok.Data = Str.data();
160 Res.Tok.Length = Str.size();
164 static ARMOperand CreateReg(unsigned RegNum, bool Writeback) {
167 Res.Reg.RegNum = RegNum;
168 Res.Reg.Writeback = Writeback;
172 static ARMOperand CreateImm(const MCExpr *Val) {
174 Res.Kind = Immediate;
179 static ARMOperand CreateMem(unsigned BaseRegNum, bool OffsetIsReg,
180 const MCExpr *Offset, unsigned OffsetRegNum,
181 bool OffsetRegShifted, enum ShiftType ShiftType,
182 const MCExpr *ShiftAmount, bool Preindexed,
183 bool Postindexed, bool Negative, bool Writeback) {
186 Res.Mem.BaseRegNum = BaseRegNum;
187 Res.Mem.OffsetIsReg = OffsetIsReg;
188 Res.Mem.Offset = Offset;
189 Res.Mem.OffsetRegNum = OffsetRegNum;
190 Res.Mem.OffsetRegShifted = OffsetRegShifted;
191 Res.Mem.ShiftType = ShiftType;
192 Res.Mem.ShiftAmount = ShiftAmount;
193 Res.Mem.Preindexed = Preindexed;
194 Res.Mem.Postindexed = Postindexed;
195 Res.Mem.Negative = Negative;
196 Res.Mem.Writeback = Writeback;
201 } // end anonymous namespace.
203 // Try to parse a register name. The token must be an Identifier when called,
204 // and if it is a register name a Reg operand is created, the token is eaten
205 // and false is returned. Else true is returned and no token is eaten.
206 // TODO this is likely to change to allow different register types and or to
207 // parse for a specific register type.
208 bool ARMAsmParser::ParseRegister(ARMOperand &Op) {
209 const AsmToken &Tok = getLexer().getTok();
210 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
212 // FIXME: Validate register for the current architecture; we have to do
213 // validation later, so maybe there is no need for this here.
216 RegNum = MatchRegisterName(Tok.getString());
219 getLexer().Lex(); // Eat identifier token.
221 bool Writeback = false;
222 const AsmToken &ExclaimTok = getLexer().getTok();
223 if (ExclaimTok.is(AsmToken::Exclaim)) {
225 getLexer().Lex(); // Eat exclaim token
228 Op = ARMOperand::CreateReg(RegNum, Writeback);
233 // Try to parse a register list. The first token must be a '{' when called
235 bool ARMAsmParser::ParseRegisterList(ARMOperand &Op) {
236 assert(getLexer().getTok().is(AsmToken::LCurly) &&
237 "Token is not an Left Curly Brace");
238 getLexer().Lex(); // Eat left curly brace token.
240 const AsmToken &RegTok = getLexer().getTok();
241 SMLoc RegLoc = RegTok.getLoc();
242 if (RegTok.isNot(AsmToken::Identifier))
243 return Error(RegLoc, "register expected");
244 int RegNum = MatchRegisterName(RegTok.getString());
246 return Error(RegLoc, "register expected");
247 getLexer().Lex(); // Eat identifier token.
248 unsigned RegList = 1 << RegNum;
250 int HighRegNum = RegNum;
251 // TODO ranges like "{Rn-Rm}"
252 while (getLexer().getTok().is(AsmToken::Comma)) {
253 getLexer().Lex(); // Eat comma token.
255 const AsmToken &RegTok = getLexer().getTok();
256 SMLoc RegLoc = RegTok.getLoc();
257 if (RegTok.isNot(AsmToken::Identifier))
258 return Error(RegLoc, "register expected");
259 int RegNum = MatchRegisterName(RegTok.getString());
261 return Error(RegLoc, "register expected");
263 if (RegList & (1 << RegNum))
264 Warning(RegLoc, "register duplicated in register list");
265 else if (RegNum <= HighRegNum)
266 Warning(RegLoc, "register not in ascending order in register list");
267 RegList |= 1 << RegNum;
270 getLexer().Lex(); // Eat identifier token.
272 const AsmToken &RCurlyTok = getLexer().getTok();
273 if (RCurlyTok.isNot(AsmToken::RCurly))
274 return Error(RCurlyTok.getLoc(), "'}' expected");
275 getLexer().Lex(); // Eat left curly brace token.
280 // Try to parse an arm memory expression. It must start with a '[' token.
281 // TODO Only preindexing and postindexing addressing are started, unindexed
282 // with option, etc are still to do.
283 bool ARMAsmParser::ParseMemory(ARMOperand &Op) {
284 assert(getLexer().getTok().is(AsmToken::LBrac) &&
285 "Token is not an Left Bracket");
286 getLexer().Lex(); // Eat left bracket token.
288 const AsmToken &BaseRegTok = getLexer().getTok();
289 if (BaseRegTok.isNot(AsmToken::Identifier))
290 return Error(BaseRegTok.getLoc(), "register expected");
291 int BaseRegNum = MatchRegisterName(BaseRegTok.getString());
292 if (BaseRegNum == -1)
293 return Error(BaseRegTok.getLoc(), "register expected");
294 getLexer().Lex(); // Eat identifier token.
296 bool Preindexed = false;
297 bool Postindexed = false;
298 bool OffsetIsReg = false;
299 bool Negative = false;
300 bool Writeback = false;
302 // First look for preindexed address forms:
305 // [Rn, +/-Rm, shift]
306 // that is after the "[Rn" we now have see if the next token is a comma.
307 const AsmToken &Tok = getLexer().getTok();
308 if (Tok.is(AsmToken::Comma)) {
310 getLexer().Lex(); // Eat comma token.
312 const AsmToken &NextTok = getLexer().getTok();
313 if (NextTok.is(AsmToken::Plus))
314 getLexer().Lex(); // Eat plus token.
315 else if (NextTok.is(AsmToken::Minus)) {
317 getLexer().Lex(); // Eat minus token
320 // See if there is a register following the "[Rn," we have so far.
321 const AsmToken &OffsetRegTok = getLexer().getTok();
322 int OffsetRegNum = MatchRegisterName(OffsetRegTok.getString());
323 bool OffsetRegShifted = false;
324 enum ShiftType ShiftType;
325 const MCExpr *ShiftAmount;
326 const MCExpr *Offset;
327 if (OffsetRegNum != -1) {
329 getLexer().Lex(); // Eat identifier token for the offset register.
330 // Look for a comma then a shift
331 const AsmToken &Tok = getLexer().getTok();
332 if (Tok.is(AsmToken::Comma)) {
333 getLexer().Lex(); // Eat comma token.
335 const AsmToken &Tok = getLexer().getTok();
336 if (ParseShift(&ShiftType, ShiftAmount))
337 return Error(Tok.getLoc(), "shift expected");
338 OffsetRegShifted = true;
341 else { // "[Rn," we have so far was not followed by "Rm"
342 // Look for #offset following the "[Rn,"
343 const AsmToken &HashTok = getLexer().getTok();
344 if (HashTok.isNot(AsmToken::Hash))
345 return Error(HashTok.getLoc(), "'#' expected");
346 getLexer().Lex(); // Eat hash token.
348 if (getParser().ParseExpression(Offset))
351 const AsmToken &RBracTok = getLexer().getTok();
352 if (RBracTok.isNot(AsmToken::RBrac))
353 return Error(RBracTok.getLoc(), "']' expected");
354 getLexer().Lex(); // Eat right bracket token.
356 const AsmToken &ExclaimTok = getLexer().getTok();
357 if (ExclaimTok.is(AsmToken::Exclaim)) {
359 getLexer().Lex(); // Eat exclaim token
361 Op = ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
362 OffsetRegShifted, ShiftType, ShiftAmount,
363 Preindexed, Postindexed, Negative, Writeback);
366 // The "[Rn" we have so far was not followed by a comma.
367 else if (Tok.is(AsmToken::RBrac)) {
368 // This is a post indexing addressing forms:
371 // [Rn], +/-Rm, shift
372 // that is a ']' follows after the "[Rn".
375 getLexer().Lex(); // Eat right bracket token.
377 const AsmToken &CommaTok = getLexer().getTok();
378 if (CommaTok.isNot(AsmToken::Comma))
379 return Error(CommaTok.getLoc(), "',' expected");
380 getLexer().Lex(); // Eat comma token.
382 const AsmToken &NextTok = getLexer().getTok();
383 if (NextTok.is(AsmToken::Plus))
384 getLexer().Lex(); // Eat plus token.
385 else if (NextTok.is(AsmToken::Minus)) {
387 getLexer().Lex(); // Eat minus token
390 // See if there is a register following the "[Rn]," we have so far.
391 const AsmToken &OffsetRegTok = getLexer().getTok();
392 int OffsetRegNum = MatchRegisterName(OffsetRegTok.getString());
393 bool OffsetRegShifted = false;
394 enum ShiftType ShiftType;
395 const MCExpr *ShiftAmount;
396 const MCExpr *Offset;
397 if (OffsetRegNum != -1) {
399 getLexer().Lex(); // Eat identifier token for the offset register.
400 // Look for a comma then a shift
401 const AsmToken &Tok = getLexer().getTok();
402 if (Tok.is(AsmToken::Comma)) {
403 getLexer().Lex(); // Eat comma token.
405 const AsmToken &Tok = getLexer().getTok();
406 if (ParseShift(&ShiftType, ShiftAmount))
407 return Error(Tok.getLoc(), "shift expected");
408 OffsetRegShifted = true;
411 else { // "[Rn]," we have so far was not followed by "Rm"
412 // Look for #offset following the "[Rn],"
413 const AsmToken &HashTok = getLexer().getTok();
414 if (HashTok.isNot(AsmToken::Hash))
415 return Error(HashTok.getLoc(), "'#' expected");
416 getLexer().Lex(); // Eat hash token.
418 if (getParser().ParseExpression(Offset))
421 Op = ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
422 OffsetRegShifted, ShiftType, ShiftAmount,
423 Preindexed, Postindexed, Negative, Writeback);
430 /// ParseShift as one of these two:
431 /// ( lsl | lsr | asr | ror ) , # shift_amount
433 /// and returns true if it parses a shift otherwise it returns false.
434 bool ARMAsmParser::ParseShift(ShiftType *St, const MCExpr *&ShiftAmount) {
435 const AsmToken &Tok = getLexer().getTok();
436 if (Tok.isNot(AsmToken::Identifier))
438 const StringRef &ShiftName = Tok.getString();
439 if (ShiftName == "lsl" || ShiftName == "LSL")
441 else if (ShiftName == "lsr" || ShiftName == "LSR")
443 else if (ShiftName == "asr" || ShiftName == "ASR")
445 else if (ShiftName == "ror" || ShiftName == "ROR")
447 else if (ShiftName == "rrx" || ShiftName == "RRX")
451 getLexer().Lex(); // Eat shift type token.
453 // For all but a Rotate right there must be a '#' and a shift amount
455 // Look for # following the shift type
456 const AsmToken &HashTok = getLexer().getTok();
457 if (HashTok.isNot(AsmToken::Hash))
458 return Error(HashTok.getLoc(), "'#' expected");
459 getLexer().Lex(); // Eat hash token.
461 if (getParser().ParseExpression(ShiftAmount))
468 // A hack to allow some testing
469 int ARMAsmParser::MatchRegisterName(const StringRef &Name) {
470 if (Name == "r0" || Name == "R0")
472 else if (Name == "r1" || Name == "R1")
474 else if (Name == "r2" || Name == "R2")
476 else if (Name == "r3" || Name == "R3")
478 else if (Name == "r3" || Name == "R3")
480 else if (Name == "r4" || Name == "R4")
482 else if (Name == "r5" || Name == "R5")
484 else if (Name == "r6" || Name == "R6")
486 else if (Name == "r7" || Name == "R7")
488 else if (Name == "r8" || Name == "R8")
490 else if (Name == "r9" || Name == "R9")
492 else if (Name == "r10" || Name == "R10")
494 else if (Name == "r11" || Name == "R11" || Name == "fp")
496 else if (Name == "r12" || Name == "R12" || Name == "ip")
498 else if (Name == "r13" || Name == "R13" || Name == "sp")
500 else if (Name == "r14" || Name == "R14" || Name == "lr")
502 else if (Name == "r15" || Name == "R15" || Name == "pc")
507 // A hack to allow some testing
508 bool ARMAsmParser::MatchInstruction(SmallVectorImpl<ARMOperand> &Operands,
510 struct ARMOperand Op0 = Operands[0];
511 assert(Op0.Kind == ARMOperand::Token && "First operand not a Token");
512 const StringRef &Mnemonic = Op0.getToken();
513 if (Mnemonic == "add" ||
514 Mnemonic == "stmfd" ||
516 Mnemonic == "ldmfd" ||
525 // TODO - this is a work in progress
526 bool ARMAsmParser::ParseOperand(ARMOperand &Op) {
527 switch (getLexer().getKind()) {
528 case AsmToken::Identifier:
529 if (!ParseRegister(Op))
531 // TODO parse other operands that start with an identifier like labels
532 return Error(getLexer().getTok().getLoc(), "labels not yet supported");
533 case AsmToken::LBrac:
534 if (!ParseMemory(Op))
536 case AsmToken::LCurly:
537 if (!ParseRegisterList(Op))
543 if (getParser().ParseExpression(Val))
545 Op = ARMOperand::CreateImm(Val);
548 return Error(getLexer().getTok().getLoc(), "unexpected token in operand");
552 bool ARMAsmParser::ParseInstruction(const StringRef &Name, MCInst &Inst) {
553 SmallVector<ARMOperand, 7> Operands;
555 Operands.push_back(ARMOperand::CreateToken(Name));
557 SMLoc Loc = getLexer().getTok().getLoc();
558 if (getLexer().isNot(AsmToken::EndOfStatement)) {
560 // Read the first operand.
561 Operands.push_back(ARMOperand());
562 if (ParseOperand(Operands.back()))
565 while (getLexer().is(AsmToken::Comma)) {
566 getLexer().Lex(); // Eat the comma.
568 // Parse and remember the operand.
569 Operands.push_back(ARMOperand());
570 if (ParseOperand(Operands.back()))
574 if (!MatchInstruction(Operands, Inst))
577 Error(Loc, "ARMAsmParser::ParseInstruction only partly implemented");
581 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
582 StringRef IDVal = DirectiveID.getIdentifier();
583 if (IDVal == ".word")
584 return ParseDirectiveWord(4, DirectiveID.getLoc());
588 /// ParseDirectiveWord
589 /// ::= .word [ expression (, expression)* ]
590 bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
591 if (getLexer().isNot(AsmToken::EndOfStatement)) {
594 if (getParser().ParseExpression(Value))
597 getParser().getStreamer().EmitValue(Value, Size);
599 if (getLexer().is(AsmToken::EndOfStatement))
602 // FIXME: Improve diagnostic.
603 if (getLexer().isNot(AsmToken::Comma))
604 return Error(L, "unexpected token in directive");
613 // Force static initialization.
614 extern "C" void LLVMInitializeARMAsmParser() {
615 RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
616 RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);