1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "ARMFPUName.h"
11 #include "ARMFeatures.h"
12 #include "MCTargetDesc/ARMAddressingModes.h"
13 #include "MCTargetDesc/ARMArchName.h"
14 #include "MCTargetDesc/ARMBaseInfo.h"
15 #include "MCTargetDesc/ARMMCExpr.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/ADT/Twine.h"
21 #include "llvm/MC/MCAsmInfo.h"
22 #include "llvm/MC/MCAssembler.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCDisassembler.h"
25 #include "llvm/MC/MCELF.h"
26 #include "llvm/MC/MCELFStreamer.h"
27 #include "llvm/MC/MCELFSymbolFlags.h"
28 #include "llvm/MC/MCExpr.h"
29 #include "llvm/MC/MCInst.h"
30 #include "llvm/MC/MCInstrDesc.h"
31 #include "llvm/MC/MCInstrInfo.h"
32 #include "llvm/MC/MCObjectFileInfo.h"
33 #include "llvm/MC/MCParser/MCAsmLexer.h"
34 #include "llvm/MC/MCParser/MCAsmParser.h"
35 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
36 #include "llvm/MC/MCRegisterInfo.h"
37 #include "llvm/MC/MCSection.h"
38 #include "llvm/MC/MCStreamer.h"
39 #include "llvm/MC/MCSubtargetInfo.h"
40 #include "llvm/MC/MCSymbol.h"
41 #include "llvm/MC/MCTargetAsmParser.h"
42 #include "llvm/Support/ARMBuildAttributes.h"
43 #include "llvm/Support/ARMEHABI.h"
44 #include "llvm/Support/COFF.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/ELF.h"
47 #include "llvm/Support/MathExtras.h"
48 #include "llvm/Support/SourceMgr.h"
49 #include "llvm/Support/TargetRegistry.h"
50 #include "llvm/Support/raw_ostream.h"
58 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
63 typedef SmallVector<SMLoc, 4> Locs;
68 Locs PersonalityIndexLocs;
73 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
75 bool hasFnStart() const { return !FnStartLocs.empty(); }
76 bool cantUnwind() const { return !CantUnwindLocs.empty(); }
77 bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
78 bool hasPersonality() const {
79 return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
82 void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
83 void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
84 void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
85 void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
86 void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
88 void saveFPReg(int Reg) { FPReg = Reg; }
89 int getFPReg() const { return FPReg; }
91 void emitFnStartLocNotes() const {
92 for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
94 Parser.Note(*FI, ".fnstart was specified here");
96 void emitCantUnwindLocNotes() const {
97 for (Locs::const_iterator UI = CantUnwindLocs.begin(),
98 UE = CantUnwindLocs.end(); UI != UE; ++UI)
99 Parser.Note(*UI, ".cantunwind was specified here");
101 void emitHandlerDataLocNotes() const {
102 for (Locs::const_iterator HI = HandlerDataLocs.begin(),
103 HE = HandlerDataLocs.end(); HI != HE; ++HI)
104 Parser.Note(*HI, ".handlerdata was specified here");
106 void emitPersonalityLocNotes() const {
107 for (Locs::const_iterator PI = PersonalityLocs.begin(),
108 PE = PersonalityLocs.end(),
109 PII = PersonalityIndexLocs.begin(),
110 PIE = PersonalityIndexLocs.end();
111 PI != PE || PII != PIE;) {
112 if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
113 Parser.Note(*PI++, ".personality was specified here");
114 else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
115 Parser.Note(*PII++, ".personalityindex was specified here");
117 llvm_unreachable(".personality and .personalityindex cannot be "
118 "at the same location");
123 FnStartLocs = Locs();
124 CantUnwindLocs = Locs();
125 PersonalityLocs = Locs();
126 HandlerDataLocs = Locs();
127 PersonalityIndexLocs = Locs();
132 class ARMAsmParser : public MCTargetAsmParser {
133 MCSubtargetInfo &STI;
135 const MCInstrInfo &MII;
136 const MCRegisterInfo *MRI;
139 ARMTargetStreamer &getTargetStreamer() {
140 MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
141 return static_cast<ARMTargetStreamer &>(TS);
144 // Map of register aliases registers via the .req directive.
145 StringMap<unsigned> RegisterReqs;
147 bool NextSymbolIsThumb;
150 ARMCC::CondCodes Cond; // Condition for IT block.
151 unsigned Mask:4; // Condition mask for instructions.
152 // Starting at first 1 (from lsb).
153 // '1' condition as indicated in IT.
154 // '0' inverse of condition (else).
155 // Count of instructions in IT block is
156 // 4 - trailingzeroes(mask)
158 bool FirstCond; // Explicit flag for when we're parsing the
159 // First instruction in the IT block. It's
160 // implied in the mask, so needs special
163 unsigned CurPosition; // Current position in parsing of IT
164 // block. In range [0,3]. Initialized
165 // according to count of instructions in block.
166 // ~0U if no active IT block.
168 bool inITBlock() { return ITState.CurPosition != ~0U;}
169 void forwardITPosition() {
170 if (!inITBlock()) return;
171 // Move to the next instruction in the IT block, if there is one. If not,
172 // mark the block as done.
173 unsigned TZ = countTrailingZeros(ITState.Mask);
174 if (++ITState.CurPosition == 5 - TZ)
175 ITState.CurPosition = ~0U; // Done with the IT block after this.
179 MCAsmParser &getParser() const { return Parser; }
180 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
182 void Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges = None) {
183 return Parser.Note(L, Msg, Ranges);
185 bool Warning(SMLoc L, const Twine &Msg,
186 ArrayRef<SMRange> Ranges = None) {
187 return Parser.Warning(L, Msg, Ranges);
189 bool Error(SMLoc L, const Twine &Msg,
190 ArrayRef<SMRange> Ranges = None) {
191 return Parser.Error(L, Msg, Ranges);
194 int tryParseRegister();
195 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
196 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
197 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
198 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
199 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
200 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
201 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
202 unsigned &ShiftAmount);
203 bool parseLiteralValues(unsigned Size, SMLoc L);
204 bool parseDirectiveThumb(SMLoc L);
205 bool parseDirectiveARM(SMLoc L);
206 bool parseDirectiveThumbFunc(SMLoc L);
207 bool parseDirectiveCode(SMLoc L);
208 bool parseDirectiveSyntax(SMLoc L);
209 bool parseDirectiveReq(StringRef Name, SMLoc L);
210 bool parseDirectiveUnreq(SMLoc L);
211 bool parseDirectiveArch(SMLoc L);
212 bool parseDirectiveEabiAttr(SMLoc L);
213 bool parseDirectiveCPU(SMLoc L);
214 bool parseDirectiveFPU(SMLoc L);
215 bool parseDirectiveFnStart(SMLoc L);
216 bool parseDirectiveFnEnd(SMLoc L);
217 bool parseDirectiveCantUnwind(SMLoc L);
218 bool parseDirectivePersonality(SMLoc L);
219 bool parseDirectiveHandlerData(SMLoc L);
220 bool parseDirectiveSetFP(SMLoc L);
221 bool parseDirectivePad(SMLoc L);
222 bool parseDirectiveRegSave(SMLoc L, bool IsVector);
223 bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
224 bool parseDirectiveLtorg(SMLoc L);
225 bool parseDirectiveEven(SMLoc L);
226 bool parseDirectivePersonalityIndex(SMLoc L);
227 bool parseDirectiveUnwindRaw(SMLoc L);
228 bool parseDirectiveTLSDescSeq(SMLoc L);
229 bool parseDirectiveMovSP(SMLoc L);
230 bool parseDirectiveObjectArch(SMLoc L);
231 bool parseDirectiveArchExtension(SMLoc L);
232 bool parseDirectiveAlign(SMLoc L);
233 bool parseDirectiveThumbSet(SMLoc L);
235 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
236 bool &CarrySetting, unsigned &ProcessorIMod,
238 void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
239 bool &CanAcceptCarrySet,
240 bool &CanAcceptPredicationCode);
242 bool isThumb() const {
243 // FIXME: Can tablegen auto-generate this?
244 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
246 bool isThumbOne() const {
247 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
249 bool isThumbTwo() const {
250 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
252 bool hasThumb() const {
253 return STI.getFeatureBits() & ARM::HasV4TOps;
255 bool hasV6Ops() const {
256 return STI.getFeatureBits() & ARM::HasV6Ops;
258 bool hasV6MOps() const {
259 return STI.getFeatureBits() & ARM::HasV6MOps;
261 bool hasV7Ops() const {
262 return STI.getFeatureBits() & ARM::HasV7Ops;
264 bool hasV8Ops() const {
265 return STI.getFeatureBits() & ARM::HasV8Ops;
267 bool hasARM() const {
268 return !(STI.getFeatureBits() & ARM::FeatureNoARM);
272 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
273 setAvailableFeatures(FB);
275 bool isMClass() const {
276 return STI.getFeatureBits() & ARM::FeatureMClass;
279 /// @name Auto-generated Match Functions
282 #define GET_ASSEMBLER_HEADER
283 #include "ARMGenAsmMatcher.inc"
287 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
288 OperandMatchResultTy parseCoprocNumOperand(
289 SmallVectorImpl<MCParsedAsmOperand*>&);
290 OperandMatchResultTy parseCoprocRegOperand(
291 SmallVectorImpl<MCParsedAsmOperand*>&);
292 OperandMatchResultTy parseCoprocOptionOperand(
293 SmallVectorImpl<MCParsedAsmOperand*>&);
294 OperandMatchResultTy parseMemBarrierOptOperand(
295 SmallVectorImpl<MCParsedAsmOperand*>&);
296 OperandMatchResultTy parseInstSyncBarrierOptOperand(
297 SmallVectorImpl<MCParsedAsmOperand*>&);
298 OperandMatchResultTy parseProcIFlagsOperand(
299 SmallVectorImpl<MCParsedAsmOperand*>&);
300 OperandMatchResultTy parseMSRMaskOperand(
301 SmallVectorImpl<MCParsedAsmOperand*>&);
302 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
303 StringRef Op, int Low, int High);
304 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
305 return parsePKHImm(O, "lsl", 0, 31);
307 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
308 return parsePKHImm(O, "asr", 1, 32);
310 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
311 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
312 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
313 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
314 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
315 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
316 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
317 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
318 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
321 // Asm Match Converter Methods
322 void cvtThumbMultiply(MCInst &Inst,
323 const SmallVectorImpl<MCParsedAsmOperand*> &);
324 void cvtThumbBranches(MCInst &Inst,
325 const SmallVectorImpl<MCParsedAsmOperand*> &);
327 bool validateInstruction(MCInst &Inst,
328 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
329 bool processInstruction(MCInst &Inst,
330 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
331 bool shouldOmitCCOutOperand(StringRef Mnemonic,
332 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
333 bool shouldOmitPredicateOperand(StringRef Mnemonic,
334 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
336 enum ARMMatchResultTy {
337 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
338 Match_RequiresNotITBlock,
340 Match_RequiresThumb2,
341 #define GET_OPERAND_DIAGNOSTIC_TYPES
342 #include "ARMGenAsmMatcher.inc"
346 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
347 const MCInstrInfo &MII,
348 const MCTargetOptions &Options)
349 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(MII), UC(_Parser) {
350 MCAsmParserExtension::Initialize(_Parser);
352 // Cache the MCRegisterInfo.
353 MRI = getContext().getRegisterInfo();
355 // Initialize the set of available features.
356 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
358 // Not in an ITBlock to start with.
359 ITState.CurPosition = ~0U;
361 NextSymbolIsThumb = false;
364 // Implementation of the MCTargetAsmParser interface:
365 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
367 ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
369 SmallVectorImpl<MCParsedAsmOperand*> &Operands) override;
370 bool ParseDirective(AsmToken DirectiveID) override;
372 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op,
373 unsigned Kind) override;
374 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
376 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
377 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
378 MCStreamer &Out, unsigned &ErrorInfo,
379 bool MatchingInlineAsm) override;
380 void onLabelParsed(MCSymbol *Symbol) override;
382 } // end anonymous namespace
386 /// ARMOperand - Instances of this class represent a parsed ARM machine
388 class ARMOperand : public MCParsedAsmOperand {
398 k_InstSyncBarrierOpt,
409 k_VectorListAllLanes,
415 k_BitfieldDescriptor,
419 SMLoc StartLoc, EndLoc, AlignmentLoc;
420 SmallVector<unsigned, 8> Registers;
423 ARMCC::CondCodes Val;
430 struct CoprocOptionOp {
443 ARM_ISB::InstSyncBOpt Val;
447 ARM_PROC::IFlags Val;
463 // A vector register list is a sequential list of 1 to 4 registers.
464 struct VectorListOp {
471 struct VectorIndexOp {
479 /// Combined record for all forms of ARM address expressions.
482 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
484 const MCConstantExpr *OffsetImm; // Offset immediate value
485 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
486 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
487 unsigned ShiftImm; // shift for OffsetReg.
488 unsigned Alignment; // 0 = no alignment specified
489 // n = alignment in bytes (2, 4, 8, 16, or 32)
490 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
493 struct PostIdxRegOp {
496 ARM_AM::ShiftOpc ShiftTy;
500 struct ShifterImmOp {
505 struct RegShiftedRegOp {
506 ARM_AM::ShiftOpc ShiftTy;
512 struct RegShiftedImmOp {
513 ARM_AM::ShiftOpc ShiftTy;
530 struct CoprocOptionOp CoprocOption;
531 struct MBOptOp MBOpt;
532 struct ISBOptOp ISBOpt;
533 struct ITMaskOp ITMask;
534 struct IFlagsOp IFlags;
535 struct MMaskOp MMask;
538 struct VectorListOp VectorList;
539 struct VectorIndexOp VectorIndex;
541 struct MemoryOp Memory;
542 struct PostIdxRegOp PostIdxReg;
543 struct ShifterImmOp ShifterImm;
544 struct RegShiftedRegOp RegShiftedReg;
545 struct RegShiftedImmOp RegShiftedImm;
546 struct RotImmOp RotImm;
547 struct BitfieldOp Bitfield;
550 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
552 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
554 StartLoc = o.StartLoc;
571 case k_DPRRegisterList:
572 case k_SPRRegisterList:
573 Registers = o.Registers;
576 case k_VectorListAllLanes:
577 case k_VectorListIndexed:
578 VectorList = o.VectorList;
585 CoprocOption = o.CoprocOption;
590 case k_MemBarrierOpt:
593 case k_InstSyncBarrierOpt:
598 case k_PostIndexRegister:
599 PostIdxReg = o.PostIdxReg;
607 case k_ShifterImmediate:
608 ShifterImm = o.ShifterImm;
610 case k_ShiftedRegister:
611 RegShiftedReg = o.RegShiftedReg;
613 case k_ShiftedImmediate:
614 RegShiftedImm = o.RegShiftedImm;
616 case k_RotateImmediate:
619 case k_BitfieldDescriptor:
620 Bitfield = o.Bitfield;
623 VectorIndex = o.VectorIndex;
628 /// getStartLoc - Get the location of the first token of this operand.
629 SMLoc getStartLoc() const override { return StartLoc; }
630 /// getEndLoc - Get the location of the last token of this operand.
631 SMLoc getEndLoc() const override { return EndLoc; }
632 /// getLocRange - Get the range between the first and last token of this
634 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
636 /// getAlignmentLoc - Get the location of the Alignment token of this operand.
637 SMLoc getAlignmentLoc() const {
638 assert(Kind == k_Memory && "Invalid access!");
642 ARMCC::CondCodes getCondCode() const {
643 assert(Kind == k_CondCode && "Invalid access!");
647 unsigned getCoproc() const {
648 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
652 StringRef getToken() const {
653 assert(Kind == k_Token && "Invalid access!");
654 return StringRef(Tok.Data, Tok.Length);
657 unsigned getReg() const override {
658 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
662 const SmallVectorImpl<unsigned> &getRegList() const {
663 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
664 Kind == k_SPRRegisterList) && "Invalid access!");
668 const MCExpr *getImm() const {
669 assert(isImm() && "Invalid access!");
673 unsigned getVectorIndex() const {
674 assert(Kind == k_VectorIndex && "Invalid access!");
675 return VectorIndex.Val;
678 ARM_MB::MemBOpt getMemBarrierOpt() const {
679 assert(Kind == k_MemBarrierOpt && "Invalid access!");
683 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
684 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
688 ARM_PROC::IFlags getProcIFlags() const {
689 assert(Kind == k_ProcIFlags && "Invalid access!");
693 unsigned getMSRMask() const {
694 assert(Kind == k_MSRMask && "Invalid access!");
698 bool isCoprocNum() const { return Kind == k_CoprocNum; }
699 bool isCoprocReg() const { return Kind == k_CoprocReg; }
700 bool isCoprocOption() const { return Kind == k_CoprocOption; }
701 bool isCondCode() const { return Kind == k_CondCode; }
702 bool isCCOut() const { return Kind == k_CCOut; }
703 bool isITMask() const { return Kind == k_ITCondMask; }
704 bool isITCondCode() const { return Kind == k_CondCode; }
705 bool isImm() const override { return Kind == k_Immediate; }
706 // checks whether this operand is an unsigned offset which fits is a field
707 // of specified width and scaled by a specific number of bits
708 template<unsigned width, unsigned scale>
709 bool isUnsignedOffset() const {
710 if (!isImm()) return false;
711 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
712 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
713 int64_t Val = CE->getValue();
714 int64_t Align = 1LL << scale;
715 int64_t Max = Align * ((1LL << width) - 1);
716 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
720 // checks whether this operand is an signed offset which fits is a field
721 // of specified width and scaled by a specific number of bits
722 template<unsigned width, unsigned scale>
723 bool isSignedOffset() const {
724 if (!isImm()) return false;
725 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
726 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
727 int64_t Val = CE->getValue();
728 int64_t Align = 1LL << scale;
729 int64_t Max = Align * ((1LL << (width-1)) - 1);
730 int64_t Min = -Align * (1LL << (width-1));
731 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
736 // checks whether this operand is a memory operand computed as an offset
737 // applied to PC. the offset may have 8 bits of magnitude and is represented
738 // with two bits of shift. textually it may be either [pc, #imm], #imm or
739 // relocable expression...
740 bool isThumbMemPC() const {
743 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
744 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
745 if (!CE) return false;
746 Val = CE->getValue();
749 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
750 if(Memory.BaseRegNum != ARM::PC) return false;
751 Val = Memory.OffsetImm->getValue();
754 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
756 bool isFPImm() const {
757 if (!isImm()) return false;
758 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
759 if (!CE) return false;
760 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
763 bool isFBits16() const {
764 if (!isImm()) return false;
765 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
766 if (!CE) return false;
767 int64_t Value = CE->getValue();
768 return Value >= 0 && Value <= 16;
770 bool isFBits32() const {
771 if (!isImm()) return false;
772 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
773 if (!CE) return false;
774 int64_t Value = CE->getValue();
775 return Value >= 1 && Value <= 32;
777 bool isImm8s4() const {
778 if (!isImm()) return false;
779 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
780 if (!CE) return false;
781 int64_t Value = CE->getValue();
782 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
784 bool isImm0_1020s4() const {
785 if (!isImm()) return false;
786 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
787 if (!CE) return false;
788 int64_t Value = CE->getValue();
789 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
791 bool isImm0_508s4() const {
792 if (!isImm()) return false;
793 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
794 if (!CE) return false;
795 int64_t Value = CE->getValue();
796 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
798 bool isImm0_508s4Neg() const {
799 if (!isImm()) return false;
800 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
801 if (!CE) return false;
802 int64_t Value = -CE->getValue();
803 // explicitly exclude zero. we want that to use the normal 0_508 version.
804 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
806 bool isImm0_239() const {
807 if (!isImm()) return false;
808 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
809 if (!CE) return false;
810 int64_t Value = CE->getValue();
811 return Value >= 0 && Value < 240;
813 bool isImm0_255() const {
814 if (!isImm()) return false;
815 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
816 if (!CE) return false;
817 int64_t Value = CE->getValue();
818 return Value >= 0 && Value < 256;
820 bool isImm0_4095() const {
821 if (!isImm()) return false;
822 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
823 if (!CE) return false;
824 int64_t Value = CE->getValue();
825 return Value >= 0 && Value < 4096;
827 bool isImm0_4095Neg() const {
828 if (!isImm()) return false;
829 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
830 if (!CE) return false;
831 int64_t Value = -CE->getValue();
832 return Value > 0 && Value < 4096;
834 bool isImm0_1() const {
835 if (!isImm()) return false;
836 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
837 if (!CE) return false;
838 int64_t Value = CE->getValue();
839 return Value >= 0 && Value < 2;
841 bool isImm0_3() const {
842 if (!isImm()) return false;
843 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
844 if (!CE) return false;
845 int64_t Value = CE->getValue();
846 return Value >= 0 && Value < 4;
848 bool isImm0_7() const {
849 if (!isImm()) return false;
850 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
851 if (!CE) return false;
852 int64_t Value = CE->getValue();
853 return Value >= 0 && Value < 8;
855 bool isImm0_15() const {
856 if (!isImm()) return false;
857 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
858 if (!CE) return false;
859 int64_t Value = CE->getValue();
860 return Value >= 0 && Value < 16;
862 bool isImm0_31() const {
863 if (!isImm()) return false;
864 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
865 if (!CE) return false;
866 int64_t Value = CE->getValue();
867 return Value >= 0 && Value < 32;
869 bool isImm0_63() const {
870 if (!isImm()) return false;
871 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
872 if (!CE) return false;
873 int64_t Value = CE->getValue();
874 return Value >= 0 && Value < 64;
876 bool isImm8() const {
877 if (!isImm()) return false;
878 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
879 if (!CE) return false;
880 int64_t Value = CE->getValue();
883 bool isImm16() const {
884 if (!isImm()) return false;
885 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
886 if (!CE) return false;
887 int64_t Value = CE->getValue();
890 bool isImm32() const {
891 if (!isImm()) return false;
892 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
893 if (!CE) return false;
894 int64_t Value = CE->getValue();
897 bool isShrImm8() const {
898 if (!isImm()) return false;
899 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
900 if (!CE) return false;
901 int64_t Value = CE->getValue();
902 return Value > 0 && Value <= 8;
904 bool isShrImm16() const {
905 if (!isImm()) return false;
906 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
907 if (!CE) return false;
908 int64_t Value = CE->getValue();
909 return Value > 0 && Value <= 16;
911 bool isShrImm32() const {
912 if (!isImm()) return false;
913 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
914 if (!CE) return false;
915 int64_t Value = CE->getValue();
916 return Value > 0 && Value <= 32;
918 bool isShrImm64() const {
919 if (!isImm()) return false;
920 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
921 if (!CE) return false;
922 int64_t Value = CE->getValue();
923 return Value > 0 && Value <= 64;
925 bool isImm1_7() const {
926 if (!isImm()) return false;
927 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
928 if (!CE) return false;
929 int64_t Value = CE->getValue();
930 return Value > 0 && Value < 8;
932 bool isImm1_15() const {
933 if (!isImm()) return false;
934 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
935 if (!CE) return false;
936 int64_t Value = CE->getValue();
937 return Value > 0 && Value < 16;
939 bool isImm1_31() const {
940 if (!isImm()) return false;
941 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
942 if (!CE) return false;
943 int64_t Value = CE->getValue();
944 return Value > 0 && Value < 32;
946 bool isImm1_16() const {
947 if (!isImm()) return false;
948 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
949 if (!CE) return false;
950 int64_t Value = CE->getValue();
951 return Value > 0 && Value < 17;
953 bool isImm1_32() const {
954 if (!isImm()) return false;
955 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
956 if (!CE) return false;
957 int64_t Value = CE->getValue();
958 return Value > 0 && Value < 33;
960 bool isImm0_32() const {
961 if (!isImm()) return false;
962 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
963 if (!CE) return false;
964 int64_t Value = CE->getValue();
965 return Value >= 0 && Value < 33;
967 bool isImm0_65535() const {
968 if (!isImm()) return false;
969 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
970 if (!CE) return false;
971 int64_t Value = CE->getValue();
972 return Value >= 0 && Value < 65536;
974 bool isImm256_65535Expr() const {
975 if (!isImm()) return false;
976 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
977 // If it's not a constant expression, it'll generate a fixup and be
979 if (!CE) return true;
980 int64_t Value = CE->getValue();
981 return Value >= 256 && Value < 65536;
983 bool isImm0_65535Expr() const {
984 if (!isImm()) return false;
985 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
986 // If it's not a constant expression, it'll generate a fixup and be
988 if (!CE) return true;
989 int64_t Value = CE->getValue();
990 return Value >= 0 && Value < 65536;
992 bool isImm24bit() const {
993 if (!isImm()) return false;
994 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
995 if (!CE) return false;
996 int64_t Value = CE->getValue();
997 return Value >= 0 && Value <= 0xffffff;
999 bool isImmThumbSR() const {
1000 if (!isImm()) return false;
1001 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1002 if (!CE) return false;
1003 int64_t Value = CE->getValue();
1004 return Value > 0 && Value < 33;
1006 bool isPKHLSLImm() const {
1007 if (!isImm()) return false;
1008 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1009 if (!CE) return false;
1010 int64_t Value = CE->getValue();
1011 return Value >= 0 && Value < 32;
1013 bool isPKHASRImm() const {
1014 if (!isImm()) return false;
1015 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1016 if (!CE) return false;
1017 int64_t Value = CE->getValue();
1018 return Value > 0 && Value <= 32;
1020 bool isAdrLabel() const {
1021 // If we have an immediate that's not a constant, treat it as a label
1022 // reference needing a fixup. If it is a constant, but it can't fit
1023 // into shift immediate encoding, we reject it.
1024 if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
1025 else return (isARMSOImm() || isARMSOImmNeg());
1027 bool isARMSOImm() const {
1028 if (!isImm()) return false;
1029 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1030 if (!CE) return false;
1031 int64_t Value = CE->getValue();
1032 return ARM_AM::getSOImmVal(Value) != -1;
1034 bool isARMSOImmNot() const {
1035 if (!isImm()) return false;
1036 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1037 if (!CE) return false;
1038 int64_t Value = CE->getValue();
1039 return ARM_AM::getSOImmVal(~Value) != -1;
1041 bool isARMSOImmNeg() const {
1042 if (!isImm()) return false;
1043 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1044 if (!CE) return false;
1045 int64_t Value = CE->getValue();
1046 // Only use this when not representable as a plain so_imm.
1047 return ARM_AM::getSOImmVal(Value) == -1 &&
1048 ARM_AM::getSOImmVal(-Value) != -1;
1050 bool isT2SOImm() const {
1051 if (!isImm()) return false;
1052 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1053 if (!CE) return false;
1054 int64_t Value = CE->getValue();
1055 return ARM_AM::getT2SOImmVal(Value) != -1;
1057 bool isT2SOImmNot() const {
1058 if (!isImm()) return false;
1059 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1060 if (!CE) return false;
1061 int64_t Value = CE->getValue();
1062 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1063 ARM_AM::getT2SOImmVal(~Value) != -1;
1065 bool isT2SOImmNeg() const {
1066 if (!isImm()) return false;
1067 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1068 if (!CE) return false;
1069 int64_t Value = CE->getValue();
1070 // Only use this when not representable as a plain so_imm.
1071 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1072 ARM_AM::getT2SOImmVal(-Value) != -1;
1074 bool isSetEndImm() const {
1075 if (!isImm()) return false;
1076 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1077 if (!CE) return false;
1078 int64_t Value = CE->getValue();
1079 return Value == 1 || Value == 0;
1081 bool isReg() const override { return Kind == k_Register; }
1082 bool isRegList() const { return Kind == k_RegisterList; }
1083 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1084 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1085 bool isToken() const override { return Kind == k_Token; }
1086 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1087 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1088 bool isMem() const override { return Kind == k_Memory; }
1089 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1090 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
1091 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
1092 bool isRotImm() const { return Kind == k_RotateImmediate; }
1093 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1094 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
1095 bool isPostIdxReg() const {
1096 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
1098 bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1101 // No offset of any kind.
1102 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1103 (alignOK || Memory.Alignment == Alignment);
1105 bool isMemPCRelImm12() const {
1106 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1108 // Base register must be PC.
1109 if (Memory.BaseRegNum != ARM::PC)
1111 // Immediate offset in range [-4095, 4095].
1112 if (!Memory.OffsetImm) return true;
1113 int64_t Val = Memory.OffsetImm->getValue();
1114 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1116 bool isAlignedMemory() const {
1117 return isMemNoOffset(true);
1119 bool isAlignedMemoryNone() const {
1120 return isMemNoOffset(false, 0);
1122 bool isDupAlignedMemoryNone() const {
1123 return isMemNoOffset(false, 0);
1125 bool isAlignedMemory16() const {
1126 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1128 return isMemNoOffset(false, 0);
1130 bool isDupAlignedMemory16() const {
1131 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1133 return isMemNoOffset(false, 0);
1135 bool isAlignedMemory32() const {
1136 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1138 return isMemNoOffset(false, 0);
1140 bool isDupAlignedMemory32() const {
1141 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1143 return isMemNoOffset(false, 0);
1145 bool isAlignedMemory64() const {
1146 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1148 return isMemNoOffset(false, 0);
1150 bool isDupAlignedMemory64() const {
1151 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1153 return isMemNoOffset(false, 0);
1155 bool isAlignedMemory64or128() const {
1156 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1158 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1160 return isMemNoOffset(false, 0);
1162 bool isDupAlignedMemory64or128() const {
1163 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1165 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1167 return isMemNoOffset(false, 0);
1169 bool isAlignedMemory64or128or256() const {
1170 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1172 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1174 if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
1176 return isMemNoOffset(false, 0);
1178 bool isAddrMode2() const {
1179 if (!isMem() || Memory.Alignment != 0) return false;
1180 // Check for register offset.
1181 if (Memory.OffsetRegNum) return true;
1182 // Immediate offset in range [-4095, 4095].
1183 if (!Memory.OffsetImm) return true;
1184 int64_t Val = Memory.OffsetImm->getValue();
1185 return Val > -4096 && Val < 4096;
1187 bool isAM2OffsetImm() const {
1188 if (!isImm()) return false;
1189 // Immediate offset in range [-4095, 4095].
1190 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1191 if (!CE) return false;
1192 int64_t Val = CE->getValue();
1193 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1195 bool isAddrMode3() const {
1196 // If we have an immediate that's not a constant, treat it as a label
1197 // reference needing a fixup. If it is a constant, it's something else
1198 // and we reject it.
1199 if (isImm() && !isa<MCConstantExpr>(getImm()))
1201 if (!isMem() || Memory.Alignment != 0) return false;
1202 // No shifts are legal for AM3.
1203 if (Memory.ShiftType != ARM_AM::no_shift) return false;
1204 // Check for register offset.
1205 if (Memory.OffsetRegNum) return true;
1206 // Immediate offset in range [-255, 255].
1207 if (!Memory.OffsetImm) return true;
1208 int64_t Val = Memory.OffsetImm->getValue();
1209 // The #-0 offset is encoded as INT32_MIN, and we have to check
1211 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1213 bool isAM3Offset() const {
1214 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1216 if (Kind == k_PostIndexRegister)
1217 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1218 // Immediate offset in range [-255, 255].
1219 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1220 if (!CE) return false;
1221 int64_t Val = CE->getValue();
1222 // Special case, #-0 is INT32_MIN.
1223 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1225 bool isAddrMode5() const {
1226 // If we have an immediate that's not a constant, treat it as a label
1227 // reference needing a fixup. If it is a constant, it's something else
1228 // and we reject it.
1229 if (isImm() && !isa<MCConstantExpr>(getImm()))
1231 if (!isMem() || Memory.Alignment != 0) return false;
1232 // Check for register offset.
1233 if (Memory.OffsetRegNum) return false;
1234 // Immediate offset in range [-1020, 1020] and a multiple of 4.
1235 if (!Memory.OffsetImm) return true;
1236 int64_t Val = Memory.OffsetImm->getValue();
1237 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1240 bool isMemTBB() const {
1241 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1242 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1246 bool isMemTBH() const {
1247 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1248 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1249 Memory.Alignment != 0 )
1253 bool isMemRegOffset() const {
1254 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1258 bool isT2MemRegOffset() const {
1259 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1260 Memory.Alignment != 0)
1262 // Only lsl #{0, 1, 2, 3} allowed.
1263 if (Memory.ShiftType == ARM_AM::no_shift)
1265 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1269 bool isMemThumbRR() const {
1270 // Thumb reg+reg addressing is simple. Just two registers, a base and
1271 // an offset. No shifts, negations or any other complicating factors.
1272 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1273 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1275 return isARMLowRegister(Memory.BaseRegNum) &&
1276 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1278 bool isMemThumbRIs4() const {
1279 if (!isMem() || Memory.OffsetRegNum != 0 ||
1280 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1282 // Immediate offset, multiple of 4 in range [0, 124].
1283 if (!Memory.OffsetImm) return true;
1284 int64_t Val = Memory.OffsetImm->getValue();
1285 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1287 bool isMemThumbRIs2() const {
1288 if (!isMem() || Memory.OffsetRegNum != 0 ||
1289 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1291 // Immediate offset, multiple of 4 in range [0, 62].
1292 if (!Memory.OffsetImm) return true;
1293 int64_t Val = Memory.OffsetImm->getValue();
1294 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1296 bool isMemThumbRIs1() const {
1297 if (!isMem() || Memory.OffsetRegNum != 0 ||
1298 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1300 // Immediate offset in range [0, 31].
1301 if (!Memory.OffsetImm) return true;
1302 int64_t Val = Memory.OffsetImm->getValue();
1303 return Val >= 0 && Val <= 31;
1305 bool isMemThumbSPI() const {
1306 if (!isMem() || Memory.OffsetRegNum != 0 ||
1307 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1309 // Immediate offset, multiple of 4 in range [0, 1020].
1310 if (!Memory.OffsetImm) return true;
1311 int64_t Val = Memory.OffsetImm->getValue();
1312 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1314 bool isMemImm8s4Offset() const {
1315 // If we have an immediate that's not a constant, treat it as a label
1316 // reference needing a fixup. If it is a constant, it's something else
1317 // and we reject it.
1318 if (isImm() && !isa<MCConstantExpr>(getImm()))
1320 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1322 // Immediate offset a multiple of 4 in range [-1020, 1020].
1323 if (!Memory.OffsetImm) return true;
1324 int64_t Val = Memory.OffsetImm->getValue();
1325 // Special case, #-0 is INT32_MIN.
1326 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1328 bool isMemImm0_1020s4Offset() const {
1329 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1331 // Immediate offset a multiple of 4 in range [0, 1020].
1332 if (!Memory.OffsetImm) return true;
1333 int64_t Val = Memory.OffsetImm->getValue();
1334 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1336 bool isMemImm8Offset() const {
1337 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1339 // Base reg of PC isn't allowed for these encodings.
1340 if (Memory.BaseRegNum == ARM::PC) return false;
1341 // Immediate offset in range [-255, 255].
1342 if (!Memory.OffsetImm) return true;
1343 int64_t Val = Memory.OffsetImm->getValue();
1344 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1346 bool isMemPosImm8Offset() const {
1347 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1349 // Immediate offset in range [0, 255].
1350 if (!Memory.OffsetImm) return true;
1351 int64_t Val = Memory.OffsetImm->getValue();
1352 return Val >= 0 && Val < 256;
1354 bool isMemNegImm8Offset() const {
1355 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1357 // Base reg of PC isn't allowed for these encodings.
1358 if (Memory.BaseRegNum == ARM::PC) return false;
1359 // Immediate offset in range [-255, -1].
1360 if (!Memory.OffsetImm) return false;
1361 int64_t Val = Memory.OffsetImm->getValue();
1362 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1364 bool isMemUImm12Offset() const {
1365 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1367 // Immediate offset in range [0, 4095].
1368 if (!Memory.OffsetImm) return true;
1369 int64_t Val = Memory.OffsetImm->getValue();
1370 return (Val >= 0 && Val < 4096);
1372 bool isMemImm12Offset() const {
1373 // If we have an immediate that's not a constant, treat it as a label
1374 // reference needing a fixup. If it is a constant, it's something else
1375 // and we reject it.
1376 if (isImm() && !isa<MCConstantExpr>(getImm()))
1379 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1381 // Immediate offset in range [-4095, 4095].
1382 if (!Memory.OffsetImm) return true;
1383 int64_t Val = Memory.OffsetImm->getValue();
1384 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1386 bool isPostIdxImm8() const {
1387 if (!isImm()) return false;
1388 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1389 if (!CE) return false;
1390 int64_t Val = CE->getValue();
1391 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1393 bool isPostIdxImm8s4() const {
1394 if (!isImm()) return false;
1395 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1396 if (!CE) return false;
1397 int64_t Val = CE->getValue();
1398 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1402 bool isMSRMask() const { return Kind == k_MSRMask; }
1403 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1406 bool isSingleSpacedVectorList() const {
1407 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1409 bool isDoubleSpacedVectorList() const {
1410 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1412 bool isVecListOneD() const {
1413 if (!isSingleSpacedVectorList()) return false;
1414 return VectorList.Count == 1;
1417 bool isVecListDPair() const {
1418 if (!isSingleSpacedVectorList()) return false;
1419 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1420 .contains(VectorList.RegNum));
1423 bool isVecListThreeD() const {
1424 if (!isSingleSpacedVectorList()) return false;
1425 return VectorList.Count == 3;
1428 bool isVecListFourD() const {
1429 if (!isSingleSpacedVectorList()) return false;
1430 return VectorList.Count == 4;
1433 bool isVecListDPairSpaced() const {
1434 if (Kind != k_VectorList) return false;
1435 if (isSingleSpacedVectorList()) return false;
1436 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1437 .contains(VectorList.RegNum));
1440 bool isVecListThreeQ() const {
1441 if (!isDoubleSpacedVectorList()) return false;
1442 return VectorList.Count == 3;
1445 bool isVecListFourQ() const {
1446 if (!isDoubleSpacedVectorList()) return false;
1447 return VectorList.Count == 4;
1450 bool isSingleSpacedVectorAllLanes() const {
1451 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1453 bool isDoubleSpacedVectorAllLanes() const {
1454 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1456 bool isVecListOneDAllLanes() const {
1457 if (!isSingleSpacedVectorAllLanes()) return false;
1458 return VectorList.Count == 1;
1461 bool isVecListDPairAllLanes() const {
1462 if (!isSingleSpacedVectorAllLanes()) return false;
1463 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1464 .contains(VectorList.RegNum));
1467 bool isVecListDPairSpacedAllLanes() const {
1468 if (!isDoubleSpacedVectorAllLanes()) return false;
1469 return VectorList.Count == 2;
1472 bool isVecListThreeDAllLanes() const {
1473 if (!isSingleSpacedVectorAllLanes()) return false;
1474 return VectorList.Count == 3;
1477 bool isVecListThreeQAllLanes() const {
1478 if (!isDoubleSpacedVectorAllLanes()) return false;
1479 return VectorList.Count == 3;
1482 bool isVecListFourDAllLanes() const {
1483 if (!isSingleSpacedVectorAllLanes()) return false;
1484 return VectorList.Count == 4;
1487 bool isVecListFourQAllLanes() const {
1488 if (!isDoubleSpacedVectorAllLanes()) return false;
1489 return VectorList.Count == 4;
1492 bool isSingleSpacedVectorIndexed() const {
1493 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1495 bool isDoubleSpacedVectorIndexed() const {
1496 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1498 bool isVecListOneDByteIndexed() const {
1499 if (!isSingleSpacedVectorIndexed()) return false;
1500 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1503 bool isVecListOneDHWordIndexed() const {
1504 if (!isSingleSpacedVectorIndexed()) return false;
1505 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1508 bool isVecListOneDWordIndexed() const {
1509 if (!isSingleSpacedVectorIndexed()) return false;
1510 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1513 bool isVecListTwoDByteIndexed() const {
1514 if (!isSingleSpacedVectorIndexed()) return false;
1515 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1518 bool isVecListTwoDHWordIndexed() const {
1519 if (!isSingleSpacedVectorIndexed()) return false;
1520 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1523 bool isVecListTwoQWordIndexed() const {
1524 if (!isDoubleSpacedVectorIndexed()) return false;
1525 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1528 bool isVecListTwoQHWordIndexed() const {
1529 if (!isDoubleSpacedVectorIndexed()) return false;
1530 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1533 bool isVecListTwoDWordIndexed() const {
1534 if (!isSingleSpacedVectorIndexed()) return false;
1535 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1538 bool isVecListThreeDByteIndexed() const {
1539 if (!isSingleSpacedVectorIndexed()) return false;
1540 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1543 bool isVecListThreeDHWordIndexed() const {
1544 if (!isSingleSpacedVectorIndexed()) return false;
1545 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1548 bool isVecListThreeQWordIndexed() const {
1549 if (!isDoubleSpacedVectorIndexed()) return false;
1550 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1553 bool isVecListThreeQHWordIndexed() const {
1554 if (!isDoubleSpacedVectorIndexed()) return false;
1555 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1558 bool isVecListThreeDWordIndexed() const {
1559 if (!isSingleSpacedVectorIndexed()) return false;
1560 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1563 bool isVecListFourDByteIndexed() const {
1564 if (!isSingleSpacedVectorIndexed()) return false;
1565 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1568 bool isVecListFourDHWordIndexed() const {
1569 if (!isSingleSpacedVectorIndexed()) return false;
1570 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1573 bool isVecListFourQWordIndexed() const {
1574 if (!isDoubleSpacedVectorIndexed()) return false;
1575 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1578 bool isVecListFourQHWordIndexed() const {
1579 if (!isDoubleSpacedVectorIndexed()) return false;
1580 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1583 bool isVecListFourDWordIndexed() const {
1584 if (!isSingleSpacedVectorIndexed()) return false;
1585 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1588 bool isVectorIndex8() const {
1589 if (Kind != k_VectorIndex) return false;
1590 return VectorIndex.Val < 8;
1592 bool isVectorIndex16() const {
1593 if (Kind != k_VectorIndex) return false;
1594 return VectorIndex.Val < 4;
1596 bool isVectorIndex32() const {
1597 if (Kind != k_VectorIndex) return false;
1598 return VectorIndex.Val < 2;
1601 bool isNEONi8splat() const {
1602 if (!isImm()) return false;
1603 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1604 // Must be a constant.
1605 if (!CE) return false;
1606 int64_t Value = CE->getValue();
1607 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1609 return Value >= 0 && Value < 256;
1612 bool isNEONi16splat() const {
1613 if (isNEONByteReplicate(2))
1614 return false; // Leave that for bytes replication and forbid by default.
1617 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1618 // Must be a constant.
1619 if (!CE) return false;
1620 int64_t Value = CE->getValue();
1621 // i16 value in the range [0,255] or [0x0100, 0xff00]
1622 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1625 bool isNEONi32splat() const {
1626 if (isNEONByteReplicate(4))
1627 return false; // Leave that for bytes replication and forbid by default.
1630 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1631 // Must be a constant.
1632 if (!CE) return false;
1633 int64_t Value = CE->getValue();
1634 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1635 return (Value >= 0 && Value < 256) ||
1636 (Value >= 0x0100 && Value <= 0xff00) ||
1637 (Value >= 0x010000 && Value <= 0xff0000) ||
1638 (Value >= 0x01000000 && Value <= 0xff000000);
1641 bool isNEONByteReplicate(unsigned NumBytes) const {
1644 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1645 // Must be a constant.
1648 int64_t Value = CE->getValue();
1650 return false; // Don't bother with zero.
1652 unsigned char B = Value & 0xff;
1653 for (unsigned i = 1; i < NumBytes; ++i) {
1655 if ((Value & 0xff) != B)
1660 bool isNEONi16ByteReplicate() const { return isNEONByteReplicate(2); }
1661 bool isNEONi32ByteReplicate() const { return isNEONByteReplicate(4); }
1662 bool isNEONi32vmov() const {
1663 if (isNEONByteReplicate(4))
1664 return false; // Let it to be classified as byte-replicate case.
1667 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1668 // Must be a constant.
1671 int64_t Value = CE->getValue();
1672 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1673 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1674 return (Value >= 0 && Value < 256) ||
1675 (Value >= 0x0100 && Value <= 0xff00) ||
1676 (Value >= 0x010000 && Value <= 0xff0000) ||
1677 (Value >= 0x01000000 && Value <= 0xff000000) ||
1678 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1679 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1681 bool isNEONi32vmovNeg() const {
1682 if (!isImm()) return false;
1683 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1684 // Must be a constant.
1685 if (!CE) return false;
1686 int64_t Value = ~CE->getValue();
1687 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1688 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1689 return (Value >= 0 && Value < 256) ||
1690 (Value >= 0x0100 && Value <= 0xff00) ||
1691 (Value >= 0x010000 && Value <= 0xff0000) ||
1692 (Value >= 0x01000000 && Value <= 0xff000000) ||
1693 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1694 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1697 bool isNEONi64splat() const {
1698 if (!isImm()) return false;
1699 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1700 // Must be a constant.
1701 if (!CE) return false;
1702 uint64_t Value = CE->getValue();
1703 // i64 value with each byte being either 0 or 0xff.
1704 for (unsigned i = 0; i < 8; ++i)
1705 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1709 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1710 // Add as immediates when possible. Null MCExpr = 0.
1712 Inst.addOperand(MCOperand::CreateImm(0));
1713 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1714 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1716 Inst.addOperand(MCOperand::CreateExpr(Expr));
1719 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1720 assert(N == 2 && "Invalid number of operands!");
1721 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1722 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1723 Inst.addOperand(MCOperand::CreateReg(RegNum));
1726 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1727 assert(N == 1 && "Invalid number of operands!");
1728 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1731 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1732 assert(N == 1 && "Invalid number of operands!");
1733 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1736 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1737 assert(N == 1 && "Invalid number of operands!");
1738 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1741 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1742 assert(N == 1 && "Invalid number of operands!");
1743 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1746 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1747 assert(N == 1 && "Invalid number of operands!");
1748 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1751 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1752 assert(N == 1 && "Invalid number of operands!");
1753 Inst.addOperand(MCOperand::CreateReg(getReg()));
1756 void addRegOperands(MCInst &Inst, unsigned N) const {
1757 assert(N == 1 && "Invalid number of operands!");
1758 Inst.addOperand(MCOperand::CreateReg(getReg()));
1761 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1762 assert(N == 3 && "Invalid number of operands!");
1763 assert(isRegShiftedReg() &&
1764 "addRegShiftedRegOperands() on non-RegShiftedReg!");
1765 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1766 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1767 Inst.addOperand(MCOperand::CreateImm(
1768 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1771 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1772 assert(N == 2 && "Invalid number of operands!");
1773 assert(isRegShiftedImm() &&
1774 "addRegShiftedImmOperands() on non-RegShiftedImm!");
1775 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1776 // Shift of #32 is encoded as 0 where permitted
1777 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1778 Inst.addOperand(MCOperand::CreateImm(
1779 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1782 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1783 assert(N == 1 && "Invalid number of operands!");
1784 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1788 void addRegListOperands(MCInst &Inst, unsigned N) const {
1789 assert(N == 1 && "Invalid number of operands!");
1790 const SmallVectorImpl<unsigned> &RegList = getRegList();
1791 for (SmallVectorImpl<unsigned>::const_iterator
1792 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1793 Inst.addOperand(MCOperand::CreateReg(*I));
1796 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1797 addRegListOperands(Inst, N);
1800 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1801 addRegListOperands(Inst, N);
1804 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1805 assert(N == 1 && "Invalid number of operands!");
1806 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1807 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1810 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1811 assert(N == 1 && "Invalid number of operands!");
1812 // Munge the lsb/width into a bitfield mask.
1813 unsigned lsb = Bitfield.LSB;
1814 unsigned width = Bitfield.Width;
1815 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1816 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1817 (32 - (lsb + width)));
1818 Inst.addOperand(MCOperand::CreateImm(Mask));
1821 void addImmOperands(MCInst &Inst, unsigned N) const {
1822 assert(N == 1 && "Invalid number of operands!");
1823 addExpr(Inst, getImm());
1826 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1827 assert(N == 1 && "Invalid number of operands!");
1828 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1829 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1832 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1833 assert(N == 1 && "Invalid number of operands!");
1834 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1835 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1838 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1839 assert(N == 1 && "Invalid number of operands!");
1840 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1841 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1842 Inst.addOperand(MCOperand::CreateImm(Val));
1845 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1846 assert(N == 1 && "Invalid number of operands!");
1847 // FIXME: We really want to scale the value here, but the LDRD/STRD
1848 // instruction don't encode operands that way yet.
1849 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1850 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1853 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1854 assert(N == 1 && "Invalid number of operands!");
1855 // The immediate is scaled by four in the encoding and is stored
1856 // in the MCInst as such. Lop off the low two bits here.
1857 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1858 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1861 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1862 assert(N == 1 && "Invalid number of operands!");
1863 // The immediate is scaled by four in the encoding and is stored
1864 // in the MCInst as such. Lop off the low two bits here.
1865 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1866 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1869 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1870 assert(N == 1 && "Invalid number of operands!");
1871 // The immediate is scaled by four in the encoding and is stored
1872 // in the MCInst as such. Lop off the low two bits here.
1873 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1874 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1877 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1878 assert(N == 1 && "Invalid number of operands!");
1879 // The constant encodes as the immediate-1, and we store in the instruction
1880 // the bits as encoded, so subtract off one here.
1881 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1882 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1885 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1886 assert(N == 1 && "Invalid number of operands!");
1887 // The constant encodes as the immediate-1, and we store in the instruction
1888 // the bits as encoded, so subtract off one here.
1889 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1890 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1893 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1894 assert(N == 1 && "Invalid number of operands!");
1895 // The constant encodes as the immediate, except for 32, which encodes as
1897 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1898 unsigned Imm = CE->getValue();
1899 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1902 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1903 assert(N == 1 && "Invalid number of operands!");
1904 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1905 // the instruction as well.
1906 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1907 int Val = CE->getValue();
1908 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1911 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1912 assert(N == 1 && "Invalid number of operands!");
1913 // The operand is actually a t2_so_imm, but we have its bitwise
1914 // negation in the assembly source, so twiddle it here.
1915 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1916 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1919 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1920 assert(N == 1 && "Invalid number of operands!");
1921 // The operand is actually a t2_so_imm, but we have its
1922 // negation in the assembly source, so twiddle it here.
1923 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1924 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1927 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1928 assert(N == 1 && "Invalid number of operands!");
1929 // The operand is actually an imm0_4095, but we have its
1930 // negation in the assembly source, so twiddle it here.
1931 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1932 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1935 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1936 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1937 Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
1941 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1942 assert(SR && "Unknown value type!");
1943 Inst.addOperand(MCOperand::CreateExpr(SR));
1946 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
1947 assert(N == 1 && "Invalid number of operands!");
1949 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1951 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1955 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1956 assert(SR && "Unknown value type!");
1957 Inst.addOperand(MCOperand::CreateExpr(SR));
1961 assert(isMem() && "Unknown value type!");
1962 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
1963 Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
1966 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1967 assert(N == 1 && "Invalid number of operands!");
1968 // The operand is actually a so_imm, but we have its bitwise
1969 // negation in the assembly source, so twiddle it here.
1970 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1971 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1974 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1975 assert(N == 1 && "Invalid number of operands!");
1976 // The operand is actually a so_imm, but we have its
1977 // negation in the assembly source, so twiddle it here.
1978 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1979 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1982 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1983 assert(N == 1 && "Invalid number of operands!");
1984 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1987 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
1988 assert(N == 1 && "Invalid number of operands!");
1989 Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
1992 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1993 assert(N == 1 && "Invalid number of operands!");
1994 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1997 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1998 assert(N == 1 && "Invalid number of operands!");
1999 int32_t Imm = Memory.OffsetImm->getValue();
2000 Inst.addOperand(MCOperand::CreateImm(Imm));
2003 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
2004 assert(N == 1 && "Invalid number of operands!");
2005 assert(isImm() && "Not an immediate!");
2007 // If we have an immediate that's not a constant, treat it as a label
2008 // reference needing a fixup.
2009 if (!isa<MCConstantExpr>(getImm())) {
2010 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2014 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2015 int Val = CE->getValue();
2016 Inst.addOperand(MCOperand::CreateImm(Val));
2019 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
2020 assert(N == 2 && "Invalid number of operands!");
2021 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2022 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
2025 void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2026 addAlignedMemoryOperands(Inst, N);
2029 void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2030 addAlignedMemoryOperands(Inst, N);
2033 void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2034 addAlignedMemoryOperands(Inst, N);
2037 void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2038 addAlignedMemoryOperands(Inst, N);
2041 void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2042 addAlignedMemoryOperands(Inst, N);
2045 void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2046 addAlignedMemoryOperands(Inst, N);
2049 void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2050 addAlignedMemoryOperands(Inst, N);
2053 void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2054 addAlignedMemoryOperands(Inst, N);
2057 void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2058 addAlignedMemoryOperands(Inst, N);
2061 void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2062 addAlignedMemoryOperands(Inst, N);
2065 void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2066 addAlignedMemoryOperands(Inst, N);
2069 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
2070 assert(N == 3 && "Invalid number of operands!");
2071 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2072 if (!Memory.OffsetRegNum) {
2073 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2074 // Special case for #-0
2075 if (Val == INT32_MIN) Val = 0;
2076 if (Val < 0) Val = -Val;
2077 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2079 // For register offset, we encode the shift type and negation flag
2081 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2082 Memory.ShiftImm, Memory.ShiftType);
2084 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2085 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2086 Inst.addOperand(MCOperand::CreateImm(Val));
2089 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2090 assert(N == 2 && "Invalid number of operands!");
2091 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2092 assert(CE && "non-constant AM2OffsetImm operand!");
2093 int32_t Val = CE->getValue();
2094 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2095 // Special case for #-0
2096 if (Val == INT32_MIN) Val = 0;
2097 if (Val < 0) Val = -Val;
2098 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2099 Inst.addOperand(MCOperand::CreateReg(0));
2100 Inst.addOperand(MCOperand::CreateImm(Val));
2103 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2104 assert(N == 3 && "Invalid number of operands!");
2105 // If we have an immediate that's not a constant, treat it as a label
2106 // reference needing a fixup. If it is a constant, it's something else
2107 // and we reject it.
2109 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2110 Inst.addOperand(MCOperand::CreateReg(0));
2111 Inst.addOperand(MCOperand::CreateImm(0));
2115 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2116 if (!Memory.OffsetRegNum) {
2117 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2118 // Special case for #-0
2119 if (Val == INT32_MIN) Val = 0;
2120 if (Val < 0) Val = -Val;
2121 Val = ARM_AM::getAM3Opc(AddSub, Val);
2123 // For register offset, we encode the shift type and negation flag
2125 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
2127 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2128 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2129 Inst.addOperand(MCOperand::CreateImm(Val));
2132 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
2133 assert(N == 2 && "Invalid number of operands!");
2134 if (Kind == k_PostIndexRegister) {
2136 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
2137 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2138 Inst.addOperand(MCOperand::CreateImm(Val));
2143 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
2144 int32_t Val = CE->getValue();
2145 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2146 // Special case for #-0
2147 if (Val == INT32_MIN) Val = 0;
2148 if (Val < 0) Val = -Val;
2149 Val = ARM_AM::getAM3Opc(AddSub, Val);
2150 Inst.addOperand(MCOperand::CreateReg(0));
2151 Inst.addOperand(MCOperand::CreateImm(Val));
2154 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2155 assert(N == 2 && "Invalid number of operands!");
2156 // If we have an immediate that's not a constant, treat it as a label
2157 // reference needing a fixup. If it is a constant, it's something else
2158 // and we reject it.
2160 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2161 Inst.addOperand(MCOperand::CreateImm(0));
2165 // The lower two bits are always zero and as such are not encoded.
2166 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2167 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2168 // Special case for #-0
2169 if (Val == INT32_MIN) Val = 0;
2170 if (Val < 0) Val = -Val;
2171 Val = ARM_AM::getAM5Opc(AddSub, Val);
2172 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2173 Inst.addOperand(MCOperand::CreateImm(Val));
2176 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2177 assert(N == 2 && "Invalid number of operands!");
2178 // If we have an immediate that's not a constant, treat it as a label
2179 // reference needing a fixup. If it is a constant, it's something else
2180 // and we reject it.
2182 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2183 Inst.addOperand(MCOperand::CreateImm(0));
2187 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2188 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2189 Inst.addOperand(MCOperand::CreateImm(Val));
2192 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2193 assert(N == 2 && "Invalid number of operands!");
2194 // The lower two bits are always zero and as such are not encoded.
2195 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2196 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2197 Inst.addOperand(MCOperand::CreateImm(Val));
2200 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2201 assert(N == 2 && "Invalid number of operands!");
2202 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2203 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2204 Inst.addOperand(MCOperand::CreateImm(Val));
2207 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2208 addMemImm8OffsetOperands(Inst, N);
2211 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2212 addMemImm8OffsetOperands(Inst, N);
2215 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2216 assert(N == 2 && "Invalid number of operands!");
2217 // If this is an immediate, it's a label reference.
2219 addExpr(Inst, getImm());
2220 Inst.addOperand(MCOperand::CreateImm(0));
2224 // Otherwise, it's a normal memory reg+offset.
2225 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2226 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2227 Inst.addOperand(MCOperand::CreateImm(Val));
2230 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2231 assert(N == 2 && "Invalid number of operands!");
2232 // If this is an immediate, it's a label reference.
2234 addExpr(Inst, getImm());
2235 Inst.addOperand(MCOperand::CreateImm(0));
2239 // Otherwise, it's a normal memory reg+offset.
2240 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2241 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2242 Inst.addOperand(MCOperand::CreateImm(Val));
2245 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2246 assert(N == 2 && "Invalid number of operands!");
2247 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2248 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2251 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2252 assert(N == 2 && "Invalid number of operands!");
2253 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2254 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2257 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2258 assert(N == 3 && "Invalid number of operands!");
2260 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2261 Memory.ShiftImm, Memory.ShiftType);
2262 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2263 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2264 Inst.addOperand(MCOperand::CreateImm(Val));
2267 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2268 assert(N == 3 && "Invalid number of operands!");
2269 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2270 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2271 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
2274 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2275 assert(N == 2 && "Invalid number of operands!");
2276 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2277 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2280 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2281 assert(N == 2 && "Invalid number of operands!");
2282 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2283 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2284 Inst.addOperand(MCOperand::CreateImm(Val));
2287 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2288 assert(N == 2 && "Invalid number of operands!");
2289 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2290 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2291 Inst.addOperand(MCOperand::CreateImm(Val));
2294 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2295 assert(N == 2 && "Invalid number of operands!");
2296 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2297 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2298 Inst.addOperand(MCOperand::CreateImm(Val));
2301 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2302 assert(N == 2 && "Invalid number of operands!");
2303 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2304 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2305 Inst.addOperand(MCOperand::CreateImm(Val));
2308 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2309 assert(N == 1 && "Invalid number of operands!");
2310 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2311 assert(CE && "non-constant post-idx-imm8 operand!");
2312 int Imm = CE->getValue();
2313 bool isAdd = Imm >= 0;
2314 if (Imm == INT32_MIN) Imm = 0;
2315 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2316 Inst.addOperand(MCOperand::CreateImm(Imm));
2319 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2320 assert(N == 1 && "Invalid number of operands!");
2321 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2322 assert(CE && "non-constant post-idx-imm8s4 operand!");
2323 int Imm = CE->getValue();
2324 bool isAdd = Imm >= 0;
2325 if (Imm == INT32_MIN) Imm = 0;
2326 // Immediate is scaled by 4.
2327 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2328 Inst.addOperand(MCOperand::CreateImm(Imm));
2331 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2332 assert(N == 2 && "Invalid number of operands!");
2333 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2334 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2337 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2338 assert(N == 2 && "Invalid number of operands!");
2339 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2340 // The sign, shift type, and shift amount are encoded in a single operand
2341 // using the AM2 encoding helpers.
2342 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2343 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2344 PostIdxReg.ShiftTy);
2345 Inst.addOperand(MCOperand::CreateImm(Imm));
2348 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2349 assert(N == 1 && "Invalid number of operands!");
2350 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2353 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2354 assert(N == 1 && "Invalid number of operands!");
2355 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2358 void addVecListOperands(MCInst &Inst, unsigned N) const {
2359 assert(N == 1 && "Invalid number of operands!");
2360 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2363 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2364 assert(N == 2 && "Invalid number of operands!");
2365 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2366 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2369 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2370 assert(N == 1 && "Invalid number of operands!");
2371 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2374 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2375 assert(N == 1 && "Invalid number of operands!");
2376 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2379 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2380 assert(N == 1 && "Invalid number of operands!");
2381 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2384 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2385 assert(N == 1 && "Invalid number of operands!");
2386 // The immediate encodes the type of constant as well as the value.
2387 // Mask in that this is an i8 splat.
2388 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2389 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2392 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2393 assert(N == 1 && "Invalid number of operands!");
2394 // The immediate encodes the type of constant as well as the value.
2395 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2396 unsigned Value = CE->getValue();
2398 Value = (Value >> 8) | 0xa00;
2401 Inst.addOperand(MCOperand::CreateImm(Value));
2404 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2405 assert(N == 1 && "Invalid number of operands!");
2406 // The immediate encodes the type of constant as well as the value.
2407 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2408 unsigned Value = CE->getValue();
2409 if (Value >= 256 && Value <= 0xff00)
2410 Value = (Value >> 8) | 0x200;
2411 else if (Value > 0xffff && Value <= 0xff0000)
2412 Value = (Value >> 16) | 0x400;
2413 else if (Value > 0xffffff)
2414 Value = (Value >> 24) | 0x600;
2415 Inst.addOperand(MCOperand::CreateImm(Value));
2418 void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const {
2419 assert(N == 1 && "Invalid number of operands!");
2420 // The immediate encodes the type of constant as well as the value.
2421 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2422 unsigned Value = CE->getValue();
2423 assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2424 Inst.getOpcode() == ARM::VMOVv16i8) &&
2425 "All vmvn instructions that wants to replicate non-zero byte "
2426 "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2427 unsigned B = ((~Value) & 0xff);
2428 B |= 0xe00; // cmode = 0b1110
2429 Inst.addOperand(MCOperand::CreateImm(B));
2431 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2432 assert(N == 1 && "Invalid number of operands!");
2433 // The immediate encodes the type of constant as well as the value.
2434 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2435 unsigned Value = CE->getValue();
2436 if (Value >= 256 && Value <= 0xffff)
2437 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2438 else if (Value > 0xffff && Value <= 0xffffff)
2439 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2440 else if (Value > 0xffffff)
2441 Value = (Value >> 24) | 0x600;
2442 Inst.addOperand(MCOperand::CreateImm(Value));
2445 void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const {
2446 assert(N == 1 && "Invalid number of operands!");
2447 // The immediate encodes the type of constant as well as the value.
2448 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2449 unsigned Value = CE->getValue();
2450 assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2451 Inst.getOpcode() == ARM::VMOVv16i8) &&
2452 "All instructions that wants to replicate non-zero byte "
2453 "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2454 unsigned B = Value & 0xff;
2455 B |= 0xe00; // cmode = 0b1110
2456 Inst.addOperand(MCOperand::CreateImm(B));
2458 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2459 assert(N == 1 && "Invalid number of operands!");
2460 // The immediate encodes the type of constant as well as the value.
2461 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2462 unsigned Value = ~CE->getValue();
2463 if (Value >= 256 && Value <= 0xffff)
2464 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2465 else if (Value > 0xffff && Value <= 0xffffff)
2466 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2467 else if (Value > 0xffffff)
2468 Value = (Value >> 24) | 0x600;
2469 Inst.addOperand(MCOperand::CreateImm(Value));
2472 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2473 assert(N == 1 && "Invalid number of operands!");
2474 // The immediate encodes the type of constant as well as the value.
2475 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2476 uint64_t Value = CE->getValue();
2478 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2479 Imm |= (Value & 1) << i;
2481 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2484 void print(raw_ostream &OS) const override;
2486 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2487 ARMOperand *Op = new ARMOperand(k_ITCondMask);
2488 Op->ITMask.Mask = Mask;
2494 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2495 ARMOperand *Op = new ARMOperand(k_CondCode);
2502 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2503 ARMOperand *Op = new ARMOperand(k_CoprocNum);
2504 Op->Cop.Val = CopVal;
2510 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2511 ARMOperand *Op = new ARMOperand(k_CoprocReg);
2512 Op->Cop.Val = CopVal;
2518 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2519 ARMOperand *Op = new ARMOperand(k_CoprocOption);
2526 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2527 ARMOperand *Op = new ARMOperand(k_CCOut);
2528 Op->Reg.RegNum = RegNum;
2534 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2535 ARMOperand *Op = new ARMOperand(k_Token);
2536 Op->Tok.Data = Str.data();
2537 Op->Tok.Length = Str.size();
2543 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2544 ARMOperand *Op = new ARMOperand(k_Register);
2545 Op->Reg.RegNum = RegNum;
2551 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2556 ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2557 Op->RegShiftedReg.ShiftTy = ShTy;
2558 Op->RegShiftedReg.SrcReg = SrcReg;
2559 Op->RegShiftedReg.ShiftReg = ShiftReg;
2560 Op->RegShiftedReg.ShiftImm = ShiftImm;
2566 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2570 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2571 Op->RegShiftedImm.ShiftTy = ShTy;
2572 Op->RegShiftedImm.SrcReg = SrcReg;
2573 Op->RegShiftedImm.ShiftImm = ShiftImm;
2579 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2581 ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2582 Op->ShifterImm.isASR = isASR;
2583 Op->ShifterImm.Imm = Imm;
2589 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2590 ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2591 Op->RotImm.Imm = Imm;
2597 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2599 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2600 Op->Bitfield.LSB = LSB;
2601 Op->Bitfield.Width = Width;
2608 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned> > &Regs,
2609 SMLoc StartLoc, SMLoc EndLoc) {
2610 assert (Regs.size() > 0 && "RegList contains no registers?");
2611 KindTy Kind = k_RegisterList;
2613 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2614 Kind = k_DPRRegisterList;
2615 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2616 contains(Regs.front().second))
2617 Kind = k_SPRRegisterList;
2619 // Sort based on the register encoding values.
2620 array_pod_sort(Regs.begin(), Regs.end());
2622 ARMOperand *Op = new ARMOperand(Kind);
2623 for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2624 I = Regs.begin(), E = Regs.end(); I != E; ++I)
2625 Op->Registers.push_back(I->second);
2626 Op->StartLoc = StartLoc;
2627 Op->EndLoc = EndLoc;
2631 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2632 bool isDoubleSpaced, SMLoc S, SMLoc E) {
2633 ARMOperand *Op = new ARMOperand(k_VectorList);
2634 Op->VectorList.RegNum = RegNum;
2635 Op->VectorList.Count = Count;
2636 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2642 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2643 bool isDoubleSpaced,
2645 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2646 Op->VectorList.RegNum = RegNum;
2647 Op->VectorList.Count = Count;
2648 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2654 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2656 bool isDoubleSpaced,
2658 ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2659 Op->VectorList.RegNum = RegNum;
2660 Op->VectorList.Count = Count;
2661 Op->VectorList.LaneIndex = Index;
2662 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2668 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2670 ARMOperand *Op = new ARMOperand(k_VectorIndex);
2671 Op->VectorIndex.Val = Idx;
2677 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2678 ARMOperand *Op = new ARMOperand(k_Immediate);
2685 static ARMOperand *CreateMem(unsigned BaseRegNum,
2686 const MCConstantExpr *OffsetImm,
2687 unsigned OffsetRegNum,
2688 ARM_AM::ShiftOpc ShiftType,
2693 SMLoc AlignmentLoc = SMLoc()) {
2694 ARMOperand *Op = new ARMOperand(k_Memory);
2695 Op->Memory.BaseRegNum = BaseRegNum;
2696 Op->Memory.OffsetImm = OffsetImm;
2697 Op->Memory.OffsetRegNum = OffsetRegNum;
2698 Op->Memory.ShiftType = ShiftType;
2699 Op->Memory.ShiftImm = ShiftImm;
2700 Op->Memory.Alignment = Alignment;
2701 Op->Memory.isNegative = isNegative;
2704 Op->AlignmentLoc = AlignmentLoc;
2708 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2709 ARM_AM::ShiftOpc ShiftTy,
2712 ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2713 Op->PostIdxReg.RegNum = RegNum;
2714 Op->PostIdxReg.isAdd = isAdd;
2715 Op->PostIdxReg.ShiftTy = ShiftTy;
2716 Op->PostIdxReg.ShiftImm = ShiftImm;
2722 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2723 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2724 Op->MBOpt.Val = Opt;
2730 static ARMOperand *CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt,
2732 ARMOperand *Op = new ARMOperand(k_InstSyncBarrierOpt);
2733 Op->ISBOpt.Val = Opt;
2739 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2740 ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2741 Op->IFlags.Val = IFlags;
2747 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2748 ARMOperand *Op = new ARMOperand(k_MSRMask);
2749 Op->MMask.Val = MMask;
2756 } // end anonymous namespace.
2758 void ARMOperand::print(raw_ostream &OS) const {
2761 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2764 OS << "<ccout " << getReg() << ">";
2766 case k_ITCondMask: {
2767 static const char *const MaskStr[] = {
2768 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2769 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2771 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2772 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2776 OS << "<coprocessor number: " << getCoproc() << ">";
2779 OS << "<coprocessor register: " << getCoproc() << ">";
2781 case k_CoprocOption:
2782 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2785 OS << "<mask: " << getMSRMask() << ">";
2788 getImm()->print(OS);
2790 case k_MemBarrierOpt:
2791 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
2793 case k_InstSyncBarrierOpt:
2794 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2798 << " base:" << Memory.BaseRegNum;
2801 case k_PostIndexRegister:
2802 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2803 << PostIdxReg.RegNum;
2804 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2805 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2806 << PostIdxReg.ShiftImm;
2809 case k_ProcIFlags: {
2810 OS << "<ARM_PROC::";
2811 unsigned IFlags = getProcIFlags();
2812 for (int i=2; i >= 0; --i)
2813 if (IFlags & (1 << i))
2814 OS << ARM_PROC::IFlagsToString(1 << i);
2819 OS << "<register " << getReg() << ">";
2821 case k_ShifterImmediate:
2822 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2823 << " #" << ShifterImm.Imm << ">";
2825 case k_ShiftedRegister:
2826 OS << "<so_reg_reg "
2827 << RegShiftedReg.SrcReg << " "
2828 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2829 << " " << RegShiftedReg.ShiftReg << ">";
2831 case k_ShiftedImmediate:
2832 OS << "<so_reg_imm "
2833 << RegShiftedImm.SrcReg << " "
2834 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2835 << " #" << RegShiftedImm.ShiftImm << ">";
2837 case k_RotateImmediate:
2838 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2840 case k_BitfieldDescriptor:
2841 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2842 << ", width: " << Bitfield.Width << ">";
2844 case k_RegisterList:
2845 case k_DPRRegisterList:
2846 case k_SPRRegisterList: {
2847 OS << "<register_list ";
2849 const SmallVectorImpl<unsigned> &RegList = getRegList();
2850 for (SmallVectorImpl<unsigned>::const_iterator
2851 I = RegList.begin(), E = RegList.end(); I != E; ) {
2853 if (++I < E) OS << ", ";
2860 OS << "<vector_list " << VectorList.Count << " * "
2861 << VectorList.RegNum << ">";
2863 case k_VectorListAllLanes:
2864 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2865 << VectorList.RegNum << ">";
2867 case k_VectorListIndexed:
2868 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2869 << VectorList.Count << " * " << VectorList.RegNum << ">";
2872 OS << "'" << getToken() << "'";
2875 OS << "<vectorindex " << getVectorIndex() << ">";
2880 /// @name Auto-generated Match Functions
2883 static unsigned MatchRegisterName(StringRef Name);
2887 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2888 SMLoc &StartLoc, SMLoc &EndLoc) {
2889 StartLoc = Parser.getTok().getLoc();
2890 EndLoc = Parser.getTok().getEndLoc();
2891 RegNo = tryParseRegister();
2893 return (RegNo == (unsigned)-1);
2896 /// Try to parse a register name. The token must be an Identifier when called,
2897 /// and if it is a register name the token is eaten and the register number is
2898 /// returned. Otherwise return -1.
2900 int ARMAsmParser::tryParseRegister() {
2901 const AsmToken &Tok = Parser.getTok();
2902 if (Tok.isNot(AsmToken::Identifier)) return -1;
2904 std::string lowerCase = Tok.getString().lower();
2905 unsigned RegNum = MatchRegisterName(lowerCase);
2907 RegNum = StringSwitch<unsigned>(lowerCase)
2908 .Case("r13", ARM::SP)
2909 .Case("r14", ARM::LR)
2910 .Case("r15", ARM::PC)
2911 .Case("ip", ARM::R12)
2912 // Additional register name aliases for 'gas' compatibility.
2913 .Case("a1", ARM::R0)
2914 .Case("a2", ARM::R1)
2915 .Case("a3", ARM::R2)
2916 .Case("a4", ARM::R3)
2917 .Case("v1", ARM::R4)
2918 .Case("v2", ARM::R5)
2919 .Case("v3", ARM::R6)
2920 .Case("v4", ARM::R7)
2921 .Case("v5", ARM::R8)
2922 .Case("v6", ARM::R9)
2923 .Case("v7", ARM::R10)
2924 .Case("v8", ARM::R11)
2925 .Case("sb", ARM::R9)
2926 .Case("sl", ARM::R10)
2927 .Case("fp", ARM::R11)
2931 // Check for aliases registered via .req. Canonicalize to lower case.
2932 // That's more consistent since register names are case insensitive, and
2933 // it's how the original entry was passed in from MC/MCParser/AsmParser.
2934 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2935 // If no match, return failure.
2936 if (Entry == RegisterReqs.end())
2938 Parser.Lex(); // Eat identifier token.
2939 return Entry->getValue();
2942 Parser.Lex(); // Eat identifier token.
2947 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
2948 // If a recoverable error occurs, return 1. If an irrecoverable error
2949 // occurs, return -1. An irrecoverable error is one where tokens have been
2950 // consumed in the process of trying to parse the shifter (i.e., when it is
2951 // indeed a shifter operand, but malformed).
2952 int ARMAsmParser::tryParseShiftRegister(
2953 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2954 SMLoc S = Parser.getTok().getLoc();
2955 const AsmToken &Tok = Parser.getTok();
2956 if (Tok.isNot(AsmToken::Identifier))
2959 std::string lowerCase = Tok.getString().lower();
2960 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2961 .Case("asl", ARM_AM::lsl)
2962 .Case("lsl", ARM_AM::lsl)
2963 .Case("lsr", ARM_AM::lsr)
2964 .Case("asr", ARM_AM::asr)
2965 .Case("ror", ARM_AM::ror)
2966 .Case("rrx", ARM_AM::rrx)
2967 .Default(ARM_AM::no_shift);
2969 if (ShiftTy == ARM_AM::no_shift)
2972 Parser.Lex(); // Eat the operator.
2974 // The source register for the shift has already been added to the
2975 // operand list, so we need to pop it off and combine it into the shifted
2976 // register operand instead.
2977 std::unique_ptr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2978 if (!PrevOp->isReg())
2979 return Error(PrevOp->getStartLoc(), "shift must be of a register");
2980 int SrcReg = PrevOp->getReg();
2985 if (ShiftTy == ARM_AM::rrx) {
2986 // RRX Doesn't have an explicit shift amount. The encoder expects
2987 // the shift register to be the same as the source register. Seems odd,
2991 // Figure out if this is shifted by a constant or a register (for non-RRX).
2992 if (Parser.getTok().is(AsmToken::Hash) ||
2993 Parser.getTok().is(AsmToken::Dollar)) {
2994 Parser.Lex(); // Eat hash.
2995 SMLoc ImmLoc = Parser.getTok().getLoc();
2996 const MCExpr *ShiftExpr = nullptr;
2997 if (getParser().parseExpression(ShiftExpr, EndLoc)) {
2998 Error(ImmLoc, "invalid immediate shift value");
3001 // The expression must be evaluatable as an immediate.
3002 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
3004 Error(ImmLoc, "invalid immediate shift value");
3007 // Range check the immediate.
3008 // lsl, ror: 0 <= imm <= 31
3009 // lsr, asr: 0 <= imm <= 32
3010 Imm = CE->getValue();
3012 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
3013 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
3014 Error(ImmLoc, "immediate shift value out of range");
3017 // shift by zero is a nop. Always send it through as lsl.
3018 // ('as' compatibility)
3020 ShiftTy = ARM_AM::lsl;
3021 } else if (Parser.getTok().is(AsmToken::Identifier)) {
3022 SMLoc L = Parser.getTok().getLoc();
3023 EndLoc = Parser.getTok().getEndLoc();
3024 ShiftReg = tryParseRegister();
3025 if (ShiftReg == -1) {
3026 Error (L, "expected immediate or register in shift operand");
3030 Error (Parser.getTok().getLoc(),
3031 "expected immediate or register in shift operand");
3036 if (ShiftReg && ShiftTy != ARM_AM::rrx)
3037 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
3041 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
3048 /// Try to parse a register name. The token must be an Identifier when called.
3049 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
3050 /// if there is a "writeback". 'true' if it's not a register.
3052 /// TODO this is likely to change to allow different register types and or to
3053 /// parse for a specific register type.
3055 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3056 const AsmToken &RegTok = Parser.getTok();
3057 int RegNo = tryParseRegister();
3061 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
3062 RegTok.getEndLoc()));
3064 const AsmToken &ExclaimTok = Parser.getTok();
3065 if (ExclaimTok.is(AsmToken::Exclaim)) {
3066 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
3067 ExclaimTok.getLoc()));
3068 Parser.Lex(); // Eat exclaim token
3072 // Also check for an index operand. This is only legal for vector registers,
3073 // but that'll get caught OK in operand matching, so we don't need to
3074 // explicitly filter everything else out here.
3075 if (Parser.getTok().is(AsmToken::LBrac)) {
3076 SMLoc SIdx = Parser.getTok().getLoc();
3077 Parser.Lex(); // Eat left bracket token.
3079 const MCExpr *ImmVal;
3080 if (getParser().parseExpression(ImmVal))
3082 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
3084 return TokError("immediate value expected for vector index");
3086 if (Parser.getTok().isNot(AsmToken::RBrac))
3087 return Error(Parser.getTok().getLoc(), "']' expected");
3089 SMLoc E = Parser.getTok().getEndLoc();
3090 Parser.Lex(); // Eat right bracket token.
3092 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
3100 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
3101 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
3103 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
3104 // Use the same layout as the tablegen'erated register name matcher. Ugly,
3106 switch (Name.size()) {
3109 if (Name[0] != CoprocOp)
3125 if (Name[0] != CoprocOp || Name[1] != '1')
3129 // p10 and p11 are invalid for coproc instructions (reserved for FP/NEON)
3130 case '0': return CoprocOp == 'p'? -1: 10;
3131 case '1': return CoprocOp == 'p'? -1: 11;
3132 case '2': return 12;
3133 case '3': return 13;
3134 case '4': return 14;
3135 case '5': return 15;
3140 /// parseITCondCode - Try to parse a condition code for an IT instruction.
3141 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3142 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3143 SMLoc S = Parser.getTok().getLoc();
3144 const AsmToken &Tok = Parser.getTok();
3145 if (!Tok.is(AsmToken::Identifier))
3146 return MatchOperand_NoMatch;
3147 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
3148 .Case("eq", ARMCC::EQ)
3149 .Case("ne", ARMCC::NE)
3150 .Case("hs", ARMCC::HS)
3151 .Case("cs", ARMCC::HS)
3152 .Case("lo", ARMCC::LO)
3153 .Case("cc", ARMCC::LO)
3154 .Case("mi", ARMCC::MI)
3155 .Case("pl", ARMCC::PL)
3156 .Case("vs", ARMCC::VS)
3157 .Case("vc", ARMCC::VC)
3158 .Case("hi", ARMCC::HI)
3159 .Case("ls", ARMCC::LS)
3160 .Case("ge", ARMCC::GE)
3161 .Case("lt", ARMCC::LT)
3162 .Case("gt", ARMCC::GT)
3163 .Case("le", ARMCC::LE)
3164 .Case("al", ARMCC::AL)
3167 return MatchOperand_NoMatch;
3168 Parser.Lex(); // Eat the token.
3170 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
3172 return MatchOperand_Success;
3175 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
3176 /// token must be an Identifier when called, and if it is a coprocessor
3177 /// number, the token is eaten and the operand is added to the operand list.
3178 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3179 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3180 SMLoc S = Parser.getTok().getLoc();
3181 const AsmToken &Tok = Parser.getTok();
3182 if (Tok.isNot(AsmToken::Identifier))
3183 return MatchOperand_NoMatch;
3185 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
3187 return MatchOperand_NoMatch;
3189 Parser.Lex(); // Eat identifier token.
3190 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
3191 return MatchOperand_Success;
3194 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
3195 /// token must be an Identifier when called, and if it is a coprocessor
3196 /// number, the token is eaten and the operand is added to the operand list.
3197 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3198 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3199 SMLoc S = Parser.getTok().getLoc();
3200 const AsmToken &Tok = Parser.getTok();
3201 if (Tok.isNot(AsmToken::Identifier))
3202 return MatchOperand_NoMatch;
3204 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
3206 return MatchOperand_NoMatch;
3208 Parser.Lex(); // Eat identifier token.
3209 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
3210 return MatchOperand_Success;
3213 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
3214 /// coproc_option : '{' imm0_255 '}'
3215 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3216 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3217 SMLoc S = Parser.getTok().getLoc();
3219 // If this isn't a '{', this isn't a coprocessor immediate operand.
3220 if (Parser.getTok().isNot(AsmToken::LCurly))
3221 return MatchOperand_NoMatch;
3222 Parser.Lex(); // Eat the '{'
3225 SMLoc Loc = Parser.getTok().getLoc();
3226 if (getParser().parseExpression(Expr)) {
3227 Error(Loc, "illegal expression");
3228 return MatchOperand_ParseFail;
3230 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3231 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
3232 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
3233 return MatchOperand_ParseFail;
3235 int Val = CE->getValue();
3237 // Check for and consume the closing '}'
3238 if (Parser.getTok().isNot(AsmToken::RCurly))
3239 return MatchOperand_ParseFail;
3240 SMLoc E = Parser.getTok().getEndLoc();
3241 Parser.Lex(); // Eat the '}'
3243 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
3244 return MatchOperand_Success;
3247 // For register list parsing, we need to map from raw GPR register numbering
3248 // to the enumeration values. The enumeration values aren't sorted by
3249 // register number due to our using "sp", "lr" and "pc" as canonical names.
3250 static unsigned getNextRegister(unsigned Reg) {
3251 // If this is a GPR, we need to do it manually, otherwise we can rely
3252 // on the sort ordering of the enumeration since the other reg-classes
3254 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3257 default: llvm_unreachable("Invalid GPR number!");
3258 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
3259 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
3260 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
3261 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
3262 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
3263 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3264 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
3265 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
3269 // Return the low-subreg of a given Q register.
3270 static unsigned getDRegFromQReg(unsigned QReg) {
3272 default: llvm_unreachable("expected a Q register!");
3273 case ARM::Q0: return ARM::D0;
3274 case ARM::Q1: return ARM::D2;
3275 case ARM::Q2: return ARM::D4;
3276 case ARM::Q3: return ARM::D6;
3277 case ARM::Q4: return ARM::D8;
3278 case ARM::Q5: return ARM::D10;
3279 case ARM::Q6: return ARM::D12;
3280 case ARM::Q7: return ARM::D14;
3281 case ARM::Q8: return ARM::D16;
3282 case ARM::Q9: return ARM::D18;
3283 case ARM::Q10: return ARM::D20;
3284 case ARM::Q11: return ARM::D22;
3285 case ARM::Q12: return ARM::D24;
3286 case ARM::Q13: return ARM::D26;
3287 case ARM::Q14: return ARM::D28;
3288 case ARM::Q15: return ARM::D30;
3292 /// Parse a register list.
3294 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3295 assert(Parser.getTok().is(AsmToken::LCurly) &&
3296 "Token is not a Left Curly Brace");
3297 SMLoc S = Parser.getTok().getLoc();
3298 Parser.Lex(); // Eat '{' token.
3299 SMLoc RegLoc = Parser.getTok().getLoc();
3301 // Check the first register in the list to see what register class
3302 // this is a list of.
3303 int Reg = tryParseRegister();
3305 return Error(RegLoc, "register expected");
3307 // The reglist instructions have at most 16 registers, so reserve
3308 // space for that many.
3310 SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3312 // Allow Q regs and just interpret them as the two D sub-registers.
3313 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3314 Reg = getDRegFromQReg(Reg);
3315 EReg = MRI->getEncodingValue(Reg);
3316 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3319 const MCRegisterClass *RC;
3320 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3321 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3322 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3323 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3324 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3325 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3327 return Error(RegLoc, "invalid register in register list");
3329 // Store the register.
3330 EReg = MRI->getEncodingValue(Reg);
3331 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3333 // This starts immediately after the first register token in the list,
3334 // so we can see either a comma or a minus (range separator) as a legal
3336 while (Parser.getTok().is(AsmToken::Comma) ||
3337 Parser.getTok().is(AsmToken::Minus)) {
3338 if (Parser.getTok().is(AsmToken::Minus)) {
3339 Parser.Lex(); // Eat the minus.
3340 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3341 int EndReg = tryParseRegister();
3343 return Error(AfterMinusLoc, "register expected");
3344 // Allow Q regs and just interpret them as the two D sub-registers.
3345 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3346 EndReg = getDRegFromQReg(EndReg) + 1;
3347 // If the register is the same as the start reg, there's nothing
3351 // The register must be in the same register class as the first.
3352 if (!RC->contains(EndReg))
3353 return Error(AfterMinusLoc, "invalid register in register list");
3354 // Ranges must go from low to high.
3355 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3356 return Error(AfterMinusLoc, "bad range in register list");
3358 // Add all the registers in the range to the register list.
3359 while (Reg != EndReg) {
3360 Reg = getNextRegister(Reg);
3361 EReg = MRI->getEncodingValue(Reg);
3362 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3366 Parser.Lex(); // Eat the comma.
3367 RegLoc = Parser.getTok().getLoc();
3369 const AsmToken RegTok = Parser.getTok();
3370 Reg = tryParseRegister();
3372 return Error(RegLoc, "register expected");
3373 // Allow Q regs and just interpret them as the two D sub-registers.
3374 bool isQReg = false;
3375 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3376 Reg = getDRegFromQReg(Reg);
3379 // The register must be in the same register class as the first.
3380 if (!RC->contains(Reg))
3381 return Error(RegLoc, "invalid register in register list");
3382 // List must be monotonically increasing.
3383 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3384 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3385 Warning(RegLoc, "register list not in ascending order");
3387 return Error(RegLoc, "register list not in ascending order");
3389 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3390 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3391 ") in register list");
3394 // VFP register lists must also be contiguous.
3395 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3397 return Error(RegLoc, "non-contiguous register range");
3398 EReg = MRI->getEncodingValue(Reg);
3399 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3401 EReg = MRI->getEncodingValue(++Reg);
3402 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3406 if (Parser.getTok().isNot(AsmToken::RCurly))
3407 return Error(Parser.getTok().getLoc(), "'}' expected");
3408 SMLoc E = Parser.getTok().getEndLoc();
3409 Parser.Lex(); // Eat '}' token.
3411 // Push the register list operand.
3412 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3414 // The ARM system instruction variants for LDM/STM have a '^' token here.
3415 if (Parser.getTok().is(AsmToken::Caret)) {
3416 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3417 Parser.Lex(); // Eat '^' token.
3423 // Helper function to parse the lane index for vector lists.
3424 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3425 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3426 Index = 0; // Always return a defined index value.
3427 if (Parser.getTok().is(AsmToken::LBrac)) {
3428 Parser.Lex(); // Eat the '['.
3429 if (Parser.getTok().is(AsmToken::RBrac)) {
3430 // "Dn[]" is the 'all lanes' syntax.
3431 LaneKind = AllLanes;
3432 EndLoc = Parser.getTok().getEndLoc();
3433 Parser.Lex(); // Eat the ']'.
3434 return MatchOperand_Success;
3437 // There's an optional '#' token here. Normally there wouldn't be, but
3438 // inline assemble puts one in, and it's friendly to accept that.
3439 if (Parser.getTok().is(AsmToken::Hash))
3440 Parser.Lex(); // Eat '#' or '$'.
3442 const MCExpr *LaneIndex;
3443 SMLoc Loc = Parser.getTok().getLoc();
3444 if (getParser().parseExpression(LaneIndex)) {
3445 Error(Loc, "illegal expression");
3446 return MatchOperand_ParseFail;
3448 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3450 Error(Loc, "lane index must be empty or an integer");
3451 return MatchOperand_ParseFail;
3453 if (Parser.getTok().isNot(AsmToken::RBrac)) {
3454 Error(Parser.getTok().getLoc(), "']' expected");
3455 return MatchOperand_ParseFail;
3457 EndLoc = Parser.getTok().getEndLoc();
3458 Parser.Lex(); // Eat the ']'.
3459 int64_t Val = CE->getValue();
3461 // FIXME: Make this range check context sensitive for .8, .16, .32.
3462 if (Val < 0 || Val > 7) {
3463 Error(Parser.getTok().getLoc(), "lane index out of range");
3464 return MatchOperand_ParseFail;
3467 LaneKind = IndexedLane;
3468 return MatchOperand_Success;
3471 return MatchOperand_Success;
3474 // parse a vector register list
3475 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3476 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3477 VectorLaneTy LaneKind;
3479 SMLoc S = Parser.getTok().getLoc();
3480 // As an extension (to match gas), support a plain D register or Q register
3481 // (without encosing curly braces) as a single or double entry list,
3483 if (Parser.getTok().is(AsmToken::Identifier)) {
3484 SMLoc E = Parser.getTok().getEndLoc();
3485 int Reg = tryParseRegister();
3487 return MatchOperand_NoMatch;
3488 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3489 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3490 if (Res != MatchOperand_Success)
3494 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3497 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3501 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3506 return MatchOperand_Success;
3508 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3509 Reg = getDRegFromQReg(Reg);
3510 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3511 if (Res != MatchOperand_Success)
3515 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3516 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3517 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3520 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3521 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3522 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3526 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3531 return MatchOperand_Success;
3533 Error(S, "vector register expected");
3534 return MatchOperand_ParseFail;
3537 if (Parser.getTok().isNot(AsmToken::LCurly))
3538 return MatchOperand_NoMatch;
3540 Parser.Lex(); // Eat '{' token.
3541 SMLoc RegLoc = Parser.getTok().getLoc();
3543 int Reg = tryParseRegister();
3545 Error(RegLoc, "register expected");
3546 return MatchOperand_ParseFail;
3550 unsigned FirstReg = Reg;
3551 // The list is of D registers, but we also allow Q regs and just interpret
3552 // them as the two D sub-registers.
3553 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3554 FirstReg = Reg = getDRegFromQReg(Reg);
3555 Spacing = 1; // double-spacing requires explicit D registers, otherwise
3556 // it's ambiguous with four-register single spaced.
3562 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3563 return MatchOperand_ParseFail;
3565 while (Parser.getTok().is(AsmToken::Comma) ||
3566 Parser.getTok().is(AsmToken::Minus)) {
3567 if (Parser.getTok().is(AsmToken::Minus)) {
3569 Spacing = 1; // Register range implies a single spaced list.
3570 else if (Spacing == 2) {
3571 Error(Parser.getTok().getLoc(),
3572 "sequential registers in double spaced list");
3573 return MatchOperand_ParseFail;
3575 Parser.Lex(); // Eat the minus.
3576 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3577 int EndReg = tryParseRegister();
3579 Error(AfterMinusLoc, "register expected");
3580 return MatchOperand_ParseFail;
3582 // Allow Q regs and just interpret them as the two D sub-registers.
3583 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3584 EndReg = getDRegFromQReg(EndReg) + 1;
3585 // If the register is the same as the start reg, there's nothing
3589 // The register must be in the same register class as the first.
3590 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3591 Error(AfterMinusLoc, "invalid register in register list");
3592 return MatchOperand_ParseFail;
3594 // Ranges must go from low to high.
3596 Error(AfterMinusLoc, "bad range in register list");
3597 return MatchOperand_ParseFail;
3599 // Parse the lane specifier if present.
3600 VectorLaneTy NextLaneKind;
3601 unsigned NextLaneIndex;
3602 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3603 MatchOperand_Success)
3604 return MatchOperand_ParseFail;
3605 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3606 Error(AfterMinusLoc, "mismatched lane index in register list");
3607 return MatchOperand_ParseFail;
3610 // Add all the registers in the range to the register list.
3611 Count += EndReg - Reg;
3615 Parser.Lex(); // Eat the comma.
3616 RegLoc = Parser.getTok().getLoc();
3618 Reg = tryParseRegister();
3620 Error(RegLoc, "register expected");
3621 return MatchOperand_ParseFail;
3623 // vector register lists must be contiguous.
3624 // It's OK to use the enumeration values directly here rather, as the
3625 // VFP register classes have the enum sorted properly.
3627 // The list is of D registers, but we also allow Q regs and just interpret
3628 // them as the two D sub-registers.
3629 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3631 Spacing = 1; // Register range implies a single spaced list.
3632 else if (Spacing == 2) {
3634 "invalid register in double-spaced list (must be 'D' register')");
3635 return MatchOperand_ParseFail;
3637 Reg = getDRegFromQReg(Reg);
3638 if (Reg != OldReg + 1) {
3639 Error(RegLoc, "non-contiguous register range");
3640 return MatchOperand_ParseFail;
3644 // Parse the lane specifier if present.
3645 VectorLaneTy NextLaneKind;
3646 unsigned NextLaneIndex;
3647 SMLoc LaneLoc = Parser.getTok().getLoc();
3648 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3649 MatchOperand_Success)
3650 return MatchOperand_ParseFail;
3651 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3652 Error(LaneLoc, "mismatched lane index in register list");
3653 return MatchOperand_ParseFail;
3657 // Normal D register.
3658 // Figure out the register spacing (single or double) of the list if
3659 // we don't know it already.
3661 Spacing = 1 + (Reg == OldReg + 2);
3663 // Just check that it's contiguous and keep going.
3664 if (Reg != OldReg + Spacing) {
3665 Error(RegLoc, "non-contiguous register range");
3666 return MatchOperand_ParseFail;
3669 // Parse the lane specifier if present.
3670 VectorLaneTy NextLaneKind;
3671 unsigned NextLaneIndex;
3672 SMLoc EndLoc = Parser.getTok().getLoc();
3673 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3674 return MatchOperand_ParseFail;
3675 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3676 Error(EndLoc, "mismatched lane index in register list");
3677 return MatchOperand_ParseFail;
3681 if (Parser.getTok().isNot(AsmToken::RCurly)) {
3682 Error(Parser.getTok().getLoc(), "'}' expected");
3683 return MatchOperand_ParseFail;
3685 E = Parser.getTok().getEndLoc();
3686 Parser.Lex(); // Eat '}' token.
3690 // Two-register operands have been converted to the
3691 // composite register classes.
3693 const MCRegisterClass *RC = (Spacing == 1) ?
3694 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3695 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3696 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3699 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3700 (Spacing == 2), S, E));
3703 // Two-register operands have been converted to the
3704 // composite register classes.
3706 const MCRegisterClass *RC = (Spacing == 1) ?
3707 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3708 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3709 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3711 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3716 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3722 return MatchOperand_Success;
3725 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3726 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3727 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3728 SMLoc S = Parser.getTok().getLoc();
3729 const AsmToken &Tok = Parser.getTok();
3732 if (Tok.is(AsmToken::Identifier)) {
3733 StringRef OptStr = Tok.getString();
3735 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3736 .Case("sy", ARM_MB::SY)
3737 .Case("st", ARM_MB::ST)
3738 .Case("ld", ARM_MB::LD)
3739 .Case("sh", ARM_MB::ISH)
3740 .Case("ish", ARM_MB::ISH)
3741 .Case("shst", ARM_MB::ISHST)
3742 .Case("ishst", ARM_MB::ISHST)
3743 .Case("ishld", ARM_MB::ISHLD)
3744 .Case("nsh", ARM_MB::NSH)
3745 .Case("un", ARM_MB::NSH)
3746 .Case("nshst", ARM_MB::NSHST)
3747 .Case("nshld", ARM_MB::NSHLD)
3748 .Case("unst", ARM_MB::NSHST)
3749 .Case("osh", ARM_MB::OSH)
3750 .Case("oshst", ARM_MB::OSHST)
3751 .Case("oshld", ARM_MB::OSHLD)
3754 // ishld, oshld, nshld and ld are only available from ARMv8.
3755 if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
3756 Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
3760 return MatchOperand_NoMatch;
3762 Parser.Lex(); // Eat identifier token.
3763 } else if (Tok.is(AsmToken::Hash) ||
3764 Tok.is(AsmToken::Dollar) ||
3765 Tok.is(AsmToken::Integer)) {
3766 if (Parser.getTok().isNot(AsmToken::Integer))
3767 Parser.Lex(); // Eat '#' or '$'.
3768 SMLoc Loc = Parser.getTok().getLoc();
3770 const MCExpr *MemBarrierID;
3771 if (getParser().parseExpression(MemBarrierID)) {
3772 Error(Loc, "illegal expression");
3773 return MatchOperand_ParseFail;
3776 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3778 Error(Loc, "constant expression expected");
3779 return MatchOperand_ParseFail;
3782 int Val = CE->getValue();
3784 Error(Loc, "immediate value out of range");
3785 return MatchOperand_ParseFail;
3788 Opt = ARM_MB::RESERVED_0 + Val;
3790 return MatchOperand_ParseFail;
3792 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3793 return MatchOperand_Success;
3796 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3797 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3798 parseInstSyncBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3799 SMLoc S = Parser.getTok().getLoc();
3800 const AsmToken &Tok = Parser.getTok();
3803 if (Tok.is(AsmToken::Identifier)) {
3804 StringRef OptStr = Tok.getString();
3806 if (OptStr.equals_lower("sy"))
3809 return MatchOperand_NoMatch;
3811 Parser.Lex(); // Eat identifier token.
3812 } else if (Tok.is(AsmToken::Hash) ||
3813 Tok.is(AsmToken::Dollar) ||
3814 Tok.is(AsmToken::Integer)) {
3815 if (Parser.getTok().isNot(AsmToken::Integer))
3816 Parser.Lex(); // Eat '#' or '$'.
3817 SMLoc Loc = Parser.getTok().getLoc();
3819 const MCExpr *ISBarrierID;
3820 if (getParser().parseExpression(ISBarrierID)) {
3821 Error(Loc, "illegal expression");
3822 return MatchOperand_ParseFail;
3825 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3827 Error(Loc, "constant expression expected");
3828 return MatchOperand_ParseFail;
3831 int Val = CE->getValue();
3833 Error(Loc, "immediate value out of range");
3834 return MatchOperand_ParseFail;
3837 Opt = ARM_ISB::RESERVED_0 + Val;
3839 return MatchOperand_ParseFail;
3841 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3842 (ARM_ISB::InstSyncBOpt)Opt, S));
3843 return MatchOperand_Success;
3847 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3848 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3849 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3850 SMLoc S = Parser.getTok().getLoc();
3851 const AsmToken &Tok = Parser.getTok();
3852 if (!Tok.is(AsmToken::Identifier))
3853 return MatchOperand_NoMatch;
3854 StringRef IFlagsStr = Tok.getString();
3856 // An iflags string of "none" is interpreted to mean that none of the AIF
3857 // bits are set. Not a terribly useful instruction, but a valid encoding.
3858 unsigned IFlags = 0;
3859 if (IFlagsStr != "none") {
3860 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3861 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3862 .Case("a", ARM_PROC::A)
3863 .Case("i", ARM_PROC::I)
3864 .Case("f", ARM_PROC::F)
3867 // If some specific iflag is already set, it means that some letter is
3868 // present more than once, this is not acceptable.
3869 if (Flag == ~0U || (IFlags & Flag))
3870 return MatchOperand_NoMatch;
3876 Parser.Lex(); // Eat identifier token.
3877 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3878 return MatchOperand_Success;
3881 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3882 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3883 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3884 SMLoc S = Parser.getTok().getLoc();
3885 const AsmToken &Tok = Parser.getTok();
3886 if (!Tok.is(AsmToken::Identifier))
3887 return MatchOperand_NoMatch;
3888 StringRef Mask = Tok.getString();
3891 // See ARMv6-M 10.1.1
3892 std::string Name = Mask.lower();
3893 unsigned FlagsVal = StringSwitch<unsigned>(Name)
3894 // Note: in the documentation:
3895 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3896 // for MSR APSR_nzcvq.
3897 // but we do make it an alias here. This is so to get the "mask encoding"
3898 // bits correct on MSR APSR writes.
3900 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3901 // should really only be allowed when writing a special register. Note
3902 // they get dropped in the MRS instruction reading a special register as
3903 // the SYSm field is only 8 bits.
3905 // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3906 // includes the DSP extension but that is not checked.
3907 .Case("apsr", 0x800)
3908 .Case("apsr_nzcvq", 0x800)
3909 .Case("apsr_g", 0x400)
3910 .Case("apsr_nzcvqg", 0xc00)
3911 .Case("iapsr", 0x801)
3912 .Case("iapsr_nzcvq", 0x801)
3913 .Case("iapsr_g", 0x401)
3914 .Case("iapsr_nzcvqg", 0xc01)
3915 .Case("eapsr", 0x802)
3916 .Case("eapsr_nzcvq", 0x802)
3917 .Case("eapsr_g", 0x402)
3918 .Case("eapsr_nzcvqg", 0xc02)
3919 .Case("xpsr", 0x803)
3920 .Case("xpsr_nzcvq", 0x803)
3921 .Case("xpsr_g", 0x403)
3922 .Case("xpsr_nzcvqg", 0xc03)
3923 .Case("ipsr", 0x805)
3924 .Case("epsr", 0x806)
3925 .Case("iepsr", 0x807)
3928 .Case("primask", 0x810)
3929 .Case("basepri", 0x811)
3930 .Case("basepri_max", 0x812)
3931 .Case("faultmask", 0x813)
3932 .Case("control", 0x814)
3935 if (FlagsVal == ~0U)
3936 return MatchOperand_NoMatch;
3938 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3939 // basepri, basepri_max and faultmask only valid for V7m.
3940 return MatchOperand_NoMatch;
3942 Parser.Lex(); // Eat identifier token.
3943 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3944 return MatchOperand_Success;
3947 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3948 size_t Start = 0, Next = Mask.find('_');
3949 StringRef Flags = "";
3950 std::string SpecReg = Mask.slice(Start, Next).lower();
3951 if (Next != StringRef::npos)
3952 Flags = Mask.slice(Next+1, Mask.size());
3954 // FlagsVal contains the complete mask:
3956 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3957 unsigned FlagsVal = 0;
3959 if (SpecReg == "apsr") {
3960 FlagsVal = StringSwitch<unsigned>(Flags)
3961 .Case("nzcvq", 0x8) // same as CPSR_f
3962 .Case("g", 0x4) // same as CPSR_s
3963 .Case("nzcvqg", 0xc) // same as CPSR_fs
3966 if (FlagsVal == ~0U) {
3968 return MatchOperand_NoMatch;
3970 FlagsVal = 8; // No flag
3972 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3973 // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3974 if (Flags == "all" || Flags == "")
3976 for (int i = 0, e = Flags.size(); i != e; ++i) {
3977 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3984 // If some specific flag is already set, it means that some letter is
3985 // present more than once, this is not acceptable.
3986 if (FlagsVal == ~0U || (FlagsVal & Flag))
3987 return MatchOperand_NoMatch;
3990 } else // No match for special register.
3991 return MatchOperand_NoMatch;
3993 // Special register without flags is NOT equivalent to "fc" flags.
3994 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
3995 // two lines would enable gas compatibility at the expense of breaking
4001 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4002 if (SpecReg == "spsr")
4005 Parser.Lex(); // Eat identifier token.
4006 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
4007 return MatchOperand_Success;
4010 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4011 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
4012 int Low, int High) {
4013 const AsmToken &Tok = Parser.getTok();
4014 if (Tok.isNot(AsmToken::Identifier)) {
4015 Error(Parser.getTok().getLoc(), Op + " operand expected.");
4016 return MatchOperand_ParseFail;
4018 StringRef ShiftName = Tok.getString();
4019 std::string LowerOp = Op.lower();
4020 std::string UpperOp = Op.upper();
4021 if (ShiftName != LowerOp && ShiftName != UpperOp) {
4022 Error(Parser.getTok().getLoc(), Op + " operand expected.");
4023 return MatchOperand_ParseFail;
4025 Parser.Lex(); // Eat shift type token.
4027 // There must be a '#' and a shift amount.
4028 if (Parser.getTok().isNot(AsmToken::Hash) &&
4029 Parser.getTok().isNot(AsmToken::Dollar)) {
4030 Error(Parser.getTok().getLoc(), "'#' expected");
4031 return MatchOperand_ParseFail;
4033 Parser.Lex(); // Eat hash token.
4035 const MCExpr *ShiftAmount;
4036 SMLoc Loc = Parser.getTok().getLoc();
4038 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4039 Error(Loc, "illegal expression");
4040 return MatchOperand_ParseFail;
4042 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4044 Error(Loc, "constant expression expected");
4045 return MatchOperand_ParseFail;
4047 int Val = CE->getValue();
4048 if (Val < Low || Val > High) {
4049 Error(Loc, "immediate value out of range");
4050 return MatchOperand_ParseFail;
4053 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
4055 return MatchOperand_Success;
4058 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4059 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4060 const AsmToken &Tok = Parser.getTok();
4061 SMLoc S = Tok.getLoc();
4062 if (Tok.isNot(AsmToken::Identifier)) {
4063 Error(S, "'be' or 'le' operand expected");
4064 return MatchOperand_ParseFail;
4066 int Val = StringSwitch<int>(Tok.getString().lower())
4070 Parser.Lex(); // Eat the token.
4073 Error(S, "'be' or 'le' operand expected");
4074 return MatchOperand_ParseFail;
4076 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
4078 S, Tok.getEndLoc()));
4079 return MatchOperand_Success;
4082 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
4083 /// instructions. Legal values are:
4084 /// lsl #n 'n' in [0,31]
4085 /// asr #n 'n' in [1,32]
4086 /// n == 32 encoded as n == 0.
4087 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4088 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4089 const AsmToken &Tok = Parser.getTok();
4090 SMLoc S = Tok.getLoc();
4091 if (Tok.isNot(AsmToken::Identifier)) {
4092 Error(S, "shift operator 'asr' or 'lsl' expected");
4093 return MatchOperand_ParseFail;
4095 StringRef ShiftName = Tok.getString();
4097 if (ShiftName == "lsl" || ShiftName == "LSL")
4099 else if (ShiftName == "asr" || ShiftName == "ASR")
4102 Error(S, "shift operator 'asr' or 'lsl' expected");
4103 return MatchOperand_ParseFail;
4105 Parser.Lex(); // Eat the operator.
4107 // A '#' and a shift amount.
4108 if (Parser.getTok().isNot(AsmToken::Hash) &&
4109 Parser.getTok().isNot(AsmToken::Dollar)) {
4110 Error(Parser.getTok().getLoc(), "'#' expected");
4111 return MatchOperand_ParseFail;
4113 Parser.Lex(); // Eat hash token.
4114 SMLoc ExLoc = Parser.getTok().getLoc();
4116 const MCExpr *ShiftAmount;
4118 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4119 Error(ExLoc, "malformed shift expression");
4120 return MatchOperand_ParseFail;
4122 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4124 Error(ExLoc, "shift amount must be an immediate");
4125 return MatchOperand_ParseFail;
4128 int64_t Val = CE->getValue();
4130 // Shift amount must be in [1,32]
4131 if (Val < 1 || Val > 32) {
4132 Error(ExLoc, "'asr' shift amount must be in range [1,32]");
4133 return MatchOperand_ParseFail;
4135 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
4136 if (isThumb() && Val == 32) {
4137 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
4138 return MatchOperand_ParseFail;
4140 if (Val == 32) Val = 0;
4142 // Shift amount must be in [1,32]
4143 if (Val < 0 || Val > 31) {
4144 Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
4145 return MatchOperand_ParseFail;
4149 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
4151 return MatchOperand_Success;
4154 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
4155 /// of instructions. Legal values are:
4156 /// ror #n 'n' in {0, 8, 16, 24}
4157 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4158 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4159 const AsmToken &Tok = Parser.getTok();
4160 SMLoc S = Tok.getLoc();
4161 if (Tok.isNot(AsmToken::Identifier))
4162 return MatchOperand_NoMatch;
4163 StringRef ShiftName = Tok.getString();
4164 if (ShiftName != "ror" && ShiftName != "ROR")
4165 return MatchOperand_NoMatch;
4166 Parser.Lex(); // Eat the operator.
4168 // A '#' and a rotate amount.
4169 if (Parser.getTok().isNot(AsmToken::Hash) &&
4170 Parser.getTok().isNot(AsmToken::Dollar)) {
4171 Error(Parser.getTok().getLoc(), "'#' expected");
4172 return MatchOperand_ParseFail;
4174 Parser.Lex(); // Eat hash token.
4175 SMLoc ExLoc = Parser.getTok().getLoc();
4177 const MCExpr *ShiftAmount;
4179 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4180 Error(ExLoc, "malformed rotate expression");
4181 return MatchOperand_ParseFail;
4183 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4185 Error(ExLoc, "rotate amount must be an immediate");
4186 return MatchOperand_ParseFail;
4189 int64_t Val = CE->getValue();
4190 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
4191 // normally, zero is represented in asm by omitting the rotate operand
4193 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
4194 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
4195 return MatchOperand_ParseFail;
4198 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
4200 return MatchOperand_Success;
4203 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4204 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4205 SMLoc S = Parser.getTok().getLoc();
4206 // The bitfield descriptor is really two operands, the LSB and the width.
4207 if (Parser.getTok().isNot(AsmToken::Hash) &&
4208 Parser.getTok().isNot(AsmToken::Dollar)) {
4209 Error(Parser.getTok().getLoc(), "'#' expected");
4210 return MatchOperand_ParseFail;
4212 Parser.Lex(); // Eat hash token.
4214 const MCExpr *LSBExpr;
4215 SMLoc E = Parser.getTok().getLoc();
4216 if (getParser().parseExpression(LSBExpr)) {
4217 Error(E, "malformed immediate expression");
4218 return MatchOperand_ParseFail;
4220 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
4222 Error(E, "'lsb' operand must be an immediate");
4223 return MatchOperand_ParseFail;
4226 int64_t LSB = CE->getValue();
4227 // The LSB must be in the range [0,31]
4228 if (LSB < 0 || LSB > 31) {
4229 Error(E, "'lsb' operand must be in the range [0,31]");
4230 return MatchOperand_ParseFail;
4232 E = Parser.getTok().getLoc();
4234 // Expect another immediate operand.
4235 if (Parser.getTok().isNot(AsmToken::Comma)) {
4236 Error(Parser.getTok().getLoc(), "too few operands");
4237 return MatchOperand_ParseFail;
4239 Parser.Lex(); // Eat hash token.
4240 if (Parser.getTok().isNot(AsmToken::Hash) &&
4241 Parser.getTok().isNot(AsmToken::Dollar)) {
4242 Error(Parser.getTok().getLoc(), "'#' expected");
4243 return MatchOperand_ParseFail;
4245 Parser.Lex(); // Eat hash token.
4247 const MCExpr *WidthExpr;
4249 if (getParser().parseExpression(WidthExpr, EndLoc)) {
4250 Error(E, "malformed immediate expression");
4251 return MatchOperand_ParseFail;
4253 CE = dyn_cast<MCConstantExpr>(WidthExpr);
4255 Error(E, "'width' operand must be an immediate");
4256 return MatchOperand_ParseFail;
4259 int64_t Width = CE->getValue();
4260 // The LSB must be in the range [1,32-lsb]
4261 if (Width < 1 || Width > 32 - LSB) {
4262 Error(E, "'width' operand must be in the range [1,32-lsb]");
4263 return MatchOperand_ParseFail;
4266 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4268 return MatchOperand_Success;
4271 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4272 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4273 // Check for a post-index addressing register operand. Specifically:
4274 // postidx_reg := '+' register {, shift}
4275 // | '-' register {, shift}
4276 // | register {, shift}
4278 // This method must return MatchOperand_NoMatch without consuming any tokens
4279 // in the case where there is no match, as other alternatives take other
4281 AsmToken Tok = Parser.getTok();
4282 SMLoc S = Tok.getLoc();
4283 bool haveEaten = false;
4285 if (Tok.is(AsmToken::Plus)) {
4286 Parser.Lex(); // Eat the '+' token.
4288 } else if (Tok.is(AsmToken::Minus)) {
4289 Parser.Lex(); // Eat the '-' token.
4294 SMLoc E = Parser.getTok().getEndLoc();
4295 int Reg = tryParseRegister();
4298 return MatchOperand_NoMatch;
4299 Error(Parser.getTok().getLoc(), "register expected");
4300 return MatchOperand_ParseFail;
4303 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4304 unsigned ShiftImm = 0;
4305 if (Parser.getTok().is(AsmToken::Comma)) {
4306 Parser.Lex(); // Eat the ','.
4307 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4308 return MatchOperand_ParseFail;
4310 // FIXME: Only approximates end...may include intervening whitespace.
4311 E = Parser.getTok().getLoc();
4314 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4317 return MatchOperand_Success;
4320 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4321 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4322 // Check for a post-index addressing register operand. Specifically:
4323 // am3offset := '+' register
4330 // This method must return MatchOperand_NoMatch without consuming any tokens
4331 // in the case where there is no match, as other alternatives take other
4333 AsmToken Tok = Parser.getTok();
4334 SMLoc S = Tok.getLoc();
4336 // Do immediates first, as we always parse those if we have a '#'.
4337 if (Parser.getTok().is(AsmToken::Hash) ||
4338 Parser.getTok().is(AsmToken::Dollar)) {
4339 Parser.Lex(); // Eat '#' or '$'.
4340 // Explicitly look for a '-', as we need to encode negative zero
4342 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4343 const MCExpr *Offset;
4345 if (getParser().parseExpression(Offset, E))
4346 return MatchOperand_ParseFail;
4347 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4349 Error(S, "constant expression expected");
4350 return MatchOperand_ParseFail;
4352 // Negative zero is encoded as the flag value INT32_MIN.
4353 int32_t Val = CE->getValue();
4354 if (isNegative && Val == 0)
4358 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4360 return MatchOperand_Success;
4364 bool haveEaten = false;
4366 if (Tok.is(AsmToken::Plus)) {
4367 Parser.Lex(); // Eat the '+' token.
4369 } else if (Tok.is(AsmToken::Minus)) {
4370 Parser.Lex(); // Eat the '-' token.
4375 Tok = Parser.getTok();
4376 int Reg = tryParseRegister();
4379 return MatchOperand_NoMatch;
4380 Error(Tok.getLoc(), "register expected");
4381 return MatchOperand_ParseFail;
4384 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4385 0, S, Tok.getEndLoc()));
4387 return MatchOperand_Success;
4390 /// Convert parsed operands to MCInst. Needed here because this instruction
4391 /// only has two register operands, but multiplication is commutative so
4392 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4394 cvtThumbMultiply(MCInst &Inst,
4395 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4396 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4397 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4398 // If we have a three-operand form, make sure to set Rn to be the operand
4399 // that isn't the same as Rd.
4401 if (Operands.size() == 6 &&
4402 ((ARMOperand*)Operands[4])->getReg() ==
4403 ((ARMOperand*)Operands[3])->getReg())
4405 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4406 Inst.addOperand(Inst.getOperand(0));
4407 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4411 cvtThumbBranches(MCInst &Inst,
4412 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4413 int CondOp = -1, ImmOp = -1;
4414 switch(Inst.getOpcode()) {
4416 case ARM::tBcc: CondOp = 1; ImmOp = 2; break;
4419 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4421 default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4423 // first decide whether or not the branch should be conditional
4424 // by looking at it's location relative to an IT block
4426 // inside an IT block we cannot have any conditional branches. any
4427 // such instructions needs to be converted to unconditional form
4428 switch(Inst.getOpcode()) {
4429 case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4430 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4433 // outside IT blocks we can only have unconditional branches with AL
4434 // condition code or conditional branches with non-AL condition code
4435 unsigned Cond = static_cast<ARMOperand*>(Operands[CondOp])->getCondCode();
4436 switch(Inst.getOpcode()) {
4439 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4443 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4448 // now decide on encoding size based on branch target range
4449 switch(Inst.getOpcode()) {
4450 // classify tB as either t2B or t1B based on range of immediate operand
4452 ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4453 if(!op->isSignedOffset<11, 1>() && isThumbTwo())
4454 Inst.setOpcode(ARM::t2B);
4457 // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4459 ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4460 if(!op->isSignedOffset<8, 1>() && isThumbTwo())
4461 Inst.setOpcode(ARM::t2Bcc);
4465 ((ARMOperand*)Operands[ImmOp])->addImmOperands(Inst, 1);
4466 ((ARMOperand*)Operands[CondOp])->addCondCodeOperands(Inst, 2);
4469 /// Parse an ARM memory expression, return false if successful else return true
4470 /// or an error. The first token must be a '[' when called.
4472 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4474 assert(Parser.getTok().is(AsmToken::LBrac) &&
4475 "Token is not a Left Bracket");
4476 S = Parser.getTok().getLoc();
4477 Parser.Lex(); // Eat left bracket token.
4479 const AsmToken &BaseRegTok = Parser.getTok();
4480 int BaseRegNum = tryParseRegister();
4481 if (BaseRegNum == -1)
4482 return Error(BaseRegTok.getLoc(), "register expected");
4484 // The next token must either be a comma, a colon or a closing bracket.
4485 const AsmToken &Tok = Parser.getTok();
4486 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4487 !Tok.is(AsmToken::RBrac))
4488 return Error(Tok.getLoc(), "malformed memory operand");
4490 if (Tok.is(AsmToken::RBrac)) {
4491 E = Tok.getEndLoc();
4492 Parser.Lex(); // Eat right bracket token.
4494 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4495 ARM_AM::no_shift, 0, 0, false,
4498 // If there's a pre-indexing writeback marker, '!', just add it as a token
4499 // operand. It's rather odd, but syntactically valid.
4500 if (Parser.getTok().is(AsmToken::Exclaim)) {
4501 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4502 Parser.Lex(); // Eat the '!'.
4508 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4509 "Lost colon or comma in memory operand?!");
4510 if (Tok.is(AsmToken::Comma)) {
4511 Parser.Lex(); // Eat the comma.
4514 // If we have a ':', it's an alignment specifier.
4515 if (Parser.getTok().is(AsmToken::Colon)) {
4516 Parser.Lex(); // Eat the ':'.
4517 E = Parser.getTok().getLoc();
4518 SMLoc AlignmentLoc = Tok.getLoc();
4521 if (getParser().parseExpression(Expr))
4524 // The expression has to be a constant. Memory references with relocations
4525 // don't come through here, as they use the <label> forms of the relevant
4527 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4529 return Error (E, "constant expression expected");
4532 switch (CE->getValue()) {
4535 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4536 case 16: Align = 2; break;
4537 case 32: Align = 4; break;
4538 case 64: Align = 8; break;
4539 case 128: Align = 16; break;
4540 case 256: Align = 32; break;
4543 // Now we should have the closing ']'
4544 if (Parser.getTok().isNot(AsmToken::RBrac))
4545 return Error(Parser.getTok().getLoc(), "']' expected");
4546 E = Parser.getTok().getEndLoc();
4547 Parser.Lex(); // Eat right bracket token.
4549 // Don't worry about range checking the value here. That's handled by
4550 // the is*() predicates.
4551 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4552 ARM_AM::no_shift, 0, Align,
4553 false, S, E, AlignmentLoc));
4555 // If there's a pre-indexing writeback marker, '!', just add it as a token
4557 if (Parser.getTok().is(AsmToken::Exclaim)) {
4558 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4559 Parser.Lex(); // Eat the '!'.
4565 // If we have a '#', it's an immediate offset, else assume it's a register
4566 // offset. Be friendly and also accept a plain integer (without a leading
4567 // hash) for gas compatibility.
4568 if (Parser.getTok().is(AsmToken::Hash) ||
4569 Parser.getTok().is(AsmToken::Dollar) ||
4570 Parser.getTok().is(AsmToken::Integer)) {
4571 if (Parser.getTok().isNot(AsmToken::Integer))
4572 Parser.Lex(); // Eat '#' or '$'.
4573 E = Parser.getTok().getLoc();
4575 bool isNegative = getParser().getTok().is(AsmToken::Minus);
4576 const MCExpr *Offset;
4577 if (getParser().parseExpression(Offset))
4580 // The expression has to be a constant. Memory references with relocations
4581 // don't come through here, as they use the <label> forms of the relevant
4583 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4585 return Error (E, "constant expression expected");
4587 // If the constant was #-0, represent it as INT32_MIN.
4588 int32_t Val = CE->getValue();
4589 if (isNegative && Val == 0)
4590 CE = MCConstantExpr::Create(INT32_MIN, getContext());
4592 // Now we should have the closing ']'
4593 if (Parser.getTok().isNot(AsmToken::RBrac))
4594 return Error(Parser.getTok().getLoc(), "']' expected");
4595 E = Parser.getTok().getEndLoc();
4596 Parser.Lex(); // Eat right bracket token.
4598 // Don't worry about range checking the value here. That's handled by
4599 // the is*() predicates.
4600 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4601 ARM_AM::no_shift, 0, 0,
4604 // If there's a pre-indexing writeback marker, '!', just add it as a token
4606 if (Parser.getTok().is(AsmToken::Exclaim)) {
4607 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4608 Parser.Lex(); // Eat the '!'.
4614 // The register offset is optionally preceded by a '+' or '-'
4615 bool isNegative = false;
4616 if (Parser.getTok().is(AsmToken::Minus)) {
4618 Parser.Lex(); // Eat the '-'.
4619 } else if (Parser.getTok().is(AsmToken::Plus)) {
4621 Parser.Lex(); // Eat the '+'.
4624 E = Parser.getTok().getLoc();
4625 int OffsetRegNum = tryParseRegister();
4626 if (OffsetRegNum == -1)
4627 return Error(E, "register expected");
4629 // If there's a shift operator, handle it.
4630 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4631 unsigned ShiftImm = 0;
4632 if (Parser.getTok().is(AsmToken::Comma)) {
4633 Parser.Lex(); // Eat the ','.
4634 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4638 // Now we should have the closing ']'
4639 if (Parser.getTok().isNot(AsmToken::RBrac))
4640 return Error(Parser.getTok().getLoc(), "']' expected");
4641 E = Parser.getTok().getEndLoc();
4642 Parser.Lex(); // Eat right bracket token.
4644 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum,
4645 ShiftType, ShiftImm, 0, isNegative,
4648 // If there's a pre-indexing writeback marker, '!', just add it as a token
4650 if (Parser.getTok().is(AsmToken::Exclaim)) {
4651 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4652 Parser.Lex(); // Eat the '!'.
4658 /// parseMemRegOffsetShift - one of these two:
4659 /// ( lsl | lsr | asr | ror ) , # shift_amount
4661 /// return true if it parses a shift otherwise it returns false.
4662 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4664 SMLoc Loc = Parser.getTok().getLoc();
4665 const AsmToken &Tok = Parser.getTok();
4666 if (Tok.isNot(AsmToken::Identifier))
4668 StringRef ShiftName = Tok.getString();
4669 if (ShiftName == "lsl" || ShiftName == "LSL" ||
4670 ShiftName == "asl" || ShiftName == "ASL")
4672 else if (ShiftName == "lsr" || ShiftName == "LSR")
4674 else if (ShiftName == "asr" || ShiftName == "ASR")
4676 else if (ShiftName == "ror" || ShiftName == "ROR")
4678 else if (ShiftName == "rrx" || ShiftName == "RRX")
4681 return Error(Loc, "illegal shift operator");
4682 Parser.Lex(); // Eat shift type token.
4684 // rrx stands alone.
4686 if (St != ARM_AM::rrx) {
4687 Loc = Parser.getTok().getLoc();
4688 // A '#' and a shift amount.
4689 const AsmToken &HashTok = Parser.getTok();
4690 if (HashTok.isNot(AsmToken::Hash) &&
4691 HashTok.isNot(AsmToken::Dollar))
4692 return Error(HashTok.getLoc(), "'#' expected");
4693 Parser.Lex(); // Eat hash token.
4696 if (getParser().parseExpression(Expr))
4698 // Range check the immediate.
4699 // lsl, ror: 0 <= imm <= 31
4700 // lsr, asr: 0 <= imm <= 32
4701 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4703 return Error(Loc, "shift amount must be an immediate");
4704 int64_t Imm = CE->getValue();
4706 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4707 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4708 return Error(Loc, "immediate shift value out of range");
4709 // If <ShiftTy> #0, turn it into a no_shift.
4712 // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4721 /// parseFPImm - A floating point immediate expression operand.
4722 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4723 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4724 // Anything that can accept a floating point constant as an operand
4725 // needs to go through here, as the regular parseExpression is
4728 // This routine still creates a generic Immediate operand, containing
4729 // a bitcast of the 64-bit floating point value. The various operands
4730 // that accept floats can check whether the value is valid for them
4731 // via the standard is*() predicates.
4733 SMLoc S = Parser.getTok().getLoc();
4735 if (Parser.getTok().isNot(AsmToken::Hash) &&
4736 Parser.getTok().isNot(AsmToken::Dollar))
4737 return MatchOperand_NoMatch;
4739 // Disambiguate the VMOV forms that can accept an FP immediate.
4740 // vmov.f32 <sreg>, #imm
4741 // vmov.f64 <dreg>, #imm
4742 // vmov.f32 <dreg>, #imm @ vector f32x2
4743 // vmov.f32 <qreg>, #imm @ vector f32x4
4745 // There are also the NEON VMOV instructions which expect an
4746 // integer constant. Make sure we don't try to parse an FPImm
4748 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4749 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4750 bool isVmovf = TyOp->isToken() && (TyOp->getToken() == ".f32" ||
4751 TyOp->getToken() == ".f64");
4752 ARMOperand *Mnemonic = static_cast<ARMOperand*>(Operands[0]);
4753 bool isFconst = Mnemonic->isToken() && (Mnemonic->getToken() == "fconstd" ||
4754 Mnemonic->getToken() == "fconsts");
4755 if (!(isVmovf || isFconst))
4756 return MatchOperand_NoMatch;
4758 Parser.Lex(); // Eat '#' or '$'.
4760 // Handle negation, as that still comes through as a separate token.
4761 bool isNegative = false;
4762 if (Parser.getTok().is(AsmToken::Minus)) {
4766 const AsmToken &Tok = Parser.getTok();
4767 SMLoc Loc = Tok.getLoc();
4768 if (Tok.is(AsmToken::Real) && isVmovf) {
4769 APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4770 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4771 // If we had a '-' in front, toggle the sign bit.
4772 IntVal ^= (uint64_t)isNegative << 31;
4773 Parser.Lex(); // Eat the token.
4774 Operands.push_back(ARMOperand::CreateImm(
4775 MCConstantExpr::Create(IntVal, getContext()),
4776 S, Parser.getTok().getLoc()));
4777 return MatchOperand_Success;
4779 // Also handle plain integers. Instructions which allow floating point
4780 // immediates also allow a raw encoded 8-bit value.
4781 if (Tok.is(AsmToken::Integer) && isFconst) {
4782 int64_t Val = Tok.getIntVal();
4783 Parser.Lex(); // Eat the token.
4784 if (Val > 255 || Val < 0) {
4785 Error(Loc, "encoded floating point value out of range");
4786 return MatchOperand_ParseFail;
4788 float RealVal = ARM_AM::getFPImmFloat(Val);
4789 Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
4791 Operands.push_back(ARMOperand::CreateImm(
4792 MCConstantExpr::Create(Val, getContext()), S,
4793 Parser.getTok().getLoc()));
4794 return MatchOperand_Success;
4797 Error(Loc, "invalid floating point immediate");
4798 return MatchOperand_ParseFail;
4801 /// Parse a arm instruction operand. For now this parses the operand regardless
4802 /// of the mnemonic.
4803 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4804 StringRef Mnemonic) {
4807 // Check if the current operand has a custom associated parser, if so, try to
4808 // custom parse the operand, or fallback to the general approach.
4809 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4810 if (ResTy == MatchOperand_Success)
4812 // If there wasn't a custom match, try the generic matcher below. Otherwise,
4813 // there was a match, but an error occurred, in which case, just return that
4814 // the operand parsing failed.
4815 if (ResTy == MatchOperand_ParseFail)
4818 switch (getLexer().getKind()) {
4820 Error(Parser.getTok().getLoc(), "unexpected token in operand");
4822 case AsmToken::Identifier: {
4823 // If we've seen a branch mnemonic, the next operand must be a label. This
4824 // is true even if the label is a register name. So "br r1" means branch to
4826 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
4828 if (!tryParseRegisterWithWriteBack(Operands))
4830 int Res = tryParseShiftRegister(Operands);
4831 if (Res == 0) // success
4833 else if (Res == -1) // irrecoverable error
4835 // If this is VMRS, check for the apsr_nzcv operand.
4836 if (Mnemonic == "vmrs" &&
4837 Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4838 S = Parser.getTok().getLoc();
4840 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4845 // Fall though for the Identifier case that is not a register or a
4848 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
4849 case AsmToken::Integer: // things like 1f and 2b as a branch targets
4850 case AsmToken::String: // quoted label names.
4851 case AsmToken::Dot: { // . as a branch target
4852 // This was not a register so parse other operands that start with an
4853 // identifier (like labels) as expressions and create them as immediates.
4854 const MCExpr *IdVal;
4855 S = Parser.getTok().getLoc();
4856 if (getParser().parseExpression(IdVal))
4858 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4859 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4862 case AsmToken::LBrac:
4863 return parseMemory(Operands);
4864 case AsmToken::LCurly:
4865 return parseRegisterList(Operands);
4866 case AsmToken::Dollar:
4867 case AsmToken::Hash: {
4868 // #42 -> immediate.
4869 S = Parser.getTok().getLoc();
4872 if (Parser.getTok().isNot(AsmToken::Colon)) {
4873 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4874 const MCExpr *ImmVal;
4875 if (getParser().parseExpression(ImmVal))
4877 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4879 int32_t Val = CE->getValue();
4880 if (isNegative && Val == 0)
4881 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4883 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4884 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4886 // There can be a trailing '!' on operands that we want as a separate
4887 // '!' Token operand. Handle that here. For example, the compatibility
4888 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
4889 if (Parser.getTok().is(AsmToken::Exclaim)) {
4890 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
4891 Parser.getTok().getLoc()));
4892 Parser.Lex(); // Eat exclaim token
4896 // w/ a ':' after the '#', it's just like a plain ':'.
4899 case AsmToken::Colon: {
4900 // ":lower16:" and ":upper16:" expression prefixes
4901 // FIXME: Check it's an expression prefix,
4902 // e.g. (FOO - :lower16:BAR) isn't legal.
4903 ARMMCExpr::VariantKind RefKind;
4904 if (parsePrefix(RefKind))
4907 const MCExpr *SubExprVal;
4908 if (getParser().parseExpression(SubExprVal))
4911 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4913 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4914 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4917 case AsmToken::Equal: {
4918 if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
4919 return Error(Parser.getTok().getLoc(), "unexpected token in operand");
4921 Parser.Lex(); // Eat '='
4922 const MCExpr *SubExprVal;
4923 if (getParser().parseExpression(SubExprVal))
4925 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4927 const MCExpr *CPLoc = getTargetStreamer().addConstantPoolEntry(SubExprVal);
4928 Operands.push_back(ARMOperand::CreateImm(CPLoc, S, E));
4934 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4935 // :lower16: and :upper16:.
4936 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4937 RefKind = ARMMCExpr::VK_ARM_None;
4939 // consume an optional '#' (GNU compatibility)
4940 if (getLexer().is(AsmToken::Hash))
4943 // :lower16: and :upper16: modifiers
4944 assert(getLexer().is(AsmToken::Colon) && "expected a :");
4945 Parser.Lex(); // Eat ':'
4947 if (getLexer().isNot(AsmToken::Identifier)) {
4948 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4952 StringRef IDVal = Parser.getTok().getIdentifier();
4953 if (IDVal == "lower16") {
4954 RefKind = ARMMCExpr::VK_ARM_LO16;
4955 } else if (IDVal == "upper16") {
4956 RefKind = ARMMCExpr::VK_ARM_HI16;
4958 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4963 if (getLexer().isNot(AsmToken::Colon)) {
4964 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4967 Parser.Lex(); // Eat the last ':'
4971 /// \brief Given a mnemonic, split out possible predication code and carry
4972 /// setting letters to form a canonical mnemonic and flags.
4974 // FIXME: Would be nice to autogen this.
4975 // FIXME: This is a bit of a maze of special cases.
4976 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4977 unsigned &PredicationCode,
4979 unsigned &ProcessorIMod,
4980 StringRef &ITMask) {
4981 PredicationCode = ARMCC::AL;
4982 CarrySetting = false;
4985 // Ignore some mnemonics we know aren't predicated forms.
4987 // FIXME: Would be nice to autogen this.
4988 if ((Mnemonic == "movs" && isThumb()) ||
4989 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
4990 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
4991 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
4992 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
4993 Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" ||
4994 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
4995 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
4996 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4997 Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
4998 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" ||
4999 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
5000 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel"))
5003 // First, split out any predication code. Ignore mnemonics we know aren't
5004 // predicated but do have a carry-set and so weren't caught above.
5005 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
5006 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
5007 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
5008 Mnemonic != "sbcs" && Mnemonic != "rscs") {
5009 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
5010 .Case("eq", ARMCC::EQ)
5011 .Case("ne", ARMCC::NE)
5012 .Case("hs", ARMCC::HS)
5013 .Case("cs", ARMCC::HS)
5014 .Case("lo", ARMCC::LO)
5015 .Case("cc", ARMCC::LO)
5016 .Case("mi", ARMCC::MI)
5017 .Case("pl", ARMCC::PL)
5018 .Case("vs", ARMCC::VS)
5019 .Case("vc", ARMCC::VC)
5020 .Case("hi", ARMCC::HI)
5021 .Case("ls", ARMCC::LS)
5022 .Case("ge", ARMCC::GE)
5023 .Case("lt", ARMCC::LT)
5024 .Case("gt", ARMCC::GT)
5025 .Case("le", ARMCC::LE)
5026 .Case("al", ARMCC::AL)
5029 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
5030 PredicationCode = CC;
5034 // Next, determine if we have a carry setting bit. We explicitly ignore all
5035 // the instructions we know end in 's'.
5036 if (Mnemonic.endswith("s") &&
5037 !(Mnemonic == "cps" || Mnemonic == "mls" ||
5038 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
5039 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
5040 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
5041 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
5042 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
5043 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
5044 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
5045 Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
5046 (Mnemonic == "movs" && isThumb()))) {
5047 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
5048 CarrySetting = true;
5051 // The "cps" instruction can have a interrupt mode operand which is glued into
5052 // the mnemonic. Check if this is the case, split it and parse the imod op
5053 if (Mnemonic.startswith("cps")) {
5054 // Split out any imod code.
5056 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
5057 .Case("ie", ARM_PROC::IE)
5058 .Case("id", ARM_PROC::ID)
5061 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
5062 ProcessorIMod = IMod;
5066 // The "it" instruction has the condition mask on the end of the mnemonic.
5067 if (Mnemonic.startswith("it")) {
5068 ITMask = Mnemonic.slice(2, Mnemonic.size());
5069 Mnemonic = Mnemonic.slice(0, 2);
5075 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
5076 /// inclusion of carry set or predication code operands.
5078 // FIXME: It would be nice to autogen this.
5080 getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
5081 bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) {
5082 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5083 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
5084 Mnemonic == "add" || Mnemonic == "adc" ||
5085 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
5086 Mnemonic == "orr" || Mnemonic == "mvn" ||
5087 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
5088 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
5089 Mnemonic == "vfm" || Mnemonic == "vfnm" ||
5090 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
5091 Mnemonic == "mla" || Mnemonic == "smlal" ||
5092 Mnemonic == "umlal" || Mnemonic == "umull"))) {
5093 CanAcceptCarrySet = true;
5095 CanAcceptCarrySet = false;
5097 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
5098 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
5099 Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic.startswith("crc32") ||
5100 Mnemonic.startswith("cps") || Mnemonic.startswith("vsel") ||
5101 Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
5102 Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
5103 Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
5104 Mnemonic == "vrintm" || Mnemonic.startswith("aes") ||
5105 Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
5106 (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) {
5107 // These mnemonics are never predicable
5108 CanAcceptPredicationCode = false;
5109 } else if (!isThumb()) {
5110 // Some instructions are only predicable in Thumb mode
5111 CanAcceptPredicationCode
5112 = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
5113 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
5114 Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
5115 Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
5116 Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
5117 Mnemonic != "stc2" && Mnemonic != "stc2l" &&
5118 !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
5119 } else if (isThumbOne()) {
5121 CanAcceptPredicationCode = Mnemonic != "movs";
5123 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
5125 CanAcceptPredicationCode = true;
5128 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
5129 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5130 // FIXME: This is all horribly hacky. We really need a better way to deal
5131 // with optional operands like this in the matcher table.
5133 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
5134 // another does not. Specifically, the MOVW instruction does not. So we
5135 // special case it here and remove the defaulted (non-setting) cc_out
5136 // operand if that's the instruction we're trying to match.
5138 // We do this as post-processing of the explicit operands rather than just
5139 // conditionally adding the cc_out in the first place because we need
5140 // to check the type of the parsed immediate operand.
5141 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
5142 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
5143 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
5144 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
5147 // Register-register 'add' for thumb does not have a cc_out operand
5148 // when there are only two register operands.
5149 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
5150 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5151 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5152 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
5154 // Register-register 'add' for thumb does not have a cc_out operand
5155 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
5156 // have to check the immediate range here since Thumb2 has a variant
5157 // that can handle a different range and has a cc_out operand.
5158 if (((isThumb() && Mnemonic == "add") ||
5159 (isThumbTwo() && Mnemonic == "sub")) &&
5160 Operands.size() == 6 &&
5161 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5162 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5163 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
5164 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5165 ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
5166 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
5168 // For Thumb2, add/sub immediate does not have a cc_out operand for the
5169 // imm0_4095 variant. That's the least-preferred variant when
5170 // selecting via the generic "add" mnemonic, so to know that we
5171 // should remove the cc_out operand, we have to explicitly check that
5172 // it's not one of the other variants. Ugh.
5173 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
5174 Operands.size() == 6 &&
5175 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5176 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5177 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5178 // Nest conditions rather than one big 'if' statement for readability.
5180 // If both registers are low, we're in an IT block, and the immediate is
5181 // in range, we should use encoding T1 instead, which has a cc_out.
5183 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
5184 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
5185 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
5187 // Check against T3. If the second register is the PC, this is an
5188 // alternate form of ADR, which uses encoding T4, so check for that too.
5189 if (static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
5190 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
5193 // Otherwise, we use encoding T4, which does not have a cc_out
5198 // The thumb2 multiply instruction doesn't have a CCOut register, so
5199 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
5200 // use the 16-bit encoding or not.
5201 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5202 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5203 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5204 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5205 static_cast<ARMOperand*>(Operands[5])->isReg() &&
5206 // If the registers aren't low regs, the destination reg isn't the
5207 // same as one of the source regs, or the cc_out operand is zero
5208 // outside of an IT block, we have to use the 32-bit encoding, so
5209 // remove the cc_out operand.
5210 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
5211 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
5212 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
5214 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
5215 static_cast<ARMOperand*>(Operands[5])->getReg() &&
5216 static_cast<ARMOperand*>(Operands[3])->getReg() !=
5217 static_cast<ARMOperand*>(Operands[4])->getReg())))
5220 // Also check the 'mul' syntax variant that doesn't specify an explicit
5221 // destination register.
5222 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5223 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5224 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5225 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5226 // If the registers aren't low regs or the cc_out operand is zero
5227 // outside of an IT block, we have to use the 32-bit encoding, so
5228 // remove the cc_out operand.
5229 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
5230 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
5236 // Register-register 'add/sub' for thumb does not have a cc_out operand
5237 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5238 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
5239 // right, this will result in better diagnostics (which operand is off)
5241 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
5242 (Operands.size() == 5 || Operands.size() == 6) &&
5243 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5244 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
5245 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5246 (static_cast<ARMOperand*>(Operands[4])->isImm() ||
5247 (Operands.size() == 6 &&
5248 static_cast<ARMOperand*>(Operands[5])->isImm())))
5254 bool ARMAsmParser::shouldOmitPredicateOperand(
5255 StringRef Mnemonic, SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
5256 // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
5257 unsigned RegIdx = 3;
5258 if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
5259 static_cast<ARMOperand *>(Operands[2])->getToken() == ".f32") {
5260 if (static_cast<ARMOperand *>(Operands[3])->isToken() &&
5261 static_cast<ARMOperand *>(Operands[3])->getToken() == ".f32")
5264 if (static_cast<ARMOperand *>(Operands[RegIdx])->isReg() &&
5265 (ARMMCRegisterClasses[ARM::DPRRegClassID]
5266 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg()) ||
5267 ARMMCRegisterClasses[ARM::QPRRegClassID]
5268 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg())))
5274 static bool isDataTypeToken(StringRef Tok) {
5275 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5276 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5277 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5278 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5279 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5280 Tok == ".f" || Tok == ".d";
5283 // FIXME: This bit should probably be handled via an explicit match class
5284 // in the .td files that matches the suffix instead of having it be
5285 // a literal string token the way it is now.
5286 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5287 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5289 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
5290 unsigned VariantID);
5292 static bool RequiresVFPRegListValidation(StringRef Inst,
5293 bool &AcceptSinglePrecisionOnly,
5294 bool &AcceptDoublePrecisionOnly) {
5295 if (Inst.size() < 7)
5298 if (Inst.startswith("fldm") || Inst.startswith("fstm")) {
5299 StringRef AddressingMode = Inst.substr(4, 2);
5300 if (AddressingMode == "ia" || AddressingMode == "db" ||
5301 AddressingMode == "ea" || AddressingMode == "fd") {
5302 AcceptSinglePrecisionOnly = Inst[6] == 's';
5303 AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x';
5311 /// Parse an arm instruction mnemonic followed by its operands.
5312 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5314 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5315 // FIXME: Can this be done via tablegen in some fashion?
5316 bool RequireVFPRegisterListCheck;
5317 bool AcceptSinglePrecisionOnly;
5318 bool AcceptDoublePrecisionOnly;
5319 RequireVFPRegisterListCheck =
5320 RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly,
5321 AcceptDoublePrecisionOnly);
5323 // Apply mnemonic aliases before doing anything else, as the destination
5324 // mnemonic may include suffices and we want to handle them normally.
5325 // The generic tblgen'erated code does this later, at the start of
5326 // MatchInstructionImpl(), but that's too late for aliases that include
5327 // any sort of suffix.
5328 unsigned AvailableFeatures = getAvailableFeatures();
5329 unsigned AssemblerDialect = getParser().getAssemblerDialect();
5330 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5332 // First check for the ARM-specific .req directive.
5333 if (Parser.getTok().is(AsmToken::Identifier) &&
5334 Parser.getTok().getIdentifier() == ".req") {
5335 parseDirectiveReq(Name, NameLoc);
5336 // We always return 'error' for this, as we're done with this
5337 // statement and don't need to match the 'instruction."
5341 // Create the leading tokens for the mnemonic, split by '.' characters.
5342 size_t Start = 0, Next = Name.find('.');
5343 StringRef Mnemonic = Name.slice(Start, Next);
5345 // Split out the predication code and carry setting flag from the mnemonic.
5346 unsigned PredicationCode;
5347 unsigned ProcessorIMod;
5350 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5351 ProcessorIMod, ITMask);
5353 // In Thumb1, only the branch (B) instruction can be predicated.
5354 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5355 Parser.eatToEndOfStatement();
5356 return Error(NameLoc, "conditional execution not supported in Thumb1");
5359 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5361 // Handle the IT instruction ITMask. Convert it to a bitmask. This
5362 // is the mask as it will be for the IT encoding if the conditional
5363 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5364 // where the conditional bit0 is zero, the instruction post-processing
5365 // will adjust the mask accordingly.
5366 if (Mnemonic == "it") {
5367 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5368 if (ITMask.size() > 3) {
5369 Parser.eatToEndOfStatement();
5370 return Error(Loc, "too many conditions on IT instruction");
5373 for (unsigned i = ITMask.size(); i != 0; --i) {
5374 char pos = ITMask[i - 1];
5375 if (pos != 't' && pos != 'e') {
5376 Parser.eatToEndOfStatement();
5377 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5380 if (ITMask[i - 1] == 't')
5383 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5386 // FIXME: This is all a pretty gross hack. We should automatically handle
5387 // optional operands like this via tblgen.
5389 // Next, add the CCOut and ConditionCode operands, if needed.
5391 // For mnemonics which can ever incorporate a carry setting bit or predication
5392 // code, our matching model involves us always generating CCOut and
5393 // ConditionCode operands to match the mnemonic "as written" and then we let
5394 // the matcher deal with finding the right instruction or generating an
5395 // appropriate error.
5396 bool CanAcceptCarrySet, CanAcceptPredicationCode;
5397 getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
5399 // If we had a carry-set on an instruction that can't do that, issue an
5401 if (!CanAcceptCarrySet && CarrySetting) {
5402 Parser.eatToEndOfStatement();
5403 return Error(NameLoc, "instruction '" + Mnemonic +
5404 "' can not set flags, but 's' suffix specified");
5406 // If we had a predication code on an instruction that can't do that, issue an
5408 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5409 Parser.eatToEndOfStatement();
5410 return Error(NameLoc, "instruction '" + Mnemonic +
5411 "' is not predicable, but condition code specified");
5414 // Add the carry setting operand, if necessary.
5415 if (CanAcceptCarrySet) {
5416 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5417 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5421 // Add the predication code operand, if necessary.
5422 if (CanAcceptPredicationCode) {
5423 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5425 Operands.push_back(ARMOperand::CreateCondCode(
5426 ARMCC::CondCodes(PredicationCode), Loc));
5429 // Add the processor imod operand, if necessary.
5430 if (ProcessorIMod) {
5431 Operands.push_back(ARMOperand::CreateImm(
5432 MCConstantExpr::Create(ProcessorIMod, getContext()),
5436 // Add the remaining tokens in the mnemonic.
5437 while (Next != StringRef::npos) {
5439 Next = Name.find('.', Start + 1);
5440 StringRef ExtraToken = Name.slice(Start, Next);
5442 // Some NEON instructions have an optional datatype suffix that is
5443 // completely ignored. Check for that.
5444 if (isDataTypeToken(ExtraToken) &&
5445 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5448 // For for ARM mode generate an error if the .n qualifier is used.
5449 if (ExtraToken == ".n" && !isThumb()) {
5450 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5451 Parser.eatToEndOfStatement();
5452 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5456 // The .n qualifier is always discarded as that is what the tables
5457 // and matcher expect. In ARM mode the .w qualifier has no effect,
5458 // so discard it to avoid errors that can be caused by the matcher.
5459 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5460 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5461 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5465 // Read the remaining operands.
5466 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5467 // Read the first operand.
5468 if (parseOperand(Operands, Mnemonic)) {
5469 Parser.eatToEndOfStatement();
5473 while (getLexer().is(AsmToken::Comma)) {
5474 Parser.Lex(); // Eat the comma.
5476 // Parse and remember the operand.
5477 if (parseOperand(Operands, Mnemonic)) {
5478 Parser.eatToEndOfStatement();
5484 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5485 SMLoc Loc = getLexer().getLoc();
5486 Parser.eatToEndOfStatement();
5487 return Error(Loc, "unexpected token in argument list");
5490 Parser.Lex(); // Consume the EndOfStatement
5492 if (RequireVFPRegisterListCheck) {
5493 ARMOperand *Op = static_cast<ARMOperand*>(Operands.back());
5494 if (AcceptSinglePrecisionOnly && !Op->isSPRRegList())
5495 return Error(Op->getStartLoc(),
5496 "VFP/Neon single precision register expected");
5497 if (AcceptDoublePrecisionOnly && !Op->isDPRRegList())
5498 return Error(Op->getStartLoc(),
5499 "VFP/Neon double precision register expected");
5502 // Some instructions, mostly Thumb, have forms for the same mnemonic that
5503 // do and don't have a cc_out optional-def operand. With some spot-checks
5504 // of the operand list, we can figure out which variant we're trying to
5505 // parse and adjust accordingly before actually matching. We shouldn't ever
5506 // try to remove a cc_out operand that was explicitly set on the the
5507 // mnemonic, of course (CarrySetting == true). Reason number #317 the
5508 // table driven matcher doesn't fit well with the ARM instruction set.
5509 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5510 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5511 Operands.erase(Operands.begin() + 1);
5515 // Some instructions have the same mnemonic, but don't always
5516 // have a predicate. Distinguish them here and delete the
5517 // predicate if needed.
5518 if (shouldOmitPredicateOperand(Mnemonic, Operands)) {
5519 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5520 Operands.erase(Operands.begin() + 1);
5524 // ARM mode 'blx' need special handling, as the register operand version
5525 // is predicable, but the label operand version is not. So, we can't rely
5526 // on the Mnemonic based checking to correctly figure out when to put
5527 // a k_CondCode operand in the list. If we're trying to match the label
5528 // version, remove the k_CondCode operand here.
5529 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5530 static_cast<ARMOperand*>(Operands[2])->isImm()) {
5531 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5532 Operands.erase(Operands.begin() + 1);
5536 // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5537 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5538 // a single GPRPair reg operand is used in the .td file to replace the two
5539 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5540 // expressed as a GPRPair, so we have to manually merge them.
5541 // FIXME: We would really like to be able to tablegen'erate this.
5542 if (!isThumb() && Operands.size() > 4 &&
5543 (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
5544 Mnemonic == "stlexd")) {
5545 bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
5546 unsigned Idx = isLoad ? 2 : 3;
5547 ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]);
5548 ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]);
5550 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5551 // Adjust only if Op1 and Op2 are GPRs.
5552 if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) &&
5553 MRC.contains(Op2->getReg())) {
5554 unsigned Reg1 = Op1->getReg();
5555 unsigned Reg2 = Op2->getReg();
5556 unsigned Rt = MRI->getEncodingValue(Reg1);
5557 unsigned Rt2 = MRI->getEncodingValue(Reg2);
5559 // Rt2 must be Rt + 1 and Rt must be even.
5560 if (Rt + 1 != Rt2 || (Rt & 1)) {
5561 Error(Op2->getStartLoc(), isLoad ?
5562 "destination operands must be sequential" :
5563 "source operands must be sequential");
5566 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5567 &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5568 Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2);
5569 Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg(
5570 NewReg, Op1->getStartLoc(), Op2->getEndLoc()));
5576 // GNU Assembler extension (compatibility)
5577 if ((Mnemonic == "ldrd" || Mnemonic == "strd")) {
5578 ARMOperand *Op2 = static_cast<ARMOperand *>(Operands[2]);
5579 ARMOperand *Op3 = static_cast<ARMOperand *>(Operands[3]);
5581 assert(Op2->isReg() && "expected register argument");
5583 unsigned SuperReg = MRI->getMatchingSuperReg(
5584 Op2->getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID));
5586 assert(SuperReg && "expected register pair");
5588 unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1);
5590 Operands.insert(Operands.begin() + 3,
5591 ARMOperand::CreateReg(PairedReg,
5597 // FIXME: As said above, this is all a pretty gross hack. This instruction
5598 // does not fit with other "subs" and tblgen.
5599 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
5600 // so the Mnemonic is the original name "subs" and delete the predicate
5601 // operand so it will match the table entry.
5602 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
5603 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5604 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::PC &&
5605 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5606 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::LR &&
5607 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5608 ARMOperand *Op0 = static_cast<ARMOperand*>(Operands[0]);
5609 Operands.erase(Operands.begin());
5611 Operands.insert(Operands.begin(), ARMOperand::CreateToken(Name, NameLoc));
5613 ARMOperand *Op1 = static_cast<ARMOperand*>(Operands[1]);
5614 Operands.erase(Operands.begin() + 1);
5620 // Validate context-sensitive operand constraints.
5622 // return 'true' if register list contains non-low GPR registers,
5623 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5624 // 'containsReg' to true.
5625 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5626 unsigned HiReg, bool &containsReg) {
5627 containsReg = false;
5628 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5629 unsigned OpReg = Inst.getOperand(i).getReg();
5632 // Anything other than a low register isn't legal here.
5633 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5639 // Check if the specified regisgter is in the register list of the inst,
5640 // starting at the indicated operand number.
5641 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5642 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5643 unsigned OpReg = Inst.getOperand(i).getReg();
5650 // Return true if instruction has the interesting property of being
5651 // allowed in IT blocks, but not being predicable.
5652 static bool instIsBreakpoint(const MCInst &Inst) {
5653 return Inst.getOpcode() == ARM::tBKPT ||
5654 Inst.getOpcode() == ARM::BKPT ||
5655 Inst.getOpcode() == ARM::tHLT ||
5656 Inst.getOpcode() == ARM::HLT;
5660 // FIXME: We would really like to be able to tablegen'erate this.
5662 validateInstruction(MCInst &Inst,
5663 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5664 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
5665 SMLoc Loc = Operands[0]->getStartLoc();
5667 // Check the IT block state first.
5668 // NOTE: BKPT and HLT instructions have the interesting property of being
5669 // allowed in IT blocks, but not being predicable. They just always execute.
5670 if (inITBlock() && !instIsBreakpoint(Inst)) {
5672 if (ITState.FirstCond)
5673 ITState.FirstCond = false;
5675 Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5676 // The instruction must be predicable.
5677 if (!MCID.isPredicable())
5678 return Error(Loc, "instructions in IT block must be predicable");
5679 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5680 unsigned ITCond = Bit ? ITState.Cond :
5681 ARMCC::getOppositeCondition(ITState.Cond);
5682 if (Cond != ITCond) {
5683 // Find the condition code Operand to get its SMLoc information.
5685 for (unsigned I = 1; I < Operands.size(); ++I)
5686 if (static_cast<ARMOperand*>(Operands[I])->isCondCode())
5687 CondLoc = Operands[I]->getStartLoc();
5688 return Error(CondLoc, "incorrect condition in IT block; got '" +
5689 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5690 "', but expected '" +
5691 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5693 // Check for non-'al' condition codes outside of the IT block.
5694 } else if (isThumbTwo() && MCID.isPredicable() &&
5695 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5696 ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
5697 Inst.getOpcode() != ARM::t2Bcc)
5698 return Error(Loc, "predicated instructions must be in IT block");
5700 const unsigned Opcode = Inst.getOpcode();
5704 case ARM::LDRD_POST: {
5705 const unsigned RtReg = Inst.getOperand(0).getReg();
5708 if (RtReg == ARM::LR)
5709 return Error(Operands[3]->getStartLoc(),
5712 const unsigned Rt = MRI->getEncodingValue(RtReg);
5713 // Rt must be even-numbered.
5715 return Error(Operands[3]->getStartLoc(),
5716 "Rt must be even-numbered");
5718 // Rt2 must be Rt + 1.
5719 const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5721 return Error(Operands[3]->getStartLoc(),
5722 "destination operands must be sequential");
5724 if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) {
5725 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
5726 // For addressing modes with writeback, the base register needs to be
5727 // different from the destination registers.
5728 if (Rn == Rt || Rn == Rt2)
5729 return Error(Operands[3]->getStartLoc(),
5730 "base register needs to be different from destination "
5737 case ARM::t2LDRD_PRE:
5738 case ARM::t2LDRD_POST: {
5739 // Rt2 must be different from Rt.
5740 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5741 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5743 return Error(Operands[3]->getStartLoc(),
5744 "destination operands can't be identical");
5748 // Rt2 must be Rt + 1.
5749 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5750 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5752 return Error(Operands[3]->getStartLoc(),
5753 "source operands must be sequential");
5757 case ARM::STRD_POST: {
5758 // Rt2 must be Rt + 1.
5759 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5760 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5762 return Error(Operands[3]->getStartLoc(),
5763 "source operands must be sequential");
5768 // Width must be in range [1, 32-lsb].
5769 unsigned LSB = Inst.getOperand(2).getImm();
5770 unsigned Widthm1 = Inst.getOperand(3).getImm();
5771 if (Widthm1 >= 32 - LSB)
5772 return Error(Operands[5]->getStartLoc(),
5773 "bitfield width must be in range [1,32-lsb]");
5776 // Notionally handles ARM::tLDMIA_UPD too.
5778 // If we're parsing Thumb2, the .w variant is available and handles
5779 // most cases that are normally illegal for a Thumb1 LDM instruction.
5780 // We'll make the transformation in processInstruction() if necessary.
5782 // Thumb LDM instructions are writeback iff the base register is not
5783 // in the register list.
5784 unsigned Rn = Inst.getOperand(0).getReg();
5785 bool HasWritebackToken =
5786 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5787 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5788 bool ListContainsBase;
5789 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
5790 return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
5791 "registers must be in range r0-r7");
5792 // If we should have writeback, then there should be a '!' token.
5793 if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
5794 return Error(Operands[2]->getStartLoc(),
5795 "writeback operator '!' expected");
5796 // If we should not have writeback, there must not be a '!'. This is
5797 // true even for the 32-bit wide encodings.
5798 if (ListContainsBase && HasWritebackToken)
5799 return Error(Operands[3]->getStartLoc(),
5800 "writeback operator '!' not allowed when base register "
5801 "in register list");
5805 case ARM::LDMIA_UPD:
5806 case ARM::LDMDB_UPD:
5807 case ARM::LDMIB_UPD:
5808 case ARM::LDMDA_UPD:
5809 // ARM variants loading and updating the same register are only officially
5810 // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
5814 case ARM::t2LDMIA_UPD:
5815 case ARM::t2LDMDB_UPD:
5816 case ARM::t2STMIA_UPD:
5817 case ARM::t2STMDB_UPD: {
5818 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5819 return Error(Operands.back()->getStartLoc(),
5820 "writeback register not allowed in register list");
5823 case ARM::sysLDMIA_UPD:
5824 case ARM::sysLDMDA_UPD:
5825 case ARM::sysLDMDB_UPD:
5826 case ARM::sysLDMIB_UPD:
5827 if (!listContainsReg(Inst, 3, ARM::PC))
5828 return Error(Operands[4]->getStartLoc(),
5829 "writeback register only allowed on system LDM "
5830 "if PC in register-list");
5832 case ARM::sysSTMIA_UPD:
5833 case ARM::sysSTMDA_UPD:
5834 case ARM::sysSTMDB_UPD:
5835 case ARM::sysSTMIB_UPD:
5836 return Error(Operands[2]->getStartLoc(),
5837 "system STM cannot have writeback register");
5839 // The second source operand must be the same register as the destination
5842 // In this case, we must directly check the parsed operands because the
5843 // cvtThumbMultiply() function is written in such a way that it guarantees
5844 // this first statement is always true for the new Inst. Essentially, the
5845 // destination is unconditionally copied into the second source operand
5846 // without checking to see if it matches what we actually parsed.
5847 if (Operands.size() == 6 &&
5848 (((ARMOperand*)Operands[3])->getReg() !=
5849 ((ARMOperand*)Operands[5])->getReg()) &&
5850 (((ARMOperand*)Operands[3])->getReg() !=
5851 ((ARMOperand*)Operands[4])->getReg())) {
5852 return Error(Operands[3]->getStartLoc(),
5853 "destination register must match source register");
5857 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5858 // so only issue a diagnostic for thumb1. The instructions will be
5859 // switched to the t2 encodings in processInstruction() if necessary.
5861 bool ListContainsBase;
5862 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
5864 return Error(Operands[2]->getStartLoc(),
5865 "registers must be in range r0-r7 or pc");
5869 bool ListContainsBase;
5870 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
5872 return Error(Operands[2]->getStartLoc(),
5873 "registers must be in range r0-r7 or lr");
5876 case ARM::tSTMIA_UPD: {
5877 bool ListContainsBase, InvalidLowList;
5878 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
5879 0, ListContainsBase);
5880 if (InvalidLowList && !isThumbTwo())
5881 return Error(Operands[4]->getStartLoc(),
5882 "registers must be in range r0-r7");
5884 // This would be converted to a 32-bit stm, but that's not valid if the
5885 // writeback register is in the list.
5886 if (InvalidLowList && ListContainsBase)
5887 return Error(Operands[4]->getStartLoc(),
5888 "writeback operator '!' not allowed when base register "
5889 "in register list");
5892 case ARM::tADDrSP: {
5893 // If the non-SP source operand and the destination operand are not the
5894 // same, we need thumb2 (for the wide encoding), or we have an error.
5895 if (!isThumbTwo() &&
5896 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5897 return Error(Operands[4]->getStartLoc(),
5898 "source register must be the same as destination");
5902 // Final range checking for Thumb unconditional branch instructions.
5904 if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<11, 1>())
5905 return Error(Operands[2]->getStartLoc(), "branch target out of range");
5908 int op = (Operands[2]->isImm()) ? 2 : 3;
5909 if (!(static_cast<ARMOperand*>(Operands[op]))->isSignedOffset<24, 1>())
5910 return Error(Operands[op]->getStartLoc(), "branch target out of range");
5913 // Final range checking for Thumb conditional branch instructions.
5915 if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<8, 1>())
5916 return Error(Operands[2]->getStartLoc(), "branch target out of range");
5919 int Op = (Operands[2]->isImm()) ? 2 : 3;
5920 if (!(static_cast<ARMOperand*>(Operands[Op]))->isSignedOffset<20, 1>())
5921 return Error(Operands[Op]->getStartLoc(), "branch target out of range");
5926 case ARM::t2MOVTi16:
5928 // We want to avoid misleadingly allowing something like "mov r0, <symbol>"
5929 // especially when we turn it into a movw and the expression <symbol> does
5930 // not have a :lower16: or :upper16 as part of the expression. We don't
5931 // want the behavior of silently truncating, which can be unexpected and
5932 // lead to bugs that are difficult to find since this is an easy mistake
5934 int i = (Operands[3]->isImm()) ? 3 : 4;
5935 ARMOperand *Op = static_cast<ARMOperand*>(Operands[i]);
5936 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5938 const MCExpr *E = dyn_cast<MCExpr>(Op->getImm());
5940 const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E);
5941 if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
5942 ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16)) {
5943 return Error(Op->getStartLoc(),
5944 "immediate expression for mov requires :lower16: or :upper16");
5953 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5955 default: llvm_unreachable("unexpected opcode!");
5957 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5958 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5959 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5960 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5961 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5962 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5963 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
5964 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5965 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5968 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5969 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5970 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5971 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5972 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5974 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5975 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5976 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5977 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5978 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5980 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
5981 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5982 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5983 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5984 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5987 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5988 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5989 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5990 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5991 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5992 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5993 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5994 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5995 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5996 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5997 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
5998 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5999 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
6000 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
6001 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
6004 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
6005 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6006 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6007 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
6008 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6009 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6010 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
6011 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6012 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6013 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
6014 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6015 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6016 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
6017 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
6018 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
6019 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
6020 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
6021 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
6024 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
6025 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6026 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6027 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
6028 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6029 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
6030 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6031 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6032 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
6033 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6034 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
6035 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
6036 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
6037 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
6038 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
6041 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
6042 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6043 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6044 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
6045 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6046 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6047 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
6048 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6049 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6050 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
6051 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6052 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6053 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
6054 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
6055 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
6056 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
6057 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
6058 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
6062 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
6064 default: llvm_unreachable("unexpected opcode!");
6066 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
6067 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6068 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6069 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
6070 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6071 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6072 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
6073 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
6074 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
6077 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
6078 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6079 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6080 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
6081 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6082 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
6083 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6084 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6085 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
6086 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6087 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
6088 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
6089 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
6090 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
6091 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
6094 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
6095 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6096 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6097 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
6098 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6099 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6100 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
6101 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6102 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6103 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
6104 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6105 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6106 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
6107 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
6108 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
6109 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
6110 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
6111 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
6114 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
6115 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6116 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6117 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
6118 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6119 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
6120 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6121 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6122 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
6123 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6124 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
6125 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
6126 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
6127 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
6128 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
6131 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
6132 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6133 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6134 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
6135 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6136 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6137 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
6138 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6139 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6140 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
6141 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6142 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6143 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
6144 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
6145 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
6146 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
6147 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
6148 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
6151 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
6152 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6153 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6154 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6155 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6156 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
6157 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6158 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6159 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6160 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6161 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
6162 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
6163 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
6164 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
6165 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
6168 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
6169 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6170 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6171 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
6172 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
6173 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6174 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
6175 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6176 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6177 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
6178 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
6179 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6180 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
6181 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
6182 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
6183 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
6184 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
6185 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
6188 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
6189 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6190 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6191 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
6192 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6193 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6194 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
6195 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6196 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6197 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
6198 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6199 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6200 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
6201 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
6202 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
6203 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
6204 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
6205 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
6210 processInstruction(MCInst &Inst,
6211 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
6212 switch (Inst.getOpcode()) {
6213 // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
6214 case ARM::LDRT_POST:
6215 case ARM::LDRBT_POST: {
6216 const unsigned Opcode =
6217 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
6218 : ARM::LDRBT_POST_IMM;
6220 TmpInst.setOpcode(Opcode);
6221 TmpInst.addOperand(Inst.getOperand(0));
6222 TmpInst.addOperand(Inst.getOperand(1));
6223 TmpInst.addOperand(Inst.getOperand(1));
6224 TmpInst.addOperand(MCOperand::CreateReg(0));
6225 TmpInst.addOperand(MCOperand::CreateImm(0));
6226 TmpInst.addOperand(Inst.getOperand(2));
6227 TmpInst.addOperand(Inst.getOperand(3));
6231 // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
6232 case ARM::STRT_POST:
6233 case ARM::STRBT_POST: {
6234 const unsigned Opcode =
6235 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
6236 : ARM::STRBT_POST_IMM;
6238 TmpInst.setOpcode(Opcode);
6239 TmpInst.addOperand(Inst.getOperand(1));
6240 TmpInst.addOperand(Inst.getOperand(0));
6241 TmpInst.addOperand(Inst.getOperand(1));
6242 TmpInst.addOperand(MCOperand::CreateReg(0));
6243 TmpInst.addOperand(MCOperand::CreateImm(0));
6244 TmpInst.addOperand(Inst.getOperand(2));
6245 TmpInst.addOperand(Inst.getOperand(3));
6249 // Alias for alternate form of 'ADR Rd, #imm' instruction.
6251 if (Inst.getOperand(1).getReg() != ARM::PC ||
6252 Inst.getOperand(5).getReg() != 0)
6255 TmpInst.setOpcode(ARM::ADR);
6256 TmpInst.addOperand(Inst.getOperand(0));
6257 TmpInst.addOperand(Inst.getOperand(2));
6258 TmpInst.addOperand(Inst.getOperand(3));
6259 TmpInst.addOperand(Inst.getOperand(4));
6263 // Aliases for alternate PC+imm syntax of LDR instructions.
6264 case ARM::t2LDRpcrel:
6265 // Select the narrow version if the immediate will fit.
6266 if (Inst.getOperand(1).getImm() > 0 &&
6267 Inst.getOperand(1).getImm() <= 0xff &&
6268 !(static_cast<ARMOperand*>(Operands[2])->isToken() &&
6269 static_cast<ARMOperand*>(Operands[2])->getToken() == ".w"))
6270 Inst.setOpcode(ARM::tLDRpci);
6272 Inst.setOpcode(ARM::t2LDRpci);
6274 case ARM::t2LDRBpcrel:
6275 Inst.setOpcode(ARM::t2LDRBpci);
6277 case ARM::t2LDRHpcrel:
6278 Inst.setOpcode(ARM::t2LDRHpci);
6280 case ARM::t2LDRSBpcrel:
6281 Inst.setOpcode(ARM::t2LDRSBpci);
6283 case ARM::t2LDRSHpcrel:
6284 Inst.setOpcode(ARM::t2LDRSHpci);
6286 // Handle NEON VST complex aliases.
6287 case ARM::VST1LNdWB_register_Asm_8:
6288 case ARM::VST1LNdWB_register_Asm_16:
6289 case ARM::VST1LNdWB_register_Asm_32: {
6291 // Shuffle the operands around so the lane index operand is in the
6294 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6295 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6296 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6297 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6298 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6299 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6300 TmpInst.addOperand(Inst.getOperand(1)); // lane
6301 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6302 TmpInst.addOperand(Inst.getOperand(6));
6307 case ARM::VST2LNdWB_register_Asm_8:
6308 case ARM::VST2LNdWB_register_Asm_16:
6309 case ARM::VST2LNdWB_register_Asm_32:
6310 case ARM::VST2LNqWB_register_Asm_16:
6311 case ARM::VST2LNqWB_register_Asm_32: {
6313 // Shuffle the operands around so the lane index operand is in the
6316 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6317 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6318 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6319 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6320 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6321 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6322 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6324 TmpInst.addOperand(Inst.getOperand(1)); // lane
6325 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6326 TmpInst.addOperand(Inst.getOperand(6));
6331 case ARM::VST3LNdWB_register_Asm_8:
6332 case ARM::VST3LNdWB_register_Asm_16:
6333 case ARM::VST3LNdWB_register_Asm_32:
6334 case ARM::VST3LNqWB_register_Asm_16:
6335 case ARM::VST3LNqWB_register_Asm_32: {
6337 // Shuffle the operands around so the lane index operand is in the
6340 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6341 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6342 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6343 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6344 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6345 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6346 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6348 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6350 TmpInst.addOperand(Inst.getOperand(1)); // lane
6351 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6352 TmpInst.addOperand(Inst.getOperand(6));
6357 case ARM::VST4LNdWB_register_Asm_8:
6358 case ARM::VST4LNdWB_register_Asm_16:
6359 case ARM::VST4LNdWB_register_Asm_32:
6360 case ARM::VST4LNqWB_register_Asm_16:
6361 case ARM::VST4LNqWB_register_Asm_32: {
6363 // Shuffle the operands around so the lane index operand is in the
6366 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6367 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6368 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6369 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6370 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6371 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6372 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6374 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6376 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6378 TmpInst.addOperand(Inst.getOperand(1)); // lane
6379 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6380 TmpInst.addOperand(Inst.getOperand(6));
6385 case ARM::VST1LNdWB_fixed_Asm_8:
6386 case ARM::VST1LNdWB_fixed_Asm_16:
6387 case ARM::VST1LNdWB_fixed_Asm_32: {
6389 // Shuffle the operands around so the lane index operand is in the
6392 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6393 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6394 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6395 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6396 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6397 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6398 TmpInst.addOperand(Inst.getOperand(1)); // lane
6399 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6400 TmpInst.addOperand(Inst.getOperand(5));
6405 case ARM::VST2LNdWB_fixed_Asm_8:
6406 case ARM::VST2LNdWB_fixed_Asm_16:
6407 case ARM::VST2LNdWB_fixed_Asm_32:
6408 case ARM::VST2LNqWB_fixed_Asm_16:
6409 case ARM::VST2LNqWB_fixed_Asm_32: {
6411 // Shuffle the operands around so the lane index operand is in the
6414 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6415 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6416 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6417 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6418 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6419 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6420 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6422 TmpInst.addOperand(Inst.getOperand(1)); // lane
6423 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6424 TmpInst.addOperand(Inst.getOperand(5));
6429 case ARM::VST3LNdWB_fixed_Asm_8:
6430 case ARM::VST3LNdWB_fixed_Asm_16:
6431 case ARM::VST3LNdWB_fixed_Asm_32:
6432 case ARM::VST3LNqWB_fixed_Asm_16:
6433 case ARM::VST3LNqWB_fixed_Asm_32: {
6435 // Shuffle the operands around so the lane index operand is in the
6438 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6439 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6440 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6441 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6442 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6443 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6444 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6446 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6448 TmpInst.addOperand(Inst.getOperand(1)); // lane
6449 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6450 TmpInst.addOperand(Inst.getOperand(5));
6455 case ARM::VST4LNdWB_fixed_Asm_8:
6456 case ARM::VST4LNdWB_fixed_Asm_16:
6457 case ARM::VST4LNdWB_fixed_Asm_32:
6458 case ARM::VST4LNqWB_fixed_Asm_16:
6459 case ARM::VST4LNqWB_fixed_Asm_32: {
6461 // Shuffle the operands around so the lane index operand is in the
6464 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6465 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6466 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6467 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6468 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6469 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6470 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6472 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6474 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6476 TmpInst.addOperand(Inst.getOperand(1)); // lane
6477 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6478 TmpInst.addOperand(Inst.getOperand(5));
6483 case ARM::VST1LNdAsm_8:
6484 case ARM::VST1LNdAsm_16:
6485 case ARM::VST1LNdAsm_32: {
6487 // Shuffle the operands around so the lane index operand is in the
6490 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6491 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6492 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6493 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6494 TmpInst.addOperand(Inst.getOperand(1)); // lane
6495 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6496 TmpInst.addOperand(Inst.getOperand(5));
6501 case ARM::VST2LNdAsm_8:
6502 case ARM::VST2LNdAsm_16:
6503 case ARM::VST2LNdAsm_32:
6504 case ARM::VST2LNqAsm_16:
6505 case ARM::VST2LNqAsm_32: {
6507 // Shuffle the operands around so the lane index operand is in the
6510 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6511 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6512 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6513 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6514 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6516 TmpInst.addOperand(Inst.getOperand(1)); // lane
6517 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6518 TmpInst.addOperand(Inst.getOperand(5));
6523 case ARM::VST3LNdAsm_8:
6524 case ARM::VST3LNdAsm_16:
6525 case ARM::VST3LNdAsm_32:
6526 case ARM::VST3LNqAsm_16:
6527 case ARM::VST3LNqAsm_32: {
6529 // Shuffle the operands around so the lane index operand is in the
6532 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6533 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6534 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6535 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6536 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6538 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6540 TmpInst.addOperand(Inst.getOperand(1)); // lane
6541 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6542 TmpInst.addOperand(Inst.getOperand(5));
6547 case ARM::VST4LNdAsm_8:
6548 case ARM::VST4LNdAsm_16:
6549 case ARM::VST4LNdAsm_32:
6550 case ARM::VST4LNqAsm_16:
6551 case ARM::VST4LNqAsm_32: {
6553 // Shuffle the operands around so the lane index operand is in the
6556 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6557 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6558 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6559 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6560 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6562 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6564 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6566 TmpInst.addOperand(Inst.getOperand(1)); // lane
6567 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6568 TmpInst.addOperand(Inst.getOperand(5));
6573 // Handle NEON VLD complex aliases.
6574 case ARM::VLD1LNdWB_register_Asm_8:
6575 case ARM::VLD1LNdWB_register_Asm_16:
6576 case ARM::VLD1LNdWB_register_Asm_32: {
6578 // Shuffle the operands around so the lane index operand is in the
6581 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6582 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6583 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6584 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6585 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6586 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6587 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6588 TmpInst.addOperand(Inst.getOperand(1)); // lane
6589 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6590 TmpInst.addOperand(Inst.getOperand(6));
6595 case ARM::VLD2LNdWB_register_Asm_8:
6596 case ARM::VLD2LNdWB_register_Asm_16:
6597 case ARM::VLD2LNdWB_register_Asm_32:
6598 case ARM::VLD2LNqWB_register_Asm_16:
6599 case ARM::VLD2LNqWB_register_Asm_32: {
6601 // Shuffle the operands around so the lane index operand is in the
6604 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6605 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6606 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6608 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6609 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6610 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6611 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6612 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6613 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6615 TmpInst.addOperand(Inst.getOperand(1)); // lane
6616 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6617 TmpInst.addOperand(Inst.getOperand(6));
6622 case ARM::VLD3LNdWB_register_Asm_8:
6623 case ARM::VLD3LNdWB_register_Asm_16:
6624 case ARM::VLD3LNdWB_register_Asm_32:
6625 case ARM::VLD3LNqWB_register_Asm_16:
6626 case ARM::VLD3LNqWB_register_Asm_32: {
6628 // Shuffle the operands around so the lane index operand is in the
6631 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6632 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6633 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6635 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6637 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6638 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6639 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6640 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6641 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6642 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6644 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6646 TmpInst.addOperand(Inst.getOperand(1)); // lane
6647 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6648 TmpInst.addOperand(Inst.getOperand(6));
6653 case ARM::VLD4LNdWB_register_Asm_8:
6654 case ARM::VLD4LNdWB_register_Asm_16:
6655 case ARM::VLD4LNdWB_register_Asm_32:
6656 case ARM::VLD4LNqWB_register_Asm_16:
6657 case ARM::VLD4LNqWB_register_Asm_32: {
6659 // Shuffle the operands around so the lane index operand is in the
6662 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6663 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6664 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6666 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6668 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6670 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6671 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6672 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6673 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6674 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6675 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6677 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6679 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6681 TmpInst.addOperand(Inst.getOperand(1)); // lane
6682 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6683 TmpInst.addOperand(Inst.getOperand(6));
6688 case ARM::VLD1LNdWB_fixed_Asm_8:
6689 case ARM::VLD1LNdWB_fixed_Asm_16:
6690 case ARM::VLD1LNdWB_fixed_Asm_32: {
6692 // Shuffle the operands around so the lane index operand is in the
6695 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6696 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6697 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6698 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6699 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6700 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6701 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6702 TmpInst.addOperand(Inst.getOperand(1)); // lane
6703 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6704 TmpInst.addOperand(Inst.getOperand(5));
6709 case ARM::VLD2LNdWB_fixed_Asm_8:
6710 case ARM::VLD2LNdWB_fixed_Asm_16:
6711 case ARM::VLD2LNdWB_fixed_Asm_32:
6712 case ARM::VLD2LNqWB_fixed_Asm_16:
6713 case ARM::VLD2LNqWB_fixed_Asm_32: {
6715 // Shuffle the operands around so the lane index operand is in the
6718 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6719 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6720 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6722 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6723 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6724 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6725 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6726 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6727 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6729 TmpInst.addOperand(Inst.getOperand(1)); // lane
6730 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6731 TmpInst.addOperand(Inst.getOperand(5));
6736 case ARM::VLD3LNdWB_fixed_Asm_8:
6737 case ARM::VLD3LNdWB_fixed_Asm_16:
6738 case ARM::VLD3LNdWB_fixed_Asm_32:
6739 case ARM::VLD3LNqWB_fixed_Asm_16:
6740 case ARM::VLD3LNqWB_fixed_Asm_32: {
6742 // Shuffle the operands around so the lane index operand is in the
6745 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6746 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6747 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6749 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6751 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6752 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6753 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6754 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6755 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6756 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6758 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6760 TmpInst.addOperand(Inst.getOperand(1)); // lane
6761 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6762 TmpInst.addOperand(Inst.getOperand(5));
6767 case ARM::VLD4LNdWB_fixed_Asm_8:
6768 case ARM::VLD4LNdWB_fixed_Asm_16:
6769 case ARM::VLD4LNdWB_fixed_Asm_32:
6770 case ARM::VLD4LNqWB_fixed_Asm_16:
6771 case ARM::VLD4LNqWB_fixed_Asm_32: {
6773 // Shuffle the operands around so the lane index operand is in the
6776 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6777 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6778 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6780 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6782 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6784 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6785 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6786 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6787 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6788 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6789 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6791 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6793 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6795 TmpInst.addOperand(Inst.getOperand(1)); // lane
6796 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6797 TmpInst.addOperand(Inst.getOperand(5));
6802 case ARM::VLD1LNdAsm_8:
6803 case ARM::VLD1LNdAsm_16:
6804 case ARM::VLD1LNdAsm_32: {
6806 // Shuffle the operands around so the lane index operand is in the
6809 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6810 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6811 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6812 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6813 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6814 TmpInst.addOperand(Inst.getOperand(1)); // lane
6815 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6816 TmpInst.addOperand(Inst.getOperand(5));
6821 case ARM::VLD2LNdAsm_8:
6822 case ARM::VLD2LNdAsm_16:
6823 case ARM::VLD2LNdAsm_32:
6824 case ARM::VLD2LNqAsm_16:
6825 case ARM::VLD2LNqAsm_32: {
6827 // Shuffle the operands around so the lane index operand is in the
6830 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6831 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6832 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6834 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6835 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6836 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6837 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6839 TmpInst.addOperand(Inst.getOperand(1)); // lane
6840 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6841 TmpInst.addOperand(Inst.getOperand(5));
6846 case ARM::VLD3LNdAsm_8:
6847 case ARM::VLD3LNdAsm_16:
6848 case ARM::VLD3LNdAsm_32:
6849 case ARM::VLD3LNqAsm_16:
6850 case ARM::VLD3LNqAsm_32: {
6852 // Shuffle the operands around so the lane index operand is in the
6855 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6856 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6857 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6859 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6861 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6862 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6863 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6864 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6866 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6868 TmpInst.addOperand(Inst.getOperand(1)); // lane
6869 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6870 TmpInst.addOperand(Inst.getOperand(5));
6875 case ARM::VLD4LNdAsm_8:
6876 case ARM::VLD4LNdAsm_16:
6877 case ARM::VLD4LNdAsm_32:
6878 case ARM::VLD4LNqAsm_16:
6879 case ARM::VLD4LNqAsm_32: {
6881 // Shuffle the operands around so the lane index operand is in the
6884 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6885 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6886 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6888 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6890 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6892 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6893 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6894 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6895 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6897 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6899 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6901 TmpInst.addOperand(Inst.getOperand(1)); // lane
6902 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6903 TmpInst.addOperand(Inst.getOperand(5));
6908 // VLD3DUP single 3-element structure to all lanes instructions.
6909 case ARM::VLD3DUPdAsm_8:
6910 case ARM::VLD3DUPdAsm_16:
6911 case ARM::VLD3DUPdAsm_32:
6912 case ARM::VLD3DUPqAsm_8:
6913 case ARM::VLD3DUPqAsm_16:
6914 case ARM::VLD3DUPqAsm_32: {
6917 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6918 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6919 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6921 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6923 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6924 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6925 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6926 TmpInst.addOperand(Inst.getOperand(4));
6931 case ARM::VLD3DUPdWB_fixed_Asm_8:
6932 case ARM::VLD3DUPdWB_fixed_Asm_16:
6933 case ARM::VLD3DUPdWB_fixed_Asm_32:
6934 case ARM::VLD3DUPqWB_fixed_Asm_8:
6935 case ARM::VLD3DUPqWB_fixed_Asm_16:
6936 case ARM::VLD3DUPqWB_fixed_Asm_32: {
6939 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6940 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6941 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6943 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6945 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6946 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6947 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6948 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6949 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6950 TmpInst.addOperand(Inst.getOperand(4));
6955 case ARM::VLD3DUPdWB_register_Asm_8:
6956 case ARM::VLD3DUPdWB_register_Asm_16:
6957 case ARM::VLD3DUPdWB_register_Asm_32:
6958 case ARM::VLD3DUPqWB_register_Asm_8:
6959 case ARM::VLD3DUPqWB_register_Asm_16:
6960 case ARM::VLD3DUPqWB_register_Asm_32: {
6963 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6964 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6965 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6967 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6969 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6970 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6971 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6972 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6973 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6974 TmpInst.addOperand(Inst.getOperand(5));
6979 // VLD3 multiple 3-element structure instructions.
6980 case ARM::VLD3dAsm_8:
6981 case ARM::VLD3dAsm_16:
6982 case ARM::VLD3dAsm_32:
6983 case ARM::VLD3qAsm_8:
6984 case ARM::VLD3qAsm_16:
6985 case ARM::VLD3qAsm_32: {
6988 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6989 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6990 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6992 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6994 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6995 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6996 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6997 TmpInst.addOperand(Inst.getOperand(4));
7002 case ARM::VLD3dWB_fixed_Asm_8:
7003 case ARM::VLD3dWB_fixed_Asm_16:
7004 case ARM::VLD3dWB_fixed_Asm_32:
7005 case ARM::VLD3qWB_fixed_Asm_8:
7006 case ARM::VLD3qWB_fixed_Asm_16:
7007 case ARM::VLD3qWB_fixed_Asm_32: {
7010 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7011 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7012 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7014 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7016 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7017 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7018 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7019 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7020 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7021 TmpInst.addOperand(Inst.getOperand(4));
7026 case ARM::VLD3dWB_register_Asm_8:
7027 case ARM::VLD3dWB_register_Asm_16:
7028 case ARM::VLD3dWB_register_Asm_32:
7029 case ARM::VLD3qWB_register_Asm_8:
7030 case ARM::VLD3qWB_register_Asm_16:
7031 case ARM::VLD3qWB_register_Asm_32: {
7034 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7035 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7036 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7038 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7040 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7041 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7042 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7043 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7044 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7045 TmpInst.addOperand(Inst.getOperand(5));
7050 // VLD4DUP single 3-element structure to all lanes instructions.
7051 case ARM::VLD4DUPdAsm_8:
7052 case ARM::VLD4DUPdAsm_16:
7053 case ARM::VLD4DUPdAsm_32:
7054 case ARM::VLD4DUPqAsm_8:
7055 case ARM::VLD4DUPqAsm_16:
7056 case ARM::VLD4DUPqAsm_32: {
7059 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7060 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7061 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7063 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7065 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7067 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7068 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7069 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7070 TmpInst.addOperand(Inst.getOperand(4));
7075 case ARM::VLD4DUPdWB_fixed_Asm_8:
7076 case ARM::VLD4DUPdWB_fixed_Asm_16:
7077 case ARM::VLD4DUPdWB_fixed_Asm_32:
7078 case ARM::VLD4DUPqWB_fixed_Asm_8:
7079 case ARM::VLD4DUPqWB_fixed_Asm_16:
7080 case ARM::VLD4DUPqWB_fixed_Asm_32: {
7083 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7084 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7085 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7087 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7089 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7091 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7092 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7093 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7094 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7095 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7096 TmpInst.addOperand(Inst.getOperand(4));
7101 case ARM::VLD4DUPdWB_register_Asm_8:
7102 case ARM::VLD4DUPdWB_register_Asm_16:
7103 case ARM::VLD4DUPdWB_register_Asm_32:
7104 case ARM::VLD4DUPqWB_register_Asm_8:
7105 case ARM::VLD4DUPqWB_register_Asm_16:
7106 case ARM::VLD4DUPqWB_register_Asm_32: {
7109 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7110 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7111 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7113 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7115 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7117 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7118 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7119 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7120 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7121 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7122 TmpInst.addOperand(Inst.getOperand(5));
7127 // VLD4 multiple 4-element structure instructions.
7128 case ARM::VLD4dAsm_8:
7129 case ARM::VLD4dAsm_16:
7130 case ARM::VLD4dAsm_32:
7131 case ARM::VLD4qAsm_8:
7132 case ARM::VLD4qAsm_16:
7133 case ARM::VLD4qAsm_32: {
7136 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7137 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7138 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7140 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7142 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7144 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7145 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7146 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7147 TmpInst.addOperand(Inst.getOperand(4));
7152 case ARM::VLD4dWB_fixed_Asm_8:
7153 case ARM::VLD4dWB_fixed_Asm_16:
7154 case ARM::VLD4dWB_fixed_Asm_32:
7155 case ARM::VLD4qWB_fixed_Asm_8:
7156 case ARM::VLD4qWB_fixed_Asm_16:
7157 case ARM::VLD4qWB_fixed_Asm_32: {
7160 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7161 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7162 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7164 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7166 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7168 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7169 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7170 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7171 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7172 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7173 TmpInst.addOperand(Inst.getOperand(4));
7178 case ARM::VLD4dWB_register_Asm_8:
7179 case ARM::VLD4dWB_register_Asm_16:
7180 case ARM::VLD4dWB_register_Asm_32:
7181 case ARM::VLD4qWB_register_Asm_8:
7182 case ARM::VLD4qWB_register_Asm_16:
7183 case ARM::VLD4qWB_register_Asm_32: {
7186 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7187 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7188 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7190 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7192 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7194 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7195 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7196 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7197 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7198 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7199 TmpInst.addOperand(Inst.getOperand(5));
7204 // VST3 multiple 3-element structure instructions.
7205 case ARM::VST3dAsm_8:
7206 case ARM::VST3dAsm_16:
7207 case ARM::VST3dAsm_32:
7208 case ARM::VST3qAsm_8:
7209 case ARM::VST3qAsm_16:
7210 case ARM::VST3qAsm_32: {
7213 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7214 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7215 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7216 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7217 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7219 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7221 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7222 TmpInst.addOperand(Inst.getOperand(4));
7227 case ARM::VST3dWB_fixed_Asm_8:
7228 case ARM::VST3dWB_fixed_Asm_16:
7229 case ARM::VST3dWB_fixed_Asm_32:
7230 case ARM::VST3qWB_fixed_Asm_8:
7231 case ARM::VST3qWB_fixed_Asm_16:
7232 case ARM::VST3qWB_fixed_Asm_32: {
7235 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7236 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7237 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7238 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7239 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7240 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7241 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7243 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7245 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7246 TmpInst.addOperand(Inst.getOperand(4));
7251 case ARM::VST3dWB_register_Asm_8:
7252 case ARM::VST3dWB_register_Asm_16:
7253 case ARM::VST3dWB_register_Asm_32:
7254 case ARM::VST3qWB_register_Asm_8:
7255 case ARM::VST3qWB_register_Asm_16:
7256 case ARM::VST3qWB_register_Asm_32: {
7259 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7260 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7261 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7262 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7263 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7264 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7265 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7267 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7269 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7270 TmpInst.addOperand(Inst.getOperand(5));
7275 // VST4 multiple 3-element structure instructions.
7276 case ARM::VST4dAsm_8:
7277 case ARM::VST4dAsm_16:
7278 case ARM::VST4dAsm_32:
7279 case ARM::VST4qAsm_8:
7280 case ARM::VST4qAsm_16:
7281 case ARM::VST4qAsm_32: {
7284 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7285 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7286 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7287 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7288 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7290 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7292 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7294 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7295 TmpInst.addOperand(Inst.getOperand(4));
7300 case ARM::VST4dWB_fixed_Asm_8:
7301 case ARM::VST4dWB_fixed_Asm_16:
7302 case ARM::VST4dWB_fixed_Asm_32:
7303 case ARM::VST4qWB_fixed_Asm_8:
7304 case ARM::VST4qWB_fixed_Asm_16:
7305 case ARM::VST4qWB_fixed_Asm_32: {
7308 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7309 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7310 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7311 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7312 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7313 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7314 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7316 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7318 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7320 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7321 TmpInst.addOperand(Inst.getOperand(4));
7326 case ARM::VST4dWB_register_Asm_8:
7327 case ARM::VST4dWB_register_Asm_16:
7328 case ARM::VST4dWB_register_Asm_32:
7329 case ARM::VST4qWB_register_Asm_8:
7330 case ARM::VST4qWB_register_Asm_16:
7331 case ARM::VST4qWB_register_Asm_32: {
7334 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7335 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7336 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7337 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7338 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7339 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7340 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7342 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7344 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7346 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7347 TmpInst.addOperand(Inst.getOperand(5));
7352 // Handle encoding choice for the shift-immediate instructions.
7355 case ARM::t2ASRri: {
7356 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7357 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7358 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
7359 !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
7360 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
7362 switch (Inst.getOpcode()) {
7363 default: llvm_unreachable("unexpected opcode");
7364 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
7365 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
7366 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
7368 // The Thumb1 operands aren't in the same order. Awesome, eh?
7370 TmpInst.setOpcode(NewOpc);
7371 TmpInst.addOperand(Inst.getOperand(0));
7372 TmpInst.addOperand(Inst.getOperand(5));
7373 TmpInst.addOperand(Inst.getOperand(1));
7374 TmpInst.addOperand(Inst.getOperand(2));
7375 TmpInst.addOperand(Inst.getOperand(3));
7376 TmpInst.addOperand(Inst.getOperand(4));
7383 // Handle the Thumb2 mode MOV complex aliases.
7385 case ARM::t2MOVSsr: {
7386 // Which instruction to expand to depends on the CCOut operand and
7387 // whether we're in an IT block if the register operands are low
7389 bool isNarrow = false;
7390 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7391 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7392 isARMLowRegister(Inst.getOperand(2).getReg()) &&
7393 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7394 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
7398 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
7399 default: llvm_unreachable("unexpected opcode!");
7400 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7401 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7402 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7403 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
7405 TmpInst.setOpcode(newOpc);
7406 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7408 TmpInst.addOperand(MCOperand::CreateReg(
7409 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7410 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7411 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7412 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7413 TmpInst.addOperand(Inst.getOperand(5));
7415 TmpInst.addOperand(MCOperand::CreateReg(
7416 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7421 case ARM::t2MOVSsi: {
7422 // Which instruction to expand to depends on the CCOut operand and
7423 // whether we're in an IT block if the register operands are low
7425 bool isNarrow = false;
7426 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7427 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7428 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
7432 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
7433 default: llvm_unreachable("unexpected opcode!");
7434 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7435 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7436 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7437 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7438 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7440 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
7441 if (Amount == 32) Amount = 0;
7442 TmpInst.setOpcode(newOpc);
7443 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7445 TmpInst.addOperand(MCOperand::CreateReg(
7446 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7447 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7448 if (newOpc != ARM::t2RRX)
7449 TmpInst.addOperand(MCOperand::CreateImm(Amount));
7450 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7451 TmpInst.addOperand(Inst.getOperand(4));
7453 TmpInst.addOperand(MCOperand::CreateReg(
7454 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7458 // Handle the ARM mode MOV complex aliases.
7463 ARM_AM::ShiftOpc ShiftTy;
7464 switch(Inst.getOpcode()) {
7465 default: llvm_unreachable("unexpected opcode!");
7466 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
7467 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
7468 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
7469 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
7471 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
7473 TmpInst.setOpcode(ARM::MOVsr);
7474 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7475 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7476 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7477 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7478 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7479 TmpInst.addOperand(Inst.getOperand(4));
7480 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7488 ARM_AM::ShiftOpc ShiftTy;
7489 switch(Inst.getOpcode()) {
7490 default: llvm_unreachable("unexpected opcode!");
7491 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
7492 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
7493 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7494 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
7496 // A shift by zero is a plain MOVr, not a MOVsi.
7497 unsigned Amt = Inst.getOperand(2).getImm();
7498 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
7499 // A shift by 32 should be encoded as 0 when permitted
7500 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
7502 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
7504 TmpInst.setOpcode(Opc);
7505 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7506 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7507 if (Opc == ARM::MOVsi)
7508 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7509 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7510 TmpInst.addOperand(Inst.getOperand(4));
7511 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7516 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
7518 TmpInst.setOpcode(ARM::MOVsi);
7519 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7520 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7521 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7522 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7523 TmpInst.addOperand(Inst.getOperand(3));
7524 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7528 case ARM::t2LDMIA_UPD: {
7529 // If this is a load of a single register, then we should use
7530 // a post-indexed LDR instruction instead, per the ARM ARM.
7531 if (Inst.getNumOperands() != 5)
7534 TmpInst.setOpcode(ARM::t2LDR_POST);
7535 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7536 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7537 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7538 TmpInst.addOperand(MCOperand::CreateImm(4));
7539 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7540 TmpInst.addOperand(Inst.getOperand(3));
7544 case ARM::t2STMDB_UPD: {
7545 // If this is a store of a single register, then we should use
7546 // a pre-indexed STR instruction instead, per the ARM ARM.
7547 if (Inst.getNumOperands() != 5)
7550 TmpInst.setOpcode(ARM::t2STR_PRE);
7551 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7552 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7553 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7554 TmpInst.addOperand(MCOperand::CreateImm(-4));
7555 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7556 TmpInst.addOperand(Inst.getOperand(3));
7560 case ARM::LDMIA_UPD:
7561 // If this is a load of a single register via a 'pop', then we should use
7562 // a post-indexed LDR instruction instead, per the ARM ARM.
7563 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
7564 Inst.getNumOperands() == 5) {
7566 TmpInst.setOpcode(ARM::LDR_POST_IMM);
7567 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7568 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7569 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7570 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
7571 TmpInst.addOperand(MCOperand::CreateImm(4));
7572 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7573 TmpInst.addOperand(Inst.getOperand(3));
7578 case ARM::STMDB_UPD:
7579 // If this is a store of a single register via a 'push', then we should use
7580 // a pre-indexed STR instruction instead, per the ARM ARM.
7581 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
7582 Inst.getNumOperands() == 5) {
7584 TmpInst.setOpcode(ARM::STR_PRE_IMM);
7585 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7586 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7587 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7588 TmpInst.addOperand(MCOperand::CreateImm(-4));
7589 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7590 TmpInst.addOperand(Inst.getOperand(3));
7594 case ARM::t2ADDri12:
7595 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7596 // mnemonic was used (not "addw"), encoding T3 is preferred.
7597 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
7598 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7600 Inst.setOpcode(ARM::t2ADDri);
7601 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7603 case ARM::t2SUBri12:
7604 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7605 // mnemonic was used (not "subw"), encoding T3 is preferred.
7606 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7607 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7609 Inst.setOpcode(ARM::t2SUBri);
7610 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7613 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7614 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7615 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7616 // to encoding T1 if <Rd> is omitted."
7617 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7618 Inst.setOpcode(ARM::tADDi3);
7623 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7624 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7625 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7626 // to encoding T1 if <Rd> is omitted."
7627 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7628 Inst.setOpcode(ARM::tSUBi3);
7633 case ARM::t2SUBri: {
7634 // If the destination and first source operand are the same, and
7635 // the flags are compatible with the current IT status, use encoding T2
7636 // instead of T3. For compatibility with the system 'as'. Make sure the
7637 // wide encoding wasn't explicit.
7638 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7639 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7640 (unsigned)Inst.getOperand(2).getImm() > 255 ||
7641 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7642 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7643 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7644 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7647 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7648 ARM::tADDi8 : ARM::tSUBi8);
7649 TmpInst.addOperand(Inst.getOperand(0));
7650 TmpInst.addOperand(Inst.getOperand(5));
7651 TmpInst.addOperand(Inst.getOperand(0));
7652 TmpInst.addOperand(Inst.getOperand(2));
7653 TmpInst.addOperand(Inst.getOperand(3));
7654 TmpInst.addOperand(Inst.getOperand(4));
7658 case ARM::t2ADDrr: {
7659 // If the destination and first source operand are the same, and
7660 // there's no setting of the flags, use encoding T2 instead of T3.
7661 // Note that this is only for ADD, not SUB. This mirrors the system
7662 // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7663 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7664 Inst.getOperand(5).getReg() != 0 ||
7665 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7666 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7669 TmpInst.setOpcode(ARM::tADDhirr);
7670 TmpInst.addOperand(Inst.getOperand(0));
7671 TmpInst.addOperand(Inst.getOperand(0));
7672 TmpInst.addOperand(Inst.getOperand(2));
7673 TmpInst.addOperand(Inst.getOperand(3));
7674 TmpInst.addOperand(Inst.getOperand(4));
7678 case ARM::tADDrSP: {
7679 // If the non-SP source operand and the destination operand are not the
7680 // same, we need to use the 32-bit encoding if it's available.
7681 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7682 Inst.setOpcode(ARM::t2ADDrr);
7683 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7689 // A Thumb conditional branch outside of an IT block is a tBcc.
7690 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7691 Inst.setOpcode(ARM::tBcc);
7696 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7697 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7698 Inst.setOpcode(ARM::t2Bcc);
7703 // If the conditional is AL or we're in an IT block, we really want t2B.
7704 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7705 Inst.setOpcode(ARM::t2B);
7710 // If the conditional is AL, we really want tB.
7711 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7712 Inst.setOpcode(ARM::tB);
7717 // If the register list contains any high registers, or if the writeback
7718 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7719 // instead if we're in Thumb2. Otherwise, this should have generated
7720 // an error in validateInstruction().
7721 unsigned Rn = Inst.getOperand(0).getReg();
7722 bool hasWritebackToken =
7723 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7724 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7725 bool listContainsBase;
7726 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7727 (!listContainsBase && !hasWritebackToken) ||
7728 (listContainsBase && hasWritebackToken)) {
7729 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7730 assert (isThumbTwo());
7731 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7732 // If we're switching to the updating version, we need to insert
7733 // the writeback tied operand.
7734 if (hasWritebackToken)
7735 Inst.insert(Inst.begin(),
7736 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7741 case ARM::tSTMIA_UPD: {
7742 // If the register list contains any high registers, we need to use
7743 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7744 // should have generated an error in validateInstruction().
7745 unsigned Rn = Inst.getOperand(0).getReg();
7746 bool listContainsBase;
7747 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7748 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7749 assert (isThumbTwo());
7750 Inst.setOpcode(ARM::t2STMIA_UPD);
7756 bool listContainsBase;
7757 // If the register list contains any high registers, we need to use
7758 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7759 // should have generated an error in validateInstruction().
7760 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7762 assert (isThumbTwo());
7763 Inst.setOpcode(ARM::t2LDMIA_UPD);
7764 // Add the base register and writeback operands.
7765 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7766 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7770 bool listContainsBase;
7771 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7773 assert (isThumbTwo());
7774 Inst.setOpcode(ARM::t2STMDB_UPD);
7775 // Add the base register and writeback operands.
7776 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7777 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7781 // If we can use the 16-bit encoding and the user didn't explicitly
7782 // request the 32-bit variant, transform it here.
7783 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7784 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7785 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7786 Inst.getOperand(4).getReg() == ARM::CPSR) ||
7787 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7788 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7789 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7790 // The operands aren't in the same order for tMOVi8...
7792 TmpInst.setOpcode(ARM::tMOVi8);
7793 TmpInst.addOperand(Inst.getOperand(0));
7794 TmpInst.addOperand(Inst.getOperand(4));
7795 TmpInst.addOperand(Inst.getOperand(1));
7796 TmpInst.addOperand(Inst.getOperand(2));
7797 TmpInst.addOperand(Inst.getOperand(3));
7804 // If we can use the 16-bit encoding and the user didn't explicitly
7805 // request the 32-bit variant, transform it here.
7806 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7807 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7808 Inst.getOperand(2).getImm() == ARMCC::AL &&
7809 Inst.getOperand(4).getReg() == ARM::CPSR &&
7810 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7811 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7812 // The operands aren't the same for tMOV[S]r... (no cc_out)
7814 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7815 TmpInst.addOperand(Inst.getOperand(0));
7816 TmpInst.addOperand(Inst.getOperand(1));
7817 TmpInst.addOperand(Inst.getOperand(2));
7818 TmpInst.addOperand(Inst.getOperand(3));
7828 // If we can use the 16-bit encoding and the user didn't explicitly
7829 // request the 32-bit variant, transform it here.
7830 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7831 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7832 Inst.getOperand(2).getImm() == 0 &&
7833 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7834 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7836 switch (Inst.getOpcode()) {
7837 default: llvm_unreachable("Illegal opcode!");
7838 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7839 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7840 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7841 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7843 // The operands aren't the same for thumb1 (no rotate operand).
7845 TmpInst.setOpcode(NewOpc);
7846 TmpInst.addOperand(Inst.getOperand(0));
7847 TmpInst.addOperand(Inst.getOperand(1));
7848 TmpInst.addOperand(Inst.getOperand(3));
7849 TmpInst.addOperand(Inst.getOperand(4));
7856 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7857 // rrx shifts and asr/lsr of #32 is encoded as 0
7858 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7860 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7861 // Shifting by zero is accepted as a vanilla 'MOVr'
7863 TmpInst.setOpcode(ARM::MOVr);
7864 TmpInst.addOperand(Inst.getOperand(0));
7865 TmpInst.addOperand(Inst.getOperand(1));
7866 TmpInst.addOperand(Inst.getOperand(3));
7867 TmpInst.addOperand(Inst.getOperand(4));
7868 TmpInst.addOperand(Inst.getOperand(5));
7881 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7882 if (SOpc == ARM_AM::rrx) return false;
7883 switch (Inst.getOpcode()) {
7884 default: llvm_unreachable("unexpected opcode!");
7885 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7886 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7887 case ARM::EORrsi: newOpc = ARM::EORrr; break;
7888 case ARM::BICrsi: newOpc = ARM::BICrr; break;
7889 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7890 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7892 // If the shift is by zero, use the non-shifted instruction definition.
7893 // The exception is for right shifts, where 0 == 32
7894 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7895 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7897 TmpInst.setOpcode(newOpc);
7898 TmpInst.addOperand(Inst.getOperand(0));
7899 TmpInst.addOperand(Inst.getOperand(1));
7900 TmpInst.addOperand(Inst.getOperand(2));
7901 TmpInst.addOperand(Inst.getOperand(4));
7902 TmpInst.addOperand(Inst.getOperand(5));
7903 TmpInst.addOperand(Inst.getOperand(6));
7911 // The mask bits for all but the first condition are represented as
7912 // the low bit of the condition code value implies 't'. We currently
7913 // always have 1 implies 't', so XOR toggle the bits if the low bit
7914 // of the condition code is zero.
7915 MCOperand &MO = Inst.getOperand(1);
7916 unsigned Mask = MO.getImm();
7917 unsigned OrigMask = Mask;
7918 unsigned TZ = countTrailingZeros(Mask);
7919 if ((Inst.getOperand(0).getImm() & 1) == 0) {
7920 assert(Mask && TZ <= 3 && "illegal IT mask value!");
7921 Mask ^= (0xE << TZ) & 0xF;
7925 // Set up the IT block state according to the IT instruction we just
7927 assert(!inITBlock() && "nested IT blocks?!");
7928 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7929 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7930 ITState.CurPosition = 0;
7931 ITState.FirstCond = true;
7941 // Assemblers should use the narrow encodings of these instructions when permissible.
7942 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7943 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7944 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7945 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7946 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7947 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7948 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7950 switch (Inst.getOpcode()) {
7951 default: llvm_unreachable("unexpected opcode");
7952 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7953 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7954 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7955 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7956 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7957 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7960 TmpInst.setOpcode(NewOpc);
7961 TmpInst.addOperand(Inst.getOperand(0));
7962 TmpInst.addOperand(Inst.getOperand(5));
7963 TmpInst.addOperand(Inst.getOperand(1));
7964 TmpInst.addOperand(Inst.getOperand(2));
7965 TmpInst.addOperand(Inst.getOperand(3));
7966 TmpInst.addOperand(Inst.getOperand(4));
7977 // Assemblers should use the narrow encodings of these instructions when permissible.
7978 // These instructions are special in that they are commutable, so shorter encodings
7979 // are available more often.
7980 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7981 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7982 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7983 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7984 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7985 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7986 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7987 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7989 switch (Inst.getOpcode()) {
7990 default: llvm_unreachable("unexpected opcode");
7991 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7992 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7993 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7994 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7997 TmpInst.setOpcode(NewOpc);
7998 TmpInst.addOperand(Inst.getOperand(0));
7999 TmpInst.addOperand(Inst.getOperand(5));
8000 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
8001 TmpInst.addOperand(Inst.getOperand(1));
8002 TmpInst.addOperand(Inst.getOperand(2));
8004 TmpInst.addOperand(Inst.getOperand(2));
8005 TmpInst.addOperand(Inst.getOperand(1));
8007 TmpInst.addOperand(Inst.getOperand(3));
8008 TmpInst.addOperand(Inst.getOperand(4));
8018 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
8019 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
8020 // suffix depending on whether they're in an IT block or not.
8021 unsigned Opc = Inst.getOpcode();
8022 const MCInstrDesc &MCID = MII.get(Opc);
8023 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
8024 assert(MCID.hasOptionalDef() &&
8025 "optionally flag setting instruction missing optional def operand");
8026 assert(MCID.NumOperands == Inst.getNumOperands() &&
8027 "operand count mismatch!");
8028 // Find the optional-def operand (cc_out).
8031 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
8034 // If we're parsing Thumb1, reject it completely.
8035 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
8036 return Match_MnemonicFail;
8037 // If we're parsing Thumb2, which form is legal depends on whether we're
8039 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
8041 return Match_RequiresITBlock;
8042 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
8044 return Match_RequiresNotITBlock;
8046 // Some high-register supporting Thumb1 encodings only allow both registers
8047 // to be from r0-r7 when in Thumb2.
8048 else if (Opc == ARM::tADDhirr && isThumbOne() &&
8049 isARMLowRegister(Inst.getOperand(1).getReg()) &&
8050 isARMLowRegister(Inst.getOperand(2).getReg()))
8051 return Match_RequiresThumb2;
8052 // Others only require ARMv6 or later.
8053 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
8054 isARMLowRegister(Inst.getOperand(0).getReg()) &&
8055 isARMLowRegister(Inst.getOperand(1).getReg()))
8056 return Match_RequiresV6;
8057 return Match_Success;
8061 template <> inline bool IsCPSRDead<MCInst>(MCInst *Instr) {
8062 return true; // In an assembly source, no need to second-guess
8066 static const char *getSubtargetFeatureName(unsigned Val);
8068 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
8069 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
8070 MCStreamer &Out, unsigned &ErrorInfo,
8071 bool MatchingInlineAsm) {
8073 unsigned MatchResult;
8075 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
8077 switch (MatchResult) {
8080 // Context sensitive operand constraints aren't handled by the matcher,
8081 // so check them here.
8082 if (validateInstruction(Inst, Operands)) {
8083 // Still progress the IT block, otherwise one wrong condition causes
8084 // nasty cascading errors.
8085 forwardITPosition();
8089 { // processInstruction() updates inITBlock state, we need to save it away
8090 bool wasInITBlock = inITBlock();
8092 // Some instructions need post-processing to, for example, tweak which
8093 // encoding is selected. Loop on it while changes happen so the
8094 // individual transformations can chain off each other. E.g.,
8095 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
8096 while (processInstruction(Inst, Operands))
8099 // Only after the instruction is fully processed, we can validate it
8100 if (wasInITBlock && hasV8Ops() && isThumb() &&
8101 !isV8EligibleForIT(&Inst)) {
8102 Warning(IDLoc, "deprecated instruction in IT block");
8106 // Only move forward at the very end so that everything in validate
8107 // and process gets a consistent answer about whether we're in an IT
8109 forwardITPosition();
8111 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
8112 // doesn't actually encode.
8113 if (Inst.getOpcode() == ARM::ITasm)
8117 Out.EmitInstruction(Inst, STI);
8119 case Match_MissingFeature: {
8120 assert(ErrorInfo && "Unknown missing feature!");
8121 // Special case the error message for the very common case where only
8122 // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
8123 std::string Msg = "instruction requires:";
8125 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
8126 if (ErrorInfo & Mask) {
8128 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
8132 return Error(IDLoc, Msg);
8134 case Match_InvalidOperand: {
8135 SMLoc ErrorLoc = IDLoc;
8136 if (ErrorInfo != ~0U) {
8137 if (ErrorInfo >= Operands.size())
8138 return Error(IDLoc, "too few operands for instruction");
8140 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
8141 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8144 return Error(ErrorLoc, "invalid operand for instruction");
8146 case Match_MnemonicFail:
8147 return Error(IDLoc, "invalid instruction",
8148 ((ARMOperand*)Operands[0])->getLocRange());
8149 case Match_RequiresNotITBlock:
8150 return Error(IDLoc, "flag setting instruction only valid outside IT block");
8151 case Match_RequiresITBlock:
8152 return Error(IDLoc, "instruction only valid inside IT block");
8153 case Match_RequiresV6:
8154 return Error(IDLoc, "instruction variant requires ARMv6 or later");
8155 case Match_RequiresThumb2:
8156 return Error(IDLoc, "instruction variant requires Thumb2");
8157 case Match_ImmRange0_15: {
8158 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
8159 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8160 return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
8162 case Match_ImmRange0_239: {
8163 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
8164 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8165 return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
8167 case Match_AlignedMemoryRequiresNone:
8168 case Match_DupAlignedMemoryRequiresNone:
8169 case Match_AlignedMemoryRequires16:
8170 case Match_DupAlignedMemoryRequires16:
8171 case Match_AlignedMemoryRequires32:
8172 case Match_DupAlignedMemoryRequires32:
8173 case Match_AlignedMemoryRequires64:
8174 case Match_DupAlignedMemoryRequires64:
8175 case Match_AlignedMemoryRequires64or128:
8176 case Match_DupAlignedMemoryRequires64or128:
8177 case Match_AlignedMemoryRequires64or128or256:
8179 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getAlignmentLoc();
8180 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8181 switch (MatchResult) {
8183 llvm_unreachable("Missing Match_Aligned type");
8184 case Match_AlignedMemoryRequiresNone:
8185 case Match_DupAlignedMemoryRequiresNone:
8186 return Error(ErrorLoc, "alignment must be omitted");
8187 case Match_AlignedMemoryRequires16:
8188 case Match_DupAlignedMemoryRequires16:
8189 return Error(ErrorLoc, "alignment must be 16 or omitted");
8190 case Match_AlignedMemoryRequires32:
8191 case Match_DupAlignedMemoryRequires32:
8192 return Error(ErrorLoc, "alignment must be 32 or omitted");
8193 case Match_AlignedMemoryRequires64:
8194 case Match_DupAlignedMemoryRequires64:
8195 return Error(ErrorLoc, "alignment must be 64 or omitted");
8196 case Match_AlignedMemoryRequires64or128:
8197 case Match_DupAlignedMemoryRequires64or128:
8198 return Error(ErrorLoc, "alignment must be 64, 128 or omitted");
8199 case Match_AlignedMemoryRequires64or128or256:
8200 return Error(ErrorLoc, "alignment must be 64, 128, 256 or omitted");
8205 llvm_unreachable("Implement any new match types added!");
8208 /// parseDirective parses the arm specific directives
8209 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
8210 const MCObjectFileInfo::Environment Format =
8211 getContext().getObjectFileInfo()->getObjectFileType();
8212 bool IsMachO = Format == MCObjectFileInfo::IsMachO;
8214 StringRef IDVal = DirectiveID.getIdentifier();
8215 if (IDVal == ".word")
8216 return parseLiteralValues(4, DirectiveID.getLoc());
8217 else if (IDVal == ".short" || IDVal == ".hword")
8218 return parseLiteralValues(2, DirectiveID.getLoc());
8219 else if (IDVal == ".thumb")
8220 return parseDirectiveThumb(DirectiveID.getLoc());
8221 else if (IDVal == ".arm")
8222 return parseDirectiveARM(DirectiveID.getLoc());
8223 else if (IDVal == ".thumb_func")
8224 return parseDirectiveThumbFunc(DirectiveID.getLoc());
8225 else if (IDVal == ".code")
8226 return parseDirectiveCode(DirectiveID.getLoc());
8227 else if (IDVal == ".syntax")
8228 return parseDirectiveSyntax(DirectiveID.getLoc());
8229 else if (IDVal == ".unreq")
8230 return parseDirectiveUnreq(DirectiveID.getLoc());
8231 else if (IDVal == ".fnend")
8232 return parseDirectiveFnEnd(DirectiveID.getLoc());
8233 else if (IDVal == ".cantunwind")
8234 return parseDirectiveCantUnwind(DirectiveID.getLoc());
8235 else if (IDVal == ".personality")
8236 return parseDirectivePersonality(DirectiveID.getLoc());
8237 else if (IDVal == ".handlerdata")
8238 return parseDirectiveHandlerData(DirectiveID.getLoc());
8239 else if (IDVal == ".setfp")
8240 return parseDirectiveSetFP(DirectiveID.getLoc());
8241 else if (IDVal == ".pad")
8242 return parseDirectivePad(DirectiveID.getLoc());
8243 else if (IDVal == ".save")
8244 return parseDirectiveRegSave(DirectiveID.getLoc(), false);
8245 else if (IDVal == ".vsave")
8246 return parseDirectiveRegSave(DirectiveID.getLoc(), true);
8247 else if (IDVal == ".ltorg" || IDVal == ".pool")
8248 return parseDirectiveLtorg(DirectiveID.getLoc());
8249 else if (IDVal == ".even")
8250 return parseDirectiveEven(DirectiveID.getLoc());
8251 else if (IDVal == ".personalityindex")
8252 return parseDirectivePersonalityIndex(DirectiveID.getLoc());
8253 else if (IDVal == ".unwind_raw")
8254 return parseDirectiveUnwindRaw(DirectiveID.getLoc());
8255 else if (IDVal == ".movsp")
8256 return parseDirectiveMovSP(DirectiveID.getLoc());
8257 else if (IDVal == ".arch_extension")
8258 return parseDirectiveArchExtension(DirectiveID.getLoc());
8259 else if (IDVal == ".align")
8260 return parseDirectiveAlign(DirectiveID.getLoc());
8261 else if (IDVal == ".thumb_set")
8262 return parseDirectiveThumbSet(DirectiveID.getLoc());
8265 if (IDVal == ".arch")
8266 return parseDirectiveArch(DirectiveID.getLoc());
8267 else if (IDVal == ".cpu")
8268 return parseDirectiveCPU(DirectiveID.getLoc());
8269 else if (IDVal == ".eabi_attribute")
8270 return parseDirectiveEabiAttr(DirectiveID.getLoc());
8271 else if (IDVal == ".fpu")
8272 return parseDirectiveFPU(DirectiveID.getLoc());
8273 else if (IDVal == ".fnstart")
8274 return parseDirectiveFnStart(DirectiveID.getLoc());
8275 else if (IDVal == ".inst")
8276 return parseDirectiveInst(DirectiveID.getLoc());
8277 else if (IDVal == ".inst.n")
8278 return parseDirectiveInst(DirectiveID.getLoc(), 'n');
8279 else if (IDVal == ".inst.w")
8280 return parseDirectiveInst(DirectiveID.getLoc(), 'w');
8281 else if (IDVal == ".object_arch")
8282 return parseDirectiveObjectArch(DirectiveID.getLoc());
8283 else if (IDVal == ".tlsdescseq")
8284 return parseDirectiveTLSDescSeq(DirectiveID.getLoc());
8290 /// parseLiteralValues
8291 /// ::= .hword expression [, expression]*
8292 /// ::= .short expression [, expression]*
8293 /// ::= .word expression [, expression]*
8294 bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
8295 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8297 const MCExpr *Value;
8298 if (getParser().parseExpression(Value)) {
8299 Parser.eatToEndOfStatement();
8303 getParser().getStreamer().EmitValue(Value, Size);
8305 if (getLexer().is(AsmToken::EndOfStatement))
8308 // FIXME: Improve diagnostic.
8309 if (getLexer().isNot(AsmToken::Comma)) {
8310 Error(L, "unexpected token in directive");
8321 /// parseDirectiveThumb
8323 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
8324 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8325 Error(L, "unexpected token in directive");
8331 Error(L, "target does not support Thumb mode");
8338 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8342 /// parseDirectiveARM
8344 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
8345 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8346 Error(L, "unexpected token in directive");
8352 Error(L, "target does not support ARM mode");
8359 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8363 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
8364 if (NextSymbolIsThumb) {
8365 getParser().getStreamer().EmitThumbFunc(Symbol);
8366 NextSymbolIsThumb = false;
8373 const MCObjectFileInfo::Environment Format =
8374 getContext().getObjectFileInfo()->getObjectFileType();
8376 case MCObjectFileInfo::IsCOFF: {
8377 const MCSymbolData &SD =
8378 getParser().getStreamer().getOrCreateSymbolData(Symbol);
8379 char Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
8380 if (SD.getFlags() & (Type << COFF::SF_TypeShift))
8381 getParser().getStreamer().EmitThumbFunc(Symbol);
8384 case MCObjectFileInfo::IsELF: {
8385 const MCSymbolData &SD =
8386 getParser().getStreamer().getOrCreateSymbolData(Symbol);
8387 if (MCELF::GetType(SD) & (ELF::STT_FUNC << ELF_STT_Shift))
8388 getParser().getStreamer().EmitThumbFunc(Symbol);
8391 case MCObjectFileInfo::IsMachO:
8396 /// parseDirectiveThumbFunc
8397 /// ::= .thumbfunc symbol_name
8398 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
8399 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
8400 bool isMachO = MAI->hasSubsectionsViaSymbols();
8402 // Darwin asm has (optionally) function name after .thumb_func direction
8405 const AsmToken &Tok = Parser.getTok();
8406 if (Tok.isNot(AsmToken::EndOfStatement)) {
8407 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) {
8408 Error(L, "unexpected token in .thumb_func directive");
8413 getParser().getContext().GetOrCreateSymbol(Tok.getIdentifier());
8414 getParser().getStreamer().EmitThumbFunc(Func);
8415 Parser.Lex(); // Consume the identifier token.
8420 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8421 Error(L, "unexpected token in directive");
8425 NextSymbolIsThumb = true;
8429 /// parseDirectiveSyntax
8430 /// ::= .syntax unified | divided
8431 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
8432 const AsmToken &Tok = Parser.getTok();
8433 if (Tok.isNot(AsmToken::Identifier)) {
8434 Error(L, "unexpected token in .syntax directive");
8438 StringRef Mode = Tok.getString();
8439 if (Mode == "unified" || Mode == "UNIFIED") {
8441 } else if (Mode == "divided" || Mode == "DIVIDED") {
8442 Error(L, "'.syntax divided' arm asssembly not supported");
8445 Error(L, "unrecognized syntax mode in .syntax directive");
8449 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8450 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8455 // TODO tell the MC streamer the mode
8456 // getParser().getStreamer().Emit???();
8460 /// parseDirectiveCode
8461 /// ::= .code 16 | 32
8462 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
8463 const AsmToken &Tok = Parser.getTok();
8464 if (Tok.isNot(AsmToken::Integer)) {
8465 Error(L, "unexpected token in .code directive");
8468 int64_t Val = Parser.getTok().getIntVal();
8469 if (Val != 16 && Val != 32) {
8470 Error(L, "invalid operand to .code directive");
8475 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8476 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8483 Error(L, "target does not support Thumb mode");
8489 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8492 Error(L, "target does not support ARM mode");
8498 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8504 /// parseDirectiveReq
8505 /// ::= name .req registername
8506 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
8507 Parser.Lex(); // Eat the '.req' token.
8509 SMLoc SRegLoc, ERegLoc;
8510 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
8511 Parser.eatToEndOfStatement();
8512 Error(SRegLoc, "register name expected");
8516 // Shouldn't be anything else.
8517 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
8518 Parser.eatToEndOfStatement();
8519 Error(Parser.getTok().getLoc(), "unexpected input in .req directive.");
8523 Parser.Lex(); // Consume the EndOfStatement
8525 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg) {
8526 Error(SRegLoc, "redefinition of '" + Name + "' does not match original.");
8533 /// parseDirectiveUneq
8534 /// ::= .unreq registername
8535 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
8536 if (Parser.getTok().isNot(AsmToken::Identifier)) {
8537 Parser.eatToEndOfStatement();
8538 Error(L, "unexpected input in .unreq directive.");
8541 RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
8542 Parser.Lex(); // Eat the identifier.
8546 /// parseDirectiveArch
8548 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
8549 StringRef Arch = getParser().parseStringToEndOfStatement().trim();
8551 unsigned ID = StringSwitch<unsigned>(Arch)
8552 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
8553 .Case(NAME, ARM::ID)
8554 #define ARM_ARCH_ALIAS(NAME, ID) \
8555 .Case(NAME, ARM::ID)
8556 #include "MCTargetDesc/ARMArchName.def"
8557 .Default(ARM::INVALID_ARCH);
8559 if (ID == ARM::INVALID_ARCH) {
8560 Error(L, "Unknown arch name");
8564 getTargetStreamer().emitArch(ID);
8568 /// parseDirectiveEabiAttr
8569 /// ::= .eabi_attribute int, int [, "str"]
8570 /// ::= .eabi_attribute Tag_name, int [, "str"]
8571 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
8574 TagLoc = Parser.getTok().getLoc();
8575 if (Parser.getTok().is(AsmToken::Identifier)) {
8576 StringRef Name = Parser.getTok().getIdentifier();
8577 Tag = ARMBuildAttrs::AttrTypeFromString(Name);
8579 Error(TagLoc, "attribute name not recognised: " + Name);
8580 Parser.eatToEndOfStatement();
8585 const MCExpr *AttrExpr;
8587 TagLoc = Parser.getTok().getLoc();
8588 if (Parser.parseExpression(AttrExpr)) {
8589 Parser.eatToEndOfStatement();
8593 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
8595 Error(TagLoc, "expected numeric constant");
8596 Parser.eatToEndOfStatement();
8600 Tag = CE->getValue();
8603 if (Parser.getTok().isNot(AsmToken::Comma)) {
8604 Error(Parser.getTok().getLoc(), "comma expected");
8605 Parser.eatToEndOfStatement();
8608 Parser.Lex(); // skip comma
8610 StringRef StringValue = "";
8611 bool IsStringValue = false;
8613 int64_t IntegerValue = 0;
8614 bool IsIntegerValue = false;
8616 if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
8617 IsStringValue = true;
8618 else if (Tag == ARMBuildAttrs::compatibility) {
8619 IsStringValue = true;
8620 IsIntegerValue = true;
8621 } else if (Tag < 32 || Tag % 2 == 0)
8622 IsIntegerValue = true;
8623 else if (Tag % 2 == 1)
8624 IsStringValue = true;
8626 llvm_unreachable("invalid tag type");
8628 if (IsIntegerValue) {
8629 const MCExpr *ValueExpr;
8630 SMLoc ValueExprLoc = Parser.getTok().getLoc();
8631 if (Parser.parseExpression(ValueExpr)) {
8632 Parser.eatToEndOfStatement();
8636 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
8638 Error(ValueExprLoc, "expected numeric constant");
8639 Parser.eatToEndOfStatement();
8643 IntegerValue = CE->getValue();
8646 if (Tag == ARMBuildAttrs::compatibility) {
8647 if (Parser.getTok().isNot(AsmToken::Comma))
8648 IsStringValue = false;
8653 if (IsStringValue) {
8654 if (Parser.getTok().isNot(AsmToken::String)) {
8655 Error(Parser.getTok().getLoc(), "bad string constant");
8656 Parser.eatToEndOfStatement();
8660 StringValue = Parser.getTok().getStringContents();
8664 if (IsIntegerValue && IsStringValue) {
8665 assert(Tag == ARMBuildAttrs::compatibility);
8666 getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
8667 } else if (IsIntegerValue)
8668 getTargetStreamer().emitAttribute(Tag, IntegerValue);
8669 else if (IsStringValue)
8670 getTargetStreamer().emitTextAttribute(Tag, StringValue);
8674 /// parseDirectiveCPU
8676 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
8677 StringRef CPU = getParser().parseStringToEndOfStatement().trim();
8678 getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
8682 /// parseDirectiveFPU
8684 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
8685 StringRef FPU = getParser().parseStringToEndOfStatement().trim();
8687 unsigned ID = StringSwitch<unsigned>(FPU)
8688 #define ARM_FPU_NAME(NAME, ID) .Case(NAME, ARM::ID)
8689 #include "ARMFPUName.def"
8690 .Default(ARM::INVALID_FPU);
8692 if (ID == ARM::INVALID_FPU) {
8693 Error(L, "Unknown FPU name");
8697 getTargetStreamer().emitFPU(ID);
8701 /// parseDirectiveFnStart
8703 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
8704 if (UC.hasFnStart()) {
8705 Error(L, ".fnstart starts before the end of previous one");
8706 UC.emitFnStartLocNotes();
8710 // Reset the unwind directives parser state
8713 getTargetStreamer().emitFnStart();
8715 UC.recordFnStart(L);
8719 /// parseDirectiveFnEnd
8721 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
8722 // Check the ordering of unwind directives
8723 if (!UC.hasFnStart()) {
8724 Error(L, ".fnstart must precede .fnend directive");
8728 // Reset the unwind directives parser state
8729 getTargetStreamer().emitFnEnd();
8735 /// parseDirectiveCantUnwind
8737 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
8738 UC.recordCantUnwind(L);
8740 // Check the ordering of unwind directives
8741 if (!UC.hasFnStart()) {
8742 Error(L, ".fnstart must precede .cantunwind directive");
8745 if (UC.hasHandlerData()) {
8746 Error(L, ".cantunwind can't be used with .handlerdata directive");
8747 UC.emitHandlerDataLocNotes();
8750 if (UC.hasPersonality()) {
8751 Error(L, ".cantunwind can't be used with .personality directive");
8752 UC.emitPersonalityLocNotes();
8756 getTargetStreamer().emitCantUnwind();
8760 /// parseDirectivePersonality
8761 /// ::= .personality name
8762 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
8763 bool HasExistingPersonality = UC.hasPersonality();
8765 UC.recordPersonality(L);
8767 // Check the ordering of unwind directives
8768 if (!UC.hasFnStart()) {
8769 Error(L, ".fnstart must precede .personality directive");
8772 if (UC.cantUnwind()) {
8773 Error(L, ".personality can't be used with .cantunwind directive");
8774 UC.emitCantUnwindLocNotes();
8777 if (UC.hasHandlerData()) {
8778 Error(L, ".personality must precede .handlerdata directive");
8779 UC.emitHandlerDataLocNotes();
8782 if (HasExistingPersonality) {
8783 Parser.eatToEndOfStatement();
8784 Error(L, "multiple personality directives");
8785 UC.emitPersonalityLocNotes();
8789 // Parse the name of the personality routine
8790 if (Parser.getTok().isNot(AsmToken::Identifier)) {
8791 Parser.eatToEndOfStatement();
8792 Error(L, "unexpected input in .personality directive.");
8795 StringRef Name(Parser.getTok().getIdentifier());
8798 MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
8799 getTargetStreamer().emitPersonality(PR);
8803 /// parseDirectiveHandlerData
8804 /// ::= .handlerdata
8805 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
8806 UC.recordHandlerData(L);
8808 // Check the ordering of unwind directives
8809 if (!UC.hasFnStart()) {
8810 Error(L, ".fnstart must precede .personality directive");
8813 if (UC.cantUnwind()) {
8814 Error(L, ".handlerdata can't be used with .cantunwind directive");
8815 UC.emitCantUnwindLocNotes();
8819 getTargetStreamer().emitHandlerData();
8823 /// parseDirectiveSetFP
8824 /// ::= .setfp fpreg, spreg [, offset]
8825 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
8826 // Check the ordering of unwind directives
8827 if (!UC.hasFnStart()) {
8828 Error(L, ".fnstart must precede .setfp directive");
8831 if (UC.hasHandlerData()) {
8832 Error(L, ".setfp must precede .handlerdata directive");
8837 SMLoc FPRegLoc = Parser.getTok().getLoc();
8838 int FPReg = tryParseRegister();
8840 Error(FPRegLoc, "frame pointer register expected");
8845 if (Parser.getTok().isNot(AsmToken::Comma)) {
8846 Error(Parser.getTok().getLoc(), "comma expected");
8849 Parser.Lex(); // skip comma
8852 SMLoc SPRegLoc = Parser.getTok().getLoc();
8853 int SPReg = tryParseRegister();
8855 Error(SPRegLoc, "stack pointer register expected");
8859 if (SPReg != ARM::SP && SPReg != UC.getFPReg()) {
8860 Error(SPRegLoc, "register should be either $sp or the latest fp register");
8864 // Update the frame pointer register
8865 UC.saveFPReg(FPReg);
8869 if (Parser.getTok().is(AsmToken::Comma)) {
8870 Parser.Lex(); // skip comma
8872 if (Parser.getTok().isNot(AsmToken::Hash) &&
8873 Parser.getTok().isNot(AsmToken::Dollar)) {
8874 Error(Parser.getTok().getLoc(), "'#' expected");
8877 Parser.Lex(); // skip hash token.
8879 const MCExpr *OffsetExpr;
8880 SMLoc ExLoc = Parser.getTok().getLoc();
8882 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
8883 Error(ExLoc, "malformed setfp offset");
8886 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8888 Error(ExLoc, "setfp offset must be an immediate");
8892 Offset = CE->getValue();
8895 getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
8896 static_cast<unsigned>(SPReg), Offset);
8902 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
8903 // Check the ordering of unwind directives
8904 if (!UC.hasFnStart()) {
8905 Error(L, ".fnstart must precede .pad directive");
8908 if (UC.hasHandlerData()) {
8909 Error(L, ".pad must precede .handlerdata directive");
8914 if (Parser.getTok().isNot(AsmToken::Hash) &&
8915 Parser.getTok().isNot(AsmToken::Dollar)) {
8916 Error(Parser.getTok().getLoc(), "'#' expected");
8919 Parser.Lex(); // skip hash token.
8921 const MCExpr *OffsetExpr;
8922 SMLoc ExLoc = Parser.getTok().getLoc();
8924 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
8925 Error(ExLoc, "malformed pad offset");
8928 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8930 Error(ExLoc, "pad offset must be an immediate");
8934 getTargetStreamer().emitPad(CE->getValue());
8938 /// parseDirectiveRegSave
8939 /// ::= .save { registers }
8940 /// ::= .vsave { registers }
8941 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
8942 // Check the ordering of unwind directives
8943 if (!UC.hasFnStart()) {
8944 Error(L, ".fnstart must precede .save or .vsave directives");
8947 if (UC.hasHandlerData()) {
8948 Error(L, ".save or .vsave must precede .handlerdata directive");
8952 // RAII object to make sure parsed operands are deleted.
8953 struct CleanupObject {
8954 SmallVector<MCParsedAsmOperand *, 1> Operands;
8956 for (unsigned I = 0, E = Operands.size(); I != E; ++I)
8961 // Parse the register list
8962 if (parseRegisterList(CO.Operands))
8964 ARMOperand *Op = (ARMOperand*)CO.Operands[0];
8965 if (!IsVector && !Op->isRegList()) {
8966 Error(L, ".save expects GPR registers");
8969 if (IsVector && !Op->isDPRRegList()) {
8970 Error(L, ".vsave expects DPR registers");
8974 getTargetStreamer().emitRegSave(Op->getRegList(), IsVector);
8978 /// parseDirectiveInst
8979 /// ::= .inst opcode [, ...]
8980 /// ::= .inst.n opcode [, ...]
8981 /// ::= .inst.w opcode [, ...]
8982 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
8994 Parser.eatToEndOfStatement();
8995 Error(Loc, "cannot determine Thumb instruction size, "
8996 "use inst.n/inst.w instead");
9001 Parser.eatToEndOfStatement();
9002 Error(Loc, "width suffixes are invalid in ARM mode");
9008 if (getLexer().is(AsmToken::EndOfStatement)) {
9009 Parser.eatToEndOfStatement();
9010 Error(Loc, "expected expression following directive");
9017 if (getParser().parseExpression(Expr)) {
9018 Error(Loc, "expected expression");
9022 const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
9024 Error(Loc, "expected constant expression");
9030 if (Value->getValue() > 0xffff) {
9031 Error(Loc, "inst.n operand is too big, use inst.w instead");
9036 if (Value->getValue() > 0xffffffff) {
9038 StringRef(Suffix ? "inst.w" : "inst") + " operand is too big");
9043 llvm_unreachable("only supported widths are 2 and 4");
9046 getTargetStreamer().emitInst(Value->getValue(), Suffix);
9048 if (getLexer().is(AsmToken::EndOfStatement))
9051 if (getLexer().isNot(AsmToken::Comma)) {
9052 Error(Loc, "unexpected token in directive");
9063 /// parseDirectiveLtorg
9064 /// ::= .ltorg | .pool
9065 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
9066 getTargetStreamer().emitCurrentConstantPool();
9070 bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
9071 const MCSection *Section = getStreamer().getCurrentSection().first;
9073 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9074 TokError("unexpected token in directive");
9079 getStreamer().InitSections();
9080 Section = getStreamer().getCurrentSection().first;
9083 assert(Section && "must have section to emit alignment");
9084 if (Section->UseCodeAlign())
9085 getStreamer().EmitCodeAlignment(2);
9087 getStreamer().EmitValueToAlignment(2);
9092 /// parseDirectivePersonalityIndex
9093 /// ::= .personalityindex index
9094 bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) {
9095 bool HasExistingPersonality = UC.hasPersonality();
9097 UC.recordPersonalityIndex(L);
9099 if (!UC.hasFnStart()) {
9100 Parser.eatToEndOfStatement();
9101 Error(L, ".fnstart must precede .personalityindex directive");
9104 if (UC.cantUnwind()) {
9105 Parser.eatToEndOfStatement();
9106 Error(L, ".personalityindex cannot be used with .cantunwind");
9107 UC.emitCantUnwindLocNotes();
9110 if (UC.hasHandlerData()) {
9111 Parser.eatToEndOfStatement();
9112 Error(L, ".personalityindex must precede .handlerdata directive");
9113 UC.emitHandlerDataLocNotes();
9116 if (HasExistingPersonality) {
9117 Parser.eatToEndOfStatement();
9118 Error(L, "multiple personality directives");
9119 UC.emitPersonalityLocNotes();
9123 const MCExpr *IndexExpression;
9124 SMLoc IndexLoc = Parser.getTok().getLoc();
9125 if (Parser.parseExpression(IndexExpression)) {
9126 Parser.eatToEndOfStatement();
9130 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
9132 Parser.eatToEndOfStatement();
9133 Error(IndexLoc, "index must be a constant number");
9136 if (CE->getValue() < 0 ||
9137 CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) {
9138 Parser.eatToEndOfStatement();
9139 Error(IndexLoc, "personality routine index should be in range [0-3]");
9143 getTargetStreamer().emitPersonalityIndex(CE->getValue());
9147 /// parseDirectiveUnwindRaw
9148 /// ::= .unwind_raw offset, opcode [, opcode...]
9149 bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
9150 if (!UC.hasFnStart()) {
9151 Parser.eatToEndOfStatement();
9152 Error(L, ".fnstart must precede .unwind_raw directives");
9156 int64_t StackOffset;
9158 const MCExpr *OffsetExpr;
9159 SMLoc OffsetLoc = getLexer().getLoc();
9160 if (getLexer().is(AsmToken::EndOfStatement) ||
9161 getParser().parseExpression(OffsetExpr)) {
9162 Error(OffsetLoc, "expected expression");
9163 Parser.eatToEndOfStatement();
9167 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9169 Error(OffsetLoc, "offset must be a constant");
9170 Parser.eatToEndOfStatement();
9174 StackOffset = CE->getValue();
9176 if (getLexer().isNot(AsmToken::Comma)) {
9177 Error(getLexer().getLoc(), "expected comma");
9178 Parser.eatToEndOfStatement();
9183 SmallVector<uint8_t, 16> Opcodes;
9187 SMLoc OpcodeLoc = getLexer().getLoc();
9188 if (getLexer().is(AsmToken::EndOfStatement) || Parser.parseExpression(OE)) {
9189 Error(OpcodeLoc, "expected opcode expression");
9190 Parser.eatToEndOfStatement();
9194 const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
9196 Error(OpcodeLoc, "opcode value must be a constant");
9197 Parser.eatToEndOfStatement();
9201 const int64_t Opcode = OC->getValue();
9202 if (Opcode & ~0xff) {
9203 Error(OpcodeLoc, "invalid opcode");
9204 Parser.eatToEndOfStatement();
9208 Opcodes.push_back(uint8_t(Opcode));
9210 if (getLexer().is(AsmToken::EndOfStatement))
9213 if (getLexer().isNot(AsmToken::Comma)) {
9214 Error(getLexer().getLoc(), "unexpected token in directive");
9215 Parser.eatToEndOfStatement();
9222 getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes);
9228 /// parseDirectiveTLSDescSeq
9229 /// ::= .tlsdescseq tls-variable
9230 bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) {
9231 if (getLexer().isNot(AsmToken::Identifier)) {
9232 TokError("expected variable after '.tlsdescseq' directive");
9233 Parser.eatToEndOfStatement();
9237 const MCSymbolRefExpr *SRE =
9238 MCSymbolRefExpr::Create(Parser.getTok().getIdentifier(),
9239 MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext());
9242 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9243 Error(Parser.getTok().getLoc(), "unexpected token");
9244 Parser.eatToEndOfStatement();
9248 getTargetStreamer().AnnotateTLSDescriptorSequence(SRE);
9252 /// parseDirectiveMovSP
9253 /// ::= .movsp reg [, #offset]
9254 bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) {
9255 if (!UC.hasFnStart()) {
9256 Parser.eatToEndOfStatement();
9257 Error(L, ".fnstart must precede .movsp directives");
9260 if (UC.getFPReg() != ARM::SP) {
9261 Parser.eatToEndOfStatement();
9262 Error(L, "unexpected .movsp directive");
9266 SMLoc SPRegLoc = Parser.getTok().getLoc();
9267 int SPReg = tryParseRegister();
9269 Parser.eatToEndOfStatement();
9270 Error(SPRegLoc, "register expected");
9274 if (SPReg == ARM::SP || SPReg == ARM::PC) {
9275 Parser.eatToEndOfStatement();
9276 Error(SPRegLoc, "sp and pc are not permitted in .movsp directive");
9281 if (Parser.getTok().is(AsmToken::Comma)) {
9284 if (Parser.getTok().isNot(AsmToken::Hash)) {
9285 Error(Parser.getTok().getLoc(), "expected #constant");
9286 Parser.eatToEndOfStatement();
9291 const MCExpr *OffsetExpr;
9292 SMLoc OffsetLoc = Parser.getTok().getLoc();
9293 if (Parser.parseExpression(OffsetExpr)) {
9294 Parser.eatToEndOfStatement();
9295 Error(OffsetLoc, "malformed offset expression");
9299 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9301 Parser.eatToEndOfStatement();
9302 Error(OffsetLoc, "offset must be an immediate constant");
9306 Offset = CE->getValue();
9309 getTargetStreamer().emitMovSP(SPReg, Offset);
9310 UC.saveFPReg(SPReg);
9315 /// parseDirectiveObjectArch
9316 /// ::= .object_arch name
9317 bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
9318 if (getLexer().isNot(AsmToken::Identifier)) {
9319 Error(getLexer().getLoc(), "unexpected token");
9320 Parser.eatToEndOfStatement();
9324 StringRef Arch = Parser.getTok().getString();
9325 SMLoc ArchLoc = Parser.getTok().getLoc();
9328 unsigned ID = StringSwitch<unsigned>(Arch)
9329 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
9330 .Case(NAME, ARM::ID)
9331 #define ARM_ARCH_ALIAS(NAME, ID) \
9332 .Case(NAME, ARM::ID)
9333 #include "MCTargetDesc/ARMArchName.def"
9334 #undef ARM_ARCH_NAME
9335 #undef ARM_ARCH_ALIAS
9336 .Default(ARM::INVALID_ARCH);
9338 if (ID == ARM::INVALID_ARCH) {
9339 Error(ArchLoc, "unknown architecture '" + Arch + "'");
9340 Parser.eatToEndOfStatement();
9344 getTargetStreamer().emitObjectArch(ID);
9346 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9347 Error(getLexer().getLoc(), "unexpected token");
9348 Parser.eatToEndOfStatement();
9354 /// parseDirectiveAlign
9356 bool ARMAsmParser::parseDirectiveAlign(SMLoc L) {
9357 // NOTE: if this is not the end of the statement, fall back to the target
9358 // agnostic handling for this directive which will correctly handle this.
9359 if (getLexer().isNot(AsmToken::EndOfStatement))
9362 // '.align' is target specifically handled to mean 2**2 byte alignment.
9363 if (getStreamer().getCurrentSection().first->UseCodeAlign())
9364 getStreamer().EmitCodeAlignment(4, 0);
9366 getStreamer().EmitValueToAlignment(4, 0, 1, 0);
9371 /// parseDirectiveThumbSet
9372 /// ::= .thumb_set name, value
9373 bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) {
9375 if (Parser.parseIdentifier(Name)) {
9376 TokError("expected identifier after '.thumb_set'");
9377 Parser.eatToEndOfStatement();
9381 if (getLexer().isNot(AsmToken::Comma)) {
9382 TokError("expected comma after name '" + Name + "'");
9383 Parser.eatToEndOfStatement();
9388 const MCExpr *Value;
9389 if (Parser.parseExpression(Value)) {
9390 TokError("missing expression");
9391 Parser.eatToEndOfStatement();
9395 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9396 TokError("unexpected token");
9397 Parser.eatToEndOfStatement();
9402 MCSymbol *Alias = getContext().GetOrCreateSymbol(Name);
9403 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Value)) {
9404 MCSymbol *Sym = getContext().LookupSymbol(SRE->getSymbol().getName());
9405 if (!Sym->isDefined()) {
9406 getStreamer().EmitSymbolAttribute(Sym, MCSA_Global);
9407 getStreamer().EmitAssignment(Alias, Value);
9411 const MCObjectFileInfo::Environment Format =
9412 getContext().getObjectFileInfo()->getObjectFileType();
9414 case MCObjectFileInfo::IsCOFF: {
9415 char Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
9416 getStreamer().EmitCOFFSymbolType(Type);
9417 // .set values are always local in COFF
9418 getStreamer().EmitSymbolAttribute(Alias, MCSA_Local);
9421 case MCObjectFileInfo::IsELF:
9422 getStreamer().EmitSymbolAttribute(Alias, MCSA_ELF_TypeFunction);
9424 case MCObjectFileInfo::IsMachO:
9429 // FIXME: set the function as being a thumb function via the assembler
9430 getStreamer().EmitThumbFunc(Alias);
9431 getStreamer().EmitAssignment(Alias, Value);
9436 /// Force static initialization.
9437 extern "C" void LLVMInitializeARMAsmParser() {
9438 RegisterMCAsmParser<ARMAsmParser> X(TheARMLETarget);
9439 RegisterMCAsmParser<ARMAsmParser> Y(TheARMBETarget);
9440 RegisterMCAsmParser<ARMAsmParser> A(TheThumbLETarget);
9441 RegisterMCAsmParser<ARMAsmParser> B(TheThumbBETarget);
9444 #define GET_REGISTER_MATCHER
9445 #define GET_SUBTARGET_FEATURE_NAME
9446 #define GET_MATCHER_IMPLEMENTATION
9447 #include "ARMGenAsmMatcher.inc"
9449 static const struct ExtMapEntry {
9450 const char *Extension;
9451 const unsigned ArchCheck;
9452 const uint64_t Features;
9454 { "crc", Feature_HasV8, ARM::FeatureCRC },
9455 { "crypto", Feature_HasV8,
9456 ARM::FeatureCrypto | ARM::FeatureNEON | ARM::FeatureFPARMv8 },
9457 { "fp", Feature_HasV8, ARM::FeatureFPARMv8 },
9458 { "idiv", Feature_HasV7 | Feature_IsNotMClass,
9459 ARM::FeatureHWDiv | ARM::FeatureHWDivARM },
9460 // FIXME: iWMMXT not supported
9461 { "iwmmxt", Feature_None, 0 },
9462 // FIXME: iWMMXT2 not supported
9463 { "iwmmxt2", Feature_None, 0 },
9464 // FIXME: Maverick not supported
9465 { "maverick", Feature_None, 0 },
9466 { "mp", Feature_HasV7 | Feature_IsNotMClass, ARM::FeatureMP },
9467 // FIXME: ARMv6-m OS Extensions feature not checked
9468 { "os", Feature_None, 0 },
9469 // FIXME: Also available in ARMv6-K
9470 { "sec", Feature_HasV7, ARM::FeatureTrustZone },
9471 { "simd", Feature_HasV8, ARM::FeatureNEON | ARM::FeatureFPARMv8 },
9472 // FIXME: Only available in A-class, isel not predicated
9473 { "virt", Feature_HasV7, ARM::FeatureVirtualization },
9474 // FIXME: xscale not supported
9475 { "xscale", Feature_None, 0 },
9478 /// parseDirectiveArchExtension
9479 /// ::= .arch_extension [no]feature
9480 bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
9481 if (getLexer().isNot(AsmToken::Identifier)) {
9482 Error(getLexer().getLoc(), "unexpected token");
9483 Parser.eatToEndOfStatement();
9487 StringRef Extension = Parser.getTok().getString();
9488 SMLoc ExtLoc = Parser.getTok().getLoc();
9491 bool EnableFeature = true;
9492 if (Extension.startswith_lower("no")) {
9493 EnableFeature = false;
9494 Extension = Extension.substr(2);
9497 for (unsigned EI = 0, EE = array_lengthof(Extensions); EI != EE; ++EI) {
9498 if (Extensions[EI].Extension != Extension)
9501 unsigned FB = getAvailableFeatures();
9502 if ((FB & Extensions[EI].ArchCheck) != Extensions[EI].ArchCheck) {
9503 Error(ExtLoc, "architectural extension '" + Extension + "' is not "
9504 "allowed for the current base architecture");
9508 if (!Extensions[EI].Features)
9509 report_fatal_error("unsupported architectural extension: " + Extension);
9512 FB |= ComputeAvailableFeatures(Extensions[EI].Features);
9514 FB &= ~ComputeAvailableFeatures(Extensions[EI].Features);
9516 setAvailableFeatures(FB);
9520 Error(ExtLoc, "unknown architectural extension: " + Extension);
9521 Parser.eatToEndOfStatement();
9525 // Define this matcher function after the auto-generated include so we
9526 // have the match class enum definitions.
9527 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
9529 ARMOperand *Op = static_cast<ARMOperand*>(AsmOp);
9530 // If the kind is a token for a literal immediate, check if our asm
9531 // operand matches. This is for InstAliases which have a fixed-value
9532 // immediate in the syntax.
9537 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()))
9538 if (CE->getValue() == 0)
9539 return Match_Success;
9543 const MCExpr *SOExpr = Op->getImm();
9545 if (!SOExpr->EvaluateAsAbsolute(Value))
9546 return Match_Success;
9547 assert((Value >= INT32_MIN && Value <= INT32_MAX) &&
9548 "expression value must be representiable in 32 bits");
9553 MRI->getRegClass(ARM::GPRRegClassID).contains(Op->getReg()))
9554 return Match_Success;
9557 return Match_InvalidOperand;