1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMSubtarget.h"
12 #include "llvm/MC/MCParser/MCAsmLexer.h"
13 #include "llvm/MC/MCParser/MCAsmParser.h"
14 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
15 #include "llvm/MC/MCStreamer.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/Target/TargetRegistry.h"
19 #include "llvm/Target/TargetAsmParser.h"
20 #include "llvm/Support/SourceMgr.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/ADT/OwningPtr.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/StringSwitch.h"
25 #include "llvm/ADT/Twine.h"
28 // The shift types for register controlled shifts in arm memory addressing
40 class ARMAsmParser : public TargetAsmParser {
45 MCAsmParser &getParser() const { return Parser; }
47 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
49 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
51 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
53 ARMOperand *MaybeParseRegister(bool ParseWriteBack);
55 ARMOperand *ParseRegisterList();
57 bool ParseMemory(OwningPtr<ARMOperand> &Op);
59 bool ParseMemoryOffsetReg(bool &Negative,
60 bool &OffsetRegShifted,
61 enum ShiftType &ShiftType,
62 const MCExpr *&ShiftAmount,
63 const MCExpr *&Offset,
68 bool ParseShift(enum ShiftType &St, const MCExpr *&ShiftAmount, SMLoc &E);
70 bool ParseOperand(OwningPtr<ARMOperand> &Op);
72 bool ParseDirectiveWord(unsigned Size, SMLoc L);
74 bool ParseDirectiveThumb(SMLoc L);
76 bool ParseDirectiveThumbFunc(SMLoc L);
78 bool ParseDirectiveCode(SMLoc L);
80 bool ParseDirectiveSyntax(SMLoc L);
82 bool MatchAndEmitInstruction(SMLoc IDLoc,
83 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
87 if (MatchInstructionImpl(Operands, Inst, ErrorInfo) == Match_Success) {
88 Out.EmitInstruction(Inst);
92 // FIXME: We should give nicer diagnostics about the exact failure.
93 Error(IDLoc, "unrecognized instruction");
97 /// @name Auto-generated Match Functions
100 #define GET_ASSEMBLER_HEADER
101 #include "ARMGenAsmMatcher.inc"
107 ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
108 : TargetAsmParser(T), Parser(_Parser), TM(_TM) {}
110 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
111 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
113 virtual bool ParseDirective(AsmToken DirectiveID);
115 } // end anonymous namespace
119 /// ARMOperand - Instances of this class represent a parsed ARM machine
121 struct ARMOperand : public MCParsedAsmOperand {
131 SMLoc StartLoc, EndLoc;
135 ARMCC::CondCodes Val;
152 // This is for all forms of ARM address expressions
155 unsigned OffsetRegNum; // used when OffsetIsReg is true
156 const MCExpr *Offset; // used when OffsetIsReg is false
157 const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
158 enum ShiftType ShiftType; // used when OffsetRegShifted is true
160 OffsetRegShifted : 1, // only used when OffsetIsReg is true
164 Negative : 1, // only used when OffsetIsReg is true
170 //ARMOperand(KindTy K, SMLoc S, SMLoc E)
171 // : Kind(K), StartLoc(S), EndLoc(E) {}
173 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
175 StartLoc = o.StartLoc;
196 /// getStartLoc - Get the location of the first token of this operand.
197 SMLoc getStartLoc() const { return StartLoc; }
198 /// getEndLoc - Get the location of the last token of this operand.
199 SMLoc getEndLoc() const { return EndLoc; }
201 ARMCC::CondCodes getCondCode() const {
202 assert(Kind == CondCode && "Invalid access!");
206 StringRef getToken() const {
207 assert(Kind == Token && "Invalid access!");
208 return StringRef(Tok.Data, Tok.Length);
211 unsigned getReg() const {
212 assert(Kind == Register && "Invalid access!");
216 const MCExpr *getImm() const {
217 assert(Kind == Immediate && "Invalid access!");
221 bool isCondCode() const { return Kind == CondCode; }
223 bool isImm() const { return Kind == Immediate; }
225 bool isReg() const { return Kind == Register; }
227 bool isToken() const {return Kind == Token; }
229 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
230 // Add as immediates when possible.
231 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
232 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
234 Inst.addOperand(MCOperand::CreateExpr(Expr));
237 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
238 assert(N == 2 && "Invalid number of operands!");
239 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
240 // FIXME: What belongs here?
241 Inst.addOperand(MCOperand::CreateReg(0));
244 void addRegOperands(MCInst &Inst, unsigned N) const {
245 assert(N == 1 && "Invalid number of operands!");
246 Inst.addOperand(MCOperand::CreateReg(getReg()));
249 void addImmOperands(MCInst &Inst, unsigned N) const {
250 assert(N == 1 && "Invalid number of operands!");
251 addExpr(Inst, getImm());
254 virtual void dump(raw_ostream &OS) const;
256 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
257 ARMOperand *Op = new ARMOperand(CondCode);
264 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
265 ARMOperand *Op = new ARMOperand(Token);
266 Op->Tok.Data = Str.data();
267 Op->Tok.Length = Str.size();
273 static ARMOperand *CreateReg(unsigned RegNum, bool Writeback, SMLoc S,
275 ARMOperand *Op = new ARMOperand(Register);
276 Op->Reg.RegNum = RegNum;
277 Op->Reg.Writeback = Writeback;
283 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
284 ARMOperand *Op = new ARMOperand(Immediate);
291 static ARMOperand *CreateMem(unsigned BaseRegNum, bool OffsetIsReg,
292 const MCExpr *Offset, unsigned OffsetRegNum,
293 bool OffsetRegShifted, enum ShiftType ShiftType,
294 const MCExpr *ShiftAmount, bool Preindexed,
295 bool Postindexed, bool Negative, bool Writeback,
297 ARMOperand *Op = new ARMOperand(Memory);
298 Op->Mem.BaseRegNum = BaseRegNum;
299 Op->Mem.OffsetIsReg = OffsetIsReg;
300 Op->Mem.Offset = Offset;
301 Op->Mem.OffsetRegNum = OffsetRegNum;
302 Op->Mem.OffsetRegShifted = OffsetRegShifted;
303 Op->Mem.ShiftType = ShiftType;
304 Op->Mem.ShiftAmount = ShiftAmount;
305 Op->Mem.Preindexed = Preindexed;
306 Op->Mem.Postindexed = Postindexed;
307 Op->Mem.Negative = Negative;
308 Op->Mem.Writeback = Writeback;
316 ARMOperand(KindTy K) : Kind(K) {}
319 } // end anonymous namespace.
321 void ARMOperand::dump(raw_ostream &OS) const {
324 OS << ARMCondCodeToString(getCondCode());
333 OS << "<register " << getReg() << ">";
336 OS << "'" << getToken() << "'";
341 /// @name Auto-generated Match Functions
344 static unsigned MatchRegisterName(StringRef Name);
348 /// Try to parse a register name. The token must be an Identifier when called,
349 /// and if it is a register name the token is eaten and a Reg operand is created
350 /// and returned. Otherwise return null.
352 /// TODO this is likely to change to allow different register types and or to
353 /// parse for a specific register type.
354 ARMOperand *ARMAsmParser::MaybeParseRegister(bool ParseWriteBack) {
356 const AsmToken &Tok = Parser.getTok();
357 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
359 // FIXME: Validate register for the current architecture; we have to do
360 // validation later, so maybe there is no need for this here.
363 RegNum = MatchRegisterName(Tok.getString());
369 Parser.Lex(); // Eat identifier token.
371 E = Parser.getTok().getLoc();
373 bool Writeback = false;
374 if (ParseWriteBack) {
375 const AsmToken &ExclaimTok = Parser.getTok();
376 if (ExclaimTok.is(AsmToken::Exclaim)) {
377 E = ExclaimTok.getLoc();
379 Parser.Lex(); // Eat exclaim token
383 return ARMOperand::CreateReg(RegNum, Writeback, S, E);
386 /// Parse a register list, return it if successful else return null. The first
387 /// token must be a '{' when called.
388 ARMOperand *ARMAsmParser::ParseRegisterList() {
390 assert(Parser.getTok().is(AsmToken::LCurly) &&
391 "Token is not an Left Curly Brace");
392 S = Parser.getTok().getLoc();
393 Parser.Lex(); // Eat left curly brace token.
395 const AsmToken &RegTok = Parser.getTok();
396 SMLoc RegLoc = RegTok.getLoc();
397 if (RegTok.isNot(AsmToken::Identifier)) {
398 Error(RegLoc, "register expected");
401 int RegNum = MatchRegisterName(RegTok.getString());
403 Error(RegLoc, "register expected");
407 Parser.Lex(); // Eat identifier token.
408 unsigned RegList = 1 << RegNum;
410 int HighRegNum = RegNum;
411 // TODO ranges like "{Rn-Rm}"
412 while (Parser.getTok().is(AsmToken::Comma)) {
413 Parser.Lex(); // Eat comma token.
415 const AsmToken &RegTok = Parser.getTok();
416 SMLoc RegLoc = RegTok.getLoc();
417 if (RegTok.isNot(AsmToken::Identifier)) {
418 Error(RegLoc, "register expected");
421 int RegNum = MatchRegisterName(RegTok.getString());
423 Error(RegLoc, "register expected");
427 if (RegList & (1 << RegNum))
428 Warning(RegLoc, "register duplicated in register list");
429 else if (RegNum <= HighRegNum)
430 Warning(RegLoc, "register not in ascending order in register list");
431 RegList |= 1 << RegNum;
434 Parser.Lex(); // Eat identifier token.
436 const AsmToken &RCurlyTok = Parser.getTok();
437 if (RCurlyTok.isNot(AsmToken::RCurly)) {
438 Error(RCurlyTok.getLoc(), "'}' expected");
441 E = RCurlyTok.getLoc();
442 Parser.Lex(); // Eat left curly brace token.
444 // FIXME: Need to return an operand!
445 Error(E, "FIXME: register list parsing not implemented");
449 /// Parse an arm memory expression, return false if successful else return true
450 /// or an error. The first token must be a '[' when called.
451 /// TODO Only preindexing and postindexing addressing are started, unindexed
452 /// with option, etc are still to do.
453 bool ARMAsmParser::ParseMemory(OwningPtr<ARMOperand> &Op) {
455 assert(Parser.getTok().is(AsmToken::LBrac) &&
456 "Token is not an Left Bracket");
457 S = Parser.getTok().getLoc();
458 Parser.Lex(); // Eat left bracket token.
460 const AsmToken &BaseRegTok = Parser.getTok();
461 if (BaseRegTok.isNot(AsmToken::Identifier))
462 return Error(BaseRegTok.getLoc(), "register expected");
463 Op.reset(MaybeParseRegister(false));
465 return Error(BaseRegTok.getLoc(), "register expected");
466 int BaseRegNum = Op->getReg();
468 bool Preindexed = false;
469 bool Postindexed = false;
470 bool OffsetIsReg = false;
471 bool Negative = false;
472 bool Writeback = false;
474 // First look for preindexed address forms, that is after the "[Rn" we now
475 // have to see if the next token is a comma.
476 const AsmToken &Tok = Parser.getTok();
477 if (Tok.is(AsmToken::Comma)) {
479 Parser.Lex(); // Eat comma token.
481 bool OffsetRegShifted;
482 enum ShiftType ShiftType;
483 const MCExpr *ShiftAmount;
484 const MCExpr *Offset;
485 if(ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
486 Offset, OffsetIsReg, OffsetRegNum, E))
488 const AsmToken &RBracTok = Parser.getTok();
489 if (RBracTok.isNot(AsmToken::RBrac))
490 return Error(RBracTok.getLoc(), "']' expected");
491 E = RBracTok.getLoc();
492 Parser.Lex(); // Eat right bracket token.
494 const AsmToken &ExclaimTok = Parser.getTok();
495 if (ExclaimTok.is(AsmToken::Exclaim)) {
496 E = ExclaimTok.getLoc();
498 Parser.Lex(); // Eat exclaim token
501 ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
502 OffsetRegShifted, ShiftType, ShiftAmount,
503 Preindexed, Postindexed, Negative, Writeback, S,E));
506 // The "[Rn" we have so far was not followed by a comma.
507 else if (Tok.is(AsmToken::RBrac)) {
508 // This is a post indexing addressing forms, that is a ']' follows after
513 Parser.Lex(); // Eat right bracket token.
515 int OffsetRegNum = 0;
516 bool OffsetRegShifted = false;
517 enum ShiftType ShiftType;
518 const MCExpr *ShiftAmount;
519 const MCExpr *Offset;
521 const AsmToken &NextTok = Parser.getTok();
522 if (NextTok.isNot(AsmToken::EndOfStatement)) {
523 if (NextTok.isNot(AsmToken::Comma))
524 return Error(NextTok.getLoc(), "',' expected");
525 Parser.Lex(); // Eat comma token.
526 if(ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
527 ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
533 ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
534 OffsetRegShifted, ShiftType, ShiftAmount,
535 Preindexed, Postindexed, Negative, Writeback, S,E));
542 /// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
543 /// we will parse the following (were +/- means that a plus or minus is
548 /// we return false on success or an error otherwise.
549 bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
550 bool &OffsetRegShifted,
551 enum ShiftType &ShiftType,
552 const MCExpr *&ShiftAmount,
553 const MCExpr *&Offset,
557 OwningPtr<ARMOperand> Op;
559 OffsetRegShifted = false;
562 const AsmToken &NextTok = Parser.getTok();
563 E = NextTok.getLoc();
564 if (NextTok.is(AsmToken::Plus))
565 Parser.Lex(); // Eat plus token.
566 else if (NextTok.is(AsmToken::Minus)) {
568 Parser.Lex(); // Eat minus token
570 // See if there is a register following the "[Rn," or "[Rn]," we have so far.
571 const AsmToken &OffsetRegTok = Parser.getTok();
572 if (OffsetRegTok.is(AsmToken::Identifier)) {
573 Op.reset(MaybeParseRegister(false));
574 OffsetIsReg = Op.get() != 0;
577 OffsetRegNum = Op->getReg();
580 // If we parsed a register as the offset then their can be a shift after that
581 if (OffsetRegNum != -1) {
582 // Look for a comma then a shift
583 const AsmToken &Tok = Parser.getTok();
584 if (Tok.is(AsmToken::Comma)) {
585 Parser.Lex(); // Eat comma token.
587 const AsmToken &Tok = Parser.getTok();
588 if (ParseShift(ShiftType, ShiftAmount, E))
589 return Error(Tok.getLoc(), "shift expected");
590 OffsetRegShifted = true;
593 else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
594 // Look for #offset following the "[Rn," or "[Rn],"
595 const AsmToken &HashTok = Parser.getTok();
596 if (HashTok.isNot(AsmToken::Hash))
597 return Error(HashTok.getLoc(), "'#' expected");
599 Parser.Lex(); // Eat hash token.
601 if (getParser().ParseExpression(Offset))
603 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
608 /// ParseShift as one of these two:
609 /// ( lsl | lsr | asr | ror ) , # shift_amount
611 /// and returns true if it parses a shift otherwise it returns false.
612 bool ARMAsmParser::ParseShift(ShiftType &St, const MCExpr *&ShiftAmount,
614 const AsmToken &Tok = Parser.getTok();
615 if (Tok.isNot(AsmToken::Identifier))
617 StringRef ShiftName = Tok.getString();
618 if (ShiftName == "lsl" || ShiftName == "LSL")
620 else if (ShiftName == "lsr" || ShiftName == "LSR")
622 else if (ShiftName == "asr" || ShiftName == "ASR")
624 else if (ShiftName == "ror" || ShiftName == "ROR")
626 else if (ShiftName == "rrx" || ShiftName == "RRX")
630 Parser.Lex(); // Eat shift type token.
636 // Otherwise, there must be a '#' and a shift amount.
637 const AsmToken &HashTok = Parser.getTok();
638 if (HashTok.isNot(AsmToken::Hash))
639 return Error(HashTok.getLoc(), "'#' expected");
640 Parser.Lex(); // Eat hash token.
642 if (getParser().ParseExpression(ShiftAmount))
648 /// Parse a arm instruction operand. For now this parses the operand regardless
650 bool ARMAsmParser::ParseOperand(OwningPtr<ARMOperand> &Op) {
653 switch (getLexer().getKind()) {
654 case AsmToken::Identifier:
655 Op.reset(MaybeParseRegister(true));
658 // This was not a register so parse other operands that start with an
659 // identifier (like labels) as expressions and create them as immediates.
661 S = Parser.getTok().getLoc();
662 if (getParser().ParseExpression(IdVal))
664 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
665 Op.reset(ARMOperand::CreateImm(IdVal, S, E));
667 case AsmToken::LBrac:
668 return ParseMemory(Op);
669 case AsmToken::LCurly:
670 Op.reset(ParseRegisterList());
671 return Op.get() == 0;
674 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
675 S = Parser.getTok().getLoc();
677 const MCExpr *ImmVal;
678 if (getParser().ParseExpression(ImmVal))
680 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
681 Op.reset(ARMOperand::CreateImm(ImmVal, S, E));
684 return Error(Parser.getTok().getLoc(), "unexpected token in operand");
688 /// Parse an arm instruction mnemonic followed by its operands.
689 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
690 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
691 // Create the leading tokens for the mnemonic, split by '.' characters.
692 size_t Start = 0, Next = Name.find('.');
693 StringRef Head = Name.slice(Start, Next);
695 // Determine the predicate, if any.
697 // FIXME: We need a way to check whether a prefix supports predication,
698 // otherwise we will end up with an ambiguity for instructions that happen to
699 // end with a predicate name.
700 unsigned CC = StringSwitch<unsigned>(Head.substr(Head.size()-2))
701 .Case("eq", ARMCC::EQ)
702 .Case("ne", ARMCC::NE)
703 .Case("hs", ARMCC::HS)
704 .Case("lo", ARMCC::LO)
705 .Case("mi", ARMCC::MI)
706 .Case("pl", ARMCC::PL)
707 .Case("vs", ARMCC::VS)
708 .Case("vc", ARMCC::VC)
709 .Case("hi", ARMCC::HI)
710 .Case("ls", ARMCC::LS)
711 .Case("ge", ARMCC::GE)
712 .Case("lt", ARMCC::LT)
713 .Case("gt", ARMCC::GT)
714 .Case("le", ARMCC::LE)
715 .Case("al", ARMCC::AL)
719 Head = Head.slice(0, Head.size() - 2);
723 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
724 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), NameLoc));
726 // Add the remaining tokens in the mnemonic.
727 while (Next != StringRef::npos) {
729 Next = Name.find('.', Start + 1);
730 Head = Name.slice(Start, Next);
732 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
735 // Read the remaining operands.
736 if (getLexer().isNot(AsmToken::EndOfStatement)) {
737 // Read the first operand.
738 OwningPtr<ARMOperand> Op;
739 if (ParseOperand(Op)) {
740 Parser.EatToEndOfStatement();
743 Operands.push_back(Op.take());
745 while (getLexer().is(AsmToken::Comma)) {
746 Parser.Lex(); // Eat the comma.
748 // Parse and remember the operand.
749 if (ParseOperand(Op)) {
750 Parser.EatToEndOfStatement();
753 Operands.push_back(Op.take());
757 if (getLexer().isNot(AsmToken::EndOfStatement)) {
758 Parser.EatToEndOfStatement();
759 return TokError("unexpected token in argument list");
761 Parser.Lex(); // Consume the EndOfStatement
765 /// ParseDirective parses the arm specific directives
766 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
767 StringRef IDVal = DirectiveID.getIdentifier();
768 if (IDVal == ".word")
769 return ParseDirectiveWord(4, DirectiveID.getLoc());
770 else if (IDVal == ".thumb")
771 return ParseDirectiveThumb(DirectiveID.getLoc());
772 else if (IDVal == ".thumb_func")
773 return ParseDirectiveThumbFunc(DirectiveID.getLoc());
774 else if (IDVal == ".code")
775 return ParseDirectiveCode(DirectiveID.getLoc());
776 else if (IDVal == ".syntax")
777 return ParseDirectiveSyntax(DirectiveID.getLoc());
781 /// ParseDirectiveWord
782 /// ::= .word [ expression (, expression)* ]
783 bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
784 if (getLexer().isNot(AsmToken::EndOfStatement)) {
787 if (getParser().ParseExpression(Value))
790 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
792 if (getLexer().is(AsmToken::EndOfStatement))
795 // FIXME: Improve diagnostic.
796 if (getLexer().isNot(AsmToken::Comma))
797 return Error(L, "unexpected token in directive");
806 /// ParseDirectiveThumb
808 bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
809 if (getLexer().isNot(AsmToken::EndOfStatement))
810 return Error(L, "unexpected token in directive");
813 // TODO: set thumb mode
814 // TODO: tell the MC streamer the mode
815 // getParser().getStreamer().Emit???();
819 /// ParseDirectiveThumbFunc
820 /// ::= .thumbfunc symbol_name
821 bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
822 const AsmToken &Tok = Parser.getTok();
823 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
824 return Error(L, "unexpected token in .syntax directive");
825 Parser.Lex(); // Consume the identifier token.
827 if (getLexer().isNot(AsmToken::EndOfStatement))
828 return Error(L, "unexpected token in directive");
831 // TODO: mark symbol as a thumb symbol
832 // getParser().getStreamer().Emit???();
836 /// ParseDirectiveSyntax
837 /// ::= .syntax unified | divided
838 bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
839 const AsmToken &Tok = Parser.getTok();
840 if (Tok.isNot(AsmToken::Identifier))
841 return Error(L, "unexpected token in .syntax directive");
842 StringRef Mode = Tok.getString();
843 if (Mode == "unified" || Mode == "UNIFIED")
845 else if (Mode == "divided" || Mode == "DIVIDED")
848 return Error(L, "unrecognized syntax mode in .syntax directive");
850 if (getLexer().isNot(AsmToken::EndOfStatement))
851 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
854 // TODO tell the MC streamer the mode
855 // getParser().getStreamer().Emit???();
859 /// ParseDirectiveCode
860 /// ::= .code 16 | 32
861 bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
862 const AsmToken &Tok = Parser.getTok();
863 if (Tok.isNot(AsmToken::Integer))
864 return Error(L, "unexpected token in .code directive");
865 int64_t Val = Parser.getTok().getIntVal();
871 return Error(L, "invalid operand to .code directive");
873 if (getLexer().isNot(AsmToken::EndOfStatement))
874 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
877 // TODO tell the MC streamer the mode
878 // getParser().getStreamer().Emit???();
882 extern "C" void LLVMInitializeARMAsmLexer();
884 /// Force static initialization.
885 extern "C" void LLVMInitializeARMAsmParser() {
886 RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
887 RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
888 LLVMInitializeARMAsmLexer();
891 #define GET_REGISTER_MATCHER
892 #define GET_MATCHER_IMPLEMENTATION
893 #include "ARMGenAsmMatcher.inc"