1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMSubtarget.h"
12 #include "llvm/MC/MCParser/MCAsmLexer.h"
13 #include "llvm/MC/MCParser/MCAsmParser.h"
14 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
15 #include "llvm/MC/MCStreamer.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/Target/TargetRegistry.h"
19 #include "llvm/Target/TargetAsmParser.h"
20 #include "llvm/Support/SourceMgr.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/StringSwitch.h"
24 #include "llvm/ADT/Twine.h"
27 // The shift types for register controlled shifts in arm memory addressing
39 class ARMAsmParser : public TargetAsmParser {
44 MCAsmParser &getParser() const { return Parser; }
46 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
48 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
50 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
52 ARMOperand *MaybeParseRegister(bool ParseWriteBack);
53 ARMOperand *ParseRegisterList();
54 ARMOperand *ParseMemory();
56 bool ParseMemoryOffsetReg(bool &Negative,
57 bool &OffsetRegShifted,
58 enum ShiftType &ShiftType,
59 const MCExpr *&ShiftAmount,
60 const MCExpr *&Offset,
65 bool ParseShift(enum ShiftType &St, const MCExpr *&ShiftAmount, SMLoc &E);
67 ARMOperand *ParseOperand();
69 bool ParseDirectiveWord(unsigned Size, SMLoc L);
71 bool ParseDirectiveThumb(SMLoc L);
73 bool ParseDirectiveThumbFunc(SMLoc L);
75 bool ParseDirectiveCode(SMLoc L);
77 bool ParseDirectiveSyntax(SMLoc L);
79 bool MatchAndEmitInstruction(SMLoc IDLoc,
80 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
83 /// @name Auto-generated Match Functions
86 #define GET_ASSEMBLER_HEADER
87 #include "ARMGenAsmMatcher.inc"
93 ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
94 : TargetAsmParser(T), Parser(_Parser), TM(_TM) {}
96 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
97 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
99 virtual bool ParseDirective(AsmToken DirectiveID);
101 } // end anonymous namespace
105 /// ARMOperand - Instances of this class represent a parsed ARM machine
107 struct ARMOperand : public MCParsedAsmOperand {
117 SMLoc StartLoc, EndLoc;
121 ARMCC::CondCodes Val;
138 // This is for all forms of ARM address expressions
141 unsigned OffsetRegNum; // used when OffsetIsReg is true
142 const MCExpr *Offset; // used when OffsetIsReg is false
143 const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
144 enum ShiftType ShiftType; // used when OffsetRegShifted is true
146 OffsetRegShifted : 1, // only used when OffsetIsReg is true
150 Negative : 1, // only used when OffsetIsReg is true
156 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
158 StartLoc = o.StartLoc;
179 /// getStartLoc - Get the location of the first token of this operand.
180 SMLoc getStartLoc() const { return StartLoc; }
181 /// getEndLoc - Get the location of the last token of this operand.
182 SMLoc getEndLoc() const { return EndLoc; }
184 ARMCC::CondCodes getCondCode() const {
185 assert(Kind == CondCode && "Invalid access!");
189 StringRef getToken() const {
190 assert(Kind == Token && "Invalid access!");
191 return StringRef(Tok.Data, Tok.Length);
194 unsigned getReg() const {
195 assert(Kind == Register && "Invalid access!");
199 const MCExpr *getImm() const {
200 assert(Kind == Immediate && "Invalid access!");
204 bool isCondCode() const { return Kind == CondCode; }
205 bool isImm() const { return Kind == Immediate; }
206 bool isReg() const { return Kind == Register; }
207 bool isToken() const { return Kind == Token; }
208 bool isMemory() const { return Kind == Memory; }
210 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
211 // Add as immediates when possible. Null MCExpr = 0.
213 Inst.addOperand(MCOperand::CreateImm(0));
214 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
215 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
217 Inst.addOperand(MCOperand::CreateExpr(Expr));
220 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
221 assert(N == 2 && "Invalid number of operands!");
222 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
223 // FIXME: What belongs here?
224 Inst.addOperand(MCOperand::CreateReg(0));
227 void addRegOperands(MCInst &Inst, unsigned N) const {
228 assert(N == 1 && "Invalid number of operands!");
229 Inst.addOperand(MCOperand::CreateReg(getReg()));
232 void addImmOperands(MCInst &Inst, unsigned N) const {
233 assert(N == 1 && "Invalid number of operands!");
234 addExpr(Inst, getImm());
238 bool isMemMode5() const {
239 // FIXME: Is this right? What about postindexed and Writeback?
240 if (!isMemory() || Mem.OffsetIsReg || Mem.OffsetRegShifted ||
241 Mem.Preindexed || Mem.Negative)
247 void addMemMode5Operands(MCInst &Inst, unsigned N) const {
248 assert(N == 2 && isMemMode5() && "Invalid number of operands!");
250 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
251 assert(!Mem.OffsetIsReg && "invalid mode 5 operand");
252 addExpr(Inst, Mem.Offset);
255 virtual void dump(raw_ostream &OS) const;
257 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
258 ARMOperand *Op = new ARMOperand(CondCode);
265 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
266 ARMOperand *Op = new ARMOperand(Token);
267 Op->Tok.Data = Str.data();
268 Op->Tok.Length = Str.size();
274 static ARMOperand *CreateReg(unsigned RegNum, bool Writeback, SMLoc S,
276 ARMOperand *Op = new ARMOperand(Register);
277 Op->Reg.RegNum = RegNum;
278 Op->Reg.Writeback = Writeback;
284 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
285 ARMOperand *Op = new ARMOperand(Immediate);
292 static ARMOperand *CreateMem(unsigned BaseRegNum, bool OffsetIsReg,
293 const MCExpr *Offset, unsigned OffsetRegNum,
294 bool OffsetRegShifted, enum ShiftType ShiftType,
295 const MCExpr *ShiftAmount, bool Preindexed,
296 bool Postindexed, bool Negative, bool Writeback,
298 ARMOperand *Op = new ARMOperand(Memory);
299 Op->Mem.BaseRegNum = BaseRegNum;
300 Op->Mem.OffsetIsReg = OffsetIsReg;
301 Op->Mem.Offset = Offset;
302 Op->Mem.OffsetRegNum = OffsetRegNum;
303 Op->Mem.OffsetRegShifted = OffsetRegShifted;
304 Op->Mem.ShiftType = ShiftType;
305 Op->Mem.ShiftAmount = ShiftAmount;
306 Op->Mem.Preindexed = Preindexed;
307 Op->Mem.Postindexed = Postindexed;
308 Op->Mem.Negative = Negative;
309 Op->Mem.Writeback = Writeback;
317 ARMOperand(KindTy K) : Kind(K) {}
320 } // end anonymous namespace.
322 void ARMOperand::dump(raw_ostream &OS) const {
325 OS << ARMCondCodeToString(getCondCode());
334 OS << "<register " << getReg() << ">";
337 OS << "'" << getToken() << "'";
342 /// @name Auto-generated Match Functions
345 static unsigned MatchRegisterName(StringRef Name);
349 /// Try to parse a register name. The token must be an Identifier when called,
350 /// and if it is a register name the token is eaten and a Reg operand is created
351 /// and returned. Otherwise return null.
353 /// TODO this is likely to change to allow different register types and or to
354 /// parse for a specific register type.
355 ARMOperand *ARMAsmParser::MaybeParseRegister(bool ParseWriteBack) {
357 const AsmToken &Tok = Parser.getTok();
358 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
360 // FIXME: Validate register for the current architecture; we have to do
361 // validation later, so maybe there is no need for this here.
364 RegNum = MatchRegisterName(Tok.getString());
370 Parser.Lex(); // Eat identifier token.
372 E = Parser.getTok().getLoc();
374 bool Writeback = false;
375 if (ParseWriteBack) {
376 const AsmToken &ExclaimTok = Parser.getTok();
377 if (ExclaimTok.is(AsmToken::Exclaim)) {
378 E = ExclaimTok.getLoc();
380 Parser.Lex(); // Eat exclaim token
384 return ARMOperand::CreateReg(RegNum, Writeback, S, E);
387 /// Parse a register list, return it if successful else return null. The first
388 /// token must be a '{' when called.
389 ARMOperand *ARMAsmParser::ParseRegisterList() {
391 assert(Parser.getTok().is(AsmToken::LCurly) &&
392 "Token is not an Left Curly Brace");
393 S = Parser.getTok().getLoc();
394 Parser.Lex(); // Eat left curly brace token.
396 const AsmToken &RegTok = Parser.getTok();
397 SMLoc RegLoc = RegTok.getLoc();
398 if (RegTok.isNot(AsmToken::Identifier)) {
399 Error(RegLoc, "register expected");
402 int RegNum = MatchRegisterName(RegTok.getString());
404 Error(RegLoc, "register expected");
408 Parser.Lex(); // Eat identifier token.
409 unsigned RegList = 1 << RegNum;
411 int HighRegNum = RegNum;
412 // TODO ranges like "{Rn-Rm}"
413 while (Parser.getTok().is(AsmToken::Comma)) {
414 Parser.Lex(); // Eat comma token.
416 const AsmToken &RegTok = Parser.getTok();
417 SMLoc RegLoc = RegTok.getLoc();
418 if (RegTok.isNot(AsmToken::Identifier)) {
419 Error(RegLoc, "register expected");
422 int RegNum = MatchRegisterName(RegTok.getString());
424 Error(RegLoc, "register expected");
428 if (RegList & (1 << RegNum))
429 Warning(RegLoc, "register duplicated in register list");
430 else if (RegNum <= HighRegNum)
431 Warning(RegLoc, "register not in ascending order in register list");
432 RegList |= 1 << RegNum;
435 Parser.Lex(); // Eat identifier token.
437 const AsmToken &RCurlyTok = Parser.getTok();
438 if (RCurlyTok.isNot(AsmToken::RCurly)) {
439 Error(RCurlyTok.getLoc(), "'}' expected");
442 E = RCurlyTok.getLoc();
443 Parser.Lex(); // Eat left curly brace token.
445 // FIXME: Need to return an operand!
446 Error(E, "FIXME: register list parsing not implemented");
450 /// Parse an arm memory expression, return false if successful else return true
451 /// or an error. The first token must be a '[' when called.
452 /// TODO Only preindexing and postindexing addressing are started, unindexed
453 /// with option, etc are still to do.
454 ARMOperand *ARMAsmParser::ParseMemory() {
456 assert(Parser.getTok().is(AsmToken::LBrac) &&
457 "Token is not an Left Bracket");
458 S = Parser.getTok().getLoc();
459 Parser.Lex(); // Eat left bracket token.
461 const AsmToken &BaseRegTok = Parser.getTok();
462 if (BaseRegTok.isNot(AsmToken::Identifier)) {
463 Error(BaseRegTok.getLoc(), "register expected");
467 if (ARMOperand *Op = MaybeParseRegister(false))
468 BaseRegNum = Op->getReg();
470 Error(BaseRegTok.getLoc(), "register expected");
474 bool Preindexed = false;
475 bool Postindexed = false;
476 bool OffsetIsReg = false;
477 bool Negative = false;
478 bool Writeback = false;
480 // First look for preindexed address forms, that is after the "[Rn" we now
481 // have to see if the next token is a comma.
482 const AsmToken &Tok = Parser.getTok();
483 if (Tok.is(AsmToken::Comma)) {
485 Parser.Lex(); // Eat comma token.
487 bool OffsetRegShifted;
488 enum ShiftType ShiftType;
489 const MCExpr *ShiftAmount;
490 const MCExpr *Offset;
491 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
492 Offset, OffsetIsReg, OffsetRegNum, E))
494 const AsmToken &RBracTok = Parser.getTok();
495 if (RBracTok.isNot(AsmToken::RBrac)) {
496 Error(RBracTok.getLoc(), "']' expected");
499 E = RBracTok.getLoc();
500 Parser.Lex(); // Eat right bracket token.
502 const AsmToken &ExclaimTok = Parser.getTok();
503 if (ExclaimTok.is(AsmToken::Exclaim)) {
504 E = ExclaimTok.getLoc();
506 Parser.Lex(); // Eat exclaim token
508 return ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
509 OffsetRegShifted, ShiftType, ShiftAmount,
510 Preindexed, Postindexed, Negative, Writeback,
513 // The "[Rn" we have so far was not followed by a comma.
514 else if (Tok.is(AsmToken::RBrac)) {
515 // This is a post indexing addressing forms, that is a ']' follows after
520 Parser.Lex(); // Eat right bracket token.
522 int OffsetRegNum = 0;
523 bool OffsetRegShifted = false;
524 enum ShiftType ShiftType;
525 const MCExpr *ShiftAmount;
526 const MCExpr *Offset = 0;
528 const AsmToken &NextTok = Parser.getTok();
529 if (NextTok.isNot(AsmToken::EndOfStatement)) {
530 if (NextTok.isNot(AsmToken::Comma)) {
531 Error(NextTok.getLoc(), "',' expected");
534 Parser.Lex(); // Eat comma token.
535 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
536 ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
541 return ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
542 OffsetRegShifted, ShiftType, ShiftAmount,
543 Preindexed, Postindexed, Negative, Writeback,
550 /// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
551 /// we will parse the following (were +/- means that a plus or minus is
556 /// we return false on success or an error otherwise.
557 bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
558 bool &OffsetRegShifted,
559 enum ShiftType &ShiftType,
560 const MCExpr *&ShiftAmount,
561 const MCExpr *&Offset,
566 OffsetRegShifted = false;
569 const AsmToken &NextTok = Parser.getTok();
570 E = NextTok.getLoc();
571 if (NextTok.is(AsmToken::Plus))
572 Parser.Lex(); // Eat plus token.
573 else if (NextTok.is(AsmToken::Minus)) {
575 Parser.Lex(); // Eat minus token
577 // See if there is a register following the "[Rn," or "[Rn]," we have so far.
578 const AsmToken &OffsetRegTok = Parser.getTok();
579 if (OffsetRegTok.is(AsmToken::Identifier)) {
580 if (ARMOperand *Op = MaybeParseRegister(false)) {
583 OffsetRegNum = Op->getReg();
587 // If we parsed a register as the offset then their can be a shift after that
588 if (OffsetRegNum != -1) {
589 // Look for a comma then a shift
590 const AsmToken &Tok = Parser.getTok();
591 if (Tok.is(AsmToken::Comma)) {
592 Parser.Lex(); // Eat comma token.
594 const AsmToken &Tok = Parser.getTok();
595 if (ParseShift(ShiftType, ShiftAmount, E))
596 return Error(Tok.getLoc(), "shift expected");
597 OffsetRegShifted = true;
600 else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
601 // Look for #offset following the "[Rn," or "[Rn],"
602 const AsmToken &HashTok = Parser.getTok();
603 if (HashTok.isNot(AsmToken::Hash))
604 return Error(HashTok.getLoc(), "'#' expected");
606 Parser.Lex(); // Eat hash token.
608 if (getParser().ParseExpression(Offset))
610 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
615 /// ParseShift as one of these two:
616 /// ( lsl | lsr | asr | ror ) , # shift_amount
618 /// and returns true if it parses a shift otherwise it returns false.
619 bool ARMAsmParser::ParseShift(ShiftType &St, const MCExpr *&ShiftAmount,
621 const AsmToken &Tok = Parser.getTok();
622 if (Tok.isNot(AsmToken::Identifier))
624 StringRef ShiftName = Tok.getString();
625 if (ShiftName == "lsl" || ShiftName == "LSL")
627 else if (ShiftName == "lsr" || ShiftName == "LSR")
629 else if (ShiftName == "asr" || ShiftName == "ASR")
631 else if (ShiftName == "ror" || ShiftName == "ROR")
633 else if (ShiftName == "rrx" || ShiftName == "RRX")
637 Parser.Lex(); // Eat shift type token.
643 // Otherwise, there must be a '#' and a shift amount.
644 const AsmToken &HashTok = Parser.getTok();
645 if (HashTok.isNot(AsmToken::Hash))
646 return Error(HashTok.getLoc(), "'#' expected");
647 Parser.Lex(); // Eat hash token.
649 if (getParser().ParseExpression(ShiftAmount))
655 /// Parse a arm instruction operand. For now this parses the operand regardless
657 ARMOperand *ARMAsmParser::ParseOperand() {
660 switch (getLexer().getKind()) {
661 case AsmToken::Identifier:
662 if (ARMOperand *Op = MaybeParseRegister(true))
665 // This was not a register so parse other operands that start with an
666 // identifier (like labels) as expressions and create them as immediates.
668 S = Parser.getTok().getLoc();
669 if (getParser().ParseExpression(IdVal))
671 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
672 return ARMOperand::CreateImm(IdVal, S, E);
673 case AsmToken::LBrac:
674 return ParseMemory();
675 case AsmToken::LCurly:
676 return ParseRegisterList();
679 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
680 S = Parser.getTok().getLoc();
682 const MCExpr *ImmVal;
683 if (getParser().ParseExpression(ImmVal))
685 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
686 return ARMOperand::CreateImm(ImmVal, S, E);
688 Error(Parser.getTok().getLoc(), "unexpected token in operand");
693 /// Parse an arm instruction mnemonic followed by its operands.
694 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
695 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
696 // Create the leading tokens for the mnemonic, split by '.' characters.
697 size_t Start = 0, Next = Name.find('.');
698 StringRef Head = Name.slice(Start, Next);
700 // Determine the predicate, if any.
702 // FIXME: We need a way to check whether a prefix supports predication,
703 // otherwise we will end up with an ambiguity for instructions that happen to
704 // end with a predicate name.
705 unsigned CC = StringSwitch<unsigned>(Head.substr(Head.size()-2))
706 .Case("eq", ARMCC::EQ)
707 .Case("ne", ARMCC::NE)
708 .Case("hs", ARMCC::HS)
709 .Case("lo", ARMCC::LO)
710 .Case("mi", ARMCC::MI)
711 .Case("pl", ARMCC::PL)
712 .Case("vs", ARMCC::VS)
713 .Case("vc", ARMCC::VC)
714 .Case("hi", ARMCC::HI)
715 .Case("ls", ARMCC::LS)
716 .Case("ge", ARMCC::GE)
717 .Case("lt", ARMCC::LT)
718 .Case("gt", ARMCC::GT)
719 .Case("le", ARMCC::LE)
720 .Case("al", ARMCC::AL)
724 Head = Head.slice(0, Head.size() - 2);
728 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
729 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), NameLoc));
731 // Add the remaining tokens in the mnemonic.
732 while (Next != StringRef::npos) {
734 Next = Name.find('.', Start + 1);
735 Head = Name.slice(Start, Next);
737 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
740 // Read the remaining operands.
741 if (getLexer().isNot(AsmToken::EndOfStatement)) {
742 // Read the first operand.
743 if (ARMOperand *Op = ParseOperand())
744 Operands.push_back(Op);
746 Parser.EatToEndOfStatement();
750 while (getLexer().is(AsmToken::Comma)) {
751 Parser.Lex(); // Eat the comma.
753 // Parse and remember the operand.
754 if (ARMOperand *Op = ParseOperand())
755 Operands.push_back(Op);
757 Parser.EatToEndOfStatement();
763 if (getLexer().isNot(AsmToken::EndOfStatement)) {
764 Parser.EatToEndOfStatement();
765 return TokError("unexpected token in argument list");
767 Parser.Lex(); // Consume the EndOfStatement
772 MatchAndEmitInstruction(SMLoc IDLoc,
773 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
777 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo)) {
779 Out.EmitInstruction(Inst);
782 case Match_MissingFeature:
783 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
785 case Match_InvalidOperand: {
786 SMLoc ErrorLoc = IDLoc;
787 if (ErrorInfo != ~0U) {
788 if (ErrorInfo >= Operands.size())
789 return Error(IDLoc, "too few operands for instruction");
791 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
792 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
795 return Error(ErrorLoc, "invalid operand for instruction");
797 case Match_MnemonicFail:
798 return Error(IDLoc, "unrecognized instruction mnemonic");
801 llvm_unreachable("Implement any new match types added!");
806 /// ParseDirective parses the arm specific directives
807 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
808 StringRef IDVal = DirectiveID.getIdentifier();
809 if (IDVal == ".word")
810 return ParseDirectiveWord(4, DirectiveID.getLoc());
811 else if (IDVal == ".thumb")
812 return ParseDirectiveThumb(DirectiveID.getLoc());
813 else if (IDVal == ".thumb_func")
814 return ParseDirectiveThumbFunc(DirectiveID.getLoc());
815 else if (IDVal == ".code")
816 return ParseDirectiveCode(DirectiveID.getLoc());
817 else if (IDVal == ".syntax")
818 return ParseDirectiveSyntax(DirectiveID.getLoc());
822 /// ParseDirectiveWord
823 /// ::= .word [ expression (, expression)* ]
824 bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
825 if (getLexer().isNot(AsmToken::EndOfStatement)) {
828 if (getParser().ParseExpression(Value))
831 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
833 if (getLexer().is(AsmToken::EndOfStatement))
836 // FIXME: Improve diagnostic.
837 if (getLexer().isNot(AsmToken::Comma))
838 return Error(L, "unexpected token in directive");
847 /// ParseDirectiveThumb
849 bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
850 if (getLexer().isNot(AsmToken::EndOfStatement))
851 return Error(L, "unexpected token in directive");
854 // TODO: set thumb mode
855 // TODO: tell the MC streamer the mode
856 // getParser().getStreamer().Emit???();
860 /// ParseDirectiveThumbFunc
861 /// ::= .thumbfunc symbol_name
862 bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
863 const AsmToken &Tok = Parser.getTok();
864 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
865 return Error(L, "unexpected token in .syntax directive");
866 Parser.Lex(); // Consume the identifier token.
868 if (getLexer().isNot(AsmToken::EndOfStatement))
869 return Error(L, "unexpected token in directive");
872 // TODO: mark symbol as a thumb symbol
873 // getParser().getStreamer().Emit???();
877 /// ParseDirectiveSyntax
878 /// ::= .syntax unified | divided
879 bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
880 const AsmToken &Tok = Parser.getTok();
881 if (Tok.isNot(AsmToken::Identifier))
882 return Error(L, "unexpected token in .syntax directive");
883 StringRef Mode = Tok.getString();
884 if (Mode == "unified" || Mode == "UNIFIED")
886 else if (Mode == "divided" || Mode == "DIVIDED")
889 return Error(L, "unrecognized syntax mode in .syntax directive");
891 if (getLexer().isNot(AsmToken::EndOfStatement))
892 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
895 // TODO tell the MC streamer the mode
896 // getParser().getStreamer().Emit???();
900 /// ParseDirectiveCode
901 /// ::= .code 16 | 32
902 bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
903 const AsmToken &Tok = Parser.getTok();
904 if (Tok.isNot(AsmToken::Integer))
905 return Error(L, "unexpected token in .code directive");
906 int64_t Val = Parser.getTok().getIntVal();
912 return Error(L, "invalid operand to .code directive");
914 if (getLexer().isNot(AsmToken::EndOfStatement))
915 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
918 // TODO tell the MC streamer the mode
919 // getParser().getStreamer().Emit???();
923 extern "C" void LLVMInitializeARMAsmLexer();
925 /// Force static initialization.
926 extern "C" void LLVMInitializeARMAsmParser() {
927 RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
928 RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
929 LLVMInitializeARMAsmLexer();
932 #define GET_REGISTER_MATCHER
933 #define GET_MATCHER_IMPLEMENTATION
934 #include "ARMGenAsmMatcher.inc"