1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMSubtarget.h"
12 #include "llvm/MC/MCParser/MCAsmLexer.h"
13 #include "llvm/MC/MCParser/MCAsmParser.h"
14 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
15 #include "llvm/MC/MCStreamer.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/Target/TargetRegistry.h"
19 #include "llvm/Target/TargetAsmParser.h"
20 #include "llvm/Support/Compiler.h"
21 #include "llvm/Support/SourceMgr.h"
22 #include "llvm/Support/raw_ostream.h"
23 #include "llvm/ADT/OwningPtr.h"
24 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/ADT/StringSwitch.h"
26 #include "llvm/ADT/Twine.h"
32 // The shift types for register controlled shifts in arm memory addressing
41 class ARMAsmParser : public TargetAsmParser {
46 MCAsmParser &getParser() const { return Parser; }
48 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
50 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
52 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
54 bool MaybeParseRegister(OwningPtr<ARMOperand> &Op, bool ParseWriteBack);
56 bool ParseRegisterList(OwningPtr<ARMOperand> &Op);
58 bool ParseMemory(OwningPtr<ARMOperand> &Op);
60 bool ParseMemoryOffsetReg(bool &Negative,
61 bool &OffsetRegShifted,
62 enum ShiftType &ShiftType,
63 const MCExpr *&ShiftAmount,
64 const MCExpr *&Offset,
69 bool ParseShift(enum ShiftType &St, const MCExpr *&ShiftAmount, SMLoc &E);
71 bool ParseOperand(OwningPtr<ARMOperand> &Op);
73 bool ParseDirectiveWord(unsigned Size, SMLoc L);
75 bool ParseDirectiveThumb(SMLoc L);
77 bool ParseDirectiveThumbFunc(SMLoc L);
79 bool ParseDirectiveCode(SMLoc L);
81 bool ParseDirectiveSyntax(SMLoc L);
83 bool MatchInstruction(SMLoc IDLoc,
84 const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
86 if (!MatchInstructionImpl(Operands, Inst))
89 // FIXME: We should give nicer diagnostics about the exact failure.
90 Error(IDLoc, "unrecognized instruction");
95 /// @name Auto-generated Match Functions
98 #define GET_ASSEMBLER_HEADER
99 #include "ARMGenAsmMatcher.inc"
105 ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
106 : TargetAsmParser(T), Parser(_Parser), TM(_TM) {}
108 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
109 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
111 virtual bool ParseDirective(AsmToken DirectiveID);
114 /// ARMOperand - Instances of this class represent a parsed ARM machine
116 struct ARMOperand : public MCParsedAsmOperand {
128 SMLoc StartLoc, EndLoc;
132 ARMCC::CondCodes Val;
149 // This is for all forms of ARM address expressions
152 unsigned OffsetRegNum; // used when OffsetIsReg is true
153 const MCExpr *Offset; // used when OffsetIsReg is false
154 const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
155 enum ShiftType ShiftType; // used when OffsetRegShifted is true
157 OffsetRegShifted : 1, // only used when OffsetIsReg is true
161 Negative : 1, // only used when OffsetIsReg is true
167 //ARMOperand(KindTy K, SMLoc S, SMLoc E)
168 // : Kind(K), StartLoc(S), EndLoc(E) {}
170 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
172 StartLoc = o.StartLoc;
193 /// getStartLoc - Get the location of the first token of this operand.
194 SMLoc getStartLoc() const { return StartLoc; }
195 /// getEndLoc - Get the location of the last token of this operand.
196 SMLoc getEndLoc() const { return EndLoc; }
198 ARMCC::CondCodes getCondCode() const {
199 assert(Kind == CondCode && "Invalid access!");
203 StringRef getToken() const {
204 assert(Kind == Token && "Invalid access!");
205 return StringRef(Tok.Data, Tok.Length);
208 unsigned getReg() const {
209 assert(Kind == Register && "Invalid access!");
213 const MCExpr *getImm() const {
214 assert(Kind == Immediate && "Invalid access!");
218 bool isCondCode() const { return Kind == CondCode; }
220 bool isImm() const { return Kind == Immediate; }
222 bool isReg() const { return Kind == Register; }
224 bool isToken() const {return Kind == Token; }
226 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
227 // Add as immediates when possible.
228 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
229 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
231 Inst.addOperand(MCOperand::CreateExpr(Expr));
234 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
235 assert(N == 2 && "Invalid number of operands!");
236 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
237 // FIXME: What belongs here?
238 Inst.addOperand(MCOperand::CreateReg(0));
241 void addRegOperands(MCInst &Inst, unsigned N) const {
242 assert(N == 1 && "Invalid number of operands!");
243 Inst.addOperand(MCOperand::CreateReg(getReg()));
246 void addImmOperands(MCInst &Inst, unsigned N) const {
247 assert(N == 1 && "Invalid number of operands!");
248 addExpr(Inst, getImm());
251 virtual void dump(raw_ostream &OS) const;
253 static void CreateCondCode(OwningPtr<ARMOperand> &Op, ARMCC::CondCodes CC,
255 Op.reset(new ARMOperand);
262 static void CreateToken(OwningPtr<ARMOperand> &Op, StringRef Str,
264 Op.reset(new ARMOperand);
266 Op->Tok.Data = Str.data();
267 Op->Tok.Length = Str.size();
272 static void CreateReg(OwningPtr<ARMOperand> &Op, unsigned RegNum,
273 bool Writeback, SMLoc S, SMLoc E) {
274 Op.reset(new ARMOperand);
276 Op->Reg.RegNum = RegNum;
277 Op->Reg.Writeback = Writeback;
283 static void CreateImm(OwningPtr<ARMOperand> &Op, const MCExpr *Val,
285 Op.reset(new ARMOperand);
286 Op->Kind = Immediate;
293 static void CreateMem(OwningPtr<ARMOperand> &Op,
294 unsigned BaseRegNum, bool OffsetIsReg,
295 const MCExpr *Offset, unsigned OffsetRegNum,
296 bool OffsetRegShifted, enum ShiftType ShiftType,
297 const MCExpr *ShiftAmount, bool Preindexed,
298 bool Postindexed, bool Negative, bool Writeback,
300 Op.reset(new ARMOperand);
302 Op->Mem.BaseRegNum = BaseRegNum;
303 Op->Mem.OffsetIsReg = OffsetIsReg;
304 Op->Mem.Offset = Offset;
305 Op->Mem.OffsetRegNum = OffsetRegNum;
306 Op->Mem.OffsetRegShifted = OffsetRegShifted;
307 Op->Mem.ShiftType = ShiftType;
308 Op->Mem.ShiftAmount = ShiftAmount;
309 Op->Mem.Preindexed = Preindexed;
310 Op->Mem.Postindexed = Postindexed;
311 Op->Mem.Negative = Negative;
312 Op->Mem.Writeback = Writeback;
319 } // end anonymous namespace.
321 void ARMOperand::dump(raw_ostream &OS) const {
324 OS << ARMCondCodeToString(getCondCode());
333 OS << "<register " << getReg() << ">";
336 OS << "'" << getToken() << "'";
341 /// @name Auto-generated Match Functions
344 static unsigned MatchRegisterName(StringRef Name);
348 /// Try to parse a register name. The token must be an Identifier when called,
349 /// and if it is a register name a Reg operand is created, the token is eaten
350 /// and false is returned. Else true is returned and no token is eaten.
351 /// TODO this is likely to change to allow different register types and or to
352 /// parse for a specific register type.
353 bool ARMAsmParser::MaybeParseRegister
354 (OwningPtr<ARMOperand> &Op, bool ParseWriteBack) {
356 const AsmToken &Tok = Parser.getTok();
357 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
359 // FIXME: Validate register for the current architecture; we have to do
360 // validation later, so maybe there is no need for this here.
363 RegNum = MatchRegisterName(Tok.getString());
369 Parser.Lex(); // Eat identifier token.
371 E = Parser.getTok().getLoc();
373 bool Writeback = false;
374 if (ParseWriteBack) {
375 const AsmToken &ExclaimTok = Parser.getTok();
376 if (ExclaimTok.is(AsmToken::Exclaim)) {
377 E = ExclaimTok.getLoc();
379 Parser.Lex(); // Eat exclaim token
383 ARMOperand::CreateReg(Op, RegNum, Writeback, S, E);
388 /// Parse a register list, return false if successful else return true or an
389 /// error. The first token must be a '{' when called.
390 bool ARMAsmParser::ParseRegisterList(OwningPtr<ARMOperand> &Op) {
392 assert(Parser.getTok().is(AsmToken::LCurly) &&
393 "Token is not an Left Curly Brace");
394 S = Parser.getTok().getLoc();
395 Parser.Lex(); // Eat left curly brace token.
397 const AsmToken &RegTok = Parser.getTok();
398 SMLoc RegLoc = RegTok.getLoc();
399 if (RegTok.isNot(AsmToken::Identifier))
400 return Error(RegLoc, "register expected");
401 int RegNum = MatchRegisterName(RegTok.getString());
403 return Error(RegLoc, "register expected");
404 Parser.Lex(); // Eat identifier token.
405 unsigned RegList = 1 << RegNum;
407 int HighRegNum = RegNum;
408 // TODO ranges like "{Rn-Rm}"
409 while (Parser.getTok().is(AsmToken::Comma)) {
410 Parser.Lex(); // Eat comma token.
412 const AsmToken &RegTok = Parser.getTok();
413 SMLoc RegLoc = RegTok.getLoc();
414 if (RegTok.isNot(AsmToken::Identifier))
415 return Error(RegLoc, "register expected");
416 int RegNum = MatchRegisterName(RegTok.getString());
418 return Error(RegLoc, "register expected");
420 if (RegList & (1 << RegNum))
421 Warning(RegLoc, "register duplicated in register list");
422 else if (RegNum <= HighRegNum)
423 Warning(RegLoc, "register not in ascending order in register list");
424 RegList |= 1 << RegNum;
427 Parser.Lex(); // Eat identifier token.
429 const AsmToken &RCurlyTok = Parser.getTok();
430 if (RCurlyTok.isNot(AsmToken::RCurly))
431 return Error(RCurlyTok.getLoc(), "'}' expected");
432 E = RCurlyTok.getLoc();
433 Parser.Lex(); // Eat left curly brace token.
438 /// Parse an arm memory expression, return false if successful else return true
439 /// or an error. The first token must be a '[' when called.
440 /// TODO Only preindexing and postindexing addressing are started, unindexed
441 /// with option, etc are still to do.
442 bool ARMAsmParser::ParseMemory(OwningPtr<ARMOperand> &Op) {
444 assert(Parser.getTok().is(AsmToken::LBrac) &&
445 "Token is not an Left Bracket");
446 S = Parser.getTok().getLoc();
447 Parser.Lex(); // Eat left bracket token.
449 const AsmToken &BaseRegTok = Parser.getTok();
450 if (BaseRegTok.isNot(AsmToken::Identifier))
451 return Error(BaseRegTok.getLoc(), "register expected");
452 if (MaybeParseRegister(Op, false))
453 return Error(BaseRegTok.getLoc(), "register expected");
454 int BaseRegNum = Op->getReg();
456 bool Preindexed = false;
457 bool Postindexed = false;
458 bool OffsetIsReg = false;
459 bool Negative = false;
460 bool Writeback = false;
462 // First look for preindexed address forms, that is after the "[Rn" we now
463 // have to see if the next token is a comma.
464 const AsmToken &Tok = Parser.getTok();
465 if (Tok.is(AsmToken::Comma)) {
467 Parser.Lex(); // Eat comma token.
469 bool OffsetRegShifted;
470 enum ShiftType ShiftType;
471 const MCExpr *ShiftAmount;
472 const MCExpr *Offset;
473 if(ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
474 Offset, OffsetIsReg, OffsetRegNum, E))
476 const AsmToken &RBracTok = Parser.getTok();
477 if (RBracTok.isNot(AsmToken::RBrac))
478 return Error(RBracTok.getLoc(), "']' expected");
479 E = RBracTok.getLoc();
480 Parser.Lex(); // Eat right bracket token.
482 const AsmToken &ExclaimTok = Parser.getTok();
483 if (ExclaimTok.is(AsmToken::Exclaim)) {
484 E = ExclaimTok.getLoc();
486 Parser.Lex(); // Eat exclaim token
488 ARMOperand::CreateMem(Op, BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
489 OffsetRegShifted, ShiftType, ShiftAmount,
490 Preindexed, Postindexed, Negative, Writeback, S, E);
493 // The "[Rn" we have so far was not followed by a comma.
494 else if (Tok.is(AsmToken::RBrac)) {
495 // This is a post indexing addressing forms, that is a ']' follows after
500 Parser.Lex(); // Eat right bracket token.
502 int OffsetRegNum = 0;
503 bool OffsetRegShifted = false;
504 enum ShiftType ShiftType;
505 const MCExpr *ShiftAmount;
506 const MCExpr *Offset;
508 const AsmToken &NextTok = Parser.getTok();
509 if (NextTok.isNot(AsmToken::EndOfStatement)) {
510 if (NextTok.isNot(AsmToken::Comma))
511 return Error(NextTok.getLoc(), "',' expected");
512 Parser.Lex(); // Eat comma token.
513 if(ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
514 ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
519 ARMOperand::CreateMem(Op, BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
520 OffsetRegShifted, ShiftType, ShiftAmount,
521 Preindexed, Postindexed, Negative, Writeback, S, E);
528 /// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
529 /// we will parse the following (were +/- means that a plus or minus is
534 /// we return false on success or an error otherwise.
535 bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
536 bool &OffsetRegShifted,
537 enum ShiftType &ShiftType,
538 const MCExpr *&ShiftAmount,
539 const MCExpr *&Offset,
543 OwningPtr<ARMOperand> Op;
545 OffsetRegShifted = false;
548 const AsmToken &NextTok = Parser.getTok();
549 E = NextTok.getLoc();
550 if (NextTok.is(AsmToken::Plus))
551 Parser.Lex(); // Eat plus token.
552 else if (NextTok.is(AsmToken::Minus)) {
554 Parser.Lex(); // Eat minus token
556 // See if there is a register following the "[Rn," or "[Rn]," we have so far.
557 const AsmToken &OffsetRegTok = Parser.getTok();
558 if (OffsetRegTok.is(AsmToken::Identifier)) {
559 OffsetIsReg = !MaybeParseRegister(Op, false);
562 OffsetRegNum = Op->getReg();
565 // If we parsed a register as the offset then their can be a shift after that
566 if (OffsetRegNum != -1) {
567 // Look for a comma then a shift
568 const AsmToken &Tok = Parser.getTok();
569 if (Tok.is(AsmToken::Comma)) {
570 Parser.Lex(); // Eat comma token.
572 const AsmToken &Tok = Parser.getTok();
573 if (ParseShift(ShiftType, ShiftAmount, E))
574 return Error(Tok.getLoc(), "shift expected");
575 OffsetRegShifted = true;
578 else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
579 // Look for #offset following the "[Rn," or "[Rn],"
580 const AsmToken &HashTok = Parser.getTok();
581 if (HashTok.isNot(AsmToken::Hash))
582 return Error(HashTok.getLoc(), "'#' expected");
584 Parser.Lex(); // Eat hash token.
586 if (getParser().ParseExpression(Offset))
588 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
593 /// ParseShift as one of these two:
594 /// ( lsl | lsr | asr | ror ) , # shift_amount
596 /// and returns true if it parses a shift otherwise it returns false.
597 bool ARMAsmParser::ParseShift(ShiftType &St,
598 const MCExpr *&ShiftAmount,
600 const AsmToken &Tok = Parser.getTok();
601 if (Tok.isNot(AsmToken::Identifier))
603 StringRef ShiftName = Tok.getString();
604 if (ShiftName == "lsl" || ShiftName == "LSL")
606 else if (ShiftName == "lsr" || ShiftName == "LSR")
608 else if (ShiftName == "asr" || ShiftName == "ASR")
610 else if (ShiftName == "ror" || ShiftName == "ROR")
612 else if (ShiftName == "rrx" || ShiftName == "RRX")
616 Parser.Lex(); // Eat shift type token.
622 // Otherwise, there must be a '#' and a shift amount.
623 const AsmToken &HashTok = Parser.getTok();
624 if (HashTok.isNot(AsmToken::Hash))
625 return Error(HashTok.getLoc(), "'#' expected");
626 Parser.Lex(); // Eat hash token.
628 if (getParser().ParseExpression(ShiftAmount))
634 /// Parse a arm instruction operand. For now this parses the operand regardless
636 bool ARMAsmParser::ParseOperand(OwningPtr<ARMOperand> &Op) {
639 switch (getLexer().getKind()) {
640 case AsmToken::Identifier:
641 if (!MaybeParseRegister(Op, true))
643 // This was not a register so parse other operands that start with an
644 // identifier (like labels) as expressions and create them as immediates.
646 S = Parser.getTok().getLoc();
647 if (getParser().ParseExpression(IdVal))
649 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
650 ARMOperand::CreateImm(Op, IdVal, S, E);
652 case AsmToken::LBrac:
653 return ParseMemory(Op);
654 case AsmToken::LCurly:
655 return ParseRegisterList(Op);
658 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
659 S = Parser.getTok().getLoc();
661 const MCExpr *ImmVal;
662 if (getParser().ParseExpression(ImmVal))
664 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
665 ARMOperand::CreateImm(Op, ImmVal, S, E);
668 return Error(Parser.getTok().getLoc(), "unexpected token in operand");
672 /// Parse an arm instruction mnemonic followed by its operands.
673 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
674 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
675 OwningPtr<ARMOperand> Op;
677 // Create the leading tokens for the mnemonic, split by '.' characters.
678 size_t Start = 0, Next = Name.find('.');
679 StringRef Head = Name.slice(Start, Next);
681 // Determine the predicate, if any.
683 // FIXME: We need a way to check whether a prefix supports predication,
684 // otherwise we will end up with an ambiguity for instructions that happen to
685 // end with a predicate name.
686 unsigned CC = StringSwitch<unsigned>(Head.substr(Head.size()-2))
687 .Case("eq", ARMCC::EQ)
688 .Case("ne", ARMCC::NE)
689 .Case("hs", ARMCC::HS)
690 .Case("lo", ARMCC::LO)
691 .Case("mi", ARMCC::MI)
692 .Case("pl", ARMCC::PL)
693 .Case("vs", ARMCC::VS)
694 .Case("vc", ARMCC::VC)
695 .Case("hi", ARMCC::HI)
696 .Case("ls", ARMCC::LS)
697 .Case("ge", ARMCC::GE)
698 .Case("lt", ARMCC::LT)
699 .Case("gt", ARMCC::GT)
700 .Case("le", ARMCC::LE)
701 .Case("al", ARMCC::AL)
704 Head = Head.slice(0, Head.size() - 2);
708 ARMOperand::CreateToken(Op, Head, NameLoc);
709 Operands.push_back(Op.take());
711 ARMOperand::CreateCondCode(Op, ARMCC::CondCodes(CC), NameLoc);
712 Operands.push_back(Op.take());
714 // Add the remaining tokens in the mnemonic.
715 while (Next != StringRef::npos) {
717 Next = Name.find('.', Start + 1);
718 Head = Name.slice(Start, Next);
720 ARMOperand::CreateToken(Op, Head, NameLoc);
721 Operands.push_back(Op.take());
724 // Read the remaining operands.
725 if (getLexer().isNot(AsmToken::EndOfStatement)) {
726 // Read the first operand.
727 OwningPtr<ARMOperand> Op;
728 if (ParseOperand(Op)) return true;
729 Operands.push_back(Op.take());
731 while (getLexer().is(AsmToken::Comma)) {
732 Parser.Lex(); // Eat the comma.
734 // Parse and remember the operand.
735 if (ParseOperand(Op)) return true;
736 Operands.push_back(Op.take());
742 /// ParseDirective parses the arm specific directives
743 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
744 StringRef IDVal = DirectiveID.getIdentifier();
745 if (IDVal == ".word")
746 return ParseDirectiveWord(4, DirectiveID.getLoc());
747 else if (IDVal == ".thumb")
748 return ParseDirectiveThumb(DirectiveID.getLoc());
749 else if (IDVal == ".thumb_func")
750 return ParseDirectiveThumbFunc(DirectiveID.getLoc());
751 else if (IDVal == ".code")
752 return ParseDirectiveCode(DirectiveID.getLoc());
753 else if (IDVal == ".syntax")
754 return ParseDirectiveSyntax(DirectiveID.getLoc());
758 /// ParseDirectiveWord
759 /// ::= .word [ expression (, expression)* ]
760 bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
761 if (getLexer().isNot(AsmToken::EndOfStatement)) {
764 if (getParser().ParseExpression(Value))
767 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
769 if (getLexer().is(AsmToken::EndOfStatement))
772 // FIXME: Improve diagnostic.
773 if (getLexer().isNot(AsmToken::Comma))
774 return Error(L, "unexpected token in directive");
783 /// ParseDirectiveThumb
785 bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
786 if (getLexer().isNot(AsmToken::EndOfStatement))
787 return Error(L, "unexpected token in directive");
790 // TODO: set thumb mode
791 // TODO: tell the MC streamer the mode
792 // getParser().getStreamer().Emit???();
796 /// ParseDirectiveThumbFunc
797 /// ::= .thumbfunc symbol_name
798 bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
799 const AsmToken &Tok = Parser.getTok();
800 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
801 return Error(L, "unexpected token in .syntax directive");
802 StringRef ATTRIBUTE_UNUSED SymbolName = Parser.getTok().getIdentifier();
803 Parser.Lex(); // Consume the identifier token.
805 if (getLexer().isNot(AsmToken::EndOfStatement))
806 return Error(L, "unexpected token in directive");
809 // TODO: mark symbol as a thumb symbol
810 // getParser().getStreamer().Emit???();
814 /// ParseDirectiveSyntax
815 /// ::= .syntax unified | divided
816 bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
817 const AsmToken &Tok = Parser.getTok();
818 if (Tok.isNot(AsmToken::Identifier))
819 return Error(L, "unexpected token in .syntax directive");
820 StringRef Mode = Tok.getString();
821 if (Mode == "unified" || Mode == "UNIFIED")
823 else if (Mode == "divided" || Mode == "DIVIDED")
826 return Error(L, "unrecognized syntax mode in .syntax directive");
828 if (getLexer().isNot(AsmToken::EndOfStatement))
829 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
832 // TODO tell the MC streamer the mode
833 // getParser().getStreamer().Emit???();
837 /// ParseDirectiveCode
838 /// ::= .code 16 | 32
839 bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
840 const AsmToken &Tok = Parser.getTok();
841 if (Tok.isNot(AsmToken::Integer))
842 return Error(L, "unexpected token in .code directive");
843 int64_t Val = Parser.getTok().getIntVal();
849 return Error(L, "invalid operand to .code directive");
851 if (getLexer().isNot(AsmToken::EndOfStatement))
852 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
855 // TODO tell the MC streamer the mode
856 // getParser().getStreamer().Emit???();
860 extern "C" void LLVMInitializeARMAsmLexer();
862 /// Force static initialization.
863 extern "C" void LLVMInitializeARMAsmParser() {
864 RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
865 RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
866 LLVMInitializeARMAsmLexer();
869 #define GET_REGISTER_MATCHER
870 #define GET_MATCHER_IMPLEMENTATION
871 #include "ARMGenAsmMatcher.inc"