1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMBaseInfo.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMMCExpr.h"
13 #include "llvm/MC/MCParser/MCAsmLexer.h"
14 #include "llvm/MC/MCParser/MCAsmParser.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCAsmInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCTargetAsmParser.h"
25 #include "llvm/Support/SourceMgr.h"
26 #include "llvm/Support/TargetRegistry.h"
27 #include "llvm/Support/raw_ostream.h"
28 #include "llvm/ADT/BitVector.h"
29 #include "llvm/ADT/OwningPtr.h"
30 #include "llvm/ADT/STLExtras.h"
31 #include "llvm/ADT/SmallVector.h"
32 #include "llvm/ADT/StringExtras.h"
33 #include "llvm/ADT/StringSwitch.h"
34 #include "llvm/ADT/Twine.h"
42 class ARMAsmParser : public MCTargetAsmParser {
46 MCAsmParser &getParser() const { return Parser; }
47 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
49 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
50 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
52 int tryParseRegister();
53 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
54 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
55 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
56 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
57 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
58 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
59 const MCExpr *applyPrefixToExpr(const MCExpr *E,
60 MCSymbolRefExpr::VariantKind Variant);
63 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
64 unsigned &ShiftAmount);
65 bool parseDirectiveWord(unsigned Size, SMLoc L);
66 bool parseDirectiveThumb(SMLoc L);
67 bool parseDirectiveThumbFunc(SMLoc L);
68 bool parseDirectiveCode(SMLoc L);
69 bool parseDirectiveSyntax(SMLoc L);
71 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
72 bool &CarrySetting, unsigned &ProcessorIMod);
73 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
74 bool &CanAcceptPredicationCode);
76 bool isThumb() const {
77 // FIXME: Can tablegen auto-generate this?
78 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
80 bool isThumbOne() const {
81 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
83 bool isThumbTwo() const {
84 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
86 bool hasV6Ops() const {
87 return STI.getFeatureBits() & ARM::HasV6Ops;
90 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
91 setAvailableFeatures(FB);
94 /// @name Auto-generated Match Functions
97 #define GET_ASSEMBLER_HEADER
98 #include "ARMGenAsmMatcher.inc"
102 OperandMatchResultTy parseCoprocNumOperand(
103 SmallVectorImpl<MCParsedAsmOperand*>&);
104 OperandMatchResultTy parseCoprocRegOperand(
105 SmallVectorImpl<MCParsedAsmOperand*>&);
106 OperandMatchResultTy parseMemBarrierOptOperand(
107 SmallVectorImpl<MCParsedAsmOperand*>&);
108 OperandMatchResultTy parseProcIFlagsOperand(
109 SmallVectorImpl<MCParsedAsmOperand*>&);
110 OperandMatchResultTy parseMSRMaskOperand(
111 SmallVectorImpl<MCParsedAsmOperand*>&);
112 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
113 StringRef Op, int Low, int High);
114 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
115 return parsePKHImm(O, "lsl", 0, 31);
117 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
118 return parsePKHImm(O, "asr", 1, 32);
120 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
121 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
122 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
123 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
124 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
125 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
127 // Asm Match Converter Methods
128 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
129 const SmallVectorImpl<MCParsedAsmOperand*> &);
130 bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
131 const SmallVectorImpl<MCParsedAsmOperand*> &);
132 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
133 const SmallVectorImpl<MCParsedAsmOperand*> &);
134 bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
135 const SmallVectorImpl<MCParsedAsmOperand*> &);
136 bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
137 const SmallVectorImpl<MCParsedAsmOperand*> &);
138 bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
139 const SmallVectorImpl<MCParsedAsmOperand*> &);
140 bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
141 const SmallVectorImpl<MCParsedAsmOperand*> &);
142 bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
143 const SmallVectorImpl<MCParsedAsmOperand*> &);
144 bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
145 const SmallVectorImpl<MCParsedAsmOperand*> &);
146 bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
147 const SmallVectorImpl<MCParsedAsmOperand*> &);
148 bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
149 const SmallVectorImpl<MCParsedAsmOperand*> &);
150 bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
151 const SmallVectorImpl<MCParsedAsmOperand*> &);
153 bool validateInstruction(MCInst &Inst,
154 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
155 void processInstruction(MCInst &Inst,
156 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
157 bool shouldOmitCCOutOperand(StringRef Mnemonic,
158 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
161 enum ARMMatchResultTy {
162 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
167 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
168 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
169 MCAsmParserExtension::Initialize(_Parser);
171 // Initialize the set of available features.
172 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
175 // Implementation of the MCTargetAsmParser interface:
176 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
177 bool ParseInstruction(StringRef Name, SMLoc NameLoc,
178 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
179 bool ParseDirective(AsmToken DirectiveID);
181 unsigned checkTargetMatchPredicate(MCInst &Inst);
183 bool MatchAndEmitInstruction(SMLoc IDLoc,
184 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
187 } // end anonymous namespace
191 /// ARMOperand - Instances of this class represent a parsed ARM machine
193 class ARMOperand : public MCParsedAsmOperand {
217 SMLoc StartLoc, EndLoc;
218 SmallVector<unsigned, 8> Registers;
222 ARMCC::CondCodes Val;
234 ARM_PROC::IFlags Val;
254 /// Combined record for all forms of ARM address expressions.
257 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
259 const MCConstantExpr *OffsetImm; // Offset immediate value
260 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
261 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
262 unsigned ShiftImm; // shift for OffsetReg.
263 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
269 ARM_AM::ShiftOpc ShiftTy;
278 ARM_AM::ShiftOpc ShiftTy;
284 ARM_AM::ShiftOpc ShiftTy;
297 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
299 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
301 StartLoc = o.StartLoc;
315 case DPRRegisterList:
316 case SPRRegisterList:
317 Registers = o.Registers;
332 case PostIndexRegister:
333 PostIdxReg = o.PostIdxReg;
341 case ShifterImmediate:
342 ShifterImm = o.ShifterImm;
344 case ShiftedRegister:
345 RegShiftedReg = o.RegShiftedReg;
347 case ShiftedImmediate:
348 RegShiftedImm = o.RegShiftedImm;
350 case RotateImmediate:
353 case BitfieldDescriptor:
354 Bitfield = o.Bitfield;
359 /// getStartLoc - Get the location of the first token of this operand.
360 SMLoc getStartLoc() const { return StartLoc; }
361 /// getEndLoc - Get the location of the last token of this operand.
362 SMLoc getEndLoc() const { return EndLoc; }
364 ARMCC::CondCodes getCondCode() const {
365 assert(Kind == CondCode && "Invalid access!");
369 unsigned getCoproc() const {
370 assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
374 StringRef getToken() const {
375 assert(Kind == Token && "Invalid access!");
376 return StringRef(Tok.Data, Tok.Length);
379 unsigned getReg() const {
380 assert((Kind == Register || Kind == CCOut) && "Invalid access!");
384 const SmallVectorImpl<unsigned> &getRegList() const {
385 assert((Kind == RegisterList || Kind == DPRRegisterList ||
386 Kind == SPRRegisterList) && "Invalid access!");
390 const MCExpr *getImm() const {
391 assert(Kind == Immediate && "Invalid access!");
395 ARM_MB::MemBOpt getMemBarrierOpt() const {
396 assert(Kind == MemBarrierOpt && "Invalid access!");
400 ARM_PROC::IFlags getProcIFlags() const {
401 assert(Kind == ProcIFlags && "Invalid access!");
405 unsigned getMSRMask() const {
406 assert(Kind == MSRMask && "Invalid access!");
410 bool isCoprocNum() const { return Kind == CoprocNum; }
411 bool isCoprocReg() const { return Kind == CoprocReg; }
412 bool isCondCode() const { return Kind == CondCode; }
413 bool isCCOut() const { return Kind == CCOut; }
414 bool isImm() const { return Kind == Immediate; }
415 bool isImm0_1020s4() const {
416 if (Kind != Immediate)
418 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
419 if (!CE) return false;
420 int64_t Value = CE->getValue();
421 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
423 bool isImm0_508s4() const {
424 if (Kind != Immediate)
426 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
427 if (!CE) return false;
428 int64_t Value = CE->getValue();
429 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
431 bool isImm0_255() const {
432 if (Kind != Immediate)
434 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
435 if (!CE) return false;
436 int64_t Value = CE->getValue();
437 return Value >= 0 && Value < 256;
439 bool isImm0_7() const {
440 if (Kind != Immediate)
442 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
443 if (!CE) return false;
444 int64_t Value = CE->getValue();
445 return Value >= 0 && Value < 8;
447 bool isImm0_15() const {
448 if (Kind != Immediate)
450 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
451 if (!CE) return false;
452 int64_t Value = CE->getValue();
453 return Value >= 0 && Value < 16;
455 bool isImm0_31() const {
456 if (Kind != Immediate)
458 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
459 if (!CE) return false;
460 int64_t Value = CE->getValue();
461 return Value >= 0 && Value < 32;
463 bool isImm1_16() const {
464 if (Kind != Immediate)
466 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
467 if (!CE) return false;
468 int64_t Value = CE->getValue();
469 return Value > 0 && Value < 17;
471 bool isImm1_32() const {
472 if (Kind != Immediate)
474 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
475 if (!CE) return false;
476 int64_t Value = CE->getValue();
477 return Value > 0 && Value < 33;
479 bool isImm0_65535() const {
480 if (Kind != Immediate)
482 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
483 if (!CE) return false;
484 int64_t Value = CE->getValue();
485 return Value >= 0 && Value < 65536;
487 bool isImm0_65535Expr() const {
488 if (Kind != Immediate)
490 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
491 // If it's not a constant expression, it'll generate a fixup and be
493 if (!CE) return true;
494 int64_t Value = CE->getValue();
495 return Value >= 0 && Value < 65536;
497 bool isImm24bit() const {
498 if (Kind != Immediate)
500 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
501 if (!CE) return false;
502 int64_t Value = CE->getValue();
503 return Value >= 0 && Value <= 0xffffff;
505 bool isImmThumbSR() const {
506 if (Kind != Immediate)
508 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
509 if (!CE) return false;
510 int64_t Value = CE->getValue();
511 return Value > 0 && Value < 33;
513 bool isPKHLSLImm() const {
514 if (Kind != Immediate)
516 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
517 if (!CE) return false;
518 int64_t Value = CE->getValue();
519 return Value >= 0 && Value < 32;
521 bool isPKHASRImm() const {
522 if (Kind != Immediate)
524 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
525 if (!CE) return false;
526 int64_t Value = CE->getValue();
527 return Value > 0 && Value <= 32;
529 bool isARMSOImm() const {
530 if (Kind != Immediate)
532 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
533 if (!CE) return false;
534 int64_t Value = CE->getValue();
535 return ARM_AM::getSOImmVal(Value) != -1;
537 bool isT2SOImm() const {
538 if (Kind != Immediate)
540 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
541 if (!CE) return false;
542 int64_t Value = CE->getValue();
543 return ARM_AM::getT2SOImmVal(Value) != -1;
545 bool isSetEndImm() const {
546 if (Kind != Immediate)
548 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
549 if (!CE) return false;
550 int64_t Value = CE->getValue();
551 return Value == 1 || Value == 0;
553 bool isReg() const { return Kind == Register; }
554 bool isRegList() const { return Kind == RegisterList; }
555 bool isDPRRegList() const { return Kind == DPRRegisterList; }
556 bool isSPRRegList() const { return Kind == SPRRegisterList; }
557 bool isToken() const { return Kind == Token; }
558 bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
559 bool isMemory() const { return Kind == Memory; }
560 bool isShifterImm() const { return Kind == ShifterImmediate; }
561 bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
562 bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
563 bool isRotImm() const { return Kind == RotateImmediate; }
564 bool isBitfield() const { return Kind == BitfieldDescriptor; }
565 bool isPostIdxRegShifted() const { return Kind == PostIndexRegister; }
566 bool isPostIdxReg() const {
567 return Kind == PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
569 bool isMemNoOffset() const {
572 // No offset of any kind.
573 return Mem.OffsetRegNum == 0 && Mem.OffsetImm == 0;
575 bool isAddrMode2() const {
578 // Check for register offset.
579 if (Mem.OffsetRegNum) return true;
580 // Immediate offset in range [-4095, 4095].
581 if (!Mem.OffsetImm) return true;
582 int64_t Val = Mem.OffsetImm->getValue();
583 return Val > -4096 && Val < 4096;
585 bool isAM2OffsetImm() const {
586 if (Kind != Immediate)
588 // Immediate offset in range [-4095, 4095].
589 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
590 if (!CE) return false;
591 int64_t Val = CE->getValue();
592 return Val > -4096 && Val < 4096;
594 bool isAddrMode3() const {
597 // No shifts are legal for AM3.
598 if (Mem.ShiftType != ARM_AM::no_shift) return false;
599 // Check for register offset.
600 if (Mem.OffsetRegNum) return true;
601 // Immediate offset in range [-255, 255].
602 if (!Mem.OffsetImm) return true;
603 int64_t Val = Mem.OffsetImm->getValue();
604 return Val > -256 && Val < 256;
606 bool isAM3Offset() const {
607 if (Kind != Immediate && Kind != PostIndexRegister)
609 if (Kind == PostIndexRegister)
610 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
611 // Immediate offset in range [-255, 255].
612 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
613 if (!CE) return false;
614 int64_t Val = CE->getValue();
615 // Special case, #-0 is INT32_MIN.
616 return (Val > -256 && Val < 256) || Val == INT32_MIN;
618 bool isAddrMode5() const {
621 // Check for register offset.
622 if (Mem.OffsetRegNum) return false;
623 // Immediate offset in range [-1020, 1020] and a multiple of 4.
624 if (!Mem.OffsetImm) return true;
625 int64_t Val = Mem.OffsetImm->getValue();
626 return Val >= -1020 && Val <= 1020 && ((Val & 3) == 0);
628 bool isMemRegOffset() const {
629 if (Kind != Memory || !Mem.OffsetRegNum)
633 bool isMemThumbRR() const {
634 // Thumb reg+reg addressing is simple. Just two registers, a base and
635 // an offset. No shifts, negations or any other complicating factors.
636 if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative ||
637 Mem.ShiftType != ARM_AM::no_shift)
639 return isARMLowRegister(Mem.BaseRegNum) &&
640 (!Mem.OffsetRegNum || isARMLowRegister(Mem.OffsetRegNum));
642 bool isMemThumbRIs4() const {
643 if (Kind != Memory || Mem.OffsetRegNum != 0 ||
644 !isARMLowRegister(Mem.BaseRegNum))
646 // Immediate offset, multiple of 4 in range [0, 124].
647 if (!Mem.OffsetImm) return true;
648 int64_t Val = Mem.OffsetImm->getValue();
649 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
651 bool isMemThumbRIs2() const {
652 if (Kind != Memory || Mem.OffsetRegNum != 0 ||
653 !isARMLowRegister(Mem.BaseRegNum))
655 // Immediate offset, multiple of 4 in range [0, 62].
656 if (!Mem.OffsetImm) return true;
657 int64_t Val = Mem.OffsetImm->getValue();
658 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
660 bool isMemThumbRIs1() const {
661 if (Kind != Memory || Mem.OffsetRegNum != 0 ||
662 !isARMLowRegister(Mem.BaseRegNum))
664 // Immediate offset in range [0, 31].
665 if (!Mem.OffsetImm) return true;
666 int64_t Val = Mem.OffsetImm->getValue();
667 return Val >= 0 && Val <= 31;
669 bool isMemThumbSPI() const {
670 if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP)
672 // Immediate offset, multiple of 4 in range [0, 1020].
673 if (!Mem.OffsetImm) return true;
674 int64_t Val = Mem.OffsetImm->getValue();
675 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
677 bool isMemImm8Offset() const {
678 if (Kind != Memory || Mem.OffsetRegNum != 0)
680 // Immediate offset in range [-255, 255].
681 if (!Mem.OffsetImm) return true;
682 int64_t Val = Mem.OffsetImm->getValue();
683 return Val > -256 && Val < 256;
685 bool isMemImm12Offset() const {
686 // If we have an immediate that's not a constant, treat it as a label
687 // reference needing a fixup. If it is a constant, it's something else
689 if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
692 if (Kind != Memory || Mem.OffsetRegNum != 0)
694 // Immediate offset in range [-4095, 4095].
695 if (!Mem.OffsetImm) return true;
696 int64_t Val = Mem.OffsetImm->getValue();
697 return Val > -4096 && Val < 4096;
699 bool isPostIdxImm8() const {
700 if (Kind != Immediate)
702 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
703 if (!CE) return false;
704 int64_t Val = CE->getValue();
705 return Val > -256 && Val < 256;
708 bool isMSRMask() const { return Kind == MSRMask; }
709 bool isProcIFlags() const { return Kind == ProcIFlags; }
711 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
712 // Add as immediates when possible. Null MCExpr = 0.
714 Inst.addOperand(MCOperand::CreateImm(0));
715 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
716 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
718 Inst.addOperand(MCOperand::CreateExpr(Expr));
721 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
722 assert(N == 2 && "Invalid number of operands!");
723 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
724 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
725 Inst.addOperand(MCOperand::CreateReg(RegNum));
728 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
729 assert(N == 1 && "Invalid number of operands!");
730 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
733 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
734 assert(N == 1 && "Invalid number of operands!");
735 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
738 void addCCOutOperands(MCInst &Inst, unsigned N) const {
739 assert(N == 1 && "Invalid number of operands!");
740 Inst.addOperand(MCOperand::CreateReg(getReg()));
743 void addRegOperands(MCInst &Inst, unsigned N) const {
744 assert(N == 1 && "Invalid number of operands!");
745 Inst.addOperand(MCOperand::CreateReg(getReg()));
748 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
749 assert(N == 3 && "Invalid number of operands!");
750 assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
751 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
752 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
753 Inst.addOperand(MCOperand::CreateImm(
754 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
757 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
758 assert(N == 2 && "Invalid number of operands!");
759 assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
760 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
761 Inst.addOperand(MCOperand::CreateImm(
762 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
766 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
767 assert(N == 1 && "Invalid number of operands!");
768 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
772 void addRegListOperands(MCInst &Inst, unsigned N) const {
773 assert(N == 1 && "Invalid number of operands!");
774 const SmallVectorImpl<unsigned> &RegList = getRegList();
775 for (SmallVectorImpl<unsigned>::const_iterator
776 I = RegList.begin(), E = RegList.end(); I != E; ++I)
777 Inst.addOperand(MCOperand::CreateReg(*I));
780 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
781 addRegListOperands(Inst, N);
784 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
785 addRegListOperands(Inst, N);
788 void addRotImmOperands(MCInst &Inst, unsigned N) const {
789 assert(N == 1 && "Invalid number of operands!");
790 // Encoded as val>>3. The printer handles display as 8, 16, 24.
791 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
794 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
795 assert(N == 1 && "Invalid number of operands!");
796 // Munge the lsb/width into a bitfield mask.
797 unsigned lsb = Bitfield.LSB;
798 unsigned width = Bitfield.Width;
799 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
800 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
801 (32 - (lsb + width)));
802 Inst.addOperand(MCOperand::CreateImm(Mask));
805 void addImmOperands(MCInst &Inst, unsigned N) const {
806 assert(N == 1 && "Invalid number of operands!");
807 addExpr(Inst, getImm());
810 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
811 assert(N == 1 && "Invalid number of operands!");
812 // The immediate is scaled by four in the encoding and is stored
813 // in the MCInst as such. Lop off the low two bits here.
814 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
815 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
818 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
819 assert(N == 1 && "Invalid number of operands!");
820 // The immediate is scaled by four in the encoding and is stored
821 // in the MCInst as such. Lop off the low two bits here.
822 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
823 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
826 void addImm0_255Operands(MCInst &Inst, unsigned N) const {
827 assert(N == 1 && "Invalid number of operands!");
828 addExpr(Inst, getImm());
831 void addImm0_7Operands(MCInst &Inst, unsigned N) const {
832 assert(N == 1 && "Invalid number of operands!");
833 addExpr(Inst, getImm());
836 void addImm0_15Operands(MCInst &Inst, unsigned N) const {
837 assert(N == 1 && "Invalid number of operands!");
838 addExpr(Inst, getImm());
841 void addImm0_31Operands(MCInst &Inst, unsigned N) const {
842 assert(N == 1 && "Invalid number of operands!");
843 addExpr(Inst, getImm());
846 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
847 assert(N == 1 && "Invalid number of operands!");
848 // The constant encodes as the immediate-1, and we store in the instruction
849 // the bits as encoded, so subtract off one here.
850 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
851 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
854 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
855 assert(N == 1 && "Invalid number of operands!");
856 // The constant encodes as the immediate-1, and we store in the instruction
857 // the bits as encoded, so subtract off one here.
858 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
859 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
862 void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
863 assert(N == 1 && "Invalid number of operands!");
864 addExpr(Inst, getImm());
867 void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
868 assert(N == 1 && "Invalid number of operands!");
869 addExpr(Inst, getImm());
872 void addImm24bitOperands(MCInst &Inst, unsigned N) const {
873 assert(N == 1 && "Invalid number of operands!");
874 addExpr(Inst, getImm());
877 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
878 assert(N == 1 && "Invalid number of operands!");
879 // The constant encodes as the immediate, except for 32, which encodes as
881 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
882 unsigned Imm = CE->getValue();
883 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
886 void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
887 assert(N == 1 && "Invalid number of operands!");
888 addExpr(Inst, getImm());
891 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
892 assert(N == 1 && "Invalid number of operands!");
893 // An ASR value of 32 encodes as 0, so that's how we want to add it to
894 // the instruction as well.
895 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
896 int Val = CE->getValue();
897 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
900 void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
901 assert(N == 1 && "Invalid number of operands!");
902 addExpr(Inst, getImm());
905 void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
906 assert(N == 1 && "Invalid number of operands!");
907 addExpr(Inst, getImm());
910 void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
911 assert(N == 1 && "Invalid number of operands!");
912 addExpr(Inst, getImm());
915 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
916 assert(N == 1 && "Invalid number of operands!");
917 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
920 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
921 assert(N == 1 && "Invalid number of operands!");
922 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
925 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
926 assert(N == 3 && "Invalid number of operands!");
927 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
928 if (!Mem.OffsetRegNum) {
929 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
930 // Special case for #-0
931 if (Val == INT32_MIN) Val = 0;
932 if (Val < 0) Val = -Val;
933 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
935 // For register offset, we encode the shift type and negation flag
937 Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
938 Mem.ShiftImm, Mem.ShiftType);
940 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
941 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
942 Inst.addOperand(MCOperand::CreateImm(Val));
945 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
946 assert(N == 2 && "Invalid number of operands!");
947 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
948 assert(CE && "non-constant AM2OffsetImm operand!");
949 int32_t Val = CE->getValue();
950 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
951 // Special case for #-0
952 if (Val == INT32_MIN) Val = 0;
953 if (Val < 0) Val = -Val;
954 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
955 Inst.addOperand(MCOperand::CreateReg(0));
956 Inst.addOperand(MCOperand::CreateImm(Val));
959 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
960 assert(N == 3 && "Invalid number of operands!");
961 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
962 if (!Mem.OffsetRegNum) {
963 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
964 // Special case for #-0
965 if (Val == INT32_MIN) Val = 0;
966 if (Val < 0) Val = -Val;
967 Val = ARM_AM::getAM3Opc(AddSub, Val);
969 // For register offset, we encode the shift type and negation flag
971 Val = ARM_AM::getAM3Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
973 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
974 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
975 Inst.addOperand(MCOperand::CreateImm(Val));
978 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
979 assert(N == 2 && "Invalid number of operands!");
980 if (Kind == PostIndexRegister) {
982 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
983 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
984 Inst.addOperand(MCOperand::CreateImm(Val));
989 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
990 int32_t Val = CE->getValue();
991 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
992 // Special case for #-0
993 if (Val == INT32_MIN) Val = 0;
994 if (Val < 0) Val = -Val;
995 Val = ARM_AM::getAM3Opc(AddSub, Val);
996 Inst.addOperand(MCOperand::CreateReg(0));
997 Inst.addOperand(MCOperand::CreateImm(Val));
1000 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1001 assert(N == 2 && "Invalid number of operands!");
1002 // The lower two bits are always zero and as such are not encoded.
1003 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0;
1004 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1005 // Special case for #-0
1006 if (Val == INT32_MIN) Val = 0;
1007 if (Val < 0) Val = -Val;
1008 Val = ARM_AM::getAM5Opc(AddSub, Val);
1009 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1010 Inst.addOperand(MCOperand::CreateImm(Val));
1013 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1014 assert(N == 2 && "Invalid number of operands!");
1015 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1016 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1017 Inst.addOperand(MCOperand::CreateImm(Val));
1020 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1021 assert(N == 2 && "Invalid number of operands!");
1022 // If this is an immediate, it's a label reference.
1023 if (Kind == Immediate) {
1024 addExpr(Inst, getImm());
1025 Inst.addOperand(MCOperand::CreateImm(0));
1029 // Otherwise, it's a normal memory reg+offset.
1030 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1031 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1032 Inst.addOperand(MCOperand::CreateImm(Val));
1035 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1036 assert(N == 3 && "Invalid number of operands!");
1037 unsigned Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
1038 Mem.ShiftImm, Mem.ShiftType);
1039 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1040 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1041 Inst.addOperand(MCOperand::CreateImm(Val));
1044 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1045 assert(N == 2 && "Invalid number of operands!");
1046 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1047 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1050 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1051 assert(N == 2 && "Invalid number of operands!");
1052 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1053 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1054 Inst.addOperand(MCOperand::CreateImm(Val));
1057 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1058 assert(N == 2 && "Invalid number of operands!");
1059 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 2) : 0;
1060 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1061 Inst.addOperand(MCOperand::CreateImm(Val));
1064 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1065 assert(N == 2 && "Invalid number of operands!");
1066 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue()) : 0;
1067 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1068 Inst.addOperand(MCOperand::CreateImm(Val));
1071 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1072 assert(N == 2 && "Invalid number of operands!");
1073 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1074 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1075 Inst.addOperand(MCOperand::CreateImm(Val));
1078 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1079 assert(N == 1 && "Invalid number of operands!");
1080 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1081 assert(CE && "non-constant post-idx-imm8 operand!");
1082 int Imm = CE->getValue();
1083 bool isAdd = Imm >= 0;
1084 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1085 Inst.addOperand(MCOperand::CreateImm(Imm));
1088 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1089 assert(N == 2 && "Invalid number of operands!");
1090 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1091 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1094 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1095 assert(N == 2 && "Invalid number of operands!");
1096 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1097 // The sign, shift type, and shift amount are encoded in a single operand
1098 // using the AM2 encoding helpers.
1099 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1100 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1101 PostIdxReg.ShiftTy);
1102 Inst.addOperand(MCOperand::CreateImm(Imm));
1105 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1106 assert(N == 1 && "Invalid number of operands!");
1107 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1110 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1111 assert(N == 1 && "Invalid number of operands!");
1112 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1115 virtual void print(raw_ostream &OS) const;
1117 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1118 ARMOperand *Op = new ARMOperand(CondCode);
1125 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1126 ARMOperand *Op = new ARMOperand(CoprocNum);
1127 Op->Cop.Val = CopVal;
1133 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1134 ARMOperand *Op = new ARMOperand(CoprocReg);
1135 Op->Cop.Val = CopVal;
1141 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1142 ARMOperand *Op = new ARMOperand(CCOut);
1143 Op->Reg.RegNum = RegNum;
1149 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1150 ARMOperand *Op = new ARMOperand(Token);
1151 Op->Tok.Data = Str.data();
1152 Op->Tok.Length = Str.size();
1158 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1159 ARMOperand *Op = new ARMOperand(Register);
1160 Op->Reg.RegNum = RegNum;
1166 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1171 ARMOperand *Op = new ARMOperand(ShiftedRegister);
1172 Op->RegShiftedReg.ShiftTy = ShTy;
1173 Op->RegShiftedReg.SrcReg = SrcReg;
1174 Op->RegShiftedReg.ShiftReg = ShiftReg;
1175 Op->RegShiftedReg.ShiftImm = ShiftImm;
1181 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1185 ARMOperand *Op = new ARMOperand(ShiftedImmediate);
1186 Op->RegShiftedImm.ShiftTy = ShTy;
1187 Op->RegShiftedImm.SrcReg = SrcReg;
1188 Op->RegShiftedImm.ShiftImm = ShiftImm;
1194 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1196 ARMOperand *Op = new ARMOperand(ShifterImmediate);
1197 Op->ShifterImm.isASR = isASR;
1198 Op->ShifterImm.Imm = Imm;
1204 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1205 ARMOperand *Op = new ARMOperand(RotateImmediate);
1206 Op->RotImm.Imm = Imm;
1212 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1214 ARMOperand *Op = new ARMOperand(BitfieldDescriptor);
1215 Op->Bitfield.LSB = LSB;
1216 Op->Bitfield.Width = Width;
1223 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1224 SMLoc StartLoc, SMLoc EndLoc) {
1225 KindTy Kind = RegisterList;
1227 if (llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].
1228 contains(Regs.front().first))
1229 Kind = DPRRegisterList;
1230 else if (llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].
1231 contains(Regs.front().first))
1232 Kind = SPRRegisterList;
1234 ARMOperand *Op = new ARMOperand(Kind);
1235 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1236 I = Regs.begin(), E = Regs.end(); I != E; ++I)
1237 Op->Registers.push_back(I->first);
1238 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1239 Op->StartLoc = StartLoc;
1240 Op->EndLoc = EndLoc;
1244 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1245 ARMOperand *Op = new ARMOperand(Immediate);
1252 static ARMOperand *CreateMem(unsigned BaseRegNum,
1253 const MCConstantExpr *OffsetImm,
1254 unsigned OffsetRegNum,
1255 ARM_AM::ShiftOpc ShiftType,
1259 ARMOperand *Op = new ARMOperand(Memory);
1260 Op->Mem.BaseRegNum = BaseRegNum;
1261 Op->Mem.OffsetImm = OffsetImm;
1262 Op->Mem.OffsetRegNum = OffsetRegNum;
1263 Op->Mem.ShiftType = ShiftType;
1264 Op->Mem.ShiftImm = ShiftImm;
1265 Op->Mem.isNegative = isNegative;
1271 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1272 ARM_AM::ShiftOpc ShiftTy,
1275 ARMOperand *Op = new ARMOperand(PostIndexRegister);
1276 Op->PostIdxReg.RegNum = RegNum;
1277 Op->PostIdxReg.isAdd = isAdd;
1278 Op->PostIdxReg.ShiftTy = ShiftTy;
1279 Op->PostIdxReg.ShiftImm = ShiftImm;
1285 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1286 ARMOperand *Op = new ARMOperand(MemBarrierOpt);
1287 Op->MBOpt.Val = Opt;
1293 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1294 ARMOperand *Op = new ARMOperand(ProcIFlags);
1295 Op->IFlags.Val = IFlags;
1301 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1302 ARMOperand *Op = new ARMOperand(MSRMask);
1303 Op->MMask.Val = MMask;
1310 } // end anonymous namespace.
1312 void ARMOperand::print(raw_ostream &OS) const {
1315 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1318 OS << "<ccout " << getReg() << ">";
1321 OS << "<coprocessor number: " << getCoproc() << ">";
1324 OS << "<coprocessor register: " << getCoproc() << ">";
1327 OS << "<mask: " << getMSRMask() << ">";
1330 getImm()->print(OS);
1333 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1337 << " base:" << Mem.BaseRegNum;
1340 case PostIndexRegister:
1341 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
1342 << PostIdxReg.RegNum;
1343 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1344 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1345 << PostIdxReg.ShiftImm;
1349 OS << "<ARM_PROC::";
1350 unsigned IFlags = getProcIFlags();
1351 for (int i=2; i >= 0; --i)
1352 if (IFlags & (1 << i))
1353 OS << ARM_PROC::IFlagsToString(1 << i);
1358 OS << "<register " << getReg() << ">";
1360 case ShifterImmediate:
1361 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1362 << " #" << ShifterImm.Imm << ">";
1364 case ShiftedRegister:
1365 OS << "<so_reg_reg "
1366 << RegShiftedReg.SrcReg
1367 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1368 << ", " << RegShiftedReg.ShiftReg << ", "
1369 << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1372 case ShiftedImmediate:
1373 OS << "<so_reg_imm "
1374 << RegShiftedImm.SrcReg
1375 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1376 << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
1379 case RotateImmediate:
1380 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
1382 case BitfieldDescriptor:
1383 OS << "<bitfield " << "lsb: " << Bitfield.LSB
1384 << ", width: " << Bitfield.Width << ">";
1387 case DPRRegisterList:
1388 case SPRRegisterList: {
1389 OS << "<register_list ";
1391 const SmallVectorImpl<unsigned> &RegList = getRegList();
1392 for (SmallVectorImpl<unsigned>::const_iterator
1393 I = RegList.begin(), E = RegList.end(); I != E; ) {
1395 if (++I < E) OS << ", ";
1402 OS << "'" << getToken() << "'";
1407 /// @name Auto-generated Match Functions
1410 static unsigned MatchRegisterName(StringRef Name);
1414 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
1415 SMLoc &StartLoc, SMLoc &EndLoc) {
1416 RegNo = tryParseRegister();
1418 return (RegNo == (unsigned)-1);
1421 /// Try to parse a register name. The token must be an Identifier when called,
1422 /// and if it is a register name the token is eaten and the register number is
1423 /// returned. Otherwise return -1.
1425 int ARMAsmParser::tryParseRegister() {
1426 const AsmToken &Tok = Parser.getTok();
1427 if (Tok.isNot(AsmToken::Identifier)) return -1;
1429 // FIXME: Validate register for the current architecture; we have to do
1430 // validation later, so maybe there is no need for this here.
1431 std::string upperCase = Tok.getString().str();
1432 std::string lowerCase = LowercaseString(upperCase);
1433 unsigned RegNum = MatchRegisterName(lowerCase);
1435 RegNum = StringSwitch<unsigned>(lowerCase)
1436 .Case("r13", ARM::SP)
1437 .Case("r14", ARM::LR)
1438 .Case("r15", ARM::PC)
1439 .Case("ip", ARM::R12)
1442 if (!RegNum) return -1;
1444 Parser.Lex(); // Eat identifier token.
1448 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
1449 // If a recoverable error occurs, return 1. If an irrecoverable error
1450 // occurs, return -1. An irrecoverable error is one where tokens have been
1451 // consumed in the process of trying to parse the shifter (i.e., when it is
1452 // indeed a shifter operand, but malformed).
1453 int ARMAsmParser::tryParseShiftRegister(
1454 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1455 SMLoc S = Parser.getTok().getLoc();
1456 const AsmToken &Tok = Parser.getTok();
1457 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1459 std::string upperCase = Tok.getString().str();
1460 std::string lowerCase = LowercaseString(upperCase);
1461 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
1462 .Case("lsl", ARM_AM::lsl)
1463 .Case("lsr", ARM_AM::lsr)
1464 .Case("asr", ARM_AM::asr)
1465 .Case("ror", ARM_AM::ror)
1466 .Case("rrx", ARM_AM::rrx)
1467 .Default(ARM_AM::no_shift);
1469 if (ShiftTy == ARM_AM::no_shift)
1472 Parser.Lex(); // Eat the operator.
1474 // The source register for the shift has already been added to the
1475 // operand list, so we need to pop it off and combine it into the shifted
1476 // register operand instead.
1477 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
1478 if (!PrevOp->isReg())
1479 return Error(PrevOp->getStartLoc(), "shift must be of a register");
1480 int SrcReg = PrevOp->getReg();
1483 if (ShiftTy == ARM_AM::rrx) {
1484 // RRX Doesn't have an explicit shift amount. The encoder expects
1485 // the shift register to be the same as the source register. Seems odd,
1489 // Figure out if this is shifted by a constant or a register (for non-RRX).
1490 if (Parser.getTok().is(AsmToken::Hash)) {
1491 Parser.Lex(); // Eat hash.
1492 SMLoc ImmLoc = Parser.getTok().getLoc();
1493 const MCExpr *ShiftExpr = 0;
1494 if (getParser().ParseExpression(ShiftExpr)) {
1495 Error(ImmLoc, "invalid immediate shift value");
1498 // The expression must be evaluatable as an immediate.
1499 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
1501 Error(ImmLoc, "invalid immediate shift value");
1504 // Range check the immediate.
1505 // lsl, ror: 0 <= imm <= 31
1506 // lsr, asr: 0 <= imm <= 32
1507 Imm = CE->getValue();
1509 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
1510 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
1511 Error(ImmLoc, "immediate shift value out of range");
1514 } else if (Parser.getTok().is(AsmToken::Identifier)) {
1515 ShiftReg = tryParseRegister();
1516 SMLoc L = Parser.getTok().getLoc();
1517 if (ShiftReg == -1) {
1518 Error (L, "expected immediate or register in shift operand");
1522 Error (Parser.getTok().getLoc(),
1523 "expected immediate or register in shift operand");
1528 if (ShiftReg && ShiftTy != ARM_AM::rrx)
1529 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
1531 S, Parser.getTok().getLoc()));
1533 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
1534 S, Parser.getTok().getLoc()));
1540 /// Try to parse a register name. The token must be an Identifier when called.
1541 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
1542 /// if there is a "writeback". 'true' if it's not a register.
1544 /// TODO this is likely to change to allow different register types and or to
1545 /// parse for a specific register type.
1547 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1548 SMLoc S = Parser.getTok().getLoc();
1549 int RegNo = tryParseRegister();
1553 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1555 const AsmToken &ExclaimTok = Parser.getTok();
1556 if (ExclaimTok.is(AsmToken::Exclaim)) {
1557 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
1558 ExclaimTok.getLoc()));
1559 Parser.Lex(); // Eat exclaim token
1565 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
1566 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
1568 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
1569 // Use the same layout as the tablegen'erated register name matcher. Ugly,
1571 switch (Name.size()) {
1574 if (Name[0] != CoprocOp)
1591 if (Name[0] != CoprocOp || Name[1] != '1')
1595 case '0': return 10;
1596 case '1': return 11;
1597 case '2': return 12;
1598 case '3': return 13;
1599 case '4': return 14;
1600 case '5': return 15;
1608 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
1609 /// token must be an Identifier when called, and if it is a coprocessor
1610 /// number, the token is eaten and the operand is added to the operand list.
1611 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1612 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1613 SMLoc S = Parser.getTok().getLoc();
1614 const AsmToken &Tok = Parser.getTok();
1615 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1617 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
1619 return MatchOperand_NoMatch;
1621 Parser.Lex(); // Eat identifier token.
1622 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
1623 return MatchOperand_Success;
1626 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
1627 /// token must be an Identifier when called, and if it is a coprocessor
1628 /// number, the token is eaten and the operand is added to the operand list.
1629 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1630 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1631 SMLoc S = Parser.getTok().getLoc();
1632 const AsmToken &Tok = Parser.getTok();
1633 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1635 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
1637 return MatchOperand_NoMatch;
1639 Parser.Lex(); // Eat identifier token.
1640 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
1641 return MatchOperand_Success;
1644 /// Parse a register list, return it if successful else return null. The first
1645 /// token must be a '{' when called.
1647 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1648 assert(Parser.getTok().is(AsmToken::LCurly) &&
1649 "Token is not a Left Curly Brace");
1650 SMLoc S = Parser.getTok().getLoc();
1652 // Read the rest of the registers in the list.
1653 unsigned PrevRegNum = 0;
1654 SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
1657 bool IsRange = Parser.getTok().is(AsmToken::Minus);
1658 Parser.Lex(); // Eat non-identifier token.
1660 const AsmToken &RegTok = Parser.getTok();
1661 SMLoc RegLoc = RegTok.getLoc();
1662 if (RegTok.isNot(AsmToken::Identifier)) {
1663 Error(RegLoc, "register expected");
1667 int RegNum = tryParseRegister();
1669 Error(RegLoc, "register expected");
1674 int Reg = PrevRegNum;
1677 Registers.push_back(std::make_pair(Reg, RegLoc));
1678 } while (Reg != RegNum);
1680 Registers.push_back(std::make_pair(RegNum, RegLoc));
1683 PrevRegNum = RegNum;
1684 } while (Parser.getTok().is(AsmToken::Comma) ||
1685 Parser.getTok().is(AsmToken::Minus));
1687 // Process the right curly brace of the list.
1688 const AsmToken &RCurlyTok = Parser.getTok();
1689 if (RCurlyTok.isNot(AsmToken::RCurly)) {
1690 Error(RCurlyTok.getLoc(), "'}' expected");
1694 SMLoc E = RCurlyTok.getLoc();
1695 Parser.Lex(); // Eat right curly brace token.
1697 // Verify the register list.
1698 bool EmittedWarning = false;
1699 unsigned HighRegNum = 0;
1700 BitVector RegMap(32);
1701 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
1702 const std::pair<unsigned, SMLoc> &RegInfo = Registers[i];
1703 unsigned Reg = getARMRegisterNumbering(RegInfo.first);
1706 Error(RegInfo.second, "register duplicated in register list");
1710 if (!EmittedWarning && Reg < HighRegNum)
1711 Warning(RegInfo.second,
1712 "register not in ascending order in register list");
1715 HighRegNum = std::max(Reg, HighRegNum);
1718 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
1722 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
1723 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1724 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1725 SMLoc S = Parser.getTok().getLoc();
1726 const AsmToken &Tok = Parser.getTok();
1727 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1728 StringRef OptStr = Tok.getString();
1730 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
1731 .Case("sy", ARM_MB::SY)
1732 .Case("st", ARM_MB::ST)
1733 .Case("sh", ARM_MB::ISH)
1734 .Case("ish", ARM_MB::ISH)
1735 .Case("shst", ARM_MB::ISHST)
1736 .Case("ishst", ARM_MB::ISHST)
1737 .Case("nsh", ARM_MB::NSH)
1738 .Case("un", ARM_MB::NSH)
1739 .Case("nshst", ARM_MB::NSHST)
1740 .Case("unst", ARM_MB::NSHST)
1741 .Case("osh", ARM_MB::OSH)
1742 .Case("oshst", ARM_MB::OSHST)
1746 return MatchOperand_NoMatch;
1748 Parser.Lex(); // Eat identifier token.
1749 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
1750 return MatchOperand_Success;
1753 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
1754 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1755 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1756 SMLoc S = Parser.getTok().getLoc();
1757 const AsmToken &Tok = Parser.getTok();
1758 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1759 StringRef IFlagsStr = Tok.getString();
1761 unsigned IFlags = 0;
1762 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
1763 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
1764 .Case("a", ARM_PROC::A)
1765 .Case("i", ARM_PROC::I)
1766 .Case("f", ARM_PROC::F)
1769 // If some specific iflag is already set, it means that some letter is
1770 // present more than once, this is not acceptable.
1771 if (Flag == ~0U || (IFlags & Flag))
1772 return MatchOperand_NoMatch;
1777 Parser.Lex(); // Eat identifier token.
1778 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
1779 return MatchOperand_Success;
1782 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
1783 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1784 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1785 SMLoc S = Parser.getTok().getLoc();
1786 const AsmToken &Tok = Parser.getTok();
1787 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1788 StringRef Mask = Tok.getString();
1790 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
1791 size_t Start = 0, Next = Mask.find('_');
1792 StringRef Flags = "";
1793 std::string SpecReg = LowercaseString(Mask.slice(Start, Next));
1794 if (Next != StringRef::npos)
1795 Flags = Mask.slice(Next+1, Mask.size());
1797 // FlagsVal contains the complete mask:
1799 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1800 unsigned FlagsVal = 0;
1802 if (SpecReg == "apsr") {
1803 FlagsVal = StringSwitch<unsigned>(Flags)
1804 .Case("nzcvq", 0x8) // same as CPSR_f
1805 .Case("g", 0x4) // same as CPSR_s
1806 .Case("nzcvqg", 0xc) // same as CPSR_fs
1809 if (FlagsVal == ~0U) {
1811 return MatchOperand_NoMatch;
1813 FlagsVal = 0; // No flag
1815 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
1816 if (Flags == "all") // cpsr_all is an alias for cpsr_fc
1818 for (int i = 0, e = Flags.size(); i != e; ++i) {
1819 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
1826 // If some specific flag is already set, it means that some letter is
1827 // present more than once, this is not acceptable.
1828 if (FlagsVal == ~0U || (FlagsVal & Flag))
1829 return MatchOperand_NoMatch;
1832 } else // No match for special register.
1833 return MatchOperand_NoMatch;
1835 // Special register without flags are equivalent to "fc" flags.
1839 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1840 if (SpecReg == "spsr")
1843 Parser.Lex(); // Eat identifier token.
1844 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
1845 return MatchOperand_Success;
1848 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1849 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
1850 int Low, int High) {
1851 const AsmToken &Tok = Parser.getTok();
1852 if (Tok.isNot(AsmToken::Identifier)) {
1853 Error(Parser.getTok().getLoc(), Op + " operand expected.");
1854 return MatchOperand_ParseFail;
1856 StringRef ShiftName = Tok.getString();
1857 std::string LowerOp = LowercaseString(Op);
1858 std::string UpperOp = UppercaseString(Op);
1859 if (ShiftName != LowerOp && ShiftName != UpperOp) {
1860 Error(Parser.getTok().getLoc(), Op + " operand expected.");
1861 return MatchOperand_ParseFail;
1863 Parser.Lex(); // Eat shift type token.
1865 // There must be a '#' and a shift amount.
1866 if (Parser.getTok().isNot(AsmToken::Hash)) {
1867 Error(Parser.getTok().getLoc(), "'#' expected");
1868 return MatchOperand_ParseFail;
1870 Parser.Lex(); // Eat hash token.
1872 const MCExpr *ShiftAmount;
1873 SMLoc Loc = Parser.getTok().getLoc();
1874 if (getParser().ParseExpression(ShiftAmount)) {
1875 Error(Loc, "illegal expression");
1876 return MatchOperand_ParseFail;
1878 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1880 Error(Loc, "constant expression expected");
1881 return MatchOperand_ParseFail;
1883 int Val = CE->getValue();
1884 if (Val < Low || Val > High) {
1885 Error(Loc, "immediate value out of range");
1886 return MatchOperand_ParseFail;
1889 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
1891 return MatchOperand_Success;
1894 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1895 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1896 const AsmToken &Tok = Parser.getTok();
1897 SMLoc S = Tok.getLoc();
1898 if (Tok.isNot(AsmToken::Identifier)) {
1899 Error(Tok.getLoc(), "'be' or 'le' operand expected");
1900 return MatchOperand_ParseFail;
1902 int Val = StringSwitch<int>(Tok.getString())
1906 Parser.Lex(); // Eat the token.
1909 Error(Tok.getLoc(), "'be' or 'le' operand expected");
1910 return MatchOperand_ParseFail;
1912 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
1914 S, Parser.getTok().getLoc()));
1915 return MatchOperand_Success;
1918 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
1919 /// instructions. Legal values are:
1920 /// lsl #n 'n' in [0,31]
1921 /// asr #n 'n' in [1,32]
1922 /// n == 32 encoded as n == 0.
1923 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1924 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1925 const AsmToken &Tok = Parser.getTok();
1926 SMLoc S = Tok.getLoc();
1927 if (Tok.isNot(AsmToken::Identifier)) {
1928 Error(S, "shift operator 'asr' or 'lsl' expected");
1929 return MatchOperand_ParseFail;
1931 StringRef ShiftName = Tok.getString();
1933 if (ShiftName == "lsl" || ShiftName == "LSL")
1935 else if (ShiftName == "asr" || ShiftName == "ASR")
1938 Error(S, "shift operator 'asr' or 'lsl' expected");
1939 return MatchOperand_ParseFail;
1941 Parser.Lex(); // Eat the operator.
1943 // A '#' and a shift amount.
1944 if (Parser.getTok().isNot(AsmToken::Hash)) {
1945 Error(Parser.getTok().getLoc(), "'#' expected");
1946 return MatchOperand_ParseFail;
1948 Parser.Lex(); // Eat hash token.
1950 const MCExpr *ShiftAmount;
1951 SMLoc E = Parser.getTok().getLoc();
1952 if (getParser().ParseExpression(ShiftAmount)) {
1953 Error(E, "malformed shift expression");
1954 return MatchOperand_ParseFail;
1956 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1958 Error(E, "shift amount must be an immediate");
1959 return MatchOperand_ParseFail;
1962 int64_t Val = CE->getValue();
1964 // Shift amount must be in [1,32]
1965 if (Val < 1 || Val > 32) {
1966 Error(E, "'asr' shift amount must be in range [1,32]");
1967 return MatchOperand_ParseFail;
1969 // asr #32 encoded as asr #0.
1970 if (Val == 32) Val = 0;
1972 // Shift amount must be in [1,32]
1973 if (Val < 0 || Val > 31) {
1974 Error(E, "'lsr' shift amount must be in range [0,31]");
1975 return MatchOperand_ParseFail;
1979 E = Parser.getTok().getLoc();
1980 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
1982 return MatchOperand_Success;
1985 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
1986 /// of instructions. Legal values are:
1987 /// ror #n 'n' in {0, 8, 16, 24}
1988 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1989 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1990 const AsmToken &Tok = Parser.getTok();
1991 SMLoc S = Tok.getLoc();
1992 if (Tok.isNot(AsmToken::Identifier)) {
1993 Error(S, "rotate operator 'ror' expected");
1994 return MatchOperand_ParseFail;
1996 StringRef ShiftName = Tok.getString();
1997 if (ShiftName != "ror" && ShiftName != "ROR") {
1998 Error(S, "rotate operator 'ror' expected");
1999 return MatchOperand_ParseFail;
2001 Parser.Lex(); // Eat the operator.
2003 // A '#' and a rotate amount.
2004 if (Parser.getTok().isNot(AsmToken::Hash)) {
2005 Error(Parser.getTok().getLoc(), "'#' expected");
2006 return MatchOperand_ParseFail;
2008 Parser.Lex(); // Eat hash token.
2010 const MCExpr *ShiftAmount;
2011 SMLoc E = Parser.getTok().getLoc();
2012 if (getParser().ParseExpression(ShiftAmount)) {
2013 Error(E, "malformed rotate expression");
2014 return MatchOperand_ParseFail;
2016 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2018 Error(E, "rotate amount must be an immediate");
2019 return MatchOperand_ParseFail;
2022 int64_t Val = CE->getValue();
2023 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
2024 // normally, zero is represented in asm by omitting the rotate operand
2026 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
2027 Error(E, "'ror' rotate amount must be 8, 16, or 24");
2028 return MatchOperand_ParseFail;
2031 E = Parser.getTok().getLoc();
2032 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
2034 return MatchOperand_Success;
2037 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2038 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2039 SMLoc S = Parser.getTok().getLoc();
2040 // The bitfield descriptor is really two operands, the LSB and the width.
2041 if (Parser.getTok().isNot(AsmToken::Hash)) {
2042 Error(Parser.getTok().getLoc(), "'#' expected");
2043 return MatchOperand_ParseFail;
2045 Parser.Lex(); // Eat hash token.
2047 const MCExpr *LSBExpr;
2048 SMLoc E = Parser.getTok().getLoc();
2049 if (getParser().ParseExpression(LSBExpr)) {
2050 Error(E, "malformed immediate expression");
2051 return MatchOperand_ParseFail;
2053 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
2055 Error(E, "'lsb' operand must be an immediate");
2056 return MatchOperand_ParseFail;
2059 int64_t LSB = CE->getValue();
2060 // The LSB must be in the range [0,31]
2061 if (LSB < 0 || LSB > 31) {
2062 Error(E, "'lsb' operand must be in the range [0,31]");
2063 return MatchOperand_ParseFail;
2065 E = Parser.getTok().getLoc();
2067 // Expect another immediate operand.
2068 if (Parser.getTok().isNot(AsmToken::Comma)) {
2069 Error(Parser.getTok().getLoc(), "too few operands");
2070 return MatchOperand_ParseFail;
2072 Parser.Lex(); // Eat hash token.
2073 if (Parser.getTok().isNot(AsmToken::Hash)) {
2074 Error(Parser.getTok().getLoc(), "'#' expected");
2075 return MatchOperand_ParseFail;
2077 Parser.Lex(); // Eat hash token.
2079 const MCExpr *WidthExpr;
2080 if (getParser().ParseExpression(WidthExpr)) {
2081 Error(E, "malformed immediate expression");
2082 return MatchOperand_ParseFail;
2084 CE = dyn_cast<MCConstantExpr>(WidthExpr);
2086 Error(E, "'width' operand must be an immediate");
2087 return MatchOperand_ParseFail;
2090 int64_t Width = CE->getValue();
2091 // The LSB must be in the range [1,32-lsb]
2092 if (Width < 1 || Width > 32 - LSB) {
2093 Error(E, "'width' operand must be in the range [1,32-lsb]");
2094 return MatchOperand_ParseFail;
2096 E = Parser.getTok().getLoc();
2098 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
2100 return MatchOperand_Success;
2103 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2104 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2105 // Check for a post-index addressing register operand. Specifically:
2106 // postidx_reg := '+' register {, shift}
2107 // | '-' register {, shift}
2108 // | register {, shift}
2110 // This method must return MatchOperand_NoMatch without consuming any tokens
2111 // in the case where there is no match, as other alternatives take other
2113 AsmToken Tok = Parser.getTok();
2114 SMLoc S = Tok.getLoc();
2115 bool haveEaten = false;
2118 if (Tok.is(AsmToken::Plus)) {
2119 Parser.Lex(); // Eat the '+' token.
2121 } else if (Tok.is(AsmToken::Minus)) {
2122 Parser.Lex(); // Eat the '-' token.
2126 if (Parser.getTok().is(AsmToken::Identifier))
2127 Reg = tryParseRegister();
2130 return MatchOperand_NoMatch;
2131 Error(Parser.getTok().getLoc(), "register expected");
2132 return MatchOperand_ParseFail;
2134 SMLoc E = Parser.getTok().getLoc();
2136 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
2137 unsigned ShiftImm = 0;
2138 if (Parser.getTok().is(AsmToken::Comma)) {
2139 Parser.Lex(); // Eat the ','.
2140 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
2141 return MatchOperand_ParseFail;
2144 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
2147 return MatchOperand_Success;
2150 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2151 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2152 // Check for a post-index addressing register operand. Specifically:
2153 // am3offset := '+' register
2160 // This method must return MatchOperand_NoMatch without consuming any tokens
2161 // in the case where there is no match, as other alternatives take other
2163 AsmToken Tok = Parser.getTok();
2164 SMLoc S = Tok.getLoc();
2166 // Do immediates first, as we always parse those if we have a '#'.
2167 if (Parser.getTok().is(AsmToken::Hash)) {
2168 Parser.Lex(); // Eat the '#'.
2169 // Explicitly look for a '-', as we need to encode negative zero
2171 bool isNegative = Parser.getTok().is(AsmToken::Minus);
2172 const MCExpr *Offset;
2173 if (getParser().ParseExpression(Offset))
2174 return MatchOperand_ParseFail;
2175 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2177 Error(S, "constant expression expected");
2178 return MatchOperand_ParseFail;
2180 SMLoc E = Tok.getLoc();
2181 // Negative zero is encoded as the flag value INT32_MIN.
2182 int32_t Val = CE->getValue();
2183 if (isNegative && Val == 0)
2187 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
2189 return MatchOperand_Success;
2193 bool haveEaten = false;
2196 if (Tok.is(AsmToken::Plus)) {
2197 Parser.Lex(); // Eat the '+' token.
2199 } else if (Tok.is(AsmToken::Minus)) {
2200 Parser.Lex(); // Eat the '-' token.
2204 if (Parser.getTok().is(AsmToken::Identifier))
2205 Reg = tryParseRegister();
2208 return MatchOperand_NoMatch;
2209 Error(Parser.getTok().getLoc(), "register expected");
2210 return MatchOperand_ParseFail;
2212 SMLoc E = Parser.getTok().getLoc();
2214 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
2217 return MatchOperand_Success;
2220 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2221 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2222 /// when they refer multiple MIOperands inside a single one.
2224 cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2225 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2226 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2228 // Create a writeback register dummy placeholder.
2229 Inst.addOperand(MCOperand::CreateImm(0));
2231 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2232 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2236 /// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2237 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2238 /// when they refer multiple MIOperands inside a single one.
2240 cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2241 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2242 // Create a writeback register dummy placeholder.
2243 Inst.addOperand(MCOperand::CreateImm(0));
2244 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2245 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2246 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2250 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2251 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2252 /// when they refer multiple MIOperands inside a single one.
2254 cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2255 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2256 // Create a writeback register dummy placeholder.
2257 Inst.addOperand(MCOperand::CreateImm(0));
2258 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2259 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2260 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2264 /// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2265 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2266 /// when they refer multiple MIOperands inside a single one.
2268 cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2269 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2270 // Create a writeback register dummy placeholder.
2271 Inst.addOperand(MCOperand::CreateImm(0));
2272 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2273 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2274 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2278 /// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
2279 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2280 /// when they refer multiple MIOperands inside a single one.
2282 cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2283 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2285 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2286 // Create a writeback register dummy placeholder.
2287 Inst.addOperand(MCOperand::CreateImm(0));
2289 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2291 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2293 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2297 /// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
2298 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2299 /// when they refer multiple MIOperands inside a single one.
2301 cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2302 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2304 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2305 // Create a writeback register dummy placeholder.
2306 Inst.addOperand(MCOperand::CreateImm(0));
2308 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2310 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2312 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2316 /// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
2317 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2318 /// when they refer multiple MIOperands inside a single one.
2320 cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2321 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2322 // Create a writeback register dummy placeholder.
2323 Inst.addOperand(MCOperand::CreateImm(0));
2325 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2327 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2329 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2331 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2335 /// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
2336 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2337 /// when they refer multiple MIOperands inside a single one.
2339 cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2340 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2341 // Create a writeback register dummy placeholder.
2342 Inst.addOperand(MCOperand::CreateImm(0));
2344 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2346 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2348 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2350 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2354 /// cvtLdrdPre - Convert parsed operands to MCInst.
2355 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2356 /// when they refer multiple MIOperands inside a single one.
2358 cvtLdrdPre(MCInst &Inst, unsigned Opcode,
2359 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2361 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2362 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2363 // Create a writeback register dummy placeholder.
2364 Inst.addOperand(MCOperand::CreateImm(0));
2366 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2368 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2372 /// cvtStrdPre - Convert parsed operands to MCInst.
2373 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2374 /// when they refer multiple MIOperands inside a single one.
2376 cvtStrdPre(MCInst &Inst, unsigned Opcode,
2377 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2378 // Create a writeback register dummy placeholder.
2379 Inst.addOperand(MCOperand::CreateImm(0));
2381 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2382 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2384 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2386 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2390 /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2391 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2392 /// when they refer multiple MIOperands inside a single one.
2394 cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2395 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2396 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2397 // Create a writeback register dummy placeholder.
2398 Inst.addOperand(MCOperand::CreateImm(0));
2399 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2400 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2404 /// cvtThumbMultiple- Convert parsed operands to MCInst.
2405 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2406 /// when they refer multiple MIOperands inside a single one.
2408 cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
2409 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2410 // The second source operand must be the same register as the destination
2412 if (Operands.size() == 6 &&
2413 (((ARMOperand*)Operands[3])->getReg() !=
2414 ((ARMOperand*)Operands[5])->getReg()) &&
2415 (((ARMOperand*)Operands[3])->getReg() !=
2416 ((ARMOperand*)Operands[4])->getReg())) {
2417 Error(Operands[3]->getStartLoc(),
2418 "destination register must match source register");
2421 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2422 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
2423 ((ARMOperand*)Operands[4])->addRegOperands(Inst, 1);
2424 // If we have a three-operand form, use that, else the second source operand
2425 // is just the destination operand again.
2426 if (Operands.size() == 6)
2427 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
2429 Inst.addOperand(Inst.getOperand(0));
2430 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
2435 /// Parse an ARM memory expression, return false if successful else return true
2436 /// or an error. The first token must be a '[' when called.
2438 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2440 assert(Parser.getTok().is(AsmToken::LBrac) &&
2441 "Token is not a Left Bracket");
2442 S = Parser.getTok().getLoc();
2443 Parser.Lex(); // Eat left bracket token.
2445 const AsmToken &BaseRegTok = Parser.getTok();
2446 int BaseRegNum = tryParseRegister();
2447 if (BaseRegNum == -1)
2448 return Error(BaseRegTok.getLoc(), "register expected");
2450 // The next token must either be a comma or a closing bracket.
2451 const AsmToken &Tok = Parser.getTok();
2452 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
2453 return Error(Tok.getLoc(), "malformed memory operand");
2455 if (Tok.is(AsmToken::RBrac)) {
2457 Parser.Lex(); // Eat right bracket token.
2459 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
2465 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
2466 Parser.Lex(); // Eat the comma.
2468 // If we have a '#' it's an immediate offset, else assume it's a register
2470 if (Parser.getTok().is(AsmToken::Hash)) {
2471 Parser.Lex(); // Eat the '#'.
2472 E = Parser.getTok().getLoc();
2474 // FIXME: Special case #-0 so we can correctly set the U bit.
2476 const MCExpr *Offset;
2477 if (getParser().ParseExpression(Offset))
2480 // The expression has to be a constant. Memory references with relocations
2481 // don't come through here, as they use the <label> forms of the relevant
2483 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2485 return Error (E, "constant expression expected");
2487 // Now we should have the closing ']'
2488 E = Parser.getTok().getLoc();
2489 if (Parser.getTok().isNot(AsmToken::RBrac))
2490 return Error(E, "']' expected");
2491 Parser.Lex(); // Eat right bracket token.
2493 // Don't worry about range checking the value here. That's handled by
2494 // the is*() predicates.
2495 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
2496 ARM_AM::no_shift, 0, false, S,E));
2498 // If there's a pre-indexing writeback marker, '!', just add it as a token
2500 if (Parser.getTok().is(AsmToken::Exclaim)) {
2501 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2502 Parser.Lex(); // Eat the '!'.
2508 // The register offset is optionally preceded by a '+' or '-'
2509 bool isNegative = false;
2510 if (Parser.getTok().is(AsmToken::Minus)) {
2512 Parser.Lex(); // Eat the '-'.
2513 } else if (Parser.getTok().is(AsmToken::Plus)) {
2515 Parser.Lex(); // Eat the '+'.
2518 E = Parser.getTok().getLoc();
2519 int OffsetRegNum = tryParseRegister();
2520 if (OffsetRegNum == -1)
2521 return Error(E, "register expected");
2523 // If there's a shift operator, handle it.
2524 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
2525 unsigned ShiftImm = 0;
2526 if (Parser.getTok().is(AsmToken::Comma)) {
2527 Parser.Lex(); // Eat the ','.
2528 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
2532 // Now we should have the closing ']'
2533 E = Parser.getTok().getLoc();
2534 if (Parser.getTok().isNot(AsmToken::RBrac))
2535 return Error(E, "']' expected");
2536 Parser.Lex(); // Eat right bracket token.
2538 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
2539 ShiftType, ShiftImm, isNegative,
2542 // If there's a pre-indexing writeback marker, '!', just add it as a token
2544 if (Parser.getTok().is(AsmToken::Exclaim)) {
2545 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2546 Parser.Lex(); // Eat the '!'.
2552 /// parseMemRegOffsetShift - one of these two:
2553 /// ( lsl | lsr | asr | ror ) , # shift_amount
2555 /// return true if it parses a shift otherwise it returns false.
2556 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
2558 SMLoc Loc = Parser.getTok().getLoc();
2559 const AsmToken &Tok = Parser.getTok();
2560 if (Tok.isNot(AsmToken::Identifier))
2562 StringRef ShiftName = Tok.getString();
2563 if (ShiftName == "lsl" || ShiftName == "LSL")
2565 else if (ShiftName == "lsr" || ShiftName == "LSR")
2567 else if (ShiftName == "asr" || ShiftName == "ASR")
2569 else if (ShiftName == "ror" || ShiftName == "ROR")
2571 else if (ShiftName == "rrx" || ShiftName == "RRX")
2574 return Error(Loc, "illegal shift operator");
2575 Parser.Lex(); // Eat shift type token.
2577 // rrx stands alone.
2579 if (St != ARM_AM::rrx) {
2580 Loc = Parser.getTok().getLoc();
2581 // A '#' and a shift amount.
2582 const AsmToken &HashTok = Parser.getTok();
2583 if (HashTok.isNot(AsmToken::Hash))
2584 return Error(HashTok.getLoc(), "'#' expected");
2585 Parser.Lex(); // Eat hash token.
2588 if (getParser().ParseExpression(Expr))
2590 // Range check the immediate.
2591 // lsl, ror: 0 <= imm <= 31
2592 // lsr, asr: 0 <= imm <= 32
2593 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2595 return Error(Loc, "shift amount must be an immediate");
2596 int64_t Imm = CE->getValue();
2598 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
2599 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
2600 return Error(Loc, "immediate shift value out of range");
2607 /// Parse a arm instruction operand. For now this parses the operand regardless
2608 /// of the mnemonic.
2609 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2610 StringRef Mnemonic) {
2613 // Check if the current operand has a custom associated parser, if so, try to
2614 // custom parse the operand, or fallback to the general approach.
2615 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
2616 if (ResTy == MatchOperand_Success)
2618 // If there wasn't a custom match, try the generic matcher below. Otherwise,
2619 // there was a match, but an error occurred, in which case, just return that
2620 // the operand parsing failed.
2621 if (ResTy == MatchOperand_ParseFail)
2624 switch (getLexer().getKind()) {
2626 Error(Parser.getTok().getLoc(), "unexpected token in operand");
2628 case AsmToken::Identifier: {
2629 if (!tryParseRegisterWithWriteBack(Operands))
2631 int Res = tryParseShiftRegister(Operands);
2632 if (Res == 0) // success
2634 else if (Res == -1) // irrecoverable error
2637 // Fall though for the Identifier case that is not a register or a
2640 case AsmToken::Integer: // things like 1f and 2b as a branch targets
2641 case AsmToken::Dot: { // . as a branch target
2642 // This was not a register so parse other operands that start with an
2643 // identifier (like labels) as expressions and create them as immediates.
2644 const MCExpr *IdVal;
2645 S = Parser.getTok().getLoc();
2646 if (getParser().ParseExpression(IdVal))
2648 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2649 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
2652 case AsmToken::LBrac:
2653 return parseMemory(Operands);
2654 case AsmToken::LCurly:
2655 return parseRegisterList(Operands);
2656 case AsmToken::Hash:
2657 // #42 -> immediate.
2658 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
2659 S = Parser.getTok().getLoc();
2661 const MCExpr *ImmVal;
2662 if (getParser().ParseExpression(ImmVal))
2664 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2665 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
2667 case AsmToken::Colon: {
2668 // ":lower16:" and ":upper16:" expression prefixes
2669 // FIXME: Check it's an expression prefix,
2670 // e.g. (FOO - :lower16:BAR) isn't legal.
2671 ARMMCExpr::VariantKind RefKind;
2672 if (parsePrefix(RefKind))
2675 const MCExpr *SubExprVal;
2676 if (getParser().ParseExpression(SubExprVal))
2679 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
2681 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2682 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
2688 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
2689 // :lower16: and :upper16:.
2690 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
2691 RefKind = ARMMCExpr::VK_ARM_None;
2693 // :lower16: and :upper16: modifiers
2694 assert(getLexer().is(AsmToken::Colon) && "expected a :");
2695 Parser.Lex(); // Eat ':'
2697 if (getLexer().isNot(AsmToken::Identifier)) {
2698 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
2702 StringRef IDVal = Parser.getTok().getIdentifier();
2703 if (IDVal == "lower16") {
2704 RefKind = ARMMCExpr::VK_ARM_LO16;
2705 } else if (IDVal == "upper16") {
2706 RefKind = ARMMCExpr::VK_ARM_HI16;
2708 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
2713 if (getLexer().isNot(AsmToken::Colon)) {
2714 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
2717 Parser.Lex(); // Eat the last ':'
2722 ARMAsmParser::applyPrefixToExpr(const MCExpr *E,
2723 MCSymbolRefExpr::VariantKind Variant) {
2724 // Recurse over the given expression, rebuilding it to apply the given variant
2725 // to the leftmost symbol.
2726 if (Variant == MCSymbolRefExpr::VK_None)
2729 switch (E->getKind()) {
2730 case MCExpr::Target:
2731 llvm_unreachable("Can't handle target expr yet");
2732 case MCExpr::Constant:
2733 llvm_unreachable("Can't handle lower16/upper16 of constant yet");
2735 case MCExpr::SymbolRef: {
2736 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
2738 if (SRE->getKind() != MCSymbolRefExpr::VK_None)
2741 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext());
2745 llvm_unreachable("Can't handle unary expressions yet");
2747 case MCExpr::Binary: {
2748 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
2749 const MCExpr *LHS = applyPrefixToExpr(BE->getLHS(), Variant);
2750 const MCExpr *RHS = BE->getRHS();
2754 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext());
2758 assert(0 && "Invalid expression kind!");
2762 /// \brief Given a mnemonic, split out possible predication code and carry
2763 /// setting letters to form a canonical mnemonic and flags.
2765 // FIXME: Would be nice to autogen this.
2766 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
2767 unsigned &PredicationCode,
2769 unsigned &ProcessorIMod) {
2770 PredicationCode = ARMCC::AL;
2771 CarrySetting = false;
2774 // Ignore some mnemonics we know aren't predicated forms.
2776 // FIXME: Would be nice to autogen this.
2777 if ((Mnemonic == "movs" && isThumb()) ||
2778 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
2779 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
2780 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
2781 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
2782 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
2783 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
2784 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
2787 // First, split out any predication code. Ignore mnemonics we know aren't
2788 // predicated but do have a carry-set and so weren't caught above.
2789 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
2790 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
2791 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
2792 Mnemonic != "sbcs") {
2793 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
2794 .Case("eq", ARMCC::EQ)
2795 .Case("ne", ARMCC::NE)
2796 .Case("hs", ARMCC::HS)
2797 .Case("cs", ARMCC::HS)
2798 .Case("lo", ARMCC::LO)
2799 .Case("cc", ARMCC::LO)
2800 .Case("mi", ARMCC::MI)
2801 .Case("pl", ARMCC::PL)
2802 .Case("vs", ARMCC::VS)
2803 .Case("vc", ARMCC::VC)
2804 .Case("hi", ARMCC::HI)
2805 .Case("ls", ARMCC::LS)
2806 .Case("ge", ARMCC::GE)
2807 .Case("lt", ARMCC::LT)
2808 .Case("gt", ARMCC::GT)
2809 .Case("le", ARMCC::LE)
2810 .Case("al", ARMCC::AL)
2813 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
2814 PredicationCode = CC;
2818 // Next, determine if we have a carry setting bit. We explicitly ignore all
2819 // the instructions we know end in 's'.
2820 if (Mnemonic.endswith("s") &&
2821 !(Mnemonic == "cps" || Mnemonic == "mls" ||
2822 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
2823 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
2824 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
2825 Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
2826 (Mnemonic == "movs" && isThumb()))) {
2827 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
2828 CarrySetting = true;
2831 // The "cps" instruction can have a interrupt mode operand which is glued into
2832 // the mnemonic. Check if this is the case, split it and parse the imod op
2833 if (Mnemonic.startswith("cps")) {
2834 // Split out any imod code.
2836 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
2837 .Case("ie", ARM_PROC::IE)
2838 .Case("id", ARM_PROC::ID)
2841 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
2842 ProcessorIMod = IMod;
2849 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
2850 /// inclusion of carry set or predication code operands.
2852 // FIXME: It would be nice to autogen this.
2854 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
2855 bool &CanAcceptPredicationCode) {
2856 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
2857 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
2858 Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
2859 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
2860 Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" ||
2861 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
2862 Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
2863 Mnemonic == "eor" || Mnemonic == "smlal" || Mnemonic == "neg" ||
2864 // FIXME: We need a better way. This really confused Thumb2
2865 // parsing for 'mov'.
2866 (Mnemonic == "mov" && !isThumbOne())) {
2867 CanAcceptCarrySet = true;
2869 CanAcceptCarrySet = false;
2872 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
2873 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
2874 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
2875 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
2876 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "clrex" ||
2877 Mnemonic == "setend" ||
2878 (Mnemonic == "nop" && isThumbOne()) ||
2879 ((Mnemonic == "pld" || Mnemonic == "pli") && !isThumb()) ||
2880 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs"))
2882 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumb())) {
2883 CanAcceptPredicationCode = false;
2885 CanAcceptPredicationCode = true;
2889 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
2890 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
2891 CanAcceptPredicationCode = false;
2894 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
2895 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2897 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
2898 // another does not. Specifically, the MOVW instruction does not. So we
2899 // special case it here and remove the defaulted (non-setting) cc_out
2900 // operand if that's the instruction we're trying to match.
2902 // We do this as post-processing of the explicit operands rather than just
2903 // conditionally adding the cc_out in the first place because we need
2904 // to check the type of the parsed immediate operand.
2905 if (Mnemonic == "mov" && Operands.size() > 4 &&
2906 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
2907 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
2908 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
2911 // Register-register 'add' for thumb does not have a cc_out operand
2912 // when there are only two register operands.
2913 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
2914 static_cast<ARMOperand*>(Operands[3])->isReg() &&
2915 static_cast<ARMOperand*>(Operands[4])->isReg() &&
2916 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
2918 // Register-register 'add' for thumb does not have a cc_out operand
2919 // when it's an ADD Rdm, SP, {Rdm|#imm} instruction.
2920 if (isThumb() && Mnemonic == "add" && Operands.size() == 6 &&
2921 static_cast<ARMOperand*>(Operands[3])->isReg() &&
2922 static_cast<ARMOperand*>(Operands[4])->isReg() &&
2923 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
2924 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
2926 // Register-register 'add/sub' for thumb does not have a cc_out operand
2927 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
2928 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
2929 // right, this will result in better diagnostics (which operand is off)
2931 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
2932 (Operands.size() == 5 || Operands.size() == 6) &&
2933 static_cast<ARMOperand*>(Operands[3])->isReg() &&
2934 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
2935 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
2941 /// Parse an arm instruction mnemonic followed by its operands.
2942 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
2943 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2944 // Create the leading tokens for the mnemonic, split by '.' characters.
2945 size_t Start = 0, Next = Name.find('.');
2946 StringRef Mnemonic = Name.slice(Start, Next);
2948 // Split out the predication code and carry setting flag from the mnemonic.
2949 unsigned PredicationCode;
2950 unsigned ProcessorIMod;
2952 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
2955 // In Thumb1, only the branch (B) instruction can be predicated.
2956 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
2957 Parser.EatToEndOfStatement();
2958 return Error(NameLoc, "conditional execution not supported in Thumb1");
2961 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
2963 // FIXME: This is all a pretty gross hack. We should automatically handle
2964 // optional operands like this via tblgen.
2966 // Next, add the CCOut and ConditionCode operands, if needed.
2968 // For mnemonics which can ever incorporate a carry setting bit or predication
2969 // code, our matching model involves us always generating CCOut and
2970 // ConditionCode operands to match the mnemonic "as written" and then we let
2971 // the matcher deal with finding the right instruction or generating an
2972 // appropriate error.
2973 bool CanAcceptCarrySet, CanAcceptPredicationCode;
2974 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
2976 // If we had a carry-set on an instruction that can't do that, issue an
2978 if (!CanAcceptCarrySet && CarrySetting) {
2979 Parser.EatToEndOfStatement();
2980 return Error(NameLoc, "instruction '" + Mnemonic +
2981 "' can not set flags, but 's' suffix specified");
2983 // If we had a predication code on an instruction that can't do that, issue an
2985 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
2986 Parser.EatToEndOfStatement();
2987 return Error(NameLoc, "instruction '" + Mnemonic +
2988 "' is not predicable, but condition code specified");
2991 // Add the carry setting operand, if necessary.
2993 // FIXME: It would be awesome if we could somehow invent a location such that
2994 // match errors on this operand would print a nice diagnostic about how the
2995 // 's' character in the mnemonic resulted in a CCOut operand.
2996 if (CanAcceptCarrySet)
2997 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
3000 // Add the predication code operand, if necessary.
3001 if (CanAcceptPredicationCode) {
3002 Operands.push_back(ARMOperand::CreateCondCode(
3003 ARMCC::CondCodes(PredicationCode), NameLoc));
3006 // Add the processor imod operand, if necessary.
3007 if (ProcessorIMod) {
3008 Operands.push_back(ARMOperand::CreateImm(
3009 MCConstantExpr::Create(ProcessorIMod, getContext()),
3012 // This mnemonic can't ever accept a imod, but the user wrote
3013 // one (or misspelled another mnemonic).
3015 // FIXME: Issue a nice error.
3018 // Add the remaining tokens in the mnemonic.
3019 while (Next != StringRef::npos) {
3021 Next = Name.find('.', Start + 1);
3022 StringRef ExtraToken = Name.slice(Start, Next);
3024 // For now, we're only parsing Thumb1 (for the most part), so
3025 // just ignore ".n" qualifiers. We'll use them to restrict
3026 // matching when we do Thumb2.
3027 if (ExtraToken != ".n")
3028 Operands.push_back(ARMOperand::CreateToken(ExtraToken, NameLoc));
3031 // Read the remaining operands.
3032 if (getLexer().isNot(AsmToken::EndOfStatement)) {
3033 // Read the first operand.
3034 if (parseOperand(Operands, Mnemonic)) {
3035 Parser.EatToEndOfStatement();
3039 while (getLexer().is(AsmToken::Comma)) {
3040 Parser.Lex(); // Eat the comma.
3042 // Parse and remember the operand.
3043 if (parseOperand(Operands, Mnemonic)) {
3044 Parser.EatToEndOfStatement();
3050 if (getLexer().isNot(AsmToken::EndOfStatement)) {
3051 Parser.EatToEndOfStatement();
3052 return TokError("unexpected token in argument list");
3055 Parser.Lex(); // Consume the EndOfStatement
3057 // Some instructions, mostly Thumb, have forms for the same mnemonic that
3058 // do and don't have a cc_out optional-def operand. With some spot-checks
3059 // of the operand list, we can figure out which variant we're trying to
3060 // parse and adjust accordingly before actually matching. Reason number
3061 // #317 the table driven matcher doesn't fit well with the ARM instruction
3063 if (shouldOmitCCOutOperand(Mnemonic, Operands)) {
3064 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3065 Operands.erase(Operands.begin() + 1);
3069 // ARM mode 'blx' need special handling, as the register operand version
3070 // is predicable, but the label operand version is not. So, we can't rely
3071 // on the Mnemonic based checking to correctly figure out when to put
3072 // a CondCode operand in the list. If we're trying to match the label
3073 // version, remove the CondCode operand here.
3074 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
3075 static_cast<ARMOperand*>(Operands[2])->isImm()) {
3076 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3077 Operands.erase(Operands.begin() + 1);
3081 // The vector-compare-to-zero instructions have a literal token "#0" at
3082 // the end that comes to here as an immediate operand. Convert it to a
3083 // token to play nicely with the matcher.
3084 if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
3085 Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
3086 static_cast<ARMOperand*>(Operands[5])->isImm()) {
3087 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
3088 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
3089 if (CE && CE->getValue() == 0) {
3090 Operands.erase(Operands.begin() + 5);
3091 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3095 // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
3096 // end. Convert it to a token here.
3097 if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
3098 static_cast<ARMOperand*>(Operands[5])->isImm()) {
3099 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
3100 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
3101 if (CE && CE->getValue() == 0) {
3102 Operands.erase(Operands.begin() + 5);
3103 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3111 // Validate context-sensitive operand constraints.
3113 // return 'true' if register list contains non-low GPR registers,
3114 // 'false' otherwise. If Reg is in the register list or is HiReg, set
3115 // 'containsReg' to true.
3116 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
3117 unsigned HiReg, bool &containsReg) {
3118 containsReg = false;
3119 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
3120 unsigned OpReg = Inst.getOperand(i).getReg();
3123 // Anything other than a low register isn't legal here.
3124 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
3130 // FIXME: We would really like to be able to tablegen'erate this.
3132 validateInstruction(MCInst &Inst,
3133 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3134 switch (Inst.getOpcode()) {
3137 case ARM::LDRD_POST:
3139 // Rt2 must be Rt + 1.
3140 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3141 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3143 return Error(Operands[3]->getStartLoc(),
3144 "destination operands must be sequential");
3148 // Rt2 must be Rt + 1.
3149 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3150 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3152 return Error(Operands[3]->getStartLoc(),
3153 "source operands must be sequential");
3157 case ARM::STRD_POST:
3159 // Rt2 must be Rt + 1.
3160 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3161 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
3163 return Error(Operands[3]->getStartLoc(),
3164 "source operands must be sequential");
3169 // width must be in range [1, 32-lsb]
3170 unsigned lsb = Inst.getOperand(2).getImm();
3171 unsigned widthm1 = Inst.getOperand(3).getImm();
3172 if (widthm1 >= 32 - lsb)
3173 return Error(Operands[5]->getStartLoc(),
3174 "bitfield width must be in range [1,32-lsb]");
3178 // Thumb LDM instructions are writeback iff the base register is not
3179 // in the register list.
3180 unsigned Rn = Inst.getOperand(0).getReg();
3181 bool hasWritebackToken =
3182 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
3183 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
3184 bool listContainsBase;
3185 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase))
3186 return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
3187 "registers must be in range r0-r7");
3188 // If we should have writeback, then there should be a '!' token.
3189 if (!listContainsBase && !hasWritebackToken)
3190 return Error(Operands[2]->getStartLoc(),
3191 "writeback operator '!' expected");
3192 // Likewise, if we should not have writeback, there must not be a '!'
3193 if (listContainsBase && hasWritebackToken)
3194 return Error(Operands[3]->getStartLoc(),
3195 "writeback operator '!' not allowed when base register "
3196 "in register list");
3201 bool listContainsBase;
3202 if (checkLowRegisterList(Inst, 3, 0, ARM::PC, listContainsBase))
3203 return Error(Operands[2]->getStartLoc(),
3204 "registers must be in range r0-r7 or pc");
3208 bool listContainsBase;
3209 if (checkLowRegisterList(Inst, 3, 0, ARM::LR, listContainsBase))
3210 return Error(Operands[2]->getStartLoc(),
3211 "registers must be in range r0-r7 or lr");
3214 case ARM::tSTMIA_UPD: {
3215 bool listContainsBase;
3216 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase))
3217 return Error(Operands[4]->getStartLoc(),
3218 "registers must be in range r0-r7");
3227 processInstruction(MCInst &Inst,
3228 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3229 switch (Inst.getOpcode()) {
3230 case ARM::LDMIA_UPD:
3231 // If this is a load of a single register via a 'pop', then we should use
3232 // a post-indexed LDR instruction instead, per the ARM ARM.
3233 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
3234 Inst.getNumOperands() == 5) {
3236 TmpInst.setOpcode(ARM::LDR_POST_IMM);
3237 TmpInst.addOperand(Inst.getOperand(4)); // Rt
3238 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3239 TmpInst.addOperand(Inst.getOperand(1)); // Rn
3240 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
3241 TmpInst.addOperand(MCOperand::CreateImm(4));
3242 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3243 TmpInst.addOperand(Inst.getOperand(3));
3247 case ARM::STMDB_UPD:
3248 // If this is a store of a single register via a 'push', then we should use
3249 // a pre-indexed STR instruction instead, per the ARM ARM.
3250 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
3251 Inst.getNumOperands() == 5) {
3253 TmpInst.setOpcode(ARM::STR_PRE_IMM);
3254 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3255 TmpInst.addOperand(Inst.getOperand(4)); // Rt
3256 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
3257 TmpInst.addOperand(MCOperand::CreateImm(-4));
3258 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3259 TmpInst.addOperand(Inst.getOperand(3));
3264 // If the immediate is in the range 0-7, we really wanted tADDi3.
3265 if (Inst.getOperand(3).getImm() < 8)
3266 Inst.setOpcode(ARM::tADDi3);
3269 // If the conditional is AL, we really want tB.
3270 if (Inst.getOperand(1).getImm() == ARMCC::AL)
3271 Inst.setOpcode(ARM::tB);
3276 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around
3277 // the ARMInsts array) instead. Getting that here requires awkward
3278 // API changes, though. Better way?
3280 extern MCInstrDesc ARMInsts[];
3282 static MCInstrDesc &getInstDesc(unsigned Opcode) {
3283 return ARMInsts[Opcode];
3286 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
3287 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
3288 // suffix depending on whether they're in an IT block or not.
3289 unsigned Opc = Inst.getOpcode();
3290 MCInstrDesc &MCID = getInstDesc(Opc);
3291 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
3292 assert(MCID.hasOptionalDef() &&
3293 "optionally flag setting instruction missing optional def operand");
3294 assert(MCID.NumOperands == Inst.getNumOperands() &&
3295 "operand count mismatch!");
3296 // Find the optional-def operand (cc_out).
3299 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
3302 // If we're parsing Thumb1, reject it completely.
3303 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3304 return Match_MnemonicFail;
3305 // If we're parsing Thumb2, which form is legal depends on whether we're
3307 // FIXME: We don't yet do IT blocks, so just always consider it to be
3308 // that we aren't in one until we do.
3309 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3310 return Match_RequiresITBlock;
3312 // Some high-register supporting Thumb1 encodings only allow both registers
3313 // to be from r0-r7 when in Thumb2.
3314 else if (Opc == ARM::tADDhirr && isThumbOne() &&
3315 isARMLowRegister(Inst.getOperand(1).getReg()) &&
3316 isARMLowRegister(Inst.getOperand(2).getReg()))
3317 return Match_RequiresThumb2;
3318 // Others only require ARMv6 or later.
3319 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
3320 isARMLowRegister(Inst.getOperand(0).getReg()) &&
3321 isARMLowRegister(Inst.getOperand(1).getReg()))
3322 return Match_RequiresV6;
3323 return Match_Success;
3327 MatchAndEmitInstruction(SMLoc IDLoc,
3328 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
3332 unsigned MatchResult;
3333 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
3334 switch (MatchResult) {
3337 // Context sensitive operand constraints aren't handled by the matcher,
3338 // so check them here.
3339 if (validateInstruction(Inst, Operands))
3342 // Some instructions need post-processing to, for example, tweak which
3343 // encoding is selected.
3344 processInstruction(Inst, Operands);
3346 Out.EmitInstruction(Inst);
3348 case Match_MissingFeature:
3349 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
3351 case Match_InvalidOperand: {
3352 SMLoc ErrorLoc = IDLoc;
3353 if (ErrorInfo != ~0U) {
3354 if (ErrorInfo >= Operands.size())
3355 return Error(IDLoc, "too few operands for instruction");
3357 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
3358 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
3361 return Error(ErrorLoc, "invalid operand for instruction");
3363 case Match_MnemonicFail:
3364 return Error(IDLoc, "invalid instruction");
3365 case Match_ConversionFail:
3366 // The converter function will have already emited a diagnostic.
3368 case Match_RequiresITBlock:
3369 return Error(IDLoc, "instruction only valid inside IT block");
3370 case Match_RequiresV6:
3371 return Error(IDLoc, "instruction variant requires ARMv6 or later");
3372 case Match_RequiresThumb2:
3373 return Error(IDLoc, "instruction variant requires Thumb2");
3376 llvm_unreachable("Implement any new match types added!");
3380 /// parseDirective parses the arm specific directives
3381 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
3382 StringRef IDVal = DirectiveID.getIdentifier();
3383 if (IDVal == ".word")
3384 return parseDirectiveWord(4, DirectiveID.getLoc());
3385 else if (IDVal == ".thumb")
3386 return parseDirectiveThumb(DirectiveID.getLoc());
3387 else if (IDVal == ".thumb_func")
3388 return parseDirectiveThumbFunc(DirectiveID.getLoc());
3389 else if (IDVal == ".code")
3390 return parseDirectiveCode(DirectiveID.getLoc());
3391 else if (IDVal == ".syntax")
3392 return parseDirectiveSyntax(DirectiveID.getLoc());
3396 /// parseDirectiveWord
3397 /// ::= .word [ expression (, expression)* ]
3398 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
3399 if (getLexer().isNot(AsmToken::EndOfStatement)) {
3401 const MCExpr *Value;
3402 if (getParser().ParseExpression(Value))
3405 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
3407 if (getLexer().is(AsmToken::EndOfStatement))
3410 // FIXME: Improve diagnostic.
3411 if (getLexer().isNot(AsmToken::Comma))
3412 return Error(L, "unexpected token in directive");
3421 /// parseDirectiveThumb
3423 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
3424 if (getLexer().isNot(AsmToken::EndOfStatement))
3425 return Error(L, "unexpected token in directive");
3428 // TODO: set thumb mode
3429 // TODO: tell the MC streamer the mode
3430 // getParser().getStreamer().Emit???();
3434 /// parseDirectiveThumbFunc
3435 /// ::= .thumbfunc symbol_name
3436 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
3437 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
3438 bool isMachO = MAI.hasSubsectionsViaSymbols();
3441 // Darwin asm has function name after .thumb_func direction
3444 const AsmToken &Tok = Parser.getTok();
3445 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
3446 return Error(L, "unexpected token in .thumb_func directive");
3447 Name = Tok.getString();
3448 Parser.Lex(); // Consume the identifier token.
3451 if (getLexer().isNot(AsmToken::EndOfStatement))
3452 return Error(L, "unexpected token in directive");
3455 // FIXME: assuming function name will be the line following .thumb_func
3457 Name = Parser.getTok().getString();
3460 // Mark symbol as a thumb symbol.
3461 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
3462 getParser().getStreamer().EmitThumbFunc(Func);
3466 /// parseDirectiveSyntax
3467 /// ::= .syntax unified | divided
3468 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
3469 const AsmToken &Tok = Parser.getTok();
3470 if (Tok.isNot(AsmToken::Identifier))
3471 return Error(L, "unexpected token in .syntax directive");
3472 StringRef Mode = Tok.getString();
3473 if (Mode == "unified" || Mode == "UNIFIED")
3475 else if (Mode == "divided" || Mode == "DIVIDED")
3476 return Error(L, "'.syntax divided' arm asssembly not supported");
3478 return Error(L, "unrecognized syntax mode in .syntax directive");
3480 if (getLexer().isNot(AsmToken::EndOfStatement))
3481 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3484 // TODO tell the MC streamer the mode
3485 // getParser().getStreamer().Emit???();
3489 /// parseDirectiveCode
3490 /// ::= .code 16 | 32
3491 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
3492 const AsmToken &Tok = Parser.getTok();
3493 if (Tok.isNot(AsmToken::Integer))
3494 return Error(L, "unexpected token in .code directive");
3495 int64_t Val = Parser.getTok().getIntVal();
3501 return Error(L, "invalid operand to .code directive");
3503 if (getLexer().isNot(AsmToken::EndOfStatement))
3504 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3510 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
3515 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
3522 extern "C" void LLVMInitializeARMAsmLexer();
3524 /// Force static initialization.
3525 extern "C" void LLVMInitializeARMAsmParser() {
3526 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
3527 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
3528 LLVMInitializeARMAsmLexer();
3531 #define GET_REGISTER_MATCHER
3532 #define GET_MATCHER_IMPLEMENTATION
3533 #include "ARMGenAsmMatcher.inc"