1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "ARMBuildAttrs.h"
11 #include "ARMFPUName.h"
12 #include "ARMFeatures.h"
13 #include "llvm/MC/MCTargetAsmParser.h"
14 #include "MCTargetDesc/ARMAddressingModes.h"
15 #include "MCTargetDesc/ARMArchName.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "MCTargetDesc/ARMMCExpr.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/OwningPtr.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/StringExtras.h"
23 #include "llvm/ADT/StringSwitch.h"
24 #include "llvm/ADT/Twine.h"
25 #include "llvm/MC/MCAsmInfo.h"
26 #include "llvm/MC/MCAssembler.h"
27 #include "llvm/MC/MCContext.h"
28 #include "llvm/MC/MCELFStreamer.h"
29 #include "llvm/MC/MCExpr.h"
30 #include "llvm/MC/MCInst.h"
31 #include "llvm/MC/MCInstrDesc.h"
32 #include "llvm/MC/MCInstrInfo.h"
33 #include "llvm/MC/MCParser/MCAsmLexer.h"
34 #include "llvm/MC/MCParser/MCAsmParser.h"
35 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
36 #include "llvm/MC/MCRegisterInfo.h"
37 #include "llvm/MC/MCStreamer.h"
38 #include "llvm/MC/MCSubtargetInfo.h"
39 #include "llvm/MC/MCSymbol.h"
40 #include "llvm/Support/ELF.h"
41 #include "llvm/Support/MathExtras.h"
42 #include "llvm/Support/SourceMgr.h"
43 #include "llvm/Support/TargetRegistry.h"
44 #include "llvm/Support/raw_ostream.h"
52 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
54 // A class to keep track of assembler-generated constant pools that are use to
55 // implement the ldr-pseudo.
57 typedef SmallVector<std::pair<MCSymbol *, const MCExpr *>, 4> EntryVecTy;
61 // Initialize a new empty constant pool
64 // Add a new entry to the constant pool in the next slot.
65 // \param Value is the new entry to put in the constant pool.
67 // \returns a MCExpr that references the newly inserted value
68 const MCExpr *addEntry(const MCExpr *Value, MCContext &Context) {
69 MCSymbol *CPEntryLabel = Context.CreateTempSymbol();
71 Entries.push_back(std::make_pair(CPEntryLabel, Value));
72 return MCSymbolRefExpr::Create(CPEntryLabel, Context);
75 // Emit the contents of the constant pool using the provided streamer.
76 void emitEntries(MCStreamer &Streamer) const {
77 Streamer.EmitCodeAlignment(4); // align to 4-byte address
78 Streamer.EmitDataRegion(MCDR_DataRegion);
79 for (EntryVecTy::const_iterator I = Entries.begin(), E = Entries.end();
81 Streamer.EmitLabel(I->first);
82 Streamer.EmitValue(I->second, 4);
84 Streamer.EmitDataRegion(MCDR_DataRegionEnd);
88 // Map type used to keep track of per-Section constant pools used by the
89 // ldr-pseudo opcode. The map associates a section to its constant pool. The
90 // constant pool is a vector of (label, value) pairs. When the ldr
91 // pseudo is parsed we insert a new (label, value) pair into the constant pool
92 // for the current section and add MCSymbolRefExpr to the new label as
93 // an opcode to the ldr. After we have parsed all the user input we
94 // output the (label, value) pairs in each constant pool at the end of the
96 typedef std::map<const MCSection *, ConstantPool> ConstantPoolMapTy;
98 class ARMAsmParser : public MCTargetAsmParser {
101 const MCInstrInfo &MII;
102 const MCRegisterInfo *MRI;
103 ConstantPoolMapTy ConstantPools;
105 // Assembler created constant pools for ldr pseudo
106 ConstantPool *getConstantPool(const MCSection *Section) {
107 ConstantPoolMapTy::iterator CP = ConstantPools.find(Section);
108 if (CP == ConstantPools.end())
114 ConstantPool &getOrCreateConstantPool(const MCSection *Section) {
115 return ConstantPools[Section];
118 ARMTargetStreamer &getTargetStreamer() {
119 MCTargetStreamer &TS = getParser().getStreamer().getTargetStreamer();
120 return static_cast<ARMTargetStreamer &>(TS);
123 // Unwind directives state
126 SMLoc PersonalityLoc;
127 SMLoc HandlerDataLoc;
129 void resetUnwindDirectiveParserState() {
130 FnStartLoc = SMLoc();
131 CantUnwindLoc = SMLoc();
132 PersonalityLoc = SMLoc();
133 HandlerDataLoc = SMLoc();
137 // Map of register aliases registers via the .req directive.
138 StringMap<unsigned> RegisterReqs;
140 bool NextSymbolIsThumb;
143 ARMCC::CondCodes Cond; // Condition for IT block.
144 unsigned Mask:4; // Condition mask for instructions.
145 // Starting at first 1 (from lsb).
146 // '1' condition as indicated in IT.
147 // '0' inverse of condition (else).
148 // Count of instructions in IT block is
149 // 4 - trailingzeroes(mask)
151 bool FirstCond; // Explicit flag for when we're parsing the
152 // First instruction in the IT block. It's
153 // implied in the mask, so needs special
156 unsigned CurPosition; // Current position in parsing of IT
157 // block. In range [0,3]. Initialized
158 // according to count of instructions in block.
159 // ~0U if no active IT block.
161 bool inITBlock() { return ITState.CurPosition != ~0U;}
162 void forwardITPosition() {
163 if (!inITBlock()) return;
164 // Move to the next instruction in the IT block, if there is one. If not,
165 // mark the block as done.
166 unsigned TZ = countTrailingZeros(ITState.Mask);
167 if (++ITState.CurPosition == 5 - TZ)
168 ITState.CurPosition = ~0U; // Done with the IT block after this.
172 MCAsmParser &getParser() const { return Parser; }
173 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
175 bool Warning(SMLoc L, const Twine &Msg,
176 ArrayRef<SMRange> Ranges = None) {
177 return Parser.Warning(L, Msg, Ranges);
179 bool Error(SMLoc L, const Twine &Msg,
180 ArrayRef<SMRange> Ranges = None) {
181 return Parser.Error(L, Msg, Ranges);
184 int tryParseRegister();
185 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
186 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
187 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
188 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
189 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
190 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
191 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
192 unsigned &ShiftAmount);
193 bool parseDirectiveWord(unsigned Size, SMLoc L);
194 bool parseDirectiveThumb(SMLoc L);
195 bool parseDirectiveARM(SMLoc L);
196 bool parseDirectiveThumbFunc(SMLoc L);
197 bool parseDirectiveCode(SMLoc L);
198 bool parseDirectiveSyntax(SMLoc L);
199 bool parseDirectiveReq(StringRef Name, SMLoc L);
200 bool parseDirectiveUnreq(SMLoc L);
201 bool parseDirectiveArch(SMLoc L);
202 bool parseDirectiveEabiAttr(SMLoc L);
203 bool parseDirectiveCPU(SMLoc L);
204 bool parseDirectiveFPU(SMLoc L);
205 bool parseDirectiveFnStart(SMLoc L);
206 bool parseDirectiveFnEnd(SMLoc L);
207 bool parseDirectiveCantUnwind(SMLoc L);
208 bool parseDirectivePersonality(SMLoc L);
209 bool parseDirectiveHandlerData(SMLoc L);
210 bool parseDirectiveSetFP(SMLoc L);
211 bool parseDirectivePad(SMLoc L);
212 bool parseDirectiveRegSave(SMLoc L, bool IsVector);
213 bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
215 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
216 bool &CarrySetting, unsigned &ProcessorIMod,
218 void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
219 bool &CanAcceptCarrySet,
220 bool &CanAcceptPredicationCode);
222 bool isThumb() const {
223 // FIXME: Can tablegen auto-generate this?
224 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
226 bool isThumbOne() const {
227 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
229 bool isThumbTwo() const {
230 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
232 bool hasThumb() const {
233 return STI.getFeatureBits() & ARM::HasV4TOps;
235 bool hasV6Ops() const {
236 return STI.getFeatureBits() & ARM::HasV6Ops;
238 bool hasV6MOps() const {
239 return STI.getFeatureBits() & ARM::HasV6MOps;
241 bool hasV7Ops() const {
242 return STI.getFeatureBits() & ARM::HasV7Ops;
244 bool hasV8Ops() const {
245 return STI.getFeatureBits() & ARM::HasV8Ops;
247 bool hasARM() const {
248 return !(STI.getFeatureBits() & ARM::FeatureNoARM);
252 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
253 setAvailableFeatures(FB);
255 bool isMClass() const {
256 return STI.getFeatureBits() & ARM::FeatureMClass;
259 /// @name Auto-generated Match Functions
262 #define GET_ASSEMBLER_HEADER
263 #include "ARMGenAsmMatcher.inc"
267 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
268 OperandMatchResultTy parseCoprocNumOperand(
269 SmallVectorImpl<MCParsedAsmOperand*>&);
270 OperandMatchResultTy parseCoprocRegOperand(
271 SmallVectorImpl<MCParsedAsmOperand*>&);
272 OperandMatchResultTy parseCoprocOptionOperand(
273 SmallVectorImpl<MCParsedAsmOperand*>&);
274 OperandMatchResultTy parseMemBarrierOptOperand(
275 SmallVectorImpl<MCParsedAsmOperand*>&);
276 OperandMatchResultTy parseInstSyncBarrierOptOperand(
277 SmallVectorImpl<MCParsedAsmOperand*>&);
278 OperandMatchResultTy parseProcIFlagsOperand(
279 SmallVectorImpl<MCParsedAsmOperand*>&);
280 OperandMatchResultTy parseMSRMaskOperand(
281 SmallVectorImpl<MCParsedAsmOperand*>&);
282 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
283 StringRef Op, int Low, int High);
284 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
285 return parsePKHImm(O, "lsl", 0, 31);
287 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
288 return parsePKHImm(O, "asr", 1, 32);
290 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
291 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
292 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
293 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
294 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
295 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
296 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
297 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
298 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
301 // Asm Match Converter Methods
302 void cvtThumbMultiply(MCInst &Inst,
303 const SmallVectorImpl<MCParsedAsmOperand*> &);
304 void cvtThumbBranches(MCInst &Inst,
305 const SmallVectorImpl<MCParsedAsmOperand*> &);
307 bool validateInstruction(MCInst &Inst,
308 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
309 bool processInstruction(MCInst &Inst,
310 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
311 bool shouldOmitCCOutOperand(StringRef Mnemonic,
312 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
313 bool shouldOmitPredicateOperand(StringRef Mnemonic,
314 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
316 enum ARMMatchResultTy {
317 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
318 Match_RequiresNotITBlock,
320 Match_RequiresThumb2,
321 #define GET_OPERAND_DIAGNOSTIC_TYPES
322 #include "ARMGenAsmMatcher.inc"
326 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
327 const MCInstrInfo &MII)
328 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(MII), FPReg(-1) {
329 MCAsmParserExtension::Initialize(_Parser);
331 // Cache the MCRegisterInfo.
332 MRI = getContext().getRegisterInfo();
334 // Initialize the set of available features.
335 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
337 // Not in an ITBlock to start with.
338 ITState.CurPosition = ~0U;
340 NextSymbolIsThumb = false;
343 // Implementation of the MCTargetAsmParser interface:
344 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
345 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
347 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
348 bool ParseDirective(AsmToken DirectiveID);
350 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
351 unsigned checkTargetMatchPredicate(MCInst &Inst);
353 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
354 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
355 MCStreamer &Out, unsigned &ErrorInfo,
356 bool MatchingInlineAsm);
357 void onLabelParsed(MCSymbol *Symbol);
360 } // end anonymous namespace
364 /// ARMOperand - Instances of this class represent a parsed ARM machine
366 class ARMOperand : public MCParsedAsmOperand {
376 k_InstSyncBarrierOpt,
387 k_VectorListAllLanes,
393 k_BitfieldDescriptor,
397 SMLoc StartLoc, EndLoc;
398 SmallVector<unsigned, 8> Registers;
401 ARMCC::CondCodes Val;
408 struct CoprocOptionOp {
421 ARM_ISB::InstSyncBOpt Val;
425 ARM_PROC::IFlags Val;
441 // A vector register list is a sequential list of 1 to 4 registers.
442 struct VectorListOp {
449 struct VectorIndexOp {
457 /// Combined record for all forms of ARM address expressions.
460 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
462 const MCConstantExpr *OffsetImm; // Offset immediate value
463 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
464 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
465 unsigned ShiftImm; // shift for OffsetReg.
466 unsigned Alignment; // 0 = no alignment specified
467 // n = alignment in bytes (2, 4, 8, 16, or 32)
468 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
471 struct PostIdxRegOp {
474 ARM_AM::ShiftOpc ShiftTy;
478 struct ShifterImmOp {
483 struct RegShiftedRegOp {
484 ARM_AM::ShiftOpc ShiftTy;
490 struct RegShiftedImmOp {
491 ARM_AM::ShiftOpc ShiftTy;
508 struct CoprocOptionOp CoprocOption;
509 struct MBOptOp MBOpt;
510 struct ISBOptOp ISBOpt;
511 struct ITMaskOp ITMask;
512 struct IFlagsOp IFlags;
513 struct MMaskOp MMask;
516 struct VectorListOp VectorList;
517 struct VectorIndexOp VectorIndex;
519 struct MemoryOp Memory;
520 struct PostIdxRegOp PostIdxReg;
521 struct ShifterImmOp ShifterImm;
522 struct RegShiftedRegOp RegShiftedReg;
523 struct RegShiftedImmOp RegShiftedImm;
524 struct RotImmOp RotImm;
525 struct BitfieldOp Bitfield;
528 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
530 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
532 StartLoc = o.StartLoc;
549 case k_DPRRegisterList:
550 case k_SPRRegisterList:
551 Registers = o.Registers;
554 case k_VectorListAllLanes:
555 case k_VectorListIndexed:
556 VectorList = o.VectorList;
563 CoprocOption = o.CoprocOption;
568 case k_MemBarrierOpt:
571 case k_InstSyncBarrierOpt:
576 case k_PostIndexRegister:
577 PostIdxReg = o.PostIdxReg;
585 case k_ShifterImmediate:
586 ShifterImm = o.ShifterImm;
588 case k_ShiftedRegister:
589 RegShiftedReg = o.RegShiftedReg;
591 case k_ShiftedImmediate:
592 RegShiftedImm = o.RegShiftedImm;
594 case k_RotateImmediate:
597 case k_BitfieldDescriptor:
598 Bitfield = o.Bitfield;
601 VectorIndex = o.VectorIndex;
606 /// getStartLoc - Get the location of the first token of this operand.
607 SMLoc getStartLoc() const { return StartLoc; }
608 /// getEndLoc - Get the location of the last token of this operand.
609 SMLoc getEndLoc() const { return EndLoc; }
610 /// getLocRange - Get the range between the first and last token of this
612 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
614 ARMCC::CondCodes getCondCode() const {
615 assert(Kind == k_CondCode && "Invalid access!");
619 unsigned getCoproc() const {
620 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
624 StringRef getToken() const {
625 assert(Kind == k_Token && "Invalid access!");
626 return StringRef(Tok.Data, Tok.Length);
629 unsigned getReg() const {
630 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
634 const SmallVectorImpl<unsigned> &getRegList() const {
635 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
636 Kind == k_SPRRegisterList) && "Invalid access!");
640 const MCExpr *getImm() const {
641 assert(isImm() && "Invalid access!");
645 unsigned getVectorIndex() const {
646 assert(Kind == k_VectorIndex && "Invalid access!");
647 return VectorIndex.Val;
650 ARM_MB::MemBOpt getMemBarrierOpt() const {
651 assert(Kind == k_MemBarrierOpt && "Invalid access!");
655 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
656 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
660 ARM_PROC::IFlags getProcIFlags() const {
661 assert(Kind == k_ProcIFlags && "Invalid access!");
665 unsigned getMSRMask() const {
666 assert(Kind == k_MSRMask && "Invalid access!");
670 bool isCoprocNum() const { return Kind == k_CoprocNum; }
671 bool isCoprocReg() const { return Kind == k_CoprocReg; }
672 bool isCoprocOption() const { return Kind == k_CoprocOption; }
673 bool isCondCode() const { return Kind == k_CondCode; }
674 bool isCCOut() const { return Kind == k_CCOut; }
675 bool isITMask() const { return Kind == k_ITCondMask; }
676 bool isITCondCode() const { return Kind == k_CondCode; }
677 bool isImm() const { return Kind == k_Immediate; }
678 // checks whether this operand is an unsigned offset which fits is a field
679 // of specified width and scaled by a specific number of bits
680 template<unsigned width, unsigned scale>
681 bool isUnsignedOffset() const {
682 if (!isImm()) return false;
683 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
684 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
685 int64_t Val = CE->getValue();
686 int64_t Align = 1LL << scale;
687 int64_t Max = Align * ((1LL << width) - 1);
688 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
692 // checks whether this operand is an signed offset which fits is a field
693 // of specified width and scaled by a specific number of bits
694 template<unsigned width, unsigned scale>
695 bool isSignedOffset() const {
696 if (!isImm()) return false;
697 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
698 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
699 int64_t Val = CE->getValue();
700 int64_t Align = 1LL << scale;
701 int64_t Max = Align * ((1LL << (width-1)) - 1);
702 int64_t Min = -Align * (1LL << (width-1));
703 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
708 // checks whether this operand is a memory operand computed as an offset
709 // applied to PC. the offset may have 8 bits of magnitude and is represented
710 // with two bits of shift. textually it may be either [pc, #imm], #imm or
711 // relocable expression...
712 bool isThumbMemPC() const {
715 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
716 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
717 if (!CE) return false;
718 Val = CE->getValue();
721 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
722 if(Memory.BaseRegNum != ARM::PC) return false;
723 Val = Memory.OffsetImm->getValue();
726 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
728 bool isFPImm() const {
729 if (!isImm()) return false;
730 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
731 if (!CE) return false;
732 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
735 bool isFBits16() const {
736 if (!isImm()) return false;
737 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
738 if (!CE) return false;
739 int64_t Value = CE->getValue();
740 return Value >= 0 && Value <= 16;
742 bool isFBits32() const {
743 if (!isImm()) return false;
744 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
745 if (!CE) return false;
746 int64_t Value = CE->getValue();
747 return Value >= 1 && Value <= 32;
749 bool isImm8s4() const {
750 if (!isImm()) return false;
751 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
752 if (!CE) return false;
753 int64_t Value = CE->getValue();
754 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
756 bool isImm0_1020s4() const {
757 if (!isImm()) return false;
758 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
759 if (!CE) return false;
760 int64_t Value = CE->getValue();
761 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
763 bool isImm0_508s4() const {
764 if (!isImm()) return false;
765 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
766 if (!CE) return false;
767 int64_t Value = CE->getValue();
768 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
770 bool isImm0_508s4Neg() const {
771 if (!isImm()) return false;
772 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
773 if (!CE) return false;
774 int64_t Value = -CE->getValue();
775 // explicitly exclude zero. we want that to use the normal 0_508 version.
776 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
778 bool isImm0_239() const {
779 if (!isImm()) return false;
780 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
781 if (!CE) return false;
782 int64_t Value = CE->getValue();
783 return Value >= 0 && Value < 240;
785 bool isImm0_255() const {
786 if (!isImm()) return false;
787 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
788 if (!CE) return false;
789 int64_t Value = CE->getValue();
790 return Value >= 0 && Value < 256;
792 bool isImm0_4095() const {
793 if (!isImm()) return false;
794 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
795 if (!CE) return false;
796 int64_t Value = CE->getValue();
797 return Value >= 0 && Value < 4096;
799 bool isImm0_4095Neg() const {
800 if (!isImm()) return false;
801 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
802 if (!CE) return false;
803 int64_t Value = -CE->getValue();
804 return Value > 0 && Value < 4096;
806 bool isImm0_1() const {
807 if (!isImm()) return false;
808 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
809 if (!CE) return false;
810 int64_t Value = CE->getValue();
811 return Value >= 0 && Value < 2;
813 bool isImm0_3() const {
814 if (!isImm()) return false;
815 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
816 if (!CE) return false;
817 int64_t Value = CE->getValue();
818 return Value >= 0 && Value < 4;
820 bool isImm0_7() const {
821 if (!isImm()) return false;
822 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
823 if (!CE) return false;
824 int64_t Value = CE->getValue();
825 return Value >= 0 && Value < 8;
827 bool isImm0_15() const {
828 if (!isImm()) return false;
829 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
830 if (!CE) return false;
831 int64_t Value = CE->getValue();
832 return Value >= 0 && Value < 16;
834 bool isImm0_31() const {
835 if (!isImm()) return false;
836 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
837 if (!CE) return false;
838 int64_t Value = CE->getValue();
839 return Value >= 0 && Value < 32;
841 bool isImm0_63() const {
842 if (!isImm()) return false;
843 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
844 if (!CE) return false;
845 int64_t Value = CE->getValue();
846 return Value >= 0 && Value < 64;
848 bool isImm8() const {
849 if (!isImm()) return false;
850 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
851 if (!CE) return false;
852 int64_t Value = CE->getValue();
855 bool isImm16() const {
856 if (!isImm()) return false;
857 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
858 if (!CE) return false;
859 int64_t Value = CE->getValue();
862 bool isImm32() const {
863 if (!isImm()) return false;
864 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
865 if (!CE) return false;
866 int64_t Value = CE->getValue();
869 bool isShrImm8() const {
870 if (!isImm()) return false;
871 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
872 if (!CE) return false;
873 int64_t Value = CE->getValue();
874 return Value > 0 && Value <= 8;
876 bool isShrImm16() const {
877 if (!isImm()) return false;
878 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
879 if (!CE) return false;
880 int64_t Value = CE->getValue();
881 return Value > 0 && Value <= 16;
883 bool isShrImm32() const {
884 if (!isImm()) return false;
885 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
886 if (!CE) return false;
887 int64_t Value = CE->getValue();
888 return Value > 0 && Value <= 32;
890 bool isShrImm64() const {
891 if (!isImm()) return false;
892 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
893 if (!CE) return false;
894 int64_t Value = CE->getValue();
895 return Value > 0 && Value <= 64;
897 bool isImm1_7() const {
898 if (!isImm()) return false;
899 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
900 if (!CE) return false;
901 int64_t Value = CE->getValue();
902 return Value > 0 && Value < 8;
904 bool isImm1_15() const {
905 if (!isImm()) return false;
906 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
907 if (!CE) return false;
908 int64_t Value = CE->getValue();
909 return Value > 0 && Value < 16;
911 bool isImm1_31() const {
912 if (!isImm()) return false;
913 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
914 if (!CE) return false;
915 int64_t Value = CE->getValue();
916 return Value > 0 && Value < 32;
918 bool isImm1_16() const {
919 if (!isImm()) return false;
920 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
921 if (!CE) return false;
922 int64_t Value = CE->getValue();
923 return Value > 0 && Value < 17;
925 bool isImm1_32() const {
926 if (!isImm()) return false;
927 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
928 if (!CE) return false;
929 int64_t Value = CE->getValue();
930 return Value > 0 && Value < 33;
932 bool isImm0_32() const {
933 if (!isImm()) return false;
934 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
935 if (!CE) return false;
936 int64_t Value = CE->getValue();
937 return Value >= 0 && Value < 33;
939 bool isImm0_65535() const {
940 if (!isImm()) return false;
941 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
942 if (!CE) return false;
943 int64_t Value = CE->getValue();
944 return Value >= 0 && Value < 65536;
946 bool isImm256_65535Expr() const {
947 if (!isImm()) return false;
948 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
949 // If it's not a constant expression, it'll generate a fixup and be
951 if (!CE) return true;
952 int64_t Value = CE->getValue();
953 return Value >= 256 && Value < 65536;
955 bool isImm0_65535Expr() const {
956 if (!isImm()) return false;
957 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
958 // If it's not a constant expression, it'll generate a fixup and be
960 if (!CE) return true;
961 int64_t Value = CE->getValue();
962 return Value >= 0 && Value < 65536;
964 bool isImm24bit() const {
965 if (!isImm()) return false;
966 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
967 if (!CE) return false;
968 int64_t Value = CE->getValue();
969 return Value >= 0 && Value <= 0xffffff;
971 bool isImmThumbSR() const {
972 if (!isImm()) return false;
973 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
974 if (!CE) return false;
975 int64_t Value = CE->getValue();
976 return Value > 0 && Value < 33;
978 bool isPKHLSLImm() const {
979 if (!isImm()) return false;
980 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
981 if (!CE) return false;
982 int64_t Value = CE->getValue();
983 return Value >= 0 && Value < 32;
985 bool isPKHASRImm() const {
986 if (!isImm()) return false;
987 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
988 if (!CE) return false;
989 int64_t Value = CE->getValue();
990 return Value > 0 && Value <= 32;
992 bool isAdrLabel() const {
993 // If we have an immediate that's not a constant, treat it as a label
994 // reference needing a fixup. If it is a constant, but it can't fit
995 // into shift immediate encoding, we reject it.
996 if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
997 else return (isARMSOImm() || isARMSOImmNeg());
999 bool isARMSOImm() const {
1000 if (!isImm()) return false;
1001 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1002 if (!CE) return false;
1003 int64_t Value = CE->getValue();
1004 return ARM_AM::getSOImmVal(Value) != -1;
1006 bool isARMSOImmNot() const {
1007 if (!isImm()) return false;
1008 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1009 if (!CE) return false;
1010 int64_t Value = CE->getValue();
1011 return ARM_AM::getSOImmVal(~Value) != -1;
1013 bool isARMSOImmNeg() const {
1014 if (!isImm()) return false;
1015 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1016 if (!CE) return false;
1017 int64_t Value = CE->getValue();
1018 // Only use this when not representable as a plain so_imm.
1019 return ARM_AM::getSOImmVal(Value) == -1 &&
1020 ARM_AM::getSOImmVal(-Value) != -1;
1022 bool isT2SOImm() const {
1023 if (!isImm()) return false;
1024 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1025 if (!CE) return false;
1026 int64_t Value = CE->getValue();
1027 return ARM_AM::getT2SOImmVal(Value) != -1;
1029 bool isT2SOImmNot() const {
1030 if (!isImm()) return false;
1031 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1032 if (!CE) return false;
1033 int64_t Value = CE->getValue();
1034 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1035 ARM_AM::getT2SOImmVal(~Value) != -1;
1037 bool isT2SOImmNeg() const {
1038 if (!isImm()) return false;
1039 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1040 if (!CE) return false;
1041 int64_t Value = CE->getValue();
1042 // Only use this when not representable as a plain so_imm.
1043 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1044 ARM_AM::getT2SOImmVal(-Value) != -1;
1046 bool isSetEndImm() const {
1047 if (!isImm()) return false;
1048 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1049 if (!CE) return false;
1050 int64_t Value = CE->getValue();
1051 return Value == 1 || Value == 0;
1053 bool isReg() const { return Kind == k_Register; }
1054 bool isRegList() const { return Kind == k_RegisterList; }
1055 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1056 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1057 bool isToken() const { return Kind == k_Token; }
1058 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1059 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1060 bool isMem() const { return Kind == k_Memory; }
1061 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1062 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
1063 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
1064 bool isRotImm() const { return Kind == k_RotateImmediate; }
1065 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1066 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
1067 bool isPostIdxReg() const {
1068 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
1070 bool isMemNoOffset(bool alignOK = false) const {
1073 // No offset of any kind.
1074 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
1075 (alignOK || Memory.Alignment == 0);
1077 bool isMemPCRelImm12() const {
1078 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1080 // Base register must be PC.
1081 if (Memory.BaseRegNum != ARM::PC)
1083 // Immediate offset in range [-4095, 4095].
1084 if (!Memory.OffsetImm) return true;
1085 int64_t Val = Memory.OffsetImm->getValue();
1086 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1088 bool isAlignedMemory() const {
1089 return isMemNoOffset(true);
1091 bool isAddrMode2() const {
1092 if (!isMem() || Memory.Alignment != 0) return false;
1093 // Check for register offset.
1094 if (Memory.OffsetRegNum) return true;
1095 // Immediate offset in range [-4095, 4095].
1096 if (!Memory.OffsetImm) return true;
1097 int64_t Val = Memory.OffsetImm->getValue();
1098 return Val > -4096 && Val < 4096;
1100 bool isAM2OffsetImm() const {
1101 if (!isImm()) return false;
1102 // Immediate offset in range [-4095, 4095].
1103 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1104 if (!CE) return false;
1105 int64_t Val = CE->getValue();
1106 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1108 bool isAddrMode3() const {
1109 // If we have an immediate that's not a constant, treat it as a label
1110 // reference needing a fixup. If it is a constant, it's something else
1111 // and we reject it.
1112 if (isImm() && !isa<MCConstantExpr>(getImm()))
1114 if (!isMem() || Memory.Alignment != 0) return false;
1115 // No shifts are legal for AM3.
1116 if (Memory.ShiftType != ARM_AM::no_shift) return false;
1117 // Check for register offset.
1118 if (Memory.OffsetRegNum) return true;
1119 // Immediate offset in range [-255, 255].
1120 if (!Memory.OffsetImm) return true;
1121 int64_t Val = Memory.OffsetImm->getValue();
1122 // The #-0 offset is encoded as INT32_MIN, and we have to check
1124 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1126 bool isAM3Offset() const {
1127 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1129 if (Kind == k_PostIndexRegister)
1130 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1131 // Immediate offset in range [-255, 255].
1132 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1133 if (!CE) return false;
1134 int64_t Val = CE->getValue();
1135 // Special case, #-0 is INT32_MIN.
1136 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1138 bool isAddrMode5() const {
1139 // If we have an immediate that's not a constant, treat it as a label
1140 // reference needing a fixup. If it is a constant, it's something else
1141 // and we reject it.
1142 if (isImm() && !isa<MCConstantExpr>(getImm()))
1144 if (!isMem() || Memory.Alignment != 0) return false;
1145 // Check for register offset.
1146 if (Memory.OffsetRegNum) return false;
1147 // Immediate offset in range [-1020, 1020] and a multiple of 4.
1148 if (!Memory.OffsetImm) return true;
1149 int64_t Val = Memory.OffsetImm->getValue();
1150 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1153 bool isMemTBB() const {
1154 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1155 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1159 bool isMemTBH() const {
1160 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1161 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1162 Memory.Alignment != 0 )
1166 bool isMemRegOffset() const {
1167 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1171 bool isT2MemRegOffset() const {
1172 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1173 Memory.Alignment != 0)
1175 // Only lsl #{0, 1, 2, 3} allowed.
1176 if (Memory.ShiftType == ARM_AM::no_shift)
1178 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1182 bool isMemThumbRR() const {
1183 // Thumb reg+reg addressing is simple. Just two registers, a base and
1184 // an offset. No shifts, negations or any other complicating factors.
1185 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1186 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1188 return isARMLowRegister(Memory.BaseRegNum) &&
1189 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1191 bool isMemThumbRIs4() const {
1192 if (!isMem() || Memory.OffsetRegNum != 0 ||
1193 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1195 // Immediate offset, multiple of 4 in range [0, 124].
1196 if (!Memory.OffsetImm) return true;
1197 int64_t Val = Memory.OffsetImm->getValue();
1198 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1200 bool isMemThumbRIs2() const {
1201 if (!isMem() || Memory.OffsetRegNum != 0 ||
1202 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1204 // Immediate offset, multiple of 4 in range [0, 62].
1205 if (!Memory.OffsetImm) return true;
1206 int64_t Val = Memory.OffsetImm->getValue();
1207 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1209 bool isMemThumbRIs1() const {
1210 if (!isMem() || Memory.OffsetRegNum != 0 ||
1211 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1213 // Immediate offset in range [0, 31].
1214 if (!Memory.OffsetImm) return true;
1215 int64_t Val = Memory.OffsetImm->getValue();
1216 return Val >= 0 && Val <= 31;
1218 bool isMemThumbSPI() const {
1219 if (!isMem() || Memory.OffsetRegNum != 0 ||
1220 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1222 // Immediate offset, multiple of 4 in range [0, 1020].
1223 if (!Memory.OffsetImm) return true;
1224 int64_t Val = Memory.OffsetImm->getValue();
1225 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1227 bool isMemImm8s4Offset() const {
1228 // If we have an immediate that's not a constant, treat it as a label
1229 // reference needing a fixup. If it is a constant, it's something else
1230 // and we reject it.
1231 if (isImm() && !isa<MCConstantExpr>(getImm()))
1233 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1235 // Immediate offset a multiple of 4 in range [-1020, 1020].
1236 if (!Memory.OffsetImm) return true;
1237 int64_t Val = Memory.OffsetImm->getValue();
1238 // Special case, #-0 is INT32_MIN.
1239 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1241 bool isMemImm0_1020s4Offset() const {
1242 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1244 // Immediate offset a multiple of 4 in range [0, 1020].
1245 if (!Memory.OffsetImm) return true;
1246 int64_t Val = Memory.OffsetImm->getValue();
1247 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1249 bool isMemImm8Offset() const {
1250 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1252 // Base reg of PC isn't allowed for these encodings.
1253 if (Memory.BaseRegNum == ARM::PC) return false;
1254 // Immediate offset in range [-255, 255].
1255 if (!Memory.OffsetImm) return true;
1256 int64_t Val = Memory.OffsetImm->getValue();
1257 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1259 bool isMemPosImm8Offset() const {
1260 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1262 // Immediate offset in range [0, 255].
1263 if (!Memory.OffsetImm) return true;
1264 int64_t Val = Memory.OffsetImm->getValue();
1265 return Val >= 0 && Val < 256;
1267 bool isMemNegImm8Offset() const {
1268 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1270 // Base reg of PC isn't allowed for these encodings.
1271 if (Memory.BaseRegNum == ARM::PC) return false;
1272 // Immediate offset in range [-255, -1].
1273 if (!Memory.OffsetImm) return false;
1274 int64_t Val = Memory.OffsetImm->getValue();
1275 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1277 bool isMemUImm12Offset() const {
1278 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1280 // Immediate offset in range [0, 4095].
1281 if (!Memory.OffsetImm) return true;
1282 int64_t Val = Memory.OffsetImm->getValue();
1283 return (Val >= 0 && Val < 4096);
1285 bool isMemImm12Offset() const {
1286 // If we have an immediate that's not a constant, treat it as a label
1287 // reference needing a fixup. If it is a constant, it's something else
1288 // and we reject it.
1289 if (isImm() && !isa<MCConstantExpr>(getImm()))
1292 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1294 // Immediate offset in range [-4095, 4095].
1295 if (!Memory.OffsetImm) return true;
1296 int64_t Val = Memory.OffsetImm->getValue();
1297 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1299 bool isPostIdxImm8() const {
1300 if (!isImm()) return false;
1301 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1302 if (!CE) return false;
1303 int64_t Val = CE->getValue();
1304 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1306 bool isPostIdxImm8s4() const {
1307 if (!isImm()) return false;
1308 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1309 if (!CE) return false;
1310 int64_t Val = CE->getValue();
1311 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1315 bool isMSRMask() const { return Kind == k_MSRMask; }
1316 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1319 bool isSingleSpacedVectorList() const {
1320 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1322 bool isDoubleSpacedVectorList() const {
1323 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1325 bool isVecListOneD() const {
1326 if (!isSingleSpacedVectorList()) return false;
1327 return VectorList.Count == 1;
1330 bool isVecListDPair() const {
1331 if (!isSingleSpacedVectorList()) return false;
1332 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1333 .contains(VectorList.RegNum));
1336 bool isVecListThreeD() const {
1337 if (!isSingleSpacedVectorList()) return false;
1338 return VectorList.Count == 3;
1341 bool isVecListFourD() const {
1342 if (!isSingleSpacedVectorList()) return false;
1343 return VectorList.Count == 4;
1346 bool isVecListDPairSpaced() const {
1347 if (isSingleSpacedVectorList()) return false;
1348 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1349 .contains(VectorList.RegNum));
1352 bool isVecListThreeQ() const {
1353 if (!isDoubleSpacedVectorList()) return false;
1354 return VectorList.Count == 3;
1357 bool isVecListFourQ() const {
1358 if (!isDoubleSpacedVectorList()) return false;
1359 return VectorList.Count == 4;
1362 bool isSingleSpacedVectorAllLanes() const {
1363 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1365 bool isDoubleSpacedVectorAllLanes() const {
1366 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1368 bool isVecListOneDAllLanes() const {
1369 if (!isSingleSpacedVectorAllLanes()) return false;
1370 return VectorList.Count == 1;
1373 bool isVecListDPairAllLanes() const {
1374 if (!isSingleSpacedVectorAllLanes()) return false;
1375 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1376 .contains(VectorList.RegNum));
1379 bool isVecListDPairSpacedAllLanes() const {
1380 if (!isDoubleSpacedVectorAllLanes()) return false;
1381 return VectorList.Count == 2;
1384 bool isVecListThreeDAllLanes() const {
1385 if (!isSingleSpacedVectorAllLanes()) return false;
1386 return VectorList.Count == 3;
1389 bool isVecListThreeQAllLanes() const {
1390 if (!isDoubleSpacedVectorAllLanes()) return false;
1391 return VectorList.Count == 3;
1394 bool isVecListFourDAllLanes() const {
1395 if (!isSingleSpacedVectorAllLanes()) return false;
1396 return VectorList.Count == 4;
1399 bool isVecListFourQAllLanes() const {
1400 if (!isDoubleSpacedVectorAllLanes()) return false;
1401 return VectorList.Count == 4;
1404 bool isSingleSpacedVectorIndexed() const {
1405 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1407 bool isDoubleSpacedVectorIndexed() const {
1408 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1410 bool isVecListOneDByteIndexed() const {
1411 if (!isSingleSpacedVectorIndexed()) return false;
1412 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1415 bool isVecListOneDHWordIndexed() const {
1416 if (!isSingleSpacedVectorIndexed()) return false;
1417 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1420 bool isVecListOneDWordIndexed() const {
1421 if (!isSingleSpacedVectorIndexed()) return false;
1422 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1425 bool isVecListTwoDByteIndexed() const {
1426 if (!isSingleSpacedVectorIndexed()) return false;
1427 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1430 bool isVecListTwoDHWordIndexed() const {
1431 if (!isSingleSpacedVectorIndexed()) return false;
1432 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1435 bool isVecListTwoQWordIndexed() const {
1436 if (!isDoubleSpacedVectorIndexed()) return false;
1437 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1440 bool isVecListTwoQHWordIndexed() const {
1441 if (!isDoubleSpacedVectorIndexed()) return false;
1442 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1445 bool isVecListTwoDWordIndexed() const {
1446 if (!isSingleSpacedVectorIndexed()) return false;
1447 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1450 bool isVecListThreeDByteIndexed() const {
1451 if (!isSingleSpacedVectorIndexed()) return false;
1452 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1455 bool isVecListThreeDHWordIndexed() const {
1456 if (!isSingleSpacedVectorIndexed()) return false;
1457 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1460 bool isVecListThreeQWordIndexed() const {
1461 if (!isDoubleSpacedVectorIndexed()) return false;
1462 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1465 bool isVecListThreeQHWordIndexed() const {
1466 if (!isDoubleSpacedVectorIndexed()) return false;
1467 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1470 bool isVecListThreeDWordIndexed() const {
1471 if (!isSingleSpacedVectorIndexed()) return false;
1472 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1475 bool isVecListFourDByteIndexed() const {
1476 if (!isSingleSpacedVectorIndexed()) return false;
1477 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1480 bool isVecListFourDHWordIndexed() const {
1481 if (!isSingleSpacedVectorIndexed()) return false;
1482 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1485 bool isVecListFourQWordIndexed() const {
1486 if (!isDoubleSpacedVectorIndexed()) return false;
1487 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1490 bool isVecListFourQHWordIndexed() const {
1491 if (!isDoubleSpacedVectorIndexed()) return false;
1492 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1495 bool isVecListFourDWordIndexed() const {
1496 if (!isSingleSpacedVectorIndexed()) return false;
1497 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1500 bool isVectorIndex8() const {
1501 if (Kind != k_VectorIndex) return false;
1502 return VectorIndex.Val < 8;
1504 bool isVectorIndex16() const {
1505 if (Kind != k_VectorIndex) return false;
1506 return VectorIndex.Val < 4;
1508 bool isVectorIndex32() const {
1509 if (Kind != k_VectorIndex) return false;
1510 return VectorIndex.Val < 2;
1513 bool isNEONi8splat() const {
1514 if (!isImm()) return false;
1515 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1516 // Must be a constant.
1517 if (!CE) return false;
1518 int64_t Value = CE->getValue();
1519 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1521 return Value >= 0 && Value < 256;
1524 bool isNEONi16splat() const {
1525 if (!isImm()) return false;
1526 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1527 // Must be a constant.
1528 if (!CE) return false;
1529 int64_t Value = CE->getValue();
1530 // i16 value in the range [0,255] or [0x0100, 0xff00]
1531 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1534 bool isNEONi32splat() const {
1535 if (!isImm()) return false;
1536 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1537 // Must be a constant.
1538 if (!CE) return false;
1539 int64_t Value = CE->getValue();
1540 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1541 return (Value >= 0 && Value < 256) ||
1542 (Value >= 0x0100 && Value <= 0xff00) ||
1543 (Value >= 0x010000 && Value <= 0xff0000) ||
1544 (Value >= 0x01000000 && Value <= 0xff000000);
1547 bool isNEONi32vmov() const {
1548 if (!isImm()) return false;
1549 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1550 // Must be a constant.
1551 if (!CE) return false;
1552 int64_t Value = CE->getValue();
1553 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1554 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1555 return (Value >= 0 && Value < 256) ||
1556 (Value >= 0x0100 && Value <= 0xff00) ||
1557 (Value >= 0x010000 && Value <= 0xff0000) ||
1558 (Value >= 0x01000000 && Value <= 0xff000000) ||
1559 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1560 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1562 bool isNEONi32vmovNeg() const {
1563 if (!isImm()) return false;
1564 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1565 // Must be a constant.
1566 if (!CE) return false;
1567 int64_t Value = ~CE->getValue();
1568 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1569 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1570 return (Value >= 0 && Value < 256) ||
1571 (Value >= 0x0100 && Value <= 0xff00) ||
1572 (Value >= 0x010000 && Value <= 0xff0000) ||
1573 (Value >= 0x01000000 && Value <= 0xff000000) ||
1574 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1575 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1578 bool isNEONi64splat() const {
1579 if (!isImm()) return false;
1580 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1581 // Must be a constant.
1582 if (!CE) return false;
1583 uint64_t Value = CE->getValue();
1584 // i64 value with each byte being either 0 or 0xff.
1585 for (unsigned i = 0; i < 8; ++i)
1586 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1590 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1591 // Add as immediates when possible. Null MCExpr = 0.
1593 Inst.addOperand(MCOperand::CreateImm(0));
1594 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1595 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1597 Inst.addOperand(MCOperand::CreateExpr(Expr));
1600 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1601 assert(N == 2 && "Invalid number of operands!");
1602 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1603 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1604 Inst.addOperand(MCOperand::CreateReg(RegNum));
1607 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1608 assert(N == 1 && "Invalid number of operands!");
1609 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1612 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1613 assert(N == 1 && "Invalid number of operands!");
1614 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1617 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1618 assert(N == 1 && "Invalid number of operands!");
1619 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1622 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1623 assert(N == 1 && "Invalid number of operands!");
1624 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1627 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1628 assert(N == 1 && "Invalid number of operands!");
1629 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1632 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1633 assert(N == 1 && "Invalid number of operands!");
1634 Inst.addOperand(MCOperand::CreateReg(getReg()));
1637 void addRegOperands(MCInst &Inst, unsigned N) const {
1638 assert(N == 1 && "Invalid number of operands!");
1639 Inst.addOperand(MCOperand::CreateReg(getReg()));
1642 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1643 assert(N == 3 && "Invalid number of operands!");
1644 assert(isRegShiftedReg() &&
1645 "addRegShiftedRegOperands() on non-RegShiftedReg!");
1646 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1647 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1648 Inst.addOperand(MCOperand::CreateImm(
1649 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1652 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1653 assert(N == 2 && "Invalid number of operands!");
1654 assert(isRegShiftedImm() &&
1655 "addRegShiftedImmOperands() on non-RegShiftedImm!");
1656 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1657 // Shift of #32 is encoded as 0 where permitted
1658 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1659 Inst.addOperand(MCOperand::CreateImm(
1660 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1663 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1664 assert(N == 1 && "Invalid number of operands!");
1665 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1669 void addRegListOperands(MCInst &Inst, unsigned N) const {
1670 assert(N == 1 && "Invalid number of operands!");
1671 const SmallVectorImpl<unsigned> &RegList = getRegList();
1672 for (SmallVectorImpl<unsigned>::const_iterator
1673 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1674 Inst.addOperand(MCOperand::CreateReg(*I));
1677 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1678 addRegListOperands(Inst, N);
1681 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1682 addRegListOperands(Inst, N);
1685 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1686 assert(N == 1 && "Invalid number of operands!");
1687 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1688 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1691 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1692 assert(N == 1 && "Invalid number of operands!");
1693 // Munge the lsb/width into a bitfield mask.
1694 unsigned lsb = Bitfield.LSB;
1695 unsigned width = Bitfield.Width;
1696 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1697 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1698 (32 - (lsb + width)));
1699 Inst.addOperand(MCOperand::CreateImm(Mask));
1702 void addImmOperands(MCInst &Inst, unsigned N) const {
1703 assert(N == 1 && "Invalid number of operands!");
1704 addExpr(Inst, getImm());
1707 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1708 assert(N == 1 && "Invalid number of operands!");
1709 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1710 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1713 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1714 assert(N == 1 && "Invalid number of operands!");
1715 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1716 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1719 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1720 assert(N == 1 && "Invalid number of operands!");
1721 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1722 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1723 Inst.addOperand(MCOperand::CreateImm(Val));
1726 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1727 assert(N == 1 && "Invalid number of operands!");
1728 // FIXME: We really want to scale the value here, but the LDRD/STRD
1729 // instruction don't encode operands that way yet.
1730 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1731 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1734 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1735 assert(N == 1 && "Invalid number of operands!");
1736 // The immediate is scaled by four in the encoding and is stored
1737 // in the MCInst as such. Lop off the low two bits here.
1738 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1739 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1742 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1743 assert(N == 1 && "Invalid number of operands!");
1744 // The immediate is scaled by four in the encoding and is stored
1745 // in the MCInst as such. Lop off the low two bits here.
1746 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1747 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1750 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1751 assert(N == 1 && "Invalid number of operands!");
1752 // The immediate is scaled by four in the encoding and is stored
1753 // in the MCInst as such. Lop off the low two bits here.
1754 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1755 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1758 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1759 assert(N == 1 && "Invalid number of operands!");
1760 // The constant encodes as the immediate-1, and we store in the instruction
1761 // the bits as encoded, so subtract off one here.
1762 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1763 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1766 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1767 assert(N == 1 && "Invalid number of operands!");
1768 // The constant encodes as the immediate-1, and we store in the instruction
1769 // the bits as encoded, so subtract off one here.
1770 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1771 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1774 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1775 assert(N == 1 && "Invalid number of operands!");
1776 // The constant encodes as the immediate, except for 32, which encodes as
1778 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1779 unsigned Imm = CE->getValue();
1780 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1783 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1784 assert(N == 1 && "Invalid number of operands!");
1785 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1786 // the instruction as well.
1787 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1788 int Val = CE->getValue();
1789 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1792 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1793 assert(N == 1 && "Invalid number of operands!");
1794 // The operand is actually a t2_so_imm, but we have its bitwise
1795 // negation in the assembly source, so twiddle it here.
1796 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1797 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1800 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1801 assert(N == 1 && "Invalid number of operands!");
1802 // The operand is actually a t2_so_imm, but we have its
1803 // negation in the assembly source, so twiddle it here.
1804 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1805 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1808 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1809 assert(N == 1 && "Invalid number of operands!");
1810 // The operand is actually an imm0_4095, but we have its
1811 // negation in the assembly source, so twiddle it here.
1812 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1813 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1816 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1817 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1818 Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
1822 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1823 assert(SR && "Unknown value type!");
1824 Inst.addOperand(MCOperand::CreateExpr(SR));
1827 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
1828 assert(N == 1 && "Invalid number of operands!");
1830 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1832 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1836 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1837 assert(SR && "Unknown value type!");
1838 Inst.addOperand(MCOperand::CreateExpr(SR));
1842 assert(isMem() && "Unknown value type!");
1843 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
1844 Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
1847 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1848 assert(N == 1 && "Invalid number of operands!");
1849 // The operand is actually a so_imm, but we have its bitwise
1850 // negation in the assembly source, so twiddle it here.
1851 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1852 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1855 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1856 assert(N == 1 && "Invalid number of operands!");
1857 // The operand is actually a so_imm, but we have its
1858 // negation in the assembly source, so twiddle it here.
1859 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1860 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1863 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1864 assert(N == 1 && "Invalid number of operands!");
1865 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1868 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
1869 assert(N == 1 && "Invalid number of operands!");
1870 Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
1873 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1874 assert(N == 1 && "Invalid number of operands!");
1875 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1878 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1879 assert(N == 1 && "Invalid number of operands!");
1880 int32_t Imm = Memory.OffsetImm->getValue();
1881 Inst.addOperand(MCOperand::CreateImm(Imm));
1884 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1885 assert(N == 1 && "Invalid number of operands!");
1886 assert(isImm() && "Not an immediate!");
1888 // If we have an immediate that's not a constant, treat it as a label
1889 // reference needing a fixup.
1890 if (!isa<MCConstantExpr>(getImm())) {
1891 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1895 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1896 int Val = CE->getValue();
1897 Inst.addOperand(MCOperand::CreateImm(Val));
1900 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1901 assert(N == 2 && "Invalid number of operands!");
1902 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1903 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1906 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1907 assert(N == 3 && "Invalid number of operands!");
1908 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1909 if (!Memory.OffsetRegNum) {
1910 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1911 // Special case for #-0
1912 if (Val == INT32_MIN) Val = 0;
1913 if (Val < 0) Val = -Val;
1914 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1916 // For register offset, we encode the shift type and negation flag
1918 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1919 Memory.ShiftImm, Memory.ShiftType);
1921 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1922 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1923 Inst.addOperand(MCOperand::CreateImm(Val));
1926 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1927 assert(N == 2 && "Invalid number of operands!");
1928 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1929 assert(CE && "non-constant AM2OffsetImm operand!");
1930 int32_t Val = CE->getValue();
1931 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1932 // Special case for #-0
1933 if (Val == INT32_MIN) Val = 0;
1934 if (Val < 0) Val = -Val;
1935 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1936 Inst.addOperand(MCOperand::CreateReg(0));
1937 Inst.addOperand(MCOperand::CreateImm(Val));
1940 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1941 assert(N == 3 && "Invalid number of operands!");
1942 // If we have an immediate that's not a constant, treat it as a label
1943 // reference needing a fixup. If it is a constant, it's something else
1944 // and we reject it.
1946 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1947 Inst.addOperand(MCOperand::CreateReg(0));
1948 Inst.addOperand(MCOperand::CreateImm(0));
1952 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1953 if (!Memory.OffsetRegNum) {
1954 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1955 // Special case for #-0
1956 if (Val == INT32_MIN) Val = 0;
1957 if (Val < 0) Val = -Val;
1958 Val = ARM_AM::getAM3Opc(AddSub, Val);
1960 // For register offset, we encode the shift type and negation flag
1962 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1964 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1965 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1966 Inst.addOperand(MCOperand::CreateImm(Val));
1969 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1970 assert(N == 2 && "Invalid number of operands!");
1971 if (Kind == k_PostIndexRegister) {
1973 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1974 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1975 Inst.addOperand(MCOperand::CreateImm(Val));
1980 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1981 int32_t Val = CE->getValue();
1982 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1983 // Special case for #-0
1984 if (Val == INT32_MIN) Val = 0;
1985 if (Val < 0) Val = -Val;
1986 Val = ARM_AM::getAM3Opc(AddSub, Val);
1987 Inst.addOperand(MCOperand::CreateReg(0));
1988 Inst.addOperand(MCOperand::CreateImm(Val));
1991 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1992 assert(N == 2 && "Invalid number of operands!");
1993 // If we have an immediate that's not a constant, treat it as a label
1994 // reference needing a fixup. If it is a constant, it's something else
1995 // and we reject it.
1997 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1998 Inst.addOperand(MCOperand::CreateImm(0));
2002 // The lower two bits are always zero and as such are not encoded.
2003 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2004 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2005 // Special case for #-0
2006 if (Val == INT32_MIN) Val = 0;
2007 if (Val < 0) Val = -Val;
2008 Val = ARM_AM::getAM5Opc(AddSub, Val);
2009 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2010 Inst.addOperand(MCOperand::CreateImm(Val));
2013 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2014 assert(N == 2 && "Invalid number of operands!");
2015 // If we have an immediate that's not a constant, treat it as a label
2016 // reference needing a fixup. If it is a constant, it's something else
2017 // and we reject it.
2019 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2020 Inst.addOperand(MCOperand::CreateImm(0));
2024 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2025 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2026 Inst.addOperand(MCOperand::CreateImm(Val));
2029 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2030 assert(N == 2 && "Invalid number of operands!");
2031 // The lower two bits are always zero and as such are not encoded.
2032 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2033 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2034 Inst.addOperand(MCOperand::CreateImm(Val));
2037 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2038 assert(N == 2 && "Invalid number of operands!");
2039 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2040 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2041 Inst.addOperand(MCOperand::CreateImm(Val));
2044 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2045 addMemImm8OffsetOperands(Inst, N);
2048 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2049 addMemImm8OffsetOperands(Inst, N);
2052 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2053 assert(N == 2 && "Invalid number of operands!");
2054 // If this is an immediate, it's a label reference.
2056 addExpr(Inst, getImm());
2057 Inst.addOperand(MCOperand::CreateImm(0));
2061 // Otherwise, it's a normal memory reg+offset.
2062 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2063 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2064 Inst.addOperand(MCOperand::CreateImm(Val));
2067 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2068 assert(N == 2 && "Invalid number of operands!");
2069 // If this is an immediate, it's a label reference.
2071 addExpr(Inst, getImm());
2072 Inst.addOperand(MCOperand::CreateImm(0));
2076 // Otherwise, it's a normal memory reg+offset.
2077 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2078 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2079 Inst.addOperand(MCOperand::CreateImm(Val));
2082 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2083 assert(N == 2 && "Invalid number of operands!");
2084 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2085 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2088 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2089 assert(N == 2 && "Invalid number of operands!");
2090 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2091 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2094 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2095 assert(N == 3 && "Invalid number of operands!");
2097 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2098 Memory.ShiftImm, Memory.ShiftType);
2099 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2100 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2101 Inst.addOperand(MCOperand::CreateImm(Val));
2104 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2105 assert(N == 3 && "Invalid number of operands!");
2106 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2107 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2108 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
2111 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2112 assert(N == 2 && "Invalid number of operands!");
2113 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2114 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2117 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2118 assert(N == 2 && "Invalid number of operands!");
2119 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2120 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2121 Inst.addOperand(MCOperand::CreateImm(Val));
2124 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2125 assert(N == 2 && "Invalid number of operands!");
2126 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2127 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2128 Inst.addOperand(MCOperand::CreateImm(Val));
2131 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2132 assert(N == 2 && "Invalid number of operands!");
2133 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2134 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2135 Inst.addOperand(MCOperand::CreateImm(Val));
2138 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2139 assert(N == 2 && "Invalid number of operands!");
2140 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2141 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2142 Inst.addOperand(MCOperand::CreateImm(Val));
2145 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2146 assert(N == 1 && "Invalid number of operands!");
2147 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2148 assert(CE && "non-constant post-idx-imm8 operand!");
2149 int Imm = CE->getValue();
2150 bool isAdd = Imm >= 0;
2151 if (Imm == INT32_MIN) Imm = 0;
2152 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2153 Inst.addOperand(MCOperand::CreateImm(Imm));
2156 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2157 assert(N == 1 && "Invalid number of operands!");
2158 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2159 assert(CE && "non-constant post-idx-imm8s4 operand!");
2160 int Imm = CE->getValue();
2161 bool isAdd = Imm >= 0;
2162 if (Imm == INT32_MIN) Imm = 0;
2163 // Immediate is scaled by 4.
2164 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2165 Inst.addOperand(MCOperand::CreateImm(Imm));
2168 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2169 assert(N == 2 && "Invalid number of operands!");
2170 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2171 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2174 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2175 assert(N == 2 && "Invalid number of operands!");
2176 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2177 // The sign, shift type, and shift amount are encoded in a single operand
2178 // using the AM2 encoding helpers.
2179 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2180 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2181 PostIdxReg.ShiftTy);
2182 Inst.addOperand(MCOperand::CreateImm(Imm));
2185 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2186 assert(N == 1 && "Invalid number of operands!");
2187 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2190 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2191 assert(N == 1 && "Invalid number of operands!");
2192 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2195 void addVecListOperands(MCInst &Inst, unsigned N) const {
2196 assert(N == 1 && "Invalid number of operands!");
2197 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2200 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2201 assert(N == 2 && "Invalid number of operands!");
2202 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2203 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2206 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2207 assert(N == 1 && "Invalid number of operands!");
2208 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2211 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2212 assert(N == 1 && "Invalid number of operands!");
2213 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2216 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2217 assert(N == 1 && "Invalid number of operands!");
2218 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2221 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2222 assert(N == 1 && "Invalid number of operands!");
2223 // The immediate encodes the type of constant as well as the value.
2224 // Mask in that this is an i8 splat.
2225 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2226 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2229 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2230 assert(N == 1 && "Invalid number of operands!");
2231 // The immediate encodes the type of constant as well as the value.
2232 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2233 unsigned Value = CE->getValue();
2235 Value = (Value >> 8) | 0xa00;
2238 Inst.addOperand(MCOperand::CreateImm(Value));
2241 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2242 assert(N == 1 && "Invalid number of operands!");
2243 // The immediate encodes the type of constant as well as the value.
2244 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2245 unsigned Value = CE->getValue();
2246 if (Value >= 256 && Value <= 0xff00)
2247 Value = (Value >> 8) | 0x200;
2248 else if (Value > 0xffff && Value <= 0xff0000)
2249 Value = (Value >> 16) | 0x400;
2250 else if (Value > 0xffffff)
2251 Value = (Value >> 24) | 0x600;
2252 Inst.addOperand(MCOperand::CreateImm(Value));
2255 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2256 assert(N == 1 && "Invalid number of operands!");
2257 // The immediate encodes the type of constant as well as the value.
2258 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2259 unsigned Value = CE->getValue();
2260 if (Value >= 256 && Value <= 0xffff)
2261 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2262 else if (Value > 0xffff && Value <= 0xffffff)
2263 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2264 else if (Value > 0xffffff)
2265 Value = (Value >> 24) | 0x600;
2266 Inst.addOperand(MCOperand::CreateImm(Value));
2269 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2270 assert(N == 1 && "Invalid number of operands!");
2271 // The immediate encodes the type of constant as well as the value.
2272 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2273 unsigned Value = ~CE->getValue();
2274 if (Value >= 256 && Value <= 0xffff)
2275 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2276 else if (Value > 0xffff && Value <= 0xffffff)
2277 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2278 else if (Value > 0xffffff)
2279 Value = (Value >> 24) | 0x600;
2280 Inst.addOperand(MCOperand::CreateImm(Value));
2283 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2284 assert(N == 1 && "Invalid number of operands!");
2285 // The immediate encodes the type of constant as well as the value.
2286 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2287 uint64_t Value = CE->getValue();
2289 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2290 Imm |= (Value & 1) << i;
2292 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2295 virtual void print(raw_ostream &OS) const;
2297 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2298 ARMOperand *Op = new ARMOperand(k_ITCondMask);
2299 Op->ITMask.Mask = Mask;
2305 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2306 ARMOperand *Op = new ARMOperand(k_CondCode);
2313 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2314 ARMOperand *Op = new ARMOperand(k_CoprocNum);
2315 Op->Cop.Val = CopVal;
2321 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2322 ARMOperand *Op = new ARMOperand(k_CoprocReg);
2323 Op->Cop.Val = CopVal;
2329 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2330 ARMOperand *Op = new ARMOperand(k_CoprocOption);
2337 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2338 ARMOperand *Op = new ARMOperand(k_CCOut);
2339 Op->Reg.RegNum = RegNum;
2345 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2346 ARMOperand *Op = new ARMOperand(k_Token);
2347 Op->Tok.Data = Str.data();
2348 Op->Tok.Length = Str.size();
2354 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2355 ARMOperand *Op = new ARMOperand(k_Register);
2356 Op->Reg.RegNum = RegNum;
2362 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2367 ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2368 Op->RegShiftedReg.ShiftTy = ShTy;
2369 Op->RegShiftedReg.SrcReg = SrcReg;
2370 Op->RegShiftedReg.ShiftReg = ShiftReg;
2371 Op->RegShiftedReg.ShiftImm = ShiftImm;
2377 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2381 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2382 Op->RegShiftedImm.ShiftTy = ShTy;
2383 Op->RegShiftedImm.SrcReg = SrcReg;
2384 Op->RegShiftedImm.ShiftImm = ShiftImm;
2390 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2392 ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2393 Op->ShifterImm.isASR = isASR;
2394 Op->ShifterImm.Imm = Imm;
2400 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2401 ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2402 Op->RotImm.Imm = Imm;
2408 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2410 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2411 Op->Bitfield.LSB = LSB;
2412 Op->Bitfield.Width = Width;
2419 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned> > &Regs,
2420 SMLoc StartLoc, SMLoc EndLoc) {
2421 assert (Regs.size() > 0 && "RegList contains no registers?");
2422 KindTy Kind = k_RegisterList;
2424 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2425 Kind = k_DPRRegisterList;
2426 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2427 contains(Regs.front().second))
2428 Kind = k_SPRRegisterList;
2430 // Sort based on the register encoding values.
2431 array_pod_sort(Regs.begin(), Regs.end());
2433 ARMOperand *Op = new ARMOperand(Kind);
2434 for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2435 I = Regs.begin(), E = Regs.end(); I != E; ++I)
2436 Op->Registers.push_back(I->second);
2437 Op->StartLoc = StartLoc;
2438 Op->EndLoc = EndLoc;
2442 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2443 bool isDoubleSpaced, SMLoc S, SMLoc E) {
2444 ARMOperand *Op = new ARMOperand(k_VectorList);
2445 Op->VectorList.RegNum = RegNum;
2446 Op->VectorList.Count = Count;
2447 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2453 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2454 bool isDoubleSpaced,
2456 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2457 Op->VectorList.RegNum = RegNum;
2458 Op->VectorList.Count = Count;
2459 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2465 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2467 bool isDoubleSpaced,
2469 ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2470 Op->VectorList.RegNum = RegNum;
2471 Op->VectorList.Count = Count;
2472 Op->VectorList.LaneIndex = Index;
2473 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2479 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2481 ARMOperand *Op = new ARMOperand(k_VectorIndex);
2482 Op->VectorIndex.Val = Idx;
2488 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2489 ARMOperand *Op = new ARMOperand(k_Immediate);
2496 static ARMOperand *CreateMem(unsigned BaseRegNum,
2497 const MCConstantExpr *OffsetImm,
2498 unsigned OffsetRegNum,
2499 ARM_AM::ShiftOpc ShiftType,
2504 ARMOperand *Op = new ARMOperand(k_Memory);
2505 Op->Memory.BaseRegNum = BaseRegNum;
2506 Op->Memory.OffsetImm = OffsetImm;
2507 Op->Memory.OffsetRegNum = OffsetRegNum;
2508 Op->Memory.ShiftType = ShiftType;
2509 Op->Memory.ShiftImm = ShiftImm;
2510 Op->Memory.Alignment = Alignment;
2511 Op->Memory.isNegative = isNegative;
2517 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2518 ARM_AM::ShiftOpc ShiftTy,
2521 ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2522 Op->PostIdxReg.RegNum = RegNum;
2523 Op->PostIdxReg.isAdd = isAdd;
2524 Op->PostIdxReg.ShiftTy = ShiftTy;
2525 Op->PostIdxReg.ShiftImm = ShiftImm;
2531 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2532 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2533 Op->MBOpt.Val = Opt;
2539 static ARMOperand *CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt,
2541 ARMOperand *Op = new ARMOperand(k_InstSyncBarrierOpt);
2542 Op->ISBOpt.Val = Opt;
2548 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2549 ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2550 Op->IFlags.Val = IFlags;
2556 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2557 ARMOperand *Op = new ARMOperand(k_MSRMask);
2558 Op->MMask.Val = MMask;
2565 } // end anonymous namespace.
2567 void ARMOperand::print(raw_ostream &OS) const {
2570 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2573 OS << "<ccout " << getReg() << ">";
2575 case k_ITCondMask: {
2576 static const char *const MaskStr[] = {
2577 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2578 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2580 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2581 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2585 OS << "<coprocessor number: " << getCoproc() << ">";
2588 OS << "<coprocessor register: " << getCoproc() << ">";
2590 case k_CoprocOption:
2591 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2594 OS << "<mask: " << getMSRMask() << ">";
2597 getImm()->print(OS);
2599 case k_MemBarrierOpt:
2600 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
2602 case k_InstSyncBarrierOpt:
2603 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2607 << " base:" << Memory.BaseRegNum;
2610 case k_PostIndexRegister:
2611 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2612 << PostIdxReg.RegNum;
2613 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2614 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2615 << PostIdxReg.ShiftImm;
2618 case k_ProcIFlags: {
2619 OS << "<ARM_PROC::";
2620 unsigned IFlags = getProcIFlags();
2621 for (int i=2; i >= 0; --i)
2622 if (IFlags & (1 << i))
2623 OS << ARM_PROC::IFlagsToString(1 << i);
2628 OS << "<register " << getReg() << ">";
2630 case k_ShifterImmediate:
2631 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2632 << " #" << ShifterImm.Imm << ">";
2634 case k_ShiftedRegister:
2635 OS << "<so_reg_reg "
2636 << RegShiftedReg.SrcReg << " "
2637 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2638 << " " << RegShiftedReg.ShiftReg << ">";
2640 case k_ShiftedImmediate:
2641 OS << "<so_reg_imm "
2642 << RegShiftedImm.SrcReg << " "
2643 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2644 << " #" << RegShiftedImm.ShiftImm << ">";
2646 case k_RotateImmediate:
2647 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2649 case k_BitfieldDescriptor:
2650 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2651 << ", width: " << Bitfield.Width << ">";
2653 case k_RegisterList:
2654 case k_DPRRegisterList:
2655 case k_SPRRegisterList: {
2656 OS << "<register_list ";
2658 const SmallVectorImpl<unsigned> &RegList = getRegList();
2659 for (SmallVectorImpl<unsigned>::const_iterator
2660 I = RegList.begin(), E = RegList.end(); I != E; ) {
2662 if (++I < E) OS << ", ";
2669 OS << "<vector_list " << VectorList.Count << " * "
2670 << VectorList.RegNum << ">";
2672 case k_VectorListAllLanes:
2673 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2674 << VectorList.RegNum << ">";
2676 case k_VectorListIndexed:
2677 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2678 << VectorList.Count << " * " << VectorList.RegNum << ">";
2681 OS << "'" << getToken() << "'";
2684 OS << "<vectorindex " << getVectorIndex() << ">";
2689 /// @name Auto-generated Match Functions
2692 static unsigned MatchRegisterName(StringRef Name);
2696 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2697 SMLoc &StartLoc, SMLoc &EndLoc) {
2698 StartLoc = Parser.getTok().getLoc();
2699 EndLoc = Parser.getTok().getEndLoc();
2700 RegNo = tryParseRegister();
2702 return (RegNo == (unsigned)-1);
2705 /// Try to parse a register name. The token must be an Identifier when called,
2706 /// and if it is a register name the token is eaten and the register number is
2707 /// returned. Otherwise return -1.
2709 int ARMAsmParser::tryParseRegister() {
2710 const AsmToken &Tok = Parser.getTok();
2711 if (Tok.isNot(AsmToken::Identifier)) return -1;
2713 std::string lowerCase = Tok.getString().lower();
2714 unsigned RegNum = MatchRegisterName(lowerCase);
2716 RegNum = StringSwitch<unsigned>(lowerCase)
2717 .Case("r13", ARM::SP)
2718 .Case("r14", ARM::LR)
2719 .Case("r15", ARM::PC)
2720 .Case("ip", ARM::R12)
2721 // Additional register name aliases for 'gas' compatibility.
2722 .Case("a1", ARM::R0)
2723 .Case("a2", ARM::R1)
2724 .Case("a3", ARM::R2)
2725 .Case("a4", ARM::R3)
2726 .Case("v1", ARM::R4)
2727 .Case("v2", ARM::R5)
2728 .Case("v3", ARM::R6)
2729 .Case("v4", ARM::R7)
2730 .Case("v5", ARM::R8)
2731 .Case("v6", ARM::R9)
2732 .Case("v7", ARM::R10)
2733 .Case("v8", ARM::R11)
2734 .Case("sb", ARM::R9)
2735 .Case("sl", ARM::R10)
2736 .Case("fp", ARM::R11)
2740 // Check for aliases registered via .req. Canonicalize to lower case.
2741 // That's more consistent since register names are case insensitive, and
2742 // it's how the original entry was passed in from MC/MCParser/AsmParser.
2743 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2744 // If no match, return failure.
2745 if (Entry == RegisterReqs.end())
2747 Parser.Lex(); // Eat identifier token.
2748 return Entry->getValue();
2751 Parser.Lex(); // Eat identifier token.
2756 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
2757 // If a recoverable error occurs, return 1. If an irrecoverable error
2758 // occurs, return -1. An irrecoverable error is one where tokens have been
2759 // consumed in the process of trying to parse the shifter (i.e., when it is
2760 // indeed a shifter operand, but malformed).
2761 int ARMAsmParser::tryParseShiftRegister(
2762 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2763 SMLoc S = Parser.getTok().getLoc();
2764 const AsmToken &Tok = Parser.getTok();
2765 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2767 std::string lowerCase = Tok.getString().lower();
2768 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2769 .Case("asl", ARM_AM::lsl)
2770 .Case("lsl", ARM_AM::lsl)
2771 .Case("lsr", ARM_AM::lsr)
2772 .Case("asr", ARM_AM::asr)
2773 .Case("ror", ARM_AM::ror)
2774 .Case("rrx", ARM_AM::rrx)
2775 .Default(ARM_AM::no_shift);
2777 if (ShiftTy == ARM_AM::no_shift)
2780 Parser.Lex(); // Eat the operator.
2782 // The source register for the shift has already been added to the
2783 // operand list, so we need to pop it off and combine it into the shifted
2784 // register operand instead.
2785 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2786 if (!PrevOp->isReg())
2787 return Error(PrevOp->getStartLoc(), "shift must be of a register");
2788 int SrcReg = PrevOp->getReg();
2793 if (ShiftTy == ARM_AM::rrx) {
2794 // RRX Doesn't have an explicit shift amount. The encoder expects
2795 // the shift register to be the same as the source register. Seems odd,
2799 // Figure out if this is shifted by a constant or a register (for non-RRX).
2800 if (Parser.getTok().is(AsmToken::Hash) ||
2801 Parser.getTok().is(AsmToken::Dollar)) {
2802 Parser.Lex(); // Eat hash.
2803 SMLoc ImmLoc = Parser.getTok().getLoc();
2804 const MCExpr *ShiftExpr = 0;
2805 if (getParser().parseExpression(ShiftExpr, EndLoc)) {
2806 Error(ImmLoc, "invalid immediate shift value");
2809 // The expression must be evaluatable as an immediate.
2810 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2812 Error(ImmLoc, "invalid immediate shift value");
2815 // Range check the immediate.
2816 // lsl, ror: 0 <= imm <= 31
2817 // lsr, asr: 0 <= imm <= 32
2818 Imm = CE->getValue();
2820 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2821 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2822 Error(ImmLoc, "immediate shift value out of range");
2825 // shift by zero is a nop. Always send it through as lsl.
2826 // ('as' compatibility)
2828 ShiftTy = ARM_AM::lsl;
2829 } else if (Parser.getTok().is(AsmToken::Identifier)) {
2830 SMLoc L = Parser.getTok().getLoc();
2831 EndLoc = Parser.getTok().getEndLoc();
2832 ShiftReg = tryParseRegister();
2833 if (ShiftReg == -1) {
2834 Error (L, "expected immediate or register in shift operand");
2838 Error (Parser.getTok().getLoc(),
2839 "expected immediate or register in shift operand");
2844 if (ShiftReg && ShiftTy != ARM_AM::rrx)
2845 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2849 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2856 /// Try to parse a register name. The token must be an Identifier when called.
2857 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
2858 /// if there is a "writeback". 'true' if it's not a register.
2860 /// TODO this is likely to change to allow different register types and or to
2861 /// parse for a specific register type.
2863 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2864 const AsmToken &RegTok = Parser.getTok();
2865 int RegNo = tryParseRegister();
2869 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
2870 RegTok.getEndLoc()));
2872 const AsmToken &ExclaimTok = Parser.getTok();
2873 if (ExclaimTok.is(AsmToken::Exclaim)) {
2874 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2875 ExclaimTok.getLoc()));
2876 Parser.Lex(); // Eat exclaim token
2880 // Also check for an index operand. This is only legal for vector registers,
2881 // but that'll get caught OK in operand matching, so we don't need to
2882 // explicitly filter everything else out here.
2883 if (Parser.getTok().is(AsmToken::LBrac)) {
2884 SMLoc SIdx = Parser.getTok().getLoc();
2885 Parser.Lex(); // Eat left bracket token.
2887 const MCExpr *ImmVal;
2888 if (getParser().parseExpression(ImmVal))
2890 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2892 return TokError("immediate value expected for vector index");
2894 if (Parser.getTok().isNot(AsmToken::RBrac))
2895 return Error(Parser.getTok().getLoc(), "']' expected");
2897 SMLoc E = Parser.getTok().getEndLoc();
2898 Parser.Lex(); // Eat right bracket token.
2900 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2908 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
2909 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2911 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2912 // Use the same layout as the tablegen'erated register name matcher. Ugly,
2914 switch (Name.size()) {
2917 if (Name[0] != CoprocOp)
2933 if (Name[0] != CoprocOp || Name[1] != '1')
2937 // p10 and p11 are invalid for coproc instructions (reserved for FP/NEON)
2938 case '0': return CoprocOp == 'p'? -1: 10;
2939 case '1': return CoprocOp == 'p'? -1: 11;
2940 case '2': return 12;
2941 case '3': return 13;
2942 case '4': return 14;
2943 case '5': return 15;
2948 /// parseITCondCode - Try to parse a condition code for an IT instruction.
2949 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2950 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2951 SMLoc S = Parser.getTok().getLoc();
2952 const AsmToken &Tok = Parser.getTok();
2953 if (!Tok.is(AsmToken::Identifier))
2954 return MatchOperand_NoMatch;
2955 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
2956 .Case("eq", ARMCC::EQ)
2957 .Case("ne", ARMCC::NE)
2958 .Case("hs", ARMCC::HS)
2959 .Case("cs", ARMCC::HS)
2960 .Case("lo", ARMCC::LO)
2961 .Case("cc", ARMCC::LO)
2962 .Case("mi", ARMCC::MI)
2963 .Case("pl", ARMCC::PL)
2964 .Case("vs", ARMCC::VS)
2965 .Case("vc", ARMCC::VC)
2966 .Case("hi", ARMCC::HI)
2967 .Case("ls", ARMCC::LS)
2968 .Case("ge", ARMCC::GE)
2969 .Case("lt", ARMCC::LT)
2970 .Case("gt", ARMCC::GT)
2971 .Case("le", ARMCC::LE)
2972 .Case("al", ARMCC::AL)
2975 return MatchOperand_NoMatch;
2976 Parser.Lex(); // Eat the token.
2978 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2980 return MatchOperand_Success;
2983 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2984 /// token must be an Identifier when called, and if it is a coprocessor
2985 /// number, the token is eaten and the operand is added to the operand list.
2986 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2987 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2988 SMLoc S = Parser.getTok().getLoc();
2989 const AsmToken &Tok = Parser.getTok();
2990 if (Tok.isNot(AsmToken::Identifier))
2991 return MatchOperand_NoMatch;
2993 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2995 return MatchOperand_NoMatch;
2997 Parser.Lex(); // Eat identifier token.
2998 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2999 return MatchOperand_Success;
3002 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
3003 /// token must be an Identifier when called, and if it is a coprocessor
3004 /// number, the token is eaten and the operand is added to the operand list.
3005 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3006 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3007 SMLoc S = Parser.getTok().getLoc();
3008 const AsmToken &Tok = Parser.getTok();
3009 if (Tok.isNot(AsmToken::Identifier))
3010 return MatchOperand_NoMatch;
3012 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
3014 return MatchOperand_NoMatch;
3016 Parser.Lex(); // Eat identifier token.
3017 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
3018 return MatchOperand_Success;
3021 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
3022 /// coproc_option : '{' imm0_255 '}'
3023 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3024 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3025 SMLoc S = Parser.getTok().getLoc();
3027 // If this isn't a '{', this isn't a coprocessor immediate operand.
3028 if (Parser.getTok().isNot(AsmToken::LCurly))
3029 return MatchOperand_NoMatch;
3030 Parser.Lex(); // Eat the '{'
3033 SMLoc Loc = Parser.getTok().getLoc();
3034 if (getParser().parseExpression(Expr)) {
3035 Error(Loc, "illegal expression");
3036 return MatchOperand_ParseFail;
3038 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3039 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
3040 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
3041 return MatchOperand_ParseFail;
3043 int Val = CE->getValue();
3045 // Check for and consume the closing '}'
3046 if (Parser.getTok().isNot(AsmToken::RCurly))
3047 return MatchOperand_ParseFail;
3048 SMLoc E = Parser.getTok().getEndLoc();
3049 Parser.Lex(); // Eat the '}'
3051 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
3052 return MatchOperand_Success;
3055 // For register list parsing, we need to map from raw GPR register numbering
3056 // to the enumeration values. The enumeration values aren't sorted by
3057 // register number due to our using "sp", "lr" and "pc" as canonical names.
3058 static unsigned getNextRegister(unsigned Reg) {
3059 // If this is a GPR, we need to do it manually, otherwise we can rely
3060 // on the sort ordering of the enumeration since the other reg-classes
3062 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3065 default: llvm_unreachable("Invalid GPR number!");
3066 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
3067 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
3068 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
3069 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
3070 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
3071 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3072 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
3073 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
3077 // Return the low-subreg of a given Q register.
3078 static unsigned getDRegFromQReg(unsigned QReg) {
3080 default: llvm_unreachable("expected a Q register!");
3081 case ARM::Q0: return ARM::D0;
3082 case ARM::Q1: return ARM::D2;
3083 case ARM::Q2: return ARM::D4;
3084 case ARM::Q3: return ARM::D6;
3085 case ARM::Q4: return ARM::D8;
3086 case ARM::Q5: return ARM::D10;
3087 case ARM::Q6: return ARM::D12;
3088 case ARM::Q7: return ARM::D14;
3089 case ARM::Q8: return ARM::D16;
3090 case ARM::Q9: return ARM::D18;
3091 case ARM::Q10: return ARM::D20;
3092 case ARM::Q11: return ARM::D22;
3093 case ARM::Q12: return ARM::D24;
3094 case ARM::Q13: return ARM::D26;
3095 case ARM::Q14: return ARM::D28;
3096 case ARM::Q15: return ARM::D30;
3100 /// Parse a register list.
3102 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3103 assert(Parser.getTok().is(AsmToken::LCurly) &&
3104 "Token is not a Left Curly Brace");
3105 SMLoc S = Parser.getTok().getLoc();
3106 Parser.Lex(); // Eat '{' token.
3107 SMLoc RegLoc = Parser.getTok().getLoc();
3109 // Check the first register in the list to see what register class
3110 // this is a list of.
3111 int Reg = tryParseRegister();
3113 return Error(RegLoc, "register expected");
3115 // The reglist instructions have at most 16 registers, so reserve
3116 // space for that many.
3118 SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3120 // Allow Q regs and just interpret them as the two D sub-registers.
3121 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3122 Reg = getDRegFromQReg(Reg);
3123 EReg = MRI->getEncodingValue(Reg);
3124 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3127 const MCRegisterClass *RC;
3128 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3129 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3130 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3131 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3132 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3133 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3135 return Error(RegLoc, "invalid register in register list");
3137 // Store the register.
3138 EReg = MRI->getEncodingValue(Reg);
3139 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3141 // This starts immediately after the first register token in the list,
3142 // so we can see either a comma or a minus (range separator) as a legal
3144 while (Parser.getTok().is(AsmToken::Comma) ||
3145 Parser.getTok().is(AsmToken::Minus)) {
3146 if (Parser.getTok().is(AsmToken::Minus)) {
3147 Parser.Lex(); // Eat the minus.
3148 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3149 int EndReg = tryParseRegister();
3151 return Error(AfterMinusLoc, "register expected");
3152 // Allow Q regs and just interpret them as the two D sub-registers.
3153 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3154 EndReg = getDRegFromQReg(EndReg) + 1;
3155 // If the register is the same as the start reg, there's nothing
3159 // The register must be in the same register class as the first.
3160 if (!RC->contains(EndReg))
3161 return Error(AfterMinusLoc, "invalid register in register list");
3162 // Ranges must go from low to high.
3163 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3164 return Error(AfterMinusLoc, "bad range in register list");
3166 // Add all the registers in the range to the register list.
3167 while (Reg != EndReg) {
3168 Reg = getNextRegister(Reg);
3169 EReg = MRI->getEncodingValue(Reg);
3170 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3174 Parser.Lex(); // Eat the comma.
3175 RegLoc = Parser.getTok().getLoc();
3177 const AsmToken RegTok = Parser.getTok();
3178 Reg = tryParseRegister();
3180 return Error(RegLoc, "register expected");
3181 // Allow Q regs and just interpret them as the two D sub-registers.
3182 bool isQReg = false;
3183 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3184 Reg = getDRegFromQReg(Reg);
3187 // The register must be in the same register class as the first.
3188 if (!RC->contains(Reg))
3189 return Error(RegLoc, "invalid register in register list");
3190 // List must be monotonically increasing.
3191 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3192 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3193 Warning(RegLoc, "register list not in ascending order");
3195 return Error(RegLoc, "register list not in ascending order");
3197 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3198 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3199 ") in register list");
3202 // VFP register lists must also be contiguous.
3203 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3205 return Error(RegLoc, "non-contiguous register range");
3206 EReg = MRI->getEncodingValue(Reg);
3207 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3209 EReg = MRI->getEncodingValue(++Reg);
3210 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3214 if (Parser.getTok().isNot(AsmToken::RCurly))
3215 return Error(Parser.getTok().getLoc(), "'}' expected");
3216 SMLoc E = Parser.getTok().getEndLoc();
3217 Parser.Lex(); // Eat '}' token.
3219 // Push the register list operand.
3220 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3222 // The ARM system instruction variants for LDM/STM have a '^' token here.
3223 if (Parser.getTok().is(AsmToken::Caret)) {
3224 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3225 Parser.Lex(); // Eat '^' token.
3231 // Helper function to parse the lane index for vector lists.
3232 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3233 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3234 Index = 0; // Always return a defined index value.
3235 if (Parser.getTok().is(AsmToken::LBrac)) {
3236 Parser.Lex(); // Eat the '['.
3237 if (Parser.getTok().is(AsmToken::RBrac)) {
3238 // "Dn[]" is the 'all lanes' syntax.
3239 LaneKind = AllLanes;
3240 EndLoc = Parser.getTok().getEndLoc();
3241 Parser.Lex(); // Eat the ']'.
3242 return MatchOperand_Success;
3245 // There's an optional '#' token here. Normally there wouldn't be, but
3246 // inline assemble puts one in, and it's friendly to accept that.
3247 if (Parser.getTok().is(AsmToken::Hash))
3248 Parser.Lex(); // Eat '#' or '$'.
3250 const MCExpr *LaneIndex;
3251 SMLoc Loc = Parser.getTok().getLoc();
3252 if (getParser().parseExpression(LaneIndex)) {
3253 Error(Loc, "illegal expression");
3254 return MatchOperand_ParseFail;
3256 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3258 Error(Loc, "lane index must be empty or an integer");
3259 return MatchOperand_ParseFail;
3261 if (Parser.getTok().isNot(AsmToken::RBrac)) {
3262 Error(Parser.getTok().getLoc(), "']' expected");
3263 return MatchOperand_ParseFail;
3265 EndLoc = Parser.getTok().getEndLoc();
3266 Parser.Lex(); // Eat the ']'.
3267 int64_t Val = CE->getValue();
3269 // FIXME: Make this range check context sensitive for .8, .16, .32.
3270 if (Val < 0 || Val > 7) {
3271 Error(Parser.getTok().getLoc(), "lane index out of range");
3272 return MatchOperand_ParseFail;
3275 LaneKind = IndexedLane;
3276 return MatchOperand_Success;
3279 return MatchOperand_Success;
3282 // parse a vector register list
3283 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3284 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3285 VectorLaneTy LaneKind;
3287 SMLoc S = Parser.getTok().getLoc();
3288 // As an extension (to match gas), support a plain D register or Q register
3289 // (without encosing curly braces) as a single or double entry list,
3291 if (Parser.getTok().is(AsmToken::Identifier)) {
3292 SMLoc E = Parser.getTok().getEndLoc();
3293 int Reg = tryParseRegister();
3295 return MatchOperand_NoMatch;
3296 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3297 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3298 if (Res != MatchOperand_Success)
3302 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3305 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3309 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3314 return MatchOperand_Success;
3316 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3317 Reg = getDRegFromQReg(Reg);
3318 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3319 if (Res != MatchOperand_Success)
3323 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3324 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3325 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3328 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3329 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3330 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3334 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3339 return MatchOperand_Success;
3341 Error(S, "vector register expected");
3342 return MatchOperand_ParseFail;
3345 if (Parser.getTok().isNot(AsmToken::LCurly))
3346 return MatchOperand_NoMatch;
3348 Parser.Lex(); // Eat '{' token.
3349 SMLoc RegLoc = Parser.getTok().getLoc();
3351 int Reg = tryParseRegister();
3353 Error(RegLoc, "register expected");
3354 return MatchOperand_ParseFail;
3358 unsigned FirstReg = Reg;
3359 // The list is of D registers, but we also allow Q regs and just interpret
3360 // them as the two D sub-registers.
3361 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3362 FirstReg = Reg = getDRegFromQReg(Reg);
3363 Spacing = 1; // double-spacing requires explicit D registers, otherwise
3364 // it's ambiguous with four-register single spaced.
3370 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3371 return MatchOperand_ParseFail;
3373 while (Parser.getTok().is(AsmToken::Comma) ||
3374 Parser.getTok().is(AsmToken::Minus)) {
3375 if (Parser.getTok().is(AsmToken::Minus)) {
3377 Spacing = 1; // Register range implies a single spaced list.
3378 else if (Spacing == 2) {
3379 Error(Parser.getTok().getLoc(),
3380 "sequential registers in double spaced list");
3381 return MatchOperand_ParseFail;
3383 Parser.Lex(); // Eat the minus.
3384 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3385 int EndReg = tryParseRegister();
3387 Error(AfterMinusLoc, "register expected");
3388 return MatchOperand_ParseFail;
3390 // Allow Q regs and just interpret them as the two D sub-registers.
3391 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3392 EndReg = getDRegFromQReg(EndReg) + 1;
3393 // If the register is the same as the start reg, there's nothing
3397 // The register must be in the same register class as the first.
3398 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3399 Error(AfterMinusLoc, "invalid register in register list");
3400 return MatchOperand_ParseFail;
3402 // Ranges must go from low to high.
3404 Error(AfterMinusLoc, "bad range in register list");
3405 return MatchOperand_ParseFail;
3407 // Parse the lane specifier if present.
3408 VectorLaneTy NextLaneKind;
3409 unsigned NextLaneIndex;
3410 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3411 MatchOperand_Success)
3412 return MatchOperand_ParseFail;
3413 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3414 Error(AfterMinusLoc, "mismatched lane index in register list");
3415 return MatchOperand_ParseFail;
3418 // Add all the registers in the range to the register list.
3419 Count += EndReg - Reg;
3423 Parser.Lex(); // Eat the comma.
3424 RegLoc = Parser.getTok().getLoc();
3426 Reg = tryParseRegister();
3428 Error(RegLoc, "register expected");
3429 return MatchOperand_ParseFail;
3431 // vector register lists must be contiguous.
3432 // It's OK to use the enumeration values directly here rather, as the
3433 // VFP register classes have the enum sorted properly.
3435 // The list is of D registers, but we also allow Q regs and just interpret
3436 // them as the two D sub-registers.
3437 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3439 Spacing = 1; // Register range implies a single spaced list.
3440 else if (Spacing == 2) {
3442 "invalid register in double-spaced list (must be 'D' register')");
3443 return MatchOperand_ParseFail;
3445 Reg = getDRegFromQReg(Reg);
3446 if (Reg != OldReg + 1) {
3447 Error(RegLoc, "non-contiguous register range");
3448 return MatchOperand_ParseFail;
3452 // Parse the lane specifier if present.
3453 VectorLaneTy NextLaneKind;
3454 unsigned NextLaneIndex;
3455 SMLoc LaneLoc = Parser.getTok().getLoc();
3456 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3457 MatchOperand_Success)
3458 return MatchOperand_ParseFail;
3459 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3460 Error(LaneLoc, "mismatched lane index in register list");
3461 return MatchOperand_ParseFail;
3465 // Normal D register.
3466 // Figure out the register spacing (single or double) of the list if
3467 // we don't know it already.
3469 Spacing = 1 + (Reg == OldReg + 2);
3471 // Just check that it's contiguous and keep going.
3472 if (Reg != OldReg + Spacing) {
3473 Error(RegLoc, "non-contiguous register range");
3474 return MatchOperand_ParseFail;
3477 // Parse the lane specifier if present.
3478 VectorLaneTy NextLaneKind;
3479 unsigned NextLaneIndex;
3480 SMLoc EndLoc = Parser.getTok().getLoc();
3481 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3482 return MatchOperand_ParseFail;
3483 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3484 Error(EndLoc, "mismatched lane index in register list");
3485 return MatchOperand_ParseFail;
3489 if (Parser.getTok().isNot(AsmToken::RCurly)) {
3490 Error(Parser.getTok().getLoc(), "'}' expected");
3491 return MatchOperand_ParseFail;
3493 E = Parser.getTok().getEndLoc();
3494 Parser.Lex(); // Eat '}' token.
3498 // Two-register operands have been converted to the
3499 // composite register classes.
3501 const MCRegisterClass *RC = (Spacing == 1) ?
3502 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3503 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3504 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3507 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3508 (Spacing == 2), S, E));
3511 // Two-register operands have been converted to the
3512 // composite register classes.
3514 const MCRegisterClass *RC = (Spacing == 1) ?
3515 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3516 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3517 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3519 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3524 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3530 return MatchOperand_Success;
3533 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3534 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3535 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3536 SMLoc S = Parser.getTok().getLoc();
3537 const AsmToken &Tok = Parser.getTok();
3540 if (Tok.is(AsmToken::Identifier)) {
3541 StringRef OptStr = Tok.getString();
3543 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3544 .Case("sy", ARM_MB::SY)
3545 .Case("st", ARM_MB::ST)
3546 .Case("ld", ARM_MB::LD)
3547 .Case("sh", ARM_MB::ISH)
3548 .Case("ish", ARM_MB::ISH)
3549 .Case("shst", ARM_MB::ISHST)
3550 .Case("ishst", ARM_MB::ISHST)
3551 .Case("ishld", ARM_MB::ISHLD)
3552 .Case("nsh", ARM_MB::NSH)
3553 .Case("un", ARM_MB::NSH)
3554 .Case("nshst", ARM_MB::NSHST)
3555 .Case("nshld", ARM_MB::NSHLD)
3556 .Case("unst", ARM_MB::NSHST)
3557 .Case("osh", ARM_MB::OSH)
3558 .Case("oshst", ARM_MB::OSHST)
3559 .Case("oshld", ARM_MB::OSHLD)
3562 // ishld, oshld, nshld and ld are only available from ARMv8.
3563 if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
3564 Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
3568 return MatchOperand_NoMatch;
3570 Parser.Lex(); // Eat identifier token.
3571 } else if (Tok.is(AsmToken::Hash) ||
3572 Tok.is(AsmToken::Dollar) ||
3573 Tok.is(AsmToken::Integer)) {
3574 if (Parser.getTok().isNot(AsmToken::Integer))
3575 Parser.Lex(); // Eat '#' or '$'.
3576 SMLoc Loc = Parser.getTok().getLoc();
3578 const MCExpr *MemBarrierID;
3579 if (getParser().parseExpression(MemBarrierID)) {
3580 Error(Loc, "illegal expression");
3581 return MatchOperand_ParseFail;
3584 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3586 Error(Loc, "constant expression expected");
3587 return MatchOperand_ParseFail;
3590 int Val = CE->getValue();
3592 Error(Loc, "immediate value out of range");
3593 return MatchOperand_ParseFail;
3596 Opt = ARM_MB::RESERVED_0 + Val;
3598 return MatchOperand_ParseFail;
3600 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3601 return MatchOperand_Success;
3604 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3605 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3606 parseInstSyncBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3607 SMLoc S = Parser.getTok().getLoc();
3608 const AsmToken &Tok = Parser.getTok();
3611 if (Tok.is(AsmToken::Identifier)) {
3612 StringRef OptStr = Tok.getString();
3614 if (OptStr.equals_lower("sy"))
3617 return MatchOperand_NoMatch;
3619 Parser.Lex(); // Eat identifier token.
3620 } else if (Tok.is(AsmToken::Hash) ||
3621 Tok.is(AsmToken::Dollar) ||
3622 Tok.is(AsmToken::Integer)) {
3623 if (Parser.getTok().isNot(AsmToken::Integer))
3624 Parser.Lex(); // Eat '#' or '$'.
3625 SMLoc Loc = Parser.getTok().getLoc();
3627 const MCExpr *ISBarrierID;
3628 if (getParser().parseExpression(ISBarrierID)) {
3629 Error(Loc, "illegal expression");
3630 return MatchOperand_ParseFail;
3633 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3635 Error(Loc, "constant expression expected");
3636 return MatchOperand_ParseFail;
3639 int Val = CE->getValue();
3641 Error(Loc, "immediate value out of range");
3642 return MatchOperand_ParseFail;
3645 Opt = ARM_ISB::RESERVED_0 + Val;
3647 return MatchOperand_ParseFail;
3649 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3650 (ARM_ISB::InstSyncBOpt)Opt, S));
3651 return MatchOperand_Success;
3655 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3656 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3657 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3658 SMLoc S = Parser.getTok().getLoc();
3659 const AsmToken &Tok = Parser.getTok();
3660 if (!Tok.is(AsmToken::Identifier))
3661 return MatchOperand_NoMatch;
3662 StringRef IFlagsStr = Tok.getString();
3664 // An iflags string of "none" is interpreted to mean that none of the AIF
3665 // bits are set. Not a terribly useful instruction, but a valid encoding.
3666 unsigned IFlags = 0;
3667 if (IFlagsStr != "none") {
3668 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3669 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3670 .Case("a", ARM_PROC::A)
3671 .Case("i", ARM_PROC::I)
3672 .Case("f", ARM_PROC::F)
3675 // If some specific iflag is already set, it means that some letter is
3676 // present more than once, this is not acceptable.
3677 if (Flag == ~0U || (IFlags & Flag))
3678 return MatchOperand_NoMatch;
3684 Parser.Lex(); // Eat identifier token.
3685 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3686 return MatchOperand_Success;
3689 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3690 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3691 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3692 SMLoc S = Parser.getTok().getLoc();
3693 const AsmToken &Tok = Parser.getTok();
3694 if (!Tok.is(AsmToken::Identifier))
3695 return MatchOperand_NoMatch;
3696 StringRef Mask = Tok.getString();
3699 // See ARMv6-M 10.1.1
3700 std::string Name = Mask.lower();
3701 unsigned FlagsVal = StringSwitch<unsigned>(Name)
3702 // Note: in the documentation:
3703 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3704 // for MSR APSR_nzcvq.
3705 // but we do make it an alias here. This is so to get the "mask encoding"
3706 // bits correct on MSR APSR writes.
3708 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3709 // should really only be allowed when writing a special register. Note
3710 // they get dropped in the MRS instruction reading a special register as
3711 // the SYSm field is only 8 bits.
3713 // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3714 // includes the DSP extension but that is not checked.
3715 .Case("apsr", 0x800)
3716 .Case("apsr_nzcvq", 0x800)
3717 .Case("apsr_g", 0x400)
3718 .Case("apsr_nzcvqg", 0xc00)
3719 .Case("iapsr", 0x801)
3720 .Case("iapsr_nzcvq", 0x801)
3721 .Case("iapsr_g", 0x401)
3722 .Case("iapsr_nzcvqg", 0xc01)
3723 .Case("eapsr", 0x802)
3724 .Case("eapsr_nzcvq", 0x802)
3725 .Case("eapsr_g", 0x402)
3726 .Case("eapsr_nzcvqg", 0xc02)
3727 .Case("xpsr", 0x803)
3728 .Case("xpsr_nzcvq", 0x803)
3729 .Case("xpsr_g", 0x403)
3730 .Case("xpsr_nzcvqg", 0xc03)
3731 .Case("ipsr", 0x805)
3732 .Case("epsr", 0x806)
3733 .Case("iepsr", 0x807)
3736 .Case("primask", 0x810)
3737 .Case("basepri", 0x811)
3738 .Case("basepri_max", 0x812)
3739 .Case("faultmask", 0x813)
3740 .Case("control", 0x814)
3743 if (FlagsVal == ~0U)
3744 return MatchOperand_NoMatch;
3746 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3747 // basepri, basepri_max and faultmask only valid for V7m.
3748 return MatchOperand_NoMatch;
3750 Parser.Lex(); // Eat identifier token.
3751 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3752 return MatchOperand_Success;
3755 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3756 size_t Start = 0, Next = Mask.find('_');
3757 StringRef Flags = "";
3758 std::string SpecReg = Mask.slice(Start, Next).lower();
3759 if (Next != StringRef::npos)
3760 Flags = Mask.slice(Next+1, Mask.size());
3762 // FlagsVal contains the complete mask:
3764 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3765 unsigned FlagsVal = 0;
3767 if (SpecReg == "apsr") {
3768 FlagsVal = StringSwitch<unsigned>(Flags)
3769 .Case("nzcvq", 0x8) // same as CPSR_f
3770 .Case("g", 0x4) // same as CPSR_s
3771 .Case("nzcvqg", 0xc) // same as CPSR_fs
3774 if (FlagsVal == ~0U) {
3776 return MatchOperand_NoMatch;
3778 FlagsVal = 8; // No flag
3780 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3781 // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3782 if (Flags == "all" || Flags == "")
3784 for (int i = 0, e = Flags.size(); i != e; ++i) {
3785 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3792 // If some specific flag is already set, it means that some letter is
3793 // present more than once, this is not acceptable.
3794 if (FlagsVal == ~0U || (FlagsVal & Flag))
3795 return MatchOperand_NoMatch;
3798 } else // No match for special register.
3799 return MatchOperand_NoMatch;
3801 // Special register without flags is NOT equivalent to "fc" flags.
3802 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
3803 // two lines would enable gas compatibility at the expense of breaking
3809 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3810 if (SpecReg == "spsr")
3813 Parser.Lex(); // Eat identifier token.
3814 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3815 return MatchOperand_Success;
3818 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3819 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3820 int Low, int High) {
3821 const AsmToken &Tok = Parser.getTok();
3822 if (Tok.isNot(AsmToken::Identifier)) {
3823 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3824 return MatchOperand_ParseFail;
3826 StringRef ShiftName = Tok.getString();
3827 std::string LowerOp = Op.lower();
3828 std::string UpperOp = Op.upper();
3829 if (ShiftName != LowerOp && ShiftName != UpperOp) {
3830 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3831 return MatchOperand_ParseFail;
3833 Parser.Lex(); // Eat shift type token.
3835 // There must be a '#' and a shift amount.
3836 if (Parser.getTok().isNot(AsmToken::Hash) &&
3837 Parser.getTok().isNot(AsmToken::Dollar)) {
3838 Error(Parser.getTok().getLoc(), "'#' expected");
3839 return MatchOperand_ParseFail;
3841 Parser.Lex(); // Eat hash token.
3843 const MCExpr *ShiftAmount;
3844 SMLoc Loc = Parser.getTok().getLoc();
3846 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3847 Error(Loc, "illegal expression");
3848 return MatchOperand_ParseFail;
3850 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3852 Error(Loc, "constant expression expected");
3853 return MatchOperand_ParseFail;
3855 int Val = CE->getValue();
3856 if (Val < Low || Val > High) {
3857 Error(Loc, "immediate value out of range");
3858 return MatchOperand_ParseFail;
3861 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
3863 return MatchOperand_Success;
3866 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3867 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3868 const AsmToken &Tok = Parser.getTok();
3869 SMLoc S = Tok.getLoc();
3870 if (Tok.isNot(AsmToken::Identifier)) {
3871 Error(S, "'be' or 'le' operand expected");
3872 return MatchOperand_ParseFail;
3874 int Val = StringSwitch<int>(Tok.getString().lower())
3878 Parser.Lex(); // Eat the token.
3881 Error(S, "'be' or 'le' operand expected");
3882 return MatchOperand_ParseFail;
3884 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3886 S, Tok.getEndLoc()));
3887 return MatchOperand_Success;
3890 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3891 /// instructions. Legal values are:
3892 /// lsl #n 'n' in [0,31]
3893 /// asr #n 'n' in [1,32]
3894 /// n == 32 encoded as n == 0.
3895 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3896 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3897 const AsmToken &Tok = Parser.getTok();
3898 SMLoc S = Tok.getLoc();
3899 if (Tok.isNot(AsmToken::Identifier)) {
3900 Error(S, "shift operator 'asr' or 'lsl' expected");
3901 return MatchOperand_ParseFail;
3903 StringRef ShiftName = Tok.getString();
3905 if (ShiftName == "lsl" || ShiftName == "LSL")
3907 else if (ShiftName == "asr" || ShiftName == "ASR")
3910 Error(S, "shift operator 'asr' or 'lsl' expected");
3911 return MatchOperand_ParseFail;
3913 Parser.Lex(); // Eat the operator.
3915 // A '#' and a shift amount.
3916 if (Parser.getTok().isNot(AsmToken::Hash) &&
3917 Parser.getTok().isNot(AsmToken::Dollar)) {
3918 Error(Parser.getTok().getLoc(), "'#' expected");
3919 return MatchOperand_ParseFail;
3921 Parser.Lex(); // Eat hash token.
3922 SMLoc ExLoc = Parser.getTok().getLoc();
3924 const MCExpr *ShiftAmount;
3926 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3927 Error(ExLoc, "malformed shift expression");
3928 return MatchOperand_ParseFail;
3930 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3932 Error(ExLoc, "shift amount must be an immediate");
3933 return MatchOperand_ParseFail;
3936 int64_t Val = CE->getValue();
3938 // Shift amount must be in [1,32]
3939 if (Val < 1 || Val > 32) {
3940 Error(ExLoc, "'asr' shift amount must be in range [1,32]");
3941 return MatchOperand_ParseFail;
3943 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3944 if (isThumb() && Val == 32) {
3945 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
3946 return MatchOperand_ParseFail;
3948 if (Val == 32) Val = 0;
3950 // Shift amount must be in [1,32]
3951 if (Val < 0 || Val > 31) {
3952 Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
3953 return MatchOperand_ParseFail;
3957 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
3959 return MatchOperand_Success;
3962 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3963 /// of instructions. Legal values are:
3964 /// ror #n 'n' in {0, 8, 16, 24}
3965 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3966 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3967 const AsmToken &Tok = Parser.getTok();
3968 SMLoc S = Tok.getLoc();
3969 if (Tok.isNot(AsmToken::Identifier))
3970 return MatchOperand_NoMatch;
3971 StringRef ShiftName = Tok.getString();
3972 if (ShiftName != "ror" && ShiftName != "ROR")
3973 return MatchOperand_NoMatch;
3974 Parser.Lex(); // Eat the operator.
3976 // A '#' and a rotate amount.
3977 if (Parser.getTok().isNot(AsmToken::Hash) &&
3978 Parser.getTok().isNot(AsmToken::Dollar)) {
3979 Error(Parser.getTok().getLoc(), "'#' expected");
3980 return MatchOperand_ParseFail;
3982 Parser.Lex(); // Eat hash token.
3983 SMLoc ExLoc = Parser.getTok().getLoc();
3985 const MCExpr *ShiftAmount;
3987 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3988 Error(ExLoc, "malformed rotate expression");
3989 return MatchOperand_ParseFail;
3991 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3993 Error(ExLoc, "rotate amount must be an immediate");
3994 return MatchOperand_ParseFail;
3997 int64_t Val = CE->getValue();
3998 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
3999 // normally, zero is represented in asm by omitting the rotate operand
4001 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
4002 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
4003 return MatchOperand_ParseFail;
4006 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
4008 return MatchOperand_Success;
4011 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4012 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4013 SMLoc S = Parser.getTok().getLoc();
4014 // The bitfield descriptor is really two operands, the LSB and the width.
4015 if (Parser.getTok().isNot(AsmToken::Hash) &&
4016 Parser.getTok().isNot(AsmToken::Dollar)) {
4017 Error(Parser.getTok().getLoc(), "'#' expected");
4018 return MatchOperand_ParseFail;
4020 Parser.Lex(); // Eat hash token.
4022 const MCExpr *LSBExpr;
4023 SMLoc E = Parser.getTok().getLoc();
4024 if (getParser().parseExpression(LSBExpr)) {
4025 Error(E, "malformed immediate expression");
4026 return MatchOperand_ParseFail;
4028 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
4030 Error(E, "'lsb' operand must be an immediate");
4031 return MatchOperand_ParseFail;
4034 int64_t LSB = CE->getValue();
4035 // The LSB must be in the range [0,31]
4036 if (LSB < 0 || LSB > 31) {
4037 Error(E, "'lsb' operand must be in the range [0,31]");
4038 return MatchOperand_ParseFail;
4040 E = Parser.getTok().getLoc();
4042 // Expect another immediate operand.
4043 if (Parser.getTok().isNot(AsmToken::Comma)) {
4044 Error(Parser.getTok().getLoc(), "too few operands");
4045 return MatchOperand_ParseFail;
4047 Parser.Lex(); // Eat hash token.
4048 if (Parser.getTok().isNot(AsmToken::Hash) &&
4049 Parser.getTok().isNot(AsmToken::Dollar)) {
4050 Error(Parser.getTok().getLoc(), "'#' expected");
4051 return MatchOperand_ParseFail;
4053 Parser.Lex(); // Eat hash token.
4055 const MCExpr *WidthExpr;
4057 if (getParser().parseExpression(WidthExpr, EndLoc)) {
4058 Error(E, "malformed immediate expression");
4059 return MatchOperand_ParseFail;
4061 CE = dyn_cast<MCConstantExpr>(WidthExpr);
4063 Error(E, "'width' operand must be an immediate");
4064 return MatchOperand_ParseFail;
4067 int64_t Width = CE->getValue();
4068 // The LSB must be in the range [1,32-lsb]
4069 if (Width < 1 || Width > 32 - LSB) {
4070 Error(E, "'width' operand must be in the range [1,32-lsb]");
4071 return MatchOperand_ParseFail;
4074 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4076 return MatchOperand_Success;
4079 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4080 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4081 // Check for a post-index addressing register operand. Specifically:
4082 // postidx_reg := '+' register {, shift}
4083 // | '-' register {, shift}
4084 // | register {, shift}
4086 // This method must return MatchOperand_NoMatch without consuming any tokens
4087 // in the case where there is no match, as other alternatives take other
4089 AsmToken Tok = Parser.getTok();
4090 SMLoc S = Tok.getLoc();
4091 bool haveEaten = false;
4093 if (Tok.is(AsmToken::Plus)) {
4094 Parser.Lex(); // Eat the '+' token.
4096 } else if (Tok.is(AsmToken::Minus)) {
4097 Parser.Lex(); // Eat the '-' token.
4102 SMLoc E = Parser.getTok().getEndLoc();
4103 int Reg = tryParseRegister();
4106 return MatchOperand_NoMatch;
4107 Error(Parser.getTok().getLoc(), "register expected");
4108 return MatchOperand_ParseFail;
4111 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4112 unsigned ShiftImm = 0;
4113 if (Parser.getTok().is(AsmToken::Comma)) {
4114 Parser.Lex(); // Eat the ','.
4115 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4116 return MatchOperand_ParseFail;
4118 // FIXME: Only approximates end...may include intervening whitespace.
4119 E = Parser.getTok().getLoc();
4122 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4125 return MatchOperand_Success;
4128 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4129 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4130 // Check for a post-index addressing register operand. Specifically:
4131 // am3offset := '+' register
4138 // This method must return MatchOperand_NoMatch without consuming any tokens
4139 // in the case where there is no match, as other alternatives take other
4141 AsmToken Tok = Parser.getTok();
4142 SMLoc S = Tok.getLoc();
4144 // Do immediates first, as we always parse those if we have a '#'.
4145 if (Parser.getTok().is(AsmToken::Hash) ||
4146 Parser.getTok().is(AsmToken::Dollar)) {
4147 Parser.Lex(); // Eat '#' or '$'.
4148 // Explicitly look for a '-', as we need to encode negative zero
4150 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4151 const MCExpr *Offset;
4153 if (getParser().parseExpression(Offset, E))
4154 return MatchOperand_ParseFail;
4155 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4157 Error(S, "constant expression expected");
4158 return MatchOperand_ParseFail;
4160 // Negative zero is encoded as the flag value INT32_MIN.
4161 int32_t Val = CE->getValue();
4162 if (isNegative && Val == 0)
4166 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4168 return MatchOperand_Success;
4172 bool haveEaten = false;
4174 if (Tok.is(AsmToken::Plus)) {
4175 Parser.Lex(); // Eat the '+' token.
4177 } else if (Tok.is(AsmToken::Minus)) {
4178 Parser.Lex(); // Eat the '-' token.
4183 Tok = Parser.getTok();
4184 int Reg = tryParseRegister();
4187 return MatchOperand_NoMatch;
4188 Error(Tok.getLoc(), "register expected");
4189 return MatchOperand_ParseFail;
4192 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4193 0, S, Tok.getEndLoc()));
4195 return MatchOperand_Success;
4198 /// Convert parsed operands to MCInst. Needed here because this instruction
4199 /// only has two register operands, but multiplication is commutative so
4200 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4202 cvtThumbMultiply(MCInst &Inst,
4203 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4204 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4205 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4206 // If we have a three-operand form, make sure to set Rn to be the operand
4207 // that isn't the same as Rd.
4209 if (Operands.size() == 6 &&
4210 ((ARMOperand*)Operands[4])->getReg() ==
4211 ((ARMOperand*)Operands[3])->getReg())
4213 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4214 Inst.addOperand(Inst.getOperand(0));
4215 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4219 cvtThumbBranches(MCInst &Inst,
4220 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4221 int CondOp = -1, ImmOp = -1;
4222 switch(Inst.getOpcode()) {
4224 case ARM::tBcc: CondOp = 1; ImmOp = 2; break;
4227 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4229 default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4231 // first decide whether or not the branch should be conditional
4232 // by looking at it's location relative to an IT block
4234 // inside an IT block we cannot have any conditional branches. any
4235 // such instructions needs to be converted to unconditional form
4236 switch(Inst.getOpcode()) {
4237 case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4238 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4241 // outside IT blocks we can only have unconditional branches with AL
4242 // condition code or conditional branches with non-AL condition code
4243 unsigned Cond = static_cast<ARMOperand*>(Operands[CondOp])->getCondCode();
4244 switch(Inst.getOpcode()) {
4247 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4251 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4256 // now decide on encoding size based on branch target range
4257 switch(Inst.getOpcode()) {
4258 // classify tB as either t2B or t1B based on range of immediate operand
4260 ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4261 if(!op->isSignedOffset<11, 1>() && isThumbTwo())
4262 Inst.setOpcode(ARM::t2B);
4265 // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4267 ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4268 if(!op->isSignedOffset<8, 1>() && isThumbTwo())
4269 Inst.setOpcode(ARM::t2Bcc);
4273 ((ARMOperand*)Operands[ImmOp])->addImmOperands(Inst, 1);
4274 ((ARMOperand*)Operands[CondOp])->addCondCodeOperands(Inst, 2);
4277 /// Parse an ARM memory expression, return false if successful else return true
4278 /// or an error. The first token must be a '[' when called.
4280 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4282 assert(Parser.getTok().is(AsmToken::LBrac) &&
4283 "Token is not a Left Bracket");
4284 S = Parser.getTok().getLoc();
4285 Parser.Lex(); // Eat left bracket token.
4287 const AsmToken &BaseRegTok = Parser.getTok();
4288 int BaseRegNum = tryParseRegister();
4289 if (BaseRegNum == -1)
4290 return Error(BaseRegTok.getLoc(), "register expected");
4292 // The next token must either be a comma, a colon or a closing bracket.
4293 const AsmToken &Tok = Parser.getTok();
4294 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4295 !Tok.is(AsmToken::RBrac))
4296 return Error(Tok.getLoc(), "malformed memory operand");
4298 if (Tok.is(AsmToken::RBrac)) {
4299 E = Tok.getEndLoc();
4300 Parser.Lex(); // Eat right bracket token.
4302 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4303 0, 0, false, S, E));
4305 // If there's a pre-indexing writeback marker, '!', just add it as a token
4306 // operand. It's rather odd, but syntactically valid.
4307 if (Parser.getTok().is(AsmToken::Exclaim)) {
4308 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4309 Parser.Lex(); // Eat the '!'.
4315 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4316 "Lost colon or comma in memory operand?!");
4317 if (Tok.is(AsmToken::Comma)) {
4318 Parser.Lex(); // Eat the comma.
4321 // If we have a ':', it's an alignment specifier.
4322 if (Parser.getTok().is(AsmToken::Colon)) {
4323 Parser.Lex(); // Eat the ':'.
4324 E = Parser.getTok().getLoc();
4327 if (getParser().parseExpression(Expr))
4330 // The expression has to be a constant. Memory references with relocations
4331 // don't come through here, as they use the <label> forms of the relevant
4333 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4335 return Error (E, "constant expression expected");
4338 switch (CE->getValue()) {
4341 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4342 case 16: Align = 2; break;
4343 case 32: Align = 4; break;
4344 case 64: Align = 8; break;
4345 case 128: Align = 16; break;
4346 case 256: Align = 32; break;
4349 // Now we should have the closing ']'
4350 if (Parser.getTok().isNot(AsmToken::RBrac))
4351 return Error(Parser.getTok().getLoc(), "']' expected");
4352 E = Parser.getTok().getEndLoc();
4353 Parser.Lex(); // Eat right bracket token.
4355 // Don't worry about range checking the value here. That's handled by
4356 // the is*() predicates.
4357 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4358 ARM_AM::no_shift, 0, Align,
4361 // If there's a pre-indexing writeback marker, '!', just add it as a token
4363 if (Parser.getTok().is(AsmToken::Exclaim)) {
4364 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4365 Parser.Lex(); // Eat the '!'.
4371 // If we have a '#', it's an immediate offset, else assume it's a register
4372 // offset. Be friendly and also accept a plain integer (without a leading
4373 // hash) for gas compatibility.
4374 if (Parser.getTok().is(AsmToken::Hash) ||
4375 Parser.getTok().is(AsmToken::Dollar) ||
4376 Parser.getTok().is(AsmToken::Integer)) {
4377 if (Parser.getTok().isNot(AsmToken::Integer))
4378 Parser.Lex(); // Eat '#' or '$'.
4379 E = Parser.getTok().getLoc();
4381 bool isNegative = getParser().getTok().is(AsmToken::Minus);
4382 const MCExpr *Offset;
4383 if (getParser().parseExpression(Offset))
4386 // The expression has to be a constant. Memory references with relocations
4387 // don't come through here, as they use the <label> forms of the relevant
4389 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4391 return Error (E, "constant expression expected");
4393 // If the constant was #-0, represent it as INT32_MIN.
4394 int32_t Val = CE->getValue();
4395 if (isNegative && Val == 0)
4396 CE = MCConstantExpr::Create(INT32_MIN, getContext());
4398 // Now we should have the closing ']'
4399 if (Parser.getTok().isNot(AsmToken::RBrac))
4400 return Error(Parser.getTok().getLoc(), "']' expected");
4401 E = Parser.getTok().getEndLoc();
4402 Parser.Lex(); // Eat right bracket token.
4404 // Don't worry about range checking the value here. That's handled by
4405 // the is*() predicates.
4406 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4407 ARM_AM::no_shift, 0, 0,
4410 // If there's a pre-indexing writeback marker, '!', just add it as a token
4412 if (Parser.getTok().is(AsmToken::Exclaim)) {
4413 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4414 Parser.Lex(); // Eat the '!'.
4420 // The register offset is optionally preceded by a '+' or '-'
4421 bool isNegative = false;
4422 if (Parser.getTok().is(AsmToken::Minus)) {
4424 Parser.Lex(); // Eat the '-'.
4425 } else if (Parser.getTok().is(AsmToken::Plus)) {
4427 Parser.Lex(); // Eat the '+'.
4430 E = Parser.getTok().getLoc();
4431 int OffsetRegNum = tryParseRegister();
4432 if (OffsetRegNum == -1)
4433 return Error(E, "register expected");
4435 // If there's a shift operator, handle it.
4436 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4437 unsigned ShiftImm = 0;
4438 if (Parser.getTok().is(AsmToken::Comma)) {
4439 Parser.Lex(); // Eat the ','.
4440 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4444 // Now we should have the closing ']'
4445 if (Parser.getTok().isNot(AsmToken::RBrac))
4446 return Error(Parser.getTok().getLoc(), "']' expected");
4447 E = Parser.getTok().getEndLoc();
4448 Parser.Lex(); // Eat right bracket token.
4450 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4451 ShiftType, ShiftImm, 0, isNegative,
4454 // If there's a pre-indexing writeback marker, '!', just add it as a token
4456 if (Parser.getTok().is(AsmToken::Exclaim)) {
4457 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4458 Parser.Lex(); // Eat the '!'.
4464 /// parseMemRegOffsetShift - one of these two:
4465 /// ( lsl | lsr | asr | ror ) , # shift_amount
4467 /// return true if it parses a shift otherwise it returns false.
4468 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4470 SMLoc Loc = Parser.getTok().getLoc();
4471 const AsmToken &Tok = Parser.getTok();
4472 if (Tok.isNot(AsmToken::Identifier))
4474 StringRef ShiftName = Tok.getString();
4475 if (ShiftName == "lsl" || ShiftName == "LSL" ||
4476 ShiftName == "asl" || ShiftName == "ASL")
4478 else if (ShiftName == "lsr" || ShiftName == "LSR")
4480 else if (ShiftName == "asr" || ShiftName == "ASR")
4482 else if (ShiftName == "ror" || ShiftName == "ROR")
4484 else if (ShiftName == "rrx" || ShiftName == "RRX")
4487 return Error(Loc, "illegal shift operator");
4488 Parser.Lex(); // Eat shift type token.
4490 // rrx stands alone.
4492 if (St != ARM_AM::rrx) {
4493 Loc = Parser.getTok().getLoc();
4494 // A '#' and a shift amount.
4495 const AsmToken &HashTok = Parser.getTok();
4496 if (HashTok.isNot(AsmToken::Hash) &&
4497 HashTok.isNot(AsmToken::Dollar))
4498 return Error(HashTok.getLoc(), "'#' expected");
4499 Parser.Lex(); // Eat hash token.
4502 if (getParser().parseExpression(Expr))
4504 // Range check the immediate.
4505 // lsl, ror: 0 <= imm <= 31
4506 // lsr, asr: 0 <= imm <= 32
4507 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4509 return Error(Loc, "shift amount must be an immediate");
4510 int64_t Imm = CE->getValue();
4512 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4513 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4514 return Error(Loc, "immediate shift value out of range");
4515 // If <ShiftTy> #0, turn it into a no_shift.
4518 // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4527 /// parseFPImm - A floating point immediate expression operand.
4528 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4529 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4530 // Anything that can accept a floating point constant as an operand
4531 // needs to go through here, as the regular parseExpression is
4534 // This routine still creates a generic Immediate operand, containing
4535 // a bitcast of the 64-bit floating point value. The various operands
4536 // that accept floats can check whether the value is valid for them
4537 // via the standard is*() predicates.
4539 SMLoc S = Parser.getTok().getLoc();
4541 if (Parser.getTok().isNot(AsmToken::Hash) &&
4542 Parser.getTok().isNot(AsmToken::Dollar))
4543 return MatchOperand_NoMatch;
4545 // Disambiguate the VMOV forms that can accept an FP immediate.
4546 // vmov.f32 <sreg>, #imm
4547 // vmov.f64 <dreg>, #imm
4548 // vmov.f32 <dreg>, #imm @ vector f32x2
4549 // vmov.f32 <qreg>, #imm @ vector f32x4
4551 // There are also the NEON VMOV instructions which expect an
4552 // integer constant. Make sure we don't try to parse an FPImm
4554 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4555 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4556 if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
4557 TyOp->getToken() != ".f64"))
4558 return MatchOperand_NoMatch;
4560 Parser.Lex(); // Eat '#' or '$'.
4562 // Handle negation, as that still comes through as a separate token.
4563 bool isNegative = false;
4564 if (Parser.getTok().is(AsmToken::Minus)) {
4568 const AsmToken &Tok = Parser.getTok();
4569 SMLoc Loc = Tok.getLoc();
4570 if (Tok.is(AsmToken::Real)) {
4571 APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4572 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4573 // If we had a '-' in front, toggle the sign bit.
4574 IntVal ^= (uint64_t)isNegative << 31;
4575 Parser.Lex(); // Eat the token.
4576 Operands.push_back(ARMOperand::CreateImm(
4577 MCConstantExpr::Create(IntVal, getContext()),
4578 S, Parser.getTok().getLoc()));
4579 return MatchOperand_Success;
4581 // Also handle plain integers. Instructions which allow floating point
4582 // immediates also allow a raw encoded 8-bit value.
4583 if (Tok.is(AsmToken::Integer)) {
4584 int64_t Val = Tok.getIntVal();
4585 Parser.Lex(); // Eat the token.
4586 if (Val > 255 || Val < 0) {
4587 Error(Loc, "encoded floating point value out of range");
4588 return MatchOperand_ParseFail;
4590 double RealVal = ARM_AM::getFPImmFloat(Val);
4591 Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue();
4592 Operands.push_back(ARMOperand::CreateImm(
4593 MCConstantExpr::Create(Val, getContext()), S,
4594 Parser.getTok().getLoc()));
4595 return MatchOperand_Success;
4598 Error(Loc, "invalid floating point immediate");
4599 return MatchOperand_ParseFail;
4602 /// Parse a arm instruction operand. For now this parses the operand regardless
4603 /// of the mnemonic.
4604 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4605 StringRef Mnemonic) {
4608 // Check if the current operand has a custom associated parser, if so, try to
4609 // custom parse the operand, or fallback to the general approach.
4610 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4611 if (ResTy == MatchOperand_Success)
4613 // If there wasn't a custom match, try the generic matcher below. Otherwise,
4614 // there was a match, but an error occurred, in which case, just return that
4615 // the operand parsing failed.
4616 if (ResTy == MatchOperand_ParseFail)
4619 switch (getLexer().getKind()) {
4621 Error(Parser.getTok().getLoc(), "unexpected token in operand");
4623 case AsmToken::Identifier: {
4624 // If we've seen a branch mnemonic, the next operand must be a label. This
4625 // is true even if the label is a register name. So "br r1" means branch to
4627 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
4629 if (!tryParseRegisterWithWriteBack(Operands))
4631 int Res = tryParseShiftRegister(Operands);
4632 if (Res == 0) // success
4634 else if (Res == -1) // irrecoverable error
4636 // If this is VMRS, check for the apsr_nzcv operand.
4637 if (Mnemonic == "vmrs" &&
4638 Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4639 S = Parser.getTok().getLoc();
4641 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4646 // Fall though for the Identifier case that is not a register or a
4649 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
4650 case AsmToken::Integer: // things like 1f and 2b as a branch targets
4651 case AsmToken::String: // quoted label names.
4652 case AsmToken::Dot: { // . as a branch target
4653 // This was not a register so parse other operands that start with an
4654 // identifier (like labels) as expressions and create them as immediates.
4655 const MCExpr *IdVal;
4656 S = Parser.getTok().getLoc();
4657 if (getParser().parseExpression(IdVal))
4659 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4660 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4663 case AsmToken::LBrac:
4664 return parseMemory(Operands);
4665 case AsmToken::LCurly:
4666 return parseRegisterList(Operands);
4667 case AsmToken::Dollar:
4668 case AsmToken::Hash: {
4669 // #42 -> immediate.
4670 S = Parser.getTok().getLoc();
4673 if (Parser.getTok().isNot(AsmToken::Colon)) {
4674 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4675 const MCExpr *ImmVal;
4676 if (getParser().parseExpression(ImmVal))
4678 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4680 int32_t Val = CE->getValue();
4681 if (isNegative && Val == 0)
4682 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4684 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4685 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4687 // There can be a trailing '!' on operands that we want as a separate
4688 // '!' Token operand. Handle that here. For example, the compatibilty
4689 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
4690 if (Parser.getTok().is(AsmToken::Exclaim)) {
4691 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
4692 Parser.getTok().getLoc()));
4693 Parser.Lex(); // Eat exclaim token
4697 // w/ a ':' after the '#', it's just like a plain ':'.
4700 case AsmToken::Colon: {
4701 // ":lower16:" and ":upper16:" expression prefixes
4702 // FIXME: Check it's an expression prefix,
4703 // e.g. (FOO - :lower16:BAR) isn't legal.
4704 ARMMCExpr::VariantKind RefKind;
4705 if (parsePrefix(RefKind))
4708 const MCExpr *SubExprVal;
4709 if (getParser().parseExpression(SubExprVal))
4712 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4714 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4715 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4718 case AsmToken::Equal: {
4719 if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
4720 return Error(Parser.getTok().getLoc(), "unexpected token in operand");
4722 const MCSection *Section =
4723 getParser().getStreamer().getCurrentSection().first;
4725 Parser.Lex(); // Eat '='
4726 const MCExpr *SubExprVal;
4727 if (getParser().parseExpression(SubExprVal))
4729 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4731 const MCExpr *CPLoc =
4732 getOrCreateConstantPool(Section).addEntry(SubExprVal, getContext());
4733 Operands.push_back(ARMOperand::CreateImm(CPLoc, S, E));
4739 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4740 // :lower16: and :upper16:.
4741 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4742 RefKind = ARMMCExpr::VK_ARM_None;
4744 // :lower16: and :upper16: modifiers
4745 assert(getLexer().is(AsmToken::Colon) && "expected a :");
4746 Parser.Lex(); // Eat ':'
4748 if (getLexer().isNot(AsmToken::Identifier)) {
4749 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4753 StringRef IDVal = Parser.getTok().getIdentifier();
4754 if (IDVal == "lower16") {
4755 RefKind = ARMMCExpr::VK_ARM_LO16;
4756 } else if (IDVal == "upper16") {
4757 RefKind = ARMMCExpr::VK_ARM_HI16;
4759 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4764 if (getLexer().isNot(AsmToken::Colon)) {
4765 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4768 Parser.Lex(); // Eat the last ':'
4772 /// \brief Given a mnemonic, split out possible predication code and carry
4773 /// setting letters to form a canonical mnemonic and flags.
4775 // FIXME: Would be nice to autogen this.
4776 // FIXME: This is a bit of a maze of special cases.
4777 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4778 unsigned &PredicationCode,
4780 unsigned &ProcessorIMod,
4781 StringRef &ITMask) {
4782 PredicationCode = ARMCC::AL;
4783 CarrySetting = false;
4786 // Ignore some mnemonics we know aren't predicated forms.
4788 // FIXME: Would be nice to autogen this.
4789 if ((Mnemonic == "movs" && isThumb()) ||
4790 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
4791 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
4792 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
4793 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
4794 Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" ||
4795 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
4796 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
4797 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4798 Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
4799 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" ||
4800 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
4801 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel"))
4804 // First, split out any predication code. Ignore mnemonics we know aren't
4805 // predicated but do have a carry-set and so weren't caught above.
4806 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4807 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4808 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4809 Mnemonic != "sbcs" && Mnemonic != "rscs") {
4810 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4811 .Case("eq", ARMCC::EQ)
4812 .Case("ne", ARMCC::NE)
4813 .Case("hs", ARMCC::HS)
4814 .Case("cs", ARMCC::HS)
4815 .Case("lo", ARMCC::LO)
4816 .Case("cc", ARMCC::LO)
4817 .Case("mi", ARMCC::MI)
4818 .Case("pl", ARMCC::PL)
4819 .Case("vs", ARMCC::VS)
4820 .Case("vc", ARMCC::VC)
4821 .Case("hi", ARMCC::HI)
4822 .Case("ls", ARMCC::LS)
4823 .Case("ge", ARMCC::GE)
4824 .Case("lt", ARMCC::LT)
4825 .Case("gt", ARMCC::GT)
4826 .Case("le", ARMCC::LE)
4827 .Case("al", ARMCC::AL)
4830 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4831 PredicationCode = CC;
4835 // Next, determine if we have a carry setting bit. We explicitly ignore all
4836 // the instructions we know end in 's'.
4837 if (Mnemonic.endswith("s") &&
4838 !(Mnemonic == "cps" || Mnemonic == "mls" ||
4839 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4840 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4841 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4842 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4843 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4844 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4845 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
4846 Mnemonic == "vfms" || Mnemonic == "vfnms" ||
4847 (Mnemonic == "movs" && isThumb()))) {
4848 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4849 CarrySetting = true;
4852 // The "cps" instruction can have a interrupt mode operand which is glued into
4853 // the mnemonic. Check if this is the case, split it and parse the imod op
4854 if (Mnemonic.startswith("cps")) {
4855 // Split out any imod code.
4857 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4858 .Case("ie", ARM_PROC::IE)
4859 .Case("id", ARM_PROC::ID)
4862 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4863 ProcessorIMod = IMod;
4867 // The "it" instruction has the condition mask on the end of the mnemonic.
4868 if (Mnemonic.startswith("it")) {
4869 ITMask = Mnemonic.slice(2, Mnemonic.size());
4870 Mnemonic = Mnemonic.slice(0, 2);
4876 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
4877 /// inclusion of carry set or predication code operands.
4879 // FIXME: It would be nice to autogen this.
4881 getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
4882 bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) {
4883 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4884 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4885 Mnemonic == "add" || Mnemonic == "adc" ||
4886 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4887 Mnemonic == "orr" || Mnemonic == "mvn" ||
4888 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4889 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4890 Mnemonic == "vfm" || Mnemonic == "vfnm" ||
4891 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4892 Mnemonic == "mla" || Mnemonic == "smlal" ||
4893 Mnemonic == "umlal" || Mnemonic == "umull"))) {
4894 CanAcceptCarrySet = true;
4896 CanAcceptCarrySet = false;
4898 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
4899 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
4900 Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic.startswith("crc32") ||
4901 Mnemonic.startswith("cps") || Mnemonic.startswith("vsel") ||
4902 Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
4903 Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
4904 Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
4905 Mnemonic == "vrintm" || Mnemonic.startswith("aes") ||
4906 Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
4907 (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) {
4908 // These mnemonics are never predicable
4909 CanAcceptPredicationCode = false;
4910 } else if (!isThumb()) {
4911 // Some instructions are only predicable in Thumb mode
4912 CanAcceptPredicationCode
4913 = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
4914 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
4915 Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
4916 Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
4917 Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
4918 Mnemonic != "stc2" && Mnemonic != "stc2l" &&
4919 !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
4920 } else if (isThumbOne()) {
4922 CanAcceptPredicationCode = Mnemonic != "movs";
4924 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
4926 CanAcceptPredicationCode = true;
4929 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4930 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4931 // FIXME: This is all horribly hacky. We really need a better way to deal
4932 // with optional operands like this in the matcher table.
4934 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4935 // another does not. Specifically, the MOVW instruction does not. So we
4936 // special case it here and remove the defaulted (non-setting) cc_out
4937 // operand if that's the instruction we're trying to match.
4939 // We do this as post-processing of the explicit operands rather than just
4940 // conditionally adding the cc_out in the first place because we need
4941 // to check the type of the parsed immediate operand.
4942 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4943 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4944 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4945 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4948 // Register-register 'add' for thumb does not have a cc_out operand
4949 // when there are only two register operands.
4950 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4951 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4952 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4953 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4955 // Register-register 'add' for thumb does not have a cc_out operand
4956 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4957 // have to check the immediate range here since Thumb2 has a variant
4958 // that can handle a different range and has a cc_out operand.
4959 if (((isThumb() && Mnemonic == "add") ||
4960 (isThumbTwo() && Mnemonic == "sub")) &&
4961 Operands.size() == 6 &&
4962 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4963 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4964 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4965 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4966 ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
4967 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4969 // For Thumb2, add/sub immediate does not have a cc_out operand for the
4970 // imm0_4095 variant. That's the least-preferred variant when
4971 // selecting via the generic "add" mnemonic, so to know that we
4972 // should remove the cc_out operand, we have to explicitly check that
4973 // it's not one of the other variants. Ugh.
4974 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4975 Operands.size() == 6 &&
4976 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4977 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4978 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4979 // Nest conditions rather than one big 'if' statement for readability.
4981 // If both registers are low, we're in an IT block, and the immediate is
4982 // in range, we should use encoding T1 instead, which has a cc_out.
4984 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4985 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4986 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
4988 // Check against T3. If the second register is the PC, this is an
4989 // alternate form of ADR, which uses encoding T4, so check for that too.
4990 if (static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
4991 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
4994 // Otherwise, we use encoding T4, which does not have a cc_out
4999 // The thumb2 multiply instruction doesn't have a CCOut register, so
5000 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
5001 // use the 16-bit encoding or not.
5002 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5003 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5004 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5005 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5006 static_cast<ARMOperand*>(Operands[5])->isReg() &&
5007 // If the registers aren't low regs, the destination reg isn't the
5008 // same as one of the source regs, or the cc_out operand is zero
5009 // outside of an IT block, we have to use the 32-bit encoding, so
5010 // remove the cc_out operand.
5011 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
5012 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
5013 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
5015 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
5016 static_cast<ARMOperand*>(Operands[5])->getReg() &&
5017 static_cast<ARMOperand*>(Operands[3])->getReg() !=
5018 static_cast<ARMOperand*>(Operands[4])->getReg())))
5021 // Also check the 'mul' syntax variant that doesn't specify an explicit
5022 // destination register.
5023 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5024 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5025 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5026 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5027 // If the registers aren't low regs or the cc_out operand is zero
5028 // outside of an IT block, we have to use the 32-bit encoding, so
5029 // remove the cc_out operand.
5030 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
5031 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
5037 // Register-register 'add/sub' for thumb does not have a cc_out operand
5038 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5039 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
5040 // right, this will result in better diagnostics (which operand is off)
5042 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
5043 (Operands.size() == 5 || Operands.size() == 6) &&
5044 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5045 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
5046 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5047 (static_cast<ARMOperand*>(Operands[4])->isImm() ||
5048 (Operands.size() == 6 &&
5049 static_cast<ARMOperand*>(Operands[5])->isImm())))
5055 bool ARMAsmParser::shouldOmitPredicateOperand(
5056 StringRef Mnemonic, SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
5057 // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
5058 unsigned RegIdx = 3;
5059 if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
5060 static_cast<ARMOperand *>(Operands[2])->getToken() == ".f32") {
5061 if (static_cast<ARMOperand *>(Operands[3])->isToken() &&
5062 static_cast<ARMOperand *>(Operands[3])->getToken() == ".f32")
5065 if (static_cast<ARMOperand *>(Operands[RegIdx])->isReg() &&
5066 (ARMMCRegisterClasses[ARM::DPRRegClassID]
5067 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg()) ||
5068 ARMMCRegisterClasses[ARM::QPRRegClassID]
5069 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg())))
5075 static bool isDataTypeToken(StringRef Tok) {
5076 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5077 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5078 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5079 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5080 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5081 Tok == ".f" || Tok == ".d";
5084 // FIXME: This bit should probably be handled via an explicit match class
5085 // in the .td files that matches the suffix instead of having it be
5086 // a literal string token the way it is now.
5087 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5088 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5090 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
5091 unsigned VariantID);
5092 /// Parse an arm instruction mnemonic followed by its operands.
5093 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5095 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5096 // Apply mnemonic aliases before doing anything else, as the destination
5097 // mnemnonic may include suffices and we want to handle them normally.
5098 // The generic tblgen'erated code does this later, at the start of
5099 // MatchInstructionImpl(), but that's too late for aliases that include
5100 // any sort of suffix.
5101 unsigned AvailableFeatures = getAvailableFeatures();
5102 unsigned AssemblerDialect = getParser().getAssemblerDialect();
5103 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5105 // First check for the ARM-specific .req directive.
5106 if (Parser.getTok().is(AsmToken::Identifier) &&
5107 Parser.getTok().getIdentifier() == ".req") {
5108 parseDirectiveReq(Name, NameLoc);
5109 // We always return 'error' for this, as we're done with this
5110 // statement and don't need to match the 'instruction."
5114 // Create the leading tokens for the mnemonic, split by '.' characters.
5115 size_t Start = 0, Next = Name.find('.');
5116 StringRef Mnemonic = Name.slice(Start, Next);
5118 // Split out the predication code and carry setting flag from the mnemonic.
5119 unsigned PredicationCode;
5120 unsigned ProcessorIMod;
5123 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5124 ProcessorIMod, ITMask);
5126 // In Thumb1, only the branch (B) instruction can be predicated.
5127 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5128 Parser.eatToEndOfStatement();
5129 return Error(NameLoc, "conditional execution not supported in Thumb1");
5132 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5134 // Handle the IT instruction ITMask. Convert it to a bitmask. This
5135 // is the mask as it will be for the IT encoding if the conditional
5136 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5137 // where the conditional bit0 is zero, the instruction post-processing
5138 // will adjust the mask accordingly.
5139 if (Mnemonic == "it") {
5140 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5141 if (ITMask.size() > 3) {
5142 Parser.eatToEndOfStatement();
5143 return Error(Loc, "too many conditions on IT instruction");
5146 for (unsigned i = ITMask.size(); i != 0; --i) {
5147 char pos = ITMask[i - 1];
5148 if (pos != 't' && pos != 'e') {
5149 Parser.eatToEndOfStatement();
5150 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5153 if (ITMask[i - 1] == 't')
5156 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5159 // FIXME: This is all a pretty gross hack. We should automatically handle
5160 // optional operands like this via tblgen.
5162 // Next, add the CCOut and ConditionCode operands, if needed.
5164 // For mnemonics which can ever incorporate a carry setting bit or predication
5165 // code, our matching model involves us always generating CCOut and
5166 // ConditionCode operands to match the mnemonic "as written" and then we let
5167 // the matcher deal with finding the right instruction or generating an
5168 // appropriate error.
5169 bool CanAcceptCarrySet, CanAcceptPredicationCode;
5170 getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
5172 // If we had a carry-set on an instruction that can't do that, issue an
5174 if (!CanAcceptCarrySet && CarrySetting) {
5175 Parser.eatToEndOfStatement();
5176 return Error(NameLoc, "instruction '" + Mnemonic +
5177 "' can not set flags, but 's' suffix specified");
5179 // If we had a predication code on an instruction that can't do that, issue an
5181 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5182 Parser.eatToEndOfStatement();
5183 return Error(NameLoc, "instruction '" + Mnemonic +
5184 "' is not predicable, but condition code specified");
5187 // Add the carry setting operand, if necessary.
5188 if (CanAcceptCarrySet) {
5189 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5190 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5194 // Add the predication code operand, if necessary.
5195 if (CanAcceptPredicationCode) {
5196 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5198 Operands.push_back(ARMOperand::CreateCondCode(
5199 ARMCC::CondCodes(PredicationCode), Loc));
5202 // Add the processor imod operand, if necessary.
5203 if (ProcessorIMod) {
5204 Operands.push_back(ARMOperand::CreateImm(
5205 MCConstantExpr::Create(ProcessorIMod, getContext()),
5209 // Add the remaining tokens in the mnemonic.
5210 while (Next != StringRef::npos) {
5212 Next = Name.find('.', Start + 1);
5213 StringRef ExtraToken = Name.slice(Start, Next);
5215 // Some NEON instructions have an optional datatype suffix that is
5216 // completely ignored. Check for that.
5217 if (isDataTypeToken(ExtraToken) &&
5218 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5221 // For for ARM mode generate an error if the .n qualifier is used.
5222 if (ExtraToken == ".n" && !isThumb()) {
5223 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5224 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5228 // The .n qualifier is always discarded as that is what the tables
5229 // and matcher expect. In ARM mode the .w qualifier has no effect,
5230 // so discard it to avoid errors that can be caused by the matcher.
5231 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5232 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5233 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5237 // Read the remaining operands.
5238 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5239 // Read the first operand.
5240 if (parseOperand(Operands, Mnemonic)) {
5241 Parser.eatToEndOfStatement();
5245 while (getLexer().is(AsmToken::Comma)) {
5246 Parser.Lex(); // Eat the comma.
5248 // Parse and remember the operand.
5249 if (parseOperand(Operands, Mnemonic)) {
5250 Parser.eatToEndOfStatement();
5256 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5257 SMLoc Loc = getLexer().getLoc();
5258 Parser.eatToEndOfStatement();
5259 return Error(Loc, "unexpected token in argument list");
5262 Parser.Lex(); // Consume the EndOfStatement
5264 // Some instructions, mostly Thumb, have forms for the same mnemonic that
5265 // do and don't have a cc_out optional-def operand. With some spot-checks
5266 // of the operand list, we can figure out which variant we're trying to
5267 // parse and adjust accordingly before actually matching. We shouldn't ever
5268 // try to remove a cc_out operand that was explicitly set on the the
5269 // mnemonic, of course (CarrySetting == true). Reason number #317 the
5270 // table driven matcher doesn't fit well with the ARM instruction set.
5271 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5272 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5273 Operands.erase(Operands.begin() + 1);
5277 // Some instructions have the same mnemonic, but don't always
5278 // have a predicate. Distinguish them here and delete the
5279 // predicate if needed.
5280 if (shouldOmitPredicateOperand(Mnemonic, Operands)) {
5281 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5282 Operands.erase(Operands.begin() + 1);
5286 // ARM mode 'blx' need special handling, as the register operand version
5287 // is predicable, but the label operand version is not. So, we can't rely
5288 // on the Mnemonic based checking to correctly figure out when to put
5289 // a k_CondCode operand in the list. If we're trying to match the label
5290 // version, remove the k_CondCode operand here.
5291 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5292 static_cast<ARMOperand*>(Operands[2])->isImm()) {
5293 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5294 Operands.erase(Operands.begin() + 1);
5298 // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5299 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5300 // a single GPRPair reg operand is used in the .td file to replace the two
5301 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5302 // expressed as a GPRPair, so we have to manually merge them.
5303 // FIXME: We would really like to be able to tablegen'erate this.
5304 if (!isThumb() && Operands.size() > 4 &&
5305 (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
5306 Mnemonic == "stlexd")) {
5307 bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
5308 unsigned Idx = isLoad ? 2 : 3;
5309 ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]);
5310 ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]);
5312 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5313 // Adjust only if Op1 and Op2 are GPRs.
5314 if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) &&
5315 MRC.contains(Op2->getReg())) {
5316 unsigned Reg1 = Op1->getReg();
5317 unsigned Reg2 = Op2->getReg();
5318 unsigned Rt = MRI->getEncodingValue(Reg1);
5319 unsigned Rt2 = MRI->getEncodingValue(Reg2);
5321 // Rt2 must be Rt + 1 and Rt must be even.
5322 if (Rt + 1 != Rt2 || (Rt & 1)) {
5323 Error(Op2->getStartLoc(), isLoad ?
5324 "destination operands must be sequential" :
5325 "source operands must be sequential");
5328 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5329 &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5330 Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2);
5331 Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg(
5332 NewReg, Op1->getStartLoc(), Op2->getEndLoc()));
5338 // FIXME: As said above, this is all a pretty gross hack. This instruction
5339 // does not fit with other "subs" and tblgen.
5340 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
5341 // so the Mnemonic is the original name "subs" and delete the predicate
5342 // operand so it will match the table entry.
5343 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
5344 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5345 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::PC &&
5346 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5347 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::LR &&
5348 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5349 ARMOperand *Op0 = static_cast<ARMOperand*>(Operands[0]);
5350 Operands.erase(Operands.begin());
5352 Operands.insert(Operands.begin(), ARMOperand::CreateToken(Name, NameLoc));
5354 ARMOperand *Op1 = static_cast<ARMOperand*>(Operands[1]);
5355 Operands.erase(Operands.begin() + 1);
5361 // Validate context-sensitive operand constraints.
5363 // return 'true' if register list contains non-low GPR registers,
5364 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5365 // 'containsReg' to true.
5366 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5367 unsigned HiReg, bool &containsReg) {
5368 containsReg = false;
5369 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5370 unsigned OpReg = Inst.getOperand(i).getReg();
5373 // Anything other than a low register isn't legal here.
5374 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5380 // Check if the specified regisgter is in the register list of the inst,
5381 // starting at the indicated operand number.
5382 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5383 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5384 unsigned OpReg = Inst.getOperand(i).getReg();
5391 // Return true if instruction has the interesting property of being
5392 // allowed in IT blocks, but not being predicable.
5393 static bool instIsBreakpoint(const MCInst &Inst) {
5394 return Inst.getOpcode() == ARM::tBKPT ||
5395 Inst.getOpcode() == ARM::BKPT ||
5396 Inst.getOpcode() == ARM::tHLT ||
5397 Inst.getOpcode() == ARM::HLT;
5401 // FIXME: We would really like to be able to tablegen'erate this.
5403 validateInstruction(MCInst &Inst,
5404 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5405 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
5406 SMLoc Loc = Operands[0]->getStartLoc();
5408 // Check the IT block state first.
5409 // NOTE: BKPT and HLT instructions have the interesting property of being
5410 // allowed in IT blocks, but not being predicable. They just always execute.
5411 if (inITBlock() && !instIsBreakpoint(Inst)) {
5413 if (ITState.FirstCond)
5414 ITState.FirstCond = false;
5416 Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5417 // The instruction must be predicable.
5418 if (!MCID.isPredicable())
5419 return Error(Loc, "instructions in IT block must be predicable");
5420 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5421 unsigned ITCond = Bit ? ITState.Cond :
5422 ARMCC::getOppositeCondition(ITState.Cond);
5423 if (Cond != ITCond) {
5424 // Find the condition code Operand to get its SMLoc information.
5426 for (unsigned I = 1; I < Operands.size(); ++I)
5427 if (static_cast<ARMOperand*>(Operands[I])->isCondCode())
5428 CondLoc = Operands[I]->getStartLoc();
5429 return Error(CondLoc, "incorrect condition in IT block; got '" +
5430 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5431 "', but expected '" +
5432 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5434 // Check for non-'al' condition codes outside of the IT block.
5435 } else if (isThumbTwo() && MCID.isPredicable() &&
5436 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5437 ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
5438 Inst.getOpcode() != ARM::t2Bcc)
5439 return Error(Loc, "predicated instructions must be in IT block");
5441 const unsigned Opcode = Inst.getOpcode();
5445 case ARM::LDRD_POST: {
5446 const unsigned RtReg = Inst.getOperand(0).getReg();
5449 if (RtReg == ARM::LR)
5450 return Error(Operands[3]->getStartLoc(),
5453 const unsigned Rt = MRI->getEncodingValue(RtReg);
5454 // Rt must be even-numbered.
5456 return Error(Operands[3]->getStartLoc(),
5457 "Rt must be even-numbered");
5459 // Rt2 must be Rt + 1.
5460 const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5462 return Error(Operands[3]->getStartLoc(),
5463 "destination operands must be sequential");
5465 if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) {
5466 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
5467 // For addressing modes with writeback, the base register needs to be
5468 // different from the destination registers.
5469 if (Rn == Rt || Rn == Rt2)
5470 return Error(Operands[3]->getStartLoc(),
5471 "base register needs to be different from destination "
5478 case ARM::t2LDRD_PRE:
5479 case ARM::t2LDRD_POST: {
5480 // Rt2 must be different from Rt.
5481 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5482 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5484 return Error(Operands[3]->getStartLoc(),
5485 "destination operands can't be identical");
5489 // Rt2 must be Rt + 1.
5490 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5491 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5493 return Error(Operands[3]->getStartLoc(),
5494 "source operands must be sequential");
5498 case ARM::STRD_POST: {
5499 // Rt2 must be Rt + 1.
5500 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5501 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5503 return Error(Operands[3]->getStartLoc(),
5504 "source operands must be sequential");
5509 // Width must be in range [1, 32-lsb].
5510 unsigned LSB = Inst.getOperand(2).getImm();
5511 unsigned Widthm1 = Inst.getOperand(3).getImm();
5512 if (Widthm1 >= 32 - LSB)
5513 return Error(Operands[5]->getStartLoc(),
5514 "bitfield width must be in range [1,32-lsb]");
5517 // Notionally handles ARM::tLDMIA_UPD too.
5519 // If we're parsing Thumb2, the .w variant is available and handles
5520 // most cases that are normally illegal for a Thumb1 LDM instruction.
5521 // We'll make the transformation in processInstruction() if necessary.
5523 // Thumb LDM instructions are writeback iff the base register is not
5524 // in the register list.
5525 unsigned Rn = Inst.getOperand(0).getReg();
5526 bool HasWritebackToken =
5527 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5528 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5529 bool ListContainsBase;
5530 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
5531 return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
5532 "registers must be in range r0-r7");
5533 // If we should have writeback, then there should be a '!' token.
5534 if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
5535 return Error(Operands[2]->getStartLoc(),
5536 "writeback operator '!' expected");
5537 // If we should not have writeback, there must not be a '!'. This is
5538 // true even for the 32-bit wide encodings.
5539 if (ListContainsBase && HasWritebackToken)
5540 return Error(Operands[3]->getStartLoc(),
5541 "writeback operator '!' not allowed when base register "
5542 "in register list");
5546 case ARM::LDMIA_UPD:
5547 case ARM::LDMDB_UPD:
5548 case ARM::LDMIB_UPD:
5549 case ARM::LDMDA_UPD:
5550 // ARM variants loading and updating the same register are only officially
5551 // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
5555 case ARM::t2LDMIA_UPD:
5556 case ARM::t2LDMDB_UPD:
5557 case ARM::t2STMIA_UPD:
5558 case ARM::t2STMDB_UPD: {
5559 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5560 return Error(Operands.back()->getStartLoc(),
5561 "writeback register not allowed in register list");
5564 case ARM::sysLDMIA_UPD:
5565 case ARM::sysLDMDA_UPD:
5566 case ARM::sysLDMDB_UPD:
5567 case ARM::sysLDMIB_UPD:
5568 if (!listContainsReg(Inst, 3, ARM::PC))
5569 return Error(Operands[4]->getStartLoc(),
5570 "writeback register only allowed on system LDM "
5571 "if PC in register-list");
5573 case ARM::sysSTMIA_UPD:
5574 case ARM::sysSTMDA_UPD:
5575 case ARM::sysSTMDB_UPD:
5576 case ARM::sysSTMIB_UPD:
5577 return Error(Operands[2]->getStartLoc(),
5578 "system STM cannot have writeback register");
5581 // The second source operand must be the same register as the destination
5584 // In this case, we must directly check the parsed operands because the
5585 // cvtThumbMultiply() function is written in such a way that it guarantees
5586 // this first statement is always true for the new Inst. Essentially, the
5587 // destination is unconditionally copied into the second source operand
5588 // without checking to see if it matches what we actually parsed.
5589 if (Operands.size() == 6 &&
5590 (((ARMOperand*)Operands[3])->getReg() !=
5591 ((ARMOperand*)Operands[5])->getReg()) &&
5592 (((ARMOperand*)Operands[3])->getReg() !=
5593 ((ARMOperand*)Operands[4])->getReg())) {
5594 return Error(Operands[3]->getStartLoc(),
5595 "destination register must match source register");
5599 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5600 // so only issue a diagnostic for thumb1. The instructions will be
5601 // switched to the t2 encodings in processInstruction() if necessary.
5603 bool ListContainsBase;
5604 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
5606 return Error(Operands[2]->getStartLoc(),
5607 "registers must be in range r0-r7 or pc");
5611 bool ListContainsBase;
5612 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
5614 return Error(Operands[2]->getStartLoc(),
5615 "registers must be in range r0-r7 or lr");
5618 case ARM::tSTMIA_UPD: {
5619 bool ListContainsBase, InvalidLowList;
5620 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
5621 0, ListContainsBase);
5622 if (InvalidLowList && !isThumbTwo())
5623 return Error(Operands[4]->getStartLoc(),
5624 "registers must be in range r0-r7");
5626 // This would be converted to a 32-bit stm, but that's not valid if the
5627 // writeback register is in the list.
5628 if (InvalidLowList && ListContainsBase)
5629 return Error(Operands[4]->getStartLoc(),
5630 "writeback operator '!' not allowed when base register "
5631 "in register list");
5634 case ARM::tADDrSP: {
5635 // If the non-SP source operand and the destination operand are not the
5636 // same, we need thumb2 (for the wide encoding), or we have an error.
5637 if (!isThumbTwo() &&
5638 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5639 return Error(Operands[4]->getStartLoc(),
5640 "source register must be the same as destination");
5644 // Final range checking for Thumb unconditional branch instructions.
5646 if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<11, 1>())
5647 return Error(Operands[2]->getStartLoc(), "branch target out of range");
5650 int op = (Operands[2]->isImm()) ? 2 : 3;
5651 if (!(static_cast<ARMOperand*>(Operands[op]))->isSignedOffset<24, 1>())
5652 return Error(Operands[op]->getStartLoc(), "branch target out of range");
5655 // Final range checking for Thumb conditional branch instructions.
5657 if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<8, 1>())
5658 return Error(Operands[2]->getStartLoc(), "branch target out of range");
5661 int Op = (Operands[2]->isImm()) ? 2 : 3;
5662 if (!(static_cast<ARMOperand*>(Operands[Op]))->isSignedOffset<20, 1>())
5663 return Error(Operands[Op]->getStartLoc(), "branch target out of range");
5671 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5673 default: llvm_unreachable("unexpected opcode!");
5675 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5676 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5677 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5678 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5679 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5680 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5681 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
5682 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5683 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5686 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5687 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5688 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5689 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5690 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5692 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5693 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5694 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5695 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5696 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5698 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
5699 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5700 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5701 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5702 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5705 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5706 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5707 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5708 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5709 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5710 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5711 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5712 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5713 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5714 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5715 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
5716 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5717 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5718 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5719 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5722 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5723 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5724 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5725 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5726 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5727 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5728 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5729 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5730 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5731 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5732 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5733 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5734 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
5735 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5736 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5737 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
5738 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5739 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5742 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5743 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5744 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5745 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5746 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5747 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5748 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5749 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5750 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5751 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5752 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
5753 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5754 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5755 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5756 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5759 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5760 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5761 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5762 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5763 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5764 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5765 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5766 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5767 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5768 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5769 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5770 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5771 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
5772 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5773 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5774 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
5775 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5776 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5780 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
5782 default: llvm_unreachable("unexpected opcode!");
5784 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5785 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5786 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5787 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5788 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5789 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5790 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
5791 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5792 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5795 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5796 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5797 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5798 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5799 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5800 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5801 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5802 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5803 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5804 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5805 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
5806 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5807 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5808 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5809 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5812 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5813 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5814 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5815 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5816 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5817 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5818 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5819 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5820 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5821 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5822 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5823 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5824 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
5825 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5826 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5827 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5828 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5829 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5832 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5833 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5834 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5835 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5836 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5837 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5838 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5839 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5840 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5841 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5842 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
5843 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5844 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5845 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5846 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5849 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5850 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5851 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5852 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5853 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5854 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5855 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5856 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5857 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5858 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5859 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5860 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5861 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
5862 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5863 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5864 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
5865 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5866 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
5869 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5870 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5871 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5872 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
5873 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5874 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5875 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5876 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5877 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5878 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5879 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
5880 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5881 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5882 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5883 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5886 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5887 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5888 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5889 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5890 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5891 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5892 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5893 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5894 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5895 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
5896 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
5897 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5898 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
5899 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
5900 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
5901 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
5902 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
5903 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
5906 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5907 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5908 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5909 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5910 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5911 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5912 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5913 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5914 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5915 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5916 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5917 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5918 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
5919 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
5920 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
5921 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
5922 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
5923 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
5928 processInstruction(MCInst &Inst,
5929 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5930 switch (Inst.getOpcode()) {
5931 // Alias for alternate form of 'ADR Rd, #imm' instruction.
5933 if (Inst.getOperand(1).getReg() != ARM::PC ||
5934 Inst.getOperand(5).getReg() != 0)
5937 TmpInst.setOpcode(ARM::ADR);
5938 TmpInst.addOperand(Inst.getOperand(0));
5939 TmpInst.addOperand(Inst.getOperand(2));
5940 TmpInst.addOperand(Inst.getOperand(3));
5941 TmpInst.addOperand(Inst.getOperand(4));
5945 // Aliases for alternate PC+imm syntax of LDR instructions.
5946 case ARM::t2LDRpcrel:
5947 // Select the narrow version if the immediate will fit.
5948 if (Inst.getOperand(1).getImm() > 0 &&
5949 Inst.getOperand(1).getImm() <= 0xff &&
5950 !(static_cast<ARMOperand*>(Operands[2])->isToken() &&
5951 static_cast<ARMOperand*>(Operands[2])->getToken() == ".w"))
5952 Inst.setOpcode(ARM::tLDRpci);
5954 Inst.setOpcode(ARM::t2LDRpci);
5956 case ARM::t2LDRBpcrel:
5957 Inst.setOpcode(ARM::t2LDRBpci);
5959 case ARM::t2LDRHpcrel:
5960 Inst.setOpcode(ARM::t2LDRHpci);
5962 case ARM::t2LDRSBpcrel:
5963 Inst.setOpcode(ARM::t2LDRSBpci);
5965 case ARM::t2LDRSHpcrel:
5966 Inst.setOpcode(ARM::t2LDRSHpci);
5968 // Handle NEON VST complex aliases.
5969 case ARM::VST1LNdWB_register_Asm_8:
5970 case ARM::VST1LNdWB_register_Asm_16:
5971 case ARM::VST1LNdWB_register_Asm_32: {
5973 // Shuffle the operands around so the lane index operand is in the
5976 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5977 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5978 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5979 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5980 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5981 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5982 TmpInst.addOperand(Inst.getOperand(1)); // lane
5983 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5984 TmpInst.addOperand(Inst.getOperand(6));
5989 case ARM::VST2LNdWB_register_Asm_8:
5990 case ARM::VST2LNdWB_register_Asm_16:
5991 case ARM::VST2LNdWB_register_Asm_32:
5992 case ARM::VST2LNqWB_register_Asm_16:
5993 case ARM::VST2LNqWB_register_Asm_32: {
5995 // Shuffle the operands around so the lane index operand is in the
5998 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5999 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6000 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6001 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6002 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6003 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6004 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6006 TmpInst.addOperand(Inst.getOperand(1)); // lane
6007 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6008 TmpInst.addOperand(Inst.getOperand(6));
6013 case ARM::VST3LNdWB_register_Asm_8:
6014 case ARM::VST3LNdWB_register_Asm_16:
6015 case ARM::VST3LNdWB_register_Asm_32:
6016 case ARM::VST3LNqWB_register_Asm_16:
6017 case ARM::VST3LNqWB_register_Asm_32: {
6019 // Shuffle the operands around so the lane index operand is in the
6022 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6023 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6024 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6025 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6026 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6027 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6028 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6030 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6032 TmpInst.addOperand(Inst.getOperand(1)); // lane
6033 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6034 TmpInst.addOperand(Inst.getOperand(6));
6039 case ARM::VST4LNdWB_register_Asm_8:
6040 case ARM::VST4LNdWB_register_Asm_16:
6041 case ARM::VST4LNdWB_register_Asm_32:
6042 case ARM::VST4LNqWB_register_Asm_16:
6043 case ARM::VST4LNqWB_register_Asm_32: {
6045 // Shuffle the operands around so the lane index operand is in the
6048 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6049 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6050 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6051 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6052 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6053 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6054 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6056 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6058 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6060 TmpInst.addOperand(Inst.getOperand(1)); // lane
6061 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6062 TmpInst.addOperand(Inst.getOperand(6));
6067 case ARM::VST1LNdWB_fixed_Asm_8:
6068 case ARM::VST1LNdWB_fixed_Asm_16:
6069 case ARM::VST1LNdWB_fixed_Asm_32: {
6071 // Shuffle the operands around so the lane index operand is in the
6074 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6075 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6076 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6077 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6078 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6079 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6080 TmpInst.addOperand(Inst.getOperand(1)); // lane
6081 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6082 TmpInst.addOperand(Inst.getOperand(5));
6087 case ARM::VST2LNdWB_fixed_Asm_8:
6088 case ARM::VST2LNdWB_fixed_Asm_16:
6089 case ARM::VST2LNdWB_fixed_Asm_32:
6090 case ARM::VST2LNqWB_fixed_Asm_16:
6091 case ARM::VST2LNqWB_fixed_Asm_32: {
6093 // Shuffle the operands around so the lane index operand is in the
6096 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6097 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6098 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6099 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6100 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6101 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6102 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6104 TmpInst.addOperand(Inst.getOperand(1)); // lane
6105 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6106 TmpInst.addOperand(Inst.getOperand(5));
6111 case ARM::VST3LNdWB_fixed_Asm_8:
6112 case ARM::VST3LNdWB_fixed_Asm_16:
6113 case ARM::VST3LNdWB_fixed_Asm_32:
6114 case ARM::VST3LNqWB_fixed_Asm_16:
6115 case ARM::VST3LNqWB_fixed_Asm_32: {
6117 // Shuffle the operands around so the lane index operand is in the
6120 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6121 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6122 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6123 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6124 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6125 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6126 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6128 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6130 TmpInst.addOperand(Inst.getOperand(1)); // lane
6131 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6132 TmpInst.addOperand(Inst.getOperand(5));
6137 case ARM::VST4LNdWB_fixed_Asm_8:
6138 case ARM::VST4LNdWB_fixed_Asm_16:
6139 case ARM::VST4LNdWB_fixed_Asm_32:
6140 case ARM::VST4LNqWB_fixed_Asm_16:
6141 case ARM::VST4LNqWB_fixed_Asm_32: {
6143 // Shuffle the operands around so the lane index operand is in the
6146 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6147 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6148 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6149 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6150 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6151 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6152 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6154 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6156 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6158 TmpInst.addOperand(Inst.getOperand(1)); // lane
6159 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6160 TmpInst.addOperand(Inst.getOperand(5));
6165 case ARM::VST1LNdAsm_8:
6166 case ARM::VST1LNdAsm_16:
6167 case ARM::VST1LNdAsm_32: {
6169 // Shuffle the operands around so the lane index operand is in the
6172 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6173 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6174 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6175 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6176 TmpInst.addOperand(Inst.getOperand(1)); // lane
6177 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6178 TmpInst.addOperand(Inst.getOperand(5));
6183 case ARM::VST2LNdAsm_8:
6184 case ARM::VST2LNdAsm_16:
6185 case ARM::VST2LNdAsm_32:
6186 case ARM::VST2LNqAsm_16:
6187 case ARM::VST2LNqAsm_32: {
6189 // Shuffle the operands around so the lane index operand is in the
6192 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6193 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6194 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6195 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6196 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6198 TmpInst.addOperand(Inst.getOperand(1)); // lane
6199 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6200 TmpInst.addOperand(Inst.getOperand(5));
6205 case ARM::VST3LNdAsm_8:
6206 case ARM::VST3LNdAsm_16:
6207 case ARM::VST3LNdAsm_32:
6208 case ARM::VST3LNqAsm_16:
6209 case ARM::VST3LNqAsm_32: {
6211 // Shuffle the operands around so the lane index operand is in the
6214 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6215 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6216 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6217 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6218 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6220 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6222 TmpInst.addOperand(Inst.getOperand(1)); // lane
6223 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6224 TmpInst.addOperand(Inst.getOperand(5));
6229 case ARM::VST4LNdAsm_8:
6230 case ARM::VST4LNdAsm_16:
6231 case ARM::VST4LNdAsm_32:
6232 case ARM::VST4LNqAsm_16:
6233 case ARM::VST4LNqAsm_32: {
6235 // Shuffle the operands around so the lane index operand is in the
6238 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6239 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6240 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6241 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6242 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6244 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6246 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6248 TmpInst.addOperand(Inst.getOperand(1)); // lane
6249 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6250 TmpInst.addOperand(Inst.getOperand(5));
6255 // Handle NEON VLD complex aliases.
6256 case ARM::VLD1LNdWB_register_Asm_8:
6257 case ARM::VLD1LNdWB_register_Asm_16:
6258 case ARM::VLD1LNdWB_register_Asm_32: {
6260 // Shuffle the operands around so the lane index operand is in the
6263 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6264 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6265 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6266 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6267 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6268 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6269 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6270 TmpInst.addOperand(Inst.getOperand(1)); // lane
6271 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6272 TmpInst.addOperand(Inst.getOperand(6));
6277 case ARM::VLD2LNdWB_register_Asm_8:
6278 case ARM::VLD2LNdWB_register_Asm_16:
6279 case ARM::VLD2LNdWB_register_Asm_32:
6280 case ARM::VLD2LNqWB_register_Asm_16:
6281 case ARM::VLD2LNqWB_register_Asm_32: {
6283 // Shuffle the operands around so the lane index operand is in the
6286 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6287 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6288 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6290 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6291 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6292 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6293 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6294 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6295 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6297 TmpInst.addOperand(Inst.getOperand(1)); // lane
6298 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6299 TmpInst.addOperand(Inst.getOperand(6));
6304 case ARM::VLD3LNdWB_register_Asm_8:
6305 case ARM::VLD3LNdWB_register_Asm_16:
6306 case ARM::VLD3LNdWB_register_Asm_32:
6307 case ARM::VLD3LNqWB_register_Asm_16:
6308 case ARM::VLD3LNqWB_register_Asm_32: {
6310 // Shuffle the operands around so the lane index operand is in the
6313 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6314 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6315 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6317 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6319 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6320 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6321 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6322 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6323 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6324 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6326 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6328 TmpInst.addOperand(Inst.getOperand(1)); // lane
6329 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6330 TmpInst.addOperand(Inst.getOperand(6));
6335 case ARM::VLD4LNdWB_register_Asm_8:
6336 case ARM::VLD4LNdWB_register_Asm_16:
6337 case ARM::VLD4LNdWB_register_Asm_32:
6338 case ARM::VLD4LNqWB_register_Asm_16:
6339 case ARM::VLD4LNqWB_register_Asm_32: {
6341 // Shuffle the operands around so the lane index operand is in the
6344 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6345 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6346 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6348 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6350 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6352 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6353 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6354 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6355 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6356 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6357 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6359 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6361 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6363 TmpInst.addOperand(Inst.getOperand(1)); // lane
6364 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6365 TmpInst.addOperand(Inst.getOperand(6));
6370 case ARM::VLD1LNdWB_fixed_Asm_8:
6371 case ARM::VLD1LNdWB_fixed_Asm_16:
6372 case ARM::VLD1LNdWB_fixed_Asm_32: {
6374 // Shuffle the operands around so the lane index operand is in the
6377 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6378 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6379 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6380 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6381 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6382 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6383 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6384 TmpInst.addOperand(Inst.getOperand(1)); // lane
6385 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6386 TmpInst.addOperand(Inst.getOperand(5));
6391 case ARM::VLD2LNdWB_fixed_Asm_8:
6392 case ARM::VLD2LNdWB_fixed_Asm_16:
6393 case ARM::VLD2LNdWB_fixed_Asm_32:
6394 case ARM::VLD2LNqWB_fixed_Asm_16:
6395 case ARM::VLD2LNqWB_fixed_Asm_32: {
6397 // Shuffle the operands around so the lane index operand is in the
6400 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6401 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6402 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6404 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6405 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6406 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6407 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6408 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6409 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6411 TmpInst.addOperand(Inst.getOperand(1)); // lane
6412 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6413 TmpInst.addOperand(Inst.getOperand(5));
6418 case ARM::VLD3LNdWB_fixed_Asm_8:
6419 case ARM::VLD3LNdWB_fixed_Asm_16:
6420 case ARM::VLD3LNdWB_fixed_Asm_32:
6421 case ARM::VLD3LNqWB_fixed_Asm_16:
6422 case ARM::VLD3LNqWB_fixed_Asm_32: {
6424 // Shuffle the operands around so the lane index operand is in the
6427 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6428 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6429 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6431 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6433 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6434 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6435 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6436 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6437 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6438 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6440 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6442 TmpInst.addOperand(Inst.getOperand(1)); // lane
6443 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6444 TmpInst.addOperand(Inst.getOperand(5));
6449 case ARM::VLD4LNdWB_fixed_Asm_8:
6450 case ARM::VLD4LNdWB_fixed_Asm_16:
6451 case ARM::VLD4LNdWB_fixed_Asm_32:
6452 case ARM::VLD4LNqWB_fixed_Asm_16:
6453 case ARM::VLD4LNqWB_fixed_Asm_32: {
6455 // Shuffle the operands around so the lane index operand is in the
6458 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6459 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6460 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6462 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6464 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6466 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6467 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6468 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6469 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6470 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6471 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6473 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6475 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6477 TmpInst.addOperand(Inst.getOperand(1)); // lane
6478 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6479 TmpInst.addOperand(Inst.getOperand(5));
6484 case ARM::VLD1LNdAsm_8:
6485 case ARM::VLD1LNdAsm_16:
6486 case ARM::VLD1LNdAsm_32: {
6488 // Shuffle the operands around so the lane index operand is in the
6491 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6492 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6493 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6494 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6495 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6496 TmpInst.addOperand(Inst.getOperand(1)); // lane
6497 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6498 TmpInst.addOperand(Inst.getOperand(5));
6503 case ARM::VLD2LNdAsm_8:
6504 case ARM::VLD2LNdAsm_16:
6505 case ARM::VLD2LNdAsm_32:
6506 case ARM::VLD2LNqAsm_16:
6507 case ARM::VLD2LNqAsm_32: {
6509 // Shuffle the operands around so the lane index operand is in the
6512 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6513 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6514 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6516 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6517 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6518 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6519 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6521 TmpInst.addOperand(Inst.getOperand(1)); // lane
6522 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6523 TmpInst.addOperand(Inst.getOperand(5));
6528 case ARM::VLD3LNdAsm_8:
6529 case ARM::VLD3LNdAsm_16:
6530 case ARM::VLD3LNdAsm_32:
6531 case ARM::VLD3LNqAsm_16:
6532 case ARM::VLD3LNqAsm_32: {
6534 // Shuffle the operands around so the lane index operand is in the
6537 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6538 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6539 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6541 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6543 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6544 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6545 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6546 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6548 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6550 TmpInst.addOperand(Inst.getOperand(1)); // lane
6551 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6552 TmpInst.addOperand(Inst.getOperand(5));
6557 case ARM::VLD4LNdAsm_8:
6558 case ARM::VLD4LNdAsm_16:
6559 case ARM::VLD4LNdAsm_32:
6560 case ARM::VLD4LNqAsm_16:
6561 case ARM::VLD4LNqAsm_32: {
6563 // Shuffle the operands around so the lane index operand is in the
6566 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6567 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6568 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6570 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6572 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6574 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6575 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6576 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6577 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6579 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6581 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6583 TmpInst.addOperand(Inst.getOperand(1)); // lane
6584 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6585 TmpInst.addOperand(Inst.getOperand(5));
6590 // VLD3DUP single 3-element structure to all lanes instructions.
6591 case ARM::VLD3DUPdAsm_8:
6592 case ARM::VLD3DUPdAsm_16:
6593 case ARM::VLD3DUPdAsm_32:
6594 case ARM::VLD3DUPqAsm_8:
6595 case ARM::VLD3DUPqAsm_16:
6596 case ARM::VLD3DUPqAsm_32: {
6599 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6600 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6601 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6603 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6605 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6606 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6607 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6608 TmpInst.addOperand(Inst.getOperand(4));
6613 case ARM::VLD3DUPdWB_fixed_Asm_8:
6614 case ARM::VLD3DUPdWB_fixed_Asm_16:
6615 case ARM::VLD3DUPdWB_fixed_Asm_32:
6616 case ARM::VLD3DUPqWB_fixed_Asm_8:
6617 case ARM::VLD3DUPqWB_fixed_Asm_16:
6618 case ARM::VLD3DUPqWB_fixed_Asm_32: {
6621 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6622 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6623 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6625 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6627 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6628 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6629 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6630 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6631 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6632 TmpInst.addOperand(Inst.getOperand(4));
6637 case ARM::VLD3DUPdWB_register_Asm_8:
6638 case ARM::VLD3DUPdWB_register_Asm_16:
6639 case ARM::VLD3DUPdWB_register_Asm_32:
6640 case ARM::VLD3DUPqWB_register_Asm_8:
6641 case ARM::VLD3DUPqWB_register_Asm_16:
6642 case ARM::VLD3DUPqWB_register_Asm_32: {
6645 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6646 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6647 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6649 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6651 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6652 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6653 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6654 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6655 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6656 TmpInst.addOperand(Inst.getOperand(5));
6661 // VLD3 multiple 3-element structure instructions.
6662 case ARM::VLD3dAsm_8:
6663 case ARM::VLD3dAsm_16:
6664 case ARM::VLD3dAsm_32:
6665 case ARM::VLD3qAsm_8:
6666 case ARM::VLD3qAsm_16:
6667 case ARM::VLD3qAsm_32: {
6670 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6671 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6672 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6674 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6676 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6677 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6678 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6679 TmpInst.addOperand(Inst.getOperand(4));
6684 case ARM::VLD3dWB_fixed_Asm_8:
6685 case ARM::VLD3dWB_fixed_Asm_16:
6686 case ARM::VLD3dWB_fixed_Asm_32:
6687 case ARM::VLD3qWB_fixed_Asm_8:
6688 case ARM::VLD3qWB_fixed_Asm_16:
6689 case ARM::VLD3qWB_fixed_Asm_32: {
6692 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6693 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6694 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6696 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6698 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6699 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6700 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6701 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6702 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6703 TmpInst.addOperand(Inst.getOperand(4));
6708 case ARM::VLD3dWB_register_Asm_8:
6709 case ARM::VLD3dWB_register_Asm_16:
6710 case ARM::VLD3dWB_register_Asm_32:
6711 case ARM::VLD3qWB_register_Asm_8:
6712 case ARM::VLD3qWB_register_Asm_16:
6713 case ARM::VLD3qWB_register_Asm_32: {
6716 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6717 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6718 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6720 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6722 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6723 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6724 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6725 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6726 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6727 TmpInst.addOperand(Inst.getOperand(5));
6732 // VLD4DUP single 3-element structure to all lanes instructions.
6733 case ARM::VLD4DUPdAsm_8:
6734 case ARM::VLD4DUPdAsm_16:
6735 case ARM::VLD4DUPdAsm_32:
6736 case ARM::VLD4DUPqAsm_8:
6737 case ARM::VLD4DUPqAsm_16:
6738 case ARM::VLD4DUPqAsm_32: {
6741 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6742 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6743 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6745 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6747 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6749 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6750 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6751 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6752 TmpInst.addOperand(Inst.getOperand(4));
6757 case ARM::VLD4DUPdWB_fixed_Asm_8:
6758 case ARM::VLD4DUPdWB_fixed_Asm_16:
6759 case ARM::VLD4DUPdWB_fixed_Asm_32:
6760 case ARM::VLD4DUPqWB_fixed_Asm_8:
6761 case ARM::VLD4DUPqWB_fixed_Asm_16:
6762 case ARM::VLD4DUPqWB_fixed_Asm_32: {
6765 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6766 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6767 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6769 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6771 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6773 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6774 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6775 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6776 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6777 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6778 TmpInst.addOperand(Inst.getOperand(4));
6783 case ARM::VLD4DUPdWB_register_Asm_8:
6784 case ARM::VLD4DUPdWB_register_Asm_16:
6785 case ARM::VLD4DUPdWB_register_Asm_32:
6786 case ARM::VLD4DUPqWB_register_Asm_8:
6787 case ARM::VLD4DUPqWB_register_Asm_16:
6788 case ARM::VLD4DUPqWB_register_Asm_32: {
6791 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6792 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6793 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6795 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6797 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6799 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6800 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6801 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6802 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6803 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6804 TmpInst.addOperand(Inst.getOperand(5));
6809 // VLD4 multiple 4-element structure instructions.
6810 case ARM::VLD4dAsm_8:
6811 case ARM::VLD4dAsm_16:
6812 case ARM::VLD4dAsm_32:
6813 case ARM::VLD4qAsm_8:
6814 case ARM::VLD4qAsm_16:
6815 case ARM::VLD4qAsm_32: {
6818 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6819 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6820 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6822 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6824 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6826 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6827 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6828 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6829 TmpInst.addOperand(Inst.getOperand(4));
6834 case ARM::VLD4dWB_fixed_Asm_8:
6835 case ARM::VLD4dWB_fixed_Asm_16:
6836 case ARM::VLD4dWB_fixed_Asm_32:
6837 case ARM::VLD4qWB_fixed_Asm_8:
6838 case ARM::VLD4qWB_fixed_Asm_16:
6839 case ARM::VLD4qWB_fixed_Asm_32: {
6842 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6843 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6844 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6846 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6848 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6850 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6851 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6852 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6853 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6854 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6855 TmpInst.addOperand(Inst.getOperand(4));
6860 case ARM::VLD4dWB_register_Asm_8:
6861 case ARM::VLD4dWB_register_Asm_16:
6862 case ARM::VLD4dWB_register_Asm_32:
6863 case ARM::VLD4qWB_register_Asm_8:
6864 case ARM::VLD4qWB_register_Asm_16:
6865 case ARM::VLD4qWB_register_Asm_32: {
6868 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6869 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6870 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6872 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6874 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6876 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6877 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6878 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6879 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6880 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6881 TmpInst.addOperand(Inst.getOperand(5));
6886 // VST3 multiple 3-element structure instructions.
6887 case ARM::VST3dAsm_8:
6888 case ARM::VST3dAsm_16:
6889 case ARM::VST3dAsm_32:
6890 case ARM::VST3qAsm_8:
6891 case ARM::VST3qAsm_16:
6892 case ARM::VST3qAsm_32: {
6895 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6896 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6897 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6898 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6899 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6901 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6903 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6904 TmpInst.addOperand(Inst.getOperand(4));
6909 case ARM::VST3dWB_fixed_Asm_8:
6910 case ARM::VST3dWB_fixed_Asm_16:
6911 case ARM::VST3dWB_fixed_Asm_32:
6912 case ARM::VST3qWB_fixed_Asm_8:
6913 case ARM::VST3qWB_fixed_Asm_16:
6914 case ARM::VST3qWB_fixed_Asm_32: {
6917 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6918 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6919 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6920 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6921 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6922 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6923 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6925 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6927 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6928 TmpInst.addOperand(Inst.getOperand(4));
6933 case ARM::VST3dWB_register_Asm_8:
6934 case ARM::VST3dWB_register_Asm_16:
6935 case ARM::VST3dWB_register_Asm_32:
6936 case ARM::VST3qWB_register_Asm_8:
6937 case ARM::VST3qWB_register_Asm_16:
6938 case ARM::VST3qWB_register_Asm_32: {
6941 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6942 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6943 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6944 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6945 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6946 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6947 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6949 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6951 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6952 TmpInst.addOperand(Inst.getOperand(5));
6957 // VST4 multiple 3-element structure instructions.
6958 case ARM::VST4dAsm_8:
6959 case ARM::VST4dAsm_16:
6960 case ARM::VST4dAsm_32:
6961 case ARM::VST4qAsm_8:
6962 case ARM::VST4qAsm_16:
6963 case ARM::VST4qAsm_32: {
6966 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6967 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6968 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6969 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6970 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6972 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6974 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6976 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6977 TmpInst.addOperand(Inst.getOperand(4));
6982 case ARM::VST4dWB_fixed_Asm_8:
6983 case ARM::VST4dWB_fixed_Asm_16:
6984 case ARM::VST4dWB_fixed_Asm_32:
6985 case ARM::VST4qWB_fixed_Asm_8:
6986 case ARM::VST4qWB_fixed_Asm_16:
6987 case ARM::VST4qWB_fixed_Asm_32: {
6990 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6991 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6992 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6993 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6994 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6995 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6996 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6998 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7000 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7002 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7003 TmpInst.addOperand(Inst.getOperand(4));
7008 case ARM::VST4dWB_register_Asm_8:
7009 case ARM::VST4dWB_register_Asm_16:
7010 case ARM::VST4dWB_register_Asm_32:
7011 case ARM::VST4qWB_register_Asm_8:
7012 case ARM::VST4qWB_register_Asm_16:
7013 case ARM::VST4qWB_register_Asm_32: {
7016 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7017 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7018 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7019 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7020 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7021 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7022 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7024 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7026 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7028 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7029 TmpInst.addOperand(Inst.getOperand(5));
7034 // Handle encoding choice for the shift-immediate instructions.
7037 case ARM::t2ASRri: {
7038 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7039 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7040 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
7041 !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
7042 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
7044 switch (Inst.getOpcode()) {
7045 default: llvm_unreachable("unexpected opcode");
7046 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
7047 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
7048 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
7050 // The Thumb1 operands aren't in the same order. Awesome, eh?
7052 TmpInst.setOpcode(NewOpc);
7053 TmpInst.addOperand(Inst.getOperand(0));
7054 TmpInst.addOperand(Inst.getOperand(5));
7055 TmpInst.addOperand(Inst.getOperand(1));
7056 TmpInst.addOperand(Inst.getOperand(2));
7057 TmpInst.addOperand(Inst.getOperand(3));
7058 TmpInst.addOperand(Inst.getOperand(4));
7065 // Handle the Thumb2 mode MOV complex aliases.
7067 case ARM::t2MOVSsr: {
7068 // Which instruction to expand to depends on the CCOut operand and
7069 // whether we're in an IT block if the register operands are low
7071 bool isNarrow = false;
7072 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7073 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7074 isARMLowRegister(Inst.getOperand(2).getReg()) &&
7075 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7076 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
7080 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
7081 default: llvm_unreachable("unexpected opcode!");
7082 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7083 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7084 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7085 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
7087 TmpInst.setOpcode(newOpc);
7088 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7090 TmpInst.addOperand(MCOperand::CreateReg(
7091 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7092 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7093 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7094 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7095 TmpInst.addOperand(Inst.getOperand(5));
7097 TmpInst.addOperand(MCOperand::CreateReg(
7098 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7103 case ARM::t2MOVSsi: {
7104 // Which instruction to expand to depends on the CCOut operand and
7105 // whether we're in an IT block if the register operands are low
7107 bool isNarrow = false;
7108 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7109 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7110 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
7114 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
7115 default: llvm_unreachable("unexpected opcode!");
7116 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7117 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7118 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7119 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7120 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7122 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
7123 if (Amount == 32) Amount = 0;
7124 TmpInst.setOpcode(newOpc);
7125 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7127 TmpInst.addOperand(MCOperand::CreateReg(
7128 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7129 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7130 if (newOpc != ARM::t2RRX)
7131 TmpInst.addOperand(MCOperand::CreateImm(Amount));
7132 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7133 TmpInst.addOperand(Inst.getOperand(4));
7135 TmpInst.addOperand(MCOperand::CreateReg(
7136 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7140 // Handle the ARM mode MOV complex aliases.
7145 ARM_AM::ShiftOpc ShiftTy;
7146 switch(Inst.getOpcode()) {
7147 default: llvm_unreachable("unexpected opcode!");
7148 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
7149 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
7150 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
7151 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
7153 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
7155 TmpInst.setOpcode(ARM::MOVsr);
7156 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7157 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7158 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7159 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7160 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7161 TmpInst.addOperand(Inst.getOperand(4));
7162 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7170 ARM_AM::ShiftOpc ShiftTy;
7171 switch(Inst.getOpcode()) {
7172 default: llvm_unreachable("unexpected opcode!");
7173 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
7174 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
7175 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7176 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
7178 // A shift by zero is a plain MOVr, not a MOVsi.
7179 unsigned Amt = Inst.getOperand(2).getImm();
7180 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
7181 // A shift by 32 should be encoded as 0 when permitted
7182 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
7184 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
7186 TmpInst.setOpcode(Opc);
7187 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7188 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7189 if (Opc == ARM::MOVsi)
7190 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7191 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7192 TmpInst.addOperand(Inst.getOperand(4));
7193 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7198 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
7200 TmpInst.setOpcode(ARM::MOVsi);
7201 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7202 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7203 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7204 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7205 TmpInst.addOperand(Inst.getOperand(3));
7206 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7210 case ARM::t2LDMIA_UPD: {
7211 // If this is a load of a single register, then we should use
7212 // a post-indexed LDR instruction instead, per the ARM ARM.
7213 if (Inst.getNumOperands() != 5)
7216 TmpInst.setOpcode(ARM::t2LDR_POST);
7217 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7218 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7219 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7220 TmpInst.addOperand(MCOperand::CreateImm(4));
7221 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7222 TmpInst.addOperand(Inst.getOperand(3));
7226 case ARM::t2STMDB_UPD: {
7227 // If this is a store of a single register, then we should use
7228 // a pre-indexed STR instruction instead, per the ARM ARM.
7229 if (Inst.getNumOperands() != 5)
7232 TmpInst.setOpcode(ARM::t2STR_PRE);
7233 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7234 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7235 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7236 TmpInst.addOperand(MCOperand::CreateImm(-4));
7237 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7238 TmpInst.addOperand(Inst.getOperand(3));
7242 case ARM::LDMIA_UPD:
7243 // If this is a load of a single register via a 'pop', then we should use
7244 // a post-indexed LDR instruction instead, per the ARM ARM.
7245 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
7246 Inst.getNumOperands() == 5) {
7248 TmpInst.setOpcode(ARM::LDR_POST_IMM);
7249 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7250 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7251 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7252 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
7253 TmpInst.addOperand(MCOperand::CreateImm(4));
7254 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7255 TmpInst.addOperand(Inst.getOperand(3));
7260 case ARM::STMDB_UPD:
7261 // If this is a store of a single register via a 'push', then we should use
7262 // a pre-indexed STR instruction instead, per the ARM ARM.
7263 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
7264 Inst.getNumOperands() == 5) {
7266 TmpInst.setOpcode(ARM::STR_PRE_IMM);
7267 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7268 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7269 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7270 TmpInst.addOperand(MCOperand::CreateImm(-4));
7271 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7272 TmpInst.addOperand(Inst.getOperand(3));
7276 case ARM::t2ADDri12:
7277 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7278 // mnemonic was used (not "addw"), encoding T3 is preferred.
7279 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
7280 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7282 Inst.setOpcode(ARM::t2ADDri);
7283 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7285 case ARM::t2SUBri12:
7286 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7287 // mnemonic was used (not "subw"), encoding T3 is preferred.
7288 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7289 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7291 Inst.setOpcode(ARM::t2SUBri);
7292 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7295 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7296 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7297 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7298 // to encoding T1 if <Rd> is omitted."
7299 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7300 Inst.setOpcode(ARM::tADDi3);
7305 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7306 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7307 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7308 // to encoding T1 if <Rd> is omitted."
7309 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7310 Inst.setOpcode(ARM::tSUBi3);
7315 case ARM::t2SUBri: {
7316 // If the destination and first source operand are the same, and
7317 // the flags are compatible with the current IT status, use encoding T2
7318 // instead of T3. For compatibility with the system 'as'. Make sure the
7319 // wide encoding wasn't explicit.
7320 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7321 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7322 (unsigned)Inst.getOperand(2).getImm() > 255 ||
7323 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7324 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7325 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7326 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7329 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7330 ARM::tADDi8 : ARM::tSUBi8);
7331 TmpInst.addOperand(Inst.getOperand(0));
7332 TmpInst.addOperand(Inst.getOperand(5));
7333 TmpInst.addOperand(Inst.getOperand(0));
7334 TmpInst.addOperand(Inst.getOperand(2));
7335 TmpInst.addOperand(Inst.getOperand(3));
7336 TmpInst.addOperand(Inst.getOperand(4));
7340 case ARM::t2ADDrr: {
7341 // If the destination and first source operand are the same, and
7342 // there's no setting of the flags, use encoding T2 instead of T3.
7343 // Note that this is only for ADD, not SUB. This mirrors the system
7344 // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7345 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7346 Inst.getOperand(5).getReg() != 0 ||
7347 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7348 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7351 TmpInst.setOpcode(ARM::tADDhirr);
7352 TmpInst.addOperand(Inst.getOperand(0));
7353 TmpInst.addOperand(Inst.getOperand(0));
7354 TmpInst.addOperand(Inst.getOperand(2));
7355 TmpInst.addOperand(Inst.getOperand(3));
7356 TmpInst.addOperand(Inst.getOperand(4));
7360 case ARM::tADDrSP: {
7361 // If the non-SP source operand and the destination operand are not the
7362 // same, we need to use the 32-bit encoding if it's available.
7363 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7364 Inst.setOpcode(ARM::t2ADDrr);
7365 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7371 // A Thumb conditional branch outside of an IT block is a tBcc.
7372 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7373 Inst.setOpcode(ARM::tBcc);
7378 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7379 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7380 Inst.setOpcode(ARM::t2Bcc);
7385 // If the conditional is AL or we're in an IT block, we really want t2B.
7386 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7387 Inst.setOpcode(ARM::t2B);
7392 // If the conditional is AL, we really want tB.
7393 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7394 Inst.setOpcode(ARM::tB);
7399 // If the register list contains any high registers, or if the writeback
7400 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7401 // instead if we're in Thumb2. Otherwise, this should have generated
7402 // an error in validateInstruction().
7403 unsigned Rn = Inst.getOperand(0).getReg();
7404 bool hasWritebackToken =
7405 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7406 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7407 bool listContainsBase;
7408 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7409 (!listContainsBase && !hasWritebackToken) ||
7410 (listContainsBase && hasWritebackToken)) {
7411 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7412 assert (isThumbTwo());
7413 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7414 // If we're switching to the updating version, we need to insert
7415 // the writeback tied operand.
7416 if (hasWritebackToken)
7417 Inst.insert(Inst.begin(),
7418 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7423 case ARM::tSTMIA_UPD: {
7424 // If the register list contains any high registers, we need to use
7425 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7426 // should have generated an error in validateInstruction().
7427 unsigned Rn = Inst.getOperand(0).getReg();
7428 bool listContainsBase;
7429 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7430 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7431 assert (isThumbTwo());
7432 Inst.setOpcode(ARM::t2STMIA_UPD);
7438 bool listContainsBase;
7439 // If the register list contains any high registers, we need to use
7440 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7441 // should have generated an error in validateInstruction().
7442 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7444 assert (isThumbTwo());
7445 Inst.setOpcode(ARM::t2LDMIA_UPD);
7446 // Add the base register and writeback operands.
7447 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7448 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7452 bool listContainsBase;
7453 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7455 assert (isThumbTwo());
7456 Inst.setOpcode(ARM::t2STMDB_UPD);
7457 // Add the base register and writeback operands.
7458 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7459 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7463 // If we can use the 16-bit encoding and the user didn't explicitly
7464 // request the 32-bit variant, transform it here.
7465 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7466 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7467 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7468 Inst.getOperand(4).getReg() == ARM::CPSR) ||
7469 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7470 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7471 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7472 // The operands aren't in the same order for tMOVi8...
7474 TmpInst.setOpcode(ARM::tMOVi8);
7475 TmpInst.addOperand(Inst.getOperand(0));
7476 TmpInst.addOperand(Inst.getOperand(4));
7477 TmpInst.addOperand(Inst.getOperand(1));
7478 TmpInst.addOperand(Inst.getOperand(2));
7479 TmpInst.addOperand(Inst.getOperand(3));
7486 // If we can use the 16-bit encoding and the user didn't explicitly
7487 // request the 32-bit variant, transform it here.
7488 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7489 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7490 Inst.getOperand(2).getImm() == ARMCC::AL &&
7491 Inst.getOperand(4).getReg() == ARM::CPSR &&
7492 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7493 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7494 // The operands aren't the same for tMOV[S]r... (no cc_out)
7496 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7497 TmpInst.addOperand(Inst.getOperand(0));
7498 TmpInst.addOperand(Inst.getOperand(1));
7499 TmpInst.addOperand(Inst.getOperand(2));
7500 TmpInst.addOperand(Inst.getOperand(3));
7510 // If we can use the 16-bit encoding and the user didn't explicitly
7511 // request the 32-bit variant, transform it here.
7512 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7513 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7514 Inst.getOperand(2).getImm() == 0 &&
7515 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7516 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7518 switch (Inst.getOpcode()) {
7519 default: llvm_unreachable("Illegal opcode!");
7520 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7521 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7522 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7523 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7525 // The operands aren't the same for thumb1 (no rotate operand).
7527 TmpInst.setOpcode(NewOpc);
7528 TmpInst.addOperand(Inst.getOperand(0));
7529 TmpInst.addOperand(Inst.getOperand(1));
7530 TmpInst.addOperand(Inst.getOperand(3));
7531 TmpInst.addOperand(Inst.getOperand(4));
7538 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7539 // rrx shifts and asr/lsr of #32 is encoded as 0
7540 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7542 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7543 // Shifting by zero is accepted as a vanilla 'MOVr'
7545 TmpInst.setOpcode(ARM::MOVr);
7546 TmpInst.addOperand(Inst.getOperand(0));
7547 TmpInst.addOperand(Inst.getOperand(1));
7548 TmpInst.addOperand(Inst.getOperand(3));
7549 TmpInst.addOperand(Inst.getOperand(4));
7550 TmpInst.addOperand(Inst.getOperand(5));
7563 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7564 if (SOpc == ARM_AM::rrx) return false;
7565 switch (Inst.getOpcode()) {
7566 default: llvm_unreachable("unexpected opcode!");
7567 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7568 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7569 case ARM::EORrsi: newOpc = ARM::EORrr; break;
7570 case ARM::BICrsi: newOpc = ARM::BICrr; break;
7571 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7572 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7574 // If the shift is by zero, use the non-shifted instruction definition.
7575 // The exception is for right shifts, where 0 == 32
7576 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7577 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7579 TmpInst.setOpcode(newOpc);
7580 TmpInst.addOperand(Inst.getOperand(0));
7581 TmpInst.addOperand(Inst.getOperand(1));
7582 TmpInst.addOperand(Inst.getOperand(2));
7583 TmpInst.addOperand(Inst.getOperand(4));
7584 TmpInst.addOperand(Inst.getOperand(5));
7585 TmpInst.addOperand(Inst.getOperand(6));
7593 // The mask bits for all but the first condition are represented as
7594 // the low bit of the condition code value implies 't'. We currently
7595 // always have 1 implies 't', so XOR toggle the bits if the low bit
7596 // of the condition code is zero.
7597 MCOperand &MO = Inst.getOperand(1);
7598 unsigned Mask = MO.getImm();
7599 unsigned OrigMask = Mask;
7600 unsigned TZ = countTrailingZeros(Mask);
7601 if ((Inst.getOperand(0).getImm() & 1) == 0) {
7602 assert(Mask && TZ <= 3 && "illegal IT mask value!");
7603 Mask ^= (0xE << TZ) & 0xF;
7607 // Set up the IT block state according to the IT instruction we just
7609 assert(!inITBlock() && "nested IT blocks?!");
7610 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7611 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7612 ITState.CurPosition = 0;
7613 ITState.FirstCond = true;
7623 // Assemblers should use the narrow encodings of these instructions when permissible.
7624 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7625 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7626 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7627 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7628 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7629 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7630 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7632 switch (Inst.getOpcode()) {
7633 default: llvm_unreachable("unexpected opcode");
7634 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7635 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7636 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7637 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7638 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7639 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7642 TmpInst.setOpcode(NewOpc);
7643 TmpInst.addOperand(Inst.getOperand(0));
7644 TmpInst.addOperand(Inst.getOperand(5));
7645 TmpInst.addOperand(Inst.getOperand(1));
7646 TmpInst.addOperand(Inst.getOperand(2));
7647 TmpInst.addOperand(Inst.getOperand(3));
7648 TmpInst.addOperand(Inst.getOperand(4));
7659 // Assemblers should use the narrow encodings of these instructions when permissible.
7660 // These instructions are special in that they are commutable, so shorter encodings
7661 // are available more often.
7662 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7663 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7664 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7665 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7666 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7667 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7668 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7669 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7671 switch (Inst.getOpcode()) {
7672 default: llvm_unreachable("unexpected opcode");
7673 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7674 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7675 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7676 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7679 TmpInst.setOpcode(NewOpc);
7680 TmpInst.addOperand(Inst.getOperand(0));
7681 TmpInst.addOperand(Inst.getOperand(5));
7682 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7683 TmpInst.addOperand(Inst.getOperand(1));
7684 TmpInst.addOperand(Inst.getOperand(2));
7686 TmpInst.addOperand(Inst.getOperand(2));
7687 TmpInst.addOperand(Inst.getOperand(1));
7689 TmpInst.addOperand(Inst.getOperand(3));
7690 TmpInst.addOperand(Inst.getOperand(4));
7700 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7701 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7702 // suffix depending on whether they're in an IT block or not.
7703 unsigned Opc = Inst.getOpcode();
7704 const MCInstrDesc &MCID = MII.get(Opc);
7705 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7706 assert(MCID.hasOptionalDef() &&
7707 "optionally flag setting instruction missing optional def operand");
7708 assert(MCID.NumOperands == Inst.getNumOperands() &&
7709 "operand count mismatch!");
7710 // Find the optional-def operand (cc_out).
7713 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7716 // If we're parsing Thumb1, reject it completely.
7717 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7718 return Match_MnemonicFail;
7719 // If we're parsing Thumb2, which form is legal depends on whether we're
7721 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7723 return Match_RequiresITBlock;
7724 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7726 return Match_RequiresNotITBlock;
7728 // Some high-register supporting Thumb1 encodings only allow both registers
7729 // to be from r0-r7 when in Thumb2.
7730 else if (Opc == ARM::tADDhirr && isThumbOne() &&
7731 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7732 isARMLowRegister(Inst.getOperand(2).getReg()))
7733 return Match_RequiresThumb2;
7734 // Others only require ARMv6 or later.
7735 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7736 isARMLowRegister(Inst.getOperand(0).getReg()) &&
7737 isARMLowRegister(Inst.getOperand(1).getReg()))
7738 return Match_RequiresV6;
7739 return Match_Success;
7742 static const char *getSubtargetFeatureName(unsigned Val);
7744 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
7745 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
7746 MCStreamer &Out, unsigned &ErrorInfo,
7747 bool MatchingInlineAsm) {
7749 unsigned MatchResult;
7751 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
7753 switch (MatchResult) {
7756 // Context sensitive operand constraints aren't handled by the matcher,
7757 // so check them here.
7758 if (validateInstruction(Inst, Operands)) {
7759 // Still progress the IT block, otherwise one wrong condition causes
7760 // nasty cascading errors.
7761 forwardITPosition();
7765 { // processInstruction() updates inITBlock state, we need to save it away
7766 bool wasInITBlock = inITBlock();
7768 // Some instructions need post-processing to, for example, tweak which
7769 // encoding is selected. Loop on it while changes happen so the
7770 // individual transformations can chain off each other. E.g.,
7771 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
7772 while (processInstruction(Inst, Operands))
7775 // Only after the instruction is fully processed, we can validate it
7776 if (wasInITBlock && hasV8Ops() && isThumb() &&
7777 !isV8EligibleForIT(&Inst, 2)) {
7778 Warning(IDLoc, "deprecated instruction in IT block");
7782 // Only move forward at the very end so that everything in validate
7783 // and process gets a consistent answer about whether we're in an IT
7785 forwardITPosition();
7787 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7788 // doesn't actually encode.
7789 if (Inst.getOpcode() == ARM::ITasm)
7793 Out.EmitInstruction(Inst);
7795 case Match_MissingFeature: {
7796 assert(ErrorInfo && "Unknown missing feature!");
7797 // Special case the error message for the very common case where only
7798 // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
7799 std::string Msg = "instruction requires:";
7801 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
7802 if (ErrorInfo & Mask) {
7804 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
7808 return Error(IDLoc, Msg);
7810 case Match_InvalidOperand: {
7811 SMLoc ErrorLoc = IDLoc;
7812 if (ErrorInfo != ~0U) {
7813 if (ErrorInfo >= Operands.size())
7814 return Error(IDLoc, "too few operands for instruction");
7816 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7817 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7820 return Error(ErrorLoc, "invalid operand for instruction");
7822 case Match_MnemonicFail:
7823 return Error(IDLoc, "invalid instruction",
7824 ((ARMOperand*)Operands[0])->getLocRange());
7825 case Match_RequiresNotITBlock:
7826 return Error(IDLoc, "flag setting instruction only valid outside IT block");
7827 case Match_RequiresITBlock:
7828 return Error(IDLoc, "instruction only valid inside IT block");
7829 case Match_RequiresV6:
7830 return Error(IDLoc, "instruction variant requires ARMv6 or later");
7831 case Match_RequiresThumb2:
7832 return Error(IDLoc, "instruction variant requires Thumb2");
7833 case Match_ImmRange0_15: {
7834 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7835 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7836 return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
7838 case Match_ImmRange0_239: {
7839 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7840 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7841 return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
7845 llvm_unreachable("Implement any new match types added!");
7848 /// parseDirective parses the arm specific directives
7849 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
7850 StringRef IDVal = DirectiveID.getIdentifier();
7851 if (IDVal == ".word")
7852 return parseDirectiveWord(4, DirectiveID.getLoc());
7853 else if (IDVal == ".thumb")
7854 return parseDirectiveThumb(DirectiveID.getLoc());
7855 else if (IDVal == ".arm")
7856 return parseDirectiveARM(DirectiveID.getLoc());
7857 else if (IDVal == ".thumb_func")
7858 return parseDirectiveThumbFunc(DirectiveID.getLoc());
7859 else if (IDVal == ".code")
7860 return parseDirectiveCode(DirectiveID.getLoc());
7861 else if (IDVal == ".syntax")
7862 return parseDirectiveSyntax(DirectiveID.getLoc());
7863 else if (IDVal == ".unreq")
7864 return parseDirectiveUnreq(DirectiveID.getLoc());
7865 else if (IDVal == ".arch")
7866 return parseDirectiveArch(DirectiveID.getLoc());
7867 else if (IDVal == ".eabi_attribute")
7868 return parseDirectiveEabiAttr(DirectiveID.getLoc());
7869 else if (IDVal == ".cpu")
7870 return parseDirectiveCPU(DirectiveID.getLoc());
7871 else if (IDVal == ".fpu")
7872 return parseDirectiveFPU(DirectiveID.getLoc());
7873 else if (IDVal == ".fnstart")
7874 return parseDirectiveFnStart(DirectiveID.getLoc());
7875 else if (IDVal == ".fnend")
7876 return parseDirectiveFnEnd(DirectiveID.getLoc());
7877 else if (IDVal == ".cantunwind")
7878 return parseDirectiveCantUnwind(DirectiveID.getLoc());
7879 else if (IDVal == ".personality")
7880 return parseDirectivePersonality(DirectiveID.getLoc());
7881 else if (IDVal == ".handlerdata")
7882 return parseDirectiveHandlerData(DirectiveID.getLoc());
7883 else if (IDVal == ".setfp")
7884 return parseDirectiveSetFP(DirectiveID.getLoc());
7885 else if (IDVal == ".pad")
7886 return parseDirectivePad(DirectiveID.getLoc());
7887 else if (IDVal == ".save")
7888 return parseDirectiveRegSave(DirectiveID.getLoc(), false);
7889 else if (IDVal == ".vsave")
7890 return parseDirectiveRegSave(DirectiveID.getLoc(), true);
7891 else if (IDVal == ".inst")
7892 return parseDirectiveInst(DirectiveID.getLoc());
7893 else if (IDVal == ".inst.n")
7894 return parseDirectiveInst(DirectiveID.getLoc(), 'n');
7895 else if (IDVal == ".inst.w")
7896 return parseDirectiveInst(DirectiveID.getLoc(), 'w');
7900 /// parseDirectiveWord
7901 /// ::= .word [ expression (, expression)* ]
7902 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
7903 if (getLexer().isNot(AsmToken::EndOfStatement)) {
7905 const MCExpr *Value;
7906 if (getParser().parseExpression(Value))
7909 getParser().getStreamer().EmitValue(Value, Size);
7911 if (getLexer().is(AsmToken::EndOfStatement))
7914 // FIXME: Improve diagnostic.
7915 if (getLexer().isNot(AsmToken::Comma))
7916 return Error(L, "unexpected token in directive");
7925 /// parseDirectiveThumb
7927 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
7928 if (getLexer().isNot(AsmToken::EndOfStatement))
7929 return Error(L, "unexpected token in directive");
7933 return Error(L, "target does not support Thumb mode");
7937 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7941 /// parseDirectiveARM
7943 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
7944 if (getLexer().isNot(AsmToken::EndOfStatement))
7945 return Error(L, "unexpected token in directive");
7949 return Error(L, "target does not support ARM mode");
7953 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7957 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
7958 if (NextSymbolIsThumb) {
7959 getParser().getStreamer().EmitThumbFunc(Symbol);
7960 NextSymbolIsThumb = false;
7964 /// parseDirectiveThumbFunc
7965 /// ::= .thumbfunc symbol_name
7966 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
7967 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
7968 bool isMachO = MAI->hasSubsectionsViaSymbols();
7970 // Darwin asm has (optionally) function name after .thumb_func direction
7973 const AsmToken &Tok = Parser.getTok();
7974 if (Tok.isNot(AsmToken::EndOfStatement)) {
7975 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
7976 return Error(L, "unexpected token in .thumb_func directive");
7978 getParser().getContext().GetOrCreateSymbol(Tok.getIdentifier());
7979 getParser().getStreamer().EmitThumbFunc(Func);
7980 Parser.Lex(); // Consume the identifier token.
7985 if (getLexer().isNot(AsmToken::EndOfStatement))
7986 return Error(L, "unexpected token in directive");
7988 NextSymbolIsThumb = true;
7993 /// parseDirectiveSyntax
7994 /// ::= .syntax unified | divided
7995 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
7996 const AsmToken &Tok = Parser.getTok();
7997 if (Tok.isNot(AsmToken::Identifier))
7998 return Error(L, "unexpected token in .syntax directive");
7999 StringRef Mode = Tok.getString();
8000 if (Mode == "unified" || Mode == "UNIFIED")
8002 else if (Mode == "divided" || Mode == "DIVIDED")
8003 return Error(L, "'.syntax divided' arm asssembly not supported");
8005 return Error(L, "unrecognized syntax mode in .syntax directive");
8007 if (getLexer().isNot(AsmToken::EndOfStatement))
8008 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
8011 // TODO tell the MC streamer the mode
8012 // getParser().getStreamer().Emit???();
8016 /// parseDirectiveCode
8017 /// ::= .code 16 | 32
8018 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
8019 const AsmToken &Tok = Parser.getTok();
8020 if (Tok.isNot(AsmToken::Integer))
8021 return Error(L, "unexpected token in .code directive");
8022 int64_t Val = Parser.getTok().getIntVal();
8028 return Error(L, "invalid operand to .code directive");
8030 if (getLexer().isNot(AsmToken::EndOfStatement))
8031 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
8036 return Error(L, "target does not support Thumb mode");
8040 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8043 return Error(L, "target does not support ARM mode");
8047 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8053 /// parseDirectiveReq
8054 /// ::= name .req registername
8055 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
8056 Parser.Lex(); // Eat the '.req' token.
8058 SMLoc SRegLoc, ERegLoc;
8059 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
8060 Parser.eatToEndOfStatement();
8061 return Error(SRegLoc, "register name expected");
8064 // Shouldn't be anything else.
8065 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
8066 Parser.eatToEndOfStatement();
8067 return Error(Parser.getTok().getLoc(),
8068 "unexpected input in .req directive.");
8071 Parser.Lex(); // Consume the EndOfStatement
8073 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg)
8074 return Error(SRegLoc, "redefinition of '" + Name +
8075 "' does not match original.");
8080 /// parseDirectiveUneq
8081 /// ::= .unreq registername
8082 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
8083 if (Parser.getTok().isNot(AsmToken::Identifier)) {
8084 Parser.eatToEndOfStatement();
8085 return Error(L, "unexpected input in .unreq directive.");
8087 RegisterReqs.erase(Parser.getTok().getIdentifier());
8088 Parser.Lex(); // Eat the identifier.
8092 /// parseDirectiveArch
8094 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
8095 StringRef Arch = getParser().parseStringToEndOfStatement().trim();
8097 unsigned ID = StringSwitch<unsigned>(Arch)
8098 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
8099 .Case(NAME, ARM::ID)
8100 #include "MCTargetDesc/ARMArchName.def"
8101 .Default(ARM::INVALID_ARCH);
8103 if (ID == ARM::INVALID_ARCH)
8104 return Error(L, "Unknown arch name");
8106 getTargetStreamer().emitArch(ID);
8110 /// parseDirectiveEabiAttr
8111 /// ::= .eabi_attribute int, int
8112 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
8113 if (Parser.getTok().isNot(AsmToken::Integer))
8114 return Error(L, "integer expected");
8115 int64_t Tag = Parser.getTok().getIntVal();
8116 Parser.Lex(); // eat tag integer
8118 if (Parser.getTok().isNot(AsmToken::Comma))
8119 return Error(L, "comma expected");
8120 Parser.Lex(); // skip comma
8122 L = Parser.getTok().getLoc();
8123 if (Parser.getTok().isNot(AsmToken::Integer))
8124 return Error(L, "integer expected");
8125 int64_t Value = Parser.getTok().getIntVal();
8126 Parser.Lex(); // eat value integer
8128 getTargetStreamer().emitAttribute(Tag, Value);
8132 /// parseDirectiveCPU
8134 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
8135 StringRef CPU = getParser().parseStringToEndOfStatement().trim();
8136 getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
8140 /// parseDirectiveFPU
8142 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
8143 StringRef FPU = getParser().parseStringToEndOfStatement().trim();
8145 unsigned ID = StringSwitch<unsigned>(FPU)
8146 #define ARM_FPU_NAME(NAME, ID) .Case(NAME, ARM::ID)
8147 #include "ARMFPUName.def"
8148 .Default(ARM::INVALID_FPU);
8150 if (ID == ARM::INVALID_FPU)
8151 return Error(L, "Unknown FPU name");
8153 getTargetStreamer().emitFPU(ID);
8157 /// parseDirectiveFnStart
8159 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
8160 if (FnStartLoc.isValid()) {
8161 Error(L, ".fnstart starts before the end of previous one");
8162 Error(FnStartLoc, "previous .fnstart starts here");
8167 getTargetStreamer().emitFnStart();
8171 /// parseDirectiveFnEnd
8173 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
8174 // Check the ordering of unwind directives
8175 if (!FnStartLoc.isValid())
8176 return Error(L, ".fnstart must precede .fnend directive");
8178 // Reset the unwind directives parser state
8179 resetUnwindDirectiveParserState();
8180 getTargetStreamer().emitFnEnd();
8184 /// parseDirectiveCantUnwind
8186 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
8187 // Check the ordering of unwind directives
8189 if (!FnStartLoc.isValid())
8190 return Error(L, ".fnstart must precede .cantunwind directive");
8191 if (HandlerDataLoc.isValid()) {
8192 Error(L, ".cantunwind can't be used with .handlerdata directive");
8193 Error(HandlerDataLoc, ".handlerdata was specified here");
8196 if (PersonalityLoc.isValid()) {
8197 Error(L, ".cantunwind can't be used with .personality directive");
8198 Error(PersonalityLoc, ".personality was specified here");
8202 getTargetStreamer().emitCantUnwind();
8206 /// parseDirectivePersonality
8207 /// ::= .personality name
8208 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
8209 // Check the ordering of unwind directives
8211 if (!FnStartLoc.isValid())
8212 return Error(L, ".fnstart must precede .personality directive");
8213 if (CantUnwindLoc.isValid()) {
8214 Error(L, ".personality can't be used with .cantunwind directive");
8215 Error(CantUnwindLoc, ".cantunwind was specified here");
8218 if (HandlerDataLoc.isValid()) {
8219 Error(L, ".personality must precede .handlerdata directive");
8220 Error(HandlerDataLoc, ".handlerdata was specified here");
8224 // Parse the name of the personality routine
8225 if (Parser.getTok().isNot(AsmToken::Identifier)) {
8226 Parser.eatToEndOfStatement();
8227 return Error(L, "unexpected input in .personality directive.");
8229 StringRef Name(Parser.getTok().getIdentifier());
8232 MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
8233 getTargetStreamer().emitPersonality(PR);
8237 /// parseDirectiveHandlerData
8238 /// ::= .handlerdata
8239 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
8240 // Check the ordering of unwind directives
8242 if (!FnStartLoc.isValid())
8243 return Error(L, ".fnstart must precede .personality directive");
8244 if (CantUnwindLoc.isValid()) {
8245 Error(L, ".handlerdata can't be used with .cantunwind directive");
8246 Error(CantUnwindLoc, ".cantunwind was specified here");
8250 getTargetStreamer().emitHandlerData();
8254 /// parseDirectiveSetFP
8255 /// ::= .setfp fpreg, spreg [, offset]
8256 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
8257 // Check the ordering of unwind directives
8258 if (!FnStartLoc.isValid())
8259 return Error(L, ".fnstart must precede .setfp directive");
8260 if (HandlerDataLoc.isValid())
8261 return Error(L, ".setfp must precede .handlerdata directive");
8264 SMLoc NewFPRegLoc = Parser.getTok().getLoc();
8265 int NewFPReg = tryParseRegister();
8267 return Error(NewFPRegLoc, "frame pointer register expected");
8270 if (!Parser.getTok().is(AsmToken::Comma))
8271 return Error(Parser.getTok().getLoc(), "comma expected");
8272 Parser.Lex(); // skip comma
8275 SMLoc NewSPRegLoc = Parser.getTok().getLoc();
8276 int NewSPReg = tryParseRegister();
8278 return Error(NewSPRegLoc, "stack pointer register expected");
8280 if (NewSPReg != ARM::SP && NewSPReg != FPReg)
8281 return Error(NewSPRegLoc,
8282 "register should be either $sp or the latest fp register");
8284 // Update the frame pointer register
8289 if (Parser.getTok().is(AsmToken::Comma)) {
8290 Parser.Lex(); // skip comma
8292 if (Parser.getTok().isNot(AsmToken::Hash) &&
8293 Parser.getTok().isNot(AsmToken::Dollar)) {
8294 return Error(Parser.getTok().getLoc(), "'#' expected");
8296 Parser.Lex(); // skip hash token.
8298 const MCExpr *OffsetExpr;
8299 SMLoc ExLoc = Parser.getTok().getLoc();
8301 if (getParser().parseExpression(OffsetExpr, EndLoc))
8302 return Error(ExLoc, "malformed setfp offset");
8303 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8305 return Error(ExLoc, "setfp offset must be an immediate");
8307 Offset = CE->getValue();
8310 getTargetStreamer().emitSetFP(static_cast<unsigned>(NewFPReg),
8311 static_cast<unsigned>(NewSPReg), Offset);
8317 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
8318 // Check the ordering of unwind directives
8319 if (!FnStartLoc.isValid())
8320 return Error(L, ".fnstart must precede .pad directive");
8321 if (HandlerDataLoc.isValid())
8322 return Error(L, ".pad must precede .handlerdata directive");
8325 if (Parser.getTok().isNot(AsmToken::Hash) &&
8326 Parser.getTok().isNot(AsmToken::Dollar)) {
8327 return Error(Parser.getTok().getLoc(), "'#' expected");
8329 Parser.Lex(); // skip hash token.
8331 const MCExpr *OffsetExpr;
8332 SMLoc ExLoc = Parser.getTok().getLoc();
8334 if (getParser().parseExpression(OffsetExpr, EndLoc))
8335 return Error(ExLoc, "malformed pad offset");
8336 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8338 return Error(ExLoc, "pad offset must be an immediate");
8340 getTargetStreamer().emitPad(CE->getValue());
8344 /// parseDirectiveRegSave
8345 /// ::= .save { registers }
8346 /// ::= .vsave { registers }
8347 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
8348 // Check the ordering of unwind directives
8349 if (!FnStartLoc.isValid())
8350 return Error(L, ".fnstart must precede .save or .vsave directives");
8351 if (HandlerDataLoc.isValid())
8352 return Error(L, ".save or .vsave must precede .handlerdata directive");
8354 // RAII object to make sure parsed operands are deleted.
8355 struct CleanupObject {
8356 SmallVector<MCParsedAsmOperand *, 1> Operands;
8358 for (unsigned I = 0, E = Operands.size(); I != E; ++I)
8363 // Parse the register list
8364 if (parseRegisterList(CO.Operands))
8366 ARMOperand *Op = (ARMOperand*)CO.Operands[0];
8367 if (!IsVector && !Op->isRegList())
8368 return Error(L, ".save expects GPR registers");
8369 if (IsVector && !Op->isDPRRegList())
8370 return Error(L, ".vsave expects DPR registers");
8372 getTargetStreamer().emitRegSave(Op->getRegList(), IsVector);
8376 /// parseDirectiveInst
8377 /// ::= .inst opcode [, ...]
8378 /// ::= .inst.n opcode [, ...]
8379 /// ::= .inst.w opcode [, ...]
8380 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
8392 Parser.eatToEndOfStatement();
8393 return Error(Loc, "cannot determine Thumb instruction size, "
8394 "use inst.n/inst.w instead");
8398 Parser.eatToEndOfStatement();
8399 return Error(Loc, "width suffixes are invalid in ARM mode");
8404 if (getLexer().is(AsmToken::EndOfStatement)) {
8405 Parser.eatToEndOfStatement();
8406 return Error(Loc, "expected expression following directive");
8412 if (getParser().parseExpression(Expr))
8413 return Error(Loc, "expected expression");
8415 const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
8417 return Error(Loc, "expected constant expression");
8421 if (Value->getValue() > 0xffff)
8422 return Error(Loc, "inst.n operand is too big, use inst.w instead");
8425 if (Value->getValue() > 0xffffffff)
8427 StringRef(Suffix ? "inst.w" : "inst") + " operand is too big");
8430 llvm_unreachable("only supported widths are 2 and 4");
8433 getTargetStreamer().emitInst(Value->getValue(), Suffix);
8435 if (getLexer().is(AsmToken::EndOfStatement))
8438 if (getLexer().isNot(AsmToken::Comma))
8439 return Error(Loc, "unexpected token in directive");
8448 /// Force static initialization.
8449 extern "C" void LLVMInitializeARMAsmParser() {
8450 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
8451 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
8454 #define GET_REGISTER_MATCHER
8455 #define GET_SUBTARGET_FEATURE_NAME
8456 #define GET_MATCHER_IMPLEMENTATION
8457 #include "ARMGenAsmMatcher.inc"
8459 // Define this matcher function after the auto-generated include so we
8460 // have the match class enum definitions.
8461 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
8463 ARMOperand *Op = static_cast<ARMOperand*>(AsmOp);
8464 // If the kind is a token for a literal immediate, check if our asm
8465 // operand matches. This is for InstAliases which have a fixed-value
8466 // immediate in the syntax.
8467 if (Kind == MCK__35_0 && Op->isImm()) {
8468 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
8470 return Match_InvalidOperand;
8471 if (CE->getValue() == 0)
8472 return Match_Success;
8474 return Match_InvalidOperand;
8477 void ARMAsmParser::finishParse() {
8478 // Dump contents of assembler constant pools.
8479 MCStreamer &Streamer = getParser().getStreamer();
8480 for (ConstantPoolMapTy::iterator CPI = ConstantPools.begin(),
8481 CPE = ConstantPools.end();
8482 CPI != CPE; ++CPI) {
8483 const MCSection *Section = CPI->first;
8484 ConstantPool &CP = CPI->second;
8486 // Dump assembler constant pools at the end of the section.
8487 Streamer.SwitchSection(Section);
8488 CP.emitEntries(Streamer);