1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMAddressingModes.h"
12 #include "ARMSubtarget.h"
13 #include "llvm/MC/MCParser/MCAsmLexer.h"
14 #include "llvm/MC/MCParser/MCAsmParser.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/Target/TargetRegistry.h"
21 #include "llvm/Target/TargetAsmParser.h"
22 #include "llvm/Support/SourceMgr.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/ADT/StringSwitch.h"
26 #include "llvm/ADT/Twine.h"
29 // The shift types for register controlled shifts in arm memory addressing
42 class ARMAsmParser : public TargetAsmParser {
46 MCAsmParser &getParser() const { return Parser; }
47 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
49 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
50 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
52 int TryParseRegister();
53 ARMOperand *TryParseRegisterWithWriteBack();
54 ARMOperand *ParseRegisterList();
55 ARMOperand *ParseMemory();
56 ARMOperand *ParseOperand();
58 bool ParseMemoryOffsetReg(bool &Negative,
59 bool &OffsetRegShifted,
60 enum ShiftType &ShiftType,
61 const MCExpr *&ShiftAmount,
62 const MCExpr *&Offset,
66 bool ParseShift(enum ShiftType &St, const MCExpr *&ShiftAmount, SMLoc &E);
67 bool ParseDirectiveWord(unsigned Size, SMLoc L);
68 bool ParseDirectiveThumb(SMLoc L);
69 bool ParseDirectiveThumbFunc(SMLoc L);
70 bool ParseDirectiveCode(SMLoc L);
71 bool ParseDirectiveSyntax(SMLoc L);
73 bool MatchAndEmitInstruction(SMLoc IDLoc,
74 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
77 /// @name Auto-generated Match Functions
80 #define GET_ASSEMBLER_HEADER
81 #include "ARMGenAsmMatcher.inc"
87 ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
88 : TargetAsmParser(T), Parser(_Parser), TM(_TM) {
89 // Initialize the set of available features.
90 setAvailableFeatures(ComputeAvailableFeatures(
91 &TM.getSubtarget<ARMSubtarget>()));
94 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
95 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
97 virtual bool ParseDirective(AsmToken DirectiveID);
99 } // end anonymous namespace
103 /// ARMOperand - Instances of this class represent a parsed ARM machine
105 class ARMOperand : public MCParsedAsmOperand {
115 SMLoc StartLoc, EndLoc;
119 ARMCC::CondCodes Val;
141 // This is for all forms of ARM address expressions
144 unsigned OffsetRegNum; // used when OffsetIsReg is true
145 const MCExpr *Offset; // used when OffsetIsReg is false
146 const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
147 enum ShiftType ShiftType; // used when OffsetRegShifted is true
148 unsigned OffsetRegShifted : 1; // only used when OffsetIsReg is true
149 unsigned Preindexed : 1;
150 unsigned Postindexed : 1;
151 unsigned OffsetIsReg : 1;
152 unsigned Negative : 1; // only used when OffsetIsReg is true
153 unsigned Writeback : 1;
157 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
159 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
161 StartLoc = o.StartLoc;
185 /// getStartLoc - Get the location of the first token of this operand.
186 SMLoc getStartLoc() const { return StartLoc; }
187 /// getEndLoc - Get the location of the last token of this operand.
188 SMLoc getEndLoc() const { return EndLoc; }
190 ARMCC::CondCodes getCondCode() const {
191 assert(Kind == CondCode && "Invalid access!");
195 StringRef getToken() const {
196 assert(Kind == Token && "Invalid access!");
197 return StringRef(Tok.Data, Tok.Length);
200 unsigned getReg() const {
201 assert(Kind == Register && "Invalid access!");
205 std::pair<unsigned, unsigned> getRegList() const {
206 assert(Kind == RegisterList && "Invalid access!");
207 return std::make_pair(RegList.RegStart, RegList.Number);
210 const MCExpr *getImm() const {
211 assert(Kind == Immediate && "Invalid access!");
215 bool isCondCode() const { return Kind == CondCode; }
216 bool isImm() const { return Kind == Immediate; }
217 bool isReg() const { return Kind == Register; }
218 bool isRegList() const { return Kind == RegisterList; }
219 bool isToken() const { return Kind == Token; }
220 bool isMemory() const { return Kind == Memory; }
222 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
223 // Add as immediates when possible. Null MCExpr = 0.
225 Inst.addOperand(MCOperand::CreateImm(0));
226 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
227 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
229 Inst.addOperand(MCOperand::CreateExpr(Expr));
232 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
233 assert(N == 2 && "Invalid number of operands!");
234 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
235 // FIXME: What belongs here?
236 Inst.addOperand(MCOperand::CreateReg(0));
239 void addRegOperands(MCInst &Inst, unsigned N) const {
240 assert(N == 1 && "Invalid number of operands!");
241 Inst.addOperand(MCOperand::CreateReg(getReg()));
244 void addImmOperands(MCInst &Inst, unsigned N) const {
245 assert(N == 1 && "Invalid number of operands!");
246 addExpr(Inst, getImm());
249 bool isMemMode5() const {
250 if (!isMemory() || Mem.OffsetIsReg || Mem.OffsetRegShifted ||
251 Mem.Writeback || Mem.Negative)
253 // If there is an offset expression, make sure it's valid.
256 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
259 // The offset must be a multiple of 4 in the range 0-1020.
260 int64_t Value = CE->getValue();
261 return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020);
264 void addMemMode5Operands(MCInst &Inst, unsigned N) const {
265 assert(N == 2 && isMemMode5() && "Invalid number of operands!");
267 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
268 assert(!Mem.OffsetIsReg && "Invalid mode 5 operand");
270 // FIXME: #-0 is encoded differently than #0. Does the parser preserve
273 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
274 assert(CE && "Non-constant mode 5 offset operand!");
276 // The MCInst offset operand doesn't include the low two bits (like
277 // the instruction encoding).
278 int64_t Offset = CE->getValue() / 4;
280 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add,
283 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub,
286 Inst.addOperand(MCOperand::CreateImm(0));
290 virtual void dump(raw_ostream &OS) const;
292 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
293 ARMOperand *Op = new ARMOperand(CondCode);
300 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
301 ARMOperand *Op = new ARMOperand(Token);
302 Op->Tok.Data = Str.data();
303 Op->Tok.Length = Str.size();
309 static ARMOperand *CreateReg(unsigned RegNum, bool Writeback, SMLoc S,
311 ARMOperand *Op = new ARMOperand(Register);
312 Op->Reg.RegNum = RegNum;
313 Op->Reg.Writeback = Writeback;
319 static ARMOperand *CreateRegList(unsigned RegStart, unsigned Number,
321 ARMOperand *Op = new ARMOperand(RegisterList);
322 Op->RegList.RegStart = RegStart;
323 Op->RegList.Number = Number;
329 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
330 ARMOperand *Op = new ARMOperand(Immediate);
337 static ARMOperand *CreateMem(unsigned BaseRegNum, bool OffsetIsReg,
338 const MCExpr *Offset, unsigned OffsetRegNum,
339 bool OffsetRegShifted, enum ShiftType ShiftType,
340 const MCExpr *ShiftAmount, bool Preindexed,
341 bool Postindexed, bool Negative, bool Writeback,
343 ARMOperand *Op = new ARMOperand(Memory);
344 Op->Mem.BaseRegNum = BaseRegNum;
345 Op->Mem.OffsetIsReg = OffsetIsReg;
346 Op->Mem.Offset = Offset;
347 Op->Mem.OffsetRegNum = OffsetRegNum;
348 Op->Mem.OffsetRegShifted = OffsetRegShifted;
349 Op->Mem.ShiftType = ShiftType;
350 Op->Mem.ShiftAmount = ShiftAmount;
351 Op->Mem.Preindexed = Preindexed;
352 Op->Mem.Postindexed = Postindexed;
353 Op->Mem.Negative = Negative;
354 Op->Mem.Writeback = Writeback;
362 } // end anonymous namespace.
364 void ARMOperand::dump(raw_ostream &OS) const {
367 OS << ARMCondCodeToString(getCondCode());
376 OS << "<register " << getReg() << ">";
379 OS << "<register_list ";
380 std::pair<unsigned, unsigned> List = getRegList();
381 unsigned RegEnd = List.first + List.second;
383 for (unsigned Idx = List.first; Idx < RegEnd; ) {
385 if (++Idx < RegEnd) OS << ", ";
392 OS << "'" << getToken() << "'";
397 /// @name Auto-generated Match Functions
400 static unsigned MatchRegisterName(StringRef Name);
404 /// Try to parse a register name. The token must be an Identifier when called,
405 /// and if it is a register name the token is eaten and the register number is
406 /// returned. Otherwise return -1.
408 int ARMAsmParser::TryParseRegister() {
409 const AsmToken &Tok = Parser.getTok();
410 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
412 // FIXME: Validate register for the current architecture; we have to do
413 // validation later, so maybe there is no need for this here.
414 unsigned RegNum = MatchRegisterName(Tok.getString());
417 Parser.Lex(); // Eat identifier token.
422 /// Try to parse a register name. The token must be an Identifier when called,
423 /// and if it is a register name the token is eaten and the register number is
424 /// returned. Otherwise return -1.
426 /// TODO this is likely to change to allow different register types and or to
427 /// parse for a specific register type.
428 ARMOperand *ARMAsmParser::TryParseRegisterWithWriteBack() {
429 SMLoc S = Parser.getTok().getLoc();
430 int RegNo = TryParseRegister();
431 if (RegNo == -1) return 0;
433 SMLoc E = Parser.getTok().getLoc();
435 bool Writeback = false;
436 const AsmToken &ExclaimTok = Parser.getTok();
437 if (ExclaimTok.is(AsmToken::Exclaim)) {
438 E = ExclaimTok.getLoc();
440 Parser.Lex(); // Eat exclaim token
443 return ARMOperand::CreateReg(RegNo, Writeback, S, E);
446 /// Parse a register list, return it if successful else return null. The first
447 /// token must be a '{' when called.
448 ARMOperand *ARMAsmParser::ParseRegisterList() {
450 assert(Parser.getTok().is(AsmToken::LCurly) &&
451 "Token is not a Left Curly Brace");
452 S = Parser.getTok().getLoc();
453 Parser.Lex(); // Eat left curly brace token.
455 const AsmToken &RegTok = Parser.getTok();
456 SMLoc RegLoc = RegTok.getLoc();
457 if (RegTok.isNot(AsmToken::Identifier)) {
458 Error(RegLoc, "register expected");
461 int RegNum = TryParseRegister();
463 Error(RegLoc, "register expected");
467 unsigned RegList = 1 << RegNum;
469 int HighRegNum = RegNum;
470 // TODO ranges like "{Rn-Rm}"
471 while (Parser.getTok().is(AsmToken::Comma)) {
472 Parser.Lex(); // Eat comma token.
474 const AsmToken &RegTok = Parser.getTok();
475 SMLoc RegLoc = RegTok.getLoc();
476 if (RegTok.isNot(AsmToken::Identifier)) {
477 Error(RegLoc, "register expected");
480 int RegNum = TryParseRegister();
482 Error(RegLoc, "register expected");
486 if (RegList & (1 << RegNum))
487 Warning(RegLoc, "register duplicated in register list");
488 else if (RegNum <= HighRegNum)
489 Warning(RegLoc, "register not in ascending order in register list");
490 RegList |= 1 << RegNum;
493 const AsmToken &RCurlyTok = Parser.getTok();
494 if (RCurlyTok.isNot(AsmToken::RCurly)) {
495 Error(RCurlyTok.getLoc(), "'}' expected");
498 E = RCurlyTok.getLoc();
499 Parser.Lex(); // Eat left curly brace token.
501 // FIXME: Need to return an operand!
502 Error(E, "FIXME: register list parsing not implemented");
506 /// Parse an arm memory expression, return false if successful else return true
507 /// or an error. The first token must be a '[' when called.
508 /// TODO Only preindexing and postindexing addressing are started, unindexed
509 /// with option, etc are still to do.
510 ARMOperand *ARMAsmParser::ParseMemory() {
512 assert(Parser.getTok().is(AsmToken::LBrac) &&
513 "Token is not a Left Bracket");
514 S = Parser.getTok().getLoc();
515 Parser.Lex(); // Eat left bracket token.
517 const AsmToken &BaseRegTok = Parser.getTok();
518 if (BaseRegTok.isNot(AsmToken::Identifier)) {
519 Error(BaseRegTok.getLoc(), "register expected");
522 int BaseRegNum = TryParseRegister();
523 if (BaseRegNum == -1) {
524 Error(BaseRegTok.getLoc(), "register expected");
528 bool Preindexed = false;
529 bool Postindexed = false;
530 bool OffsetIsReg = false;
531 bool Negative = false;
532 bool Writeback = false;
534 // First look for preindexed address forms, that is after the "[Rn" we now
535 // have to see if the next token is a comma.
536 const AsmToken &Tok = Parser.getTok();
537 if (Tok.is(AsmToken::Comma)) {
539 Parser.Lex(); // Eat comma token.
541 bool OffsetRegShifted;
542 enum ShiftType ShiftType;
543 const MCExpr *ShiftAmount;
544 const MCExpr *Offset;
545 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
546 Offset, OffsetIsReg, OffsetRegNum, E))
548 const AsmToken &RBracTok = Parser.getTok();
549 if (RBracTok.isNot(AsmToken::RBrac)) {
550 Error(RBracTok.getLoc(), "']' expected");
553 E = RBracTok.getLoc();
554 Parser.Lex(); // Eat right bracket token.
556 const AsmToken &ExclaimTok = Parser.getTok();
557 if (ExclaimTok.is(AsmToken::Exclaim)) {
558 E = ExclaimTok.getLoc();
560 Parser.Lex(); // Eat exclaim token
562 return ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
563 OffsetRegShifted, ShiftType, ShiftAmount,
564 Preindexed, Postindexed, Negative, Writeback,
567 // The "[Rn" we have so far was not followed by a comma.
568 else if (Tok.is(AsmToken::RBrac)) {
569 // If there's anything other than the right brace, this is a post indexing
572 Parser.Lex(); // Eat right bracket token.
574 int OffsetRegNum = 0;
575 bool OffsetRegShifted = false;
576 enum ShiftType ShiftType;
577 const MCExpr *ShiftAmount;
578 const MCExpr *Offset = 0;
580 const AsmToken &NextTok = Parser.getTok();
581 if (NextTok.isNot(AsmToken::EndOfStatement)) {
584 if (NextTok.isNot(AsmToken::Comma)) {
585 Error(NextTok.getLoc(), "',' expected");
588 Parser.Lex(); // Eat comma token.
589 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
590 ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
595 return ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
596 OffsetRegShifted, ShiftType, ShiftAmount,
597 Preindexed, Postindexed, Negative, Writeback,
604 /// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
605 /// we will parse the following (were +/- means that a plus or minus is
610 /// we return false on success or an error otherwise.
611 bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
612 bool &OffsetRegShifted,
613 enum ShiftType &ShiftType,
614 const MCExpr *&ShiftAmount,
615 const MCExpr *&Offset,
620 OffsetRegShifted = false;
623 const AsmToken &NextTok = Parser.getTok();
624 E = NextTok.getLoc();
625 if (NextTok.is(AsmToken::Plus))
626 Parser.Lex(); // Eat plus token.
627 else if (NextTok.is(AsmToken::Minus)) {
629 Parser.Lex(); // Eat minus token
631 // See if there is a register following the "[Rn," or "[Rn]," we have so far.
632 const AsmToken &OffsetRegTok = Parser.getTok();
633 if (OffsetRegTok.is(AsmToken::Identifier)) {
634 SMLoc CurLoc = OffsetRegTok.getLoc();
635 OffsetRegNum = TryParseRegister();
636 if (OffsetRegNum != -1) {
642 // If we parsed a register as the offset then there can be a shift after that.
643 if (OffsetRegNum != -1) {
644 // Look for a comma then a shift
645 const AsmToken &Tok = Parser.getTok();
646 if (Tok.is(AsmToken::Comma)) {
647 Parser.Lex(); // Eat comma token.
649 const AsmToken &Tok = Parser.getTok();
650 if (ParseShift(ShiftType, ShiftAmount, E))
651 return Error(Tok.getLoc(), "shift expected");
652 OffsetRegShifted = true;
655 else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
656 // Look for #offset following the "[Rn," or "[Rn],"
657 const AsmToken &HashTok = Parser.getTok();
658 if (HashTok.isNot(AsmToken::Hash))
659 return Error(HashTok.getLoc(), "'#' expected");
661 Parser.Lex(); // Eat hash token.
663 if (getParser().ParseExpression(Offset))
665 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
670 /// ParseShift as one of these two:
671 /// ( lsl | lsr | asr | ror ) , # shift_amount
673 /// and returns true if it parses a shift otherwise it returns false.
674 bool ARMAsmParser::ParseShift(ShiftType &St, const MCExpr *&ShiftAmount,
676 const AsmToken &Tok = Parser.getTok();
677 if (Tok.isNot(AsmToken::Identifier))
679 StringRef ShiftName = Tok.getString();
680 if (ShiftName == "lsl" || ShiftName == "LSL")
682 else if (ShiftName == "lsr" || ShiftName == "LSR")
684 else if (ShiftName == "asr" || ShiftName == "ASR")
686 else if (ShiftName == "ror" || ShiftName == "ROR")
688 else if (ShiftName == "rrx" || ShiftName == "RRX")
692 Parser.Lex(); // Eat shift type token.
698 // Otherwise, there must be a '#' and a shift amount.
699 const AsmToken &HashTok = Parser.getTok();
700 if (HashTok.isNot(AsmToken::Hash))
701 return Error(HashTok.getLoc(), "'#' expected");
702 Parser.Lex(); // Eat hash token.
704 if (getParser().ParseExpression(ShiftAmount))
710 /// Parse a arm instruction operand. For now this parses the operand regardless
712 ARMOperand *ARMAsmParser::ParseOperand() {
714 switch (getLexer().getKind()) {
716 Error(Parser.getTok().getLoc(), "unexpected token in operand");
718 case AsmToken::Identifier:
719 if (ARMOperand *Op = TryParseRegisterWithWriteBack())
722 // This was not a register so parse other operands that start with an
723 // identifier (like labels) as expressions and create them as immediates.
725 S = Parser.getTok().getLoc();
726 if (getParser().ParseExpression(IdVal))
728 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
729 return ARMOperand::CreateImm(IdVal, S, E);
730 case AsmToken::LBrac:
731 return ParseMemory();
732 case AsmToken::LCurly:
733 return ParseRegisterList();
736 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
737 S = Parser.getTok().getLoc();
739 const MCExpr *ImmVal;
740 if (getParser().ParseExpression(ImmVal))
742 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
743 return ARMOperand::CreateImm(ImmVal, S, E);
747 /// Parse an arm instruction mnemonic followed by its operands.
748 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
749 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
750 // Create the leading tokens for the mnemonic, split by '.' characters.
751 size_t Start = 0, Next = Name.find('.');
752 StringRef Head = Name.slice(Start, Next);
754 // Determine the predicate, if any.
756 // FIXME: We need a way to check whether a prefix supports predication,
757 // otherwise we will end up with an ambiguity for instructions that happen to
758 // end with a predicate name.
759 // FIXME: Likewise, some arithmetic instructions have an 's' prefix which
760 // indicates to update the condition codes. Those instructions have an
761 // additional immediate operand which encodes the prefix as reg0 or CPSR.
762 // Just checking for a suffix of 's' definitely creates ambiguities; e.g,
763 // the SMMLS instruction.
764 unsigned CC = StringSwitch<unsigned>(Head.substr(Head.size()-2))
765 .Case("eq", ARMCC::EQ)
766 .Case("ne", ARMCC::NE)
767 .Case("hs", ARMCC::HS)
768 .Case("lo", ARMCC::LO)
769 .Case("mi", ARMCC::MI)
770 .Case("pl", ARMCC::PL)
771 .Case("vs", ARMCC::VS)
772 .Case("vc", ARMCC::VC)
773 .Case("hi", ARMCC::HI)
774 .Case("ls", ARMCC::LS)
775 .Case("ge", ARMCC::GE)
776 .Case("lt", ARMCC::LT)
777 .Case("gt", ARMCC::GT)
778 .Case("le", ARMCC::LE)
779 .Case("al", ARMCC::AL)
783 (CC == ARMCC::LS && (Head == "vmls" || Head == "vnmls"))) {
786 Head = Head.slice(0, Head.size() - 2);
789 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
790 // FIXME: Should only add this operand for predicated instructions
791 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), NameLoc));
793 // Add the remaining tokens in the mnemonic.
794 while (Next != StringRef::npos) {
796 Next = Name.find('.', Start + 1);
797 Head = Name.slice(Start, Next);
799 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
802 // Read the remaining operands.
803 if (getLexer().isNot(AsmToken::EndOfStatement)) {
804 // Read the first operand.
805 if (ARMOperand *Op = ParseOperand())
806 Operands.push_back(Op);
808 Parser.EatToEndOfStatement();
812 while (getLexer().is(AsmToken::Comma)) {
813 Parser.Lex(); // Eat the comma.
815 // Parse and remember the operand.
816 if (ARMOperand *Op = ParseOperand())
817 Operands.push_back(Op);
819 Parser.EatToEndOfStatement();
825 if (getLexer().isNot(AsmToken::EndOfStatement)) {
826 Parser.EatToEndOfStatement();
827 return TokError("unexpected token in argument list");
830 Parser.Lex(); // Consume the EndOfStatement
835 MatchAndEmitInstruction(SMLoc IDLoc,
836 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
840 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo)) {
842 Out.EmitInstruction(Inst);
844 case Match_MissingFeature:
845 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
847 case Match_InvalidOperand: {
848 SMLoc ErrorLoc = IDLoc;
849 if (ErrorInfo != ~0U) {
850 if (ErrorInfo >= Operands.size())
851 return Error(IDLoc, "too few operands for instruction");
853 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
854 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
857 return Error(ErrorLoc, "invalid operand for instruction");
859 case Match_MnemonicFail:
860 return Error(IDLoc, "unrecognized instruction mnemonic");
863 llvm_unreachable("Implement any new match types added!");
867 /// ParseDirective parses the arm specific directives
868 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
869 StringRef IDVal = DirectiveID.getIdentifier();
870 if (IDVal == ".word")
871 return ParseDirectiveWord(4, DirectiveID.getLoc());
872 else if (IDVal == ".thumb")
873 return ParseDirectiveThumb(DirectiveID.getLoc());
874 else if (IDVal == ".thumb_func")
875 return ParseDirectiveThumbFunc(DirectiveID.getLoc());
876 else if (IDVal == ".code")
877 return ParseDirectiveCode(DirectiveID.getLoc());
878 else if (IDVal == ".syntax")
879 return ParseDirectiveSyntax(DirectiveID.getLoc());
883 /// ParseDirectiveWord
884 /// ::= .word [ expression (, expression)* ]
885 bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
886 if (getLexer().isNot(AsmToken::EndOfStatement)) {
889 if (getParser().ParseExpression(Value))
892 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
894 if (getLexer().is(AsmToken::EndOfStatement))
897 // FIXME: Improve diagnostic.
898 if (getLexer().isNot(AsmToken::Comma))
899 return Error(L, "unexpected token in directive");
908 /// ParseDirectiveThumb
910 bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
911 if (getLexer().isNot(AsmToken::EndOfStatement))
912 return Error(L, "unexpected token in directive");
915 // TODO: set thumb mode
916 // TODO: tell the MC streamer the mode
917 // getParser().getStreamer().Emit???();
921 /// ParseDirectiveThumbFunc
922 /// ::= .thumbfunc symbol_name
923 bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
924 const AsmToken &Tok = Parser.getTok();
925 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
926 return Error(L, "unexpected token in .thumb_func directive");
927 StringRef Name = Tok.getString();
928 Parser.Lex(); // Consume the identifier token.
929 if (getLexer().isNot(AsmToken::EndOfStatement))
930 return Error(L, "unexpected token in directive");
933 // Mark symbol as a thumb symbol.
934 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
935 getParser().getStreamer().EmitThumbFunc(Func);
939 /// ParseDirectiveSyntax
940 /// ::= .syntax unified | divided
941 bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
942 const AsmToken &Tok = Parser.getTok();
943 if (Tok.isNot(AsmToken::Identifier))
944 return Error(L, "unexpected token in .syntax directive");
945 StringRef Mode = Tok.getString();
946 if (Mode == "unified" || Mode == "UNIFIED")
948 else if (Mode == "divided" || Mode == "DIVIDED")
951 return Error(L, "unrecognized syntax mode in .syntax directive");
953 if (getLexer().isNot(AsmToken::EndOfStatement))
954 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
957 // TODO tell the MC streamer the mode
958 // getParser().getStreamer().Emit???();
962 /// ParseDirectiveCode
963 /// ::= .code 16 | 32
964 bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
965 const AsmToken &Tok = Parser.getTok();
966 if (Tok.isNot(AsmToken::Integer))
967 return Error(L, "unexpected token in .code directive");
968 int64_t Val = Parser.getTok().getIntVal();
974 return Error(L, "invalid operand to .code directive");
976 if (getLexer().isNot(AsmToken::EndOfStatement))
977 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
981 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
983 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
988 extern "C" void LLVMInitializeARMAsmLexer();
990 /// Force static initialization.
991 extern "C" void LLVMInitializeARMAsmParser() {
992 RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
993 RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
994 LLVMInitializeARMAsmLexer();
997 #define GET_REGISTER_MATCHER
998 #define GET_MATCHER_IMPLEMENTATION
999 #include "ARMGenAsmMatcher.inc"