1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMBaseInfo.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMMCExpr.h"
13 #include "llvm/MC/MCParser/MCAsmLexer.h"
14 #include "llvm/MC/MCParser/MCAsmParser.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCAsmInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/MC/MCTargetAsmParser.h"
24 #include "llvm/Target/TargetRegistry.h"
25 #include "llvm/Support/SourceMgr.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include "llvm/ADT/OwningPtr.h"
28 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/ADT/StringExtras.h"
31 #include "llvm/ADT/StringSwitch.h"
32 #include "llvm/ADT/Twine.h"
40 class ARMAsmParser : public MCTargetAsmParser {
44 MCAsmParser &getParser() const { return Parser; }
45 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
47 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
48 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
50 int tryParseRegister();
51 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
52 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
53 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
54 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
55 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
56 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
57 const MCExpr *applyPrefixToExpr(const MCExpr *E,
58 MCSymbolRefExpr::VariantKind Variant);
61 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
62 unsigned &ShiftAmount);
63 bool parseDirectiveWord(unsigned Size, SMLoc L);
64 bool parseDirectiveThumb(SMLoc L);
65 bool parseDirectiveThumbFunc(SMLoc L);
66 bool parseDirectiveCode(SMLoc L);
67 bool parseDirectiveSyntax(SMLoc L);
69 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
70 bool &CarrySetting, unsigned &ProcessorIMod);
71 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
72 bool &CanAcceptPredicationCode);
74 bool isThumb() const {
75 // FIXME: Can tablegen auto-generate this?
76 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
78 bool isThumbOne() const {
79 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
82 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
83 setAvailableFeatures(FB);
86 /// @name Auto-generated Match Functions
89 #define GET_ASSEMBLER_HEADER
90 #include "ARMGenAsmMatcher.inc"
94 OperandMatchResultTy parseCoprocNumOperand(
95 SmallVectorImpl<MCParsedAsmOperand*>&);
96 OperandMatchResultTy parseCoprocRegOperand(
97 SmallVectorImpl<MCParsedAsmOperand*>&);
98 OperandMatchResultTy parseMemBarrierOptOperand(
99 SmallVectorImpl<MCParsedAsmOperand*>&);
100 OperandMatchResultTy parseProcIFlagsOperand(
101 SmallVectorImpl<MCParsedAsmOperand*>&);
102 OperandMatchResultTy parseMSRMaskOperand(
103 SmallVectorImpl<MCParsedAsmOperand*>&);
104 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
105 StringRef Op, int Low, int High);
106 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
107 return parsePKHImm(O, "lsl", 0, 31);
109 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
110 return parsePKHImm(O, "asr", 1, 32);
112 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
113 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
114 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
115 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
116 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
117 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
119 // Asm Match Converter Methods
120 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
121 const SmallVectorImpl<MCParsedAsmOperand*> &);
122 bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
123 const SmallVectorImpl<MCParsedAsmOperand*> &);
124 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
125 const SmallVectorImpl<MCParsedAsmOperand*> &);
126 bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
127 const SmallVectorImpl<MCParsedAsmOperand*> &);
128 bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
129 const SmallVectorImpl<MCParsedAsmOperand*> &);
130 bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
131 const SmallVectorImpl<MCParsedAsmOperand*> &);
132 bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
133 const SmallVectorImpl<MCParsedAsmOperand*> &);
134 bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
135 const SmallVectorImpl<MCParsedAsmOperand*> &);
136 bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
137 const SmallVectorImpl<MCParsedAsmOperand*> &);
138 bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
139 const SmallVectorImpl<MCParsedAsmOperand*> &);
141 bool validateInstruction(MCInst &Inst,
142 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
143 void processInstruction(MCInst &Inst,
144 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
147 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
148 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
149 MCAsmParserExtension::Initialize(_Parser);
151 // Initialize the set of available features.
152 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
155 // Implementation of the MCTargetAsmParser interface:
156 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
157 bool ParseInstruction(StringRef Name, SMLoc NameLoc,
158 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
159 bool ParseDirective(AsmToken DirectiveID);
161 bool MatchAndEmitInstruction(SMLoc IDLoc,
162 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
165 } // end anonymous namespace
169 /// ARMOperand - Instances of this class represent a parsed ARM machine
171 class ARMOperand : public MCParsedAsmOperand {
195 SMLoc StartLoc, EndLoc;
196 SmallVector<unsigned, 8> Registers;
200 ARMCC::CondCodes Val;
212 ARM_PROC::IFlags Val;
232 /// Combined record for all forms of ARM address expressions.
235 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
237 const MCConstantExpr *OffsetImm; // Offset immediate value
238 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
239 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
240 unsigned ShiftImm; // shift for OffsetReg.
241 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
247 ARM_AM::ShiftOpc ShiftTy;
256 ARM_AM::ShiftOpc ShiftTy;
262 ARM_AM::ShiftOpc ShiftTy;
275 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
277 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
279 StartLoc = o.StartLoc;
293 case DPRRegisterList:
294 case SPRRegisterList:
295 Registers = o.Registers;
310 case PostIndexRegister:
311 PostIdxReg = o.PostIdxReg;
319 case ShifterImmediate:
320 ShifterImm = o.ShifterImm;
322 case ShiftedRegister:
323 RegShiftedReg = o.RegShiftedReg;
325 case ShiftedImmediate:
326 RegShiftedImm = o.RegShiftedImm;
328 case RotateImmediate:
331 case BitfieldDescriptor:
332 Bitfield = o.Bitfield;
337 /// getStartLoc - Get the location of the first token of this operand.
338 SMLoc getStartLoc() const { return StartLoc; }
339 /// getEndLoc - Get the location of the last token of this operand.
340 SMLoc getEndLoc() const { return EndLoc; }
342 ARMCC::CondCodes getCondCode() const {
343 assert(Kind == CondCode && "Invalid access!");
347 unsigned getCoproc() const {
348 assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
352 StringRef getToken() const {
353 assert(Kind == Token && "Invalid access!");
354 return StringRef(Tok.Data, Tok.Length);
357 unsigned getReg() const {
358 assert((Kind == Register || Kind == CCOut) && "Invalid access!");
362 const SmallVectorImpl<unsigned> &getRegList() const {
363 assert((Kind == RegisterList || Kind == DPRRegisterList ||
364 Kind == SPRRegisterList) && "Invalid access!");
368 const MCExpr *getImm() const {
369 assert(Kind == Immediate && "Invalid access!");
373 ARM_MB::MemBOpt getMemBarrierOpt() const {
374 assert(Kind == MemBarrierOpt && "Invalid access!");
378 ARM_PROC::IFlags getProcIFlags() const {
379 assert(Kind == ProcIFlags && "Invalid access!");
383 unsigned getMSRMask() const {
384 assert(Kind == MSRMask && "Invalid access!");
388 bool isCoprocNum() const { return Kind == CoprocNum; }
389 bool isCoprocReg() const { return Kind == CoprocReg; }
390 bool isCondCode() const { return Kind == CondCode; }
391 bool isCCOut() const { return Kind == CCOut; }
392 bool isImm() const { return Kind == Immediate; }
393 bool isImm0_255() const {
394 if (Kind != Immediate)
396 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
397 if (!CE) return false;
398 int64_t Value = CE->getValue();
399 return Value >= 0 && Value < 256;
401 bool isImm0_7() const {
402 if (Kind != Immediate)
404 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
405 if (!CE) return false;
406 int64_t Value = CE->getValue();
407 return Value >= 0 && Value < 8;
409 bool isImm0_15() const {
410 if (Kind != Immediate)
412 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
413 if (!CE) return false;
414 int64_t Value = CE->getValue();
415 return Value >= 0 && Value < 16;
417 bool isImm0_31() const {
418 if (Kind != Immediate)
420 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
421 if (!CE) return false;
422 int64_t Value = CE->getValue();
423 return Value >= 0 && Value < 32;
425 bool isImm1_16() const {
426 if (Kind != Immediate)
428 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
429 if (!CE) return false;
430 int64_t Value = CE->getValue();
431 return Value > 0 && Value < 17;
433 bool isImm1_32() const {
434 if (Kind != Immediate)
436 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
437 if (!CE) return false;
438 int64_t Value = CE->getValue();
439 return Value > 0 && Value < 33;
441 bool isImm0_65535() const {
442 if (Kind != Immediate)
444 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
445 if (!CE) return false;
446 int64_t Value = CE->getValue();
447 return Value >= 0 && Value < 65536;
449 bool isImm0_65535Expr() const {
450 if (Kind != Immediate)
452 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
453 // If it's not a constant expression, it'll generate a fixup and be
455 if (!CE) return true;
456 int64_t Value = CE->getValue();
457 return Value >= 0 && Value < 65536;
459 bool isImm24bit() const {
460 if (Kind != Immediate)
462 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
463 if (!CE) return false;
464 int64_t Value = CE->getValue();
465 return Value >= 0 && Value <= 0xffffff;
467 bool isPKHLSLImm() const {
468 if (Kind != Immediate)
470 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
471 if (!CE) return false;
472 int64_t Value = CE->getValue();
473 return Value >= 0 && Value < 32;
475 bool isPKHASRImm() const {
476 if (Kind != Immediate)
478 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
479 if (!CE) return false;
480 int64_t Value = CE->getValue();
481 return Value > 0 && Value <= 32;
483 bool isARMSOImm() const {
484 if (Kind != Immediate)
486 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
487 if (!CE) return false;
488 int64_t Value = CE->getValue();
489 return ARM_AM::getSOImmVal(Value) != -1;
491 bool isT2SOImm() const {
492 if (Kind != Immediate)
494 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
495 if (!CE) return false;
496 int64_t Value = CE->getValue();
497 return ARM_AM::getT2SOImmVal(Value) != -1;
499 bool isSetEndImm() const {
500 if (Kind != Immediate)
502 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
503 if (!CE) return false;
504 int64_t Value = CE->getValue();
505 return Value == 1 || Value == 0;
507 bool isReg() const { return Kind == Register; }
508 bool isRegList() const { return Kind == RegisterList; }
509 bool isDPRRegList() const { return Kind == DPRRegisterList; }
510 bool isSPRRegList() const { return Kind == SPRRegisterList; }
511 bool isToken() const { return Kind == Token; }
512 bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
513 bool isMemory() const { return Kind == Memory; }
514 bool isShifterImm() const { return Kind == ShifterImmediate; }
515 bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
516 bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
517 bool isRotImm() const { return Kind == RotateImmediate; }
518 bool isBitfield() const { return Kind == BitfieldDescriptor; }
519 bool isPostIdxRegShifted() const { return Kind == PostIndexRegister; }
520 bool isPostIdxReg() const {
521 return Kind == PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
523 bool isMemNoOffset() const {
526 // No offset of any kind.
527 return Mem.OffsetRegNum == 0 && Mem.OffsetImm == 0;
529 bool isAddrMode2() const {
532 // Check for register offset.
533 if (Mem.OffsetRegNum) return true;
534 // Immediate offset in range [-4095, 4095].
535 if (!Mem.OffsetImm) return true;
536 int64_t Val = Mem.OffsetImm->getValue();
537 return Val > -4096 && Val < 4096;
539 bool isAM2OffsetImm() const {
540 if (Kind != Immediate)
542 // Immediate offset in range [-4095, 4095].
543 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
544 if (!CE) return false;
545 int64_t Val = CE->getValue();
546 return Val > -4096 && Val < 4096;
548 bool isAddrMode3() const {
551 // No shifts are legal for AM3.
552 if (Mem.ShiftType != ARM_AM::no_shift) return false;
553 // Check for register offset.
554 if (Mem.OffsetRegNum) return true;
555 // Immediate offset in range [-255, 255].
556 if (!Mem.OffsetImm) return true;
557 int64_t Val = Mem.OffsetImm->getValue();
558 return Val > -256 && Val < 256;
560 bool isAM3Offset() const {
561 if (Kind != Immediate && Kind != PostIndexRegister)
563 if (Kind == PostIndexRegister)
564 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
565 // Immediate offset in range [-255, 255].
566 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
567 if (!CE) return false;
568 int64_t Val = CE->getValue();
569 // Special case, #-0 is INT32_MIN.
570 return (Val > -256 && Val < 256) || Val == INT32_MIN;
572 bool isAddrMode5() const {
575 // Check for register offset.
576 if (Mem.OffsetRegNum) return false;
577 // Immediate offset in range [-1020, 1020] and a multiple of 4.
578 if (!Mem.OffsetImm) return true;
579 int64_t Val = Mem.OffsetImm->getValue();
580 return Val >= -1020 && Val <= 1020 && ((Val & 3) == 0);
582 bool isMemRegOffset() const {
583 if (Kind != Memory || !Mem.OffsetRegNum)
587 bool isMemThumbRR() const {
588 // Thumb reg+reg addressing is simple. Just two registers, a base and
589 // an offset. No shifts, negations or any other complicating factors.
590 if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative ||
591 Mem.ShiftType != ARM_AM::no_shift)
595 bool isMemImm8Offset() const {
596 if (Kind != Memory || Mem.OffsetRegNum != 0)
598 // Immediate offset in range [-255, 255].
599 if (!Mem.OffsetImm) return true;
600 int64_t Val = Mem.OffsetImm->getValue();
601 return Val > -256 && Val < 256;
603 bool isMemImm12Offset() const {
604 // If we have an immediate that's not a constant, treat it as a label
605 // reference needing a fixup. If it is a constant, it's something else
607 if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
610 if (Kind != Memory || Mem.OffsetRegNum != 0)
612 // Immediate offset in range [-4095, 4095].
613 if (!Mem.OffsetImm) return true;
614 int64_t Val = Mem.OffsetImm->getValue();
615 return Val > -4096 && Val < 4096;
617 bool isPostIdxImm8() const {
618 if (Kind != Immediate)
620 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
621 if (!CE) return false;
622 int64_t Val = CE->getValue();
623 return Val > -256 && Val < 256;
626 bool isMSRMask() const { return Kind == MSRMask; }
627 bool isProcIFlags() const { return Kind == ProcIFlags; }
629 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
630 // Add as immediates when possible. Null MCExpr = 0.
632 Inst.addOperand(MCOperand::CreateImm(0));
633 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
634 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
636 Inst.addOperand(MCOperand::CreateExpr(Expr));
639 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
640 assert(N == 2 && "Invalid number of operands!");
641 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
642 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
643 Inst.addOperand(MCOperand::CreateReg(RegNum));
646 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
647 assert(N == 1 && "Invalid number of operands!");
648 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
651 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
652 assert(N == 1 && "Invalid number of operands!");
653 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
656 void addCCOutOperands(MCInst &Inst, unsigned N) const {
657 assert(N == 1 && "Invalid number of operands!");
658 Inst.addOperand(MCOperand::CreateReg(getReg()));
661 void addRegOperands(MCInst &Inst, unsigned N) const {
662 assert(N == 1 && "Invalid number of operands!");
663 Inst.addOperand(MCOperand::CreateReg(getReg()));
666 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
667 assert(N == 3 && "Invalid number of operands!");
668 assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
669 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
670 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
671 Inst.addOperand(MCOperand::CreateImm(
672 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
675 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
676 assert(N == 2 && "Invalid number of operands!");
677 assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
678 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
679 Inst.addOperand(MCOperand::CreateImm(
680 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
684 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
685 assert(N == 1 && "Invalid number of operands!");
686 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
690 void addRegListOperands(MCInst &Inst, unsigned N) const {
691 assert(N == 1 && "Invalid number of operands!");
692 const SmallVectorImpl<unsigned> &RegList = getRegList();
693 for (SmallVectorImpl<unsigned>::const_iterator
694 I = RegList.begin(), E = RegList.end(); I != E; ++I)
695 Inst.addOperand(MCOperand::CreateReg(*I));
698 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
699 addRegListOperands(Inst, N);
702 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
703 addRegListOperands(Inst, N);
706 void addRotImmOperands(MCInst &Inst, unsigned N) const {
707 assert(N == 1 && "Invalid number of operands!");
708 // Encoded as val>>3. The printer handles display as 8, 16, 24.
709 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
712 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
713 assert(N == 1 && "Invalid number of operands!");
714 // Munge the lsb/width into a bitfield mask.
715 unsigned lsb = Bitfield.LSB;
716 unsigned width = Bitfield.Width;
717 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
718 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
719 (32 - (lsb + width)));
720 Inst.addOperand(MCOperand::CreateImm(Mask));
723 void addImmOperands(MCInst &Inst, unsigned N) const {
724 assert(N == 1 && "Invalid number of operands!");
725 addExpr(Inst, getImm());
728 void addImm0_255Operands(MCInst &Inst, unsigned N) const {
729 assert(N == 1 && "Invalid number of operands!");
730 addExpr(Inst, getImm());
733 void addImm0_7Operands(MCInst &Inst, unsigned N) const {
734 assert(N == 1 && "Invalid number of operands!");
735 addExpr(Inst, getImm());
738 void addImm0_15Operands(MCInst &Inst, unsigned N) const {
739 assert(N == 1 && "Invalid number of operands!");
740 addExpr(Inst, getImm());
743 void addImm0_31Operands(MCInst &Inst, unsigned N) const {
744 assert(N == 1 && "Invalid number of operands!");
745 addExpr(Inst, getImm());
748 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
749 assert(N == 1 && "Invalid number of operands!");
750 // The constant encodes as the immediate-1, and we store in the instruction
751 // the bits as encoded, so subtract off one here.
752 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
753 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
756 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
757 assert(N == 1 && "Invalid number of operands!");
758 // The constant encodes as the immediate-1, and we store in the instruction
759 // the bits as encoded, so subtract off one here.
760 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
761 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
764 void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
765 assert(N == 1 && "Invalid number of operands!");
766 addExpr(Inst, getImm());
769 void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
770 assert(N == 1 && "Invalid number of operands!");
771 addExpr(Inst, getImm());
774 void addImm24bitOperands(MCInst &Inst, unsigned N) const {
775 assert(N == 1 && "Invalid number of operands!");
776 addExpr(Inst, getImm());
779 void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
780 assert(N == 1 && "Invalid number of operands!");
781 addExpr(Inst, getImm());
784 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
785 assert(N == 1 && "Invalid number of operands!");
786 // An ASR value of 32 encodes as 0, so that's how we want to add it to
787 // the instruction as well.
788 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
789 int Val = CE->getValue();
790 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
793 void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
794 assert(N == 1 && "Invalid number of operands!");
795 addExpr(Inst, getImm());
798 void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
799 assert(N == 1 && "Invalid number of operands!");
800 addExpr(Inst, getImm());
803 void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
804 assert(N == 1 && "Invalid number of operands!");
805 addExpr(Inst, getImm());
808 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
809 assert(N == 1 && "Invalid number of operands!");
810 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
813 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
814 assert(N == 1 && "Invalid number of operands!");
815 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
818 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
819 assert(N == 3 && "Invalid number of operands!");
820 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
821 if (!Mem.OffsetRegNum) {
822 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
823 // Special case for #-0
824 if (Val == INT32_MIN) Val = 0;
825 if (Val < 0) Val = -Val;
826 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
828 // For register offset, we encode the shift type and negation flag
830 Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
833 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
834 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
835 Inst.addOperand(MCOperand::CreateImm(Val));
838 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
839 assert(N == 2 && "Invalid number of operands!");
840 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
841 assert(CE && "non-constant AM2OffsetImm operand!");
842 int32_t Val = CE->getValue();
843 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
844 // Special case for #-0
845 if (Val == INT32_MIN) Val = 0;
846 if (Val < 0) Val = -Val;
847 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
848 Inst.addOperand(MCOperand::CreateReg(0));
849 Inst.addOperand(MCOperand::CreateImm(Val));
852 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
853 assert(N == 3 && "Invalid number of operands!");
854 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
855 if (!Mem.OffsetRegNum) {
856 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
857 // Special case for #-0
858 if (Val == INT32_MIN) Val = 0;
859 if (Val < 0) Val = -Val;
860 Val = ARM_AM::getAM3Opc(AddSub, Val);
862 // For register offset, we encode the shift type and negation flag
864 Val = ARM_AM::getAM3Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
866 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
867 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
868 Inst.addOperand(MCOperand::CreateImm(Val));
871 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
872 assert(N == 2 && "Invalid number of operands!");
873 if (Kind == PostIndexRegister) {
875 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
876 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
877 Inst.addOperand(MCOperand::CreateImm(Val));
882 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
883 int32_t Val = CE->getValue();
884 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
885 // Special case for #-0
886 if (Val == INT32_MIN) Val = 0;
887 if (Val < 0) Val = -Val;
888 Val = ARM_AM::getAM3Opc(AddSub, Val);
889 Inst.addOperand(MCOperand::CreateReg(0));
890 Inst.addOperand(MCOperand::CreateImm(Val));
893 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
894 assert(N == 2 && "Invalid number of operands!");
895 // The lower two bits are always zero and as such are not encoded.
896 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0;
897 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
898 // Special case for #-0
899 if (Val == INT32_MIN) Val = 0;
900 if (Val < 0) Val = -Val;
901 Val = ARM_AM::getAM5Opc(AddSub, Val);
902 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
903 Inst.addOperand(MCOperand::CreateImm(Val));
906 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
907 assert(N == 2 && "Invalid number of operands!");
908 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
909 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
910 Inst.addOperand(MCOperand::CreateImm(Val));
913 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
914 assert(N == 2 && "Invalid number of operands!");
915 // If this is an immediate, it's a label reference.
916 if (Kind == Immediate) {
917 addExpr(Inst, getImm());
918 Inst.addOperand(MCOperand::CreateImm(0));
922 // Otherwise, it's a normal memory reg+offset.
923 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
924 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
925 Inst.addOperand(MCOperand::CreateImm(Val));
928 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
929 assert(N == 3 && "Invalid number of operands!");
930 unsigned Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
931 Mem.ShiftImm, Mem.ShiftType);
932 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
933 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
934 Inst.addOperand(MCOperand::CreateImm(Val));
937 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
938 assert(N == 2 && "Invalid number of operands!");
939 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
940 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
943 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
944 assert(N == 1 && "Invalid number of operands!");
945 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
946 assert(CE && "non-constant post-idx-imm8 operand!");
947 int Imm = CE->getValue();
948 bool isAdd = Imm >= 0;
949 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
950 Inst.addOperand(MCOperand::CreateImm(Imm));
953 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
954 assert(N == 2 && "Invalid number of operands!");
955 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
956 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
959 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
960 assert(N == 2 && "Invalid number of operands!");
961 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
962 // The sign, shift type, and shift amount are encoded in a single operand
963 // using the AM2 encoding helpers.
964 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
965 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
967 Inst.addOperand(MCOperand::CreateImm(Imm));
970 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
971 assert(N == 1 && "Invalid number of operands!");
972 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
975 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
976 assert(N == 1 && "Invalid number of operands!");
977 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
980 virtual void print(raw_ostream &OS) const;
982 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
983 ARMOperand *Op = new ARMOperand(CondCode);
990 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
991 ARMOperand *Op = new ARMOperand(CoprocNum);
992 Op->Cop.Val = CopVal;
998 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
999 ARMOperand *Op = new ARMOperand(CoprocReg);
1000 Op->Cop.Val = CopVal;
1006 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1007 ARMOperand *Op = new ARMOperand(CCOut);
1008 Op->Reg.RegNum = RegNum;
1014 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1015 ARMOperand *Op = new ARMOperand(Token);
1016 Op->Tok.Data = Str.data();
1017 Op->Tok.Length = Str.size();
1023 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1024 ARMOperand *Op = new ARMOperand(Register);
1025 Op->Reg.RegNum = RegNum;
1031 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1036 ARMOperand *Op = new ARMOperand(ShiftedRegister);
1037 Op->RegShiftedReg.ShiftTy = ShTy;
1038 Op->RegShiftedReg.SrcReg = SrcReg;
1039 Op->RegShiftedReg.ShiftReg = ShiftReg;
1040 Op->RegShiftedReg.ShiftImm = ShiftImm;
1046 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1050 ARMOperand *Op = new ARMOperand(ShiftedImmediate);
1051 Op->RegShiftedImm.ShiftTy = ShTy;
1052 Op->RegShiftedImm.SrcReg = SrcReg;
1053 Op->RegShiftedImm.ShiftImm = ShiftImm;
1059 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1061 ARMOperand *Op = new ARMOperand(ShifterImmediate);
1062 Op->ShifterImm.isASR = isASR;
1063 Op->ShifterImm.Imm = Imm;
1069 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1070 ARMOperand *Op = new ARMOperand(RotateImmediate);
1071 Op->RotImm.Imm = Imm;
1077 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1079 ARMOperand *Op = new ARMOperand(BitfieldDescriptor);
1080 Op->Bitfield.LSB = LSB;
1081 Op->Bitfield.Width = Width;
1088 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1089 SMLoc StartLoc, SMLoc EndLoc) {
1090 KindTy Kind = RegisterList;
1092 if (llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].
1093 contains(Regs.front().first))
1094 Kind = DPRRegisterList;
1095 else if (llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].
1096 contains(Regs.front().first))
1097 Kind = SPRRegisterList;
1099 ARMOperand *Op = new ARMOperand(Kind);
1100 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1101 I = Regs.begin(), E = Regs.end(); I != E; ++I)
1102 Op->Registers.push_back(I->first);
1103 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1104 Op->StartLoc = StartLoc;
1105 Op->EndLoc = EndLoc;
1109 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1110 ARMOperand *Op = new ARMOperand(Immediate);
1117 static ARMOperand *CreateMem(unsigned BaseRegNum,
1118 const MCConstantExpr *OffsetImm,
1119 unsigned OffsetRegNum,
1120 ARM_AM::ShiftOpc ShiftType,
1124 ARMOperand *Op = new ARMOperand(Memory);
1125 Op->Mem.BaseRegNum = BaseRegNum;
1126 Op->Mem.OffsetImm = OffsetImm;
1127 Op->Mem.OffsetRegNum = OffsetRegNum;
1128 Op->Mem.ShiftType = ShiftType;
1129 Op->Mem.ShiftImm = ShiftImm;
1130 Op->Mem.isNegative = isNegative;
1136 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1137 ARM_AM::ShiftOpc ShiftTy,
1140 ARMOperand *Op = new ARMOperand(PostIndexRegister);
1141 Op->PostIdxReg.RegNum = RegNum;
1142 Op->PostIdxReg.isAdd = isAdd;
1143 Op->PostIdxReg.ShiftTy = ShiftTy;
1144 Op->PostIdxReg.ShiftImm = ShiftImm;
1150 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1151 ARMOperand *Op = new ARMOperand(MemBarrierOpt);
1152 Op->MBOpt.Val = Opt;
1158 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1159 ARMOperand *Op = new ARMOperand(ProcIFlags);
1160 Op->IFlags.Val = IFlags;
1166 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1167 ARMOperand *Op = new ARMOperand(MSRMask);
1168 Op->MMask.Val = MMask;
1175 } // end anonymous namespace.
1177 void ARMOperand::print(raw_ostream &OS) const {
1180 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1183 OS << "<ccout " << getReg() << ">";
1186 OS << "<coprocessor number: " << getCoproc() << ">";
1189 OS << "<coprocessor register: " << getCoproc() << ">";
1192 OS << "<mask: " << getMSRMask() << ">";
1195 getImm()->print(OS);
1198 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1202 << " base:" << Mem.BaseRegNum;
1205 case PostIndexRegister:
1206 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
1207 << PostIdxReg.RegNum;
1208 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1209 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1210 << PostIdxReg.ShiftImm;
1214 OS << "<ARM_PROC::";
1215 unsigned IFlags = getProcIFlags();
1216 for (int i=2; i >= 0; --i)
1217 if (IFlags & (1 << i))
1218 OS << ARM_PROC::IFlagsToString(1 << i);
1223 OS << "<register " << getReg() << ">";
1225 case ShifterImmediate:
1226 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1227 << " #" << ShifterImm.Imm << ">";
1229 case ShiftedRegister:
1230 OS << "<so_reg_reg "
1231 << RegShiftedReg.SrcReg
1232 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1233 << ", " << RegShiftedReg.ShiftReg << ", "
1234 << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1237 case ShiftedImmediate:
1238 OS << "<so_reg_imm "
1239 << RegShiftedImm.SrcReg
1240 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1241 << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
1244 case RotateImmediate:
1245 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
1247 case BitfieldDescriptor:
1248 OS << "<bitfield " << "lsb: " << Bitfield.LSB
1249 << ", width: " << Bitfield.Width << ">";
1252 case DPRRegisterList:
1253 case SPRRegisterList: {
1254 OS << "<register_list ";
1256 const SmallVectorImpl<unsigned> &RegList = getRegList();
1257 for (SmallVectorImpl<unsigned>::const_iterator
1258 I = RegList.begin(), E = RegList.end(); I != E; ) {
1260 if (++I < E) OS << ", ";
1267 OS << "'" << getToken() << "'";
1272 /// @name Auto-generated Match Functions
1275 static unsigned MatchRegisterName(StringRef Name);
1279 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
1280 SMLoc &StartLoc, SMLoc &EndLoc) {
1281 RegNo = tryParseRegister();
1283 return (RegNo == (unsigned)-1);
1286 /// Try to parse a register name. The token must be an Identifier when called,
1287 /// and if it is a register name the token is eaten and the register number is
1288 /// returned. Otherwise return -1.
1290 int ARMAsmParser::tryParseRegister() {
1291 const AsmToken &Tok = Parser.getTok();
1292 if (Tok.isNot(AsmToken::Identifier)) return -1;
1294 // FIXME: Validate register for the current architecture; we have to do
1295 // validation later, so maybe there is no need for this here.
1296 std::string upperCase = Tok.getString().str();
1297 std::string lowerCase = LowercaseString(upperCase);
1298 unsigned RegNum = MatchRegisterName(lowerCase);
1300 RegNum = StringSwitch<unsigned>(lowerCase)
1301 .Case("r13", ARM::SP)
1302 .Case("r14", ARM::LR)
1303 .Case("r15", ARM::PC)
1304 .Case("ip", ARM::R12)
1307 if (!RegNum) return -1;
1309 Parser.Lex(); // Eat identifier token.
1313 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
1314 // If a recoverable error occurs, return 1. If an irrecoverable error
1315 // occurs, return -1. An irrecoverable error is one where tokens have been
1316 // consumed in the process of trying to parse the shifter (i.e., when it is
1317 // indeed a shifter operand, but malformed).
1318 int ARMAsmParser::tryParseShiftRegister(
1319 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1320 SMLoc S = Parser.getTok().getLoc();
1321 const AsmToken &Tok = Parser.getTok();
1322 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1324 std::string upperCase = Tok.getString().str();
1325 std::string lowerCase = LowercaseString(upperCase);
1326 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
1327 .Case("lsl", ARM_AM::lsl)
1328 .Case("lsr", ARM_AM::lsr)
1329 .Case("asr", ARM_AM::asr)
1330 .Case("ror", ARM_AM::ror)
1331 .Case("rrx", ARM_AM::rrx)
1332 .Default(ARM_AM::no_shift);
1334 if (ShiftTy == ARM_AM::no_shift)
1337 Parser.Lex(); // Eat the operator.
1339 // The source register for the shift has already been added to the
1340 // operand list, so we need to pop it off and combine it into the shifted
1341 // register operand instead.
1342 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
1343 if (!PrevOp->isReg())
1344 return Error(PrevOp->getStartLoc(), "shift must be of a register");
1345 int SrcReg = PrevOp->getReg();
1348 if (ShiftTy == ARM_AM::rrx) {
1349 // RRX Doesn't have an explicit shift amount. The encoder expects
1350 // the shift register to be the same as the source register. Seems odd,
1354 // Figure out if this is shifted by a constant or a register (for non-RRX).
1355 if (Parser.getTok().is(AsmToken::Hash)) {
1356 Parser.Lex(); // Eat hash.
1357 SMLoc ImmLoc = Parser.getTok().getLoc();
1358 const MCExpr *ShiftExpr = 0;
1359 if (getParser().ParseExpression(ShiftExpr)) {
1360 Error(ImmLoc, "invalid immediate shift value");
1363 // The expression must be evaluatable as an immediate.
1364 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
1366 Error(ImmLoc, "invalid immediate shift value");
1369 // Range check the immediate.
1370 // lsl, ror: 0 <= imm <= 31
1371 // lsr, asr: 0 <= imm <= 32
1372 Imm = CE->getValue();
1374 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
1375 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
1376 Error(ImmLoc, "immediate shift value out of range");
1379 } else if (Parser.getTok().is(AsmToken::Identifier)) {
1380 ShiftReg = tryParseRegister();
1381 SMLoc L = Parser.getTok().getLoc();
1382 if (ShiftReg == -1) {
1383 Error (L, "expected immediate or register in shift operand");
1387 Error (Parser.getTok().getLoc(),
1388 "expected immediate or register in shift operand");
1393 if (ShiftReg && ShiftTy != ARM_AM::rrx)
1394 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
1396 S, Parser.getTok().getLoc()));
1398 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
1399 S, Parser.getTok().getLoc()));
1405 /// Try to parse a register name. The token must be an Identifier when called.
1406 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
1407 /// if there is a "writeback". 'true' if it's not a register.
1409 /// TODO this is likely to change to allow different register types and or to
1410 /// parse for a specific register type.
1412 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1413 SMLoc S = Parser.getTok().getLoc();
1414 int RegNo = tryParseRegister();
1418 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1420 const AsmToken &ExclaimTok = Parser.getTok();
1421 if (ExclaimTok.is(AsmToken::Exclaim)) {
1422 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
1423 ExclaimTok.getLoc()));
1424 Parser.Lex(); // Eat exclaim token
1430 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
1431 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
1433 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
1434 // Use the same layout as the tablegen'erated register name matcher. Ugly,
1436 switch (Name.size()) {
1439 if (Name[0] != CoprocOp)
1456 if (Name[0] != CoprocOp || Name[1] != '1')
1460 case '0': return 10;
1461 case '1': return 11;
1462 case '2': return 12;
1463 case '3': return 13;
1464 case '4': return 14;
1465 case '5': return 15;
1473 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
1474 /// token must be an Identifier when called, and if it is a coprocessor
1475 /// number, the token is eaten and the operand is added to the operand list.
1476 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1477 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1478 SMLoc S = Parser.getTok().getLoc();
1479 const AsmToken &Tok = Parser.getTok();
1480 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1482 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
1484 return MatchOperand_NoMatch;
1486 Parser.Lex(); // Eat identifier token.
1487 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
1488 return MatchOperand_Success;
1491 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
1492 /// token must be an Identifier when called, and if it is a coprocessor
1493 /// number, the token is eaten and the operand is added to the operand list.
1494 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1495 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1496 SMLoc S = Parser.getTok().getLoc();
1497 const AsmToken &Tok = Parser.getTok();
1498 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1500 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
1502 return MatchOperand_NoMatch;
1504 Parser.Lex(); // Eat identifier token.
1505 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
1506 return MatchOperand_Success;
1509 /// Parse a register list, return it if successful else return null. The first
1510 /// token must be a '{' when called.
1512 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1513 assert(Parser.getTok().is(AsmToken::LCurly) &&
1514 "Token is not a Left Curly Brace");
1515 SMLoc S = Parser.getTok().getLoc();
1517 // Read the rest of the registers in the list.
1518 unsigned PrevRegNum = 0;
1519 SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
1522 bool IsRange = Parser.getTok().is(AsmToken::Minus);
1523 Parser.Lex(); // Eat non-identifier token.
1525 const AsmToken &RegTok = Parser.getTok();
1526 SMLoc RegLoc = RegTok.getLoc();
1527 if (RegTok.isNot(AsmToken::Identifier)) {
1528 Error(RegLoc, "register expected");
1532 int RegNum = tryParseRegister();
1534 Error(RegLoc, "register expected");
1539 int Reg = PrevRegNum;
1542 Registers.push_back(std::make_pair(Reg, RegLoc));
1543 } while (Reg != RegNum);
1545 Registers.push_back(std::make_pair(RegNum, RegLoc));
1548 PrevRegNum = RegNum;
1549 } while (Parser.getTok().is(AsmToken::Comma) ||
1550 Parser.getTok().is(AsmToken::Minus));
1552 // Process the right curly brace of the list.
1553 const AsmToken &RCurlyTok = Parser.getTok();
1554 if (RCurlyTok.isNot(AsmToken::RCurly)) {
1555 Error(RCurlyTok.getLoc(), "'}' expected");
1559 SMLoc E = RCurlyTok.getLoc();
1560 Parser.Lex(); // Eat right curly brace token.
1562 // Verify the register list.
1563 SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1564 RI = Registers.begin(), RE = Registers.end();
1566 unsigned HighRegNum = getARMRegisterNumbering(RI->first);
1567 bool EmittedWarning = false;
1569 DenseMap<unsigned, bool> RegMap;
1570 RegMap[HighRegNum] = true;
1572 for (++RI; RI != RE; ++RI) {
1573 const std::pair<unsigned, SMLoc> &RegInfo = *RI;
1574 unsigned Reg = getARMRegisterNumbering(RegInfo.first);
1577 Error(RegInfo.second, "register duplicated in register list");
1581 if (!EmittedWarning && Reg < HighRegNum)
1582 Warning(RegInfo.second,
1583 "register not in ascending order in register list");
1586 HighRegNum = std::max(Reg, HighRegNum);
1589 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
1593 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
1594 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1595 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1596 SMLoc S = Parser.getTok().getLoc();
1597 const AsmToken &Tok = Parser.getTok();
1598 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1599 StringRef OptStr = Tok.getString();
1601 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
1602 .Case("sy", ARM_MB::SY)
1603 .Case("st", ARM_MB::ST)
1604 .Case("sh", ARM_MB::ISH)
1605 .Case("ish", ARM_MB::ISH)
1606 .Case("shst", ARM_MB::ISHST)
1607 .Case("ishst", ARM_MB::ISHST)
1608 .Case("nsh", ARM_MB::NSH)
1609 .Case("un", ARM_MB::NSH)
1610 .Case("nshst", ARM_MB::NSHST)
1611 .Case("unst", ARM_MB::NSHST)
1612 .Case("osh", ARM_MB::OSH)
1613 .Case("oshst", ARM_MB::OSHST)
1617 return MatchOperand_NoMatch;
1619 Parser.Lex(); // Eat identifier token.
1620 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
1621 return MatchOperand_Success;
1624 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
1625 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1626 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1627 SMLoc S = Parser.getTok().getLoc();
1628 const AsmToken &Tok = Parser.getTok();
1629 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1630 StringRef IFlagsStr = Tok.getString();
1632 unsigned IFlags = 0;
1633 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
1634 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
1635 .Case("a", ARM_PROC::A)
1636 .Case("i", ARM_PROC::I)
1637 .Case("f", ARM_PROC::F)
1640 // If some specific iflag is already set, it means that some letter is
1641 // present more than once, this is not acceptable.
1642 if (Flag == ~0U || (IFlags & Flag))
1643 return MatchOperand_NoMatch;
1648 Parser.Lex(); // Eat identifier token.
1649 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
1650 return MatchOperand_Success;
1653 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
1654 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1655 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1656 SMLoc S = Parser.getTok().getLoc();
1657 const AsmToken &Tok = Parser.getTok();
1658 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1659 StringRef Mask = Tok.getString();
1661 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
1662 size_t Start = 0, Next = Mask.find('_');
1663 StringRef Flags = "";
1664 std::string SpecReg = LowercaseString(Mask.slice(Start, Next));
1665 if (Next != StringRef::npos)
1666 Flags = Mask.slice(Next+1, Mask.size());
1668 // FlagsVal contains the complete mask:
1670 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1671 unsigned FlagsVal = 0;
1673 if (SpecReg == "apsr") {
1674 FlagsVal = StringSwitch<unsigned>(Flags)
1675 .Case("nzcvq", 0x8) // same as CPSR_f
1676 .Case("g", 0x4) // same as CPSR_s
1677 .Case("nzcvqg", 0xc) // same as CPSR_fs
1680 if (FlagsVal == ~0U) {
1682 return MatchOperand_NoMatch;
1684 FlagsVal = 0; // No flag
1686 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
1687 if (Flags == "all") // cpsr_all is an alias for cpsr_fc
1689 for (int i = 0, e = Flags.size(); i != e; ++i) {
1690 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
1697 // If some specific flag is already set, it means that some letter is
1698 // present more than once, this is not acceptable.
1699 if (FlagsVal == ~0U || (FlagsVal & Flag))
1700 return MatchOperand_NoMatch;
1703 } else // No match for special register.
1704 return MatchOperand_NoMatch;
1706 // Special register without flags are equivalent to "fc" flags.
1710 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1711 if (SpecReg == "spsr")
1714 Parser.Lex(); // Eat identifier token.
1715 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
1716 return MatchOperand_Success;
1719 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1720 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
1721 int Low, int High) {
1722 const AsmToken &Tok = Parser.getTok();
1723 if (Tok.isNot(AsmToken::Identifier)) {
1724 Error(Parser.getTok().getLoc(), Op + " operand expected.");
1725 return MatchOperand_ParseFail;
1727 StringRef ShiftName = Tok.getString();
1728 std::string LowerOp = LowercaseString(Op);
1729 std::string UpperOp = UppercaseString(Op);
1730 if (ShiftName != LowerOp && ShiftName != UpperOp) {
1731 Error(Parser.getTok().getLoc(), Op + " operand expected.");
1732 return MatchOperand_ParseFail;
1734 Parser.Lex(); // Eat shift type token.
1736 // There must be a '#' and a shift amount.
1737 if (Parser.getTok().isNot(AsmToken::Hash)) {
1738 Error(Parser.getTok().getLoc(), "'#' expected");
1739 return MatchOperand_ParseFail;
1741 Parser.Lex(); // Eat hash token.
1743 const MCExpr *ShiftAmount;
1744 SMLoc Loc = Parser.getTok().getLoc();
1745 if (getParser().ParseExpression(ShiftAmount)) {
1746 Error(Loc, "illegal expression");
1747 return MatchOperand_ParseFail;
1749 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1751 Error(Loc, "constant expression expected");
1752 return MatchOperand_ParseFail;
1754 int Val = CE->getValue();
1755 if (Val < Low || Val > High) {
1756 Error(Loc, "immediate value out of range");
1757 return MatchOperand_ParseFail;
1760 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
1762 return MatchOperand_Success;
1765 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1766 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1767 const AsmToken &Tok = Parser.getTok();
1768 SMLoc S = Tok.getLoc();
1769 if (Tok.isNot(AsmToken::Identifier)) {
1770 Error(Tok.getLoc(), "'be' or 'le' operand expected");
1771 return MatchOperand_ParseFail;
1773 int Val = StringSwitch<int>(Tok.getString())
1777 Parser.Lex(); // Eat the token.
1780 Error(Tok.getLoc(), "'be' or 'le' operand expected");
1781 return MatchOperand_ParseFail;
1783 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
1785 S, Parser.getTok().getLoc()));
1786 return MatchOperand_Success;
1789 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
1790 /// instructions. Legal values are:
1791 /// lsl #n 'n' in [0,31]
1792 /// asr #n 'n' in [1,32]
1793 /// n == 32 encoded as n == 0.
1794 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1795 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1796 const AsmToken &Tok = Parser.getTok();
1797 SMLoc S = Tok.getLoc();
1798 if (Tok.isNot(AsmToken::Identifier)) {
1799 Error(S, "shift operator 'asr' or 'lsl' expected");
1800 return MatchOperand_ParseFail;
1802 StringRef ShiftName = Tok.getString();
1804 if (ShiftName == "lsl" || ShiftName == "LSL")
1806 else if (ShiftName == "asr" || ShiftName == "ASR")
1809 Error(S, "shift operator 'asr' or 'lsl' expected");
1810 return MatchOperand_ParseFail;
1812 Parser.Lex(); // Eat the operator.
1814 // A '#' and a shift amount.
1815 if (Parser.getTok().isNot(AsmToken::Hash)) {
1816 Error(Parser.getTok().getLoc(), "'#' expected");
1817 return MatchOperand_ParseFail;
1819 Parser.Lex(); // Eat hash token.
1821 const MCExpr *ShiftAmount;
1822 SMLoc E = Parser.getTok().getLoc();
1823 if (getParser().ParseExpression(ShiftAmount)) {
1824 Error(E, "malformed shift expression");
1825 return MatchOperand_ParseFail;
1827 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1829 Error(E, "shift amount must be an immediate");
1830 return MatchOperand_ParseFail;
1833 int64_t Val = CE->getValue();
1835 // Shift amount must be in [1,32]
1836 if (Val < 1 || Val > 32) {
1837 Error(E, "'asr' shift amount must be in range [1,32]");
1838 return MatchOperand_ParseFail;
1840 // asr #32 encoded as asr #0.
1841 if (Val == 32) Val = 0;
1843 // Shift amount must be in [1,32]
1844 if (Val < 0 || Val > 31) {
1845 Error(E, "'lsr' shift amount must be in range [0,31]");
1846 return MatchOperand_ParseFail;
1850 E = Parser.getTok().getLoc();
1851 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
1853 return MatchOperand_Success;
1856 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
1857 /// of instructions. Legal values are:
1858 /// ror #n 'n' in {0, 8, 16, 24}
1859 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1860 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1861 const AsmToken &Tok = Parser.getTok();
1862 SMLoc S = Tok.getLoc();
1863 if (Tok.isNot(AsmToken::Identifier)) {
1864 Error(S, "rotate operator 'ror' expected");
1865 return MatchOperand_ParseFail;
1867 StringRef ShiftName = Tok.getString();
1868 if (ShiftName != "ror" && ShiftName != "ROR") {
1869 Error(S, "rotate operator 'ror' expected");
1870 return MatchOperand_ParseFail;
1872 Parser.Lex(); // Eat the operator.
1874 // A '#' and a rotate amount.
1875 if (Parser.getTok().isNot(AsmToken::Hash)) {
1876 Error(Parser.getTok().getLoc(), "'#' expected");
1877 return MatchOperand_ParseFail;
1879 Parser.Lex(); // Eat hash token.
1881 const MCExpr *ShiftAmount;
1882 SMLoc E = Parser.getTok().getLoc();
1883 if (getParser().ParseExpression(ShiftAmount)) {
1884 Error(E, "malformed rotate expression");
1885 return MatchOperand_ParseFail;
1887 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1889 Error(E, "rotate amount must be an immediate");
1890 return MatchOperand_ParseFail;
1893 int64_t Val = CE->getValue();
1894 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
1895 // normally, zero is represented in asm by omitting the rotate operand
1897 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
1898 Error(E, "'ror' rotate amount must be 8, 16, or 24");
1899 return MatchOperand_ParseFail;
1902 E = Parser.getTok().getLoc();
1903 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
1905 return MatchOperand_Success;
1908 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1909 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1910 SMLoc S = Parser.getTok().getLoc();
1911 // The bitfield descriptor is really two operands, the LSB and the width.
1912 if (Parser.getTok().isNot(AsmToken::Hash)) {
1913 Error(Parser.getTok().getLoc(), "'#' expected");
1914 return MatchOperand_ParseFail;
1916 Parser.Lex(); // Eat hash token.
1918 const MCExpr *LSBExpr;
1919 SMLoc E = Parser.getTok().getLoc();
1920 if (getParser().ParseExpression(LSBExpr)) {
1921 Error(E, "malformed immediate expression");
1922 return MatchOperand_ParseFail;
1924 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
1926 Error(E, "'lsb' operand must be an immediate");
1927 return MatchOperand_ParseFail;
1930 int64_t LSB = CE->getValue();
1931 // The LSB must be in the range [0,31]
1932 if (LSB < 0 || LSB > 31) {
1933 Error(E, "'lsb' operand must be in the range [0,31]");
1934 return MatchOperand_ParseFail;
1936 E = Parser.getTok().getLoc();
1938 // Expect another immediate operand.
1939 if (Parser.getTok().isNot(AsmToken::Comma)) {
1940 Error(Parser.getTok().getLoc(), "too few operands");
1941 return MatchOperand_ParseFail;
1943 Parser.Lex(); // Eat hash token.
1944 if (Parser.getTok().isNot(AsmToken::Hash)) {
1945 Error(Parser.getTok().getLoc(), "'#' expected");
1946 return MatchOperand_ParseFail;
1948 Parser.Lex(); // Eat hash token.
1950 const MCExpr *WidthExpr;
1951 if (getParser().ParseExpression(WidthExpr)) {
1952 Error(E, "malformed immediate expression");
1953 return MatchOperand_ParseFail;
1955 CE = dyn_cast<MCConstantExpr>(WidthExpr);
1957 Error(E, "'width' operand must be an immediate");
1958 return MatchOperand_ParseFail;
1961 int64_t Width = CE->getValue();
1962 // The LSB must be in the range [1,32-lsb]
1963 if (Width < 1 || Width > 32 - LSB) {
1964 Error(E, "'width' operand must be in the range [1,32-lsb]");
1965 return MatchOperand_ParseFail;
1967 E = Parser.getTok().getLoc();
1969 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
1971 return MatchOperand_Success;
1974 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1975 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1976 // Check for a post-index addressing register operand. Specifically:
1977 // postidx_reg := '+' register {, shift}
1978 // | '-' register {, shift}
1979 // | register {, shift}
1981 // This method must return MatchOperand_NoMatch without consuming any tokens
1982 // in the case where there is no match, as other alternatives take other
1984 AsmToken Tok = Parser.getTok();
1985 SMLoc S = Tok.getLoc();
1986 bool haveEaten = false;
1989 if (Tok.is(AsmToken::Plus)) {
1990 Parser.Lex(); // Eat the '+' token.
1992 } else if (Tok.is(AsmToken::Minus)) {
1993 Parser.Lex(); // Eat the '-' token.
1997 if (Parser.getTok().is(AsmToken::Identifier))
1998 Reg = tryParseRegister();
2001 return MatchOperand_NoMatch;
2002 Error(Parser.getTok().getLoc(), "register expected");
2003 return MatchOperand_ParseFail;
2005 SMLoc E = Parser.getTok().getLoc();
2007 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
2008 unsigned ShiftImm = 0;
2009 if (Parser.getTok().is(AsmToken::Comma)) {
2010 Parser.Lex(); // Eat the ','.
2011 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
2012 return MatchOperand_ParseFail;
2015 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
2018 return MatchOperand_Success;
2021 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2022 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2023 // Check for a post-index addressing register operand. Specifically:
2024 // am3offset := '+' register
2031 // This method must return MatchOperand_NoMatch without consuming any tokens
2032 // in the case where there is no match, as other alternatives take other
2034 AsmToken Tok = Parser.getTok();
2035 SMLoc S = Tok.getLoc();
2037 // Do immediates first, as we always parse those if we have a '#'.
2038 if (Parser.getTok().is(AsmToken::Hash)) {
2039 Parser.Lex(); // Eat the '#'.
2040 // Explicitly look for a '-', as we need to encode negative zero
2042 bool isNegative = Parser.getTok().is(AsmToken::Minus);
2043 const MCExpr *Offset;
2044 if (getParser().ParseExpression(Offset))
2045 return MatchOperand_ParseFail;
2046 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2048 Error(S, "constant expression expected");
2049 return MatchOperand_ParseFail;
2051 SMLoc E = Tok.getLoc();
2052 // Negative zero is encoded as the flag value INT32_MIN.
2053 int32_t Val = CE->getValue();
2054 if (isNegative && Val == 0)
2058 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
2060 return MatchOperand_Success;
2064 bool haveEaten = false;
2067 if (Tok.is(AsmToken::Plus)) {
2068 Parser.Lex(); // Eat the '+' token.
2070 } else if (Tok.is(AsmToken::Minus)) {
2071 Parser.Lex(); // Eat the '-' token.
2075 if (Parser.getTok().is(AsmToken::Identifier))
2076 Reg = tryParseRegister();
2079 return MatchOperand_NoMatch;
2080 Error(Parser.getTok().getLoc(), "register expected");
2081 return MatchOperand_ParseFail;
2083 SMLoc E = Parser.getTok().getLoc();
2085 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
2088 return MatchOperand_Success;
2091 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2092 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2093 /// when they refer multiple MIOperands inside a single one.
2095 cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2096 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2097 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2099 // Create a writeback register dummy placeholder.
2100 Inst.addOperand(MCOperand::CreateImm(0));
2102 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2103 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2107 /// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2108 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2109 /// when they refer multiple MIOperands inside a single one.
2111 cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2112 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2113 // Create a writeback register dummy placeholder.
2114 Inst.addOperand(MCOperand::CreateImm(0));
2115 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2116 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2117 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2121 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2122 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2123 /// when they refer multiple MIOperands inside a single one.
2125 cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2126 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2127 // Create a writeback register dummy placeholder.
2128 Inst.addOperand(MCOperand::CreateImm(0));
2129 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2130 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2131 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2135 /// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
2136 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2137 /// when they refer multiple MIOperands inside a single one.
2139 cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2140 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2142 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2143 // Create a writeback register dummy placeholder.
2144 Inst.addOperand(MCOperand::CreateImm(0));
2146 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2148 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2150 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2154 /// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
2155 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2156 /// when they refer multiple MIOperands inside a single one.
2158 cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2159 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2161 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2162 // Create a writeback register dummy placeholder.
2163 Inst.addOperand(MCOperand::CreateImm(0));
2165 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2167 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2169 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2173 /// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
2174 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2175 /// when they refer multiple MIOperands inside a single one.
2177 cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2178 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2179 // Create a writeback register dummy placeholder.
2180 Inst.addOperand(MCOperand::CreateImm(0));
2182 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2184 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2186 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2188 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2192 /// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
2193 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2194 /// when they refer multiple MIOperands inside a single one.
2196 cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2197 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2198 // Create a writeback register dummy placeholder.
2199 Inst.addOperand(MCOperand::CreateImm(0));
2201 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2203 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2205 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2207 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2211 /// cvtLdrdPre - Convert parsed operands to MCInst.
2212 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2213 /// when they refer multiple MIOperands inside a single one.
2215 cvtLdrdPre(MCInst &Inst, unsigned Opcode,
2216 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2218 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2219 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2220 // Create a writeback register dummy placeholder.
2221 Inst.addOperand(MCOperand::CreateImm(0));
2223 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2225 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2229 /// cvtStrdPre - Convert parsed operands to MCInst.
2230 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2231 /// when they refer multiple MIOperands inside a single one.
2233 cvtStrdPre(MCInst &Inst, unsigned Opcode,
2234 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2235 // Create a writeback register dummy placeholder.
2236 Inst.addOperand(MCOperand::CreateImm(0));
2238 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2239 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2241 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2243 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2247 /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2248 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2249 /// when they refer multiple MIOperands inside a single one.
2251 cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2252 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2253 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2254 // Create a writeback register dummy placeholder.
2255 Inst.addOperand(MCOperand::CreateImm(0));
2256 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2257 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2262 /// Parse an ARM memory expression, return false if successful else return true
2263 /// or an error. The first token must be a '[' when called.
2265 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2267 assert(Parser.getTok().is(AsmToken::LBrac) &&
2268 "Token is not a Left Bracket");
2269 S = Parser.getTok().getLoc();
2270 Parser.Lex(); // Eat left bracket token.
2272 const AsmToken &BaseRegTok = Parser.getTok();
2273 int BaseRegNum = tryParseRegister();
2274 if (BaseRegNum == -1)
2275 return Error(BaseRegTok.getLoc(), "register expected");
2277 // The next token must either be a comma or a closing bracket.
2278 const AsmToken &Tok = Parser.getTok();
2279 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
2280 return Error(Tok.getLoc(), "malformed memory operand");
2282 if (Tok.is(AsmToken::RBrac)) {
2284 Parser.Lex(); // Eat right bracket token.
2286 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
2292 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
2293 Parser.Lex(); // Eat the comma.
2295 // If we have a '#' it's an immediate offset, else assume it's a register
2297 if (Parser.getTok().is(AsmToken::Hash)) {
2298 Parser.Lex(); // Eat the '#'.
2299 E = Parser.getTok().getLoc();
2301 // FIXME: Special case #-0 so we can correctly set the U bit.
2303 const MCExpr *Offset;
2304 if (getParser().ParseExpression(Offset))
2307 // The expression has to be a constant. Memory references with relocations
2308 // don't come through here, as they use the <label> forms of the relevant
2310 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2312 return Error (E, "constant expression expected");
2314 // Now we should have the closing ']'
2315 E = Parser.getTok().getLoc();
2316 if (Parser.getTok().isNot(AsmToken::RBrac))
2317 return Error(E, "']' expected");
2318 Parser.Lex(); // Eat right bracket token.
2320 // Don't worry about range checking the value here. That's handled by
2321 // the is*() predicates.
2322 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
2323 ARM_AM::no_shift, 0, false, S,E));
2325 // If there's a pre-indexing writeback marker, '!', just add it as a token
2327 if (Parser.getTok().is(AsmToken::Exclaim)) {
2328 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2329 Parser.Lex(); // Eat the '!'.
2335 // The register offset is optionally preceded by a '+' or '-'
2336 bool isNegative = false;
2337 if (Parser.getTok().is(AsmToken::Minus)) {
2339 Parser.Lex(); // Eat the '-'.
2340 } else if (Parser.getTok().is(AsmToken::Plus)) {
2342 Parser.Lex(); // Eat the '+'.
2345 E = Parser.getTok().getLoc();
2346 int OffsetRegNum = tryParseRegister();
2347 if (OffsetRegNum == -1)
2348 return Error(E, "register expected");
2350 // If there's a shift operator, handle it.
2351 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
2352 unsigned ShiftImm = 0;
2353 if (Parser.getTok().is(AsmToken::Comma)) {
2354 Parser.Lex(); // Eat the ','.
2355 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
2359 // Now we should have the closing ']'
2360 E = Parser.getTok().getLoc();
2361 if (Parser.getTok().isNot(AsmToken::RBrac))
2362 return Error(E, "']' expected");
2363 Parser.Lex(); // Eat right bracket token.
2365 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
2366 ShiftType, ShiftImm, isNegative,
2369 // If there's a pre-indexing writeback marker, '!', just add it as a token
2371 if (Parser.getTok().is(AsmToken::Exclaim)) {
2372 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2373 Parser.Lex(); // Eat the '!'.
2379 /// parseMemRegOffsetShift - one of these two:
2380 /// ( lsl | lsr | asr | ror ) , # shift_amount
2382 /// return true if it parses a shift otherwise it returns false.
2383 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
2385 SMLoc Loc = Parser.getTok().getLoc();
2386 const AsmToken &Tok = Parser.getTok();
2387 if (Tok.isNot(AsmToken::Identifier))
2389 StringRef ShiftName = Tok.getString();
2390 if (ShiftName == "lsl" || ShiftName == "LSL")
2392 else if (ShiftName == "lsr" || ShiftName == "LSR")
2394 else if (ShiftName == "asr" || ShiftName == "ASR")
2396 else if (ShiftName == "ror" || ShiftName == "ROR")
2398 else if (ShiftName == "rrx" || ShiftName == "RRX")
2401 return Error(Loc, "illegal shift operator");
2402 Parser.Lex(); // Eat shift type token.
2404 // rrx stands alone.
2406 if (St != ARM_AM::rrx) {
2407 Loc = Parser.getTok().getLoc();
2408 // A '#' and a shift amount.
2409 const AsmToken &HashTok = Parser.getTok();
2410 if (HashTok.isNot(AsmToken::Hash))
2411 return Error(HashTok.getLoc(), "'#' expected");
2412 Parser.Lex(); // Eat hash token.
2415 if (getParser().ParseExpression(Expr))
2417 // Range check the immediate.
2418 // lsl, ror: 0 <= imm <= 31
2419 // lsr, asr: 0 <= imm <= 32
2420 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2422 return Error(Loc, "shift amount must be an immediate");
2423 int64_t Imm = CE->getValue();
2425 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
2426 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
2427 return Error(Loc, "immediate shift value out of range");
2434 /// Parse a arm instruction operand. For now this parses the operand regardless
2435 /// of the mnemonic.
2436 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2437 StringRef Mnemonic) {
2440 // Check if the current operand has a custom associated parser, if so, try to
2441 // custom parse the operand, or fallback to the general approach.
2442 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
2443 if (ResTy == MatchOperand_Success)
2445 // If there wasn't a custom match, try the generic matcher below. Otherwise,
2446 // there was a match, but an error occurred, in which case, just return that
2447 // the operand parsing failed.
2448 if (ResTy == MatchOperand_ParseFail)
2451 switch (getLexer().getKind()) {
2453 Error(Parser.getTok().getLoc(), "unexpected token in operand");
2455 case AsmToken::Identifier: {
2456 if (!tryParseRegisterWithWriteBack(Operands))
2458 int Res = tryParseShiftRegister(Operands);
2459 if (Res == 0) // success
2461 else if (Res == -1) // irrecoverable error
2464 // Fall though for the Identifier case that is not a register or a
2467 case AsmToken::Integer: // things like 1f and 2b as a branch targets
2468 case AsmToken::Dot: { // . as a branch target
2469 // This was not a register so parse other operands that start with an
2470 // identifier (like labels) as expressions and create them as immediates.
2471 const MCExpr *IdVal;
2472 S = Parser.getTok().getLoc();
2473 if (getParser().ParseExpression(IdVal))
2475 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2476 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
2479 case AsmToken::LBrac:
2480 return parseMemory(Operands);
2481 case AsmToken::LCurly:
2482 return parseRegisterList(Operands);
2483 case AsmToken::Hash:
2484 // #42 -> immediate.
2485 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
2486 S = Parser.getTok().getLoc();
2488 const MCExpr *ImmVal;
2489 if (getParser().ParseExpression(ImmVal))
2491 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2492 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
2494 case AsmToken::Colon: {
2495 // ":lower16:" and ":upper16:" expression prefixes
2496 // FIXME: Check it's an expression prefix,
2497 // e.g. (FOO - :lower16:BAR) isn't legal.
2498 ARMMCExpr::VariantKind RefKind;
2499 if (parsePrefix(RefKind))
2502 const MCExpr *SubExprVal;
2503 if (getParser().ParseExpression(SubExprVal))
2506 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
2508 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2509 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
2515 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
2516 // :lower16: and :upper16:.
2517 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
2518 RefKind = ARMMCExpr::VK_ARM_None;
2520 // :lower16: and :upper16: modifiers
2521 assert(getLexer().is(AsmToken::Colon) && "expected a :");
2522 Parser.Lex(); // Eat ':'
2524 if (getLexer().isNot(AsmToken::Identifier)) {
2525 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
2529 StringRef IDVal = Parser.getTok().getIdentifier();
2530 if (IDVal == "lower16") {
2531 RefKind = ARMMCExpr::VK_ARM_LO16;
2532 } else if (IDVal == "upper16") {
2533 RefKind = ARMMCExpr::VK_ARM_HI16;
2535 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
2540 if (getLexer().isNot(AsmToken::Colon)) {
2541 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
2544 Parser.Lex(); // Eat the last ':'
2549 ARMAsmParser::applyPrefixToExpr(const MCExpr *E,
2550 MCSymbolRefExpr::VariantKind Variant) {
2551 // Recurse over the given expression, rebuilding it to apply the given variant
2552 // to the leftmost symbol.
2553 if (Variant == MCSymbolRefExpr::VK_None)
2556 switch (E->getKind()) {
2557 case MCExpr::Target:
2558 llvm_unreachable("Can't handle target expr yet");
2559 case MCExpr::Constant:
2560 llvm_unreachable("Can't handle lower16/upper16 of constant yet");
2562 case MCExpr::SymbolRef: {
2563 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
2565 if (SRE->getKind() != MCSymbolRefExpr::VK_None)
2568 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext());
2572 llvm_unreachable("Can't handle unary expressions yet");
2574 case MCExpr::Binary: {
2575 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
2576 const MCExpr *LHS = applyPrefixToExpr(BE->getLHS(), Variant);
2577 const MCExpr *RHS = BE->getRHS();
2581 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext());
2585 assert(0 && "Invalid expression kind!");
2589 /// \brief Given a mnemonic, split out possible predication code and carry
2590 /// setting letters to form a canonical mnemonic and flags.
2592 // FIXME: Would be nice to autogen this.
2593 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
2594 unsigned &PredicationCode,
2596 unsigned &ProcessorIMod) {
2597 PredicationCode = ARMCC::AL;
2598 CarrySetting = false;
2601 // Ignore some mnemonics we know aren't predicated forms.
2603 // FIXME: Would be nice to autogen this.
2604 if ((Mnemonic == "movs" && isThumb()) ||
2605 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
2606 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
2607 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
2608 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
2609 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
2610 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
2611 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
2614 // First, split out any predication code. Ignore mnemonics we know aren't
2615 // predicated but do have a carry-set and so weren't caught above.
2616 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
2617 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
2618 Mnemonic != "umlals" && Mnemonic != "umulls") {
2619 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
2620 .Case("eq", ARMCC::EQ)
2621 .Case("ne", ARMCC::NE)
2622 .Case("hs", ARMCC::HS)
2623 .Case("cs", ARMCC::HS)
2624 .Case("lo", ARMCC::LO)
2625 .Case("cc", ARMCC::LO)
2626 .Case("mi", ARMCC::MI)
2627 .Case("pl", ARMCC::PL)
2628 .Case("vs", ARMCC::VS)
2629 .Case("vc", ARMCC::VC)
2630 .Case("hi", ARMCC::HI)
2631 .Case("ls", ARMCC::LS)
2632 .Case("ge", ARMCC::GE)
2633 .Case("lt", ARMCC::LT)
2634 .Case("gt", ARMCC::GT)
2635 .Case("le", ARMCC::LE)
2636 .Case("al", ARMCC::AL)
2639 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
2640 PredicationCode = CC;
2644 // Next, determine if we have a carry setting bit. We explicitly ignore all
2645 // the instructions we know end in 's'.
2646 if (Mnemonic.endswith("s") &&
2647 !(Mnemonic == "asrs" || Mnemonic == "cps" || Mnemonic == "mls" ||
2648 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
2649 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
2650 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
2651 Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
2652 (Mnemonic == "movs" && isThumb()))) {
2653 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
2654 CarrySetting = true;
2657 // The "cps" instruction can have a interrupt mode operand which is glued into
2658 // the mnemonic. Check if this is the case, split it and parse the imod op
2659 if (Mnemonic.startswith("cps")) {
2660 // Split out any imod code.
2662 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
2663 .Case("ie", ARM_PROC::IE)
2664 .Case("id", ARM_PROC::ID)
2667 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
2668 ProcessorIMod = IMod;
2675 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
2676 /// inclusion of carry set or predication code operands.
2678 // FIXME: It would be nice to autogen this.
2680 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
2681 bool &CanAcceptPredicationCode) {
2682 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
2683 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
2684 Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
2685 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
2686 Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" ||
2687 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
2688 Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
2689 Mnemonic == "eor" || Mnemonic == "smlal" ||
2690 (Mnemonic == "mov" && !isThumbOne())) {
2691 CanAcceptCarrySet = true;
2693 CanAcceptCarrySet = false;
2696 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
2697 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
2698 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
2699 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
2700 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "clrex" ||
2701 Mnemonic == "setend" ||
2702 ((Mnemonic == "pld" || Mnemonic == "pli") && !isThumb()) ||
2703 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs"))
2705 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumb())) {
2706 CanAcceptPredicationCode = false;
2708 CanAcceptPredicationCode = true;
2712 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
2713 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
2714 CanAcceptPredicationCode = false;
2717 /// Parse an arm instruction mnemonic followed by its operands.
2718 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
2719 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2720 // Create the leading tokens for the mnemonic, split by '.' characters.
2721 size_t Start = 0, Next = Name.find('.');
2722 StringRef Mnemonic = Name.slice(Start, Next);
2724 // Split out the predication code and carry setting flag from the mnemonic.
2725 unsigned PredicationCode;
2726 unsigned ProcessorIMod;
2728 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
2731 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
2733 // FIXME: This is all a pretty gross hack. We should automatically handle
2734 // optional operands like this via tblgen.
2736 // Next, add the CCOut and ConditionCode operands, if needed.
2738 // For mnemonics which can ever incorporate a carry setting bit or predication
2739 // code, our matching model involves us always generating CCOut and
2740 // ConditionCode operands to match the mnemonic "as written" and then we let
2741 // the matcher deal with finding the right instruction or generating an
2742 // appropriate error.
2743 bool CanAcceptCarrySet, CanAcceptPredicationCode;
2744 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
2746 // If we had a carry-set on an instruction that can't do that, issue an
2748 if (!CanAcceptCarrySet && CarrySetting) {
2749 Parser.EatToEndOfStatement();
2750 return Error(NameLoc, "instruction '" + Mnemonic +
2751 "' can not set flags, but 's' suffix specified");
2753 // If we had a predication code on an instruction that can't do that, issue an
2755 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
2756 Parser.EatToEndOfStatement();
2757 return Error(NameLoc, "instruction '" + Mnemonic +
2758 "' is not predicable, but condition code specified");
2761 // Add the carry setting operand, if necessary.
2763 // FIXME: It would be awesome if we could somehow invent a location such that
2764 // match errors on this operand would print a nice diagnostic about how the
2765 // 's' character in the mnemonic resulted in a CCOut operand.
2766 if (CanAcceptCarrySet)
2767 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
2770 // Add the predication code operand, if necessary.
2771 if (CanAcceptPredicationCode) {
2772 Operands.push_back(ARMOperand::CreateCondCode(
2773 ARMCC::CondCodes(PredicationCode), NameLoc));
2776 // Add the processor imod operand, if necessary.
2777 if (ProcessorIMod) {
2778 Operands.push_back(ARMOperand::CreateImm(
2779 MCConstantExpr::Create(ProcessorIMod, getContext()),
2782 // This mnemonic can't ever accept a imod, but the user wrote
2783 // one (or misspelled another mnemonic).
2785 // FIXME: Issue a nice error.
2788 // Add the remaining tokens in the mnemonic.
2789 while (Next != StringRef::npos) {
2791 Next = Name.find('.', Start + 1);
2792 StringRef ExtraToken = Name.slice(Start, Next);
2794 Operands.push_back(ARMOperand::CreateToken(ExtraToken, NameLoc));
2797 // Read the remaining operands.
2798 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2799 // Read the first operand.
2800 if (parseOperand(Operands, Mnemonic)) {
2801 Parser.EatToEndOfStatement();
2805 while (getLexer().is(AsmToken::Comma)) {
2806 Parser.Lex(); // Eat the comma.
2808 // Parse and remember the operand.
2809 if (parseOperand(Operands, Mnemonic)) {
2810 Parser.EatToEndOfStatement();
2816 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2817 Parser.EatToEndOfStatement();
2818 return TokError("unexpected token in argument list");
2821 Parser.Lex(); // Consume the EndOfStatement
2824 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
2825 // another does not. Specifically, the MOVW instruction does not. So we
2826 // special case it here and remove the defaulted (non-setting) cc_out
2827 // operand if that's the instruction we're trying to match.
2829 // We do this post-processing of the explicit operands rather than just
2830 // conditionally adding the cc_out in the first place because we need
2831 // to check the type of the parsed immediate operand.
2832 if (Mnemonic == "mov" && Operands.size() > 4 &&
2833 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
2834 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
2835 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) {
2836 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
2837 Operands.erase(Operands.begin() + 1);
2841 // ARM mode 'blx' need special handling, as the register operand version
2842 // is predicable, but the label operand version is not. So, we can't rely
2843 // on the Mnemonic based checking to correctly figure out when to put
2844 // a CondCode operand in the list. If we're trying to match the label
2845 // version, remove the CondCode operand here.
2846 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
2847 static_cast<ARMOperand*>(Operands[2])->isImm()) {
2848 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
2849 Operands.erase(Operands.begin() + 1);
2855 // Validate context-sensitive operand constraints.
2856 // FIXME: We would really like to be able to tablegen'erate this.
2858 validateInstruction(MCInst &Inst,
2859 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2860 switch (Inst.getOpcode()) {
2863 case ARM::LDRD_POST:
2865 // Rt2 must be Rt + 1.
2866 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
2867 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
2869 return Error(Operands[3]->getStartLoc(),
2870 "destination operands must be sequential");
2874 // Rt2 must be Rt + 1.
2875 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
2876 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
2878 return Error(Operands[3]->getStartLoc(),
2879 "source operands must be sequential");
2883 case ARM::STRD_POST:
2885 // Rt2 must be Rt + 1.
2886 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
2887 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
2889 return Error(Operands[3]->getStartLoc(),
2890 "source operands must be sequential");
2895 // width must be in range [1, 32-lsb]
2896 unsigned lsb = Inst.getOperand(2).getImm();
2897 unsigned widthm1 = Inst.getOperand(3).getImm();
2898 if (widthm1 >= 32 - lsb)
2899 return Error(Operands[5]->getStartLoc(),
2900 "bitfield width must be in range [1,32-lsb]");
2908 processInstruction(MCInst &Inst,
2909 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2910 switch (Inst.getOpcode()) {
2911 case ARM::LDMIA_UPD:
2912 // If this is a load of a single register via a 'pop', then we should use
2913 // a post-indexed LDR instruction instead, per the ARM ARM.
2914 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
2915 Inst.getNumOperands() == 5) {
2917 TmpInst.setOpcode(ARM::LDR_POST_IMM);
2918 TmpInst.addOperand(Inst.getOperand(4)); // Rt
2919 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
2920 TmpInst.addOperand(Inst.getOperand(1)); // Rn
2921 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
2922 TmpInst.addOperand(MCOperand::CreateImm(4));
2923 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
2924 TmpInst.addOperand(Inst.getOperand(3));
2928 case ARM::STMDB_UPD:
2929 // If this is a store of a single register via a 'push', then we should use
2930 // a pre-indexed STR instruction instead, per the ARM ARM.
2931 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
2932 Inst.getNumOperands() == 5) {
2934 TmpInst.setOpcode(ARM::STR_PRE_IMM);
2935 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
2936 TmpInst.addOperand(Inst.getOperand(4)); // Rt
2937 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
2938 TmpInst.addOperand(MCOperand::CreateImm(-4));
2939 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
2940 TmpInst.addOperand(Inst.getOperand(3));
2948 MatchAndEmitInstruction(SMLoc IDLoc,
2949 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2953 MatchResultTy MatchResult;
2954 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
2955 switch (MatchResult) {
2957 // Context sensitive operand constraints aren't handled by the matcher,
2958 // so check them here.
2959 if (validateInstruction(Inst, Operands))
2962 // Some instructions need post-processing to, for example, tweak which
2963 // encoding is selected.
2964 processInstruction(Inst, Operands);
2966 Out.EmitInstruction(Inst);
2968 case Match_MissingFeature:
2969 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
2971 case Match_InvalidOperand: {
2972 SMLoc ErrorLoc = IDLoc;
2973 if (ErrorInfo != ~0U) {
2974 if (ErrorInfo >= Operands.size())
2975 return Error(IDLoc, "too few operands for instruction");
2977 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
2978 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
2981 return Error(ErrorLoc, "invalid operand for instruction");
2983 case Match_MnemonicFail:
2984 return Error(IDLoc, "unrecognized instruction mnemonic");
2985 case Match_ConversionFail:
2986 return Error(IDLoc, "unable to convert operands to instruction");
2989 llvm_unreachable("Implement any new match types added!");
2993 /// parseDirective parses the arm specific directives
2994 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
2995 StringRef IDVal = DirectiveID.getIdentifier();
2996 if (IDVal == ".word")
2997 return parseDirectiveWord(4, DirectiveID.getLoc());
2998 else if (IDVal == ".thumb")
2999 return parseDirectiveThumb(DirectiveID.getLoc());
3000 else if (IDVal == ".thumb_func")
3001 return parseDirectiveThumbFunc(DirectiveID.getLoc());
3002 else if (IDVal == ".code")
3003 return parseDirectiveCode(DirectiveID.getLoc());
3004 else if (IDVal == ".syntax")
3005 return parseDirectiveSyntax(DirectiveID.getLoc());
3009 /// parseDirectiveWord
3010 /// ::= .word [ expression (, expression)* ]
3011 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
3012 if (getLexer().isNot(AsmToken::EndOfStatement)) {
3014 const MCExpr *Value;
3015 if (getParser().ParseExpression(Value))
3018 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
3020 if (getLexer().is(AsmToken::EndOfStatement))
3023 // FIXME: Improve diagnostic.
3024 if (getLexer().isNot(AsmToken::Comma))
3025 return Error(L, "unexpected token in directive");
3034 /// parseDirectiveThumb
3036 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
3037 if (getLexer().isNot(AsmToken::EndOfStatement))
3038 return Error(L, "unexpected token in directive");
3041 // TODO: set thumb mode
3042 // TODO: tell the MC streamer the mode
3043 // getParser().getStreamer().Emit???();
3047 /// parseDirectiveThumbFunc
3048 /// ::= .thumbfunc symbol_name
3049 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
3050 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
3051 bool isMachO = MAI.hasSubsectionsViaSymbols();
3054 // Darwin asm has function name after .thumb_func direction
3057 const AsmToken &Tok = Parser.getTok();
3058 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
3059 return Error(L, "unexpected token in .thumb_func directive");
3060 Name = Tok.getString();
3061 Parser.Lex(); // Consume the identifier token.
3064 if (getLexer().isNot(AsmToken::EndOfStatement))
3065 return Error(L, "unexpected token in directive");
3068 // FIXME: assuming function name will be the line following .thumb_func
3070 Name = Parser.getTok().getString();
3073 // Mark symbol as a thumb symbol.
3074 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
3075 getParser().getStreamer().EmitThumbFunc(Func);
3079 /// parseDirectiveSyntax
3080 /// ::= .syntax unified | divided
3081 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
3082 const AsmToken &Tok = Parser.getTok();
3083 if (Tok.isNot(AsmToken::Identifier))
3084 return Error(L, "unexpected token in .syntax directive");
3085 StringRef Mode = Tok.getString();
3086 if (Mode == "unified" || Mode == "UNIFIED")
3088 else if (Mode == "divided" || Mode == "DIVIDED")
3089 return Error(L, "'.syntax divided' arm asssembly not supported");
3091 return Error(L, "unrecognized syntax mode in .syntax directive");
3093 if (getLexer().isNot(AsmToken::EndOfStatement))
3094 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3097 // TODO tell the MC streamer the mode
3098 // getParser().getStreamer().Emit???();
3102 /// parseDirectiveCode
3103 /// ::= .code 16 | 32
3104 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
3105 const AsmToken &Tok = Parser.getTok();
3106 if (Tok.isNot(AsmToken::Integer))
3107 return Error(L, "unexpected token in .code directive");
3108 int64_t Val = Parser.getTok().getIntVal();
3114 return Error(L, "invalid operand to .code directive");
3116 if (getLexer().isNot(AsmToken::EndOfStatement))
3117 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3123 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
3128 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
3135 extern "C" void LLVMInitializeARMAsmLexer();
3137 /// Force static initialization.
3138 extern "C" void LLVMInitializeARMAsmParser() {
3139 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
3140 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
3141 LLVMInitializeARMAsmLexer();
3144 #define GET_REGISTER_MATCHER
3145 #define GET_MATCHER_IMPLEMENTATION
3146 #include "ARMGenAsmMatcher.inc"