1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "ARMFPUName.h"
11 #include "ARMFeatures.h"
12 #include "MCTargetDesc/ARMAddressingModes.h"
13 #include "MCTargetDesc/ARMArchName.h"
14 #include "MCTargetDesc/ARMBaseInfo.h"
15 #include "MCTargetDesc/ARMMCExpr.h"
16 #include "llvm/ADT/OwningPtr.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/StringExtras.h"
20 #include "llvm/ADT/StringSwitch.h"
21 #include "llvm/ADT/Twine.h"
22 #include "llvm/MC/MCAsmInfo.h"
23 #include "llvm/MC/MCAssembler.h"
24 #include "llvm/MC/MCContext.h"
25 #include "llvm/MC/MCDisassembler.h"
26 #include "llvm/MC/MCELF.h"
27 #include "llvm/MC/MCELFStreamer.h"
28 #include "llvm/MC/MCELFSymbolFlags.h"
29 #include "llvm/MC/MCExpr.h"
30 #include "llvm/MC/MCInst.h"
31 #include "llvm/MC/MCInstrDesc.h"
32 #include "llvm/MC/MCInstrInfo.h"
33 #include "llvm/MC/MCObjectFileInfo.h"
34 #include "llvm/MC/MCParser/MCAsmLexer.h"
35 #include "llvm/MC/MCParser/MCAsmParser.h"
36 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
37 #include "llvm/MC/MCRegisterInfo.h"
38 #include "llvm/MC/MCSection.h"
39 #include "llvm/MC/MCStreamer.h"
40 #include "llvm/MC/MCSubtargetInfo.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/MC/MCTargetAsmParser.h"
43 #include "llvm/Support/ARMBuildAttributes.h"
44 #include "llvm/Support/ARMEHABI.h"
45 #include "llvm/Support/COFF.h"
46 #include "llvm/Support/Debug.h"
47 #include "llvm/Support/ELF.h"
48 #include "llvm/Support/MathExtras.h"
49 #include "llvm/Support/SourceMgr.h"
50 #include "llvm/Support/TargetRegistry.h"
51 #include "llvm/Support/raw_ostream.h"
59 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
64 typedef SmallVector<SMLoc, 4> Locs;
69 Locs PersonalityIndexLocs;
74 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
76 bool hasFnStart() const { return !FnStartLocs.empty(); }
77 bool cantUnwind() const { return !CantUnwindLocs.empty(); }
78 bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
79 bool hasPersonality() const {
80 return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
83 void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
84 void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
85 void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
86 void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
87 void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
89 void saveFPReg(int Reg) { FPReg = Reg; }
90 int getFPReg() const { return FPReg; }
92 void emitFnStartLocNotes() const {
93 for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
95 Parser.Note(*FI, ".fnstart was specified here");
97 void emitCantUnwindLocNotes() const {
98 for (Locs::const_iterator UI = CantUnwindLocs.begin(),
99 UE = CantUnwindLocs.end(); UI != UE; ++UI)
100 Parser.Note(*UI, ".cantunwind was specified here");
102 void emitHandlerDataLocNotes() const {
103 for (Locs::const_iterator HI = HandlerDataLocs.begin(),
104 HE = HandlerDataLocs.end(); HI != HE; ++HI)
105 Parser.Note(*HI, ".handlerdata was specified here");
107 void emitPersonalityLocNotes() const {
108 for (Locs::const_iterator PI = PersonalityLocs.begin(),
109 PE = PersonalityLocs.end(),
110 PII = PersonalityIndexLocs.begin(),
111 PIE = PersonalityIndexLocs.end();
112 PI != PE || PII != PIE;) {
113 if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
114 Parser.Note(*PI++, ".personality was specified here");
115 else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
116 Parser.Note(*PII++, ".personalityindex was specified here");
118 llvm_unreachable(".personality and .personalityindex cannot be "
119 "at the same location");
124 FnStartLocs = Locs();
125 CantUnwindLocs = Locs();
126 PersonalityLocs = Locs();
127 HandlerDataLocs = Locs();
128 PersonalityIndexLocs = Locs();
133 class ARMAsmParser : public MCTargetAsmParser {
134 MCSubtargetInfo &STI;
136 const MCInstrInfo &MII;
137 const MCRegisterInfo *MRI;
140 ARMTargetStreamer &getTargetStreamer() {
141 MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
142 return static_cast<ARMTargetStreamer &>(TS);
145 // Map of register aliases registers via the .req directive.
146 StringMap<unsigned> RegisterReqs;
148 bool NextSymbolIsThumb;
151 ARMCC::CondCodes Cond; // Condition for IT block.
152 unsigned Mask:4; // Condition mask for instructions.
153 // Starting at first 1 (from lsb).
154 // '1' condition as indicated in IT.
155 // '0' inverse of condition (else).
156 // Count of instructions in IT block is
157 // 4 - trailingzeroes(mask)
159 bool FirstCond; // Explicit flag for when we're parsing the
160 // First instruction in the IT block. It's
161 // implied in the mask, so needs special
164 unsigned CurPosition; // Current position in parsing of IT
165 // block. In range [0,3]. Initialized
166 // according to count of instructions in block.
167 // ~0U if no active IT block.
169 bool inITBlock() { return ITState.CurPosition != ~0U;}
170 void forwardITPosition() {
171 if (!inITBlock()) return;
172 // Move to the next instruction in the IT block, if there is one. If not,
173 // mark the block as done.
174 unsigned TZ = countTrailingZeros(ITState.Mask);
175 if (++ITState.CurPosition == 5 - TZ)
176 ITState.CurPosition = ~0U; // Done with the IT block after this.
180 MCAsmParser &getParser() const { return Parser; }
181 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
183 void Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges = None) {
184 return Parser.Note(L, Msg, Ranges);
186 bool Warning(SMLoc L, const Twine &Msg,
187 ArrayRef<SMRange> Ranges = None) {
188 return Parser.Warning(L, Msg, Ranges);
190 bool Error(SMLoc L, const Twine &Msg,
191 ArrayRef<SMRange> Ranges = None) {
192 return Parser.Error(L, Msg, Ranges);
195 int tryParseRegister();
196 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
197 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
198 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
199 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
200 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
201 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
202 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
203 unsigned &ShiftAmount);
204 bool parseLiteralValues(unsigned Size, SMLoc L);
205 bool parseDirectiveThumb(SMLoc L);
206 bool parseDirectiveARM(SMLoc L);
207 bool parseDirectiveThumbFunc(SMLoc L);
208 bool parseDirectiveCode(SMLoc L);
209 bool parseDirectiveSyntax(SMLoc L);
210 bool parseDirectiveReq(StringRef Name, SMLoc L);
211 bool parseDirectiveUnreq(SMLoc L);
212 bool parseDirectiveArch(SMLoc L);
213 bool parseDirectiveEabiAttr(SMLoc L);
214 bool parseDirectiveCPU(SMLoc L);
215 bool parseDirectiveFPU(SMLoc L);
216 bool parseDirectiveFnStart(SMLoc L);
217 bool parseDirectiveFnEnd(SMLoc L);
218 bool parseDirectiveCantUnwind(SMLoc L);
219 bool parseDirectivePersonality(SMLoc L);
220 bool parseDirectiveHandlerData(SMLoc L);
221 bool parseDirectiveSetFP(SMLoc L);
222 bool parseDirectivePad(SMLoc L);
223 bool parseDirectiveRegSave(SMLoc L, bool IsVector);
224 bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
225 bool parseDirectiveLtorg(SMLoc L);
226 bool parseDirectiveEven(SMLoc L);
227 bool parseDirectivePersonalityIndex(SMLoc L);
228 bool parseDirectiveUnwindRaw(SMLoc L);
229 bool parseDirectiveTLSDescSeq(SMLoc L);
230 bool parseDirectiveMovSP(SMLoc L);
231 bool parseDirectiveObjectArch(SMLoc L);
232 bool parseDirectiveArchExtension(SMLoc L);
233 bool parseDirectiveAlign(SMLoc L);
234 bool parseDirectiveThumbSet(SMLoc L);
236 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
237 bool &CarrySetting, unsigned &ProcessorIMod,
239 void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
240 bool &CanAcceptCarrySet,
241 bool &CanAcceptPredicationCode);
243 bool isThumb() const {
244 // FIXME: Can tablegen auto-generate this?
245 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
247 bool isThumbOne() const {
248 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
250 bool isThumbTwo() const {
251 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
253 bool hasThumb() const {
254 return STI.getFeatureBits() & ARM::HasV4TOps;
256 bool hasV6Ops() const {
257 return STI.getFeatureBits() & ARM::HasV6Ops;
259 bool hasV6MOps() const {
260 return STI.getFeatureBits() & ARM::HasV6MOps;
262 bool hasV7Ops() const {
263 return STI.getFeatureBits() & ARM::HasV7Ops;
265 bool hasV8Ops() const {
266 return STI.getFeatureBits() & ARM::HasV8Ops;
268 bool hasARM() const {
269 return !(STI.getFeatureBits() & ARM::FeatureNoARM);
273 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
274 setAvailableFeatures(FB);
276 bool isMClass() const {
277 return STI.getFeatureBits() & ARM::FeatureMClass;
280 /// @name Auto-generated Match Functions
283 #define GET_ASSEMBLER_HEADER
284 #include "ARMGenAsmMatcher.inc"
288 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
289 OperandMatchResultTy parseCoprocNumOperand(
290 SmallVectorImpl<MCParsedAsmOperand*>&);
291 OperandMatchResultTy parseCoprocRegOperand(
292 SmallVectorImpl<MCParsedAsmOperand*>&);
293 OperandMatchResultTy parseCoprocOptionOperand(
294 SmallVectorImpl<MCParsedAsmOperand*>&);
295 OperandMatchResultTy parseMemBarrierOptOperand(
296 SmallVectorImpl<MCParsedAsmOperand*>&);
297 OperandMatchResultTy parseInstSyncBarrierOptOperand(
298 SmallVectorImpl<MCParsedAsmOperand*>&);
299 OperandMatchResultTy parseProcIFlagsOperand(
300 SmallVectorImpl<MCParsedAsmOperand*>&);
301 OperandMatchResultTy parseMSRMaskOperand(
302 SmallVectorImpl<MCParsedAsmOperand*>&);
303 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
304 StringRef Op, int Low, int High);
305 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
306 return parsePKHImm(O, "lsl", 0, 31);
308 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
309 return parsePKHImm(O, "asr", 1, 32);
311 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
312 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
313 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
314 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
315 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
316 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
317 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
318 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
319 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
322 // Asm Match Converter Methods
323 void cvtThumbMultiply(MCInst &Inst,
324 const SmallVectorImpl<MCParsedAsmOperand*> &);
325 void cvtThumbBranches(MCInst &Inst,
326 const SmallVectorImpl<MCParsedAsmOperand*> &);
328 bool validateInstruction(MCInst &Inst,
329 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
330 bool processInstruction(MCInst &Inst,
331 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
332 bool shouldOmitCCOutOperand(StringRef Mnemonic,
333 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
334 bool shouldOmitPredicateOperand(StringRef Mnemonic,
335 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
337 enum ARMMatchResultTy {
338 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
339 Match_RequiresNotITBlock,
341 Match_RequiresThumb2,
342 #define GET_OPERAND_DIAGNOSTIC_TYPES
343 #include "ARMGenAsmMatcher.inc"
347 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
348 const MCInstrInfo &MII)
349 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(MII), UC(_Parser) {
350 MCAsmParserExtension::Initialize(_Parser);
352 // Cache the MCRegisterInfo.
353 MRI = getContext().getRegisterInfo();
355 // Initialize the set of available features.
356 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
358 // Not in an ITBlock to start with.
359 ITState.CurPosition = ~0U;
361 NextSymbolIsThumb = false;
364 // Implementation of the MCTargetAsmParser interface:
365 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
367 ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
369 SmallVectorImpl<MCParsedAsmOperand*> &Operands) override;
370 bool ParseDirective(AsmToken DirectiveID) override;
372 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op,
373 unsigned Kind) override;
374 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
376 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
377 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
378 MCStreamer &Out, unsigned &ErrorInfo,
379 bool MatchingInlineAsm) override;
380 void onLabelParsed(MCSymbol *Symbol) override;
382 } // end anonymous namespace
386 /// ARMOperand - Instances of this class represent a parsed ARM machine
388 class ARMOperand : public MCParsedAsmOperand {
398 k_InstSyncBarrierOpt,
409 k_VectorListAllLanes,
415 k_BitfieldDescriptor,
419 SMLoc StartLoc, EndLoc;
420 SmallVector<unsigned, 8> Registers;
423 ARMCC::CondCodes Val;
430 struct CoprocOptionOp {
443 ARM_ISB::InstSyncBOpt Val;
447 ARM_PROC::IFlags Val;
463 // A vector register list is a sequential list of 1 to 4 registers.
464 struct VectorListOp {
471 struct VectorIndexOp {
479 /// Combined record for all forms of ARM address expressions.
482 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
484 const MCConstantExpr *OffsetImm; // Offset immediate value
485 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
486 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
487 unsigned ShiftImm; // shift for OffsetReg.
488 unsigned Alignment; // 0 = no alignment specified
489 // n = alignment in bytes (2, 4, 8, 16, or 32)
490 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
493 struct PostIdxRegOp {
496 ARM_AM::ShiftOpc ShiftTy;
500 struct ShifterImmOp {
505 struct RegShiftedRegOp {
506 ARM_AM::ShiftOpc ShiftTy;
512 struct RegShiftedImmOp {
513 ARM_AM::ShiftOpc ShiftTy;
530 struct CoprocOptionOp CoprocOption;
531 struct MBOptOp MBOpt;
532 struct ISBOptOp ISBOpt;
533 struct ITMaskOp ITMask;
534 struct IFlagsOp IFlags;
535 struct MMaskOp MMask;
538 struct VectorListOp VectorList;
539 struct VectorIndexOp VectorIndex;
541 struct MemoryOp Memory;
542 struct PostIdxRegOp PostIdxReg;
543 struct ShifterImmOp ShifterImm;
544 struct RegShiftedRegOp RegShiftedReg;
545 struct RegShiftedImmOp RegShiftedImm;
546 struct RotImmOp RotImm;
547 struct BitfieldOp Bitfield;
550 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
552 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
554 StartLoc = o.StartLoc;
571 case k_DPRRegisterList:
572 case k_SPRRegisterList:
573 Registers = o.Registers;
576 case k_VectorListAllLanes:
577 case k_VectorListIndexed:
578 VectorList = o.VectorList;
585 CoprocOption = o.CoprocOption;
590 case k_MemBarrierOpt:
593 case k_InstSyncBarrierOpt:
598 case k_PostIndexRegister:
599 PostIdxReg = o.PostIdxReg;
607 case k_ShifterImmediate:
608 ShifterImm = o.ShifterImm;
610 case k_ShiftedRegister:
611 RegShiftedReg = o.RegShiftedReg;
613 case k_ShiftedImmediate:
614 RegShiftedImm = o.RegShiftedImm;
616 case k_RotateImmediate:
619 case k_BitfieldDescriptor:
620 Bitfield = o.Bitfield;
623 VectorIndex = o.VectorIndex;
628 /// getStartLoc - Get the location of the first token of this operand.
629 SMLoc getStartLoc() const override { return StartLoc; }
630 /// getEndLoc - Get the location of the last token of this operand.
631 SMLoc getEndLoc() const override { return EndLoc; }
632 /// getLocRange - Get the range between the first and last token of this
634 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
636 ARMCC::CondCodes getCondCode() const {
637 assert(Kind == k_CondCode && "Invalid access!");
641 unsigned getCoproc() const {
642 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
646 StringRef getToken() const {
647 assert(Kind == k_Token && "Invalid access!");
648 return StringRef(Tok.Data, Tok.Length);
651 unsigned getReg() const override {
652 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
656 const SmallVectorImpl<unsigned> &getRegList() const {
657 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
658 Kind == k_SPRRegisterList) && "Invalid access!");
662 const MCExpr *getImm() const {
663 assert(isImm() && "Invalid access!");
667 unsigned getVectorIndex() const {
668 assert(Kind == k_VectorIndex && "Invalid access!");
669 return VectorIndex.Val;
672 ARM_MB::MemBOpt getMemBarrierOpt() const {
673 assert(Kind == k_MemBarrierOpt && "Invalid access!");
677 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
678 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
682 ARM_PROC::IFlags getProcIFlags() const {
683 assert(Kind == k_ProcIFlags && "Invalid access!");
687 unsigned getMSRMask() const {
688 assert(Kind == k_MSRMask && "Invalid access!");
692 bool isCoprocNum() const { return Kind == k_CoprocNum; }
693 bool isCoprocReg() const { return Kind == k_CoprocReg; }
694 bool isCoprocOption() const { return Kind == k_CoprocOption; }
695 bool isCondCode() const { return Kind == k_CondCode; }
696 bool isCCOut() const { return Kind == k_CCOut; }
697 bool isITMask() const { return Kind == k_ITCondMask; }
698 bool isITCondCode() const { return Kind == k_CondCode; }
699 bool isImm() const override { return Kind == k_Immediate; }
700 // checks whether this operand is an unsigned offset which fits is a field
701 // of specified width and scaled by a specific number of bits
702 template<unsigned width, unsigned scale>
703 bool isUnsignedOffset() const {
704 if (!isImm()) return false;
705 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
706 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
707 int64_t Val = CE->getValue();
708 int64_t Align = 1LL << scale;
709 int64_t Max = Align * ((1LL << width) - 1);
710 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
714 // checks whether this operand is an signed offset which fits is a field
715 // of specified width and scaled by a specific number of bits
716 template<unsigned width, unsigned scale>
717 bool isSignedOffset() const {
718 if (!isImm()) return false;
719 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
720 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
721 int64_t Val = CE->getValue();
722 int64_t Align = 1LL << scale;
723 int64_t Max = Align * ((1LL << (width-1)) - 1);
724 int64_t Min = -Align * (1LL << (width-1));
725 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
730 // checks whether this operand is a memory operand computed as an offset
731 // applied to PC. the offset may have 8 bits of magnitude and is represented
732 // with two bits of shift. textually it may be either [pc, #imm], #imm or
733 // relocable expression...
734 bool isThumbMemPC() const {
737 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
738 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
739 if (!CE) return false;
740 Val = CE->getValue();
743 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
744 if(Memory.BaseRegNum != ARM::PC) return false;
745 Val = Memory.OffsetImm->getValue();
748 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
750 bool isFPImm() const {
751 if (!isImm()) return false;
752 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
753 if (!CE) return false;
754 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
757 bool isFBits16() const {
758 if (!isImm()) return false;
759 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
760 if (!CE) return false;
761 int64_t Value = CE->getValue();
762 return Value >= 0 && Value <= 16;
764 bool isFBits32() const {
765 if (!isImm()) return false;
766 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
767 if (!CE) return false;
768 int64_t Value = CE->getValue();
769 return Value >= 1 && Value <= 32;
771 bool isImm8s4() const {
772 if (!isImm()) return false;
773 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
774 if (!CE) return false;
775 int64_t Value = CE->getValue();
776 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
778 bool isImm0_1020s4() const {
779 if (!isImm()) return false;
780 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
781 if (!CE) return false;
782 int64_t Value = CE->getValue();
783 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
785 bool isImm0_508s4() const {
786 if (!isImm()) return false;
787 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
788 if (!CE) return false;
789 int64_t Value = CE->getValue();
790 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
792 bool isImm0_508s4Neg() const {
793 if (!isImm()) return false;
794 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
795 if (!CE) return false;
796 int64_t Value = -CE->getValue();
797 // explicitly exclude zero. we want that to use the normal 0_508 version.
798 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
800 bool isImm0_239() const {
801 if (!isImm()) return false;
802 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
803 if (!CE) return false;
804 int64_t Value = CE->getValue();
805 return Value >= 0 && Value < 240;
807 bool isImm0_255() const {
808 if (!isImm()) return false;
809 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
810 if (!CE) return false;
811 int64_t Value = CE->getValue();
812 return Value >= 0 && Value < 256;
814 bool isImm0_4095() const {
815 if (!isImm()) return false;
816 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
817 if (!CE) return false;
818 int64_t Value = CE->getValue();
819 return Value >= 0 && Value < 4096;
821 bool isImm0_4095Neg() const {
822 if (!isImm()) return false;
823 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
824 if (!CE) return false;
825 int64_t Value = -CE->getValue();
826 return Value > 0 && Value < 4096;
828 bool isImm0_1() const {
829 if (!isImm()) return false;
830 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
831 if (!CE) return false;
832 int64_t Value = CE->getValue();
833 return Value >= 0 && Value < 2;
835 bool isImm0_3() const {
836 if (!isImm()) return false;
837 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
838 if (!CE) return false;
839 int64_t Value = CE->getValue();
840 return Value >= 0 && Value < 4;
842 bool isImm0_7() const {
843 if (!isImm()) return false;
844 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
845 if (!CE) return false;
846 int64_t Value = CE->getValue();
847 return Value >= 0 && Value < 8;
849 bool isImm0_15() const {
850 if (!isImm()) return false;
851 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
852 if (!CE) return false;
853 int64_t Value = CE->getValue();
854 return Value >= 0 && Value < 16;
856 bool isImm0_31() const {
857 if (!isImm()) return false;
858 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
859 if (!CE) return false;
860 int64_t Value = CE->getValue();
861 return Value >= 0 && Value < 32;
863 bool isImm0_63() const {
864 if (!isImm()) return false;
865 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
866 if (!CE) return false;
867 int64_t Value = CE->getValue();
868 return Value >= 0 && Value < 64;
870 bool isImm8() const {
871 if (!isImm()) return false;
872 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
873 if (!CE) return false;
874 int64_t Value = CE->getValue();
877 bool isImm16() const {
878 if (!isImm()) return false;
879 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
880 if (!CE) return false;
881 int64_t Value = CE->getValue();
884 bool isImm32() const {
885 if (!isImm()) return false;
886 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
887 if (!CE) return false;
888 int64_t Value = CE->getValue();
891 bool isShrImm8() const {
892 if (!isImm()) return false;
893 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
894 if (!CE) return false;
895 int64_t Value = CE->getValue();
896 return Value > 0 && Value <= 8;
898 bool isShrImm16() const {
899 if (!isImm()) return false;
900 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
901 if (!CE) return false;
902 int64_t Value = CE->getValue();
903 return Value > 0 && Value <= 16;
905 bool isShrImm32() const {
906 if (!isImm()) return false;
907 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
908 if (!CE) return false;
909 int64_t Value = CE->getValue();
910 return Value > 0 && Value <= 32;
912 bool isShrImm64() const {
913 if (!isImm()) return false;
914 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
915 if (!CE) return false;
916 int64_t Value = CE->getValue();
917 return Value > 0 && Value <= 64;
919 bool isImm1_7() const {
920 if (!isImm()) return false;
921 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
922 if (!CE) return false;
923 int64_t Value = CE->getValue();
924 return Value > 0 && Value < 8;
926 bool isImm1_15() const {
927 if (!isImm()) return false;
928 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
929 if (!CE) return false;
930 int64_t Value = CE->getValue();
931 return Value > 0 && Value < 16;
933 bool isImm1_31() const {
934 if (!isImm()) return false;
935 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
936 if (!CE) return false;
937 int64_t Value = CE->getValue();
938 return Value > 0 && Value < 32;
940 bool isImm1_16() const {
941 if (!isImm()) return false;
942 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
943 if (!CE) return false;
944 int64_t Value = CE->getValue();
945 return Value > 0 && Value < 17;
947 bool isImm1_32() const {
948 if (!isImm()) return false;
949 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
950 if (!CE) return false;
951 int64_t Value = CE->getValue();
952 return Value > 0 && Value < 33;
954 bool isImm0_32() const {
955 if (!isImm()) return false;
956 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
957 if (!CE) return false;
958 int64_t Value = CE->getValue();
959 return Value >= 0 && Value < 33;
961 bool isImm0_65535() const {
962 if (!isImm()) return false;
963 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
964 if (!CE) return false;
965 int64_t Value = CE->getValue();
966 return Value >= 0 && Value < 65536;
968 bool isImm256_65535Expr() const {
969 if (!isImm()) return false;
970 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
971 // If it's not a constant expression, it'll generate a fixup and be
973 if (!CE) return true;
974 int64_t Value = CE->getValue();
975 return Value >= 256 && Value < 65536;
977 bool isImm0_65535Expr() const {
978 if (!isImm()) return false;
979 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
980 // If it's not a constant expression, it'll generate a fixup and be
982 if (!CE) return true;
983 int64_t Value = CE->getValue();
984 return Value >= 0 && Value < 65536;
986 bool isImm24bit() const {
987 if (!isImm()) return false;
988 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
989 if (!CE) return false;
990 int64_t Value = CE->getValue();
991 return Value >= 0 && Value <= 0xffffff;
993 bool isImmThumbSR() const {
994 if (!isImm()) return false;
995 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
996 if (!CE) return false;
997 int64_t Value = CE->getValue();
998 return Value > 0 && Value < 33;
1000 bool isPKHLSLImm() const {
1001 if (!isImm()) return false;
1002 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1003 if (!CE) return false;
1004 int64_t Value = CE->getValue();
1005 return Value >= 0 && Value < 32;
1007 bool isPKHASRImm() const {
1008 if (!isImm()) return false;
1009 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1010 if (!CE) return false;
1011 int64_t Value = CE->getValue();
1012 return Value > 0 && Value <= 32;
1014 bool isAdrLabel() const {
1015 // If we have an immediate that's not a constant, treat it as a label
1016 // reference needing a fixup. If it is a constant, but it can't fit
1017 // into shift immediate encoding, we reject it.
1018 if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
1019 else return (isARMSOImm() || isARMSOImmNeg());
1021 bool isARMSOImm() const {
1022 if (!isImm()) return false;
1023 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1024 if (!CE) return false;
1025 int64_t Value = CE->getValue();
1026 return ARM_AM::getSOImmVal(Value) != -1;
1028 bool isARMSOImmNot() const {
1029 if (!isImm()) return false;
1030 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1031 if (!CE) return false;
1032 int64_t Value = CE->getValue();
1033 return ARM_AM::getSOImmVal(~Value) != -1;
1035 bool isARMSOImmNeg() const {
1036 if (!isImm()) return false;
1037 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1038 if (!CE) return false;
1039 int64_t Value = CE->getValue();
1040 // Only use this when not representable as a plain so_imm.
1041 return ARM_AM::getSOImmVal(Value) == -1 &&
1042 ARM_AM::getSOImmVal(-Value) != -1;
1044 bool isT2SOImm() const {
1045 if (!isImm()) return false;
1046 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1047 if (!CE) return false;
1048 int64_t Value = CE->getValue();
1049 return ARM_AM::getT2SOImmVal(Value) != -1;
1051 bool isT2SOImmNot() const {
1052 if (!isImm()) return false;
1053 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1054 if (!CE) return false;
1055 int64_t Value = CE->getValue();
1056 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1057 ARM_AM::getT2SOImmVal(~Value) != -1;
1059 bool isT2SOImmNeg() const {
1060 if (!isImm()) return false;
1061 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1062 if (!CE) return false;
1063 int64_t Value = CE->getValue();
1064 // Only use this when not representable as a plain so_imm.
1065 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1066 ARM_AM::getT2SOImmVal(-Value) != -1;
1068 bool isSetEndImm() const {
1069 if (!isImm()) return false;
1070 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1071 if (!CE) return false;
1072 int64_t Value = CE->getValue();
1073 return Value == 1 || Value == 0;
1075 bool isReg() const override { return Kind == k_Register; }
1076 bool isRegList() const { return Kind == k_RegisterList; }
1077 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1078 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1079 bool isToken() const override { return Kind == k_Token; }
1080 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1081 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1082 bool isMem() const override { return Kind == k_Memory; }
1083 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1084 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
1085 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
1086 bool isRotImm() const { return Kind == k_RotateImmediate; }
1087 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1088 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
1089 bool isPostIdxReg() const {
1090 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
1092 bool isMemNoOffset(bool alignOK = false) const {
1095 // No offset of any kind.
1096 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
1097 (alignOK || Memory.Alignment == 0);
1099 bool isMemPCRelImm12() const {
1100 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1102 // Base register must be PC.
1103 if (Memory.BaseRegNum != ARM::PC)
1105 // Immediate offset in range [-4095, 4095].
1106 if (!Memory.OffsetImm) return true;
1107 int64_t Val = Memory.OffsetImm->getValue();
1108 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1110 bool isAlignedMemory() const {
1111 return isMemNoOffset(true);
1113 bool isAddrMode2() const {
1114 if (!isMem() || Memory.Alignment != 0) return false;
1115 // Check for register offset.
1116 if (Memory.OffsetRegNum) return true;
1117 // Immediate offset in range [-4095, 4095].
1118 if (!Memory.OffsetImm) return true;
1119 int64_t Val = Memory.OffsetImm->getValue();
1120 return Val > -4096 && Val < 4096;
1122 bool isAM2OffsetImm() const {
1123 if (!isImm()) return false;
1124 // Immediate offset in range [-4095, 4095].
1125 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1126 if (!CE) return false;
1127 int64_t Val = CE->getValue();
1128 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1130 bool isAddrMode3() const {
1131 // If we have an immediate that's not a constant, treat it as a label
1132 // reference needing a fixup. If it is a constant, it's something else
1133 // and we reject it.
1134 if (isImm() && !isa<MCConstantExpr>(getImm()))
1136 if (!isMem() || Memory.Alignment != 0) return false;
1137 // No shifts are legal for AM3.
1138 if (Memory.ShiftType != ARM_AM::no_shift) return false;
1139 // Check for register offset.
1140 if (Memory.OffsetRegNum) return true;
1141 // Immediate offset in range [-255, 255].
1142 if (!Memory.OffsetImm) return true;
1143 int64_t Val = Memory.OffsetImm->getValue();
1144 // The #-0 offset is encoded as INT32_MIN, and we have to check
1146 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1148 bool isAM3Offset() const {
1149 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1151 if (Kind == k_PostIndexRegister)
1152 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1153 // Immediate offset in range [-255, 255].
1154 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1155 if (!CE) return false;
1156 int64_t Val = CE->getValue();
1157 // Special case, #-0 is INT32_MIN.
1158 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1160 bool isAddrMode5() const {
1161 // If we have an immediate that's not a constant, treat it as a label
1162 // reference needing a fixup. If it is a constant, it's something else
1163 // and we reject it.
1164 if (isImm() && !isa<MCConstantExpr>(getImm()))
1166 if (!isMem() || Memory.Alignment != 0) return false;
1167 // Check for register offset.
1168 if (Memory.OffsetRegNum) return false;
1169 // Immediate offset in range [-1020, 1020] and a multiple of 4.
1170 if (!Memory.OffsetImm) return true;
1171 int64_t Val = Memory.OffsetImm->getValue();
1172 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1175 bool isMemTBB() const {
1176 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1177 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1181 bool isMemTBH() const {
1182 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1183 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1184 Memory.Alignment != 0 )
1188 bool isMemRegOffset() const {
1189 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1193 bool isT2MemRegOffset() const {
1194 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1195 Memory.Alignment != 0)
1197 // Only lsl #{0, 1, 2, 3} allowed.
1198 if (Memory.ShiftType == ARM_AM::no_shift)
1200 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1204 bool isMemThumbRR() const {
1205 // Thumb reg+reg addressing is simple. Just two registers, a base and
1206 // an offset. No shifts, negations or any other complicating factors.
1207 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1208 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1210 return isARMLowRegister(Memory.BaseRegNum) &&
1211 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1213 bool isMemThumbRIs4() const {
1214 if (!isMem() || Memory.OffsetRegNum != 0 ||
1215 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1217 // Immediate offset, multiple of 4 in range [0, 124].
1218 if (!Memory.OffsetImm) return true;
1219 int64_t Val = Memory.OffsetImm->getValue();
1220 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1222 bool isMemThumbRIs2() const {
1223 if (!isMem() || Memory.OffsetRegNum != 0 ||
1224 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1226 // Immediate offset, multiple of 4 in range [0, 62].
1227 if (!Memory.OffsetImm) return true;
1228 int64_t Val = Memory.OffsetImm->getValue();
1229 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1231 bool isMemThumbRIs1() const {
1232 if (!isMem() || Memory.OffsetRegNum != 0 ||
1233 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1235 // Immediate offset in range [0, 31].
1236 if (!Memory.OffsetImm) return true;
1237 int64_t Val = Memory.OffsetImm->getValue();
1238 return Val >= 0 && Val <= 31;
1240 bool isMemThumbSPI() const {
1241 if (!isMem() || Memory.OffsetRegNum != 0 ||
1242 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1244 // Immediate offset, multiple of 4 in range [0, 1020].
1245 if (!Memory.OffsetImm) return true;
1246 int64_t Val = Memory.OffsetImm->getValue();
1247 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1249 bool isMemImm8s4Offset() const {
1250 // If we have an immediate that's not a constant, treat it as a label
1251 // reference needing a fixup. If it is a constant, it's something else
1252 // and we reject it.
1253 if (isImm() && !isa<MCConstantExpr>(getImm()))
1255 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1257 // Immediate offset a multiple of 4 in range [-1020, 1020].
1258 if (!Memory.OffsetImm) return true;
1259 int64_t Val = Memory.OffsetImm->getValue();
1260 // Special case, #-0 is INT32_MIN.
1261 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1263 bool isMemImm0_1020s4Offset() const {
1264 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1266 // Immediate offset a multiple of 4 in range [0, 1020].
1267 if (!Memory.OffsetImm) return true;
1268 int64_t Val = Memory.OffsetImm->getValue();
1269 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1271 bool isMemImm8Offset() const {
1272 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1274 // Base reg of PC isn't allowed for these encodings.
1275 if (Memory.BaseRegNum == ARM::PC) return false;
1276 // Immediate offset in range [-255, 255].
1277 if (!Memory.OffsetImm) return true;
1278 int64_t Val = Memory.OffsetImm->getValue();
1279 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1281 bool isMemPosImm8Offset() const {
1282 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1284 // Immediate offset in range [0, 255].
1285 if (!Memory.OffsetImm) return true;
1286 int64_t Val = Memory.OffsetImm->getValue();
1287 return Val >= 0 && Val < 256;
1289 bool isMemNegImm8Offset() const {
1290 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1292 // Base reg of PC isn't allowed for these encodings.
1293 if (Memory.BaseRegNum == ARM::PC) return false;
1294 // Immediate offset in range [-255, -1].
1295 if (!Memory.OffsetImm) return false;
1296 int64_t Val = Memory.OffsetImm->getValue();
1297 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1299 bool isMemUImm12Offset() const {
1300 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1302 // Immediate offset in range [0, 4095].
1303 if (!Memory.OffsetImm) return true;
1304 int64_t Val = Memory.OffsetImm->getValue();
1305 return (Val >= 0 && Val < 4096);
1307 bool isMemImm12Offset() const {
1308 // If we have an immediate that's not a constant, treat it as a label
1309 // reference needing a fixup. If it is a constant, it's something else
1310 // and we reject it.
1311 if (isImm() && !isa<MCConstantExpr>(getImm()))
1314 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1316 // Immediate offset in range [-4095, 4095].
1317 if (!Memory.OffsetImm) return true;
1318 int64_t Val = Memory.OffsetImm->getValue();
1319 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1321 bool isPostIdxImm8() const {
1322 if (!isImm()) return false;
1323 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1324 if (!CE) return false;
1325 int64_t Val = CE->getValue();
1326 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1328 bool isPostIdxImm8s4() const {
1329 if (!isImm()) return false;
1330 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1331 if (!CE) return false;
1332 int64_t Val = CE->getValue();
1333 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1337 bool isMSRMask() const { return Kind == k_MSRMask; }
1338 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1341 bool isSingleSpacedVectorList() const {
1342 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1344 bool isDoubleSpacedVectorList() const {
1345 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1347 bool isVecListOneD() const {
1348 if (!isSingleSpacedVectorList()) return false;
1349 return VectorList.Count == 1;
1352 bool isVecListDPair() const {
1353 if (!isSingleSpacedVectorList()) return false;
1354 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1355 .contains(VectorList.RegNum));
1358 bool isVecListThreeD() const {
1359 if (!isSingleSpacedVectorList()) return false;
1360 return VectorList.Count == 3;
1363 bool isVecListFourD() const {
1364 if (!isSingleSpacedVectorList()) return false;
1365 return VectorList.Count == 4;
1368 bool isVecListDPairSpaced() const {
1369 if (Kind != k_VectorList) return false;
1370 if (isSingleSpacedVectorList()) return false;
1371 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1372 .contains(VectorList.RegNum));
1375 bool isVecListThreeQ() const {
1376 if (!isDoubleSpacedVectorList()) return false;
1377 return VectorList.Count == 3;
1380 bool isVecListFourQ() const {
1381 if (!isDoubleSpacedVectorList()) return false;
1382 return VectorList.Count == 4;
1385 bool isSingleSpacedVectorAllLanes() const {
1386 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1388 bool isDoubleSpacedVectorAllLanes() const {
1389 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1391 bool isVecListOneDAllLanes() const {
1392 if (!isSingleSpacedVectorAllLanes()) return false;
1393 return VectorList.Count == 1;
1396 bool isVecListDPairAllLanes() const {
1397 if (!isSingleSpacedVectorAllLanes()) return false;
1398 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1399 .contains(VectorList.RegNum));
1402 bool isVecListDPairSpacedAllLanes() const {
1403 if (!isDoubleSpacedVectorAllLanes()) return false;
1404 return VectorList.Count == 2;
1407 bool isVecListThreeDAllLanes() const {
1408 if (!isSingleSpacedVectorAllLanes()) return false;
1409 return VectorList.Count == 3;
1412 bool isVecListThreeQAllLanes() const {
1413 if (!isDoubleSpacedVectorAllLanes()) return false;
1414 return VectorList.Count == 3;
1417 bool isVecListFourDAllLanes() const {
1418 if (!isSingleSpacedVectorAllLanes()) return false;
1419 return VectorList.Count == 4;
1422 bool isVecListFourQAllLanes() const {
1423 if (!isDoubleSpacedVectorAllLanes()) return false;
1424 return VectorList.Count == 4;
1427 bool isSingleSpacedVectorIndexed() const {
1428 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1430 bool isDoubleSpacedVectorIndexed() const {
1431 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1433 bool isVecListOneDByteIndexed() const {
1434 if (!isSingleSpacedVectorIndexed()) return false;
1435 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1438 bool isVecListOneDHWordIndexed() const {
1439 if (!isSingleSpacedVectorIndexed()) return false;
1440 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1443 bool isVecListOneDWordIndexed() const {
1444 if (!isSingleSpacedVectorIndexed()) return false;
1445 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1448 bool isVecListTwoDByteIndexed() const {
1449 if (!isSingleSpacedVectorIndexed()) return false;
1450 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1453 bool isVecListTwoDHWordIndexed() const {
1454 if (!isSingleSpacedVectorIndexed()) return false;
1455 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1458 bool isVecListTwoQWordIndexed() const {
1459 if (!isDoubleSpacedVectorIndexed()) return false;
1460 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1463 bool isVecListTwoQHWordIndexed() const {
1464 if (!isDoubleSpacedVectorIndexed()) return false;
1465 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1468 bool isVecListTwoDWordIndexed() const {
1469 if (!isSingleSpacedVectorIndexed()) return false;
1470 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1473 bool isVecListThreeDByteIndexed() const {
1474 if (!isSingleSpacedVectorIndexed()) return false;
1475 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1478 bool isVecListThreeDHWordIndexed() const {
1479 if (!isSingleSpacedVectorIndexed()) return false;
1480 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1483 bool isVecListThreeQWordIndexed() const {
1484 if (!isDoubleSpacedVectorIndexed()) return false;
1485 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1488 bool isVecListThreeQHWordIndexed() const {
1489 if (!isDoubleSpacedVectorIndexed()) return false;
1490 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1493 bool isVecListThreeDWordIndexed() const {
1494 if (!isSingleSpacedVectorIndexed()) return false;
1495 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1498 bool isVecListFourDByteIndexed() const {
1499 if (!isSingleSpacedVectorIndexed()) return false;
1500 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1503 bool isVecListFourDHWordIndexed() const {
1504 if (!isSingleSpacedVectorIndexed()) return false;
1505 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1508 bool isVecListFourQWordIndexed() const {
1509 if (!isDoubleSpacedVectorIndexed()) return false;
1510 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1513 bool isVecListFourQHWordIndexed() const {
1514 if (!isDoubleSpacedVectorIndexed()) return false;
1515 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1518 bool isVecListFourDWordIndexed() const {
1519 if (!isSingleSpacedVectorIndexed()) return false;
1520 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1523 bool isVectorIndex8() const {
1524 if (Kind != k_VectorIndex) return false;
1525 return VectorIndex.Val < 8;
1527 bool isVectorIndex16() const {
1528 if (Kind != k_VectorIndex) return false;
1529 return VectorIndex.Val < 4;
1531 bool isVectorIndex32() const {
1532 if (Kind != k_VectorIndex) return false;
1533 return VectorIndex.Val < 2;
1536 bool isNEONi8splat() const {
1537 if (!isImm()) return false;
1538 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1539 // Must be a constant.
1540 if (!CE) return false;
1541 int64_t Value = CE->getValue();
1542 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1544 return Value >= 0 && Value < 256;
1547 bool isNEONi16splat() const {
1548 if (!isImm()) return false;
1549 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1550 // Must be a constant.
1551 if (!CE) return false;
1552 int64_t Value = CE->getValue();
1553 // i16 value in the range [0,255] or [0x0100, 0xff00]
1554 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1557 bool isNEONi32splat() const {
1558 if (!isImm()) return false;
1559 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1560 // Must be a constant.
1561 if (!CE) return false;
1562 int64_t Value = CE->getValue();
1563 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1564 return (Value >= 0 && Value < 256) ||
1565 (Value >= 0x0100 && Value <= 0xff00) ||
1566 (Value >= 0x010000 && Value <= 0xff0000) ||
1567 (Value >= 0x01000000 && Value <= 0xff000000);
1570 bool isNEONi32vmov() const {
1571 if (!isImm()) return false;
1572 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1573 // Must be a constant.
1574 if (!CE) return false;
1575 int64_t Value = CE->getValue();
1576 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1577 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1578 return (Value >= 0 && Value < 256) ||
1579 (Value >= 0x0100 && Value <= 0xff00) ||
1580 (Value >= 0x010000 && Value <= 0xff0000) ||
1581 (Value >= 0x01000000 && Value <= 0xff000000) ||
1582 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1583 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1585 bool isNEONi32vmovNeg() const {
1586 if (!isImm()) return false;
1587 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1588 // Must be a constant.
1589 if (!CE) return false;
1590 int64_t Value = ~CE->getValue();
1591 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1592 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1593 return (Value >= 0 && Value < 256) ||
1594 (Value >= 0x0100 && Value <= 0xff00) ||
1595 (Value >= 0x010000 && Value <= 0xff0000) ||
1596 (Value >= 0x01000000 && Value <= 0xff000000) ||
1597 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1598 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1601 bool isNEONi64splat() const {
1602 if (!isImm()) return false;
1603 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1604 // Must be a constant.
1605 if (!CE) return false;
1606 uint64_t Value = CE->getValue();
1607 // i64 value with each byte being either 0 or 0xff.
1608 for (unsigned i = 0; i < 8; ++i)
1609 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1613 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1614 // Add as immediates when possible. Null MCExpr = 0.
1616 Inst.addOperand(MCOperand::CreateImm(0));
1617 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1618 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1620 Inst.addOperand(MCOperand::CreateExpr(Expr));
1623 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1624 assert(N == 2 && "Invalid number of operands!");
1625 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1626 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1627 Inst.addOperand(MCOperand::CreateReg(RegNum));
1630 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1631 assert(N == 1 && "Invalid number of operands!");
1632 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1635 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1636 assert(N == 1 && "Invalid number of operands!");
1637 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1640 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1641 assert(N == 1 && "Invalid number of operands!");
1642 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1645 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1646 assert(N == 1 && "Invalid number of operands!");
1647 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1650 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1651 assert(N == 1 && "Invalid number of operands!");
1652 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1655 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1656 assert(N == 1 && "Invalid number of operands!");
1657 Inst.addOperand(MCOperand::CreateReg(getReg()));
1660 void addRegOperands(MCInst &Inst, unsigned N) const {
1661 assert(N == 1 && "Invalid number of operands!");
1662 Inst.addOperand(MCOperand::CreateReg(getReg()));
1665 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1666 assert(N == 3 && "Invalid number of operands!");
1667 assert(isRegShiftedReg() &&
1668 "addRegShiftedRegOperands() on non-RegShiftedReg!");
1669 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1670 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1671 Inst.addOperand(MCOperand::CreateImm(
1672 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1675 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1676 assert(N == 2 && "Invalid number of operands!");
1677 assert(isRegShiftedImm() &&
1678 "addRegShiftedImmOperands() on non-RegShiftedImm!");
1679 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1680 // Shift of #32 is encoded as 0 where permitted
1681 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1682 Inst.addOperand(MCOperand::CreateImm(
1683 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1686 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1687 assert(N == 1 && "Invalid number of operands!");
1688 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1692 void addRegListOperands(MCInst &Inst, unsigned N) const {
1693 assert(N == 1 && "Invalid number of operands!");
1694 const SmallVectorImpl<unsigned> &RegList = getRegList();
1695 for (SmallVectorImpl<unsigned>::const_iterator
1696 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1697 Inst.addOperand(MCOperand::CreateReg(*I));
1700 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1701 addRegListOperands(Inst, N);
1704 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1705 addRegListOperands(Inst, N);
1708 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1709 assert(N == 1 && "Invalid number of operands!");
1710 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1711 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1714 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1715 assert(N == 1 && "Invalid number of operands!");
1716 // Munge the lsb/width into a bitfield mask.
1717 unsigned lsb = Bitfield.LSB;
1718 unsigned width = Bitfield.Width;
1719 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1720 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1721 (32 - (lsb + width)));
1722 Inst.addOperand(MCOperand::CreateImm(Mask));
1725 void addImmOperands(MCInst &Inst, unsigned N) const {
1726 assert(N == 1 && "Invalid number of operands!");
1727 addExpr(Inst, getImm());
1730 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1731 assert(N == 1 && "Invalid number of operands!");
1732 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1733 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1736 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1737 assert(N == 1 && "Invalid number of operands!");
1738 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1739 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1742 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1743 assert(N == 1 && "Invalid number of operands!");
1744 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1745 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1746 Inst.addOperand(MCOperand::CreateImm(Val));
1749 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1750 assert(N == 1 && "Invalid number of operands!");
1751 // FIXME: We really want to scale the value here, but the LDRD/STRD
1752 // instruction don't encode operands that way yet.
1753 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1754 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1757 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1758 assert(N == 1 && "Invalid number of operands!");
1759 // The immediate is scaled by four in the encoding and is stored
1760 // in the MCInst as such. Lop off the low two bits here.
1761 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1762 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1765 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1766 assert(N == 1 && "Invalid number of operands!");
1767 // The immediate is scaled by four in the encoding and is stored
1768 // in the MCInst as such. Lop off the low two bits here.
1769 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1770 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1773 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1774 assert(N == 1 && "Invalid number of operands!");
1775 // The immediate is scaled by four in the encoding and is stored
1776 // in the MCInst as such. Lop off the low two bits here.
1777 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1778 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1781 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1782 assert(N == 1 && "Invalid number of operands!");
1783 // The constant encodes as the immediate-1, and we store in the instruction
1784 // the bits as encoded, so subtract off one here.
1785 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1786 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1789 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1790 assert(N == 1 && "Invalid number of operands!");
1791 // The constant encodes as the immediate-1, and we store in the instruction
1792 // the bits as encoded, so subtract off one here.
1793 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1794 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1797 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1798 assert(N == 1 && "Invalid number of operands!");
1799 // The constant encodes as the immediate, except for 32, which encodes as
1801 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1802 unsigned Imm = CE->getValue();
1803 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1806 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1807 assert(N == 1 && "Invalid number of operands!");
1808 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1809 // the instruction as well.
1810 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1811 int Val = CE->getValue();
1812 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1815 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1816 assert(N == 1 && "Invalid number of operands!");
1817 // The operand is actually a t2_so_imm, but we have its bitwise
1818 // negation in the assembly source, so twiddle it here.
1819 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1820 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1823 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1824 assert(N == 1 && "Invalid number of operands!");
1825 // The operand is actually a t2_so_imm, but we have its
1826 // negation in the assembly source, so twiddle it here.
1827 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1828 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1831 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1832 assert(N == 1 && "Invalid number of operands!");
1833 // The operand is actually an imm0_4095, but we have its
1834 // negation in the assembly source, so twiddle it here.
1835 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1836 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1839 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1840 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1841 Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
1845 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1846 assert(SR && "Unknown value type!");
1847 Inst.addOperand(MCOperand::CreateExpr(SR));
1850 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
1851 assert(N == 1 && "Invalid number of operands!");
1853 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1855 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1859 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1860 assert(SR && "Unknown value type!");
1861 Inst.addOperand(MCOperand::CreateExpr(SR));
1865 assert(isMem() && "Unknown value type!");
1866 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
1867 Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
1870 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1871 assert(N == 1 && "Invalid number of operands!");
1872 // The operand is actually a so_imm, but we have its bitwise
1873 // negation in the assembly source, so twiddle it here.
1874 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1875 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1878 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1879 assert(N == 1 && "Invalid number of operands!");
1880 // The operand is actually a so_imm, but we have its
1881 // negation in the assembly source, so twiddle it here.
1882 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1883 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1886 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1887 assert(N == 1 && "Invalid number of operands!");
1888 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1891 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
1892 assert(N == 1 && "Invalid number of operands!");
1893 Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
1896 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1897 assert(N == 1 && "Invalid number of operands!");
1898 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1901 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1902 assert(N == 1 && "Invalid number of operands!");
1903 int32_t Imm = Memory.OffsetImm->getValue();
1904 Inst.addOperand(MCOperand::CreateImm(Imm));
1907 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1908 assert(N == 1 && "Invalid number of operands!");
1909 assert(isImm() && "Not an immediate!");
1911 // If we have an immediate that's not a constant, treat it as a label
1912 // reference needing a fixup.
1913 if (!isa<MCConstantExpr>(getImm())) {
1914 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1918 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1919 int Val = CE->getValue();
1920 Inst.addOperand(MCOperand::CreateImm(Val));
1923 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1924 assert(N == 2 && "Invalid number of operands!");
1925 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1926 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1929 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1930 assert(N == 3 && "Invalid number of operands!");
1931 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1932 if (!Memory.OffsetRegNum) {
1933 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1934 // Special case for #-0
1935 if (Val == INT32_MIN) Val = 0;
1936 if (Val < 0) Val = -Val;
1937 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1939 // For register offset, we encode the shift type and negation flag
1941 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1942 Memory.ShiftImm, Memory.ShiftType);
1944 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1945 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1946 Inst.addOperand(MCOperand::CreateImm(Val));
1949 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1950 assert(N == 2 && "Invalid number of operands!");
1951 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1952 assert(CE && "non-constant AM2OffsetImm operand!");
1953 int32_t Val = CE->getValue();
1954 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1955 // Special case for #-0
1956 if (Val == INT32_MIN) Val = 0;
1957 if (Val < 0) Val = -Val;
1958 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1959 Inst.addOperand(MCOperand::CreateReg(0));
1960 Inst.addOperand(MCOperand::CreateImm(Val));
1963 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1964 assert(N == 3 && "Invalid number of operands!");
1965 // If we have an immediate that's not a constant, treat it as a label
1966 // reference needing a fixup. If it is a constant, it's something else
1967 // and we reject it.
1969 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1970 Inst.addOperand(MCOperand::CreateReg(0));
1971 Inst.addOperand(MCOperand::CreateImm(0));
1975 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1976 if (!Memory.OffsetRegNum) {
1977 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1978 // Special case for #-0
1979 if (Val == INT32_MIN) Val = 0;
1980 if (Val < 0) Val = -Val;
1981 Val = ARM_AM::getAM3Opc(AddSub, Val);
1983 // For register offset, we encode the shift type and negation flag
1985 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1987 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1988 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1989 Inst.addOperand(MCOperand::CreateImm(Val));
1992 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1993 assert(N == 2 && "Invalid number of operands!");
1994 if (Kind == k_PostIndexRegister) {
1996 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1997 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1998 Inst.addOperand(MCOperand::CreateImm(Val));
2003 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
2004 int32_t Val = CE->getValue();
2005 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2006 // Special case for #-0
2007 if (Val == INT32_MIN) Val = 0;
2008 if (Val < 0) Val = -Val;
2009 Val = ARM_AM::getAM3Opc(AddSub, Val);
2010 Inst.addOperand(MCOperand::CreateReg(0));
2011 Inst.addOperand(MCOperand::CreateImm(Val));
2014 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2015 assert(N == 2 && "Invalid number of operands!");
2016 // If we have an immediate that's not a constant, treat it as a label
2017 // reference needing a fixup. If it is a constant, it's something else
2018 // and we reject it.
2020 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2021 Inst.addOperand(MCOperand::CreateImm(0));
2025 // The lower two bits are always zero and as such are not encoded.
2026 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2027 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2028 // Special case for #-0
2029 if (Val == INT32_MIN) Val = 0;
2030 if (Val < 0) Val = -Val;
2031 Val = ARM_AM::getAM5Opc(AddSub, Val);
2032 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2033 Inst.addOperand(MCOperand::CreateImm(Val));
2036 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2037 assert(N == 2 && "Invalid number of operands!");
2038 // If we have an immediate that's not a constant, treat it as a label
2039 // reference needing a fixup. If it is a constant, it's something else
2040 // and we reject it.
2042 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2043 Inst.addOperand(MCOperand::CreateImm(0));
2047 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2048 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2049 Inst.addOperand(MCOperand::CreateImm(Val));
2052 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2053 assert(N == 2 && "Invalid number of operands!");
2054 // The lower two bits are always zero and as such are not encoded.
2055 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2056 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2057 Inst.addOperand(MCOperand::CreateImm(Val));
2060 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2061 assert(N == 2 && "Invalid number of operands!");
2062 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2063 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2064 Inst.addOperand(MCOperand::CreateImm(Val));
2067 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2068 addMemImm8OffsetOperands(Inst, N);
2071 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2072 addMemImm8OffsetOperands(Inst, N);
2075 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2076 assert(N == 2 && "Invalid number of operands!");
2077 // If this is an immediate, it's a label reference.
2079 addExpr(Inst, getImm());
2080 Inst.addOperand(MCOperand::CreateImm(0));
2084 // Otherwise, it's a normal memory reg+offset.
2085 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2086 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2087 Inst.addOperand(MCOperand::CreateImm(Val));
2090 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2091 assert(N == 2 && "Invalid number of operands!");
2092 // If this is an immediate, it's a label reference.
2094 addExpr(Inst, getImm());
2095 Inst.addOperand(MCOperand::CreateImm(0));
2099 // Otherwise, it's a normal memory reg+offset.
2100 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2101 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2102 Inst.addOperand(MCOperand::CreateImm(Val));
2105 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2106 assert(N == 2 && "Invalid number of operands!");
2107 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2108 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2111 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2112 assert(N == 2 && "Invalid number of operands!");
2113 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2114 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2117 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2118 assert(N == 3 && "Invalid number of operands!");
2120 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2121 Memory.ShiftImm, Memory.ShiftType);
2122 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2123 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2124 Inst.addOperand(MCOperand::CreateImm(Val));
2127 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2128 assert(N == 3 && "Invalid number of operands!");
2129 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2130 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2131 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
2134 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2135 assert(N == 2 && "Invalid number of operands!");
2136 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2137 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2140 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2141 assert(N == 2 && "Invalid number of operands!");
2142 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2143 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2144 Inst.addOperand(MCOperand::CreateImm(Val));
2147 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2148 assert(N == 2 && "Invalid number of operands!");
2149 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2150 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2151 Inst.addOperand(MCOperand::CreateImm(Val));
2154 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2155 assert(N == 2 && "Invalid number of operands!");
2156 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2157 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2158 Inst.addOperand(MCOperand::CreateImm(Val));
2161 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2162 assert(N == 2 && "Invalid number of operands!");
2163 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2164 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2165 Inst.addOperand(MCOperand::CreateImm(Val));
2168 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2169 assert(N == 1 && "Invalid number of operands!");
2170 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2171 assert(CE && "non-constant post-idx-imm8 operand!");
2172 int Imm = CE->getValue();
2173 bool isAdd = Imm >= 0;
2174 if (Imm == INT32_MIN) Imm = 0;
2175 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2176 Inst.addOperand(MCOperand::CreateImm(Imm));
2179 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2180 assert(N == 1 && "Invalid number of operands!");
2181 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2182 assert(CE && "non-constant post-idx-imm8s4 operand!");
2183 int Imm = CE->getValue();
2184 bool isAdd = Imm >= 0;
2185 if (Imm == INT32_MIN) Imm = 0;
2186 // Immediate is scaled by 4.
2187 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2188 Inst.addOperand(MCOperand::CreateImm(Imm));
2191 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2192 assert(N == 2 && "Invalid number of operands!");
2193 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2194 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2197 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2198 assert(N == 2 && "Invalid number of operands!");
2199 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2200 // The sign, shift type, and shift amount are encoded in a single operand
2201 // using the AM2 encoding helpers.
2202 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2203 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2204 PostIdxReg.ShiftTy);
2205 Inst.addOperand(MCOperand::CreateImm(Imm));
2208 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2209 assert(N == 1 && "Invalid number of operands!");
2210 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2213 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2214 assert(N == 1 && "Invalid number of operands!");
2215 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2218 void addVecListOperands(MCInst &Inst, unsigned N) const {
2219 assert(N == 1 && "Invalid number of operands!");
2220 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2223 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2224 assert(N == 2 && "Invalid number of operands!");
2225 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2226 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2229 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2230 assert(N == 1 && "Invalid number of operands!");
2231 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2234 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2235 assert(N == 1 && "Invalid number of operands!");
2236 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2239 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2240 assert(N == 1 && "Invalid number of operands!");
2241 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2244 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2245 assert(N == 1 && "Invalid number of operands!");
2246 // The immediate encodes the type of constant as well as the value.
2247 // Mask in that this is an i8 splat.
2248 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2249 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2252 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2253 assert(N == 1 && "Invalid number of operands!");
2254 // The immediate encodes the type of constant as well as the value.
2255 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2256 unsigned Value = CE->getValue();
2258 Value = (Value >> 8) | 0xa00;
2261 Inst.addOperand(MCOperand::CreateImm(Value));
2264 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2265 assert(N == 1 && "Invalid number of operands!");
2266 // The immediate encodes the type of constant as well as the value.
2267 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2268 unsigned Value = CE->getValue();
2269 if (Value >= 256 && Value <= 0xff00)
2270 Value = (Value >> 8) | 0x200;
2271 else if (Value > 0xffff && Value <= 0xff0000)
2272 Value = (Value >> 16) | 0x400;
2273 else if (Value > 0xffffff)
2274 Value = (Value >> 24) | 0x600;
2275 Inst.addOperand(MCOperand::CreateImm(Value));
2278 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2279 assert(N == 1 && "Invalid number of operands!");
2280 // The immediate encodes the type of constant as well as the value.
2281 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2282 unsigned Value = CE->getValue();
2283 if (Value >= 256 && Value <= 0xffff)
2284 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2285 else if (Value > 0xffff && Value <= 0xffffff)
2286 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2287 else if (Value > 0xffffff)
2288 Value = (Value >> 24) | 0x600;
2289 Inst.addOperand(MCOperand::CreateImm(Value));
2292 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2293 assert(N == 1 && "Invalid number of operands!");
2294 // The immediate encodes the type of constant as well as the value.
2295 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2296 unsigned Value = ~CE->getValue();
2297 if (Value >= 256 && Value <= 0xffff)
2298 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2299 else if (Value > 0xffff && Value <= 0xffffff)
2300 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2301 else if (Value > 0xffffff)
2302 Value = (Value >> 24) | 0x600;
2303 Inst.addOperand(MCOperand::CreateImm(Value));
2306 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2307 assert(N == 1 && "Invalid number of operands!");
2308 // The immediate encodes the type of constant as well as the value.
2309 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2310 uint64_t Value = CE->getValue();
2312 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2313 Imm |= (Value & 1) << i;
2315 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2318 void print(raw_ostream &OS) const override;
2320 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2321 ARMOperand *Op = new ARMOperand(k_ITCondMask);
2322 Op->ITMask.Mask = Mask;
2328 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2329 ARMOperand *Op = new ARMOperand(k_CondCode);
2336 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2337 ARMOperand *Op = new ARMOperand(k_CoprocNum);
2338 Op->Cop.Val = CopVal;
2344 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2345 ARMOperand *Op = new ARMOperand(k_CoprocReg);
2346 Op->Cop.Val = CopVal;
2352 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2353 ARMOperand *Op = new ARMOperand(k_CoprocOption);
2360 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2361 ARMOperand *Op = new ARMOperand(k_CCOut);
2362 Op->Reg.RegNum = RegNum;
2368 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2369 ARMOperand *Op = new ARMOperand(k_Token);
2370 Op->Tok.Data = Str.data();
2371 Op->Tok.Length = Str.size();
2377 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2378 ARMOperand *Op = new ARMOperand(k_Register);
2379 Op->Reg.RegNum = RegNum;
2385 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2390 ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2391 Op->RegShiftedReg.ShiftTy = ShTy;
2392 Op->RegShiftedReg.SrcReg = SrcReg;
2393 Op->RegShiftedReg.ShiftReg = ShiftReg;
2394 Op->RegShiftedReg.ShiftImm = ShiftImm;
2400 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2404 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2405 Op->RegShiftedImm.ShiftTy = ShTy;
2406 Op->RegShiftedImm.SrcReg = SrcReg;
2407 Op->RegShiftedImm.ShiftImm = ShiftImm;
2413 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2415 ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2416 Op->ShifterImm.isASR = isASR;
2417 Op->ShifterImm.Imm = Imm;
2423 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2424 ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2425 Op->RotImm.Imm = Imm;
2431 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2433 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2434 Op->Bitfield.LSB = LSB;
2435 Op->Bitfield.Width = Width;
2442 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned> > &Regs,
2443 SMLoc StartLoc, SMLoc EndLoc) {
2444 assert (Regs.size() > 0 && "RegList contains no registers?");
2445 KindTy Kind = k_RegisterList;
2447 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2448 Kind = k_DPRRegisterList;
2449 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2450 contains(Regs.front().second))
2451 Kind = k_SPRRegisterList;
2453 // Sort based on the register encoding values.
2454 array_pod_sort(Regs.begin(), Regs.end());
2456 ARMOperand *Op = new ARMOperand(Kind);
2457 for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2458 I = Regs.begin(), E = Regs.end(); I != E; ++I)
2459 Op->Registers.push_back(I->second);
2460 Op->StartLoc = StartLoc;
2461 Op->EndLoc = EndLoc;
2465 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2466 bool isDoubleSpaced, SMLoc S, SMLoc E) {
2467 ARMOperand *Op = new ARMOperand(k_VectorList);
2468 Op->VectorList.RegNum = RegNum;
2469 Op->VectorList.Count = Count;
2470 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2476 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2477 bool isDoubleSpaced,
2479 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2480 Op->VectorList.RegNum = RegNum;
2481 Op->VectorList.Count = Count;
2482 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2488 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2490 bool isDoubleSpaced,
2492 ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2493 Op->VectorList.RegNum = RegNum;
2494 Op->VectorList.Count = Count;
2495 Op->VectorList.LaneIndex = Index;
2496 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2502 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2504 ARMOperand *Op = new ARMOperand(k_VectorIndex);
2505 Op->VectorIndex.Val = Idx;
2511 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2512 ARMOperand *Op = new ARMOperand(k_Immediate);
2519 static ARMOperand *CreateMem(unsigned BaseRegNum,
2520 const MCConstantExpr *OffsetImm,
2521 unsigned OffsetRegNum,
2522 ARM_AM::ShiftOpc ShiftType,
2527 ARMOperand *Op = new ARMOperand(k_Memory);
2528 Op->Memory.BaseRegNum = BaseRegNum;
2529 Op->Memory.OffsetImm = OffsetImm;
2530 Op->Memory.OffsetRegNum = OffsetRegNum;
2531 Op->Memory.ShiftType = ShiftType;
2532 Op->Memory.ShiftImm = ShiftImm;
2533 Op->Memory.Alignment = Alignment;
2534 Op->Memory.isNegative = isNegative;
2540 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2541 ARM_AM::ShiftOpc ShiftTy,
2544 ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2545 Op->PostIdxReg.RegNum = RegNum;
2546 Op->PostIdxReg.isAdd = isAdd;
2547 Op->PostIdxReg.ShiftTy = ShiftTy;
2548 Op->PostIdxReg.ShiftImm = ShiftImm;
2554 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2555 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2556 Op->MBOpt.Val = Opt;
2562 static ARMOperand *CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt,
2564 ARMOperand *Op = new ARMOperand(k_InstSyncBarrierOpt);
2565 Op->ISBOpt.Val = Opt;
2571 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2572 ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2573 Op->IFlags.Val = IFlags;
2579 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2580 ARMOperand *Op = new ARMOperand(k_MSRMask);
2581 Op->MMask.Val = MMask;
2588 } // end anonymous namespace.
2590 void ARMOperand::print(raw_ostream &OS) const {
2593 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2596 OS << "<ccout " << getReg() << ">";
2598 case k_ITCondMask: {
2599 static const char *const MaskStr[] = {
2600 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2601 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2603 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2604 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2608 OS << "<coprocessor number: " << getCoproc() << ">";
2611 OS << "<coprocessor register: " << getCoproc() << ">";
2613 case k_CoprocOption:
2614 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2617 OS << "<mask: " << getMSRMask() << ">";
2620 getImm()->print(OS);
2622 case k_MemBarrierOpt:
2623 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
2625 case k_InstSyncBarrierOpt:
2626 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2630 << " base:" << Memory.BaseRegNum;
2633 case k_PostIndexRegister:
2634 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2635 << PostIdxReg.RegNum;
2636 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2637 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2638 << PostIdxReg.ShiftImm;
2641 case k_ProcIFlags: {
2642 OS << "<ARM_PROC::";
2643 unsigned IFlags = getProcIFlags();
2644 for (int i=2; i >= 0; --i)
2645 if (IFlags & (1 << i))
2646 OS << ARM_PROC::IFlagsToString(1 << i);
2651 OS << "<register " << getReg() << ">";
2653 case k_ShifterImmediate:
2654 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2655 << " #" << ShifterImm.Imm << ">";
2657 case k_ShiftedRegister:
2658 OS << "<so_reg_reg "
2659 << RegShiftedReg.SrcReg << " "
2660 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2661 << " " << RegShiftedReg.ShiftReg << ">";
2663 case k_ShiftedImmediate:
2664 OS << "<so_reg_imm "
2665 << RegShiftedImm.SrcReg << " "
2666 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2667 << " #" << RegShiftedImm.ShiftImm << ">";
2669 case k_RotateImmediate:
2670 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2672 case k_BitfieldDescriptor:
2673 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2674 << ", width: " << Bitfield.Width << ">";
2676 case k_RegisterList:
2677 case k_DPRRegisterList:
2678 case k_SPRRegisterList: {
2679 OS << "<register_list ";
2681 const SmallVectorImpl<unsigned> &RegList = getRegList();
2682 for (SmallVectorImpl<unsigned>::const_iterator
2683 I = RegList.begin(), E = RegList.end(); I != E; ) {
2685 if (++I < E) OS << ", ";
2692 OS << "<vector_list " << VectorList.Count << " * "
2693 << VectorList.RegNum << ">";
2695 case k_VectorListAllLanes:
2696 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2697 << VectorList.RegNum << ">";
2699 case k_VectorListIndexed:
2700 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2701 << VectorList.Count << " * " << VectorList.RegNum << ">";
2704 OS << "'" << getToken() << "'";
2707 OS << "<vectorindex " << getVectorIndex() << ">";
2712 /// @name Auto-generated Match Functions
2715 static unsigned MatchRegisterName(StringRef Name);
2719 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2720 SMLoc &StartLoc, SMLoc &EndLoc) {
2721 StartLoc = Parser.getTok().getLoc();
2722 EndLoc = Parser.getTok().getEndLoc();
2723 RegNo = tryParseRegister();
2725 return (RegNo == (unsigned)-1);
2728 /// Try to parse a register name. The token must be an Identifier when called,
2729 /// and if it is a register name the token is eaten and the register number is
2730 /// returned. Otherwise return -1.
2732 int ARMAsmParser::tryParseRegister() {
2733 const AsmToken &Tok = Parser.getTok();
2734 if (Tok.isNot(AsmToken::Identifier)) return -1;
2736 std::string lowerCase = Tok.getString().lower();
2737 unsigned RegNum = MatchRegisterName(lowerCase);
2739 RegNum = StringSwitch<unsigned>(lowerCase)
2740 .Case("r13", ARM::SP)
2741 .Case("r14", ARM::LR)
2742 .Case("r15", ARM::PC)
2743 .Case("ip", ARM::R12)
2744 // Additional register name aliases for 'gas' compatibility.
2745 .Case("a1", ARM::R0)
2746 .Case("a2", ARM::R1)
2747 .Case("a3", ARM::R2)
2748 .Case("a4", ARM::R3)
2749 .Case("v1", ARM::R4)
2750 .Case("v2", ARM::R5)
2751 .Case("v3", ARM::R6)
2752 .Case("v4", ARM::R7)
2753 .Case("v5", ARM::R8)
2754 .Case("v6", ARM::R9)
2755 .Case("v7", ARM::R10)
2756 .Case("v8", ARM::R11)
2757 .Case("sb", ARM::R9)
2758 .Case("sl", ARM::R10)
2759 .Case("fp", ARM::R11)
2763 // Check for aliases registered via .req. Canonicalize to lower case.
2764 // That's more consistent since register names are case insensitive, and
2765 // it's how the original entry was passed in from MC/MCParser/AsmParser.
2766 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2767 // If no match, return failure.
2768 if (Entry == RegisterReqs.end())
2770 Parser.Lex(); // Eat identifier token.
2771 return Entry->getValue();
2774 Parser.Lex(); // Eat identifier token.
2779 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
2780 // If a recoverable error occurs, return 1. If an irrecoverable error
2781 // occurs, return -1. An irrecoverable error is one where tokens have been
2782 // consumed in the process of trying to parse the shifter (i.e., when it is
2783 // indeed a shifter operand, but malformed).
2784 int ARMAsmParser::tryParseShiftRegister(
2785 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2786 SMLoc S = Parser.getTok().getLoc();
2787 const AsmToken &Tok = Parser.getTok();
2788 if (Tok.isNot(AsmToken::Identifier))
2791 std::string lowerCase = Tok.getString().lower();
2792 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2793 .Case("asl", ARM_AM::lsl)
2794 .Case("lsl", ARM_AM::lsl)
2795 .Case("lsr", ARM_AM::lsr)
2796 .Case("asr", ARM_AM::asr)
2797 .Case("ror", ARM_AM::ror)
2798 .Case("rrx", ARM_AM::rrx)
2799 .Default(ARM_AM::no_shift);
2801 if (ShiftTy == ARM_AM::no_shift)
2804 Parser.Lex(); // Eat the operator.
2806 // The source register for the shift has already been added to the
2807 // operand list, so we need to pop it off and combine it into the shifted
2808 // register operand instead.
2809 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2810 if (!PrevOp->isReg())
2811 return Error(PrevOp->getStartLoc(), "shift must be of a register");
2812 int SrcReg = PrevOp->getReg();
2817 if (ShiftTy == ARM_AM::rrx) {
2818 // RRX Doesn't have an explicit shift amount. The encoder expects
2819 // the shift register to be the same as the source register. Seems odd,
2823 // Figure out if this is shifted by a constant or a register (for non-RRX).
2824 if (Parser.getTok().is(AsmToken::Hash) ||
2825 Parser.getTok().is(AsmToken::Dollar)) {
2826 Parser.Lex(); // Eat hash.
2827 SMLoc ImmLoc = Parser.getTok().getLoc();
2828 const MCExpr *ShiftExpr = 0;
2829 if (getParser().parseExpression(ShiftExpr, EndLoc)) {
2830 Error(ImmLoc, "invalid immediate shift value");
2833 // The expression must be evaluatable as an immediate.
2834 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2836 Error(ImmLoc, "invalid immediate shift value");
2839 // Range check the immediate.
2840 // lsl, ror: 0 <= imm <= 31
2841 // lsr, asr: 0 <= imm <= 32
2842 Imm = CE->getValue();
2844 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2845 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2846 Error(ImmLoc, "immediate shift value out of range");
2849 // shift by zero is a nop. Always send it through as lsl.
2850 // ('as' compatibility)
2852 ShiftTy = ARM_AM::lsl;
2853 } else if (Parser.getTok().is(AsmToken::Identifier)) {
2854 SMLoc L = Parser.getTok().getLoc();
2855 EndLoc = Parser.getTok().getEndLoc();
2856 ShiftReg = tryParseRegister();
2857 if (ShiftReg == -1) {
2858 Error (L, "expected immediate or register in shift operand");
2862 Error (Parser.getTok().getLoc(),
2863 "expected immediate or register in shift operand");
2868 if (ShiftReg && ShiftTy != ARM_AM::rrx)
2869 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2873 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2880 /// Try to parse a register name. The token must be an Identifier when called.
2881 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
2882 /// if there is a "writeback". 'true' if it's not a register.
2884 /// TODO this is likely to change to allow different register types and or to
2885 /// parse for a specific register type.
2887 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2888 const AsmToken &RegTok = Parser.getTok();
2889 int RegNo = tryParseRegister();
2893 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
2894 RegTok.getEndLoc()));
2896 const AsmToken &ExclaimTok = Parser.getTok();
2897 if (ExclaimTok.is(AsmToken::Exclaim)) {
2898 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2899 ExclaimTok.getLoc()));
2900 Parser.Lex(); // Eat exclaim token
2904 // Also check for an index operand. This is only legal for vector registers,
2905 // but that'll get caught OK in operand matching, so we don't need to
2906 // explicitly filter everything else out here.
2907 if (Parser.getTok().is(AsmToken::LBrac)) {
2908 SMLoc SIdx = Parser.getTok().getLoc();
2909 Parser.Lex(); // Eat left bracket token.
2911 const MCExpr *ImmVal;
2912 if (getParser().parseExpression(ImmVal))
2914 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2916 return TokError("immediate value expected for vector index");
2918 if (Parser.getTok().isNot(AsmToken::RBrac))
2919 return Error(Parser.getTok().getLoc(), "']' expected");
2921 SMLoc E = Parser.getTok().getEndLoc();
2922 Parser.Lex(); // Eat right bracket token.
2924 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2932 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
2933 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2935 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2936 // Use the same layout as the tablegen'erated register name matcher. Ugly,
2938 switch (Name.size()) {
2941 if (Name[0] != CoprocOp)
2957 if (Name[0] != CoprocOp || Name[1] != '1')
2961 // p10 and p11 are invalid for coproc instructions (reserved for FP/NEON)
2962 case '0': return CoprocOp == 'p'? -1: 10;
2963 case '1': return CoprocOp == 'p'? -1: 11;
2964 case '2': return 12;
2965 case '3': return 13;
2966 case '4': return 14;
2967 case '5': return 15;
2972 /// parseITCondCode - Try to parse a condition code for an IT instruction.
2973 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2974 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2975 SMLoc S = Parser.getTok().getLoc();
2976 const AsmToken &Tok = Parser.getTok();
2977 if (!Tok.is(AsmToken::Identifier))
2978 return MatchOperand_NoMatch;
2979 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
2980 .Case("eq", ARMCC::EQ)
2981 .Case("ne", ARMCC::NE)
2982 .Case("hs", ARMCC::HS)
2983 .Case("cs", ARMCC::HS)
2984 .Case("lo", ARMCC::LO)
2985 .Case("cc", ARMCC::LO)
2986 .Case("mi", ARMCC::MI)
2987 .Case("pl", ARMCC::PL)
2988 .Case("vs", ARMCC::VS)
2989 .Case("vc", ARMCC::VC)
2990 .Case("hi", ARMCC::HI)
2991 .Case("ls", ARMCC::LS)
2992 .Case("ge", ARMCC::GE)
2993 .Case("lt", ARMCC::LT)
2994 .Case("gt", ARMCC::GT)
2995 .Case("le", ARMCC::LE)
2996 .Case("al", ARMCC::AL)
2999 return MatchOperand_NoMatch;
3000 Parser.Lex(); // Eat the token.
3002 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
3004 return MatchOperand_Success;
3007 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
3008 /// token must be an Identifier when called, and if it is a coprocessor
3009 /// number, the token is eaten and the operand is added to the operand list.
3010 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3011 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3012 SMLoc S = Parser.getTok().getLoc();
3013 const AsmToken &Tok = Parser.getTok();
3014 if (Tok.isNot(AsmToken::Identifier))
3015 return MatchOperand_NoMatch;
3017 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
3019 return MatchOperand_NoMatch;
3021 Parser.Lex(); // Eat identifier token.
3022 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
3023 return MatchOperand_Success;
3026 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
3027 /// token must be an Identifier when called, and if it is a coprocessor
3028 /// number, the token is eaten and the operand is added to the operand list.
3029 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3030 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3031 SMLoc S = Parser.getTok().getLoc();
3032 const AsmToken &Tok = Parser.getTok();
3033 if (Tok.isNot(AsmToken::Identifier))
3034 return MatchOperand_NoMatch;
3036 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
3038 return MatchOperand_NoMatch;
3040 Parser.Lex(); // Eat identifier token.
3041 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
3042 return MatchOperand_Success;
3045 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
3046 /// coproc_option : '{' imm0_255 '}'
3047 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3048 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3049 SMLoc S = Parser.getTok().getLoc();
3051 // If this isn't a '{', this isn't a coprocessor immediate operand.
3052 if (Parser.getTok().isNot(AsmToken::LCurly))
3053 return MatchOperand_NoMatch;
3054 Parser.Lex(); // Eat the '{'
3057 SMLoc Loc = Parser.getTok().getLoc();
3058 if (getParser().parseExpression(Expr)) {
3059 Error(Loc, "illegal expression");
3060 return MatchOperand_ParseFail;
3062 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3063 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
3064 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
3065 return MatchOperand_ParseFail;
3067 int Val = CE->getValue();
3069 // Check for and consume the closing '}'
3070 if (Parser.getTok().isNot(AsmToken::RCurly))
3071 return MatchOperand_ParseFail;
3072 SMLoc E = Parser.getTok().getEndLoc();
3073 Parser.Lex(); // Eat the '}'
3075 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
3076 return MatchOperand_Success;
3079 // For register list parsing, we need to map from raw GPR register numbering
3080 // to the enumeration values. The enumeration values aren't sorted by
3081 // register number due to our using "sp", "lr" and "pc" as canonical names.
3082 static unsigned getNextRegister(unsigned Reg) {
3083 // If this is a GPR, we need to do it manually, otherwise we can rely
3084 // on the sort ordering of the enumeration since the other reg-classes
3086 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3089 default: llvm_unreachable("Invalid GPR number!");
3090 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
3091 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
3092 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
3093 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
3094 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
3095 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3096 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
3097 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
3101 // Return the low-subreg of a given Q register.
3102 static unsigned getDRegFromQReg(unsigned QReg) {
3104 default: llvm_unreachable("expected a Q register!");
3105 case ARM::Q0: return ARM::D0;
3106 case ARM::Q1: return ARM::D2;
3107 case ARM::Q2: return ARM::D4;
3108 case ARM::Q3: return ARM::D6;
3109 case ARM::Q4: return ARM::D8;
3110 case ARM::Q5: return ARM::D10;
3111 case ARM::Q6: return ARM::D12;
3112 case ARM::Q7: return ARM::D14;
3113 case ARM::Q8: return ARM::D16;
3114 case ARM::Q9: return ARM::D18;
3115 case ARM::Q10: return ARM::D20;
3116 case ARM::Q11: return ARM::D22;
3117 case ARM::Q12: return ARM::D24;
3118 case ARM::Q13: return ARM::D26;
3119 case ARM::Q14: return ARM::D28;
3120 case ARM::Q15: return ARM::D30;
3124 /// Parse a register list.
3126 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3127 assert(Parser.getTok().is(AsmToken::LCurly) &&
3128 "Token is not a Left Curly Brace");
3129 SMLoc S = Parser.getTok().getLoc();
3130 Parser.Lex(); // Eat '{' token.
3131 SMLoc RegLoc = Parser.getTok().getLoc();
3133 // Check the first register in the list to see what register class
3134 // this is a list of.
3135 int Reg = tryParseRegister();
3137 return Error(RegLoc, "register expected");
3139 // The reglist instructions have at most 16 registers, so reserve
3140 // space for that many.
3142 SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3144 // Allow Q regs and just interpret them as the two D sub-registers.
3145 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3146 Reg = getDRegFromQReg(Reg);
3147 EReg = MRI->getEncodingValue(Reg);
3148 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3151 const MCRegisterClass *RC;
3152 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3153 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3154 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3155 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3156 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3157 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3159 return Error(RegLoc, "invalid register in register list");
3161 // Store the register.
3162 EReg = MRI->getEncodingValue(Reg);
3163 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3165 // This starts immediately after the first register token in the list,
3166 // so we can see either a comma or a minus (range separator) as a legal
3168 while (Parser.getTok().is(AsmToken::Comma) ||
3169 Parser.getTok().is(AsmToken::Minus)) {
3170 if (Parser.getTok().is(AsmToken::Minus)) {
3171 Parser.Lex(); // Eat the minus.
3172 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3173 int EndReg = tryParseRegister();
3175 return Error(AfterMinusLoc, "register expected");
3176 // Allow Q regs and just interpret them as the two D sub-registers.
3177 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3178 EndReg = getDRegFromQReg(EndReg) + 1;
3179 // If the register is the same as the start reg, there's nothing
3183 // The register must be in the same register class as the first.
3184 if (!RC->contains(EndReg))
3185 return Error(AfterMinusLoc, "invalid register in register list");
3186 // Ranges must go from low to high.
3187 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3188 return Error(AfterMinusLoc, "bad range in register list");
3190 // Add all the registers in the range to the register list.
3191 while (Reg != EndReg) {
3192 Reg = getNextRegister(Reg);
3193 EReg = MRI->getEncodingValue(Reg);
3194 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3198 Parser.Lex(); // Eat the comma.
3199 RegLoc = Parser.getTok().getLoc();
3201 const AsmToken RegTok = Parser.getTok();
3202 Reg = tryParseRegister();
3204 return Error(RegLoc, "register expected");
3205 // Allow Q regs and just interpret them as the two D sub-registers.
3206 bool isQReg = false;
3207 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3208 Reg = getDRegFromQReg(Reg);
3211 // The register must be in the same register class as the first.
3212 if (!RC->contains(Reg))
3213 return Error(RegLoc, "invalid register in register list");
3214 // List must be monotonically increasing.
3215 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3216 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3217 Warning(RegLoc, "register list not in ascending order");
3219 return Error(RegLoc, "register list not in ascending order");
3221 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3222 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3223 ") in register list");
3226 // VFP register lists must also be contiguous.
3227 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3229 return Error(RegLoc, "non-contiguous register range");
3230 EReg = MRI->getEncodingValue(Reg);
3231 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3233 EReg = MRI->getEncodingValue(++Reg);
3234 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3238 if (Parser.getTok().isNot(AsmToken::RCurly))
3239 return Error(Parser.getTok().getLoc(), "'}' expected");
3240 SMLoc E = Parser.getTok().getEndLoc();
3241 Parser.Lex(); // Eat '}' token.
3243 // Push the register list operand.
3244 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3246 // The ARM system instruction variants for LDM/STM have a '^' token here.
3247 if (Parser.getTok().is(AsmToken::Caret)) {
3248 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3249 Parser.Lex(); // Eat '^' token.
3255 // Helper function to parse the lane index for vector lists.
3256 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3257 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3258 Index = 0; // Always return a defined index value.
3259 if (Parser.getTok().is(AsmToken::LBrac)) {
3260 Parser.Lex(); // Eat the '['.
3261 if (Parser.getTok().is(AsmToken::RBrac)) {
3262 // "Dn[]" is the 'all lanes' syntax.
3263 LaneKind = AllLanes;
3264 EndLoc = Parser.getTok().getEndLoc();
3265 Parser.Lex(); // Eat the ']'.
3266 return MatchOperand_Success;
3269 // There's an optional '#' token here. Normally there wouldn't be, but
3270 // inline assemble puts one in, and it's friendly to accept that.
3271 if (Parser.getTok().is(AsmToken::Hash))
3272 Parser.Lex(); // Eat '#' or '$'.
3274 const MCExpr *LaneIndex;
3275 SMLoc Loc = Parser.getTok().getLoc();
3276 if (getParser().parseExpression(LaneIndex)) {
3277 Error(Loc, "illegal expression");
3278 return MatchOperand_ParseFail;
3280 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3282 Error(Loc, "lane index must be empty or an integer");
3283 return MatchOperand_ParseFail;
3285 if (Parser.getTok().isNot(AsmToken::RBrac)) {
3286 Error(Parser.getTok().getLoc(), "']' expected");
3287 return MatchOperand_ParseFail;
3289 EndLoc = Parser.getTok().getEndLoc();
3290 Parser.Lex(); // Eat the ']'.
3291 int64_t Val = CE->getValue();
3293 // FIXME: Make this range check context sensitive for .8, .16, .32.
3294 if (Val < 0 || Val > 7) {
3295 Error(Parser.getTok().getLoc(), "lane index out of range");
3296 return MatchOperand_ParseFail;
3299 LaneKind = IndexedLane;
3300 return MatchOperand_Success;
3303 return MatchOperand_Success;
3306 // parse a vector register list
3307 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3308 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3309 VectorLaneTy LaneKind;
3311 SMLoc S = Parser.getTok().getLoc();
3312 // As an extension (to match gas), support a plain D register or Q register
3313 // (without encosing curly braces) as a single or double entry list,
3315 if (Parser.getTok().is(AsmToken::Identifier)) {
3316 SMLoc E = Parser.getTok().getEndLoc();
3317 int Reg = tryParseRegister();
3319 return MatchOperand_NoMatch;
3320 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3321 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3322 if (Res != MatchOperand_Success)
3326 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3329 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3333 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3338 return MatchOperand_Success;
3340 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3341 Reg = getDRegFromQReg(Reg);
3342 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3343 if (Res != MatchOperand_Success)
3347 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3348 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3349 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3352 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3353 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3354 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3358 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3363 return MatchOperand_Success;
3365 Error(S, "vector register expected");
3366 return MatchOperand_ParseFail;
3369 if (Parser.getTok().isNot(AsmToken::LCurly))
3370 return MatchOperand_NoMatch;
3372 Parser.Lex(); // Eat '{' token.
3373 SMLoc RegLoc = Parser.getTok().getLoc();
3375 int Reg = tryParseRegister();
3377 Error(RegLoc, "register expected");
3378 return MatchOperand_ParseFail;
3382 unsigned FirstReg = Reg;
3383 // The list is of D registers, but we also allow Q regs and just interpret
3384 // them as the two D sub-registers.
3385 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3386 FirstReg = Reg = getDRegFromQReg(Reg);
3387 Spacing = 1; // double-spacing requires explicit D registers, otherwise
3388 // it's ambiguous with four-register single spaced.
3394 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3395 return MatchOperand_ParseFail;
3397 while (Parser.getTok().is(AsmToken::Comma) ||
3398 Parser.getTok().is(AsmToken::Minus)) {
3399 if (Parser.getTok().is(AsmToken::Minus)) {
3401 Spacing = 1; // Register range implies a single spaced list.
3402 else if (Spacing == 2) {
3403 Error(Parser.getTok().getLoc(),
3404 "sequential registers in double spaced list");
3405 return MatchOperand_ParseFail;
3407 Parser.Lex(); // Eat the minus.
3408 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3409 int EndReg = tryParseRegister();
3411 Error(AfterMinusLoc, "register expected");
3412 return MatchOperand_ParseFail;
3414 // Allow Q regs and just interpret them as the two D sub-registers.
3415 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3416 EndReg = getDRegFromQReg(EndReg) + 1;
3417 // If the register is the same as the start reg, there's nothing
3421 // The register must be in the same register class as the first.
3422 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3423 Error(AfterMinusLoc, "invalid register in register list");
3424 return MatchOperand_ParseFail;
3426 // Ranges must go from low to high.
3428 Error(AfterMinusLoc, "bad range in register list");
3429 return MatchOperand_ParseFail;
3431 // Parse the lane specifier if present.
3432 VectorLaneTy NextLaneKind;
3433 unsigned NextLaneIndex;
3434 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3435 MatchOperand_Success)
3436 return MatchOperand_ParseFail;
3437 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3438 Error(AfterMinusLoc, "mismatched lane index in register list");
3439 return MatchOperand_ParseFail;
3442 // Add all the registers in the range to the register list.
3443 Count += EndReg - Reg;
3447 Parser.Lex(); // Eat the comma.
3448 RegLoc = Parser.getTok().getLoc();
3450 Reg = tryParseRegister();
3452 Error(RegLoc, "register expected");
3453 return MatchOperand_ParseFail;
3455 // vector register lists must be contiguous.
3456 // It's OK to use the enumeration values directly here rather, as the
3457 // VFP register classes have the enum sorted properly.
3459 // The list is of D registers, but we also allow Q regs and just interpret
3460 // them as the two D sub-registers.
3461 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3463 Spacing = 1; // Register range implies a single spaced list.
3464 else if (Spacing == 2) {
3466 "invalid register in double-spaced list (must be 'D' register')");
3467 return MatchOperand_ParseFail;
3469 Reg = getDRegFromQReg(Reg);
3470 if (Reg != OldReg + 1) {
3471 Error(RegLoc, "non-contiguous register range");
3472 return MatchOperand_ParseFail;
3476 // Parse the lane specifier if present.
3477 VectorLaneTy NextLaneKind;
3478 unsigned NextLaneIndex;
3479 SMLoc LaneLoc = Parser.getTok().getLoc();
3480 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3481 MatchOperand_Success)
3482 return MatchOperand_ParseFail;
3483 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3484 Error(LaneLoc, "mismatched lane index in register list");
3485 return MatchOperand_ParseFail;
3489 // Normal D register.
3490 // Figure out the register spacing (single or double) of the list if
3491 // we don't know it already.
3493 Spacing = 1 + (Reg == OldReg + 2);
3495 // Just check that it's contiguous and keep going.
3496 if (Reg != OldReg + Spacing) {
3497 Error(RegLoc, "non-contiguous register range");
3498 return MatchOperand_ParseFail;
3501 // Parse the lane specifier if present.
3502 VectorLaneTy NextLaneKind;
3503 unsigned NextLaneIndex;
3504 SMLoc EndLoc = Parser.getTok().getLoc();
3505 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3506 return MatchOperand_ParseFail;
3507 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3508 Error(EndLoc, "mismatched lane index in register list");
3509 return MatchOperand_ParseFail;
3513 if (Parser.getTok().isNot(AsmToken::RCurly)) {
3514 Error(Parser.getTok().getLoc(), "'}' expected");
3515 return MatchOperand_ParseFail;
3517 E = Parser.getTok().getEndLoc();
3518 Parser.Lex(); // Eat '}' token.
3522 // Two-register operands have been converted to the
3523 // composite register classes.
3525 const MCRegisterClass *RC = (Spacing == 1) ?
3526 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3527 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3528 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3531 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3532 (Spacing == 2), S, E));
3535 // Two-register operands have been converted to the
3536 // composite register classes.
3538 const MCRegisterClass *RC = (Spacing == 1) ?
3539 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3540 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3541 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3543 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3548 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3554 return MatchOperand_Success;
3557 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3558 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3559 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3560 SMLoc S = Parser.getTok().getLoc();
3561 const AsmToken &Tok = Parser.getTok();
3564 if (Tok.is(AsmToken::Identifier)) {
3565 StringRef OptStr = Tok.getString();
3567 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3568 .Case("sy", ARM_MB::SY)
3569 .Case("st", ARM_MB::ST)
3570 .Case("ld", ARM_MB::LD)
3571 .Case("sh", ARM_MB::ISH)
3572 .Case("ish", ARM_MB::ISH)
3573 .Case("shst", ARM_MB::ISHST)
3574 .Case("ishst", ARM_MB::ISHST)
3575 .Case("ishld", ARM_MB::ISHLD)
3576 .Case("nsh", ARM_MB::NSH)
3577 .Case("un", ARM_MB::NSH)
3578 .Case("nshst", ARM_MB::NSHST)
3579 .Case("nshld", ARM_MB::NSHLD)
3580 .Case("unst", ARM_MB::NSHST)
3581 .Case("osh", ARM_MB::OSH)
3582 .Case("oshst", ARM_MB::OSHST)
3583 .Case("oshld", ARM_MB::OSHLD)
3586 // ishld, oshld, nshld and ld are only available from ARMv8.
3587 if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
3588 Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
3592 return MatchOperand_NoMatch;
3594 Parser.Lex(); // Eat identifier token.
3595 } else if (Tok.is(AsmToken::Hash) ||
3596 Tok.is(AsmToken::Dollar) ||
3597 Tok.is(AsmToken::Integer)) {
3598 if (Parser.getTok().isNot(AsmToken::Integer))
3599 Parser.Lex(); // Eat '#' or '$'.
3600 SMLoc Loc = Parser.getTok().getLoc();
3602 const MCExpr *MemBarrierID;
3603 if (getParser().parseExpression(MemBarrierID)) {
3604 Error(Loc, "illegal expression");
3605 return MatchOperand_ParseFail;
3608 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3610 Error(Loc, "constant expression expected");
3611 return MatchOperand_ParseFail;
3614 int Val = CE->getValue();
3616 Error(Loc, "immediate value out of range");
3617 return MatchOperand_ParseFail;
3620 Opt = ARM_MB::RESERVED_0 + Val;
3622 return MatchOperand_ParseFail;
3624 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3625 return MatchOperand_Success;
3628 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3629 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3630 parseInstSyncBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3631 SMLoc S = Parser.getTok().getLoc();
3632 const AsmToken &Tok = Parser.getTok();
3635 if (Tok.is(AsmToken::Identifier)) {
3636 StringRef OptStr = Tok.getString();
3638 if (OptStr.equals_lower("sy"))
3641 return MatchOperand_NoMatch;
3643 Parser.Lex(); // Eat identifier token.
3644 } else if (Tok.is(AsmToken::Hash) ||
3645 Tok.is(AsmToken::Dollar) ||
3646 Tok.is(AsmToken::Integer)) {
3647 if (Parser.getTok().isNot(AsmToken::Integer))
3648 Parser.Lex(); // Eat '#' or '$'.
3649 SMLoc Loc = Parser.getTok().getLoc();
3651 const MCExpr *ISBarrierID;
3652 if (getParser().parseExpression(ISBarrierID)) {
3653 Error(Loc, "illegal expression");
3654 return MatchOperand_ParseFail;
3657 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3659 Error(Loc, "constant expression expected");
3660 return MatchOperand_ParseFail;
3663 int Val = CE->getValue();
3665 Error(Loc, "immediate value out of range");
3666 return MatchOperand_ParseFail;
3669 Opt = ARM_ISB::RESERVED_0 + Val;
3671 return MatchOperand_ParseFail;
3673 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3674 (ARM_ISB::InstSyncBOpt)Opt, S));
3675 return MatchOperand_Success;
3679 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3680 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3681 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3682 SMLoc S = Parser.getTok().getLoc();
3683 const AsmToken &Tok = Parser.getTok();
3684 if (!Tok.is(AsmToken::Identifier))
3685 return MatchOperand_NoMatch;
3686 StringRef IFlagsStr = Tok.getString();
3688 // An iflags string of "none" is interpreted to mean that none of the AIF
3689 // bits are set. Not a terribly useful instruction, but a valid encoding.
3690 unsigned IFlags = 0;
3691 if (IFlagsStr != "none") {
3692 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3693 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3694 .Case("a", ARM_PROC::A)
3695 .Case("i", ARM_PROC::I)
3696 .Case("f", ARM_PROC::F)
3699 // If some specific iflag is already set, it means that some letter is
3700 // present more than once, this is not acceptable.
3701 if (Flag == ~0U || (IFlags & Flag))
3702 return MatchOperand_NoMatch;
3708 Parser.Lex(); // Eat identifier token.
3709 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3710 return MatchOperand_Success;
3713 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3714 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3715 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3716 SMLoc S = Parser.getTok().getLoc();
3717 const AsmToken &Tok = Parser.getTok();
3718 if (!Tok.is(AsmToken::Identifier))
3719 return MatchOperand_NoMatch;
3720 StringRef Mask = Tok.getString();
3723 // See ARMv6-M 10.1.1
3724 std::string Name = Mask.lower();
3725 unsigned FlagsVal = StringSwitch<unsigned>(Name)
3726 // Note: in the documentation:
3727 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3728 // for MSR APSR_nzcvq.
3729 // but we do make it an alias here. This is so to get the "mask encoding"
3730 // bits correct on MSR APSR writes.
3732 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3733 // should really only be allowed when writing a special register. Note
3734 // they get dropped in the MRS instruction reading a special register as
3735 // the SYSm field is only 8 bits.
3737 // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3738 // includes the DSP extension but that is not checked.
3739 .Case("apsr", 0x800)
3740 .Case("apsr_nzcvq", 0x800)
3741 .Case("apsr_g", 0x400)
3742 .Case("apsr_nzcvqg", 0xc00)
3743 .Case("iapsr", 0x801)
3744 .Case("iapsr_nzcvq", 0x801)
3745 .Case("iapsr_g", 0x401)
3746 .Case("iapsr_nzcvqg", 0xc01)
3747 .Case("eapsr", 0x802)
3748 .Case("eapsr_nzcvq", 0x802)
3749 .Case("eapsr_g", 0x402)
3750 .Case("eapsr_nzcvqg", 0xc02)
3751 .Case("xpsr", 0x803)
3752 .Case("xpsr_nzcvq", 0x803)
3753 .Case("xpsr_g", 0x403)
3754 .Case("xpsr_nzcvqg", 0xc03)
3755 .Case("ipsr", 0x805)
3756 .Case("epsr", 0x806)
3757 .Case("iepsr", 0x807)
3760 .Case("primask", 0x810)
3761 .Case("basepri", 0x811)
3762 .Case("basepri_max", 0x812)
3763 .Case("faultmask", 0x813)
3764 .Case("control", 0x814)
3767 if (FlagsVal == ~0U)
3768 return MatchOperand_NoMatch;
3770 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3771 // basepri, basepri_max and faultmask only valid for V7m.
3772 return MatchOperand_NoMatch;
3774 Parser.Lex(); // Eat identifier token.
3775 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3776 return MatchOperand_Success;
3779 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3780 size_t Start = 0, Next = Mask.find('_');
3781 StringRef Flags = "";
3782 std::string SpecReg = Mask.slice(Start, Next).lower();
3783 if (Next != StringRef::npos)
3784 Flags = Mask.slice(Next+1, Mask.size());
3786 // FlagsVal contains the complete mask:
3788 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3789 unsigned FlagsVal = 0;
3791 if (SpecReg == "apsr") {
3792 FlagsVal = StringSwitch<unsigned>(Flags)
3793 .Case("nzcvq", 0x8) // same as CPSR_f
3794 .Case("g", 0x4) // same as CPSR_s
3795 .Case("nzcvqg", 0xc) // same as CPSR_fs
3798 if (FlagsVal == ~0U) {
3800 return MatchOperand_NoMatch;
3802 FlagsVal = 8; // No flag
3804 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3805 // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3806 if (Flags == "all" || Flags == "")
3808 for (int i = 0, e = Flags.size(); i != e; ++i) {
3809 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3816 // If some specific flag is already set, it means that some letter is
3817 // present more than once, this is not acceptable.
3818 if (FlagsVal == ~0U || (FlagsVal & Flag))
3819 return MatchOperand_NoMatch;
3822 } else // No match for special register.
3823 return MatchOperand_NoMatch;
3825 // Special register without flags is NOT equivalent to "fc" flags.
3826 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
3827 // two lines would enable gas compatibility at the expense of breaking
3833 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3834 if (SpecReg == "spsr")
3837 Parser.Lex(); // Eat identifier token.
3838 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3839 return MatchOperand_Success;
3842 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3843 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3844 int Low, int High) {
3845 const AsmToken &Tok = Parser.getTok();
3846 if (Tok.isNot(AsmToken::Identifier)) {
3847 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3848 return MatchOperand_ParseFail;
3850 StringRef ShiftName = Tok.getString();
3851 std::string LowerOp = Op.lower();
3852 std::string UpperOp = Op.upper();
3853 if (ShiftName != LowerOp && ShiftName != UpperOp) {
3854 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3855 return MatchOperand_ParseFail;
3857 Parser.Lex(); // Eat shift type token.
3859 // There must be a '#' and a shift amount.
3860 if (Parser.getTok().isNot(AsmToken::Hash) &&
3861 Parser.getTok().isNot(AsmToken::Dollar)) {
3862 Error(Parser.getTok().getLoc(), "'#' expected");
3863 return MatchOperand_ParseFail;
3865 Parser.Lex(); // Eat hash token.
3867 const MCExpr *ShiftAmount;
3868 SMLoc Loc = Parser.getTok().getLoc();
3870 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3871 Error(Loc, "illegal expression");
3872 return MatchOperand_ParseFail;
3874 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3876 Error(Loc, "constant expression expected");
3877 return MatchOperand_ParseFail;
3879 int Val = CE->getValue();
3880 if (Val < Low || Val > High) {
3881 Error(Loc, "immediate value out of range");
3882 return MatchOperand_ParseFail;
3885 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
3887 return MatchOperand_Success;
3890 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3891 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3892 const AsmToken &Tok = Parser.getTok();
3893 SMLoc S = Tok.getLoc();
3894 if (Tok.isNot(AsmToken::Identifier)) {
3895 Error(S, "'be' or 'le' operand expected");
3896 return MatchOperand_ParseFail;
3898 int Val = StringSwitch<int>(Tok.getString().lower())
3902 Parser.Lex(); // Eat the token.
3905 Error(S, "'be' or 'le' operand expected");
3906 return MatchOperand_ParseFail;
3908 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3910 S, Tok.getEndLoc()));
3911 return MatchOperand_Success;
3914 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3915 /// instructions. Legal values are:
3916 /// lsl #n 'n' in [0,31]
3917 /// asr #n 'n' in [1,32]
3918 /// n == 32 encoded as n == 0.
3919 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3920 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3921 const AsmToken &Tok = Parser.getTok();
3922 SMLoc S = Tok.getLoc();
3923 if (Tok.isNot(AsmToken::Identifier)) {
3924 Error(S, "shift operator 'asr' or 'lsl' expected");
3925 return MatchOperand_ParseFail;
3927 StringRef ShiftName = Tok.getString();
3929 if (ShiftName == "lsl" || ShiftName == "LSL")
3931 else if (ShiftName == "asr" || ShiftName == "ASR")
3934 Error(S, "shift operator 'asr' or 'lsl' expected");
3935 return MatchOperand_ParseFail;
3937 Parser.Lex(); // Eat the operator.
3939 // A '#' and a shift amount.
3940 if (Parser.getTok().isNot(AsmToken::Hash) &&
3941 Parser.getTok().isNot(AsmToken::Dollar)) {
3942 Error(Parser.getTok().getLoc(), "'#' expected");
3943 return MatchOperand_ParseFail;
3945 Parser.Lex(); // Eat hash token.
3946 SMLoc ExLoc = Parser.getTok().getLoc();
3948 const MCExpr *ShiftAmount;
3950 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3951 Error(ExLoc, "malformed shift expression");
3952 return MatchOperand_ParseFail;
3954 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3956 Error(ExLoc, "shift amount must be an immediate");
3957 return MatchOperand_ParseFail;
3960 int64_t Val = CE->getValue();
3962 // Shift amount must be in [1,32]
3963 if (Val < 1 || Val > 32) {
3964 Error(ExLoc, "'asr' shift amount must be in range [1,32]");
3965 return MatchOperand_ParseFail;
3967 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3968 if (isThumb() && Val == 32) {
3969 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
3970 return MatchOperand_ParseFail;
3972 if (Val == 32) Val = 0;
3974 // Shift amount must be in [1,32]
3975 if (Val < 0 || Val > 31) {
3976 Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
3977 return MatchOperand_ParseFail;
3981 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
3983 return MatchOperand_Success;
3986 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3987 /// of instructions. Legal values are:
3988 /// ror #n 'n' in {0, 8, 16, 24}
3989 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3990 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3991 const AsmToken &Tok = Parser.getTok();
3992 SMLoc S = Tok.getLoc();
3993 if (Tok.isNot(AsmToken::Identifier))
3994 return MatchOperand_NoMatch;
3995 StringRef ShiftName = Tok.getString();
3996 if (ShiftName != "ror" && ShiftName != "ROR")
3997 return MatchOperand_NoMatch;
3998 Parser.Lex(); // Eat the operator.
4000 // A '#' and a rotate amount.
4001 if (Parser.getTok().isNot(AsmToken::Hash) &&
4002 Parser.getTok().isNot(AsmToken::Dollar)) {
4003 Error(Parser.getTok().getLoc(), "'#' expected");
4004 return MatchOperand_ParseFail;
4006 Parser.Lex(); // Eat hash token.
4007 SMLoc ExLoc = Parser.getTok().getLoc();
4009 const MCExpr *ShiftAmount;
4011 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4012 Error(ExLoc, "malformed rotate expression");
4013 return MatchOperand_ParseFail;
4015 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4017 Error(ExLoc, "rotate amount must be an immediate");
4018 return MatchOperand_ParseFail;
4021 int64_t Val = CE->getValue();
4022 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
4023 // normally, zero is represented in asm by omitting the rotate operand
4025 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
4026 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
4027 return MatchOperand_ParseFail;
4030 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
4032 return MatchOperand_Success;
4035 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4036 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4037 SMLoc S = Parser.getTok().getLoc();
4038 // The bitfield descriptor is really two operands, the LSB and the width.
4039 if (Parser.getTok().isNot(AsmToken::Hash) &&
4040 Parser.getTok().isNot(AsmToken::Dollar)) {
4041 Error(Parser.getTok().getLoc(), "'#' expected");
4042 return MatchOperand_ParseFail;
4044 Parser.Lex(); // Eat hash token.
4046 const MCExpr *LSBExpr;
4047 SMLoc E = Parser.getTok().getLoc();
4048 if (getParser().parseExpression(LSBExpr)) {
4049 Error(E, "malformed immediate expression");
4050 return MatchOperand_ParseFail;
4052 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
4054 Error(E, "'lsb' operand must be an immediate");
4055 return MatchOperand_ParseFail;
4058 int64_t LSB = CE->getValue();
4059 // The LSB must be in the range [0,31]
4060 if (LSB < 0 || LSB > 31) {
4061 Error(E, "'lsb' operand must be in the range [0,31]");
4062 return MatchOperand_ParseFail;
4064 E = Parser.getTok().getLoc();
4066 // Expect another immediate operand.
4067 if (Parser.getTok().isNot(AsmToken::Comma)) {
4068 Error(Parser.getTok().getLoc(), "too few operands");
4069 return MatchOperand_ParseFail;
4071 Parser.Lex(); // Eat hash token.
4072 if (Parser.getTok().isNot(AsmToken::Hash) &&
4073 Parser.getTok().isNot(AsmToken::Dollar)) {
4074 Error(Parser.getTok().getLoc(), "'#' expected");
4075 return MatchOperand_ParseFail;
4077 Parser.Lex(); // Eat hash token.
4079 const MCExpr *WidthExpr;
4081 if (getParser().parseExpression(WidthExpr, EndLoc)) {
4082 Error(E, "malformed immediate expression");
4083 return MatchOperand_ParseFail;
4085 CE = dyn_cast<MCConstantExpr>(WidthExpr);
4087 Error(E, "'width' operand must be an immediate");
4088 return MatchOperand_ParseFail;
4091 int64_t Width = CE->getValue();
4092 // The LSB must be in the range [1,32-lsb]
4093 if (Width < 1 || Width > 32 - LSB) {
4094 Error(E, "'width' operand must be in the range [1,32-lsb]");
4095 return MatchOperand_ParseFail;
4098 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4100 return MatchOperand_Success;
4103 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4104 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4105 // Check for a post-index addressing register operand. Specifically:
4106 // postidx_reg := '+' register {, shift}
4107 // | '-' register {, shift}
4108 // | register {, shift}
4110 // This method must return MatchOperand_NoMatch without consuming any tokens
4111 // in the case where there is no match, as other alternatives take other
4113 AsmToken Tok = Parser.getTok();
4114 SMLoc S = Tok.getLoc();
4115 bool haveEaten = false;
4117 if (Tok.is(AsmToken::Plus)) {
4118 Parser.Lex(); // Eat the '+' token.
4120 } else if (Tok.is(AsmToken::Minus)) {
4121 Parser.Lex(); // Eat the '-' token.
4126 SMLoc E = Parser.getTok().getEndLoc();
4127 int Reg = tryParseRegister();
4130 return MatchOperand_NoMatch;
4131 Error(Parser.getTok().getLoc(), "register expected");
4132 return MatchOperand_ParseFail;
4135 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4136 unsigned ShiftImm = 0;
4137 if (Parser.getTok().is(AsmToken::Comma)) {
4138 Parser.Lex(); // Eat the ','.
4139 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4140 return MatchOperand_ParseFail;
4142 // FIXME: Only approximates end...may include intervening whitespace.
4143 E = Parser.getTok().getLoc();
4146 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4149 return MatchOperand_Success;
4152 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4153 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4154 // Check for a post-index addressing register operand. Specifically:
4155 // am3offset := '+' register
4162 // This method must return MatchOperand_NoMatch without consuming any tokens
4163 // in the case where there is no match, as other alternatives take other
4165 AsmToken Tok = Parser.getTok();
4166 SMLoc S = Tok.getLoc();
4168 // Do immediates first, as we always parse those if we have a '#'.
4169 if (Parser.getTok().is(AsmToken::Hash) ||
4170 Parser.getTok().is(AsmToken::Dollar)) {
4171 Parser.Lex(); // Eat '#' or '$'.
4172 // Explicitly look for a '-', as we need to encode negative zero
4174 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4175 const MCExpr *Offset;
4177 if (getParser().parseExpression(Offset, E))
4178 return MatchOperand_ParseFail;
4179 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4181 Error(S, "constant expression expected");
4182 return MatchOperand_ParseFail;
4184 // Negative zero is encoded as the flag value INT32_MIN.
4185 int32_t Val = CE->getValue();
4186 if (isNegative && Val == 0)
4190 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4192 return MatchOperand_Success;
4196 bool haveEaten = false;
4198 if (Tok.is(AsmToken::Plus)) {
4199 Parser.Lex(); // Eat the '+' token.
4201 } else if (Tok.is(AsmToken::Minus)) {
4202 Parser.Lex(); // Eat the '-' token.
4207 Tok = Parser.getTok();
4208 int Reg = tryParseRegister();
4211 return MatchOperand_NoMatch;
4212 Error(Tok.getLoc(), "register expected");
4213 return MatchOperand_ParseFail;
4216 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4217 0, S, Tok.getEndLoc()));
4219 return MatchOperand_Success;
4222 /// Convert parsed operands to MCInst. Needed here because this instruction
4223 /// only has two register operands, but multiplication is commutative so
4224 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4226 cvtThumbMultiply(MCInst &Inst,
4227 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4228 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4229 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4230 // If we have a three-operand form, make sure to set Rn to be the operand
4231 // that isn't the same as Rd.
4233 if (Operands.size() == 6 &&
4234 ((ARMOperand*)Operands[4])->getReg() ==
4235 ((ARMOperand*)Operands[3])->getReg())
4237 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4238 Inst.addOperand(Inst.getOperand(0));
4239 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4243 cvtThumbBranches(MCInst &Inst,
4244 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4245 int CondOp = -1, ImmOp = -1;
4246 switch(Inst.getOpcode()) {
4248 case ARM::tBcc: CondOp = 1; ImmOp = 2; break;
4251 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4253 default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4255 // first decide whether or not the branch should be conditional
4256 // by looking at it's location relative to an IT block
4258 // inside an IT block we cannot have any conditional branches. any
4259 // such instructions needs to be converted to unconditional form
4260 switch(Inst.getOpcode()) {
4261 case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4262 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4265 // outside IT blocks we can only have unconditional branches with AL
4266 // condition code or conditional branches with non-AL condition code
4267 unsigned Cond = static_cast<ARMOperand*>(Operands[CondOp])->getCondCode();
4268 switch(Inst.getOpcode()) {
4271 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4275 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4280 // now decide on encoding size based on branch target range
4281 switch(Inst.getOpcode()) {
4282 // classify tB as either t2B or t1B based on range of immediate operand
4284 ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4285 if(!op->isSignedOffset<11, 1>() && isThumbTwo())
4286 Inst.setOpcode(ARM::t2B);
4289 // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4291 ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4292 if(!op->isSignedOffset<8, 1>() && isThumbTwo())
4293 Inst.setOpcode(ARM::t2Bcc);
4297 ((ARMOperand*)Operands[ImmOp])->addImmOperands(Inst, 1);
4298 ((ARMOperand*)Operands[CondOp])->addCondCodeOperands(Inst, 2);
4301 /// Parse an ARM memory expression, return false if successful else return true
4302 /// or an error. The first token must be a '[' when called.
4304 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4306 assert(Parser.getTok().is(AsmToken::LBrac) &&
4307 "Token is not a Left Bracket");
4308 S = Parser.getTok().getLoc();
4309 Parser.Lex(); // Eat left bracket token.
4311 const AsmToken &BaseRegTok = Parser.getTok();
4312 int BaseRegNum = tryParseRegister();
4313 if (BaseRegNum == -1)
4314 return Error(BaseRegTok.getLoc(), "register expected");
4316 // The next token must either be a comma, a colon or a closing bracket.
4317 const AsmToken &Tok = Parser.getTok();
4318 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4319 !Tok.is(AsmToken::RBrac))
4320 return Error(Tok.getLoc(), "malformed memory operand");
4322 if (Tok.is(AsmToken::RBrac)) {
4323 E = Tok.getEndLoc();
4324 Parser.Lex(); // Eat right bracket token.
4326 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4327 0, 0, false, S, E));
4329 // If there's a pre-indexing writeback marker, '!', just add it as a token
4330 // operand. It's rather odd, but syntactically valid.
4331 if (Parser.getTok().is(AsmToken::Exclaim)) {
4332 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4333 Parser.Lex(); // Eat the '!'.
4339 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4340 "Lost colon or comma in memory operand?!");
4341 if (Tok.is(AsmToken::Comma)) {
4342 Parser.Lex(); // Eat the comma.
4345 // If we have a ':', it's an alignment specifier.
4346 if (Parser.getTok().is(AsmToken::Colon)) {
4347 Parser.Lex(); // Eat the ':'.
4348 E = Parser.getTok().getLoc();
4351 if (getParser().parseExpression(Expr))
4354 // The expression has to be a constant. Memory references with relocations
4355 // don't come through here, as they use the <label> forms of the relevant
4357 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4359 return Error (E, "constant expression expected");
4362 switch (CE->getValue()) {
4365 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4366 case 16: Align = 2; break;
4367 case 32: Align = 4; break;
4368 case 64: Align = 8; break;
4369 case 128: Align = 16; break;
4370 case 256: Align = 32; break;
4373 // Now we should have the closing ']'
4374 if (Parser.getTok().isNot(AsmToken::RBrac))
4375 return Error(Parser.getTok().getLoc(), "']' expected");
4376 E = Parser.getTok().getEndLoc();
4377 Parser.Lex(); // Eat right bracket token.
4379 // Don't worry about range checking the value here. That's handled by
4380 // the is*() predicates.
4381 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4382 ARM_AM::no_shift, 0, Align,
4385 // If there's a pre-indexing writeback marker, '!', just add it as a token
4387 if (Parser.getTok().is(AsmToken::Exclaim)) {
4388 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4389 Parser.Lex(); // Eat the '!'.
4395 // If we have a '#', it's an immediate offset, else assume it's a register
4396 // offset. Be friendly and also accept a plain integer (without a leading
4397 // hash) for gas compatibility.
4398 if (Parser.getTok().is(AsmToken::Hash) ||
4399 Parser.getTok().is(AsmToken::Dollar) ||
4400 Parser.getTok().is(AsmToken::Integer)) {
4401 if (Parser.getTok().isNot(AsmToken::Integer))
4402 Parser.Lex(); // Eat '#' or '$'.
4403 E = Parser.getTok().getLoc();
4405 bool isNegative = getParser().getTok().is(AsmToken::Minus);
4406 const MCExpr *Offset;
4407 if (getParser().parseExpression(Offset))
4410 // The expression has to be a constant. Memory references with relocations
4411 // don't come through here, as they use the <label> forms of the relevant
4413 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4415 return Error (E, "constant expression expected");
4417 // If the constant was #-0, represent it as INT32_MIN.
4418 int32_t Val = CE->getValue();
4419 if (isNegative && Val == 0)
4420 CE = MCConstantExpr::Create(INT32_MIN, getContext());
4422 // Now we should have the closing ']'
4423 if (Parser.getTok().isNot(AsmToken::RBrac))
4424 return Error(Parser.getTok().getLoc(), "']' expected");
4425 E = Parser.getTok().getEndLoc();
4426 Parser.Lex(); // Eat right bracket token.
4428 // Don't worry about range checking the value here. That's handled by
4429 // the is*() predicates.
4430 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4431 ARM_AM::no_shift, 0, 0,
4434 // If there's a pre-indexing writeback marker, '!', just add it as a token
4436 if (Parser.getTok().is(AsmToken::Exclaim)) {
4437 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4438 Parser.Lex(); // Eat the '!'.
4444 // The register offset is optionally preceded by a '+' or '-'
4445 bool isNegative = false;
4446 if (Parser.getTok().is(AsmToken::Minus)) {
4448 Parser.Lex(); // Eat the '-'.
4449 } else if (Parser.getTok().is(AsmToken::Plus)) {
4451 Parser.Lex(); // Eat the '+'.
4454 E = Parser.getTok().getLoc();
4455 int OffsetRegNum = tryParseRegister();
4456 if (OffsetRegNum == -1)
4457 return Error(E, "register expected");
4459 // If there's a shift operator, handle it.
4460 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4461 unsigned ShiftImm = 0;
4462 if (Parser.getTok().is(AsmToken::Comma)) {
4463 Parser.Lex(); // Eat the ','.
4464 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4468 // Now we should have the closing ']'
4469 if (Parser.getTok().isNot(AsmToken::RBrac))
4470 return Error(Parser.getTok().getLoc(), "']' expected");
4471 E = Parser.getTok().getEndLoc();
4472 Parser.Lex(); // Eat right bracket token.
4474 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4475 ShiftType, ShiftImm, 0, isNegative,
4478 // If there's a pre-indexing writeback marker, '!', just add it as a token
4480 if (Parser.getTok().is(AsmToken::Exclaim)) {
4481 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4482 Parser.Lex(); // Eat the '!'.
4488 /// parseMemRegOffsetShift - one of these two:
4489 /// ( lsl | lsr | asr | ror ) , # shift_amount
4491 /// return true if it parses a shift otherwise it returns false.
4492 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4494 SMLoc Loc = Parser.getTok().getLoc();
4495 const AsmToken &Tok = Parser.getTok();
4496 if (Tok.isNot(AsmToken::Identifier))
4498 StringRef ShiftName = Tok.getString();
4499 if (ShiftName == "lsl" || ShiftName == "LSL" ||
4500 ShiftName == "asl" || ShiftName == "ASL")
4502 else if (ShiftName == "lsr" || ShiftName == "LSR")
4504 else if (ShiftName == "asr" || ShiftName == "ASR")
4506 else if (ShiftName == "ror" || ShiftName == "ROR")
4508 else if (ShiftName == "rrx" || ShiftName == "RRX")
4511 return Error(Loc, "illegal shift operator");
4512 Parser.Lex(); // Eat shift type token.
4514 // rrx stands alone.
4516 if (St != ARM_AM::rrx) {
4517 Loc = Parser.getTok().getLoc();
4518 // A '#' and a shift amount.
4519 const AsmToken &HashTok = Parser.getTok();
4520 if (HashTok.isNot(AsmToken::Hash) &&
4521 HashTok.isNot(AsmToken::Dollar))
4522 return Error(HashTok.getLoc(), "'#' expected");
4523 Parser.Lex(); // Eat hash token.
4526 if (getParser().parseExpression(Expr))
4528 // Range check the immediate.
4529 // lsl, ror: 0 <= imm <= 31
4530 // lsr, asr: 0 <= imm <= 32
4531 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4533 return Error(Loc, "shift amount must be an immediate");
4534 int64_t Imm = CE->getValue();
4536 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4537 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4538 return Error(Loc, "immediate shift value out of range");
4539 // If <ShiftTy> #0, turn it into a no_shift.
4542 // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4551 /// parseFPImm - A floating point immediate expression operand.
4552 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4553 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4554 // Anything that can accept a floating point constant as an operand
4555 // needs to go through here, as the regular parseExpression is
4558 // This routine still creates a generic Immediate operand, containing
4559 // a bitcast of the 64-bit floating point value. The various operands
4560 // that accept floats can check whether the value is valid for them
4561 // via the standard is*() predicates.
4563 SMLoc S = Parser.getTok().getLoc();
4565 if (Parser.getTok().isNot(AsmToken::Hash) &&
4566 Parser.getTok().isNot(AsmToken::Dollar))
4567 return MatchOperand_NoMatch;
4569 // Disambiguate the VMOV forms that can accept an FP immediate.
4570 // vmov.f32 <sreg>, #imm
4571 // vmov.f64 <dreg>, #imm
4572 // vmov.f32 <dreg>, #imm @ vector f32x2
4573 // vmov.f32 <qreg>, #imm @ vector f32x4
4575 // There are also the NEON VMOV instructions which expect an
4576 // integer constant. Make sure we don't try to parse an FPImm
4578 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4579 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4580 bool isVmovf = TyOp->isToken() && (TyOp->getToken() == ".f32" ||
4581 TyOp->getToken() == ".f64");
4582 ARMOperand *Mnemonic = static_cast<ARMOperand*>(Operands[0]);
4583 bool isFconst = Mnemonic->isToken() && (Mnemonic->getToken() == "fconstd" ||
4584 Mnemonic->getToken() == "fconsts");
4585 if (!(isVmovf || isFconst))
4586 return MatchOperand_NoMatch;
4588 Parser.Lex(); // Eat '#' or '$'.
4590 // Handle negation, as that still comes through as a separate token.
4591 bool isNegative = false;
4592 if (Parser.getTok().is(AsmToken::Minus)) {
4596 const AsmToken &Tok = Parser.getTok();
4597 SMLoc Loc = Tok.getLoc();
4598 if (Tok.is(AsmToken::Real) && isVmovf) {
4599 APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4600 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4601 // If we had a '-' in front, toggle the sign bit.
4602 IntVal ^= (uint64_t)isNegative << 31;
4603 Parser.Lex(); // Eat the token.
4604 Operands.push_back(ARMOperand::CreateImm(
4605 MCConstantExpr::Create(IntVal, getContext()),
4606 S, Parser.getTok().getLoc()));
4607 return MatchOperand_Success;
4609 // Also handle plain integers. Instructions which allow floating point
4610 // immediates also allow a raw encoded 8-bit value.
4611 if (Tok.is(AsmToken::Integer) && isFconst) {
4612 int64_t Val = Tok.getIntVal();
4613 Parser.Lex(); // Eat the token.
4614 if (Val > 255 || Val < 0) {
4615 Error(Loc, "encoded floating point value out of range");
4616 return MatchOperand_ParseFail;
4618 float RealVal = ARM_AM::getFPImmFloat(Val);
4619 Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
4621 Operands.push_back(ARMOperand::CreateImm(
4622 MCConstantExpr::Create(Val, getContext()), S,
4623 Parser.getTok().getLoc()));
4624 return MatchOperand_Success;
4627 Error(Loc, "invalid floating point immediate");
4628 return MatchOperand_ParseFail;
4631 /// Parse a arm instruction operand. For now this parses the operand regardless
4632 /// of the mnemonic.
4633 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4634 StringRef Mnemonic) {
4637 // Check if the current operand has a custom associated parser, if so, try to
4638 // custom parse the operand, or fallback to the general approach.
4639 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4640 if (ResTy == MatchOperand_Success)
4642 // If there wasn't a custom match, try the generic matcher below. Otherwise,
4643 // there was a match, but an error occurred, in which case, just return that
4644 // the operand parsing failed.
4645 if (ResTy == MatchOperand_ParseFail)
4648 switch (getLexer().getKind()) {
4650 Error(Parser.getTok().getLoc(), "unexpected token in operand");
4652 case AsmToken::Identifier: {
4653 // If we've seen a branch mnemonic, the next operand must be a label. This
4654 // is true even if the label is a register name. So "br r1" means branch to
4656 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
4658 if (!tryParseRegisterWithWriteBack(Operands))
4660 int Res = tryParseShiftRegister(Operands);
4661 if (Res == 0) // success
4663 else if (Res == -1) // irrecoverable error
4665 // If this is VMRS, check for the apsr_nzcv operand.
4666 if (Mnemonic == "vmrs" &&
4667 Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4668 S = Parser.getTok().getLoc();
4670 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4675 // Fall though for the Identifier case that is not a register or a
4678 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
4679 case AsmToken::Integer: // things like 1f and 2b as a branch targets
4680 case AsmToken::String: // quoted label names.
4681 case AsmToken::Dot: { // . as a branch target
4682 // This was not a register so parse other operands that start with an
4683 // identifier (like labels) as expressions and create them as immediates.
4684 const MCExpr *IdVal;
4685 S = Parser.getTok().getLoc();
4686 if (getParser().parseExpression(IdVal))
4688 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4689 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4692 case AsmToken::LBrac:
4693 return parseMemory(Operands);
4694 case AsmToken::LCurly:
4695 return parseRegisterList(Operands);
4696 case AsmToken::Dollar:
4697 case AsmToken::Hash: {
4698 // #42 -> immediate.
4699 S = Parser.getTok().getLoc();
4702 if (Parser.getTok().isNot(AsmToken::Colon)) {
4703 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4704 const MCExpr *ImmVal;
4705 if (getParser().parseExpression(ImmVal))
4707 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4709 int32_t Val = CE->getValue();
4710 if (isNegative && Val == 0)
4711 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4713 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4714 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4716 // There can be a trailing '!' on operands that we want as a separate
4717 // '!' Token operand. Handle that here. For example, the compatibility
4718 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
4719 if (Parser.getTok().is(AsmToken::Exclaim)) {
4720 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
4721 Parser.getTok().getLoc()));
4722 Parser.Lex(); // Eat exclaim token
4726 // w/ a ':' after the '#', it's just like a plain ':'.
4729 case AsmToken::Colon: {
4730 // ":lower16:" and ":upper16:" expression prefixes
4731 // FIXME: Check it's an expression prefix,
4732 // e.g. (FOO - :lower16:BAR) isn't legal.
4733 ARMMCExpr::VariantKind RefKind;
4734 if (parsePrefix(RefKind))
4737 const MCExpr *SubExprVal;
4738 if (getParser().parseExpression(SubExprVal))
4741 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4743 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4744 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4747 case AsmToken::Equal: {
4748 if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
4749 return Error(Parser.getTok().getLoc(), "unexpected token in operand");
4751 Parser.Lex(); // Eat '='
4752 const MCExpr *SubExprVal;
4753 if (getParser().parseExpression(SubExprVal))
4755 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4757 const MCExpr *CPLoc = getTargetStreamer().addConstantPoolEntry(SubExprVal);
4758 Operands.push_back(ARMOperand::CreateImm(CPLoc, S, E));
4764 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4765 // :lower16: and :upper16:.
4766 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4767 RefKind = ARMMCExpr::VK_ARM_None;
4769 // consume an optional '#' (GNU compatibility)
4770 if (getLexer().is(AsmToken::Hash))
4773 // :lower16: and :upper16: modifiers
4774 assert(getLexer().is(AsmToken::Colon) && "expected a :");
4775 Parser.Lex(); // Eat ':'
4777 if (getLexer().isNot(AsmToken::Identifier)) {
4778 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4782 StringRef IDVal = Parser.getTok().getIdentifier();
4783 if (IDVal == "lower16") {
4784 RefKind = ARMMCExpr::VK_ARM_LO16;
4785 } else if (IDVal == "upper16") {
4786 RefKind = ARMMCExpr::VK_ARM_HI16;
4788 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4793 if (getLexer().isNot(AsmToken::Colon)) {
4794 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4797 Parser.Lex(); // Eat the last ':'
4801 /// \brief Given a mnemonic, split out possible predication code and carry
4802 /// setting letters to form a canonical mnemonic and flags.
4804 // FIXME: Would be nice to autogen this.
4805 // FIXME: This is a bit of a maze of special cases.
4806 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4807 unsigned &PredicationCode,
4809 unsigned &ProcessorIMod,
4810 StringRef &ITMask) {
4811 PredicationCode = ARMCC::AL;
4812 CarrySetting = false;
4815 // Ignore some mnemonics we know aren't predicated forms.
4817 // FIXME: Would be nice to autogen this.
4818 if ((Mnemonic == "movs" && isThumb()) ||
4819 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
4820 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
4821 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
4822 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
4823 Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" ||
4824 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
4825 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
4826 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4827 Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
4828 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" ||
4829 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
4830 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel"))
4833 // First, split out any predication code. Ignore mnemonics we know aren't
4834 // predicated but do have a carry-set and so weren't caught above.
4835 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4836 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4837 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4838 Mnemonic != "sbcs" && Mnemonic != "rscs") {
4839 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4840 .Case("eq", ARMCC::EQ)
4841 .Case("ne", ARMCC::NE)
4842 .Case("hs", ARMCC::HS)
4843 .Case("cs", ARMCC::HS)
4844 .Case("lo", ARMCC::LO)
4845 .Case("cc", ARMCC::LO)
4846 .Case("mi", ARMCC::MI)
4847 .Case("pl", ARMCC::PL)
4848 .Case("vs", ARMCC::VS)
4849 .Case("vc", ARMCC::VC)
4850 .Case("hi", ARMCC::HI)
4851 .Case("ls", ARMCC::LS)
4852 .Case("ge", ARMCC::GE)
4853 .Case("lt", ARMCC::LT)
4854 .Case("gt", ARMCC::GT)
4855 .Case("le", ARMCC::LE)
4856 .Case("al", ARMCC::AL)
4859 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4860 PredicationCode = CC;
4864 // Next, determine if we have a carry setting bit. We explicitly ignore all
4865 // the instructions we know end in 's'.
4866 if (Mnemonic.endswith("s") &&
4867 !(Mnemonic == "cps" || Mnemonic == "mls" ||
4868 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4869 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4870 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4871 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4872 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4873 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4874 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
4875 Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
4876 (Mnemonic == "movs" && isThumb()))) {
4877 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4878 CarrySetting = true;
4881 // The "cps" instruction can have a interrupt mode operand which is glued into
4882 // the mnemonic. Check if this is the case, split it and parse the imod op
4883 if (Mnemonic.startswith("cps")) {
4884 // Split out any imod code.
4886 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4887 .Case("ie", ARM_PROC::IE)
4888 .Case("id", ARM_PROC::ID)
4891 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4892 ProcessorIMod = IMod;
4896 // The "it" instruction has the condition mask on the end of the mnemonic.
4897 if (Mnemonic.startswith("it")) {
4898 ITMask = Mnemonic.slice(2, Mnemonic.size());
4899 Mnemonic = Mnemonic.slice(0, 2);
4905 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
4906 /// inclusion of carry set or predication code operands.
4908 // FIXME: It would be nice to autogen this.
4910 getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
4911 bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) {
4912 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4913 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4914 Mnemonic == "add" || Mnemonic == "adc" ||
4915 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4916 Mnemonic == "orr" || Mnemonic == "mvn" ||
4917 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4918 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4919 Mnemonic == "vfm" || Mnemonic == "vfnm" ||
4920 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4921 Mnemonic == "mla" || Mnemonic == "smlal" ||
4922 Mnemonic == "umlal" || Mnemonic == "umull"))) {
4923 CanAcceptCarrySet = true;
4925 CanAcceptCarrySet = false;
4927 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
4928 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
4929 Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic.startswith("crc32") ||
4930 Mnemonic.startswith("cps") || Mnemonic.startswith("vsel") ||
4931 Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
4932 Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
4933 Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
4934 Mnemonic == "vrintm" || Mnemonic.startswith("aes") ||
4935 Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
4936 (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) {
4937 // These mnemonics are never predicable
4938 CanAcceptPredicationCode = false;
4939 } else if (!isThumb()) {
4940 // Some instructions are only predicable in Thumb mode
4941 CanAcceptPredicationCode
4942 = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
4943 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
4944 Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
4945 Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
4946 Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
4947 Mnemonic != "stc2" && Mnemonic != "stc2l" &&
4948 !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
4949 } else if (isThumbOne()) {
4951 CanAcceptPredicationCode = Mnemonic != "movs";
4953 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
4955 CanAcceptPredicationCode = true;
4958 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4959 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4960 // FIXME: This is all horribly hacky. We really need a better way to deal
4961 // with optional operands like this in the matcher table.
4963 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4964 // another does not. Specifically, the MOVW instruction does not. So we
4965 // special case it here and remove the defaulted (non-setting) cc_out
4966 // operand if that's the instruction we're trying to match.
4968 // We do this as post-processing of the explicit operands rather than just
4969 // conditionally adding the cc_out in the first place because we need
4970 // to check the type of the parsed immediate operand.
4971 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4972 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4973 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4974 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4977 // Register-register 'add' for thumb does not have a cc_out operand
4978 // when there are only two register operands.
4979 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4980 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4981 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4982 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4984 // Register-register 'add' for thumb does not have a cc_out operand
4985 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4986 // have to check the immediate range here since Thumb2 has a variant
4987 // that can handle a different range and has a cc_out operand.
4988 if (((isThumb() && Mnemonic == "add") ||
4989 (isThumbTwo() && Mnemonic == "sub")) &&
4990 Operands.size() == 6 &&
4991 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4992 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4993 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4994 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4995 ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
4996 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4998 // For Thumb2, add/sub immediate does not have a cc_out operand for the
4999 // imm0_4095 variant. That's the least-preferred variant when
5000 // selecting via the generic "add" mnemonic, so to know that we
5001 // should remove the cc_out operand, we have to explicitly check that
5002 // it's not one of the other variants. Ugh.
5003 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
5004 Operands.size() == 6 &&
5005 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5006 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5007 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5008 // Nest conditions rather than one big 'if' statement for readability.
5010 // If both registers are low, we're in an IT block, and the immediate is
5011 // in range, we should use encoding T1 instead, which has a cc_out.
5013 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
5014 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
5015 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
5017 // Check against T3. If the second register is the PC, this is an
5018 // alternate form of ADR, which uses encoding T4, so check for that too.
5019 if (static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
5020 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
5023 // Otherwise, we use encoding T4, which does not have a cc_out
5028 // The thumb2 multiply instruction doesn't have a CCOut register, so
5029 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
5030 // use the 16-bit encoding or not.
5031 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5032 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5033 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5034 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5035 static_cast<ARMOperand*>(Operands[5])->isReg() &&
5036 // If the registers aren't low regs, the destination reg isn't the
5037 // same as one of the source regs, or the cc_out operand is zero
5038 // outside of an IT block, we have to use the 32-bit encoding, so
5039 // remove the cc_out operand.
5040 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
5041 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
5042 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
5044 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
5045 static_cast<ARMOperand*>(Operands[5])->getReg() &&
5046 static_cast<ARMOperand*>(Operands[3])->getReg() !=
5047 static_cast<ARMOperand*>(Operands[4])->getReg())))
5050 // Also check the 'mul' syntax variant that doesn't specify an explicit
5051 // destination register.
5052 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5053 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5054 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5055 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5056 // If the registers aren't low regs or the cc_out operand is zero
5057 // outside of an IT block, we have to use the 32-bit encoding, so
5058 // remove the cc_out operand.
5059 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
5060 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
5066 // Register-register 'add/sub' for thumb does not have a cc_out operand
5067 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5068 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
5069 // right, this will result in better diagnostics (which operand is off)
5071 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
5072 (Operands.size() == 5 || Operands.size() == 6) &&
5073 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5074 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
5075 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5076 (static_cast<ARMOperand*>(Operands[4])->isImm() ||
5077 (Operands.size() == 6 &&
5078 static_cast<ARMOperand*>(Operands[5])->isImm())))
5084 bool ARMAsmParser::shouldOmitPredicateOperand(
5085 StringRef Mnemonic, SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
5086 // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
5087 unsigned RegIdx = 3;
5088 if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
5089 static_cast<ARMOperand *>(Operands[2])->getToken() == ".f32") {
5090 if (static_cast<ARMOperand *>(Operands[3])->isToken() &&
5091 static_cast<ARMOperand *>(Operands[3])->getToken() == ".f32")
5094 if (static_cast<ARMOperand *>(Operands[RegIdx])->isReg() &&
5095 (ARMMCRegisterClasses[ARM::DPRRegClassID]
5096 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg()) ||
5097 ARMMCRegisterClasses[ARM::QPRRegClassID]
5098 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg())))
5104 static bool isDataTypeToken(StringRef Tok) {
5105 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5106 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5107 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5108 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5109 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5110 Tok == ".f" || Tok == ".d";
5113 // FIXME: This bit should probably be handled via an explicit match class
5114 // in the .td files that matches the suffix instead of having it be
5115 // a literal string token the way it is now.
5116 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5117 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5119 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
5120 unsigned VariantID);
5122 static bool RequiresVFPRegListValidation(StringRef Inst,
5123 bool &AcceptSinglePrecisionOnly,
5124 bool &AcceptDoublePrecisionOnly) {
5125 if (Inst.size() < 7)
5128 if (Inst.startswith("fldm") || Inst.startswith("fstm")) {
5129 StringRef AddressingMode = Inst.substr(4, 2);
5130 if (AddressingMode == "ia" || AddressingMode == "db" ||
5131 AddressingMode == "ea" || AddressingMode == "fd") {
5132 AcceptSinglePrecisionOnly = Inst[6] == 's';
5133 AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x';
5141 /// Parse an arm instruction mnemonic followed by its operands.
5142 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5144 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5145 // FIXME: Can this be done via tablegen in some fashion?
5146 bool RequireVFPRegisterListCheck;
5147 bool AcceptSinglePrecisionOnly;
5148 bool AcceptDoublePrecisionOnly;
5149 RequireVFPRegisterListCheck =
5150 RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly,
5151 AcceptDoublePrecisionOnly);
5153 // Apply mnemonic aliases before doing anything else, as the destination
5154 // mnemonic may include suffices and we want to handle them normally.
5155 // The generic tblgen'erated code does this later, at the start of
5156 // MatchInstructionImpl(), but that's too late for aliases that include
5157 // any sort of suffix.
5158 unsigned AvailableFeatures = getAvailableFeatures();
5159 unsigned AssemblerDialect = getParser().getAssemblerDialect();
5160 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5162 // First check for the ARM-specific .req directive.
5163 if (Parser.getTok().is(AsmToken::Identifier) &&
5164 Parser.getTok().getIdentifier() == ".req") {
5165 parseDirectiveReq(Name, NameLoc);
5166 // We always return 'error' for this, as we're done with this
5167 // statement and don't need to match the 'instruction."
5171 // Create the leading tokens for the mnemonic, split by '.' characters.
5172 size_t Start = 0, Next = Name.find('.');
5173 StringRef Mnemonic = Name.slice(Start, Next);
5175 // Split out the predication code and carry setting flag from the mnemonic.
5176 unsigned PredicationCode;
5177 unsigned ProcessorIMod;
5180 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5181 ProcessorIMod, ITMask);
5183 // In Thumb1, only the branch (B) instruction can be predicated.
5184 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5185 Parser.eatToEndOfStatement();
5186 return Error(NameLoc, "conditional execution not supported in Thumb1");
5189 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5191 // Handle the IT instruction ITMask. Convert it to a bitmask. This
5192 // is the mask as it will be for the IT encoding if the conditional
5193 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5194 // where the conditional bit0 is zero, the instruction post-processing
5195 // will adjust the mask accordingly.
5196 if (Mnemonic == "it") {
5197 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5198 if (ITMask.size() > 3) {
5199 Parser.eatToEndOfStatement();
5200 return Error(Loc, "too many conditions on IT instruction");
5203 for (unsigned i = ITMask.size(); i != 0; --i) {
5204 char pos = ITMask[i - 1];
5205 if (pos != 't' && pos != 'e') {
5206 Parser.eatToEndOfStatement();
5207 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5210 if (ITMask[i - 1] == 't')
5213 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5216 // FIXME: This is all a pretty gross hack. We should automatically handle
5217 // optional operands like this via tblgen.
5219 // Next, add the CCOut and ConditionCode operands, if needed.
5221 // For mnemonics which can ever incorporate a carry setting bit or predication
5222 // code, our matching model involves us always generating CCOut and
5223 // ConditionCode operands to match the mnemonic "as written" and then we let
5224 // the matcher deal with finding the right instruction or generating an
5225 // appropriate error.
5226 bool CanAcceptCarrySet, CanAcceptPredicationCode;
5227 getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
5229 // If we had a carry-set on an instruction that can't do that, issue an
5231 if (!CanAcceptCarrySet && CarrySetting) {
5232 Parser.eatToEndOfStatement();
5233 return Error(NameLoc, "instruction '" + Mnemonic +
5234 "' can not set flags, but 's' suffix specified");
5236 // If we had a predication code on an instruction that can't do that, issue an
5238 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5239 Parser.eatToEndOfStatement();
5240 return Error(NameLoc, "instruction '" + Mnemonic +
5241 "' is not predicable, but condition code specified");
5244 // Add the carry setting operand, if necessary.
5245 if (CanAcceptCarrySet) {
5246 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5247 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5251 // Add the predication code operand, if necessary.
5252 if (CanAcceptPredicationCode) {
5253 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5255 Operands.push_back(ARMOperand::CreateCondCode(
5256 ARMCC::CondCodes(PredicationCode), Loc));
5259 // Add the processor imod operand, if necessary.
5260 if (ProcessorIMod) {
5261 Operands.push_back(ARMOperand::CreateImm(
5262 MCConstantExpr::Create(ProcessorIMod, getContext()),
5266 // Add the remaining tokens in the mnemonic.
5267 while (Next != StringRef::npos) {
5269 Next = Name.find('.', Start + 1);
5270 StringRef ExtraToken = Name.slice(Start, Next);
5272 // Some NEON instructions have an optional datatype suffix that is
5273 // completely ignored. Check for that.
5274 if (isDataTypeToken(ExtraToken) &&
5275 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5278 // For for ARM mode generate an error if the .n qualifier is used.
5279 if (ExtraToken == ".n" && !isThumb()) {
5280 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5281 Parser.eatToEndOfStatement();
5282 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5286 // The .n qualifier is always discarded as that is what the tables
5287 // and matcher expect. In ARM mode the .w qualifier has no effect,
5288 // so discard it to avoid errors that can be caused by the matcher.
5289 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5290 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5291 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5295 // Read the remaining operands.
5296 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5297 // Read the first operand.
5298 if (parseOperand(Operands, Mnemonic)) {
5299 Parser.eatToEndOfStatement();
5303 while (getLexer().is(AsmToken::Comma)) {
5304 Parser.Lex(); // Eat the comma.
5306 // Parse and remember the operand.
5307 if (parseOperand(Operands, Mnemonic)) {
5308 Parser.eatToEndOfStatement();
5314 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5315 SMLoc Loc = getLexer().getLoc();
5316 Parser.eatToEndOfStatement();
5317 return Error(Loc, "unexpected token in argument list");
5320 Parser.Lex(); // Consume the EndOfStatement
5322 if (RequireVFPRegisterListCheck) {
5323 ARMOperand *Op = static_cast<ARMOperand*>(Operands.back());
5324 if (AcceptSinglePrecisionOnly && !Op->isSPRRegList())
5325 return Error(Op->getStartLoc(),
5326 "VFP/Neon single precision register expected");
5327 if (AcceptDoublePrecisionOnly && !Op->isDPRRegList())
5328 return Error(Op->getStartLoc(),
5329 "VFP/Neon double precision register expected");
5332 // Some instructions, mostly Thumb, have forms for the same mnemonic that
5333 // do and don't have a cc_out optional-def operand. With some spot-checks
5334 // of the operand list, we can figure out which variant we're trying to
5335 // parse and adjust accordingly before actually matching. We shouldn't ever
5336 // try to remove a cc_out operand that was explicitly set on the the
5337 // mnemonic, of course (CarrySetting == true). Reason number #317 the
5338 // table driven matcher doesn't fit well with the ARM instruction set.
5339 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5340 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5341 Operands.erase(Operands.begin() + 1);
5345 // Some instructions have the same mnemonic, but don't always
5346 // have a predicate. Distinguish them here and delete the
5347 // predicate if needed.
5348 if (shouldOmitPredicateOperand(Mnemonic, Operands)) {
5349 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5350 Operands.erase(Operands.begin() + 1);
5354 // ARM mode 'blx' need special handling, as the register operand version
5355 // is predicable, but the label operand version is not. So, we can't rely
5356 // on the Mnemonic based checking to correctly figure out when to put
5357 // a k_CondCode operand in the list. If we're trying to match the label
5358 // version, remove the k_CondCode operand here.
5359 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5360 static_cast<ARMOperand*>(Operands[2])->isImm()) {
5361 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5362 Operands.erase(Operands.begin() + 1);
5366 // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5367 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5368 // a single GPRPair reg operand is used in the .td file to replace the two
5369 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5370 // expressed as a GPRPair, so we have to manually merge them.
5371 // FIXME: We would really like to be able to tablegen'erate this.
5372 if (!isThumb() && Operands.size() > 4 &&
5373 (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
5374 Mnemonic == "stlexd")) {
5375 bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
5376 unsigned Idx = isLoad ? 2 : 3;
5377 ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]);
5378 ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]);
5380 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5381 // Adjust only if Op1 and Op2 are GPRs.
5382 if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) &&
5383 MRC.contains(Op2->getReg())) {
5384 unsigned Reg1 = Op1->getReg();
5385 unsigned Reg2 = Op2->getReg();
5386 unsigned Rt = MRI->getEncodingValue(Reg1);
5387 unsigned Rt2 = MRI->getEncodingValue(Reg2);
5389 // Rt2 must be Rt + 1 and Rt must be even.
5390 if (Rt + 1 != Rt2 || (Rt & 1)) {
5391 Error(Op2->getStartLoc(), isLoad ?
5392 "destination operands must be sequential" :
5393 "source operands must be sequential");
5396 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5397 &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5398 Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2);
5399 Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg(
5400 NewReg, Op1->getStartLoc(), Op2->getEndLoc()));
5406 // GNU Assembler extension (compatibility)
5407 if ((Mnemonic == "ldrd" || Mnemonic == "strd")) {
5408 ARMOperand *Op2 = static_cast<ARMOperand *>(Operands[2]);
5409 ARMOperand *Op3 = static_cast<ARMOperand *>(Operands[3]);
5411 assert(Op2->isReg() && "expected register argument");
5413 unsigned SuperReg = MRI->getMatchingSuperReg(
5414 Op2->getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID));
5416 assert(SuperReg && "expected register pair");
5418 unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1);
5420 Operands.insert(Operands.begin() + 3,
5421 ARMOperand::CreateReg(PairedReg,
5427 // FIXME: As said above, this is all a pretty gross hack. This instruction
5428 // does not fit with other "subs" and tblgen.
5429 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
5430 // so the Mnemonic is the original name "subs" and delete the predicate
5431 // operand so it will match the table entry.
5432 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
5433 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5434 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::PC &&
5435 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5436 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::LR &&
5437 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5438 ARMOperand *Op0 = static_cast<ARMOperand*>(Operands[0]);
5439 Operands.erase(Operands.begin());
5441 Operands.insert(Operands.begin(), ARMOperand::CreateToken(Name, NameLoc));
5443 ARMOperand *Op1 = static_cast<ARMOperand*>(Operands[1]);
5444 Operands.erase(Operands.begin() + 1);
5450 // Validate context-sensitive operand constraints.
5452 // return 'true' if register list contains non-low GPR registers,
5453 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5454 // 'containsReg' to true.
5455 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5456 unsigned HiReg, bool &containsReg) {
5457 containsReg = false;
5458 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5459 unsigned OpReg = Inst.getOperand(i).getReg();
5462 // Anything other than a low register isn't legal here.
5463 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5469 // Check if the specified regisgter is in the register list of the inst,
5470 // starting at the indicated operand number.
5471 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5472 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5473 unsigned OpReg = Inst.getOperand(i).getReg();
5480 // Return true if instruction has the interesting property of being
5481 // allowed in IT blocks, but not being predicable.
5482 static bool instIsBreakpoint(const MCInst &Inst) {
5483 return Inst.getOpcode() == ARM::tBKPT ||
5484 Inst.getOpcode() == ARM::BKPT ||
5485 Inst.getOpcode() == ARM::tHLT ||
5486 Inst.getOpcode() == ARM::HLT;
5490 // FIXME: We would really like to be able to tablegen'erate this.
5492 validateInstruction(MCInst &Inst,
5493 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5494 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
5495 SMLoc Loc = Operands[0]->getStartLoc();
5497 // Check the IT block state first.
5498 // NOTE: BKPT and HLT instructions have the interesting property of being
5499 // allowed in IT blocks, but not being predicable. They just always execute.
5500 if (inITBlock() && !instIsBreakpoint(Inst)) {
5502 if (ITState.FirstCond)
5503 ITState.FirstCond = false;
5505 Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5506 // The instruction must be predicable.
5507 if (!MCID.isPredicable())
5508 return Error(Loc, "instructions in IT block must be predicable");
5509 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5510 unsigned ITCond = Bit ? ITState.Cond :
5511 ARMCC::getOppositeCondition(ITState.Cond);
5512 if (Cond != ITCond) {
5513 // Find the condition code Operand to get its SMLoc information.
5515 for (unsigned I = 1; I < Operands.size(); ++I)
5516 if (static_cast<ARMOperand*>(Operands[I])->isCondCode())
5517 CondLoc = Operands[I]->getStartLoc();
5518 return Error(CondLoc, "incorrect condition in IT block; got '" +
5519 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5520 "', but expected '" +
5521 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5523 // Check for non-'al' condition codes outside of the IT block.
5524 } else if (isThumbTwo() && MCID.isPredicable() &&
5525 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5526 ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
5527 Inst.getOpcode() != ARM::t2Bcc)
5528 return Error(Loc, "predicated instructions must be in IT block");
5530 const unsigned Opcode = Inst.getOpcode();
5534 case ARM::LDRD_POST: {
5535 const unsigned RtReg = Inst.getOperand(0).getReg();
5538 if (RtReg == ARM::LR)
5539 return Error(Operands[3]->getStartLoc(),
5542 const unsigned Rt = MRI->getEncodingValue(RtReg);
5543 // Rt must be even-numbered.
5545 return Error(Operands[3]->getStartLoc(),
5546 "Rt must be even-numbered");
5548 // Rt2 must be Rt + 1.
5549 const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5551 return Error(Operands[3]->getStartLoc(),
5552 "destination operands must be sequential");
5554 if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) {
5555 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
5556 // For addressing modes with writeback, the base register needs to be
5557 // different from the destination registers.
5558 if (Rn == Rt || Rn == Rt2)
5559 return Error(Operands[3]->getStartLoc(),
5560 "base register needs to be different from destination "
5567 case ARM::t2LDRD_PRE:
5568 case ARM::t2LDRD_POST: {
5569 // Rt2 must be different from Rt.
5570 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5571 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5573 return Error(Operands[3]->getStartLoc(),
5574 "destination operands can't be identical");
5578 // Rt2 must be Rt + 1.
5579 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5580 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5582 return Error(Operands[3]->getStartLoc(),
5583 "source operands must be sequential");
5587 case ARM::STRD_POST: {
5588 // Rt2 must be Rt + 1.
5589 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5590 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5592 return Error(Operands[3]->getStartLoc(),
5593 "source operands must be sequential");
5598 // Width must be in range [1, 32-lsb].
5599 unsigned LSB = Inst.getOperand(2).getImm();
5600 unsigned Widthm1 = Inst.getOperand(3).getImm();
5601 if (Widthm1 >= 32 - LSB)
5602 return Error(Operands[5]->getStartLoc(),
5603 "bitfield width must be in range [1,32-lsb]");
5606 // Notionally handles ARM::tLDMIA_UPD too.
5608 // If we're parsing Thumb2, the .w variant is available and handles
5609 // most cases that are normally illegal for a Thumb1 LDM instruction.
5610 // We'll make the transformation in processInstruction() if necessary.
5612 // Thumb LDM instructions are writeback iff the base register is not
5613 // in the register list.
5614 unsigned Rn = Inst.getOperand(0).getReg();
5615 bool HasWritebackToken =
5616 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5617 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5618 bool ListContainsBase;
5619 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
5620 return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
5621 "registers must be in range r0-r7");
5622 // If we should have writeback, then there should be a '!' token.
5623 if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
5624 return Error(Operands[2]->getStartLoc(),
5625 "writeback operator '!' expected");
5626 // If we should not have writeback, there must not be a '!'. This is
5627 // true even for the 32-bit wide encodings.
5628 if (ListContainsBase && HasWritebackToken)
5629 return Error(Operands[3]->getStartLoc(),
5630 "writeback operator '!' not allowed when base register "
5631 "in register list");
5635 case ARM::LDMIA_UPD:
5636 case ARM::LDMDB_UPD:
5637 case ARM::LDMIB_UPD:
5638 case ARM::LDMDA_UPD:
5639 // ARM variants loading and updating the same register are only officially
5640 // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
5644 case ARM::t2LDMIA_UPD:
5645 case ARM::t2LDMDB_UPD:
5646 case ARM::t2STMIA_UPD:
5647 case ARM::t2STMDB_UPD: {
5648 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5649 return Error(Operands.back()->getStartLoc(),
5650 "writeback register not allowed in register list");
5653 case ARM::sysLDMIA_UPD:
5654 case ARM::sysLDMDA_UPD:
5655 case ARM::sysLDMDB_UPD:
5656 case ARM::sysLDMIB_UPD:
5657 if (!listContainsReg(Inst, 3, ARM::PC))
5658 return Error(Operands[4]->getStartLoc(),
5659 "writeback register only allowed on system LDM "
5660 "if PC in register-list");
5662 case ARM::sysSTMIA_UPD:
5663 case ARM::sysSTMDA_UPD:
5664 case ARM::sysSTMDB_UPD:
5665 case ARM::sysSTMIB_UPD:
5666 return Error(Operands[2]->getStartLoc(),
5667 "system STM cannot have writeback register");
5669 // The second source operand must be the same register as the destination
5672 // In this case, we must directly check the parsed operands because the
5673 // cvtThumbMultiply() function is written in such a way that it guarantees
5674 // this first statement is always true for the new Inst. Essentially, the
5675 // destination is unconditionally copied into the second source operand
5676 // without checking to see if it matches what we actually parsed.
5677 if (Operands.size() == 6 &&
5678 (((ARMOperand*)Operands[3])->getReg() !=
5679 ((ARMOperand*)Operands[5])->getReg()) &&
5680 (((ARMOperand*)Operands[3])->getReg() !=
5681 ((ARMOperand*)Operands[4])->getReg())) {
5682 return Error(Operands[3]->getStartLoc(),
5683 "destination register must match source register");
5687 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5688 // so only issue a diagnostic for thumb1. The instructions will be
5689 // switched to the t2 encodings in processInstruction() if necessary.
5691 bool ListContainsBase;
5692 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
5694 return Error(Operands[2]->getStartLoc(),
5695 "registers must be in range r0-r7 or pc");
5699 bool ListContainsBase;
5700 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
5702 return Error(Operands[2]->getStartLoc(),
5703 "registers must be in range r0-r7 or lr");
5706 case ARM::tSTMIA_UPD: {
5707 bool ListContainsBase, InvalidLowList;
5708 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
5709 0, ListContainsBase);
5710 if (InvalidLowList && !isThumbTwo())
5711 return Error(Operands[4]->getStartLoc(),
5712 "registers must be in range r0-r7");
5714 // This would be converted to a 32-bit stm, but that's not valid if the
5715 // writeback register is in the list.
5716 if (InvalidLowList && ListContainsBase)
5717 return Error(Operands[4]->getStartLoc(),
5718 "writeback operator '!' not allowed when base register "
5719 "in register list");
5722 case ARM::tADDrSP: {
5723 // If the non-SP source operand and the destination operand are not the
5724 // same, we need thumb2 (for the wide encoding), or we have an error.
5725 if (!isThumbTwo() &&
5726 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5727 return Error(Operands[4]->getStartLoc(),
5728 "source register must be the same as destination");
5732 // Final range checking for Thumb unconditional branch instructions.
5734 if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<11, 1>())
5735 return Error(Operands[2]->getStartLoc(), "branch target out of range");
5738 int op = (Operands[2]->isImm()) ? 2 : 3;
5739 if (!(static_cast<ARMOperand*>(Operands[op]))->isSignedOffset<24, 1>())
5740 return Error(Operands[op]->getStartLoc(), "branch target out of range");
5743 // Final range checking for Thumb conditional branch instructions.
5745 if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<8, 1>())
5746 return Error(Operands[2]->getStartLoc(), "branch target out of range");
5749 int Op = (Operands[2]->isImm()) ? 2 : 3;
5750 if (!(static_cast<ARMOperand*>(Operands[Op]))->isSignedOffset<20, 1>())
5751 return Error(Operands[Op]->getStartLoc(), "branch target out of range");
5759 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5761 default: llvm_unreachable("unexpected opcode!");
5763 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5764 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5765 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5766 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5767 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5768 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5769 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
5770 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5771 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5774 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5775 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5776 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5777 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5778 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5780 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5781 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5782 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5783 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5784 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5786 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
5787 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5788 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5789 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5790 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5793 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5794 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5795 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5796 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5797 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5798 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5799 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5800 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5801 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5802 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5803 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
5804 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5805 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5806 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5807 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5810 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5811 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5812 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5813 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5814 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5815 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5816 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5817 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5818 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5819 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5820 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5821 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5822 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
5823 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5824 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5825 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
5826 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5827 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5830 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5831 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5832 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5833 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5834 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5835 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5836 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5837 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5838 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5839 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5840 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
5841 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5842 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5843 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5844 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5847 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5848 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5849 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5850 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5851 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5852 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5853 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5854 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5855 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5856 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5857 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5858 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5859 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
5860 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5861 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5862 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
5863 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5864 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5868 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
5870 default: llvm_unreachable("unexpected opcode!");
5872 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5873 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5874 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5875 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5876 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5877 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5878 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
5879 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5880 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5883 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5884 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5885 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5886 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5887 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5888 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5889 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5890 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5891 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5892 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5893 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
5894 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5895 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5896 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5897 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5900 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5901 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5902 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5903 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5904 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5905 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5906 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5907 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5908 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5909 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5910 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5911 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5912 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
5913 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5914 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5915 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5916 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5917 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5920 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5921 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5922 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5923 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5924 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5925 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5926 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5927 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5928 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5929 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5930 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
5931 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5932 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5933 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5934 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5937 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5938 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5939 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5940 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5941 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5942 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5943 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5944 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5945 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5946 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5947 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5948 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5949 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
5950 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5951 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5952 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
5953 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5954 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
5957 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5958 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5959 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5960 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5961 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5962 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5963 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5964 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5965 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5966 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5967 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
5968 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5969 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5970 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5971 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5974 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5975 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5976 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5977 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5978 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5979 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5980 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5981 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5982 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5983 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
5984 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
5985 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5986 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
5987 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
5988 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
5989 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
5990 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
5991 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
5994 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5995 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5996 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5997 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5998 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5999 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6000 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
6001 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6002 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6003 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
6004 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6005 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6006 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
6007 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
6008 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
6009 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
6010 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
6011 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
6016 processInstruction(MCInst &Inst,
6017 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
6018 switch (Inst.getOpcode()) {
6019 // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
6020 case ARM::LDRT_POST:
6021 case ARM::LDRBT_POST: {
6022 const unsigned Opcode =
6023 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
6024 : ARM::LDRBT_POST_IMM;
6026 TmpInst.setOpcode(Opcode);
6027 TmpInst.addOperand(Inst.getOperand(0));
6028 TmpInst.addOperand(Inst.getOperand(1));
6029 TmpInst.addOperand(Inst.getOperand(1));
6030 TmpInst.addOperand(MCOperand::CreateReg(0));
6031 TmpInst.addOperand(MCOperand::CreateImm(0));
6032 TmpInst.addOperand(Inst.getOperand(2));
6033 TmpInst.addOperand(Inst.getOperand(3));
6037 // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
6038 case ARM::STRT_POST:
6039 case ARM::STRBT_POST: {
6040 const unsigned Opcode =
6041 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
6042 : ARM::STRBT_POST_IMM;
6044 TmpInst.setOpcode(Opcode);
6045 TmpInst.addOperand(Inst.getOperand(1));
6046 TmpInst.addOperand(Inst.getOperand(0));
6047 TmpInst.addOperand(Inst.getOperand(1));
6048 TmpInst.addOperand(MCOperand::CreateReg(0));
6049 TmpInst.addOperand(MCOperand::CreateImm(0));
6050 TmpInst.addOperand(Inst.getOperand(2));
6051 TmpInst.addOperand(Inst.getOperand(3));
6055 // Alias for alternate form of 'ADR Rd, #imm' instruction.
6057 if (Inst.getOperand(1).getReg() != ARM::PC ||
6058 Inst.getOperand(5).getReg() != 0)
6061 TmpInst.setOpcode(ARM::ADR);
6062 TmpInst.addOperand(Inst.getOperand(0));
6063 TmpInst.addOperand(Inst.getOperand(2));
6064 TmpInst.addOperand(Inst.getOperand(3));
6065 TmpInst.addOperand(Inst.getOperand(4));
6069 // Aliases for alternate PC+imm syntax of LDR instructions.
6070 case ARM::t2LDRpcrel:
6071 // Select the narrow version if the immediate will fit.
6072 if (Inst.getOperand(1).getImm() > 0 &&
6073 Inst.getOperand(1).getImm() <= 0xff &&
6074 !(static_cast<ARMOperand*>(Operands[2])->isToken() &&
6075 static_cast<ARMOperand*>(Operands[2])->getToken() == ".w"))
6076 Inst.setOpcode(ARM::tLDRpci);
6078 Inst.setOpcode(ARM::t2LDRpci);
6080 case ARM::t2LDRBpcrel:
6081 Inst.setOpcode(ARM::t2LDRBpci);
6083 case ARM::t2LDRHpcrel:
6084 Inst.setOpcode(ARM::t2LDRHpci);
6086 case ARM::t2LDRSBpcrel:
6087 Inst.setOpcode(ARM::t2LDRSBpci);
6089 case ARM::t2LDRSHpcrel:
6090 Inst.setOpcode(ARM::t2LDRSHpci);
6092 // Handle NEON VST complex aliases.
6093 case ARM::VST1LNdWB_register_Asm_8:
6094 case ARM::VST1LNdWB_register_Asm_16:
6095 case ARM::VST1LNdWB_register_Asm_32: {
6097 // Shuffle the operands around so the lane index operand is in the
6100 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6101 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6102 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6103 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6104 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6105 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6106 TmpInst.addOperand(Inst.getOperand(1)); // lane
6107 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6108 TmpInst.addOperand(Inst.getOperand(6));
6113 case ARM::VST2LNdWB_register_Asm_8:
6114 case ARM::VST2LNdWB_register_Asm_16:
6115 case ARM::VST2LNdWB_register_Asm_32:
6116 case ARM::VST2LNqWB_register_Asm_16:
6117 case ARM::VST2LNqWB_register_Asm_32: {
6119 // Shuffle the operands around so the lane index operand is in the
6122 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6123 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6124 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6125 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6126 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6127 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6128 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6130 TmpInst.addOperand(Inst.getOperand(1)); // lane
6131 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6132 TmpInst.addOperand(Inst.getOperand(6));
6137 case ARM::VST3LNdWB_register_Asm_8:
6138 case ARM::VST3LNdWB_register_Asm_16:
6139 case ARM::VST3LNdWB_register_Asm_32:
6140 case ARM::VST3LNqWB_register_Asm_16:
6141 case ARM::VST3LNqWB_register_Asm_32: {
6143 // Shuffle the operands around so the lane index operand is in the
6146 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6147 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6148 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6149 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6150 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6151 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6152 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6154 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6156 TmpInst.addOperand(Inst.getOperand(1)); // lane
6157 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6158 TmpInst.addOperand(Inst.getOperand(6));
6163 case ARM::VST4LNdWB_register_Asm_8:
6164 case ARM::VST4LNdWB_register_Asm_16:
6165 case ARM::VST4LNdWB_register_Asm_32:
6166 case ARM::VST4LNqWB_register_Asm_16:
6167 case ARM::VST4LNqWB_register_Asm_32: {
6169 // Shuffle the operands around so the lane index operand is in the
6172 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6173 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6174 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6175 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6176 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6177 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6178 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6180 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6182 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6184 TmpInst.addOperand(Inst.getOperand(1)); // lane
6185 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6186 TmpInst.addOperand(Inst.getOperand(6));
6191 case ARM::VST1LNdWB_fixed_Asm_8:
6192 case ARM::VST1LNdWB_fixed_Asm_16:
6193 case ARM::VST1LNdWB_fixed_Asm_32: {
6195 // Shuffle the operands around so the lane index operand is in the
6198 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6199 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6200 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6201 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6202 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6203 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6204 TmpInst.addOperand(Inst.getOperand(1)); // lane
6205 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6206 TmpInst.addOperand(Inst.getOperand(5));
6211 case ARM::VST2LNdWB_fixed_Asm_8:
6212 case ARM::VST2LNdWB_fixed_Asm_16:
6213 case ARM::VST2LNdWB_fixed_Asm_32:
6214 case ARM::VST2LNqWB_fixed_Asm_16:
6215 case ARM::VST2LNqWB_fixed_Asm_32: {
6217 // Shuffle the operands around so the lane index operand is in the
6220 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6221 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6222 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6223 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6224 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6225 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6226 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6228 TmpInst.addOperand(Inst.getOperand(1)); // lane
6229 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6230 TmpInst.addOperand(Inst.getOperand(5));
6235 case ARM::VST3LNdWB_fixed_Asm_8:
6236 case ARM::VST3LNdWB_fixed_Asm_16:
6237 case ARM::VST3LNdWB_fixed_Asm_32:
6238 case ARM::VST3LNqWB_fixed_Asm_16:
6239 case ARM::VST3LNqWB_fixed_Asm_32: {
6241 // Shuffle the operands around so the lane index operand is in the
6244 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6245 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6246 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6247 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6248 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6249 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6250 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6252 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6254 TmpInst.addOperand(Inst.getOperand(1)); // lane
6255 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6256 TmpInst.addOperand(Inst.getOperand(5));
6261 case ARM::VST4LNdWB_fixed_Asm_8:
6262 case ARM::VST4LNdWB_fixed_Asm_16:
6263 case ARM::VST4LNdWB_fixed_Asm_32:
6264 case ARM::VST4LNqWB_fixed_Asm_16:
6265 case ARM::VST4LNqWB_fixed_Asm_32: {
6267 // Shuffle the operands around so the lane index operand is in the
6270 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6271 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6272 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6273 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6274 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6275 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6276 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6278 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6280 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6282 TmpInst.addOperand(Inst.getOperand(1)); // lane
6283 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6284 TmpInst.addOperand(Inst.getOperand(5));
6289 case ARM::VST1LNdAsm_8:
6290 case ARM::VST1LNdAsm_16:
6291 case ARM::VST1LNdAsm_32: {
6293 // Shuffle the operands around so the lane index operand is in the
6296 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6297 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6298 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6299 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6300 TmpInst.addOperand(Inst.getOperand(1)); // lane
6301 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6302 TmpInst.addOperand(Inst.getOperand(5));
6307 case ARM::VST2LNdAsm_8:
6308 case ARM::VST2LNdAsm_16:
6309 case ARM::VST2LNdAsm_32:
6310 case ARM::VST2LNqAsm_16:
6311 case ARM::VST2LNqAsm_32: {
6313 // Shuffle the operands around so the lane index operand is in the
6316 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6317 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6318 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6319 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6320 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6322 TmpInst.addOperand(Inst.getOperand(1)); // lane
6323 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6324 TmpInst.addOperand(Inst.getOperand(5));
6329 case ARM::VST3LNdAsm_8:
6330 case ARM::VST3LNdAsm_16:
6331 case ARM::VST3LNdAsm_32:
6332 case ARM::VST3LNqAsm_16:
6333 case ARM::VST3LNqAsm_32: {
6335 // Shuffle the operands around so the lane index operand is in the
6338 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6339 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6340 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6341 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6342 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6344 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6346 TmpInst.addOperand(Inst.getOperand(1)); // lane
6347 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6348 TmpInst.addOperand(Inst.getOperand(5));
6353 case ARM::VST4LNdAsm_8:
6354 case ARM::VST4LNdAsm_16:
6355 case ARM::VST4LNdAsm_32:
6356 case ARM::VST4LNqAsm_16:
6357 case ARM::VST4LNqAsm_32: {
6359 // Shuffle the operands around so the lane index operand is in the
6362 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6363 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6364 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6365 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6366 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6368 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6370 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6372 TmpInst.addOperand(Inst.getOperand(1)); // lane
6373 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6374 TmpInst.addOperand(Inst.getOperand(5));
6379 // Handle NEON VLD complex aliases.
6380 case ARM::VLD1LNdWB_register_Asm_8:
6381 case ARM::VLD1LNdWB_register_Asm_16:
6382 case ARM::VLD1LNdWB_register_Asm_32: {
6384 // Shuffle the operands around so the lane index operand is in the
6387 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6388 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6389 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6390 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6391 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6392 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6393 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6394 TmpInst.addOperand(Inst.getOperand(1)); // lane
6395 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6396 TmpInst.addOperand(Inst.getOperand(6));
6401 case ARM::VLD2LNdWB_register_Asm_8:
6402 case ARM::VLD2LNdWB_register_Asm_16:
6403 case ARM::VLD2LNdWB_register_Asm_32:
6404 case ARM::VLD2LNqWB_register_Asm_16:
6405 case ARM::VLD2LNqWB_register_Asm_32: {
6407 // Shuffle the operands around so the lane index operand is in the
6410 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6411 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6412 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6414 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6415 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6416 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6417 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6418 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6419 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6421 TmpInst.addOperand(Inst.getOperand(1)); // lane
6422 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6423 TmpInst.addOperand(Inst.getOperand(6));
6428 case ARM::VLD3LNdWB_register_Asm_8:
6429 case ARM::VLD3LNdWB_register_Asm_16:
6430 case ARM::VLD3LNdWB_register_Asm_32:
6431 case ARM::VLD3LNqWB_register_Asm_16:
6432 case ARM::VLD3LNqWB_register_Asm_32: {
6434 // Shuffle the operands around so the lane index operand is in the
6437 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6438 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6439 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6441 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6443 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6444 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6445 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6446 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6447 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6448 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6450 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6452 TmpInst.addOperand(Inst.getOperand(1)); // lane
6453 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6454 TmpInst.addOperand(Inst.getOperand(6));
6459 case ARM::VLD4LNdWB_register_Asm_8:
6460 case ARM::VLD4LNdWB_register_Asm_16:
6461 case ARM::VLD4LNdWB_register_Asm_32:
6462 case ARM::VLD4LNqWB_register_Asm_16:
6463 case ARM::VLD4LNqWB_register_Asm_32: {
6465 // Shuffle the operands around so the lane index operand is in the
6468 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6469 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6470 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6472 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6474 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6476 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6477 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6478 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6479 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6480 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6481 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6483 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6485 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6487 TmpInst.addOperand(Inst.getOperand(1)); // lane
6488 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6489 TmpInst.addOperand(Inst.getOperand(6));
6494 case ARM::VLD1LNdWB_fixed_Asm_8:
6495 case ARM::VLD1LNdWB_fixed_Asm_16:
6496 case ARM::VLD1LNdWB_fixed_Asm_32: {
6498 // Shuffle the operands around so the lane index operand is in the
6501 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6502 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6503 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6504 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6505 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6506 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6507 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6508 TmpInst.addOperand(Inst.getOperand(1)); // lane
6509 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6510 TmpInst.addOperand(Inst.getOperand(5));
6515 case ARM::VLD2LNdWB_fixed_Asm_8:
6516 case ARM::VLD2LNdWB_fixed_Asm_16:
6517 case ARM::VLD2LNdWB_fixed_Asm_32:
6518 case ARM::VLD2LNqWB_fixed_Asm_16:
6519 case ARM::VLD2LNqWB_fixed_Asm_32: {
6521 // Shuffle the operands around so the lane index operand is in the
6524 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6525 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6526 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6528 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6529 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6530 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6531 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6532 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6533 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6535 TmpInst.addOperand(Inst.getOperand(1)); // lane
6536 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6537 TmpInst.addOperand(Inst.getOperand(5));
6542 case ARM::VLD3LNdWB_fixed_Asm_8:
6543 case ARM::VLD3LNdWB_fixed_Asm_16:
6544 case ARM::VLD3LNdWB_fixed_Asm_32:
6545 case ARM::VLD3LNqWB_fixed_Asm_16:
6546 case ARM::VLD3LNqWB_fixed_Asm_32: {
6548 // Shuffle the operands around so the lane index operand is in the
6551 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6552 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6553 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6555 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6557 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6558 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6559 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6560 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6561 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6562 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6564 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6566 TmpInst.addOperand(Inst.getOperand(1)); // lane
6567 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6568 TmpInst.addOperand(Inst.getOperand(5));
6573 case ARM::VLD4LNdWB_fixed_Asm_8:
6574 case ARM::VLD4LNdWB_fixed_Asm_16:
6575 case ARM::VLD4LNdWB_fixed_Asm_32:
6576 case ARM::VLD4LNqWB_fixed_Asm_16:
6577 case ARM::VLD4LNqWB_fixed_Asm_32: {
6579 // Shuffle the operands around so the lane index operand is in the
6582 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6583 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6584 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6586 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6588 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6590 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6591 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6592 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6593 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6594 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6595 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6597 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6599 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6601 TmpInst.addOperand(Inst.getOperand(1)); // lane
6602 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6603 TmpInst.addOperand(Inst.getOperand(5));
6608 case ARM::VLD1LNdAsm_8:
6609 case ARM::VLD1LNdAsm_16:
6610 case ARM::VLD1LNdAsm_32: {
6612 // Shuffle the operands around so the lane index operand is in the
6615 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6616 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6617 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6618 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6619 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6620 TmpInst.addOperand(Inst.getOperand(1)); // lane
6621 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6622 TmpInst.addOperand(Inst.getOperand(5));
6627 case ARM::VLD2LNdAsm_8:
6628 case ARM::VLD2LNdAsm_16:
6629 case ARM::VLD2LNdAsm_32:
6630 case ARM::VLD2LNqAsm_16:
6631 case ARM::VLD2LNqAsm_32: {
6633 // Shuffle the operands around so the lane index operand is in the
6636 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6637 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6638 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6640 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6641 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6642 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6643 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6645 TmpInst.addOperand(Inst.getOperand(1)); // lane
6646 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6647 TmpInst.addOperand(Inst.getOperand(5));
6652 case ARM::VLD3LNdAsm_8:
6653 case ARM::VLD3LNdAsm_16:
6654 case ARM::VLD3LNdAsm_32:
6655 case ARM::VLD3LNqAsm_16:
6656 case ARM::VLD3LNqAsm_32: {
6658 // Shuffle the operands around so the lane index operand is in the
6661 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6662 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6663 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6665 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6667 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6668 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6669 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6670 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6672 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6674 TmpInst.addOperand(Inst.getOperand(1)); // lane
6675 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6676 TmpInst.addOperand(Inst.getOperand(5));
6681 case ARM::VLD4LNdAsm_8:
6682 case ARM::VLD4LNdAsm_16:
6683 case ARM::VLD4LNdAsm_32:
6684 case ARM::VLD4LNqAsm_16:
6685 case ARM::VLD4LNqAsm_32: {
6687 // Shuffle the operands around so the lane index operand is in the
6690 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6691 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6692 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6694 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6696 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6698 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6699 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6700 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6701 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6703 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6705 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6707 TmpInst.addOperand(Inst.getOperand(1)); // lane
6708 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6709 TmpInst.addOperand(Inst.getOperand(5));
6714 // VLD3DUP single 3-element structure to all lanes instructions.
6715 case ARM::VLD3DUPdAsm_8:
6716 case ARM::VLD3DUPdAsm_16:
6717 case ARM::VLD3DUPdAsm_32:
6718 case ARM::VLD3DUPqAsm_8:
6719 case ARM::VLD3DUPqAsm_16:
6720 case ARM::VLD3DUPqAsm_32: {
6723 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6724 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6725 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6727 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6729 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6730 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6731 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6732 TmpInst.addOperand(Inst.getOperand(4));
6737 case ARM::VLD3DUPdWB_fixed_Asm_8:
6738 case ARM::VLD3DUPdWB_fixed_Asm_16:
6739 case ARM::VLD3DUPdWB_fixed_Asm_32:
6740 case ARM::VLD3DUPqWB_fixed_Asm_8:
6741 case ARM::VLD3DUPqWB_fixed_Asm_16:
6742 case ARM::VLD3DUPqWB_fixed_Asm_32: {
6745 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6746 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6747 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6749 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6751 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6752 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6753 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6754 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6755 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6756 TmpInst.addOperand(Inst.getOperand(4));
6761 case ARM::VLD3DUPdWB_register_Asm_8:
6762 case ARM::VLD3DUPdWB_register_Asm_16:
6763 case ARM::VLD3DUPdWB_register_Asm_32:
6764 case ARM::VLD3DUPqWB_register_Asm_8:
6765 case ARM::VLD3DUPqWB_register_Asm_16:
6766 case ARM::VLD3DUPqWB_register_Asm_32: {
6769 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6770 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6771 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6773 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6775 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6776 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6777 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6778 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6779 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6780 TmpInst.addOperand(Inst.getOperand(5));
6785 // VLD3 multiple 3-element structure instructions.
6786 case ARM::VLD3dAsm_8:
6787 case ARM::VLD3dAsm_16:
6788 case ARM::VLD3dAsm_32:
6789 case ARM::VLD3qAsm_8:
6790 case ARM::VLD3qAsm_16:
6791 case ARM::VLD3qAsm_32: {
6794 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6795 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6796 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6798 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6800 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6801 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6802 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6803 TmpInst.addOperand(Inst.getOperand(4));
6808 case ARM::VLD3dWB_fixed_Asm_8:
6809 case ARM::VLD3dWB_fixed_Asm_16:
6810 case ARM::VLD3dWB_fixed_Asm_32:
6811 case ARM::VLD3qWB_fixed_Asm_8:
6812 case ARM::VLD3qWB_fixed_Asm_16:
6813 case ARM::VLD3qWB_fixed_Asm_32: {
6816 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6817 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6818 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6820 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6822 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6823 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6824 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6825 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6826 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6827 TmpInst.addOperand(Inst.getOperand(4));
6832 case ARM::VLD3dWB_register_Asm_8:
6833 case ARM::VLD3dWB_register_Asm_16:
6834 case ARM::VLD3dWB_register_Asm_32:
6835 case ARM::VLD3qWB_register_Asm_8:
6836 case ARM::VLD3qWB_register_Asm_16:
6837 case ARM::VLD3qWB_register_Asm_32: {
6840 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6841 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6842 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6844 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6846 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6847 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6848 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6849 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6850 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6851 TmpInst.addOperand(Inst.getOperand(5));
6856 // VLD4DUP single 3-element structure to all lanes instructions.
6857 case ARM::VLD4DUPdAsm_8:
6858 case ARM::VLD4DUPdAsm_16:
6859 case ARM::VLD4DUPdAsm_32:
6860 case ARM::VLD4DUPqAsm_8:
6861 case ARM::VLD4DUPqAsm_16:
6862 case ARM::VLD4DUPqAsm_32: {
6865 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6866 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6867 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6869 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6871 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6873 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6874 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6875 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6876 TmpInst.addOperand(Inst.getOperand(4));
6881 case ARM::VLD4DUPdWB_fixed_Asm_8:
6882 case ARM::VLD4DUPdWB_fixed_Asm_16:
6883 case ARM::VLD4DUPdWB_fixed_Asm_32:
6884 case ARM::VLD4DUPqWB_fixed_Asm_8:
6885 case ARM::VLD4DUPqWB_fixed_Asm_16:
6886 case ARM::VLD4DUPqWB_fixed_Asm_32: {
6889 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6890 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6891 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6893 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6895 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6897 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6898 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6899 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6900 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6901 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6902 TmpInst.addOperand(Inst.getOperand(4));
6907 case ARM::VLD4DUPdWB_register_Asm_8:
6908 case ARM::VLD4DUPdWB_register_Asm_16:
6909 case ARM::VLD4DUPdWB_register_Asm_32:
6910 case ARM::VLD4DUPqWB_register_Asm_8:
6911 case ARM::VLD4DUPqWB_register_Asm_16:
6912 case ARM::VLD4DUPqWB_register_Asm_32: {
6915 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6916 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6917 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6919 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6921 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6923 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6924 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6925 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6926 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6927 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6928 TmpInst.addOperand(Inst.getOperand(5));
6933 // VLD4 multiple 4-element structure instructions.
6934 case ARM::VLD4dAsm_8:
6935 case ARM::VLD4dAsm_16:
6936 case ARM::VLD4dAsm_32:
6937 case ARM::VLD4qAsm_8:
6938 case ARM::VLD4qAsm_16:
6939 case ARM::VLD4qAsm_32: {
6942 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6943 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6944 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6946 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6948 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6950 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6951 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6952 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6953 TmpInst.addOperand(Inst.getOperand(4));
6958 case ARM::VLD4dWB_fixed_Asm_8:
6959 case ARM::VLD4dWB_fixed_Asm_16:
6960 case ARM::VLD4dWB_fixed_Asm_32:
6961 case ARM::VLD4qWB_fixed_Asm_8:
6962 case ARM::VLD4qWB_fixed_Asm_16:
6963 case ARM::VLD4qWB_fixed_Asm_32: {
6966 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6967 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6968 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6970 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6972 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6974 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6975 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6976 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6977 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6978 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6979 TmpInst.addOperand(Inst.getOperand(4));
6984 case ARM::VLD4dWB_register_Asm_8:
6985 case ARM::VLD4dWB_register_Asm_16:
6986 case ARM::VLD4dWB_register_Asm_32:
6987 case ARM::VLD4qWB_register_Asm_8:
6988 case ARM::VLD4qWB_register_Asm_16:
6989 case ARM::VLD4qWB_register_Asm_32: {
6992 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6993 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6994 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6996 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6998 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7000 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7001 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7002 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7003 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7004 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7005 TmpInst.addOperand(Inst.getOperand(5));
7010 // VST3 multiple 3-element structure instructions.
7011 case ARM::VST3dAsm_8:
7012 case ARM::VST3dAsm_16:
7013 case ARM::VST3dAsm_32:
7014 case ARM::VST3qAsm_8:
7015 case ARM::VST3qAsm_16:
7016 case ARM::VST3qAsm_32: {
7019 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7020 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7021 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7022 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7023 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7025 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7027 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7028 TmpInst.addOperand(Inst.getOperand(4));
7033 case ARM::VST3dWB_fixed_Asm_8:
7034 case ARM::VST3dWB_fixed_Asm_16:
7035 case ARM::VST3dWB_fixed_Asm_32:
7036 case ARM::VST3qWB_fixed_Asm_8:
7037 case ARM::VST3qWB_fixed_Asm_16:
7038 case ARM::VST3qWB_fixed_Asm_32: {
7041 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7042 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7043 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7044 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7045 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7046 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7047 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7049 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7051 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7052 TmpInst.addOperand(Inst.getOperand(4));
7057 case ARM::VST3dWB_register_Asm_8:
7058 case ARM::VST3dWB_register_Asm_16:
7059 case ARM::VST3dWB_register_Asm_32:
7060 case ARM::VST3qWB_register_Asm_8:
7061 case ARM::VST3qWB_register_Asm_16:
7062 case ARM::VST3qWB_register_Asm_32: {
7065 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7066 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7067 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7068 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7069 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7070 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7071 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7073 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7075 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7076 TmpInst.addOperand(Inst.getOperand(5));
7081 // VST4 multiple 3-element structure instructions.
7082 case ARM::VST4dAsm_8:
7083 case ARM::VST4dAsm_16:
7084 case ARM::VST4dAsm_32:
7085 case ARM::VST4qAsm_8:
7086 case ARM::VST4qAsm_16:
7087 case ARM::VST4qAsm_32: {
7090 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7091 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7092 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7093 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7094 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7096 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7098 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7100 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7101 TmpInst.addOperand(Inst.getOperand(4));
7106 case ARM::VST4dWB_fixed_Asm_8:
7107 case ARM::VST4dWB_fixed_Asm_16:
7108 case ARM::VST4dWB_fixed_Asm_32:
7109 case ARM::VST4qWB_fixed_Asm_8:
7110 case ARM::VST4qWB_fixed_Asm_16:
7111 case ARM::VST4qWB_fixed_Asm_32: {
7114 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7115 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7116 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7117 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7118 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7119 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7120 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7122 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7124 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7126 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7127 TmpInst.addOperand(Inst.getOperand(4));
7132 case ARM::VST4dWB_register_Asm_8:
7133 case ARM::VST4dWB_register_Asm_16:
7134 case ARM::VST4dWB_register_Asm_32:
7135 case ARM::VST4qWB_register_Asm_8:
7136 case ARM::VST4qWB_register_Asm_16:
7137 case ARM::VST4qWB_register_Asm_32: {
7140 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7141 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7142 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7143 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7144 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7145 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7146 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7148 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7150 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7152 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7153 TmpInst.addOperand(Inst.getOperand(5));
7158 // Handle encoding choice for the shift-immediate instructions.
7161 case ARM::t2ASRri: {
7162 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7163 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7164 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
7165 !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
7166 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
7168 switch (Inst.getOpcode()) {
7169 default: llvm_unreachable("unexpected opcode");
7170 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
7171 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
7172 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
7174 // The Thumb1 operands aren't in the same order. Awesome, eh?
7176 TmpInst.setOpcode(NewOpc);
7177 TmpInst.addOperand(Inst.getOperand(0));
7178 TmpInst.addOperand(Inst.getOperand(5));
7179 TmpInst.addOperand(Inst.getOperand(1));
7180 TmpInst.addOperand(Inst.getOperand(2));
7181 TmpInst.addOperand(Inst.getOperand(3));
7182 TmpInst.addOperand(Inst.getOperand(4));
7189 // Handle the Thumb2 mode MOV complex aliases.
7191 case ARM::t2MOVSsr: {
7192 // Which instruction to expand to depends on the CCOut operand and
7193 // whether we're in an IT block if the register operands are low
7195 bool isNarrow = false;
7196 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7197 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7198 isARMLowRegister(Inst.getOperand(2).getReg()) &&
7199 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7200 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
7204 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
7205 default: llvm_unreachable("unexpected opcode!");
7206 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7207 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7208 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7209 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
7211 TmpInst.setOpcode(newOpc);
7212 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7214 TmpInst.addOperand(MCOperand::CreateReg(
7215 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7216 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7217 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7218 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7219 TmpInst.addOperand(Inst.getOperand(5));
7221 TmpInst.addOperand(MCOperand::CreateReg(
7222 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7227 case ARM::t2MOVSsi: {
7228 // Which instruction to expand to depends on the CCOut operand and
7229 // whether we're in an IT block if the register operands are low
7231 bool isNarrow = false;
7232 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7233 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7234 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
7238 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
7239 default: llvm_unreachable("unexpected opcode!");
7240 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7241 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7242 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7243 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7244 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7246 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
7247 if (Amount == 32) Amount = 0;
7248 TmpInst.setOpcode(newOpc);
7249 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7251 TmpInst.addOperand(MCOperand::CreateReg(
7252 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7253 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7254 if (newOpc != ARM::t2RRX)
7255 TmpInst.addOperand(MCOperand::CreateImm(Amount));
7256 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7257 TmpInst.addOperand(Inst.getOperand(4));
7259 TmpInst.addOperand(MCOperand::CreateReg(
7260 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7264 // Handle the ARM mode MOV complex aliases.
7269 ARM_AM::ShiftOpc ShiftTy;
7270 switch(Inst.getOpcode()) {
7271 default: llvm_unreachable("unexpected opcode!");
7272 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
7273 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
7274 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
7275 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
7277 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
7279 TmpInst.setOpcode(ARM::MOVsr);
7280 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7281 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7282 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7283 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7284 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7285 TmpInst.addOperand(Inst.getOperand(4));
7286 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7294 ARM_AM::ShiftOpc ShiftTy;
7295 switch(Inst.getOpcode()) {
7296 default: llvm_unreachable("unexpected opcode!");
7297 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
7298 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
7299 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7300 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
7302 // A shift by zero is a plain MOVr, not a MOVsi.
7303 unsigned Amt = Inst.getOperand(2).getImm();
7304 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
7305 // A shift by 32 should be encoded as 0 when permitted
7306 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
7308 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
7310 TmpInst.setOpcode(Opc);
7311 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7312 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7313 if (Opc == ARM::MOVsi)
7314 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7315 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7316 TmpInst.addOperand(Inst.getOperand(4));
7317 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7322 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
7324 TmpInst.setOpcode(ARM::MOVsi);
7325 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7326 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7327 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7328 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7329 TmpInst.addOperand(Inst.getOperand(3));
7330 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7334 case ARM::t2LDMIA_UPD: {
7335 // If this is a load of a single register, then we should use
7336 // a post-indexed LDR instruction instead, per the ARM ARM.
7337 if (Inst.getNumOperands() != 5)
7340 TmpInst.setOpcode(ARM::t2LDR_POST);
7341 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7342 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7343 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7344 TmpInst.addOperand(MCOperand::CreateImm(4));
7345 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7346 TmpInst.addOperand(Inst.getOperand(3));
7350 case ARM::t2STMDB_UPD: {
7351 // If this is a store of a single register, then we should use
7352 // a pre-indexed STR instruction instead, per the ARM ARM.
7353 if (Inst.getNumOperands() != 5)
7356 TmpInst.setOpcode(ARM::t2STR_PRE);
7357 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7358 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7359 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7360 TmpInst.addOperand(MCOperand::CreateImm(-4));
7361 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7362 TmpInst.addOperand(Inst.getOperand(3));
7366 case ARM::LDMIA_UPD:
7367 // If this is a load of a single register via a 'pop', then we should use
7368 // a post-indexed LDR instruction instead, per the ARM ARM.
7369 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
7370 Inst.getNumOperands() == 5) {
7372 TmpInst.setOpcode(ARM::LDR_POST_IMM);
7373 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7374 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7375 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7376 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
7377 TmpInst.addOperand(MCOperand::CreateImm(4));
7378 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7379 TmpInst.addOperand(Inst.getOperand(3));
7384 case ARM::STMDB_UPD:
7385 // If this is a store of a single register via a 'push', then we should use
7386 // a pre-indexed STR instruction instead, per the ARM ARM.
7387 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
7388 Inst.getNumOperands() == 5) {
7390 TmpInst.setOpcode(ARM::STR_PRE_IMM);
7391 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7392 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7393 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7394 TmpInst.addOperand(MCOperand::CreateImm(-4));
7395 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7396 TmpInst.addOperand(Inst.getOperand(3));
7400 case ARM::t2ADDri12:
7401 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7402 // mnemonic was used (not "addw"), encoding T3 is preferred.
7403 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
7404 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7406 Inst.setOpcode(ARM::t2ADDri);
7407 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7409 case ARM::t2SUBri12:
7410 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7411 // mnemonic was used (not "subw"), encoding T3 is preferred.
7412 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7413 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7415 Inst.setOpcode(ARM::t2SUBri);
7416 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7419 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7420 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7421 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7422 // to encoding T1 if <Rd> is omitted."
7423 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7424 Inst.setOpcode(ARM::tADDi3);
7429 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7430 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7431 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7432 // to encoding T1 if <Rd> is omitted."
7433 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7434 Inst.setOpcode(ARM::tSUBi3);
7439 case ARM::t2SUBri: {
7440 // If the destination and first source operand are the same, and
7441 // the flags are compatible with the current IT status, use encoding T2
7442 // instead of T3. For compatibility with the system 'as'. Make sure the
7443 // wide encoding wasn't explicit.
7444 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7445 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7446 (unsigned)Inst.getOperand(2).getImm() > 255 ||
7447 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7448 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7449 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7450 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7453 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7454 ARM::tADDi8 : ARM::tSUBi8);
7455 TmpInst.addOperand(Inst.getOperand(0));
7456 TmpInst.addOperand(Inst.getOperand(5));
7457 TmpInst.addOperand(Inst.getOperand(0));
7458 TmpInst.addOperand(Inst.getOperand(2));
7459 TmpInst.addOperand(Inst.getOperand(3));
7460 TmpInst.addOperand(Inst.getOperand(4));
7464 case ARM::t2ADDrr: {
7465 // If the destination and first source operand are the same, and
7466 // there's no setting of the flags, use encoding T2 instead of T3.
7467 // Note that this is only for ADD, not SUB. This mirrors the system
7468 // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7469 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7470 Inst.getOperand(5).getReg() != 0 ||
7471 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7472 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7475 TmpInst.setOpcode(ARM::tADDhirr);
7476 TmpInst.addOperand(Inst.getOperand(0));
7477 TmpInst.addOperand(Inst.getOperand(0));
7478 TmpInst.addOperand(Inst.getOperand(2));
7479 TmpInst.addOperand(Inst.getOperand(3));
7480 TmpInst.addOperand(Inst.getOperand(4));
7484 case ARM::tADDrSP: {
7485 // If the non-SP source operand and the destination operand are not the
7486 // same, we need to use the 32-bit encoding if it's available.
7487 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7488 Inst.setOpcode(ARM::t2ADDrr);
7489 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7495 // A Thumb conditional branch outside of an IT block is a tBcc.
7496 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7497 Inst.setOpcode(ARM::tBcc);
7502 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7503 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7504 Inst.setOpcode(ARM::t2Bcc);
7509 // If the conditional is AL or we're in an IT block, we really want t2B.
7510 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7511 Inst.setOpcode(ARM::t2B);
7516 // If the conditional is AL, we really want tB.
7517 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7518 Inst.setOpcode(ARM::tB);
7523 // If the register list contains any high registers, or if the writeback
7524 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7525 // instead if we're in Thumb2. Otherwise, this should have generated
7526 // an error in validateInstruction().
7527 unsigned Rn = Inst.getOperand(0).getReg();
7528 bool hasWritebackToken =
7529 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7530 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7531 bool listContainsBase;
7532 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7533 (!listContainsBase && !hasWritebackToken) ||
7534 (listContainsBase && hasWritebackToken)) {
7535 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7536 assert (isThumbTwo());
7537 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7538 // If we're switching to the updating version, we need to insert
7539 // the writeback tied operand.
7540 if (hasWritebackToken)
7541 Inst.insert(Inst.begin(),
7542 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7547 case ARM::tSTMIA_UPD: {
7548 // If the register list contains any high registers, we need to use
7549 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7550 // should have generated an error in validateInstruction().
7551 unsigned Rn = Inst.getOperand(0).getReg();
7552 bool listContainsBase;
7553 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7554 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7555 assert (isThumbTwo());
7556 Inst.setOpcode(ARM::t2STMIA_UPD);
7562 bool listContainsBase;
7563 // If the register list contains any high registers, we need to use
7564 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7565 // should have generated an error in validateInstruction().
7566 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7568 assert (isThumbTwo());
7569 Inst.setOpcode(ARM::t2LDMIA_UPD);
7570 // Add the base register and writeback operands.
7571 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7572 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7576 bool listContainsBase;
7577 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7579 assert (isThumbTwo());
7580 Inst.setOpcode(ARM::t2STMDB_UPD);
7581 // Add the base register and writeback operands.
7582 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7583 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7587 // If we can use the 16-bit encoding and the user didn't explicitly
7588 // request the 32-bit variant, transform it here.
7589 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7590 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7591 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7592 Inst.getOperand(4).getReg() == ARM::CPSR) ||
7593 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7594 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7595 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7596 // The operands aren't in the same order for tMOVi8...
7598 TmpInst.setOpcode(ARM::tMOVi8);
7599 TmpInst.addOperand(Inst.getOperand(0));
7600 TmpInst.addOperand(Inst.getOperand(4));
7601 TmpInst.addOperand(Inst.getOperand(1));
7602 TmpInst.addOperand(Inst.getOperand(2));
7603 TmpInst.addOperand(Inst.getOperand(3));
7610 // If we can use the 16-bit encoding and the user didn't explicitly
7611 // request the 32-bit variant, transform it here.
7612 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7613 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7614 Inst.getOperand(2).getImm() == ARMCC::AL &&
7615 Inst.getOperand(4).getReg() == ARM::CPSR &&
7616 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7617 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7618 // The operands aren't the same for tMOV[S]r... (no cc_out)
7620 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7621 TmpInst.addOperand(Inst.getOperand(0));
7622 TmpInst.addOperand(Inst.getOperand(1));
7623 TmpInst.addOperand(Inst.getOperand(2));
7624 TmpInst.addOperand(Inst.getOperand(3));
7634 // If we can use the 16-bit encoding and the user didn't explicitly
7635 // request the 32-bit variant, transform it here.
7636 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7637 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7638 Inst.getOperand(2).getImm() == 0 &&
7639 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7640 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7642 switch (Inst.getOpcode()) {
7643 default: llvm_unreachable("Illegal opcode!");
7644 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7645 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7646 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7647 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7649 // The operands aren't the same for thumb1 (no rotate operand).
7651 TmpInst.setOpcode(NewOpc);
7652 TmpInst.addOperand(Inst.getOperand(0));
7653 TmpInst.addOperand(Inst.getOperand(1));
7654 TmpInst.addOperand(Inst.getOperand(3));
7655 TmpInst.addOperand(Inst.getOperand(4));
7662 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7663 // rrx shifts and asr/lsr of #32 is encoded as 0
7664 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7666 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7667 // Shifting by zero is accepted as a vanilla 'MOVr'
7669 TmpInst.setOpcode(ARM::MOVr);
7670 TmpInst.addOperand(Inst.getOperand(0));
7671 TmpInst.addOperand(Inst.getOperand(1));
7672 TmpInst.addOperand(Inst.getOperand(3));
7673 TmpInst.addOperand(Inst.getOperand(4));
7674 TmpInst.addOperand(Inst.getOperand(5));
7687 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7688 if (SOpc == ARM_AM::rrx) return false;
7689 switch (Inst.getOpcode()) {
7690 default: llvm_unreachable("unexpected opcode!");
7691 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7692 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7693 case ARM::EORrsi: newOpc = ARM::EORrr; break;
7694 case ARM::BICrsi: newOpc = ARM::BICrr; break;
7695 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7696 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7698 // If the shift is by zero, use the non-shifted instruction definition.
7699 // The exception is for right shifts, where 0 == 32
7700 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7701 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7703 TmpInst.setOpcode(newOpc);
7704 TmpInst.addOperand(Inst.getOperand(0));
7705 TmpInst.addOperand(Inst.getOperand(1));
7706 TmpInst.addOperand(Inst.getOperand(2));
7707 TmpInst.addOperand(Inst.getOperand(4));
7708 TmpInst.addOperand(Inst.getOperand(5));
7709 TmpInst.addOperand(Inst.getOperand(6));
7717 // The mask bits for all but the first condition are represented as
7718 // the low bit of the condition code value implies 't'. We currently
7719 // always have 1 implies 't', so XOR toggle the bits if the low bit
7720 // of the condition code is zero.
7721 MCOperand &MO = Inst.getOperand(1);
7722 unsigned Mask = MO.getImm();
7723 unsigned OrigMask = Mask;
7724 unsigned TZ = countTrailingZeros(Mask);
7725 if ((Inst.getOperand(0).getImm() & 1) == 0) {
7726 assert(Mask && TZ <= 3 && "illegal IT mask value!");
7727 Mask ^= (0xE << TZ) & 0xF;
7731 // Set up the IT block state according to the IT instruction we just
7733 assert(!inITBlock() && "nested IT blocks?!");
7734 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7735 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7736 ITState.CurPosition = 0;
7737 ITState.FirstCond = true;
7747 // Assemblers should use the narrow encodings of these instructions when permissible.
7748 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7749 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7750 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7751 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7752 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7753 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7754 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7756 switch (Inst.getOpcode()) {
7757 default: llvm_unreachable("unexpected opcode");
7758 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7759 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7760 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7761 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7762 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7763 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7766 TmpInst.setOpcode(NewOpc);
7767 TmpInst.addOperand(Inst.getOperand(0));
7768 TmpInst.addOperand(Inst.getOperand(5));
7769 TmpInst.addOperand(Inst.getOperand(1));
7770 TmpInst.addOperand(Inst.getOperand(2));
7771 TmpInst.addOperand(Inst.getOperand(3));
7772 TmpInst.addOperand(Inst.getOperand(4));
7783 // Assemblers should use the narrow encodings of these instructions when permissible.
7784 // These instructions are special in that they are commutable, so shorter encodings
7785 // are available more often.
7786 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7787 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7788 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7789 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7790 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7791 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7792 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7793 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7795 switch (Inst.getOpcode()) {
7796 default: llvm_unreachable("unexpected opcode");
7797 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7798 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7799 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7800 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7803 TmpInst.setOpcode(NewOpc);
7804 TmpInst.addOperand(Inst.getOperand(0));
7805 TmpInst.addOperand(Inst.getOperand(5));
7806 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7807 TmpInst.addOperand(Inst.getOperand(1));
7808 TmpInst.addOperand(Inst.getOperand(2));
7810 TmpInst.addOperand(Inst.getOperand(2));
7811 TmpInst.addOperand(Inst.getOperand(1));
7813 TmpInst.addOperand(Inst.getOperand(3));
7814 TmpInst.addOperand(Inst.getOperand(4));
7824 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7825 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7826 // suffix depending on whether they're in an IT block or not.
7827 unsigned Opc = Inst.getOpcode();
7828 const MCInstrDesc &MCID = MII.get(Opc);
7829 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7830 assert(MCID.hasOptionalDef() &&
7831 "optionally flag setting instruction missing optional def operand");
7832 assert(MCID.NumOperands == Inst.getNumOperands() &&
7833 "operand count mismatch!");
7834 // Find the optional-def operand (cc_out).
7837 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7840 // If we're parsing Thumb1, reject it completely.
7841 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7842 return Match_MnemonicFail;
7843 // If we're parsing Thumb2, which form is legal depends on whether we're
7845 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7847 return Match_RequiresITBlock;
7848 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7850 return Match_RequiresNotITBlock;
7852 // Some high-register supporting Thumb1 encodings only allow both registers
7853 // to be from r0-r7 when in Thumb2.
7854 else if (Opc == ARM::tADDhirr && isThumbOne() &&
7855 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7856 isARMLowRegister(Inst.getOperand(2).getReg()))
7857 return Match_RequiresThumb2;
7858 // Others only require ARMv6 or later.
7859 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7860 isARMLowRegister(Inst.getOperand(0).getReg()) &&
7861 isARMLowRegister(Inst.getOperand(1).getReg()))
7862 return Match_RequiresV6;
7863 return Match_Success;
7866 template<> inline bool IsCPSRDead<MCInst>(MCInst* Instr) {
7867 return true; // In an assembly source, no need to second-guess
7870 static const char *getSubtargetFeatureName(unsigned Val);
7872 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
7873 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
7874 MCStreamer &Out, unsigned &ErrorInfo,
7875 bool MatchingInlineAsm) {
7877 unsigned MatchResult;
7879 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
7881 switch (MatchResult) {
7884 // Context sensitive operand constraints aren't handled by the matcher,
7885 // so check them here.
7886 if (validateInstruction(Inst, Operands)) {
7887 // Still progress the IT block, otherwise one wrong condition causes
7888 // nasty cascading errors.
7889 forwardITPosition();
7893 { // processInstruction() updates inITBlock state, we need to save it away
7894 bool wasInITBlock = inITBlock();
7896 // Some instructions need post-processing to, for example, tweak which
7897 // encoding is selected. Loop on it while changes happen so the
7898 // individual transformations can chain off each other. E.g.,
7899 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
7900 while (processInstruction(Inst, Operands))
7903 // Only after the instruction is fully processed, we can validate it
7904 if (wasInITBlock && hasV8Ops() && isThumb() &&
7905 !isV8EligibleForIT(&Inst)) {
7906 Warning(IDLoc, "deprecated instruction in IT block");
7910 // Only move forward at the very end so that everything in validate
7911 // and process gets a consistent answer about whether we're in an IT
7913 forwardITPosition();
7915 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7916 // doesn't actually encode.
7917 if (Inst.getOpcode() == ARM::ITasm)
7921 Out.EmitInstruction(Inst, STI);
7923 case Match_MissingFeature: {
7924 assert(ErrorInfo && "Unknown missing feature!");
7925 // Special case the error message for the very common case where only
7926 // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
7927 std::string Msg = "instruction requires:";
7929 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
7930 if (ErrorInfo & Mask) {
7932 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
7936 return Error(IDLoc, Msg);
7938 case Match_InvalidOperand: {
7939 SMLoc ErrorLoc = IDLoc;
7940 if (ErrorInfo != ~0U) {
7941 if (ErrorInfo >= Operands.size())
7942 return Error(IDLoc, "too few operands for instruction");
7944 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7945 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7948 return Error(ErrorLoc, "invalid operand for instruction");
7950 case Match_MnemonicFail:
7951 return Error(IDLoc, "invalid instruction",
7952 ((ARMOperand*)Operands[0])->getLocRange());
7953 case Match_RequiresNotITBlock:
7954 return Error(IDLoc, "flag setting instruction only valid outside IT block");
7955 case Match_RequiresITBlock:
7956 return Error(IDLoc, "instruction only valid inside IT block");
7957 case Match_RequiresV6:
7958 return Error(IDLoc, "instruction variant requires ARMv6 or later");
7959 case Match_RequiresThumb2:
7960 return Error(IDLoc, "instruction variant requires Thumb2");
7961 case Match_ImmRange0_15: {
7962 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7963 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7964 return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
7966 case Match_ImmRange0_239: {
7967 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7968 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7969 return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
7973 llvm_unreachable("Implement any new match types added!");
7976 /// parseDirective parses the arm specific directives
7977 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
7978 StringRef IDVal = DirectiveID.getIdentifier();
7979 if (IDVal == ".word")
7980 return parseLiteralValues(4, DirectiveID.getLoc());
7981 else if (IDVal == ".short" || IDVal == ".hword")
7982 return parseLiteralValues(2, DirectiveID.getLoc());
7983 else if (IDVal == ".thumb")
7984 return parseDirectiveThumb(DirectiveID.getLoc());
7985 else if (IDVal == ".arm")
7986 return parseDirectiveARM(DirectiveID.getLoc());
7987 else if (IDVal == ".thumb_func")
7988 return parseDirectiveThumbFunc(DirectiveID.getLoc());
7989 else if (IDVal == ".code")
7990 return parseDirectiveCode(DirectiveID.getLoc());
7991 else if (IDVal == ".syntax")
7992 return parseDirectiveSyntax(DirectiveID.getLoc());
7993 else if (IDVal == ".unreq")
7994 return parseDirectiveUnreq(DirectiveID.getLoc());
7995 else if (IDVal == ".arch")
7996 return parseDirectiveArch(DirectiveID.getLoc());
7997 else if (IDVal == ".eabi_attribute")
7998 return parseDirectiveEabiAttr(DirectiveID.getLoc());
7999 else if (IDVal == ".cpu")
8000 return parseDirectiveCPU(DirectiveID.getLoc());
8001 else if (IDVal == ".fpu")
8002 return parseDirectiveFPU(DirectiveID.getLoc());
8003 else if (IDVal == ".fnstart")
8004 return parseDirectiveFnStart(DirectiveID.getLoc());
8005 else if (IDVal == ".fnend")
8006 return parseDirectiveFnEnd(DirectiveID.getLoc());
8007 else if (IDVal == ".cantunwind")
8008 return parseDirectiveCantUnwind(DirectiveID.getLoc());
8009 else if (IDVal == ".personality")
8010 return parseDirectivePersonality(DirectiveID.getLoc());
8011 else if (IDVal == ".handlerdata")
8012 return parseDirectiveHandlerData(DirectiveID.getLoc());
8013 else if (IDVal == ".setfp")
8014 return parseDirectiveSetFP(DirectiveID.getLoc());
8015 else if (IDVal == ".pad")
8016 return parseDirectivePad(DirectiveID.getLoc());
8017 else if (IDVal == ".save")
8018 return parseDirectiveRegSave(DirectiveID.getLoc(), false);
8019 else if (IDVal == ".vsave")
8020 return parseDirectiveRegSave(DirectiveID.getLoc(), true);
8021 else if (IDVal == ".inst")
8022 return parseDirectiveInst(DirectiveID.getLoc());
8023 else if (IDVal == ".inst.n")
8024 return parseDirectiveInst(DirectiveID.getLoc(), 'n');
8025 else if (IDVal == ".inst.w")
8026 return parseDirectiveInst(DirectiveID.getLoc(), 'w');
8027 else if (IDVal == ".ltorg" || IDVal == ".pool")
8028 return parseDirectiveLtorg(DirectiveID.getLoc());
8029 else if (IDVal == ".even")
8030 return parseDirectiveEven(DirectiveID.getLoc());
8031 else if (IDVal == ".personalityindex")
8032 return parseDirectivePersonalityIndex(DirectiveID.getLoc());
8033 else if (IDVal == ".unwind_raw")
8034 return parseDirectiveUnwindRaw(DirectiveID.getLoc());
8035 else if (IDVal == ".tlsdescseq")
8036 return parseDirectiveTLSDescSeq(DirectiveID.getLoc());
8037 else if (IDVal == ".movsp")
8038 return parseDirectiveMovSP(DirectiveID.getLoc());
8039 else if (IDVal == ".object_arch")
8040 return parseDirectiveObjectArch(DirectiveID.getLoc());
8041 else if (IDVal == ".arch_extension")
8042 return parseDirectiveArchExtension(DirectiveID.getLoc());
8043 else if (IDVal == ".align")
8044 return parseDirectiveAlign(DirectiveID.getLoc());
8045 else if (IDVal == ".thumb_set")
8046 return parseDirectiveThumbSet(DirectiveID.getLoc());
8050 /// parseLiteralValues
8051 /// ::= .hword expression [, expression]*
8052 /// ::= .short expression [, expression]*
8053 /// ::= .word expression [, expression]*
8054 bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
8055 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8057 const MCExpr *Value;
8058 if (getParser().parseExpression(Value)) {
8059 Parser.eatToEndOfStatement();
8063 getParser().getStreamer().EmitValue(Value, Size);
8065 if (getLexer().is(AsmToken::EndOfStatement))
8068 // FIXME: Improve diagnostic.
8069 if (getLexer().isNot(AsmToken::Comma)) {
8070 Error(L, "unexpected token in directive");
8081 /// parseDirectiveThumb
8083 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
8084 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8085 Error(L, "unexpected token in directive");
8091 Error(L, "target does not support Thumb mode");
8098 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8102 /// parseDirectiveARM
8104 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
8105 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8106 Error(L, "unexpected token in directive");
8112 Error(L, "target does not support ARM mode");
8119 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8123 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
8124 if (NextSymbolIsThumb) {
8125 getParser().getStreamer().EmitThumbFunc(Symbol);
8126 NextSymbolIsThumb = false;
8133 const MCObjectFileInfo::Environment Format =
8134 getContext().getObjectFileInfo()->getObjectFileType();
8136 case MCObjectFileInfo::IsCOFF: {
8137 const MCSymbolData &SD =
8138 getParser().getStreamer().getOrCreateSymbolData(Symbol);
8139 char Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
8140 if (SD.getFlags() & (Type << COFF::SF_TypeShift))
8141 getParser().getStreamer().EmitThumbFunc(Symbol);
8144 case MCObjectFileInfo::IsELF: {
8145 const MCSymbolData &SD =
8146 getParser().getStreamer().getOrCreateSymbolData(Symbol);
8147 if (MCELF::GetType(SD) & (ELF::STT_FUNC << ELF_STT_Shift))
8148 getParser().getStreamer().EmitThumbFunc(Symbol);
8151 case MCObjectFileInfo::IsMachO:
8156 /// parseDirectiveThumbFunc
8157 /// ::= .thumbfunc symbol_name
8158 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
8159 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
8160 bool isMachO = MAI->hasSubsectionsViaSymbols();
8162 // Darwin asm has (optionally) function name after .thumb_func direction
8165 const AsmToken &Tok = Parser.getTok();
8166 if (Tok.isNot(AsmToken::EndOfStatement)) {
8167 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) {
8168 Error(L, "unexpected token in .thumb_func directive");
8173 getParser().getContext().GetOrCreateSymbol(Tok.getIdentifier());
8174 getParser().getStreamer().EmitThumbFunc(Func);
8175 Parser.Lex(); // Consume the identifier token.
8180 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8181 Error(L, "unexpected token in directive");
8185 NextSymbolIsThumb = true;
8189 /// parseDirectiveSyntax
8190 /// ::= .syntax unified | divided
8191 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
8192 const AsmToken &Tok = Parser.getTok();
8193 if (Tok.isNot(AsmToken::Identifier)) {
8194 Error(L, "unexpected token in .syntax directive");
8198 StringRef Mode = Tok.getString();
8199 if (Mode == "unified" || Mode == "UNIFIED") {
8201 } else if (Mode == "divided" || Mode == "DIVIDED") {
8202 Error(L, "'.syntax divided' arm asssembly not supported");
8205 Error(L, "unrecognized syntax mode in .syntax directive");
8209 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8210 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8215 // TODO tell the MC streamer the mode
8216 // getParser().getStreamer().Emit???();
8220 /// parseDirectiveCode
8221 /// ::= .code 16 | 32
8222 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
8223 const AsmToken &Tok = Parser.getTok();
8224 if (Tok.isNot(AsmToken::Integer)) {
8225 Error(L, "unexpected token in .code directive");
8228 int64_t Val = Parser.getTok().getIntVal();
8229 if (Val != 16 && Val != 32) {
8230 Error(L, "invalid operand to .code directive");
8235 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8236 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8243 Error(L, "target does not support Thumb mode");
8249 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8252 Error(L, "target does not support ARM mode");
8258 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8264 /// parseDirectiveReq
8265 /// ::= name .req registername
8266 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
8267 Parser.Lex(); // Eat the '.req' token.
8269 SMLoc SRegLoc, ERegLoc;
8270 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
8271 Parser.eatToEndOfStatement();
8272 Error(SRegLoc, "register name expected");
8276 // Shouldn't be anything else.
8277 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
8278 Parser.eatToEndOfStatement();
8279 Error(Parser.getTok().getLoc(), "unexpected input in .req directive.");
8283 Parser.Lex(); // Consume the EndOfStatement
8285 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg) {
8286 Error(SRegLoc, "redefinition of '" + Name + "' does not match original.");
8293 /// parseDirectiveUneq
8294 /// ::= .unreq registername
8295 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
8296 if (Parser.getTok().isNot(AsmToken::Identifier)) {
8297 Parser.eatToEndOfStatement();
8298 Error(L, "unexpected input in .unreq directive.");
8301 RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
8302 Parser.Lex(); // Eat the identifier.
8306 /// parseDirectiveArch
8308 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
8309 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
8310 bool isMachO = MAI->hasSubsectionsViaSymbols();
8312 Error(L, ".arch directive not valid for Mach-O");
8313 Parser.eatToEndOfStatement();
8317 StringRef Arch = getParser().parseStringToEndOfStatement().trim();
8319 unsigned ID = StringSwitch<unsigned>(Arch)
8320 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
8321 .Case(NAME, ARM::ID)
8322 #define ARM_ARCH_ALIAS(NAME, ID) \
8323 .Case(NAME, ARM::ID)
8324 #include "MCTargetDesc/ARMArchName.def"
8325 .Default(ARM::INVALID_ARCH);
8327 if (ID == ARM::INVALID_ARCH) {
8328 Error(L, "Unknown arch name");
8332 getTargetStreamer().emitArch(ID);
8336 /// parseDirectiveEabiAttr
8337 /// ::= .eabi_attribute int, int [, "str"]
8338 /// ::= .eabi_attribute Tag_name, int [, "str"]
8339 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
8340 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
8341 bool isMachO = MAI->hasSubsectionsViaSymbols();
8343 Error(L, ".eabi_attribute directive not valid for Mach-O");
8344 Parser.eatToEndOfStatement();
8350 TagLoc = Parser.getTok().getLoc();
8351 if (Parser.getTok().is(AsmToken::Identifier)) {
8352 StringRef Name = Parser.getTok().getIdentifier();
8353 Tag = ARMBuildAttrs::AttrTypeFromString(Name);
8355 Error(TagLoc, "attribute name not recognised: " + Name);
8356 Parser.eatToEndOfStatement();
8361 const MCExpr *AttrExpr;
8363 TagLoc = Parser.getTok().getLoc();
8364 if (Parser.parseExpression(AttrExpr)) {
8365 Parser.eatToEndOfStatement();
8369 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
8371 Error(TagLoc, "expected numeric constant");
8372 Parser.eatToEndOfStatement();
8376 Tag = CE->getValue();
8379 if (Parser.getTok().isNot(AsmToken::Comma)) {
8380 Error(Parser.getTok().getLoc(), "comma expected");
8381 Parser.eatToEndOfStatement();
8384 Parser.Lex(); // skip comma
8386 StringRef StringValue = "";
8387 bool IsStringValue = false;
8389 int64_t IntegerValue = 0;
8390 bool IsIntegerValue = false;
8392 if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
8393 IsStringValue = true;
8394 else if (Tag == ARMBuildAttrs::compatibility) {
8395 IsStringValue = true;
8396 IsIntegerValue = true;
8397 } else if (Tag < 32 || Tag % 2 == 0)
8398 IsIntegerValue = true;
8399 else if (Tag % 2 == 1)
8400 IsStringValue = true;
8402 llvm_unreachable("invalid tag type");
8404 if (IsIntegerValue) {
8405 const MCExpr *ValueExpr;
8406 SMLoc ValueExprLoc = Parser.getTok().getLoc();
8407 if (Parser.parseExpression(ValueExpr)) {
8408 Parser.eatToEndOfStatement();
8412 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
8414 Error(ValueExprLoc, "expected numeric constant");
8415 Parser.eatToEndOfStatement();
8419 IntegerValue = CE->getValue();
8422 if (Tag == ARMBuildAttrs::compatibility) {
8423 if (Parser.getTok().isNot(AsmToken::Comma))
8424 IsStringValue = false;
8429 if (IsStringValue) {
8430 if (Parser.getTok().isNot(AsmToken::String)) {
8431 Error(Parser.getTok().getLoc(), "bad string constant");
8432 Parser.eatToEndOfStatement();
8436 StringValue = Parser.getTok().getStringContents();
8440 if (IsIntegerValue && IsStringValue) {
8441 assert(Tag == ARMBuildAttrs::compatibility);
8442 getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
8443 } else if (IsIntegerValue)
8444 getTargetStreamer().emitAttribute(Tag, IntegerValue);
8445 else if (IsStringValue)
8446 getTargetStreamer().emitTextAttribute(Tag, StringValue);
8450 /// parseDirectiveCPU
8452 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
8453 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
8454 bool isMachO = MAI->hasSubsectionsViaSymbols();
8456 Error(L, ".cpu directive not valid for Mach-O");
8457 Parser.eatToEndOfStatement();
8461 StringRef CPU = getParser().parseStringToEndOfStatement().trim();
8462 getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
8466 /// parseDirectiveFPU
8468 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
8469 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
8470 bool isMachO = MAI->hasSubsectionsViaSymbols();
8472 Error(L, ".fpu directive not valid for Mach-O");
8473 Parser.eatToEndOfStatement();
8477 StringRef FPU = getParser().parseStringToEndOfStatement().trim();
8479 unsigned ID = StringSwitch<unsigned>(FPU)
8480 #define ARM_FPU_NAME(NAME, ID) .Case(NAME, ARM::ID)
8481 #include "ARMFPUName.def"
8482 .Default(ARM::INVALID_FPU);
8484 if (ID == ARM::INVALID_FPU) {
8485 Error(L, "Unknown FPU name");
8489 getTargetStreamer().emitFPU(ID);
8493 /// parseDirectiveFnStart
8495 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
8496 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
8497 bool isMachO = MAI->hasSubsectionsViaSymbols();
8499 Error(L, ".fnstart directive not valid for Mach-O");
8500 Parser.eatToEndOfStatement();
8504 if (UC.hasFnStart()) {
8505 Error(L, ".fnstart starts before the end of previous one");
8506 UC.emitFnStartLocNotes();
8510 // Reset the unwind directives parser state
8513 getTargetStreamer().emitFnStart();
8515 UC.recordFnStart(L);
8519 /// parseDirectiveFnEnd
8521 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
8522 // Check the ordering of unwind directives
8523 if (!UC.hasFnStart()) {
8524 Error(L, ".fnstart must precede .fnend directive");
8528 // Reset the unwind directives parser state
8529 getTargetStreamer().emitFnEnd();
8535 /// parseDirectiveCantUnwind
8537 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
8538 UC.recordCantUnwind(L);
8540 // Check the ordering of unwind directives
8541 if (!UC.hasFnStart()) {
8542 Error(L, ".fnstart must precede .cantunwind directive");
8545 if (UC.hasHandlerData()) {
8546 Error(L, ".cantunwind can't be used with .handlerdata directive");
8547 UC.emitHandlerDataLocNotes();
8550 if (UC.hasPersonality()) {
8551 Error(L, ".cantunwind can't be used with .personality directive");
8552 UC.emitPersonalityLocNotes();
8556 getTargetStreamer().emitCantUnwind();
8560 /// parseDirectivePersonality
8561 /// ::= .personality name
8562 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
8563 bool HasExistingPersonality = UC.hasPersonality();
8565 UC.recordPersonality(L);
8567 // Check the ordering of unwind directives
8568 if (!UC.hasFnStart()) {
8569 Error(L, ".fnstart must precede .personality directive");
8572 if (UC.cantUnwind()) {
8573 Error(L, ".personality can't be used with .cantunwind directive");
8574 UC.emitCantUnwindLocNotes();
8577 if (UC.hasHandlerData()) {
8578 Error(L, ".personality must precede .handlerdata directive");
8579 UC.emitHandlerDataLocNotes();
8582 if (HasExistingPersonality) {
8583 Parser.eatToEndOfStatement();
8584 Error(L, "multiple personality directives");
8585 UC.emitPersonalityLocNotes();
8589 // Parse the name of the personality routine
8590 if (Parser.getTok().isNot(AsmToken::Identifier)) {
8591 Parser.eatToEndOfStatement();
8592 Error(L, "unexpected input in .personality directive.");
8595 StringRef Name(Parser.getTok().getIdentifier());
8598 MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
8599 getTargetStreamer().emitPersonality(PR);
8603 /// parseDirectiveHandlerData
8604 /// ::= .handlerdata
8605 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
8606 UC.recordHandlerData(L);
8608 // Check the ordering of unwind directives
8609 if (!UC.hasFnStart()) {
8610 Error(L, ".fnstart must precede .personality directive");
8613 if (UC.cantUnwind()) {
8614 Error(L, ".handlerdata can't be used with .cantunwind directive");
8615 UC.emitCantUnwindLocNotes();
8619 getTargetStreamer().emitHandlerData();
8623 /// parseDirectiveSetFP
8624 /// ::= .setfp fpreg, spreg [, offset]
8625 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
8626 // Check the ordering of unwind directives
8627 if (!UC.hasFnStart()) {
8628 Error(L, ".fnstart must precede .setfp directive");
8631 if (UC.hasHandlerData()) {
8632 Error(L, ".setfp must precede .handlerdata directive");
8637 SMLoc FPRegLoc = Parser.getTok().getLoc();
8638 int FPReg = tryParseRegister();
8640 Error(FPRegLoc, "frame pointer register expected");
8645 if (Parser.getTok().isNot(AsmToken::Comma)) {
8646 Error(Parser.getTok().getLoc(), "comma expected");
8649 Parser.Lex(); // skip comma
8652 SMLoc SPRegLoc = Parser.getTok().getLoc();
8653 int SPReg = tryParseRegister();
8655 Error(SPRegLoc, "stack pointer register expected");
8659 if (SPReg != ARM::SP && SPReg != UC.getFPReg()) {
8660 Error(SPRegLoc, "register should be either $sp or the latest fp register");
8664 // Update the frame pointer register
8665 UC.saveFPReg(FPReg);
8669 if (Parser.getTok().is(AsmToken::Comma)) {
8670 Parser.Lex(); // skip comma
8672 if (Parser.getTok().isNot(AsmToken::Hash) &&
8673 Parser.getTok().isNot(AsmToken::Dollar)) {
8674 Error(Parser.getTok().getLoc(), "'#' expected");
8677 Parser.Lex(); // skip hash token.
8679 const MCExpr *OffsetExpr;
8680 SMLoc ExLoc = Parser.getTok().getLoc();
8682 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
8683 Error(ExLoc, "malformed setfp offset");
8686 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8688 Error(ExLoc, "setfp offset must be an immediate");
8692 Offset = CE->getValue();
8695 getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
8696 static_cast<unsigned>(SPReg), Offset);
8702 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
8703 // Check the ordering of unwind directives
8704 if (!UC.hasFnStart()) {
8705 Error(L, ".fnstart must precede .pad directive");
8708 if (UC.hasHandlerData()) {
8709 Error(L, ".pad must precede .handlerdata directive");
8714 if (Parser.getTok().isNot(AsmToken::Hash) &&
8715 Parser.getTok().isNot(AsmToken::Dollar)) {
8716 Error(Parser.getTok().getLoc(), "'#' expected");
8719 Parser.Lex(); // skip hash token.
8721 const MCExpr *OffsetExpr;
8722 SMLoc ExLoc = Parser.getTok().getLoc();
8724 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
8725 Error(ExLoc, "malformed pad offset");
8728 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8730 Error(ExLoc, "pad offset must be an immediate");
8734 getTargetStreamer().emitPad(CE->getValue());
8738 /// parseDirectiveRegSave
8739 /// ::= .save { registers }
8740 /// ::= .vsave { registers }
8741 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
8742 // Check the ordering of unwind directives
8743 if (!UC.hasFnStart()) {
8744 Error(L, ".fnstart must precede .save or .vsave directives");
8747 if (UC.hasHandlerData()) {
8748 Error(L, ".save or .vsave must precede .handlerdata directive");
8752 // RAII object to make sure parsed operands are deleted.
8753 struct CleanupObject {
8754 SmallVector<MCParsedAsmOperand *, 1> Operands;
8756 for (unsigned I = 0, E = Operands.size(); I != E; ++I)
8761 // Parse the register list
8762 if (parseRegisterList(CO.Operands))
8764 ARMOperand *Op = (ARMOperand*)CO.Operands[0];
8765 if (!IsVector && !Op->isRegList()) {
8766 Error(L, ".save expects GPR registers");
8769 if (IsVector && !Op->isDPRRegList()) {
8770 Error(L, ".vsave expects DPR registers");
8774 getTargetStreamer().emitRegSave(Op->getRegList(), IsVector);
8778 /// parseDirectiveInst
8779 /// ::= .inst opcode [, ...]
8780 /// ::= .inst.n opcode [, ...]
8781 /// ::= .inst.w opcode [, ...]
8782 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
8783 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
8784 bool isMachO = MAI->hasSubsectionsViaSymbols();
8786 Error(Loc, ".inst directive not valid for Mach-O");
8787 Parser.eatToEndOfStatement();
8802 Parser.eatToEndOfStatement();
8803 Error(Loc, "cannot determine Thumb instruction size, "
8804 "use inst.n/inst.w instead");
8809 Parser.eatToEndOfStatement();
8810 Error(Loc, "width suffixes are invalid in ARM mode");
8816 if (getLexer().is(AsmToken::EndOfStatement)) {
8817 Parser.eatToEndOfStatement();
8818 Error(Loc, "expected expression following directive");
8825 if (getParser().parseExpression(Expr)) {
8826 Error(Loc, "expected expression");
8830 const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
8832 Error(Loc, "expected constant expression");
8838 if (Value->getValue() > 0xffff) {
8839 Error(Loc, "inst.n operand is too big, use inst.w instead");
8844 if (Value->getValue() > 0xffffffff) {
8846 StringRef(Suffix ? "inst.w" : "inst") + " operand is too big");
8851 llvm_unreachable("only supported widths are 2 and 4");
8854 getTargetStreamer().emitInst(Value->getValue(), Suffix);
8856 if (getLexer().is(AsmToken::EndOfStatement))
8859 if (getLexer().isNot(AsmToken::Comma)) {
8860 Error(Loc, "unexpected token in directive");
8871 /// parseDirectiveLtorg
8872 /// ::= .ltorg | .pool
8873 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
8874 getTargetStreamer().emitCurrentConstantPool();
8878 bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
8879 const MCSection *Section = getStreamer().getCurrentSection().first;
8881 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8882 TokError("unexpected token in directive");
8887 getStreamer().InitSections();
8888 Section = getStreamer().getCurrentSection().first;
8891 assert(Section && "must have section to emit alignment");
8892 if (Section->UseCodeAlign())
8893 getStreamer().EmitCodeAlignment(2);
8895 getStreamer().EmitValueToAlignment(2);
8900 /// parseDirectivePersonalityIndex
8901 /// ::= .personalityindex index
8902 bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) {
8903 bool HasExistingPersonality = UC.hasPersonality();
8905 UC.recordPersonalityIndex(L);
8907 if (!UC.hasFnStart()) {
8908 Parser.eatToEndOfStatement();
8909 Error(L, ".fnstart must precede .personalityindex directive");
8912 if (UC.cantUnwind()) {
8913 Parser.eatToEndOfStatement();
8914 Error(L, ".personalityindex cannot be used with .cantunwind");
8915 UC.emitCantUnwindLocNotes();
8918 if (UC.hasHandlerData()) {
8919 Parser.eatToEndOfStatement();
8920 Error(L, ".personalityindex must precede .handlerdata directive");
8921 UC.emitHandlerDataLocNotes();
8924 if (HasExistingPersonality) {
8925 Parser.eatToEndOfStatement();
8926 Error(L, "multiple personality directives");
8927 UC.emitPersonalityLocNotes();
8931 const MCExpr *IndexExpression;
8932 SMLoc IndexLoc = Parser.getTok().getLoc();
8933 if (Parser.parseExpression(IndexExpression)) {
8934 Parser.eatToEndOfStatement();
8938 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
8940 Parser.eatToEndOfStatement();
8941 Error(IndexLoc, "index must be a constant number");
8944 if (CE->getValue() < 0 ||
8945 CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) {
8946 Parser.eatToEndOfStatement();
8947 Error(IndexLoc, "personality routine index should be in range [0-3]");
8951 getTargetStreamer().emitPersonalityIndex(CE->getValue());
8955 /// parseDirectiveUnwindRaw
8956 /// ::= .unwind_raw offset, opcode [, opcode...]
8957 bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
8958 if (!UC.hasFnStart()) {
8959 Parser.eatToEndOfStatement();
8960 Error(L, ".fnstart must precede .unwind_raw directives");
8964 int64_t StackOffset;
8966 const MCExpr *OffsetExpr;
8967 SMLoc OffsetLoc = getLexer().getLoc();
8968 if (getLexer().is(AsmToken::EndOfStatement) ||
8969 getParser().parseExpression(OffsetExpr)) {
8970 Error(OffsetLoc, "expected expression");
8971 Parser.eatToEndOfStatement();
8975 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8977 Error(OffsetLoc, "offset must be a constant");
8978 Parser.eatToEndOfStatement();
8982 StackOffset = CE->getValue();
8984 if (getLexer().isNot(AsmToken::Comma)) {
8985 Error(getLexer().getLoc(), "expected comma");
8986 Parser.eatToEndOfStatement();
8991 SmallVector<uint8_t, 16> Opcodes;
8995 SMLoc OpcodeLoc = getLexer().getLoc();
8996 if (getLexer().is(AsmToken::EndOfStatement) || Parser.parseExpression(OE)) {
8997 Error(OpcodeLoc, "expected opcode expression");
8998 Parser.eatToEndOfStatement();
9002 const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
9004 Error(OpcodeLoc, "opcode value must be a constant");
9005 Parser.eatToEndOfStatement();
9009 const int64_t Opcode = OC->getValue();
9010 if (Opcode & ~0xff) {
9011 Error(OpcodeLoc, "invalid opcode");
9012 Parser.eatToEndOfStatement();
9016 Opcodes.push_back(uint8_t(Opcode));
9018 if (getLexer().is(AsmToken::EndOfStatement))
9021 if (getLexer().isNot(AsmToken::Comma)) {
9022 Error(getLexer().getLoc(), "unexpected token in directive");
9023 Parser.eatToEndOfStatement();
9030 getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes);
9036 /// parseDirectiveTLSDescSeq
9037 /// ::= .tlsdescseq tls-variable
9038 bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) {
9039 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
9040 bool isMachO = MAI->hasSubsectionsViaSymbols();
9042 Error(L, ".tlsdescseq directive not valid for Mach-O");
9043 Parser.eatToEndOfStatement();
9047 if (getLexer().isNot(AsmToken::Identifier)) {
9048 TokError("expected variable after '.tlsdescseq' directive");
9049 Parser.eatToEndOfStatement();
9053 const MCSymbolRefExpr *SRE =
9054 MCSymbolRefExpr::Create(Parser.getTok().getIdentifier(),
9055 MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext());
9058 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9059 Error(Parser.getTok().getLoc(), "unexpected token");
9060 Parser.eatToEndOfStatement();
9064 getTargetStreamer().AnnotateTLSDescriptorSequence(SRE);
9068 /// parseDirectiveMovSP
9069 /// ::= .movsp reg [, #offset]
9070 bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) {
9071 if (!UC.hasFnStart()) {
9072 Parser.eatToEndOfStatement();
9073 Error(L, ".fnstart must precede .movsp directives");
9076 if (UC.getFPReg() != ARM::SP) {
9077 Parser.eatToEndOfStatement();
9078 Error(L, "unexpected .movsp directive");
9082 SMLoc SPRegLoc = Parser.getTok().getLoc();
9083 int SPReg = tryParseRegister();
9085 Parser.eatToEndOfStatement();
9086 Error(SPRegLoc, "register expected");
9090 if (SPReg == ARM::SP || SPReg == ARM::PC) {
9091 Parser.eatToEndOfStatement();
9092 Error(SPRegLoc, "sp and pc are not permitted in .movsp directive");
9097 if (Parser.getTok().is(AsmToken::Comma)) {
9100 if (Parser.getTok().isNot(AsmToken::Hash)) {
9101 Error(Parser.getTok().getLoc(), "expected #constant");
9102 Parser.eatToEndOfStatement();
9107 const MCExpr *OffsetExpr;
9108 SMLoc OffsetLoc = Parser.getTok().getLoc();
9109 if (Parser.parseExpression(OffsetExpr)) {
9110 Parser.eatToEndOfStatement();
9111 Error(OffsetLoc, "malformed offset expression");
9115 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9117 Parser.eatToEndOfStatement();
9118 Error(OffsetLoc, "offset must be an immediate constant");
9122 Offset = CE->getValue();
9125 getTargetStreamer().emitMovSP(SPReg, Offset);
9126 UC.saveFPReg(SPReg);
9131 /// parseDirectiveObjectArch
9132 /// ::= .object_arch name
9133 bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
9134 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
9135 bool isMachO = MAI->hasSubsectionsViaSymbols();
9137 Error(L, ".object_arch directive not valid for Mach-O");
9138 Parser.eatToEndOfStatement();
9142 if (getLexer().isNot(AsmToken::Identifier)) {
9143 Error(getLexer().getLoc(), "unexpected token");
9144 Parser.eatToEndOfStatement();
9148 StringRef Arch = Parser.getTok().getString();
9149 SMLoc ArchLoc = Parser.getTok().getLoc();
9152 unsigned ID = StringSwitch<unsigned>(Arch)
9153 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
9154 .Case(NAME, ARM::ID)
9155 #define ARM_ARCH_ALIAS(NAME, ID) \
9156 .Case(NAME, ARM::ID)
9157 #include "MCTargetDesc/ARMArchName.def"
9158 #undef ARM_ARCH_NAME
9159 #undef ARM_ARCH_ALIAS
9160 .Default(ARM::INVALID_ARCH);
9162 if (ID == ARM::INVALID_ARCH) {
9163 Error(ArchLoc, "unknown architecture '" + Arch + "'");
9164 Parser.eatToEndOfStatement();
9168 getTargetStreamer().emitObjectArch(ID);
9170 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9171 Error(getLexer().getLoc(), "unexpected token");
9172 Parser.eatToEndOfStatement();
9178 /// parseDirectiveAlign
9180 bool ARMAsmParser::parseDirectiveAlign(SMLoc L) {
9181 // NOTE: if this is not the end of the statement, fall back to the target
9182 // agnostic handling for this directive which will correctly handle this.
9183 if (getLexer().isNot(AsmToken::EndOfStatement))
9186 // '.align' is target specifically handled to mean 2**2 byte alignment.
9187 if (getStreamer().getCurrentSection().first->UseCodeAlign())
9188 getStreamer().EmitCodeAlignment(4, 0);
9190 getStreamer().EmitValueToAlignment(4, 0, 1, 0);
9195 /// parseDirectiveThumbSet
9196 /// ::= .thumb_set name, value
9197 bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) {
9199 if (Parser.parseIdentifier(Name)) {
9200 TokError("expected identifier after '.thumb_set'");
9201 Parser.eatToEndOfStatement();
9205 if (getLexer().isNot(AsmToken::Comma)) {
9206 TokError("expected comma after name '" + Name + "'");
9207 Parser.eatToEndOfStatement();
9212 const MCExpr *Value;
9213 if (Parser.parseExpression(Value)) {
9214 TokError("missing expression");
9215 Parser.eatToEndOfStatement();
9219 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9220 TokError("unexpected token");
9221 Parser.eatToEndOfStatement();
9226 MCSymbol *Alias = getContext().GetOrCreateSymbol(Name);
9227 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Value)) {
9228 MCSymbol *Sym = getContext().LookupSymbol(SRE->getSymbol().getName());
9229 if (!Sym->isDefined()) {
9230 getStreamer().EmitSymbolAttribute(Sym, MCSA_Global);
9231 getStreamer().EmitAssignment(Alias, Value);
9235 const MCObjectFileInfo::Environment Format =
9236 getContext().getObjectFileInfo()->getObjectFileType();
9238 case MCObjectFileInfo::IsCOFF: {
9239 char Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
9240 getStreamer().EmitCOFFSymbolType(Type);
9241 // .set values are always local in COFF
9242 getStreamer().EmitSymbolAttribute(Alias, MCSA_Local);
9245 case MCObjectFileInfo::IsELF:
9246 getStreamer().EmitSymbolAttribute(Alias, MCSA_ELF_TypeFunction);
9248 case MCObjectFileInfo::IsMachO:
9253 // FIXME: set the function as being a thumb function via the assembler
9254 getStreamer().EmitThumbFunc(Alias);
9255 getStreamer().EmitAssignment(Alias, Value);
9260 /// Force static initialization.
9261 extern "C" void LLVMInitializeARMAsmParser() {
9262 RegisterMCAsmParser<ARMAsmParser> X(TheARMLETarget);
9263 RegisterMCAsmParser<ARMAsmParser> Y(TheARMBETarget);
9264 RegisterMCAsmParser<ARMAsmParser> A(TheThumbLETarget);
9265 RegisterMCAsmParser<ARMAsmParser> B(TheThumbBETarget);
9268 #define GET_REGISTER_MATCHER
9269 #define GET_SUBTARGET_FEATURE_NAME
9270 #define GET_MATCHER_IMPLEMENTATION
9271 #include "ARMGenAsmMatcher.inc"
9273 static const struct ExtMapEntry {
9274 const char *Extension;
9275 const unsigned ArchCheck;
9276 const uint64_t Features;
9278 { "crc", Feature_HasV8, ARM::FeatureCRC },
9279 { "crypto", Feature_HasV8,
9280 ARM::FeatureCrypto | ARM::FeatureNEON | ARM::FeatureFPARMv8 },
9281 { "fp", Feature_HasV8, ARM::FeatureFPARMv8 },
9282 { "idiv", Feature_HasV7 | Feature_IsNotMClass,
9283 ARM::FeatureHWDiv | ARM::FeatureHWDivARM },
9284 // FIXME: iWMMXT not supported
9285 { "iwmmxt", Feature_None, 0 },
9286 // FIXME: iWMMXT2 not supported
9287 { "iwmmxt2", Feature_None, 0 },
9288 // FIXME: Maverick not supported
9289 { "maverick", Feature_None, 0 },
9290 { "mp", Feature_HasV7 | Feature_IsNotMClass, ARM::FeatureMP },
9291 // FIXME: ARMv6-m OS Extensions feature not checked
9292 { "os", Feature_None, 0 },
9293 // FIXME: Also available in ARMv6-K
9294 { "sec", Feature_HasV7, ARM::FeatureTrustZone },
9295 { "simd", Feature_HasV8, ARM::FeatureNEON | ARM::FeatureFPARMv8 },
9296 // FIXME: Only available in A-class, isel not predicated
9297 { "virt", Feature_HasV7, ARM::FeatureVirtualization },
9298 // FIXME: xscale not supported
9299 { "xscale", Feature_None, 0 },
9302 /// parseDirectiveArchExtension
9303 /// ::= .arch_extension [no]feature
9304 bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
9305 if (getLexer().isNot(AsmToken::Identifier)) {
9306 Error(getLexer().getLoc(), "unexpected token");
9307 Parser.eatToEndOfStatement();
9311 StringRef Extension = Parser.getTok().getString();
9312 SMLoc ExtLoc = Parser.getTok().getLoc();
9315 bool EnableFeature = true;
9316 if (Extension.startswith_lower("no")) {
9317 EnableFeature = false;
9318 Extension = Extension.substr(2);
9321 for (unsigned EI = 0, EE = array_lengthof(Extensions); EI != EE; ++EI) {
9322 if (Extensions[EI].Extension != Extension)
9325 unsigned FB = getAvailableFeatures();
9326 if ((FB & Extensions[EI].ArchCheck) != Extensions[EI].ArchCheck) {
9327 Error(ExtLoc, "architectural extension '" + Extension + "' is not "
9328 "allowed for the current base architecture");
9332 if (!Extensions[EI].Features)
9333 report_fatal_error("unsupported architectural extension: " + Extension);
9336 FB |= ComputeAvailableFeatures(Extensions[EI].Features);
9338 FB &= ~ComputeAvailableFeatures(Extensions[EI].Features);
9340 setAvailableFeatures(FB);
9344 Error(ExtLoc, "unknown architectural extension: " + Extension);
9345 Parser.eatToEndOfStatement();
9349 // Define this matcher function after the auto-generated include so we
9350 // have the match class enum definitions.
9351 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
9353 ARMOperand *Op = static_cast<ARMOperand*>(AsmOp);
9354 // If the kind is a token for a literal immediate, check if our asm
9355 // operand matches. This is for InstAliases which have a fixed-value
9356 // immediate in the syntax.
9361 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()))
9362 if (CE->getValue() == 0)
9363 return Match_Success;
9367 const MCExpr *SOExpr = Op->getImm();
9369 if (!SOExpr->EvaluateAsAbsolute(Value))
9370 return Match_Success;
9371 assert((Value >= INT32_MIN && Value <= INT32_MAX) &&
9372 "expression value must be representiable in 32 bits");
9377 MRI->getRegClass(ARM::GPRRegClassID).contains(Op->getReg()))
9378 return Match_Success;
9381 return Match_InvalidOperand;