1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMBaseInfo.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMMCExpr.h"
13 #include "llvm/MC/MCParser/MCAsmLexer.h"
14 #include "llvm/MC/MCParser/MCAsmParser.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCAsmInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCTargetAsmParser.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/SourceMgr.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/ADT/BitVector.h"
30 #include "llvm/ADT/OwningPtr.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/StringSwitch.h"
34 #include "llvm/ADT/Twine.h"
42 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
44 class ARMAsmParser : public MCTargetAsmParser {
48 // Map of register aliases registers via the .req directive.
49 StringMap<unsigned> RegisterReqs;
52 ARMCC::CondCodes Cond; // Condition for IT block.
53 unsigned Mask:4; // Condition mask for instructions.
54 // Starting at first 1 (from lsb).
55 // '1' condition as indicated in IT.
56 // '0' inverse of condition (else).
57 // Count of instructions in IT block is
58 // 4 - trailingzeroes(mask)
60 bool FirstCond; // Explicit flag for when we're parsing the
61 // First instruction in the IT block. It's
62 // implied in the mask, so needs special
65 unsigned CurPosition; // Current position in parsing of IT
66 // block. In range [0,3]. Initialized
67 // according to count of instructions in block.
68 // ~0U if no active IT block.
70 bool inITBlock() { return ITState.CurPosition != ~0U;}
71 void forwardITPosition() {
72 if (!inITBlock()) return;
73 // Move to the next instruction in the IT block, if there is one. If not,
74 // mark the block as done.
75 unsigned TZ = CountTrailingZeros_32(ITState.Mask);
76 if (++ITState.CurPosition == 5 - TZ)
77 ITState.CurPosition = ~0U; // Done with the IT block after this.
81 MCAsmParser &getParser() const { return Parser; }
82 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
84 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
85 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
87 int tryParseRegister();
88 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
89 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
90 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
91 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
92 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
93 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
94 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
95 unsigned &ShiftAmount);
96 bool parseDirectiveWord(unsigned Size, SMLoc L);
97 bool parseDirectiveThumb(SMLoc L);
98 bool parseDirectiveARM(SMLoc L);
99 bool parseDirectiveThumbFunc(SMLoc L);
100 bool parseDirectiveCode(SMLoc L);
101 bool parseDirectiveSyntax(SMLoc L);
102 bool parseDirectiveReq(StringRef Name, SMLoc L);
103 bool parseDirectiveUnreq(SMLoc L);
104 bool parseDirectiveArch(SMLoc L);
105 bool parseDirectiveEabiAttr(SMLoc L);
107 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
108 bool &CarrySetting, unsigned &ProcessorIMod,
110 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
111 bool &CanAcceptPredicationCode);
113 bool isThumb() const {
114 // FIXME: Can tablegen auto-generate this?
115 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
117 bool isThumbOne() const {
118 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
120 bool isThumbTwo() const {
121 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
123 bool hasV6Ops() const {
124 return STI.getFeatureBits() & ARM::HasV6Ops;
126 bool hasV7Ops() const {
127 return STI.getFeatureBits() & ARM::HasV7Ops;
130 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
131 setAvailableFeatures(FB);
133 bool isMClass() const {
134 return STI.getFeatureBits() & ARM::FeatureMClass;
137 /// @name Auto-generated Match Functions
140 #define GET_ASSEMBLER_HEADER
141 #include "ARMGenAsmMatcher.inc"
145 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
146 OperandMatchResultTy parseCoprocNumOperand(
147 SmallVectorImpl<MCParsedAsmOperand*>&);
148 OperandMatchResultTy parseCoprocRegOperand(
149 SmallVectorImpl<MCParsedAsmOperand*>&);
150 OperandMatchResultTy parseCoprocOptionOperand(
151 SmallVectorImpl<MCParsedAsmOperand*>&);
152 OperandMatchResultTy parseMemBarrierOptOperand(
153 SmallVectorImpl<MCParsedAsmOperand*>&);
154 OperandMatchResultTy parseProcIFlagsOperand(
155 SmallVectorImpl<MCParsedAsmOperand*>&);
156 OperandMatchResultTy parseMSRMaskOperand(
157 SmallVectorImpl<MCParsedAsmOperand*>&);
158 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
159 StringRef Op, int Low, int High);
160 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
161 return parsePKHImm(O, "lsl", 0, 31);
163 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
164 return parsePKHImm(O, "asr", 1, 32);
166 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
167 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
168 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
169 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
170 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
171 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
172 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
173 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
174 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index);
176 // Asm Match Converter Methods
177 bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
178 const SmallVectorImpl<MCParsedAsmOperand*> &);
179 bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
180 const SmallVectorImpl<MCParsedAsmOperand*> &);
181 bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
182 const SmallVectorImpl<MCParsedAsmOperand*> &);
183 bool cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
184 const SmallVectorImpl<MCParsedAsmOperand*> &);
185 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
186 const SmallVectorImpl<MCParsedAsmOperand*> &);
187 bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
188 const SmallVectorImpl<MCParsedAsmOperand*> &);
189 bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
190 const SmallVectorImpl<MCParsedAsmOperand*> &);
191 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
192 const SmallVectorImpl<MCParsedAsmOperand*> &);
193 bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
194 const SmallVectorImpl<MCParsedAsmOperand*> &);
195 bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
196 const SmallVectorImpl<MCParsedAsmOperand*> &);
197 bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
198 const SmallVectorImpl<MCParsedAsmOperand*> &);
199 bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
200 const SmallVectorImpl<MCParsedAsmOperand*> &);
201 bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
202 const SmallVectorImpl<MCParsedAsmOperand*> &);
203 bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
204 const SmallVectorImpl<MCParsedAsmOperand*> &);
205 bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
206 const SmallVectorImpl<MCParsedAsmOperand*> &);
207 bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
208 const SmallVectorImpl<MCParsedAsmOperand*> &);
209 bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
210 const SmallVectorImpl<MCParsedAsmOperand*> &);
211 bool cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
212 const SmallVectorImpl<MCParsedAsmOperand*> &);
213 bool cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
214 const SmallVectorImpl<MCParsedAsmOperand*> &);
215 bool cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
216 const SmallVectorImpl<MCParsedAsmOperand*> &);
217 bool cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
218 const SmallVectorImpl<MCParsedAsmOperand*> &);
220 bool validateInstruction(MCInst &Inst,
221 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
222 bool processInstruction(MCInst &Inst,
223 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
224 bool shouldOmitCCOutOperand(StringRef Mnemonic,
225 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
228 enum ARMMatchResultTy {
229 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
230 Match_RequiresNotITBlock,
235 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
236 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
237 MCAsmParserExtension::Initialize(_Parser);
239 // Initialize the set of available features.
240 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
242 // Not in an ITBlock to start with.
243 ITState.CurPosition = ~0U;
246 // Implementation of the MCTargetAsmParser interface:
247 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
248 bool ParseInstruction(StringRef Name, SMLoc NameLoc,
249 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
250 bool ParseDirective(AsmToken DirectiveID);
252 unsigned checkTargetMatchPredicate(MCInst &Inst);
254 bool MatchAndEmitInstruction(SMLoc IDLoc,
255 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
258 } // end anonymous namespace
262 /// ARMOperand - Instances of this class represent a parsed ARM machine
264 class ARMOperand : public MCParsedAsmOperand {
285 k_VectorListAllLanes,
291 k_BitfieldDescriptor,
295 SMLoc StartLoc, EndLoc;
296 SmallVector<unsigned, 8> Registers;
300 ARMCC::CondCodes Val;
320 ARM_PROC::IFlags Val;
336 // A vector register list is a sequential list of 1 to 4 registers.
353 unsigned Val; // encoded 8-bit representation
356 /// Combined record for all forms of ARM address expressions.
359 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
361 const MCConstantExpr *OffsetImm; // Offset immediate value
362 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
363 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
364 unsigned ShiftImm; // shift for OffsetReg.
365 unsigned Alignment; // 0 = no alignment specified
366 // n = alignment in bytes (2, 4, 8, 16, or 32)
367 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
373 ARM_AM::ShiftOpc ShiftTy;
382 ARM_AM::ShiftOpc ShiftTy;
388 ARM_AM::ShiftOpc ShiftTy;
401 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
403 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
405 StartLoc = o.StartLoc;
422 case k_DPRRegisterList:
423 case k_SPRRegisterList:
424 Registers = o.Registers;
427 case k_VectorListAllLanes:
428 case k_VectorListIndexed:
429 VectorList = o.VectorList;
436 CoprocOption = o.CoprocOption;
444 case k_MemBarrierOpt:
450 case k_PostIndexRegister:
451 PostIdxReg = o.PostIdxReg;
459 case k_ShifterImmediate:
460 ShifterImm = o.ShifterImm;
462 case k_ShiftedRegister:
463 RegShiftedReg = o.RegShiftedReg;
465 case k_ShiftedImmediate:
466 RegShiftedImm = o.RegShiftedImm;
468 case k_RotateImmediate:
471 case k_BitfieldDescriptor:
472 Bitfield = o.Bitfield;
475 VectorIndex = o.VectorIndex;
480 /// getStartLoc - Get the location of the first token of this operand.
481 SMLoc getStartLoc() const { return StartLoc; }
482 /// getEndLoc - Get the location of the last token of this operand.
483 SMLoc getEndLoc() const { return EndLoc; }
485 ARMCC::CondCodes getCondCode() const {
486 assert(Kind == k_CondCode && "Invalid access!");
490 unsigned getCoproc() const {
491 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
495 StringRef getToken() const {
496 assert(Kind == k_Token && "Invalid access!");
497 return StringRef(Tok.Data, Tok.Length);
500 unsigned getReg() const {
501 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
505 const SmallVectorImpl<unsigned> &getRegList() const {
506 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
507 Kind == k_SPRRegisterList) && "Invalid access!");
511 const MCExpr *getImm() const {
512 assert(Kind == k_Immediate && "Invalid access!");
516 unsigned getFPImm() const {
517 assert(Kind == k_FPImmediate && "Invalid access!");
521 unsigned getVectorIndex() const {
522 assert(Kind == k_VectorIndex && "Invalid access!");
523 return VectorIndex.Val;
526 ARM_MB::MemBOpt getMemBarrierOpt() const {
527 assert(Kind == k_MemBarrierOpt && "Invalid access!");
531 ARM_PROC::IFlags getProcIFlags() const {
532 assert(Kind == k_ProcIFlags && "Invalid access!");
536 unsigned getMSRMask() const {
537 assert(Kind == k_MSRMask && "Invalid access!");
541 bool isCoprocNum() const { return Kind == k_CoprocNum; }
542 bool isCoprocReg() const { return Kind == k_CoprocReg; }
543 bool isCoprocOption() const { return Kind == k_CoprocOption; }
544 bool isCondCode() const { return Kind == k_CondCode; }
545 bool isCCOut() const { return Kind == k_CCOut; }
546 bool isITMask() const { return Kind == k_ITCondMask; }
547 bool isITCondCode() const { return Kind == k_CondCode; }
548 bool isImm() const { return Kind == k_Immediate; }
549 bool isFPImm() const { return Kind == k_FPImmediate; }
550 bool isImm8s4() const {
551 if (Kind != k_Immediate)
553 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
554 if (!CE) return false;
555 int64_t Value = CE->getValue();
556 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
558 bool isImm0_1020s4() const {
559 if (Kind != k_Immediate)
561 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
562 if (!CE) return false;
563 int64_t Value = CE->getValue();
564 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
566 bool isImm0_508s4() const {
567 if (Kind != k_Immediate)
569 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
570 if (!CE) return false;
571 int64_t Value = CE->getValue();
572 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
574 bool isImm0_255() const {
575 if (Kind != k_Immediate)
577 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
578 if (!CE) return false;
579 int64_t Value = CE->getValue();
580 return Value >= 0 && Value < 256;
582 bool isImm0_1() const {
583 if (Kind != k_Immediate)
585 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
586 if (!CE) return false;
587 int64_t Value = CE->getValue();
588 return Value >= 0 && Value < 2;
590 bool isImm0_3() const {
591 if (Kind != k_Immediate)
593 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
594 if (!CE) return false;
595 int64_t Value = CE->getValue();
596 return Value >= 0 && Value < 4;
598 bool isImm0_7() const {
599 if (Kind != k_Immediate)
601 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
602 if (!CE) return false;
603 int64_t Value = CE->getValue();
604 return Value >= 0 && Value < 8;
606 bool isImm0_15() const {
607 if (Kind != k_Immediate)
609 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
610 if (!CE) return false;
611 int64_t Value = CE->getValue();
612 return Value >= 0 && Value < 16;
614 bool isImm0_31() const {
615 if (Kind != k_Immediate)
617 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
618 if (!CE) return false;
619 int64_t Value = CE->getValue();
620 return Value >= 0 && Value < 32;
622 bool isImm0_63() const {
623 if (Kind != k_Immediate)
625 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
626 if (!CE) return false;
627 int64_t Value = CE->getValue();
628 return Value >= 0 && Value < 64;
630 bool isImm8() const {
631 if (Kind != k_Immediate)
633 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
634 if (!CE) return false;
635 int64_t Value = CE->getValue();
638 bool isImm16() const {
639 if (Kind != k_Immediate)
641 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
642 if (!CE) return false;
643 int64_t Value = CE->getValue();
646 bool isImm32() const {
647 if (Kind != k_Immediate)
649 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
650 if (!CE) return false;
651 int64_t Value = CE->getValue();
654 bool isShrImm8() const {
655 if (Kind != k_Immediate)
657 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
658 if (!CE) return false;
659 int64_t Value = CE->getValue();
660 return Value > 0 && Value <= 8;
662 bool isShrImm16() const {
663 if (Kind != k_Immediate)
665 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
666 if (!CE) return false;
667 int64_t Value = CE->getValue();
668 return Value > 0 && Value <= 16;
670 bool isShrImm32() const {
671 if (Kind != k_Immediate)
673 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
674 if (!CE) return false;
675 int64_t Value = CE->getValue();
676 return Value > 0 && Value <= 32;
678 bool isShrImm64() const {
679 if (Kind != k_Immediate)
681 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
682 if (!CE) return false;
683 int64_t Value = CE->getValue();
684 return Value > 0 && Value <= 64;
686 bool isImm1_7() const {
687 if (Kind != k_Immediate)
689 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
690 if (!CE) return false;
691 int64_t Value = CE->getValue();
692 return Value > 0 && Value < 8;
694 bool isImm1_15() const {
695 if (Kind != k_Immediate)
697 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
698 if (!CE) return false;
699 int64_t Value = CE->getValue();
700 return Value > 0 && Value < 16;
702 bool isImm1_31() const {
703 if (Kind != k_Immediate)
705 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
706 if (!CE) return false;
707 int64_t Value = CE->getValue();
708 return Value > 0 && Value < 32;
710 bool isImm1_16() const {
711 if (Kind != k_Immediate)
713 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
714 if (!CE) return false;
715 int64_t Value = CE->getValue();
716 return Value > 0 && Value < 17;
718 bool isImm1_32() const {
719 if (Kind != k_Immediate)
721 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
722 if (!CE) return false;
723 int64_t Value = CE->getValue();
724 return Value > 0 && Value < 33;
726 bool isImm0_32() const {
727 if (Kind != k_Immediate)
729 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
730 if (!CE) return false;
731 int64_t Value = CE->getValue();
732 return Value >= 0 && Value < 33;
734 bool isImm0_65535() const {
735 if (Kind != k_Immediate)
737 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
738 if (!CE) return false;
739 int64_t Value = CE->getValue();
740 return Value >= 0 && Value < 65536;
742 bool isImm0_65535Expr() const {
743 if (Kind != k_Immediate)
745 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
746 // If it's not a constant expression, it'll generate a fixup and be
748 if (!CE) return true;
749 int64_t Value = CE->getValue();
750 return Value >= 0 && Value < 65536;
752 bool isImm24bit() const {
753 if (Kind != k_Immediate)
755 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
756 if (!CE) return false;
757 int64_t Value = CE->getValue();
758 return Value >= 0 && Value <= 0xffffff;
760 bool isImmThumbSR() const {
761 if (Kind != k_Immediate)
763 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
764 if (!CE) return false;
765 int64_t Value = CE->getValue();
766 return Value > 0 && Value < 33;
768 bool isPKHLSLImm() const {
769 if (Kind != k_Immediate)
771 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
772 if (!CE) return false;
773 int64_t Value = CE->getValue();
774 return Value >= 0 && Value < 32;
776 bool isPKHASRImm() const {
777 if (Kind != k_Immediate)
779 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
780 if (!CE) return false;
781 int64_t Value = CE->getValue();
782 return Value > 0 && Value <= 32;
784 bool isARMSOImm() const {
785 if (Kind != k_Immediate)
787 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
788 if (!CE) return false;
789 int64_t Value = CE->getValue();
790 return ARM_AM::getSOImmVal(Value) != -1;
792 bool isARMSOImmNot() const {
793 if (Kind != k_Immediate)
795 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
796 if (!CE) return false;
797 int64_t Value = CE->getValue();
798 return ARM_AM::getSOImmVal(~Value) != -1;
800 bool isARMSOImmNeg() const {
801 if (Kind != k_Immediate)
803 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
804 if (!CE) return false;
805 int64_t Value = CE->getValue();
806 return ARM_AM::getSOImmVal(-Value) != -1;
808 bool isT2SOImm() const {
809 if (Kind != k_Immediate)
811 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
812 if (!CE) return false;
813 int64_t Value = CE->getValue();
814 return ARM_AM::getT2SOImmVal(Value) != -1;
816 bool isT2SOImmNot() const {
817 if (Kind != k_Immediate)
819 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
820 if (!CE) return false;
821 int64_t Value = CE->getValue();
822 return ARM_AM::getT2SOImmVal(~Value) != -1;
824 bool isT2SOImmNeg() const {
825 if (Kind != k_Immediate)
827 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
828 if (!CE) return false;
829 int64_t Value = CE->getValue();
830 return ARM_AM::getT2SOImmVal(-Value) != -1;
832 bool isSetEndImm() const {
833 if (Kind != k_Immediate)
835 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
836 if (!CE) return false;
837 int64_t Value = CE->getValue();
838 return Value == 1 || Value == 0;
840 bool isReg() const { return Kind == k_Register; }
841 bool isRegList() const { return Kind == k_RegisterList; }
842 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
843 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
844 bool isToken() const { return Kind == k_Token; }
845 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
846 bool isMemory() const { return Kind == k_Memory; }
847 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
848 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
849 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
850 bool isRotImm() const { return Kind == k_RotateImmediate; }
851 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
852 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
853 bool isPostIdxReg() const {
854 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
856 bool isMemNoOffset(bool alignOK = false) const {
859 // No offset of any kind.
860 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
861 (alignOK || Memory.Alignment == 0);
863 bool isAlignedMemory() const {
864 return isMemNoOffset(true);
866 bool isAddrMode2() const {
867 if (!isMemory() || Memory.Alignment != 0) return false;
868 // Check for register offset.
869 if (Memory.OffsetRegNum) return true;
870 // Immediate offset in range [-4095, 4095].
871 if (!Memory.OffsetImm) return true;
872 int64_t Val = Memory.OffsetImm->getValue();
873 return Val > -4096 && Val < 4096;
875 bool isAM2OffsetImm() const {
876 if (Kind != k_Immediate)
878 // Immediate offset in range [-4095, 4095].
879 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
880 if (!CE) return false;
881 int64_t Val = CE->getValue();
882 return Val > -4096 && Val < 4096;
884 bool isAddrMode3() const {
885 // If we have an immediate that's not a constant, treat it as a label
886 // reference needing a fixup. If it is a constant, it's something else
888 if (Kind == k_Immediate && !isa<MCConstantExpr>(getImm()))
890 if (!isMemory() || Memory.Alignment != 0) return false;
891 // No shifts are legal for AM3.
892 if (Memory.ShiftType != ARM_AM::no_shift) return false;
893 // Check for register offset.
894 if (Memory.OffsetRegNum) return true;
895 // Immediate offset in range [-255, 255].
896 if (!Memory.OffsetImm) return true;
897 int64_t Val = Memory.OffsetImm->getValue();
898 return Val > -256 && Val < 256;
900 bool isAM3Offset() const {
901 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
903 if (Kind == k_PostIndexRegister)
904 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
905 // Immediate offset in range [-255, 255].
906 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
907 if (!CE) return false;
908 int64_t Val = CE->getValue();
909 // Special case, #-0 is INT32_MIN.
910 return (Val > -256 && Val < 256) || Val == INT32_MIN;
912 bool isAddrMode5() const {
913 // If we have an immediate that's not a constant, treat it as a label
914 // reference needing a fixup. If it is a constant, it's something else
916 if (Kind == k_Immediate && !isa<MCConstantExpr>(getImm()))
918 if (!isMemory() || Memory.Alignment != 0) return false;
919 // Check for register offset.
920 if (Memory.OffsetRegNum) return false;
921 // Immediate offset in range [-1020, 1020] and a multiple of 4.
922 if (!Memory.OffsetImm) return true;
923 int64_t Val = Memory.OffsetImm->getValue();
924 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
927 bool isMemTBB() const {
928 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
929 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
933 bool isMemTBH() const {
934 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
935 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
936 Memory.Alignment != 0 )
940 bool isMemRegOffset() const {
941 if (!isMemory() || !Memory.OffsetRegNum || Memory.Alignment != 0)
945 bool isT2MemRegOffset() const {
946 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
947 Memory.Alignment != 0)
949 // Only lsl #{0, 1, 2, 3} allowed.
950 if (Memory.ShiftType == ARM_AM::no_shift)
952 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
956 bool isMemThumbRR() const {
957 // Thumb reg+reg addressing is simple. Just two registers, a base and
958 // an offset. No shifts, negations or any other complicating factors.
959 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
960 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
962 return isARMLowRegister(Memory.BaseRegNum) &&
963 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
965 bool isMemThumbRIs4() const {
966 if (!isMemory() || Memory.OffsetRegNum != 0 ||
967 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
969 // Immediate offset, multiple of 4 in range [0, 124].
970 if (!Memory.OffsetImm) return true;
971 int64_t Val = Memory.OffsetImm->getValue();
972 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
974 bool isMemThumbRIs2() const {
975 if (!isMemory() || Memory.OffsetRegNum != 0 ||
976 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
978 // Immediate offset, multiple of 4 in range [0, 62].
979 if (!Memory.OffsetImm) return true;
980 int64_t Val = Memory.OffsetImm->getValue();
981 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
983 bool isMemThumbRIs1() const {
984 if (!isMemory() || Memory.OffsetRegNum != 0 ||
985 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
987 // Immediate offset in range [0, 31].
988 if (!Memory.OffsetImm) return true;
989 int64_t Val = Memory.OffsetImm->getValue();
990 return Val >= 0 && Val <= 31;
992 bool isMemThumbSPI() const {
993 if (!isMemory() || Memory.OffsetRegNum != 0 ||
994 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
996 // Immediate offset, multiple of 4 in range [0, 1020].
997 if (!Memory.OffsetImm) return true;
998 int64_t Val = Memory.OffsetImm->getValue();
999 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1001 bool isMemImm8s4Offset() const {
1002 // If we have an immediate that's not a constant, treat it as a label
1003 // reference needing a fixup. If it is a constant, it's something else
1004 // and we reject it.
1005 if (Kind == k_Immediate && !isa<MCConstantExpr>(getImm()))
1007 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1009 // Immediate offset a multiple of 4 in range [-1020, 1020].
1010 if (!Memory.OffsetImm) return true;
1011 int64_t Val = Memory.OffsetImm->getValue();
1012 return Val >= -1020 && Val <= 1020 && (Val & 3) == 0;
1014 bool isMemImm0_1020s4Offset() const {
1015 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1017 // Immediate offset a multiple of 4 in range [0, 1020].
1018 if (!Memory.OffsetImm) return true;
1019 int64_t Val = Memory.OffsetImm->getValue();
1020 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1022 bool isMemImm8Offset() const {
1023 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1025 // Immediate offset in range [-255, 255].
1026 if (!Memory.OffsetImm) return true;
1027 int64_t Val = Memory.OffsetImm->getValue();
1028 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1030 bool isMemPosImm8Offset() const {
1031 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1033 // Immediate offset in range [0, 255].
1034 if (!Memory.OffsetImm) return true;
1035 int64_t Val = Memory.OffsetImm->getValue();
1036 return Val >= 0 && Val < 256;
1038 bool isMemNegImm8Offset() const {
1039 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1041 // Immediate offset in range [-255, -1].
1042 if (!Memory.OffsetImm) return false;
1043 int64_t Val = Memory.OffsetImm->getValue();
1044 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1046 bool isMemUImm12Offset() const {
1047 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1049 // Immediate offset in range [0, 4095].
1050 if (!Memory.OffsetImm) return true;
1051 int64_t Val = Memory.OffsetImm->getValue();
1052 return (Val >= 0 && Val < 4096);
1054 bool isMemImm12Offset() const {
1055 // If we have an immediate that's not a constant, treat it as a label
1056 // reference needing a fixup. If it is a constant, it's something else
1057 // and we reject it.
1058 if (Kind == k_Immediate && !isa<MCConstantExpr>(getImm()))
1061 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1063 // Immediate offset in range [-4095, 4095].
1064 if (!Memory.OffsetImm) return true;
1065 int64_t Val = Memory.OffsetImm->getValue();
1066 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1068 bool isPostIdxImm8() const {
1069 if (Kind != k_Immediate)
1071 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1072 if (!CE) return false;
1073 int64_t Val = CE->getValue();
1074 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1076 bool isPostIdxImm8s4() const {
1077 if (Kind != k_Immediate)
1079 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1080 if (!CE) return false;
1081 int64_t Val = CE->getValue();
1082 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1086 bool isMSRMask() const { return Kind == k_MSRMask; }
1087 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1090 bool isSingleSpacedVectorList() const {
1091 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1093 bool isDoubleSpacedVectorList() const {
1094 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1096 bool isVecListOneD() const {
1097 if (!isSingleSpacedVectorList()) return false;
1098 return VectorList.Count == 1;
1101 bool isVecListTwoD() const {
1102 if (!isSingleSpacedVectorList()) return false;
1103 return VectorList.Count == 2;
1106 bool isVecListThreeD() const {
1107 if (!isSingleSpacedVectorList()) return false;
1108 return VectorList.Count == 3;
1111 bool isVecListFourD() const {
1112 if (!isSingleSpacedVectorList()) return false;
1113 return VectorList.Count == 4;
1116 bool isVecListTwoQ() const {
1117 if (!isDoubleSpacedVectorList()) return false;
1118 return VectorList.Count == 2;
1121 bool isSingleSpacedVectorAllLanes() const {
1122 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1124 bool isDoubleSpacedVectorAllLanes() const {
1125 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1127 bool isVecListOneDAllLanes() const {
1128 if (!isSingleSpacedVectorAllLanes()) return false;
1129 return VectorList.Count == 1;
1132 bool isVecListTwoDAllLanes() const {
1133 if (!isSingleSpacedVectorAllLanes()) return false;
1134 return VectorList.Count == 2;
1137 bool isVecListTwoQAllLanes() const {
1138 if (!isDoubleSpacedVectorAllLanes()) return false;
1139 return VectorList.Count == 2;
1142 bool isSingleSpacedVectorIndexed() const {
1143 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1145 bool isDoubleSpacedVectorIndexed() const {
1146 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1148 bool isVecListOneDByteIndexed() const {
1149 if (!isSingleSpacedVectorIndexed()) return false;
1150 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1153 bool isVecListOneDHWordIndexed() const {
1154 if (!isSingleSpacedVectorIndexed()) return false;
1155 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1158 bool isVecListOneDWordIndexed() const {
1159 if (!isSingleSpacedVectorIndexed()) return false;
1160 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1163 bool isVecListTwoDByteIndexed() const {
1164 if (!isSingleSpacedVectorIndexed()) return false;
1165 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1168 bool isVecListTwoDHWordIndexed() const {
1169 if (!isSingleSpacedVectorIndexed()) return false;
1170 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1173 bool isVecListTwoQWordIndexed() const {
1174 if (!isDoubleSpacedVectorIndexed()) return false;
1175 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1178 bool isVecListTwoQHWordIndexed() const {
1179 if (!isDoubleSpacedVectorIndexed()) return false;
1180 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1183 bool isVecListTwoDWordIndexed() const {
1184 if (!isSingleSpacedVectorIndexed()) return false;
1185 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1188 bool isVectorIndex8() const {
1189 if (Kind != k_VectorIndex) return false;
1190 return VectorIndex.Val < 8;
1192 bool isVectorIndex16() const {
1193 if (Kind != k_VectorIndex) return false;
1194 return VectorIndex.Val < 4;
1196 bool isVectorIndex32() const {
1197 if (Kind != k_VectorIndex) return false;
1198 return VectorIndex.Val < 2;
1201 bool isNEONi8splat() const {
1202 if (Kind != k_Immediate)
1204 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1205 // Must be a constant.
1206 if (!CE) return false;
1207 int64_t Value = CE->getValue();
1208 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1210 return Value >= 0 && Value < 256;
1213 bool isNEONi16splat() const {
1214 if (Kind != k_Immediate)
1216 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1217 // Must be a constant.
1218 if (!CE) return false;
1219 int64_t Value = CE->getValue();
1220 // i16 value in the range [0,255] or [0x0100, 0xff00]
1221 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1224 bool isNEONi32splat() const {
1225 if (Kind != k_Immediate)
1227 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1228 // Must be a constant.
1229 if (!CE) return false;
1230 int64_t Value = CE->getValue();
1231 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1232 return (Value >= 0 && Value < 256) ||
1233 (Value >= 0x0100 && Value <= 0xff00) ||
1234 (Value >= 0x010000 && Value <= 0xff0000) ||
1235 (Value >= 0x01000000 && Value <= 0xff000000);
1238 bool isNEONi32vmov() const {
1239 if (Kind != k_Immediate)
1241 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1242 // Must be a constant.
1243 if (!CE) return false;
1244 int64_t Value = CE->getValue();
1245 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1246 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1247 return (Value >= 0 && Value < 256) ||
1248 (Value >= 0x0100 && Value <= 0xff00) ||
1249 (Value >= 0x010000 && Value <= 0xff0000) ||
1250 (Value >= 0x01000000 && Value <= 0xff000000) ||
1251 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1252 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1254 bool isNEONi32vmovNeg() const {
1255 if (Kind != k_Immediate)
1257 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1258 // Must be a constant.
1259 if (!CE) return false;
1260 int64_t Value = ~CE->getValue();
1261 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1262 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1263 return (Value >= 0 && Value < 256) ||
1264 (Value >= 0x0100 && Value <= 0xff00) ||
1265 (Value >= 0x010000 && Value <= 0xff0000) ||
1266 (Value >= 0x01000000 && Value <= 0xff000000) ||
1267 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1268 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1271 bool isNEONi64splat() const {
1272 if (Kind != k_Immediate)
1274 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1275 // Must be a constant.
1276 if (!CE) return false;
1277 uint64_t Value = CE->getValue();
1278 // i64 value with each byte being either 0 or 0xff.
1279 for (unsigned i = 0; i < 8; ++i)
1280 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1284 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1285 // Add as immediates when possible. Null MCExpr = 0.
1287 Inst.addOperand(MCOperand::CreateImm(0));
1288 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1289 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1291 Inst.addOperand(MCOperand::CreateExpr(Expr));
1294 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1295 assert(N == 2 && "Invalid number of operands!");
1296 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1297 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1298 Inst.addOperand(MCOperand::CreateReg(RegNum));
1301 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1302 assert(N == 1 && "Invalid number of operands!");
1303 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1306 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1307 assert(N == 1 && "Invalid number of operands!");
1308 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1311 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1312 assert(N == 1 && "Invalid number of operands!");
1313 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1316 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1317 assert(N == 1 && "Invalid number of operands!");
1318 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1321 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1322 assert(N == 1 && "Invalid number of operands!");
1323 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1326 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1327 assert(N == 1 && "Invalid number of operands!");
1328 Inst.addOperand(MCOperand::CreateReg(getReg()));
1331 void addRegOperands(MCInst &Inst, unsigned N) const {
1332 assert(N == 1 && "Invalid number of operands!");
1333 Inst.addOperand(MCOperand::CreateReg(getReg()));
1336 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1337 assert(N == 3 && "Invalid number of operands!");
1338 assert(isRegShiftedReg() &&
1339 "addRegShiftedRegOperands() on non RegShiftedReg!");
1340 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1341 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1342 Inst.addOperand(MCOperand::CreateImm(
1343 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1346 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1347 assert(N == 2 && "Invalid number of operands!");
1348 assert(isRegShiftedImm() &&
1349 "addRegShiftedImmOperands() on non RegShiftedImm!");
1350 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1351 Inst.addOperand(MCOperand::CreateImm(
1352 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
1355 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1356 assert(N == 1 && "Invalid number of operands!");
1357 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1361 void addRegListOperands(MCInst &Inst, unsigned N) const {
1362 assert(N == 1 && "Invalid number of operands!");
1363 const SmallVectorImpl<unsigned> &RegList = getRegList();
1364 for (SmallVectorImpl<unsigned>::const_iterator
1365 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1366 Inst.addOperand(MCOperand::CreateReg(*I));
1369 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1370 addRegListOperands(Inst, N);
1373 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1374 addRegListOperands(Inst, N);
1377 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1378 assert(N == 1 && "Invalid number of operands!");
1379 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1380 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1383 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1384 assert(N == 1 && "Invalid number of operands!");
1385 // Munge the lsb/width into a bitfield mask.
1386 unsigned lsb = Bitfield.LSB;
1387 unsigned width = Bitfield.Width;
1388 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1389 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1390 (32 - (lsb + width)));
1391 Inst.addOperand(MCOperand::CreateImm(Mask));
1394 void addImmOperands(MCInst &Inst, unsigned N) const {
1395 assert(N == 1 && "Invalid number of operands!");
1396 addExpr(Inst, getImm());
1399 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1400 assert(N == 1 && "Invalid number of operands!");
1401 Inst.addOperand(MCOperand::CreateImm(getFPImm()));
1404 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1405 assert(N == 1 && "Invalid number of operands!");
1406 // FIXME: We really want to scale the value here, but the LDRD/STRD
1407 // instruction don't encode operands that way yet.
1408 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1409 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1412 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1413 assert(N == 1 && "Invalid number of operands!");
1414 // The immediate is scaled by four in the encoding and is stored
1415 // in the MCInst as such. Lop off the low two bits here.
1416 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1417 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1420 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1421 assert(N == 1 && "Invalid number of operands!");
1422 // The immediate is scaled by four in the encoding and is stored
1423 // in the MCInst as such. Lop off the low two bits here.
1424 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1425 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1428 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1429 assert(N == 1 && "Invalid number of operands!");
1430 // The constant encodes as the immediate-1, and we store in the instruction
1431 // the bits as encoded, so subtract off one here.
1432 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1433 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1436 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1437 assert(N == 1 && "Invalid number of operands!");
1438 // The constant encodes as the immediate-1, and we store in the instruction
1439 // the bits as encoded, so subtract off one here.
1440 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1441 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1444 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1445 assert(N == 1 && "Invalid number of operands!");
1446 // The constant encodes as the immediate, except for 32, which encodes as
1448 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1449 unsigned Imm = CE->getValue();
1450 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1453 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1454 assert(N == 1 && "Invalid number of operands!");
1455 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1456 // the instruction as well.
1457 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1458 int Val = CE->getValue();
1459 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1462 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1463 assert(N == 1 && "Invalid number of operands!");
1464 // The operand is actually a t2_so_imm, but we have its bitwise
1465 // negation in the assembly source, so twiddle it here.
1466 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1467 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1470 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1471 assert(N == 1 && "Invalid number of operands!");
1472 // The operand is actually a t2_so_imm, but we have its
1473 // negation in the assembly source, so twiddle it here.
1474 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1475 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1478 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1479 assert(N == 1 && "Invalid number of operands!");
1480 // The operand is actually a so_imm, but we have its bitwise
1481 // negation in the assembly source, so twiddle it here.
1482 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1483 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1486 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1487 assert(N == 1 && "Invalid number of operands!");
1488 // The operand is actually a so_imm, but we have its
1489 // negation in the assembly source, so twiddle it here.
1490 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1491 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1494 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1495 assert(N == 1 && "Invalid number of operands!");
1496 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1499 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1500 assert(N == 1 && "Invalid number of operands!");
1501 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1504 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1505 assert(N == 2 && "Invalid number of operands!");
1506 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1507 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1510 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1511 assert(N == 3 && "Invalid number of operands!");
1512 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1513 if (!Memory.OffsetRegNum) {
1514 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1515 // Special case for #-0
1516 if (Val == INT32_MIN) Val = 0;
1517 if (Val < 0) Val = -Val;
1518 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1520 // For register offset, we encode the shift type and negation flag
1522 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1523 Memory.ShiftImm, Memory.ShiftType);
1525 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1526 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1527 Inst.addOperand(MCOperand::CreateImm(Val));
1530 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1531 assert(N == 2 && "Invalid number of operands!");
1532 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1533 assert(CE && "non-constant AM2OffsetImm operand!");
1534 int32_t Val = CE->getValue();
1535 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1536 // Special case for #-0
1537 if (Val == INT32_MIN) Val = 0;
1538 if (Val < 0) Val = -Val;
1539 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1540 Inst.addOperand(MCOperand::CreateReg(0));
1541 Inst.addOperand(MCOperand::CreateImm(Val));
1544 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1545 assert(N == 3 && "Invalid number of operands!");
1546 // If we have an immediate that's not a constant, treat it as a label
1547 // reference needing a fixup. If it is a constant, it's something else
1548 // and we reject it.
1550 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1551 Inst.addOperand(MCOperand::CreateReg(0));
1552 Inst.addOperand(MCOperand::CreateImm(0));
1556 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1557 if (!Memory.OffsetRegNum) {
1558 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1559 // Special case for #-0
1560 if (Val == INT32_MIN) Val = 0;
1561 if (Val < 0) Val = -Val;
1562 Val = ARM_AM::getAM3Opc(AddSub, Val);
1564 // For register offset, we encode the shift type and negation flag
1566 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1568 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1569 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1570 Inst.addOperand(MCOperand::CreateImm(Val));
1573 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1574 assert(N == 2 && "Invalid number of operands!");
1575 if (Kind == k_PostIndexRegister) {
1577 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1578 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1579 Inst.addOperand(MCOperand::CreateImm(Val));
1584 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1585 int32_t Val = CE->getValue();
1586 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1587 // Special case for #-0
1588 if (Val == INT32_MIN) Val = 0;
1589 if (Val < 0) Val = -Val;
1590 Val = ARM_AM::getAM3Opc(AddSub, Val);
1591 Inst.addOperand(MCOperand::CreateReg(0));
1592 Inst.addOperand(MCOperand::CreateImm(Val));
1595 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1596 assert(N == 2 && "Invalid number of operands!");
1597 // If we have an immediate that's not a constant, treat it as a label
1598 // reference needing a fixup. If it is a constant, it's something else
1599 // and we reject it.
1601 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1602 Inst.addOperand(MCOperand::CreateImm(0));
1606 // The lower two bits are always zero and as such are not encoded.
1607 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1608 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1609 // Special case for #-0
1610 if (Val == INT32_MIN) Val = 0;
1611 if (Val < 0) Val = -Val;
1612 Val = ARM_AM::getAM5Opc(AddSub, Val);
1613 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1614 Inst.addOperand(MCOperand::CreateImm(Val));
1617 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1618 assert(N == 2 && "Invalid number of operands!");
1619 // If we have an immediate that's not a constant, treat it as a label
1620 // reference needing a fixup. If it is a constant, it's something else
1621 // and we reject it.
1623 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1624 Inst.addOperand(MCOperand::CreateImm(0));
1628 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1629 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1630 Inst.addOperand(MCOperand::CreateImm(Val));
1633 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1634 assert(N == 2 && "Invalid number of operands!");
1635 // The lower two bits are always zero and as such are not encoded.
1636 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1637 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1638 Inst.addOperand(MCOperand::CreateImm(Val));
1641 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1642 assert(N == 2 && "Invalid number of operands!");
1643 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1644 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1645 Inst.addOperand(MCOperand::CreateImm(Val));
1648 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1649 addMemImm8OffsetOperands(Inst, N);
1652 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1653 addMemImm8OffsetOperands(Inst, N);
1656 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1657 assert(N == 2 && "Invalid number of operands!");
1658 // If this is an immediate, it's a label reference.
1659 if (Kind == k_Immediate) {
1660 addExpr(Inst, getImm());
1661 Inst.addOperand(MCOperand::CreateImm(0));
1665 // Otherwise, it's a normal memory reg+offset.
1666 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1667 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1668 Inst.addOperand(MCOperand::CreateImm(Val));
1671 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1672 assert(N == 2 && "Invalid number of operands!");
1673 // If this is an immediate, it's a label reference.
1674 if (Kind == k_Immediate) {
1675 addExpr(Inst, getImm());
1676 Inst.addOperand(MCOperand::CreateImm(0));
1680 // Otherwise, it's a normal memory reg+offset.
1681 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1682 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1683 Inst.addOperand(MCOperand::CreateImm(Val));
1686 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1687 assert(N == 2 && "Invalid number of operands!");
1688 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1689 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1692 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
1693 assert(N == 2 && "Invalid number of operands!");
1694 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1695 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1698 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1699 assert(N == 3 && "Invalid number of operands!");
1701 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1702 Memory.ShiftImm, Memory.ShiftType);
1703 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1704 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1705 Inst.addOperand(MCOperand::CreateImm(Val));
1708 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1709 assert(N == 3 && "Invalid number of operands!");
1710 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1711 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1712 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
1715 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1716 assert(N == 2 && "Invalid number of operands!");
1717 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1718 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1721 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1722 assert(N == 2 && "Invalid number of operands!");
1723 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1724 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1725 Inst.addOperand(MCOperand::CreateImm(Val));
1728 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1729 assert(N == 2 && "Invalid number of operands!");
1730 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
1731 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1732 Inst.addOperand(MCOperand::CreateImm(Val));
1735 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1736 assert(N == 2 && "Invalid number of operands!");
1737 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
1738 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1739 Inst.addOperand(MCOperand::CreateImm(Val));
1742 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1743 assert(N == 2 && "Invalid number of operands!");
1744 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1745 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1746 Inst.addOperand(MCOperand::CreateImm(Val));
1749 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1750 assert(N == 1 && "Invalid number of operands!");
1751 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1752 assert(CE && "non-constant post-idx-imm8 operand!");
1753 int Imm = CE->getValue();
1754 bool isAdd = Imm >= 0;
1755 if (Imm == INT32_MIN) Imm = 0;
1756 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1757 Inst.addOperand(MCOperand::CreateImm(Imm));
1760 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
1761 assert(N == 1 && "Invalid number of operands!");
1762 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1763 assert(CE && "non-constant post-idx-imm8s4 operand!");
1764 int Imm = CE->getValue();
1765 bool isAdd = Imm >= 0;
1766 if (Imm == INT32_MIN) Imm = 0;
1767 // Immediate is scaled by 4.
1768 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
1769 Inst.addOperand(MCOperand::CreateImm(Imm));
1772 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1773 assert(N == 2 && "Invalid number of operands!");
1774 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1775 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1778 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1779 assert(N == 2 && "Invalid number of operands!");
1780 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1781 // The sign, shift type, and shift amount are encoded in a single operand
1782 // using the AM2 encoding helpers.
1783 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1784 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1785 PostIdxReg.ShiftTy);
1786 Inst.addOperand(MCOperand::CreateImm(Imm));
1789 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1790 assert(N == 1 && "Invalid number of operands!");
1791 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1794 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1795 assert(N == 1 && "Invalid number of operands!");
1796 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1799 void addVecListOperands(MCInst &Inst, unsigned N) const {
1800 assert(N == 1 && "Invalid number of operands!");
1801 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1804 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
1805 assert(N == 2 && "Invalid number of operands!");
1806 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1807 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
1810 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
1811 assert(N == 1 && "Invalid number of operands!");
1812 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1815 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
1816 assert(N == 1 && "Invalid number of operands!");
1817 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1820 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
1821 assert(N == 1 && "Invalid number of operands!");
1822 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1825 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
1826 assert(N == 1 && "Invalid number of operands!");
1827 // The immediate encodes the type of constant as well as the value.
1828 // Mask in that this is an i8 splat.
1829 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1830 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
1833 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
1834 assert(N == 1 && "Invalid number of operands!");
1835 // The immediate encodes the type of constant as well as the value.
1836 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1837 unsigned Value = CE->getValue();
1839 Value = (Value >> 8) | 0xa00;
1842 Inst.addOperand(MCOperand::CreateImm(Value));
1845 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
1846 assert(N == 1 && "Invalid number of operands!");
1847 // The immediate encodes the type of constant as well as the value.
1848 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1849 unsigned Value = CE->getValue();
1850 if (Value >= 256 && Value <= 0xff00)
1851 Value = (Value >> 8) | 0x200;
1852 else if (Value > 0xffff && Value <= 0xff0000)
1853 Value = (Value >> 16) | 0x400;
1854 else if (Value > 0xffffff)
1855 Value = (Value >> 24) | 0x600;
1856 Inst.addOperand(MCOperand::CreateImm(Value));
1859 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
1860 assert(N == 1 && "Invalid number of operands!");
1861 // The immediate encodes the type of constant as well as the value.
1862 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1863 unsigned Value = CE->getValue();
1864 if (Value >= 256 && Value <= 0xffff)
1865 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
1866 else if (Value > 0xffff && Value <= 0xffffff)
1867 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
1868 else if (Value > 0xffffff)
1869 Value = (Value >> 24) | 0x600;
1870 Inst.addOperand(MCOperand::CreateImm(Value));
1873 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
1874 assert(N == 1 && "Invalid number of operands!");
1875 // The immediate encodes the type of constant as well as the value.
1876 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1877 unsigned Value = ~CE->getValue();
1878 if (Value >= 256 && Value <= 0xffff)
1879 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
1880 else if (Value > 0xffff && Value <= 0xffffff)
1881 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
1882 else if (Value > 0xffffff)
1883 Value = (Value >> 24) | 0x600;
1884 Inst.addOperand(MCOperand::CreateImm(Value));
1887 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
1888 assert(N == 1 && "Invalid number of operands!");
1889 // The immediate encodes the type of constant as well as the value.
1890 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1891 uint64_t Value = CE->getValue();
1893 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
1894 Imm |= (Value & 1) << i;
1896 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
1899 virtual void print(raw_ostream &OS) const;
1901 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
1902 ARMOperand *Op = new ARMOperand(k_ITCondMask);
1903 Op->ITMask.Mask = Mask;
1909 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1910 ARMOperand *Op = new ARMOperand(k_CondCode);
1917 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1918 ARMOperand *Op = new ARMOperand(k_CoprocNum);
1919 Op->Cop.Val = CopVal;
1925 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1926 ARMOperand *Op = new ARMOperand(k_CoprocReg);
1927 Op->Cop.Val = CopVal;
1933 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
1934 ARMOperand *Op = new ARMOperand(k_CoprocOption);
1941 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1942 ARMOperand *Op = new ARMOperand(k_CCOut);
1943 Op->Reg.RegNum = RegNum;
1949 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1950 ARMOperand *Op = new ARMOperand(k_Token);
1951 Op->Tok.Data = Str.data();
1952 Op->Tok.Length = Str.size();
1958 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1959 ARMOperand *Op = new ARMOperand(k_Register);
1960 Op->Reg.RegNum = RegNum;
1966 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1971 ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
1972 Op->RegShiftedReg.ShiftTy = ShTy;
1973 Op->RegShiftedReg.SrcReg = SrcReg;
1974 Op->RegShiftedReg.ShiftReg = ShiftReg;
1975 Op->RegShiftedReg.ShiftImm = ShiftImm;
1981 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1985 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
1986 Op->RegShiftedImm.ShiftTy = ShTy;
1987 Op->RegShiftedImm.SrcReg = SrcReg;
1988 Op->RegShiftedImm.ShiftImm = ShiftImm;
1994 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1996 ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
1997 Op->ShifterImm.isASR = isASR;
1998 Op->ShifterImm.Imm = Imm;
2004 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2005 ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2006 Op->RotImm.Imm = Imm;
2012 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2014 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2015 Op->Bitfield.LSB = LSB;
2016 Op->Bitfield.Width = Width;
2023 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
2024 SMLoc StartLoc, SMLoc EndLoc) {
2025 KindTy Kind = k_RegisterList;
2027 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
2028 Kind = k_DPRRegisterList;
2029 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2030 contains(Regs.front().first))
2031 Kind = k_SPRRegisterList;
2033 ARMOperand *Op = new ARMOperand(Kind);
2034 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
2035 I = Regs.begin(), E = Regs.end(); I != E; ++I)
2036 Op->Registers.push_back(I->first);
2037 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
2038 Op->StartLoc = StartLoc;
2039 Op->EndLoc = EndLoc;
2043 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2044 bool isDoubleSpaced, SMLoc S, SMLoc E) {
2045 ARMOperand *Op = new ARMOperand(k_VectorList);
2046 Op->VectorList.RegNum = RegNum;
2047 Op->VectorList.Count = Count;
2048 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2054 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2055 bool isDoubleSpaced,
2057 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2058 Op->VectorList.RegNum = RegNum;
2059 Op->VectorList.Count = Count;
2060 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2066 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2068 bool isDoubleSpaced,
2070 ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2071 Op->VectorList.RegNum = RegNum;
2072 Op->VectorList.Count = Count;
2073 Op->VectorList.LaneIndex = Index;
2074 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2080 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2082 ARMOperand *Op = new ARMOperand(k_VectorIndex);
2083 Op->VectorIndex.Val = Idx;
2089 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2090 ARMOperand *Op = new ARMOperand(k_Immediate);
2097 static ARMOperand *CreateFPImm(unsigned Val, SMLoc S, MCContext &Ctx) {
2098 ARMOperand *Op = new ARMOperand(k_FPImmediate);
2099 Op->FPImm.Val = Val;
2105 static ARMOperand *CreateMem(unsigned BaseRegNum,
2106 const MCConstantExpr *OffsetImm,
2107 unsigned OffsetRegNum,
2108 ARM_AM::ShiftOpc ShiftType,
2113 ARMOperand *Op = new ARMOperand(k_Memory);
2114 Op->Memory.BaseRegNum = BaseRegNum;
2115 Op->Memory.OffsetImm = OffsetImm;
2116 Op->Memory.OffsetRegNum = OffsetRegNum;
2117 Op->Memory.ShiftType = ShiftType;
2118 Op->Memory.ShiftImm = ShiftImm;
2119 Op->Memory.Alignment = Alignment;
2120 Op->Memory.isNegative = isNegative;
2126 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2127 ARM_AM::ShiftOpc ShiftTy,
2130 ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2131 Op->PostIdxReg.RegNum = RegNum;
2132 Op->PostIdxReg.isAdd = isAdd;
2133 Op->PostIdxReg.ShiftTy = ShiftTy;
2134 Op->PostIdxReg.ShiftImm = ShiftImm;
2140 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2141 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2142 Op->MBOpt.Val = Opt;
2148 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2149 ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2150 Op->IFlags.Val = IFlags;
2156 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2157 ARMOperand *Op = new ARMOperand(k_MSRMask);
2158 Op->MMask.Val = MMask;
2165 } // end anonymous namespace.
2167 void ARMOperand::print(raw_ostream &OS) const {
2170 OS << "<fpimm " << getFPImm() << "(" << ARM_AM::getFPImmFloat(getFPImm())
2174 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2177 OS << "<ccout " << getReg() << ">";
2179 case k_ITCondMask: {
2180 static const char *MaskStr[] = {
2181 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2182 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2184 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2185 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2189 OS << "<coprocessor number: " << getCoproc() << ">";
2192 OS << "<coprocessor register: " << getCoproc() << ">";
2194 case k_CoprocOption:
2195 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2198 OS << "<mask: " << getMSRMask() << ">";
2201 getImm()->print(OS);
2203 case k_MemBarrierOpt:
2204 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
2208 << " base:" << Memory.BaseRegNum;
2211 case k_PostIndexRegister:
2212 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2213 << PostIdxReg.RegNum;
2214 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2215 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2216 << PostIdxReg.ShiftImm;
2219 case k_ProcIFlags: {
2220 OS << "<ARM_PROC::";
2221 unsigned IFlags = getProcIFlags();
2222 for (int i=2; i >= 0; --i)
2223 if (IFlags & (1 << i))
2224 OS << ARM_PROC::IFlagsToString(1 << i);
2229 OS << "<register " << getReg() << ">";
2231 case k_ShifterImmediate:
2232 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2233 << " #" << ShifterImm.Imm << ">";
2235 case k_ShiftedRegister:
2236 OS << "<so_reg_reg "
2237 << RegShiftedReg.SrcReg << " "
2238 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2239 << " " << RegShiftedReg.ShiftReg << ">";
2241 case k_ShiftedImmediate:
2242 OS << "<so_reg_imm "
2243 << RegShiftedImm.SrcReg << " "
2244 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2245 << " #" << RegShiftedImm.ShiftImm << ">";
2247 case k_RotateImmediate:
2248 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2250 case k_BitfieldDescriptor:
2251 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2252 << ", width: " << Bitfield.Width << ">";
2254 case k_RegisterList:
2255 case k_DPRRegisterList:
2256 case k_SPRRegisterList: {
2257 OS << "<register_list ";
2259 const SmallVectorImpl<unsigned> &RegList = getRegList();
2260 for (SmallVectorImpl<unsigned>::const_iterator
2261 I = RegList.begin(), E = RegList.end(); I != E; ) {
2263 if (++I < E) OS << ", ";
2270 OS << "<vector_list " << VectorList.Count << " * "
2271 << VectorList.RegNum << ">";
2273 case k_VectorListAllLanes:
2274 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2275 << VectorList.RegNum << ">";
2277 case k_VectorListIndexed:
2278 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2279 << VectorList.Count << " * " << VectorList.RegNum << ">";
2282 OS << "'" << getToken() << "'";
2285 OS << "<vectorindex " << getVectorIndex() << ">";
2290 /// @name Auto-generated Match Functions
2293 static unsigned MatchRegisterName(StringRef Name);
2297 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2298 SMLoc &StartLoc, SMLoc &EndLoc) {
2299 StartLoc = Parser.getTok().getLoc();
2300 RegNo = tryParseRegister();
2301 EndLoc = Parser.getTok().getLoc();
2303 return (RegNo == (unsigned)-1);
2306 /// Try to parse a register name. The token must be an Identifier when called,
2307 /// and if it is a register name the token is eaten and the register number is
2308 /// returned. Otherwise return -1.
2310 int ARMAsmParser::tryParseRegister() {
2311 const AsmToken &Tok = Parser.getTok();
2312 if (Tok.isNot(AsmToken::Identifier)) return -1;
2314 std::string lowerCase = Tok.getString().lower();
2315 unsigned RegNum = MatchRegisterName(lowerCase);
2317 RegNum = StringSwitch<unsigned>(lowerCase)
2318 .Case("r13", ARM::SP)
2319 .Case("r14", ARM::LR)
2320 .Case("r15", ARM::PC)
2321 .Case("ip", ARM::R12)
2322 // Additional register name aliases for 'gas' compatibility.
2323 .Case("a1", ARM::R0)
2324 .Case("a2", ARM::R1)
2325 .Case("a3", ARM::R2)
2326 .Case("a4", ARM::R3)
2327 .Case("v1", ARM::R4)
2328 .Case("v2", ARM::R5)
2329 .Case("v3", ARM::R6)
2330 .Case("v4", ARM::R7)
2331 .Case("v5", ARM::R8)
2332 .Case("v6", ARM::R9)
2333 .Case("v7", ARM::R10)
2334 .Case("v8", ARM::R11)
2335 .Case("sb", ARM::R9)
2336 .Case("sl", ARM::R10)
2337 .Case("fp", ARM::R11)
2341 // Check for aliases registered via .req. Canonicalize to lower case.
2342 // That's more consistent since register names are case insensitive, and
2343 // it's how the original entry was passed in from MC/MCParser/AsmParser.
2344 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2345 // If no match, return failure.
2346 if (Entry == RegisterReqs.end())
2348 Parser.Lex(); // Eat identifier token.
2349 return Entry->getValue();
2352 Parser.Lex(); // Eat identifier token.
2357 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
2358 // If a recoverable error occurs, return 1. If an irrecoverable error
2359 // occurs, return -1. An irrecoverable error is one where tokens have been
2360 // consumed in the process of trying to parse the shifter (i.e., when it is
2361 // indeed a shifter operand, but malformed).
2362 int ARMAsmParser::tryParseShiftRegister(
2363 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2364 SMLoc S = Parser.getTok().getLoc();
2365 const AsmToken &Tok = Parser.getTok();
2366 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2368 std::string lowerCase = Tok.getString().lower();
2369 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2370 .Case("asl", ARM_AM::lsl)
2371 .Case("lsl", ARM_AM::lsl)
2372 .Case("lsr", ARM_AM::lsr)
2373 .Case("asr", ARM_AM::asr)
2374 .Case("ror", ARM_AM::ror)
2375 .Case("rrx", ARM_AM::rrx)
2376 .Default(ARM_AM::no_shift);
2378 if (ShiftTy == ARM_AM::no_shift)
2381 Parser.Lex(); // Eat the operator.
2383 // The source register for the shift has already been added to the
2384 // operand list, so we need to pop it off and combine it into the shifted
2385 // register operand instead.
2386 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2387 if (!PrevOp->isReg())
2388 return Error(PrevOp->getStartLoc(), "shift must be of a register");
2389 int SrcReg = PrevOp->getReg();
2392 if (ShiftTy == ARM_AM::rrx) {
2393 // RRX Doesn't have an explicit shift amount. The encoder expects
2394 // the shift register to be the same as the source register. Seems odd,
2398 // Figure out if this is shifted by a constant or a register (for non-RRX).
2399 if (Parser.getTok().is(AsmToken::Hash) ||
2400 Parser.getTok().is(AsmToken::Dollar)) {
2401 Parser.Lex(); // Eat hash.
2402 SMLoc ImmLoc = Parser.getTok().getLoc();
2403 const MCExpr *ShiftExpr = 0;
2404 if (getParser().ParseExpression(ShiftExpr)) {
2405 Error(ImmLoc, "invalid immediate shift value");
2408 // The expression must be evaluatable as an immediate.
2409 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2411 Error(ImmLoc, "invalid immediate shift value");
2414 // Range check the immediate.
2415 // lsl, ror: 0 <= imm <= 31
2416 // lsr, asr: 0 <= imm <= 32
2417 Imm = CE->getValue();
2419 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2420 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2421 Error(ImmLoc, "immediate shift value out of range");
2424 // shift by zero is a nop. Always send it through as lsl.
2425 // ('as' compatibility)
2427 ShiftTy = ARM_AM::lsl;
2428 } else if (Parser.getTok().is(AsmToken::Identifier)) {
2429 ShiftReg = tryParseRegister();
2430 SMLoc L = Parser.getTok().getLoc();
2431 if (ShiftReg == -1) {
2432 Error (L, "expected immediate or register in shift operand");
2436 Error (Parser.getTok().getLoc(),
2437 "expected immediate or register in shift operand");
2442 if (ShiftReg && ShiftTy != ARM_AM::rrx)
2443 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2445 S, Parser.getTok().getLoc()));
2447 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2448 S, Parser.getTok().getLoc()));
2454 /// Try to parse a register name. The token must be an Identifier when called.
2455 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
2456 /// if there is a "writeback". 'true' if it's not a register.
2458 /// TODO this is likely to change to allow different register types and or to
2459 /// parse for a specific register type.
2461 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2462 SMLoc S = Parser.getTok().getLoc();
2463 int RegNo = tryParseRegister();
2467 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
2469 const AsmToken &ExclaimTok = Parser.getTok();
2470 if (ExclaimTok.is(AsmToken::Exclaim)) {
2471 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2472 ExclaimTok.getLoc()));
2473 Parser.Lex(); // Eat exclaim token
2477 // Also check for an index operand. This is only legal for vector registers,
2478 // but that'll get caught OK in operand matching, so we don't need to
2479 // explicitly filter everything else out here.
2480 if (Parser.getTok().is(AsmToken::LBrac)) {
2481 SMLoc SIdx = Parser.getTok().getLoc();
2482 Parser.Lex(); // Eat left bracket token.
2484 const MCExpr *ImmVal;
2485 if (getParser().ParseExpression(ImmVal))
2486 return MatchOperand_ParseFail;
2487 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2489 TokError("immediate value expected for vector index");
2490 return MatchOperand_ParseFail;
2493 SMLoc E = Parser.getTok().getLoc();
2494 if (Parser.getTok().isNot(AsmToken::RBrac)) {
2495 Error(E, "']' expected");
2496 return MatchOperand_ParseFail;
2499 Parser.Lex(); // Eat right bracket token.
2501 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2509 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
2510 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2512 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2513 // Use the same layout as the tablegen'erated register name matcher. Ugly,
2515 switch (Name.size()) {
2518 if (Name[0] != CoprocOp)
2535 if (Name[0] != CoprocOp || Name[1] != '1')
2539 case '0': return 10;
2540 case '1': return 11;
2541 case '2': return 12;
2542 case '3': return 13;
2543 case '4': return 14;
2544 case '5': return 15;
2552 /// parseITCondCode - Try to parse a condition code for an IT instruction.
2553 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2554 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2555 SMLoc S = Parser.getTok().getLoc();
2556 const AsmToken &Tok = Parser.getTok();
2557 if (!Tok.is(AsmToken::Identifier))
2558 return MatchOperand_NoMatch;
2559 unsigned CC = StringSwitch<unsigned>(Tok.getString())
2560 .Case("eq", ARMCC::EQ)
2561 .Case("ne", ARMCC::NE)
2562 .Case("hs", ARMCC::HS)
2563 .Case("cs", ARMCC::HS)
2564 .Case("lo", ARMCC::LO)
2565 .Case("cc", ARMCC::LO)
2566 .Case("mi", ARMCC::MI)
2567 .Case("pl", ARMCC::PL)
2568 .Case("vs", ARMCC::VS)
2569 .Case("vc", ARMCC::VC)
2570 .Case("hi", ARMCC::HI)
2571 .Case("ls", ARMCC::LS)
2572 .Case("ge", ARMCC::GE)
2573 .Case("lt", ARMCC::LT)
2574 .Case("gt", ARMCC::GT)
2575 .Case("le", ARMCC::LE)
2576 .Case("al", ARMCC::AL)
2579 return MatchOperand_NoMatch;
2580 Parser.Lex(); // Eat the token.
2582 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2584 return MatchOperand_Success;
2587 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2588 /// token must be an Identifier when called, and if it is a coprocessor
2589 /// number, the token is eaten and the operand is added to the operand list.
2590 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2591 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2592 SMLoc S = Parser.getTok().getLoc();
2593 const AsmToken &Tok = Parser.getTok();
2594 if (Tok.isNot(AsmToken::Identifier))
2595 return MatchOperand_NoMatch;
2597 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2599 return MatchOperand_NoMatch;
2601 Parser.Lex(); // Eat identifier token.
2602 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2603 return MatchOperand_Success;
2606 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2607 /// token must be an Identifier when called, and if it is a coprocessor
2608 /// number, the token is eaten and the operand is added to the operand list.
2609 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2610 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2611 SMLoc S = Parser.getTok().getLoc();
2612 const AsmToken &Tok = Parser.getTok();
2613 if (Tok.isNot(AsmToken::Identifier))
2614 return MatchOperand_NoMatch;
2616 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2618 return MatchOperand_NoMatch;
2620 Parser.Lex(); // Eat identifier token.
2621 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2622 return MatchOperand_Success;
2625 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2626 /// coproc_option : '{' imm0_255 '}'
2627 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2628 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2629 SMLoc S = Parser.getTok().getLoc();
2631 // If this isn't a '{', this isn't a coprocessor immediate operand.
2632 if (Parser.getTok().isNot(AsmToken::LCurly))
2633 return MatchOperand_NoMatch;
2634 Parser.Lex(); // Eat the '{'
2637 SMLoc Loc = Parser.getTok().getLoc();
2638 if (getParser().ParseExpression(Expr)) {
2639 Error(Loc, "illegal expression");
2640 return MatchOperand_ParseFail;
2642 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2643 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2644 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2645 return MatchOperand_ParseFail;
2647 int Val = CE->getValue();
2649 // Check for and consume the closing '}'
2650 if (Parser.getTok().isNot(AsmToken::RCurly))
2651 return MatchOperand_ParseFail;
2652 SMLoc E = Parser.getTok().getLoc();
2653 Parser.Lex(); // Eat the '}'
2655 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2656 return MatchOperand_Success;
2659 // For register list parsing, we need to map from raw GPR register numbering
2660 // to the enumeration values. The enumeration values aren't sorted by
2661 // register number due to our using "sp", "lr" and "pc" as canonical names.
2662 static unsigned getNextRegister(unsigned Reg) {
2663 // If this is a GPR, we need to do it manually, otherwise we can rely
2664 // on the sort ordering of the enumeration since the other reg-classes
2666 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2669 default: assert(0 && "Invalid GPR number!");
2670 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
2671 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
2672 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
2673 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
2674 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
2675 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2676 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
2677 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
2681 // Return the low-subreg of a given Q register.
2682 static unsigned getDRegFromQReg(unsigned QReg) {
2684 default: llvm_unreachable("expected a Q register!");
2685 case ARM::Q0: return ARM::D0;
2686 case ARM::Q1: return ARM::D2;
2687 case ARM::Q2: return ARM::D4;
2688 case ARM::Q3: return ARM::D6;
2689 case ARM::Q4: return ARM::D8;
2690 case ARM::Q5: return ARM::D10;
2691 case ARM::Q6: return ARM::D12;
2692 case ARM::Q7: return ARM::D14;
2693 case ARM::Q8: return ARM::D16;
2694 case ARM::Q9: return ARM::D18;
2695 case ARM::Q10: return ARM::D20;
2696 case ARM::Q11: return ARM::D22;
2697 case ARM::Q12: return ARM::D24;
2698 case ARM::Q13: return ARM::D26;
2699 case ARM::Q14: return ARM::D28;
2700 case ARM::Q15: return ARM::D30;
2704 /// Parse a register list.
2706 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2707 assert(Parser.getTok().is(AsmToken::LCurly) &&
2708 "Token is not a Left Curly Brace");
2709 SMLoc S = Parser.getTok().getLoc();
2710 Parser.Lex(); // Eat '{' token.
2711 SMLoc RegLoc = Parser.getTok().getLoc();
2713 // Check the first register in the list to see what register class
2714 // this is a list of.
2715 int Reg = tryParseRegister();
2717 return Error(RegLoc, "register expected");
2719 // The reglist instructions have at most 16 registers, so reserve
2720 // space for that many.
2721 SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
2723 // Allow Q regs and just interpret them as the two D sub-registers.
2724 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2725 Reg = getDRegFromQReg(Reg);
2726 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2729 const MCRegisterClass *RC;
2730 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2731 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
2732 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
2733 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
2734 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
2735 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
2737 return Error(RegLoc, "invalid register in register list");
2739 // Store the register.
2740 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2742 // This starts immediately after the first register token in the list,
2743 // so we can see either a comma or a minus (range separator) as a legal
2745 while (Parser.getTok().is(AsmToken::Comma) ||
2746 Parser.getTok().is(AsmToken::Minus)) {
2747 if (Parser.getTok().is(AsmToken::Minus)) {
2748 Parser.Lex(); // Eat the minus.
2749 SMLoc EndLoc = Parser.getTok().getLoc();
2750 int EndReg = tryParseRegister();
2752 return Error(EndLoc, "register expected");
2753 // Allow Q regs and just interpret them as the two D sub-registers.
2754 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
2755 EndReg = getDRegFromQReg(EndReg) + 1;
2756 // If the register is the same as the start reg, there's nothing
2760 // The register must be in the same register class as the first.
2761 if (!RC->contains(EndReg))
2762 return Error(EndLoc, "invalid register in register list");
2763 // Ranges must go from low to high.
2764 if (getARMRegisterNumbering(Reg) > getARMRegisterNumbering(EndReg))
2765 return Error(EndLoc, "bad range in register list");
2767 // Add all the registers in the range to the register list.
2768 while (Reg != EndReg) {
2769 Reg = getNextRegister(Reg);
2770 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2774 Parser.Lex(); // Eat the comma.
2775 RegLoc = Parser.getTok().getLoc();
2777 const AsmToken RegTok = Parser.getTok();
2778 Reg = tryParseRegister();
2780 return Error(RegLoc, "register expected");
2781 // Allow Q regs and just interpret them as the two D sub-registers.
2782 bool isQReg = false;
2783 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2784 Reg = getDRegFromQReg(Reg);
2787 // The register must be in the same register class as the first.
2788 if (!RC->contains(Reg))
2789 return Error(RegLoc, "invalid register in register list");
2790 // List must be monotonically increasing.
2791 if (getARMRegisterNumbering(Reg) < getARMRegisterNumbering(OldReg))
2792 return Error(RegLoc, "register list not in ascending order");
2793 if (getARMRegisterNumbering(Reg) == getARMRegisterNumbering(OldReg)) {
2794 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
2795 ") in register list");
2798 // VFP register lists must also be contiguous.
2799 // It's OK to use the enumeration values directly here rather, as the
2800 // VFP register classes have the enum sorted properly.
2801 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
2803 return Error(RegLoc, "non-contiguous register range");
2804 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2806 Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc));
2809 SMLoc E = Parser.getTok().getLoc();
2810 if (Parser.getTok().isNot(AsmToken::RCurly))
2811 return Error(E, "'}' expected");
2812 Parser.Lex(); // Eat '}' token.
2814 // Push the register list operand.
2815 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
2817 // The ARM system instruction variants for LDM/STM have a '^' token here.
2818 if (Parser.getTok().is(AsmToken::Caret)) {
2819 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
2820 Parser.Lex(); // Eat '^' token.
2826 // Helper function to parse the lane index for vector lists.
2827 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2828 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index) {
2829 Index = 0; // Always return a defined index value.
2830 if (Parser.getTok().is(AsmToken::LBrac)) {
2831 Parser.Lex(); // Eat the '['.
2832 if (Parser.getTok().is(AsmToken::RBrac)) {
2833 // "Dn[]" is the 'all lanes' syntax.
2834 LaneKind = AllLanes;
2835 Parser.Lex(); // Eat the ']'.
2836 return MatchOperand_Success;
2838 const MCExpr *LaneIndex;
2839 SMLoc Loc = Parser.getTok().getLoc();
2840 if (getParser().ParseExpression(LaneIndex)) {
2841 Error(Loc, "illegal expression");
2842 return MatchOperand_ParseFail;
2844 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
2846 Error(Loc, "lane index must be empty or an integer");
2847 return MatchOperand_ParseFail;
2849 if (Parser.getTok().isNot(AsmToken::RBrac)) {
2850 Error(Parser.getTok().getLoc(), "']' expected");
2851 return MatchOperand_ParseFail;
2853 Parser.Lex(); // Eat the ']'.
2854 int64_t Val = CE->getValue();
2856 // FIXME: Make this range check context sensitive for .8, .16, .32.
2857 if (Val < 0 || Val > 7) {
2858 Error(Parser.getTok().getLoc(), "lane index out of range");
2859 return MatchOperand_ParseFail;
2862 LaneKind = IndexedLane;
2863 return MatchOperand_Success;
2866 return MatchOperand_Success;
2869 // parse a vector register list
2870 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2871 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2872 VectorLaneTy LaneKind;
2874 SMLoc S = Parser.getTok().getLoc();
2875 // As an extension (to match gas), support a plain D register or Q register
2876 // (without encosing curly braces) as a single or double entry list,
2878 if (Parser.getTok().is(AsmToken::Identifier)) {
2879 int Reg = tryParseRegister();
2881 return MatchOperand_NoMatch;
2882 SMLoc E = Parser.getTok().getLoc();
2883 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
2884 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex);
2885 if (Res != MatchOperand_Success)
2889 assert(0 && "unexpected lane kind!");
2891 E = Parser.getTok().getLoc();
2892 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
2895 E = Parser.getTok().getLoc();
2896 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
2900 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
2905 return MatchOperand_Success;
2907 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2908 Reg = getDRegFromQReg(Reg);
2909 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex);
2910 if (Res != MatchOperand_Success)
2914 assert(0 && "unexpected lane kind!");
2916 E = Parser.getTok().getLoc();
2917 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
2920 E = Parser.getTok().getLoc();
2921 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
2925 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
2930 return MatchOperand_Success;
2932 Error(S, "vector register expected");
2933 return MatchOperand_ParseFail;
2936 if (Parser.getTok().isNot(AsmToken::LCurly))
2937 return MatchOperand_NoMatch;
2939 Parser.Lex(); // Eat '{' token.
2940 SMLoc RegLoc = Parser.getTok().getLoc();
2942 int Reg = tryParseRegister();
2944 Error(RegLoc, "register expected");
2945 return MatchOperand_ParseFail;
2949 unsigned FirstReg = Reg;
2950 // The list is of D registers, but we also allow Q regs and just interpret
2951 // them as the two D sub-registers.
2952 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2953 FirstReg = Reg = getDRegFromQReg(Reg);
2954 Spacing = 1; // double-spacing requires explicit D registers, otherwise
2955 // it's ambiguous with four-register single spaced.
2959 if (parseVectorLane(LaneKind, LaneIndex) != MatchOperand_Success)
2960 return MatchOperand_ParseFail;
2962 while (Parser.getTok().is(AsmToken::Comma) ||
2963 Parser.getTok().is(AsmToken::Minus)) {
2964 if (Parser.getTok().is(AsmToken::Minus)) {
2966 Spacing = 1; // Register range implies a single spaced list.
2967 else if (Spacing == 2) {
2968 Error(Parser.getTok().getLoc(),
2969 "sequential registers in double spaced list");
2970 return MatchOperand_ParseFail;
2972 Parser.Lex(); // Eat the minus.
2973 SMLoc EndLoc = Parser.getTok().getLoc();
2974 int EndReg = tryParseRegister();
2976 Error(EndLoc, "register expected");
2977 return MatchOperand_ParseFail;
2979 // Allow Q regs and just interpret them as the two D sub-registers.
2980 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
2981 EndReg = getDRegFromQReg(EndReg) + 1;
2982 // If the register is the same as the start reg, there's nothing
2986 // The register must be in the same register class as the first.
2987 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
2988 Error(EndLoc, "invalid register in register list");
2989 return MatchOperand_ParseFail;
2991 // Ranges must go from low to high.
2993 Error(EndLoc, "bad range in register list");
2994 return MatchOperand_ParseFail;
2996 // Parse the lane specifier if present.
2997 VectorLaneTy NextLaneKind;
2998 unsigned NextLaneIndex;
2999 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
3000 return MatchOperand_ParseFail;
3001 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3002 Error(EndLoc, "mismatched lane index in register list");
3003 return MatchOperand_ParseFail;
3005 EndLoc = Parser.getTok().getLoc();
3007 // Add all the registers in the range to the register list.
3008 Count += EndReg - Reg;
3012 Parser.Lex(); // Eat the comma.
3013 RegLoc = Parser.getTok().getLoc();
3015 Reg = tryParseRegister();
3017 Error(RegLoc, "register expected");
3018 return MatchOperand_ParseFail;
3020 // vector register lists must be contiguous.
3021 // It's OK to use the enumeration values directly here rather, as the
3022 // VFP register classes have the enum sorted properly.
3024 // The list is of D registers, but we also allow Q regs and just interpret
3025 // them as the two D sub-registers.
3026 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3028 Spacing = 1; // Register range implies a single spaced list.
3029 else if (Spacing == 2) {
3031 "invalid register in double-spaced list (must be 'D' register')");
3032 return MatchOperand_ParseFail;
3034 Reg = getDRegFromQReg(Reg);
3035 if (Reg != OldReg + 1) {
3036 Error(RegLoc, "non-contiguous register range");
3037 return MatchOperand_ParseFail;
3041 // Parse the lane specifier if present.
3042 VectorLaneTy NextLaneKind;
3043 unsigned NextLaneIndex;
3044 SMLoc EndLoc = Parser.getTok().getLoc();
3045 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
3046 return MatchOperand_ParseFail;
3047 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3048 Error(EndLoc, "mismatched lane index in register list");
3049 return MatchOperand_ParseFail;
3053 // Normal D register.
3054 // Figure out the register spacing (single or double) of the list if
3055 // we don't know it already.
3057 Spacing = 1 + (Reg == OldReg + 2);
3059 // Just check that it's contiguous and keep going.
3060 if (Reg != OldReg + Spacing) {
3061 Error(RegLoc, "non-contiguous register range");
3062 return MatchOperand_ParseFail;
3065 // Parse the lane specifier if present.
3066 VectorLaneTy NextLaneKind;
3067 unsigned NextLaneIndex;
3068 SMLoc EndLoc = Parser.getTok().getLoc();
3069 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
3070 return MatchOperand_ParseFail;
3071 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3072 Error(EndLoc, "mismatched lane index in register list");
3073 return MatchOperand_ParseFail;
3077 SMLoc E = Parser.getTok().getLoc();
3078 if (Parser.getTok().isNot(AsmToken::RCurly)) {
3079 Error(E, "'}' expected");
3080 return MatchOperand_ParseFail;
3082 Parser.Lex(); // Eat '}' token.
3086 assert(0 && "unexpected lane kind in register list.");
3088 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3089 (Spacing == 2), S, E));
3092 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3097 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3103 return MatchOperand_Success;
3106 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3107 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3108 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3109 SMLoc S = Parser.getTok().getLoc();
3110 const AsmToken &Tok = Parser.getTok();
3111 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
3112 StringRef OptStr = Tok.getString();
3114 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
3115 .Case("sy", ARM_MB::SY)
3116 .Case("st", ARM_MB::ST)
3117 .Case("sh", ARM_MB::ISH)
3118 .Case("ish", ARM_MB::ISH)
3119 .Case("shst", ARM_MB::ISHST)
3120 .Case("ishst", ARM_MB::ISHST)
3121 .Case("nsh", ARM_MB::NSH)
3122 .Case("un", ARM_MB::NSH)
3123 .Case("nshst", ARM_MB::NSHST)
3124 .Case("unst", ARM_MB::NSHST)
3125 .Case("osh", ARM_MB::OSH)
3126 .Case("oshst", ARM_MB::OSHST)
3130 return MatchOperand_NoMatch;
3132 Parser.Lex(); // Eat identifier token.
3133 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3134 return MatchOperand_Success;
3137 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3138 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3139 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3140 SMLoc S = Parser.getTok().getLoc();
3141 const AsmToken &Tok = Parser.getTok();
3142 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
3143 StringRef IFlagsStr = Tok.getString();
3145 // An iflags string of "none" is interpreted to mean that none of the AIF
3146 // bits are set. Not a terribly useful instruction, but a valid encoding.
3147 unsigned IFlags = 0;
3148 if (IFlagsStr != "none") {
3149 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3150 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3151 .Case("a", ARM_PROC::A)
3152 .Case("i", ARM_PROC::I)
3153 .Case("f", ARM_PROC::F)
3156 // If some specific iflag is already set, it means that some letter is
3157 // present more than once, this is not acceptable.
3158 if (Flag == ~0U || (IFlags & Flag))
3159 return MatchOperand_NoMatch;
3165 Parser.Lex(); // Eat identifier token.
3166 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3167 return MatchOperand_Success;
3170 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3171 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3172 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3173 SMLoc S = Parser.getTok().getLoc();
3174 const AsmToken &Tok = Parser.getTok();
3175 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
3176 StringRef Mask = Tok.getString();
3179 // See ARMv6-M 10.1.1
3180 unsigned FlagsVal = StringSwitch<unsigned>(Mask)
3190 .Case("primask", 16)
3191 .Case("basepri", 17)
3192 .Case("basepri_max", 18)
3193 .Case("faultmask", 19)
3194 .Case("control", 20)
3197 if (FlagsVal == ~0U)
3198 return MatchOperand_NoMatch;
3200 if (!hasV7Ops() && FlagsVal >= 17 && FlagsVal <= 19)
3201 // basepri, basepri_max and faultmask only valid for V7m.
3202 return MatchOperand_NoMatch;
3204 Parser.Lex(); // Eat identifier token.
3205 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3206 return MatchOperand_Success;
3209 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3210 size_t Start = 0, Next = Mask.find('_');
3211 StringRef Flags = "";
3212 std::string SpecReg = Mask.slice(Start, Next).lower();
3213 if (Next != StringRef::npos)
3214 Flags = Mask.slice(Next+1, Mask.size());
3216 // FlagsVal contains the complete mask:
3218 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3219 unsigned FlagsVal = 0;
3221 if (SpecReg == "apsr") {
3222 FlagsVal = StringSwitch<unsigned>(Flags)
3223 .Case("nzcvq", 0x8) // same as CPSR_f
3224 .Case("g", 0x4) // same as CPSR_s
3225 .Case("nzcvqg", 0xc) // same as CPSR_fs
3228 if (FlagsVal == ~0U) {
3230 return MatchOperand_NoMatch;
3232 FlagsVal = 8; // No flag
3234 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3235 if (Flags == "all") // cpsr_all is an alias for cpsr_fc
3237 for (int i = 0, e = Flags.size(); i != e; ++i) {
3238 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3245 // If some specific flag is already set, it means that some letter is
3246 // present more than once, this is not acceptable.
3247 if (FlagsVal == ~0U || (FlagsVal & Flag))
3248 return MatchOperand_NoMatch;
3251 } else // No match for special register.
3252 return MatchOperand_NoMatch;
3254 // Special register without flags is NOT equivalent to "fc" flags.
3255 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
3256 // two lines would enable gas compatibility at the expense of breaking
3262 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3263 if (SpecReg == "spsr")
3266 Parser.Lex(); // Eat identifier token.
3267 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3268 return MatchOperand_Success;
3271 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3272 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3273 int Low, int High) {
3274 const AsmToken &Tok = Parser.getTok();
3275 if (Tok.isNot(AsmToken::Identifier)) {
3276 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3277 return MatchOperand_ParseFail;
3279 StringRef ShiftName = Tok.getString();
3280 std::string LowerOp = Op.lower();
3281 std::string UpperOp = Op.upper();
3282 if (ShiftName != LowerOp && ShiftName != UpperOp) {
3283 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3284 return MatchOperand_ParseFail;
3286 Parser.Lex(); // Eat shift type token.
3288 // There must be a '#' and a shift amount.
3289 if (Parser.getTok().isNot(AsmToken::Hash) &&
3290 Parser.getTok().isNot(AsmToken::Dollar)) {
3291 Error(Parser.getTok().getLoc(), "'#' expected");
3292 return MatchOperand_ParseFail;
3294 Parser.Lex(); // Eat hash token.
3296 const MCExpr *ShiftAmount;
3297 SMLoc Loc = Parser.getTok().getLoc();
3298 if (getParser().ParseExpression(ShiftAmount)) {
3299 Error(Loc, "illegal expression");
3300 return MatchOperand_ParseFail;
3302 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3304 Error(Loc, "constant expression expected");
3305 return MatchOperand_ParseFail;
3307 int Val = CE->getValue();
3308 if (Val < Low || Val > High) {
3309 Error(Loc, "immediate value out of range");
3310 return MatchOperand_ParseFail;
3313 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
3315 return MatchOperand_Success;
3318 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3319 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3320 const AsmToken &Tok = Parser.getTok();
3321 SMLoc S = Tok.getLoc();
3322 if (Tok.isNot(AsmToken::Identifier)) {
3323 Error(Tok.getLoc(), "'be' or 'le' operand expected");
3324 return MatchOperand_ParseFail;
3326 int Val = StringSwitch<int>(Tok.getString())
3330 Parser.Lex(); // Eat the token.
3333 Error(Tok.getLoc(), "'be' or 'le' operand expected");
3334 return MatchOperand_ParseFail;
3336 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3338 S, Parser.getTok().getLoc()));
3339 return MatchOperand_Success;
3342 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3343 /// instructions. Legal values are:
3344 /// lsl #n 'n' in [0,31]
3345 /// asr #n 'n' in [1,32]
3346 /// n == 32 encoded as n == 0.
3347 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3348 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3349 const AsmToken &Tok = Parser.getTok();
3350 SMLoc S = Tok.getLoc();
3351 if (Tok.isNot(AsmToken::Identifier)) {
3352 Error(S, "shift operator 'asr' or 'lsl' expected");
3353 return MatchOperand_ParseFail;
3355 StringRef ShiftName = Tok.getString();
3357 if (ShiftName == "lsl" || ShiftName == "LSL")
3359 else if (ShiftName == "asr" || ShiftName == "ASR")
3362 Error(S, "shift operator 'asr' or 'lsl' expected");
3363 return MatchOperand_ParseFail;
3365 Parser.Lex(); // Eat the operator.
3367 // A '#' and a shift amount.
3368 if (Parser.getTok().isNot(AsmToken::Hash) &&
3369 Parser.getTok().isNot(AsmToken::Dollar)) {
3370 Error(Parser.getTok().getLoc(), "'#' expected");
3371 return MatchOperand_ParseFail;
3373 Parser.Lex(); // Eat hash token.
3375 const MCExpr *ShiftAmount;
3376 SMLoc E = Parser.getTok().getLoc();
3377 if (getParser().ParseExpression(ShiftAmount)) {
3378 Error(E, "malformed shift expression");
3379 return MatchOperand_ParseFail;
3381 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3383 Error(E, "shift amount must be an immediate");
3384 return MatchOperand_ParseFail;
3387 int64_t Val = CE->getValue();
3389 // Shift amount must be in [1,32]
3390 if (Val < 1 || Val > 32) {
3391 Error(E, "'asr' shift amount must be in range [1,32]");
3392 return MatchOperand_ParseFail;
3394 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3395 if (isThumb() && Val == 32) {
3396 Error(E, "'asr #32' shift amount not allowed in Thumb mode");
3397 return MatchOperand_ParseFail;
3399 if (Val == 32) Val = 0;
3401 // Shift amount must be in [1,32]
3402 if (Val < 0 || Val > 31) {
3403 Error(E, "'lsr' shift amount must be in range [0,31]");
3404 return MatchOperand_ParseFail;
3408 E = Parser.getTok().getLoc();
3409 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
3411 return MatchOperand_Success;
3414 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3415 /// of instructions. Legal values are:
3416 /// ror #n 'n' in {0, 8, 16, 24}
3417 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3418 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3419 const AsmToken &Tok = Parser.getTok();
3420 SMLoc S = Tok.getLoc();
3421 if (Tok.isNot(AsmToken::Identifier))
3422 return MatchOperand_NoMatch;
3423 StringRef ShiftName = Tok.getString();
3424 if (ShiftName != "ror" && ShiftName != "ROR")
3425 return MatchOperand_NoMatch;
3426 Parser.Lex(); // Eat the operator.
3428 // A '#' and a rotate amount.
3429 if (Parser.getTok().isNot(AsmToken::Hash) &&
3430 Parser.getTok().isNot(AsmToken::Dollar)) {
3431 Error(Parser.getTok().getLoc(), "'#' expected");
3432 return MatchOperand_ParseFail;
3434 Parser.Lex(); // Eat hash token.
3436 const MCExpr *ShiftAmount;
3437 SMLoc E = Parser.getTok().getLoc();
3438 if (getParser().ParseExpression(ShiftAmount)) {
3439 Error(E, "malformed rotate expression");
3440 return MatchOperand_ParseFail;
3442 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3444 Error(E, "rotate amount must be an immediate");
3445 return MatchOperand_ParseFail;
3448 int64_t Val = CE->getValue();
3449 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
3450 // normally, zero is represented in asm by omitting the rotate operand
3452 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
3453 Error(E, "'ror' rotate amount must be 8, 16, or 24");
3454 return MatchOperand_ParseFail;
3457 E = Parser.getTok().getLoc();
3458 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
3460 return MatchOperand_Success;
3463 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3464 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3465 SMLoc S = Parser.getTok().getLoc();
3466 // The bitfield descriptor is really two operands, the LSB and the width.
3467 if (Parser.getTok().isNot(AsmToken::Hash) &&
3468 Parser.getTok().isNot(AsmToken::Dollar)) {
3469 Error(Parser.getTok().getLoc(), "'#' expected");
3470 return MatchOperand_ParseFail;
3472 Parser.Lex(); // Eat hash token.
3474 const MCExpr *LSBExpr;
3475 SMLoc E = Parser.getTok().getLoc();
3476 if (getParser().ParseExpression(LSBExpr)) {
3477 Error(E, "malformed immediate expression");
3478 return MatchOperand_ParseFail;
3480 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
3482 Error(E, "'lsb' operand must be an immediate");
3483 return MatchOperand_ParseFail;
3486 int64_t LSB = CE->getValue();
3487 // The LSB must be in the range [0,31]
3488 if (LSB < 0 || LSB > 31) {
3489 Error(E, "'lsb' operand must be in the range [0,31]");
3490 return MatchOperand_ParseFail;
3492 E = Parser.getTok().getLoc();
3494 // Expect another immediate operand.
3495 if (Parser.getTok().isNot(AsmToken::Comma)) {
3496 Error(Parser.getTok().getLoc(), "too few operands");
3497 return MatchOperand_ParseFail;
3499 Parser.Lex(); // Eat hash token.
3500 if (Parser.getTok().isNot(AsmToken::Hash) &&
3501 Parser.getTok().isNot(AsmToken::Dollar)) {
3502 Error(Parser.getTok().getLoc(), "'#' expected");
3503 return MatchOperand_ParseFail;
3505 Parser.Lex(); // Eat hash token.
3507 const MCExpr *WidthExpr;
3508 if (getParser().ParseExpression(WidthExpr)) {
3509 Error(E, "malformed immediate expression");
3510 return MatchOperand_ParseFail;
3512 CE = dyn_cast<MCConstantExpr>(WidthExpr);
3514 Error(E, "'width' operand must be an immediate");
3515 return MatchOperand_ParseFail;
3518 int64_t Width = CE->getValue();
3519 // The LSB must be in the range [1,32-lsb]
3520 if (Width < 1 || Width > 32 - LSB) {
3521 Error(E, "'width' operand must be in the range [1,32-lsb]");
3522 return MatchOperand_ParseFail;
3524 E = Parser.getTok().getLoc();
3526 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
3528 return MatchOperand_Success;
3531 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3532 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3533 // Check for a post-index addressing register operand. Specifically:
3534 // postidx_reg := '+' register {, shift}
3535 // | '-' register {, shift}
3536 // | register {, shift}
3538 // This method must return MatchOperand_NoMatch without consuming any tokens
3539 // in the case where there is no match, as other alternatives take other
3541 AsmToken Tok = Parser.getTok();
3542 SMLoc S = Tok.getLoc();
3543 bool haveEaten = false;
3546 if (Tok.is(AsmToken::Plus)) {
3547 Parser.Lex(); // Eat the '+' token.
3549 } else if (Tok.is(AsmToken::Minus)) {
3550 Parser.Lex(); // Eat the '-' token.
3554 if (Parser.getTok().is(AsmToken::Identifier))
3555 Reg = tryParseRegister();
3558 return MatchOperand_NoMatch;
3559 Error(Parser.getTok().getLoc(), "register expected");
3560 return MatchOperand_ParseFail;
3562 SMLoc E = Parser.getTok().getLoc();
3564 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
3565 unsigned ShiftImm = 0;
3566 if (Parser.getTok().is(AsmToken::Comma)) {
3567 Parser.Lex(); // Eat the ','.
3568 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
3569 return MatchOperand_ParseFail;
3572 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
3575 return MatchOperand_Success;
3578 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3579 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3580 // Check for a post-index addressing register operand. Specifically:
3581 // am3offset := '+' register
3588 // This method must return MatchOperand_NoMatch without consuming any tokens
3589 // in the case where there is no match, as other alternatives take other
3591 AsmToken Tok = Parser.getTok();
3592 SMLoc S = Tok.getLoc();
3594 // Do immediates first, as we always parse those if we have a '#'.
3595 if (Parser.getTok().is(AsmToken::Hash) ||
3596 Parser.getTok().is(AsmToken::Dollar)) {
3597 Parser.Lex(); // Eat the '#'.
3598 // Explicitly look for a '-', as we need to encode negative zero
3600 bool isNegative = Parser.getTok().is(AsmToken::Minus);
3601 const MCExpr *Offset;
3602 if (getParser().ParseExpression(Offset))
3603 return MatchOperand_ParseFail;
3604 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
3606 Error(S, "constant expression expected");
3607 return MatchOperand_ParseFail;
3609 SMLoc E = Tok.getLoc();
3610 // Negative zero is encoded as the flag value INT32_MIN.
3611 int32_t Val = CE->getValue();
3612 if (isNegative && Val == 0)
3616 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
3618 return MatchOperand_Success;
3622 bool haveEaten = false;
3625 if (Tok.is(AsmToken::Plus)) {
3626 Parser.Lex(); // Eat the '+' token.
3628 } else if (Tok.is(AsmToken::Minus)) {
3629 Parser.Lex(); // Eat the '-' token.
3633 if (Parser.getTok().is(AsmToken::Identifier))
3634 Reg = tryParseRegister();
3637 return MatchOperand_NoMatch;
3638 Error(Parser.getTok().getLoc(), "register expected");
3639 return MatchOperand_ParseFail;
3641 SMLoc E = Parser.getTok().getLoc();
3643 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
3646 return MatchOperand_Success;
3649 /// cvtT2LdrdPre - Convert parsed operands to MCInst.
3650 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3651 /// when they refer multiple MIOperands inside a single one.
3653 cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
3654 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3656 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3657 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3658 // Create a writeback register dummy placeholder.
3659 Inst.addOperand(MCOperand::CreateReg(0));
3661 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3663 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3667 /// cvtT2StrdPre - Convert parsed operands to MCInst.
3668 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3669 /// when they refer multiple MIOperands inside a single one.
3671 cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
3672 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3673 // Create a writeback register dummy placeholder.
3674 Inst.addOperand(MCOperand::CreateReg(0));
3676 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3677 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3679 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3681 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3685 /// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3686 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3687 /// when they refer multiple MIOperands inside a single one.
3689 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3690 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3691 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3693 // Create a writeback register dummy placeholder.
3694 Inst.addOperand(MCOperand::CreateImm(0));
3696 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3697 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3701 /// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3702 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3703 /// when they refer multiple MIOperands inside a single one.
3705 cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3706 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3707 // Create a writeback register dummy placeholder.
3708 Inst.addOperand(MCOperand::CreateImm(0));
3709 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3710 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3711 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3715 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3716 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3717 /// when they refer multiple MIOperands inside a single one.
3719 cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3720 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3721 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3723 // Create a writeback register dummy placeholder.
3724 Inst.addOperand(MCOperand::CreateImm(0));
3726 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3727 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3731 /// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3732 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3733 /// when they refer multiple MIOperands inside a single one.
3735 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3736 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3737 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3739 // Create a writeback register dummy placeholder.
3740 Inst.addOperand(MCOperand::CreateImm(0));
3742 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3743 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3748 /// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3749 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3750 /// when they refer multiple MIOperands inside a single one.
3752 cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3753 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3754 // Create a writeback register dummy placeholder.
3755 Inst.addOperand(MCOperand::CreateImm(0));
3756 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3757 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3758 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3762 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3763 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3764 /// when they refer multiple MIOperands inside a single one.
3766 cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3767 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3768 // Create a writeback register dummy placeholder.
3769 Inst.addOperand(MCOperand::CreateImm(0));
3770 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3771 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3772 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3776 /// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
3777 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3778 /// when they refer multiple MIOperands inside a single one.
3780 cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
3781 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3782 // Create a writeback register dummy placeholder.
3783 Inst.addOperand(MCOperand::CreateImm(0));
3784 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3785 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
3786 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3790 /// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
3791 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3792 /// when they refer multiple MIOperands inside a single one.
3794 cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
3795 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3797 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3798 // Create a writeback register dummy placeholder.
3799 Inst.addOperand(MCOperand::CreateImm(0));
3801 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3803 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
3805 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3809 /// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
3810 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3811 /// when they refer multiple MIOperands inside a single one.
3813 cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
3814 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3816 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3817 // Create a writeback register dummy placeholder.
3818 Inst.addOperand(MCOperand::CreateImm(0));
3820 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3822 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
3824 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3828 /// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
3829 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3830 /// when they refer multiple MIOperands inside a single one.
3832 cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
3833 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3834 // Create a writeback register dummy placeholder.
3835 Inst.addOperand(MCOperand::CreateImm(0));
3837 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3839 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3841 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
3843 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3847 /// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
3848 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3849 /// when they refer multiple MIOperands inside a single one.
3851 cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
3852 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3853 // Create a writeback register dummy placeholder.
3854 Inst.addOperand(MCOperand::CreateImm(0));
3856 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3858 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3860 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
3862 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3866 /// cvtLdrdPre - Convert parsed operands to MCInst.
3867 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3868 /// when they refer multiple MIOperands inside a single one.
3870 cvtLdrdPre(MCInst &Inst, unsigned Opcode,
3871 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3873 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3874 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3875 // Create a writeback register dummy placeholder.
3876 Inst.addOperand(MCOperand::CreateImm(0));
3878 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
3880 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3884 /// cvtStrdPre - Convert parsed operands to MCInst.
3885 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3886 /// when they refer multiple MIOperands inside a single one.
3888 cvtStrdPre(MCInst &Inst, unsigned Opcode,
3889 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3890 // Create a writeback register dummy placeholder.
3891 Inst.addOperand(MCOperand::CreateImm(0));
3893 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3894 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3896 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
3898 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3902 /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
3903 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3904 /// when they refer multiple MIOperands inside a single one.
3906 cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
3907 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3908 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3909 // Create a writeback register dummy placeholder.
3910 Inst.addOperand(MCOperand::CreateImm(0));
3911 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
3912 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3916 /// cvtThumbMultiple- Convert parsed operands to MCInst.
3917 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3918 /// when they refer multiple MIOperands inside a single one.
3920 cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
3921 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3922 // The second source operand must be the same register as the destination
3924 if (Operands.size() == 6 &&
3925 (((ARMOperand*)Operands[3])->getReg() !=
3926 ((ARMOperand*)Operands[5])->getReg()) &&
3927 (((ARMOperand*)Operands[3])->getReg() !=
3928 ((ARMOperand*)Operands[4])->getReg())) {
3929 Error(Operands[3]->getStartLoc(),
3930 "destination register must match source register");
3933 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3934 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
3935 // If we have a three-operand form, make sure to set Rn to be the operand
3936 // that isn't the same as Rd.
3938 if (Operands.size() == 6 &&
3939 ((ARMOperand*)Operands[4])->getReg() ==
3940 ((ARMOperand*)Operands[3])->getReg())
3942 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
3943 Inst.addOperand(Inst.getOperand(0));
3944 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
3950 cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
3951 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3953 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
3954 // Create a writeback register dummy placeholder.
3955 Inst.addOperand(MCOperand::CreateImm(0));
3957 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3959 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3964 cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
3965 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3967 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
3968 // Create a writeback register dummy placeholder.
3969 Inst.addOperand(MCOperand::CreateImm(0));
3971 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3973 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
3975 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3980 cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
3981 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3982 // Create a writeback register dummy placeholder.
3983 Inst.addOperand(MCOperand::CreateImm(0));
3985 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3987 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
3989 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3994 cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
3995 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3996 // Create a writeback register dummy placeholder.
3997 Inst.addOperand(MCOperand::CreateImm(0));
3999 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4001 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4003 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4005 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4009 /// Parse an ARM memory expression, return false if successful else return true
4010 /// or an error. The first token must be a '[' when called.
4012 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4014 assert(Parser.getTok().is(AsmToken::LBrac) &&
4015 "Token is not a Left Bracket");
4016 S = Parser.getTok().getLoc();
4017 Parser.Lex(); // Eat left bracket token.
4019 const AsmToken &BaseRegTok = Parser.getTok();
4020 int BaseRegNum = tryParseRegister();
4021 if (BaseRegNum == -1)
4022 return Error(BaseRegTok.getLoc(), "register expected");
4024 // The next token must either be a comma or a closing bracket.
4025 const AsmToken &Tok = Parser.getTok();
4026 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
4027 return Error(Tok.getLoc(), "malformed memory operand");
4029 if (Tok.is(AsmToken::RBrac)) {
4031 Parser.Lex(); // Eat right bracket token.
4033 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4034 0, 0, false, S, E));
4036 // If there's a pre-indexing writeback marker, '!', just add it as a token
4037 // operand. It's rather odd, but syntactically valid.
4038 if (Parser.getTok().is(AsmToken::Exclaim)) {
4039 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4040 Parser.Lex(); // Eat the '!'.
4046 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
4047 Parser.Lex(); // Eat the comma.
4049 // If we have a ':', it's an alignment specifier.
4050 if (Parser.getTok().is(AsmToken::Colon)) {
4051 Parser.Lex(); // Eat the ':'.
4052 E = Parser.getTok().getLoc();
4055 if (getParser().ParseExpression(Expr))
4058 // The expression has to be a constant. Memory references with relocations
4059 // don't come through here, as they use the <label> forms of the relevant
4061 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4063 return Error (E, "constant expression expected");
4066 switch (CE->getValue()) {
4069 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4070 case 16: Align = 2; break;
4071 case 32: Align = 4; break;
4072 case 64: Align = 8; break;
4073 case 128: Align = 16; break;
4074 case 256: Align = 32; break;
4077 // Now we should have the closing ']'
4078 E = Parser.getTok().getLoc();
4079 if (Parser.getTok().isNot(AsmToken::RBrac))
4080 return Error(E, "']' expected");
4081 Parser.Lex(); // Eat right bracket token.
4083 // Don't worry about range checking the value here. That's handled by
4084 // the is*() predicates.
4085 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4086 ARM_AM::no_shift, 0, Align,
4089 // If there's a pre-indexing writeback marker, '!', just add it as a token
4091 if (Parser.getTok().is(AsmToken::Exclaim)) {
4092 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4093 Parser.Lex(); // Eat the '!'.
4099 // If we have a '#', it's an immediate offset, else assume it's a register
4100 // offset. Be friendly and also accept a plain integer (without a leading
4101 // hash) for gas compatibility.
4102 if (Parser.getTok().is(AsmToken::Hash) ||
4103 Parser.getTok().is(AsmToken::Dollar) ||
4104 Parser.getTok().is(AsmToken::Integer)) {
4105 if (Parser.getTok().isNot(AsmToken::Integer))
4106 Parser.Lex(); // Eat the '#'.
4107 E = Parser.getTok().getLoc();
4109 bool isNegative = getParser().getTok().is(AsmToken::Minus);
4110 const MCExpr *Offset;
4111 if (getParser().ParseExpression(Offset))
4114 // The expression has to be a constant. Memory references with relocations
4115 // don't come through here, as they use the <label> forms of the relevant
4117 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4119 return Error (E, "constant expression expected");
4121 // If the constant was #-0, represent it as INT32_MIN.
4122 int32_t Val = CE->getValue();
4123 if (isNegative && Val == 0)
4124 CE = MCConstantExpr::Create(INT32_MIN, getContext());
4126 // Now we should have the closing ']'
4127 E = Parser.getTok().getLoc();
4128 if (Parser.getTok().isNot(AsmToken::RBrac))
4129 return Error(E, "']' expected");
4130 Parser.Lex(); // Eat right bracket token.
4132 // Don't worry about range checking the value here. That's handled by
4133 // the is*() predicates.
4134 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4135 ARM_AM::no_shift, 0, 0,
4138 // If there's a pre-indexing writeback marker, '!', just add it as a token
4140 if (Parser.getTok().is(AsmToken::Exclaim)) {
4141 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4142 Parser.Lex(); // Eat the '!'.
4148 // The register offset is optionally preceded by a '+' or '-'
4149 bool isNegative = false;
4150 if (Parser.getTok().is(AsmToken::Minus)) {
4152 Parser.Lex(); // Eat the '-'.
4153 } else if (Parser.getTok().is(AsmToken::Plus)) {
4155 Parser.Lex(); // Eat the '+'.
4158 E = Parser.getTok().getLoc();
4159 int OffsetRegNum = tryParseRegister();
4160 if (OffsetRegNum == -1)
4161 return Error(E, "register expected");
4163 // If there's a shift operator, handle it.
4164 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4165 unsigned ShiftImm = 0;
4166 if (Parser.getTok().is(AsmToken::Comma)) {
4167 Parser.Lex(); // Eat the ','.
4168 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4172 // Now we should have the closing ']'
4173 E = Parser.getTok().getLoc();
4174 if (Parser.getTok().isNot(AsmToken::RBrac))
4175 return Error(E, "']' expected");
4176 Parser.Lex(); // Eat right bracket token.
4178 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4179 ShiftType, ShiftImm, 0, isNegative,
4182 // If there's a pre-indexing writeback marker, '!', just add it as a token
4184 if (Parser.getTok().is(AsmToken::Exclaim)) {
4185 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4186 Parser.Lex(); // Eat the '!'.
4192 /// parseMemRegOffsetShift - one of these two:
4193 /// ( lsl | lsr | asr | ror ) , # shift_amount
4195 /// return true if it parses a shift otherwise it returns false.
4196 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4198 SMLoc Loc = Parser.getTok().getLoc();
4199 const AsmToken &Tok = Parser.getTok();
4200 if (Tok.isNot(AsmToken::Identifier))
4202 StringRef ShiftName = Tok.getString();
4203 if (ShiftName == "lsl" || ShiftName == "LSL" ||
4204 ShiftName == "asl" || ShiftName == "ASL")
4206 else if (ShiftName == "lsr" || ShiftName == "LSR")
4208 else if (ShiftName == "asr" || ShiftName == "ASR")
4210 else if (ShiftName == "ror" || ShiftName == "ROR")
4212 else if (ShiftName == "rrx" || ShiftName == "RRX")
4215 return Error(Loc, "illegal shift operator");
4216 Parser.Lex(); // Eat shift type token.
4218 // rrx stands alone.
4220 if (St != ARM_AM::rrx) {
4221 Loc = Parser.getTok().getLoc();
4222 // A '#' and a shift amount.
4223 const AsmToken &HashTok = Parser.getTok();
4224 if (HashTok.isNot(AsmToken::Hash) &&
4225 HashTok.isNot(AsmToken::Dollar))
4226 return Error(HashTok.getLoc(), "'#' expected");
4227 Parser.Lex(); // Eat hash token.
4230 if (getParser().ParseExpression(Expr))
4232 // Range check the immediate.
4233 // lsl, ror: 0 <= imm <= 31
4234 // lsr, asr: 0 <= imm <= 32
4235 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4237 return Error(Loc, "shift amount must be an immediate");
4238 int64_t Imm = CE->getValue();
4240 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4241 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4242 return Error(Loc, "immediate shift value out of range");
4249 /// parseFPImm - A floating point immediate expression operand.
4250 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4251 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4252 SMLoc S = Parser.getTok().getLoc();
4254 if (Parser.getTok().isNot(AsmToken::Hash) &&
4255 Parser.getTok().isNot(AsmToken::Dollar))
4256 return MatchOperand_NoMatch;
4258 // Disambiguate the VMOV forms that can accept an FP immediate.
4259 // vmov.f32 <sreg>, #imm
4260 // vmov.f64 <dreg>, #imm
4261 // vmov.f32 <dreg>, #imm @ vector f32x2
4262 // vmov.f32 <qreg>, #imm @ vector f32x4
4264 // There are also the NEON VMOV instructions which expect an
4265 // integer constant. Make sure we don't try to parse an FPImm
4267 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4268 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4269 if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
4270 TyOp->getToken() != ".f64"))
4271 return MatchOperand_NoMatch;
4273 Parser.Lex(); // Eat the '#'.
4275 // Handle negation, as that still comes through as a separate token.
4276 bool isNegative = false;
4277 if (Parser.getTok().is(AsmToken::Minus)) {
4281 const AsmToken &Tok = Parser.getTok();
4282 if (Tok.is(AsmToken::Real)) {
4283 APFloat RealVal(APFloat::IEEEdouble, Tok.getString());
4284 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4285 // If we had a '-' in front, toggle the sign bit.
4286 IntVal ^= (uint64_t)isNegative << 63;
4287 int Val = ARM_AM::getFP64Imm(APInt(64, IntVal));
4288 Parser.Lex(); // Eat the token.
4290 TokError("floating point value out of range");
4291 return MatchOperand_ParseFail;
4293 Operands.push_back(ARMOperand::CreateFPImm(Val, S, getContext()));
4294 return MatchOperand_Success;
4296 if (Tok.is(AsmToken::Integer)) {
4297 int64_t Val = Tok.getIntVal();
4298 Parser.Lex(); // Eat the token.
4299 if (Val > 255 || Val < 0) {
4300 TokError("encoded floating point value out of range");
4301 return MatchOperand_ParseFail;
4303 Operands.push_back(ARMOperand::CreateFPImm(Val, S, getContext()));
4304 return MatchOperand_Success;
4307 TokError("invalid floating point immediate");
4308 return MatchOperand_ParseFail;
4310 /// Parse a arm instruction operand. For now this parses the operand regardless
4311 /// of the mnemonic.
4312 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4313 StringRef Mnemonic) {
4316 // Check if the current operand has a custom associated parser, if so, try to
4317 // custom parse the operand, or fallback to the general approach.
4318 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4319 if (ResTy == MatchOperand_Success)
4321 // If there wasn't a custom match, try the generic matcher below. Otherwise,
4322 // there was a match, but an error occurred, in which case, just return that
4323 // the operand parsing failed.
4324 if (ResTy == MatchOperand_ParseFail)
4327 switch (getLexer().getKind()) {
4329 Error(Parser.getTok().getLoc(), "unexpected token in operand");
4331 case AsmToken::Identifier: {
4332 if (!tryParseRegisterWithWriteBack(Operands))
4334 int Res = tryParseShiftRegister(Operands);
4335 if (Res == 0) // success
4337 else if (Res == -1) // irrecoverable error
4339 // If this is VMRS, check for the apsr_nzcv operand.
4340 if (Mnemonic == "vmrs" && Parser.getTok().getString() == "apsr_nzcv") {
4341 S = Parser.getTok().getLoc();
4343 Operands.push_back(ARMOperand::CreateToken("apsr_nzcv", S));
4347 // Fall though for the Identifier case that is not a register or a
4350 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
4351 case AsmToken::Integer: // things like 1f and 2b as a branch targets
4352 case AsmToken::String: // quoted label names.
4353 case AsmToken::Dot: { // . as a branch target
4354 // This was not a register so parse other operands that start with an
4355 // identifier (like labels) as expressions and create them as immediates.
4356 const MCExpr *IdVal;
4357 S = Parser.getTok().getLoc();
4358 if (getParser().ParseExpression(IdVal))
4360 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4361 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4364 case AsmToken::LBrac:
4365 return parseMemory(Operands);
4366 case AsmToken::LCurly:
4367 return parseRegisterList(Operands);
4368 case AsmToken::Dollar:
4369 case AsmToken::Hash: {
4370 // #42 -> immediate.
4371 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
4372 S = Parser.getTok().getLoc();
4374 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4375 const MCExpr *ImmVal;
4376 if (getParser().ParseExpression(ImmVal))
4378 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4380 int32_t Val = CE->getValue();
4381 if (isNegative && Val == 0)
4382 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4384 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4385 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4388 case AsmToken::Colon: {
4389 // ":lower16:" and ":upper16:" expression prefixes
4390 // FIXME: Check it's an expression prefix,
4391 // e.g. (FOO - :lower16:BAR) isn't legal.
4392 ARMMCExpr::VariantKind RefKind;
4393 if (parsePrefix(RefKind))
4396 const MCExpr *SubExprVal;
4397 if (getParser().ParseExpression(SubExprVal))
4400 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4402 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4403 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4409 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4410 // :lower16: and :upper16:.
4411 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4412 RefKind = ARMMCExpr::VK_ARM_None;
4414 // :lower16: and :upper16: modifiers
4415 assert(getLexer().is(AsmToken::Colon) && "expected a :");
4416 Parser.Lex(); // Eat ':'
4418 if (getLexer().isNot(AsmToken::Identifier)) {
4419 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4423 StringRef IDVal = Parser.getTok().getIdentifier();
4424 if (IDVal == "lower16") {
4425 RefKind = ARMMCExpr::VK_ARM_LO16;
4426 } else if (IDVal == "upper16") {
4427 RefKind = ARMMCExpr::VK_ARM_HI16;
4429 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4434 if (getLexer().isNot(AsmToken::Colon)) {
4435 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4438 Parser.Lex(); // Eat the last ':'
4442 /// \brief Given a mnemonic, split out possible predication code and carry
4443 /// setting letters to form a canonical mnemonic and flags.
4445 // FIXME: Would be nice to autogen this.
4446 // FIXME: This is a bit of a maze of special cases.
4447 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4448 unsigned &PredicationCode,
4450 unsigned &ProcessorIMod,
4451 StringRef &ITMask) {
4452 PredicationCode = ARMCC::AL;
4453 CarrySetting = false;
4456 // Ignore some mnemonics we know aren't predicated forms.
4458 // FIXME: Would be nice to autogen this.
4459 if ((Mnemonic == "movs" && isThumb()) ||
4460 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
4461 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
4462 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
4463 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
4464 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
4465 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
4466 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4467 Mnemonic == "fmuls")
4470 // First, split out any predication code. Ignore mnemonics we know aren't
4471 // predicated but do have a carry-set and so weren't caught above.
4472 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4473 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4474 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4475 Mnemonic != "sbcs" && Mnemonic != "rscs") {
4476 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4477 .Case("eq", ARMCC::EQ)
4478 .Case("ne", ARMCC::NE)
4479 .Case("hs", ARMCC::HS)
4480 .Case("cs", ARMCC::HS)
4481 .Case("lo", ARMCC::LO)
4482 .Case("cc", ARMCC::LO)
4483 .Case("mi", ARMCC::MI)
4484 .Case("pl", ARMCC::PL)
4485 .Case("vs", ARMCC::VS)
4486 .Case("vc", ARMCC::VC)
4487 .Case("hi", ARMCC::HI)
4488 .Case("ls", ARMCC::LS)
4489 .Case("ge", ARMCC::GE)
4490 .Case("lt", ARMCC::LT)
4491 .Case("gt", ARMCC::GT)
4492 .Case("le", ARMCC::LE)
4493 .Case("al", ARMCC::AL)
4496 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4497 PredicationCode = CC;
4501 // Next, determine if we have a carry setting bit. We explicitly ignore all
4502 // the instructions we know end in 's'.
4503 if (Mnemonic.endswith("s") &&
4504 !(Mnemonic == "cps" || Mnemonic == "mls" ||
4505 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4506 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4507 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4508 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4509 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4510 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4511 Mnemonic == "fmuls" || Mnemonic == "fcmps" ||
4512 (Mnemonic == "movs" && isThumb()))) {
4513 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4514 CarrySetting = true;
4517 // The "cps" instruction can have a interrupt mode operand which is glued into
4518 // the mnemonic. Check if this is the case, split it and parse the imod op
4519 if (Mnemonic.startswith("cps")) {
4520 // Split out any imod code.
4522 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4523 .Case("ie", ARM_PROC::IE)
4524 .Case("id", ARM_PROC::ID)
4527 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4528 ProcessorIMod = IMod;
4532 // The "it" instruction has the condition mask on the end of the mnemonic.
4533 if (Mnemonic.startswith("it")) {
4534 ITMask = Mnemonic.slice(2, Mnemonic.size());
4535 Mnemonic = Mnemonic.slice(0, 2);
4541 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
4542 /// inclusion of carry set or predication code operands.
4544 // FIXME: It would be nice to autogen this.
4546 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
4547 bool &CanAcceptPredicationCode) {
4548 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4549 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4550 Mnemonic == "add" || Mnemonic == "adc" ||
4551 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4552 Mnemonic == "orr" || Mnemonic == "mvn" ||
4553 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4554 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4555 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4556 Mnemonic == "mla" || Mnemonic == "smlal" ||
4557 Mnemonic == "umlal" || Mnemonic == "umull"))) {
4558 CanAcceptCarrySet = true;
4560 CanAcceptCarrySet = false;
4562 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
4563 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
4564 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
4565 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
4566 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
4567 (Mnemonic == "clrex" && !isThumb()) ||
4568 (Mnemonic == "nop" && isThumbOne()) ||
4569 ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" ||
4570 Mnemonic == "ldc2" || Mnemonic == "ldc2l" ||
4571 Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) ||
4572 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
4574 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
4575 CanAcceptPredicationCode = false;
4577 CanAcceptPredicationCode = true;
4580 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
4581 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
4582 CanAcceptPredicationCode = false;
4586 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4587 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4588 // FIXME: This is all horribly hacky. We really need a better way to deal
4589 // with optional operands like this in the matcher table.
4591 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4592 // another does not. Specifically, the MOVW instruction does not. So we
4593 // special case it here and remove the defaulted (non-setting) cc_out
4594 // operand if that's the instruction we're trying to match.
4596 // We do this as post-processing of the explicit operands rather than just
4597 // conditionally adding the cc_out in the first place because we need
4598 // to check the type of the parsed immediate operand.
4599 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4600 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4601 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4602 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4605 // Register-register 'add' for thumb does not have a cc_out operand
4606 // when there are only two register operands.
4607 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4608 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4609 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4610 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4612 // Register-register 'add' for thumb does not have a cc_out operand
4613 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4614 // have to check the immediate range here since Thumb2 has a variant
4615 // that can handle a different range and has a cc_out operand.
4616 if (((isThumb() && Mnemonic == "add") ||
4617 (isThumbTwo() && Mnemonic == "sub")) &&
4618 Operands.size() == 6 &&
4619 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4620 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4621 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4622 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4623 (static_cast<ARMOperand*>(Operands[5])->isReg() ||
4624 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4626 // For Thumb2, add/sub immediate does not have a cc_out operand for the
4627 // imm0_4095 variant. That's the least-preferred variant when
4628 // selecting via the generic "add" mnemonic, so to know that we
4629 // should remove the cc_out operand, we have to explicitly check that
4630 // it's not one of the other variants. Ugh.
4631 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4632 Operands.size() == 6 &&
4633 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4634 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4635 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4636 // Nest conditions rather than one big 'if' statement for readability.
4638 // If either register is a high reg, it's either one of the SP
4639 // variants (handled above) or a 32-bit encoding, so we just
4640 // check against T3.
4641 if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4642 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
4643 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
4645 // If both registers are low, we're in an IT block, and the immediate is
4646 // in range, we should use encoding T1 instead, which has a cc_out.
4648 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4649 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4650 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
4653 // Otherwise, we use encoding T4, which does not have a cc_out
4658 // The thumb2 multiply instruction doesn't have a CCOut register, so
4659 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
4660 // use the 16-bit encoding or not.
4661 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
4662 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4663 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4664 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4665 static_cast<ARMOperand*>(Operands[5])->isReg() &&
4666 // If the registers aren't low regs, the destination reg isn't the
4667 // same as one of the source regs, or the cc_out operand is zero
4668 // outside of an IT block, we have to use the 32-bit encoding, so
4669 // remove the cc_out operand.
4670 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4671 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4672 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
4674 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4675 static_cast<ARMOperand*>(Operands[5])->getReg() &&
4676 static_cast<ARMOperand*>(Operands[3])->getReg() !=
4677 static_cast<ARMOperand*>(Operands[4])->getReg())))
4680 // Also check the 'mul' syntax variant that doesn't specify an explicit
4681 // destination register.
4682 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
4683 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4684 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4685 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4686 // If the registers aren't low regs or the cc_out operand is zero
4687 // outside of an IT block, we have to use the 32-bit encoding, so
4688 // remove the cc_out operand.
4689 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4690 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4696 // Register-register 'add/sub' for thumb does not have a cc_out operand
4697 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
4698 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
4699 // right, this will result in better diagnostics (which operand is off)
4701 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
4702 (Operands.size() == 5 || Operands.size() == 6) &&
4703 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4704 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4705 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4711 static bool isDataTypeToken(StringRef Tok) {
4712 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
4713 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
4714 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
4715 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
4716 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
4717 Tok == ".f" || Tok == ".d";
4720 // FIXME: This bit should probably be handled via an explicit match class
4721 // in the .td files that matches the suffix instead of having it be
4722 // a literal string token the way it is now.
4723 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
4724 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
4727 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features);
4728 /// Parse an arm instruction mnemonic followed by its operands.
4729 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
4730 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4731 // Apply mnemonic aliases before doing anything else, as the destination
4732 // mnemnonic may include suffices and we want to handle them normally.
4733 // The generic tblgen'erated code does this later, at the start of
4734 // MatchInstructionImpl(), but that's too late for aliases that include
4735 // any sort of suffix.
4736 unsigned AvailableFeatures = getAvailableFeatures();
4737 applyMnemonicAliases(Name, AvailableFeatures);
4739 // First check for the ARM-specific .req directive.
4740 if (Parser.getTok().is(AsmToken::Identifier) &&
4741 Parser.getTok().getIdentifier() == ".req") {
4742 parseDirectiveReq(Name, NameLoc);
4743 // We always return 'error' for this, as we're done with this
4744 // statement and don't need to match the 'instruction."
4748 // Create the leading tokens for the mnemonic, split by '.' characters.
4749 size_t Start = 0, Next = Name.find('.');
4750 StringRef Mnemonic = Name.slice(Start, Next);
4752 // Split out the predication code and carry setting flag from the mnemonic.
4753 unsigned PredicationCode;
4754 unsigned ProcessorIMod;
4757 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
4758 ProcessorIMod, ITMask);
4760 // In Thumb1, only the branch (B) instruction can be predicated.
4761 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
4762 Parser.EatToEndOfStatement();
4763 return Error(NameLoc, "conditional execution not supported in Thumb1");
4766 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
4768 // Handle the IT instruction ITMask. Convert it to a bitmask. This
4769 // is the mask as it will be for the IT encoding if the conditional
4770 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
4771 // where the conditional bit0 is zero, the instruction post-processing
4772 // will adjust the mask accordingly.
4773 if (Mnemonic == "it") {
4774 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
4775 if (ITMask.size() > 3) {
4776 Parser.EatToEndOfStatement();
4777 return Error(Loc, "too many conditions on IT instruction");
4780 for (unsigned i = ITMask.size(); i != 0; --i) {
4781 char pos = ITMask[i - 1];
4782 if (pos != 't' && pos != 'e') {
4783 Parser.EatToEndOfStatement();
4784 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
4787 if (ITMask[i - 1] == 't')
4790 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
4793 // FIXME: This is all a pretty gross hack. We should automatically handle
4794 // optional operands like this via tblgen.
4796 // Next, add the CCOut and ConditionCode operands, if needed.
4798 // For mnemonics which can ever incorporate a carry setting bit or predication
4799 // code, our matching model involves us always generating CCOut and
4800 // ConditionCode operands to match the mnemonic "as written" and then we let
4801 // the matcher deal with finding the right instruction or generating an
4802 // appropriate error.
4803 bool CanAcceptCarrySet, CanAcceptPredicationCode;
4804 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
4806 // If we had a carry-set on an instruction that can't do that, issue an
4808 if (!CanAcceptCarrySet && CarrySetting) {
4809 Parser.EatToEndOfStatement();
4810 return Error(NameLoc, "instruction '" + Mnemonic +
4811 "' can not set flags, but 's' suffix specified");
4813 // If we had a predication code on an instruction that can't do that, issue an
4815 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
4816 Parser.EatToEndOfStatement();
4817 return Error(NameLoc, "instruction '" + Mnemonic +
4818 "' is not predicable, but condition code specified");
4821 // Add the carry setting operand, if necessary.
4822 if (CanAcceptCarrySet) {
4823 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
4824 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
4828 // Add the predication code operand, if necessary.
4829 if (CanAcceptPredicationCode) {
4830 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
4832 Operands.push_back(ARMOperand::CreateCondCode(
4833 ARMCC::CondCodes(PredicationCode), Loc));
4836 // Add the processor imod operand, if necessary.
4837 if (ProcessorIMod) {
4838 Operands.push_back(ARMOperand::CreateImm(
4839 MCConstantExpr::Create(ProcessorIMod, getContext()),
4843 // Add the remaining tokens in the mnemonic.
4844 while (Next != StringRef::npos) {
4846 Next = Name.find('.', Start + 1);
4847 StringRef ExtraToken = Name.slice(Start, Next);
4849 // Some NEON instructions have an optional datatype suffix that is
4850 // completely ignored. Check for that.
4851 if (isDataTypeToken(ExtraToken) &&
4852 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
4855 if (ExtraToken != ".n") {
4856 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
4857 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
4861 // Read the remaining operands.
4862 if (getLexer().isNot(AsmToken::EndOfStatement)) {
4863 // Read the first operand.
4864 if (parseOperand(Operands, Mnemonic)) {
4865 Parser.EatToEndOfStatement();
4869 while (getLexer().is(AsmToken::Comma)) {
4870 Parser.Lex(); // Eat the comma.
4872 // Parse and remember the operand.
4873 if (parseOperand(Operands, Mnemonic)) {
4874 Parser.EatToEndOfStatement();
4880 if (getLexer().isNot(AsmToken::EndOfStatement)) {
4881 SMLoc Loc = getLexer().getLoc();
4882 Parser.EatToEndOfStatement();
4883 return Error(Loc, "unexpected token in argument list");
4886 Parser.Lex(); // Consume the EndOfStatement
4888 // Some instructions, mostly Thumb, have forms for the same mnemonic that
4889 // do and don't have a cc_out optional-def operand. With some spot-checks
4890 // of the operand list, we can figure out which variant we're trying to
4891 // parse and adjust accordingly before actually matching. We shouldn't ever
4892 // try to remove a cc_out operand that was explicitly set on the the
4893 // mnemonic, of course (CarrySetting == true). Reason number #317 the
4894 // table driven matcher doesn't fit well with the ARM instruction set.
4895 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
4896 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
4897 Operands.erase(Operands.begin() + 1);
4901 // ARM mode 'blx' need special handling, as the register operand version
4902 // is predicable, but the label operand version is not. So, we can't rely
4903 // on the Mnemonic based checking to correctly figure out when to put
4904 // a k_CondCode operand in the list. If we're trying to match the label
4905 // version, remove the k_CondCode operand here.
4906 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
4907 static_cast<ARMOperand*>(Operands[2])->isImm()) {
4908 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
4909 Operands.erase(Operands.begin() + 1);
4913 // The vector-compare-to-zero instructions have a literal token "#0" at
4914 // the end that comes to here as an immediate operand. Convert it to a
4915 // token to play nicely with the matcher.
4916 if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
4917 Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
4918 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4919 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
4920 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4921 if (CE && CE->getValue() == 0) {
4922 Operands.erase(Operands.begin() + 5);
4923 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4927 // VCMP{E} does the same thing, but with a different operand count.
4928 if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 &&
4929 static_cast<ARMOperand*>(Operands[4])->isImm()) {
4930 ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]);
4931 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4932 if (CE && CE->getValue() == 0) {
4933 Operands.erase(Operands.begin() + 4);
4934 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4938 // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
4939 // end. Convert it to a token here. Take care not to convert those
4940 // that should hit the Thumb2 encoding.
4941 if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
4942 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4943 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4944 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4945 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
4946 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4947 if (CE && CE->getValue() == 0 &&
4949 // The cc_out operand matches the IT block.
4950 ((inITBlock() != CarrySetting) &&
4951 // Neither register operand is a high register.
4952 (isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4953 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()))))){
4954 Operands.erase(Operands.begin() + 5);
4955 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4963 // Validate context-sensitive operand constraints.
4965 // return 'true' if register list contains non-low GPR registers,
4966 // 'false' otherwise. If Reg is in the register list or is HiReg, set
4967 // 'containsReg' to true.
4968 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
4969 unsigned HiReg, bool &containsReg) {
4970 containsReg = false;
4971 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
4972 unsigned OpReg = Inst.getOperand(i).getReg();
4975 // Anything other than a low register isn't legal here.
4976 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
4982 // Check if the specified regisgter is in the register list of the inst,
4983 // starting at the indicated operand number.
4984 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
4985 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
4986 unsigned OpReg = Inst.getOperand(i).getReg();
4993 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around
4994 // the ARMInsts array) instead. Getting that here requires awkward
4995 // API changes, though. Better way?
4997 extern const MCInstrDesc ARMInsts[];
4999 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
5000 return ARMInsts[Opcode];
5003 // FIXME: We would really like to be able to tablegen'erate this.
5005 validateInstruction(MCInst &Inst,
5006 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5007 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
5008 SMLoc Loc = Operands[0]->getStartLoc();
5009 // Check the IT block state first.
5010 // NOTE: In Thumb mode, the BKPT instruction has the interesting property of
5011 // being allowed in IT blocks, but not being predicable. It just always
5013 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT) {
5015 if (ITState.FirstCond)
5016 ITState.FirstCond = false;
5018 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5019 // The instruction must be predicable.
5020 if (!MCID.isPredicable())
5021 return Error(Loc, "instructions in IT block must be predicable");
5022 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5023 unsigned ITCond = bit ? ITState.Cond :
5024 ARMCC::getOppositeCondition(ITState.Cond);
5025 if (Cond != ITCond) {
5026 // Find the condition code Operand to get its SMLoc information.
5028 for (unsigned i = 1; i < Operands.size(); ++i)
5029 if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
5030 CondLoc = Operands[i]->getStartLoc();
5031 return Error(CondLoc, "incorrect condition in IT block; got '" +
5032 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5033 "', but expected '" +
5034 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5036 // Check for non-'al' condition codes outside of the IT block.
5037 } else if (isThumbTwo() && MCID.isPredicable() &&
5038 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5039 ARMCC::AL && Inst.getOpcode() != ARM::tB &&
5040 Inst.getOpcode() != ARM::t2B)
5041 return Error(Loc, "predicated instructions must be in IT block");
5043 switch (Inst.getOpcode()) {
5046 case ARM::LDRD_POST:
5048 // Rt2 must be Rt + 1.
5049 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
5050 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
5052 return Error(Operands[3]->getStartLoc(),
5053 "destination operands must be sequential");
5057 // Rt2 must be Rt + 1.
5058 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
5059 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
5061 return Error(Operands[3]->getStartLoc(),
5062 "source operands must be sequential");
5066 case ARM::STRD_POST:
5068 // Rt2 must be Rt + 1.
5069 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
5070 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
5072 return Error(Operands[3]->getStartLoc(),
5073 "source operands must be sequential");
5078 // width must be in range [1, 32-lsb]
5079 unsigned lsb = Inst.getOperand(2).getImm();
5080 unsigned widthm1 = Inst.getOperand(3).getImm();
5081 if (widthm1 >= 32 - lsb)
5082 return Error(Operands[5]->getStartLoc(),
5083 "bitfield width must be in range [1,32-lsb]");
5087 // If we're parsing Thumb2, the .w variant is available and handles
5088 // most cases that are normally illegal for a Thumb1 LDM
5089 // instruction. We'll make the transformation in processInstruction()
5092 // Thumb LDM instructions are writeback iff the base register is not
5093 // in the register list.
5094 unsigned Rn = Inst.getOperand(0).getReg();
5095 bool hasWritebackToken =
5096 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5097 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5098 bool listContainsBase;
5099 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
5100 return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
5101 "registers must be in range r0-r7");
5102 // If we should have writeback, then there should be a '!' token.
5103 if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
5104 return Error(Operands[2]->getStartLoc(),
5105 "writeback operator '!' expected");
5106 // If we should not have writeback, there must not be a '!'. This is
5107 // true even for the 32-bit wide encodings.
5108 if (listContainsBase && hasWritebackToken)
5109 return Error(Operands[3]->getStartLoc(),
5110 "writeback operator '!' not allowed when base register "
5111 "in register list");
5115 case ARM::t2LDMIA_UPD: {
5116 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5117 return Error(Operands[4]->getStartLoc(),
5118 "writeback operator '!' not allowed when base register "
5119 "in register list");
5122 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5123 // so only issue a diagnostic for thumb1. The instructions will be
5124 // switched to the t2 encodings in processInstruction() if necessary.
5126 bool listContainsBase;
5127 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
5129 return Error(Operands[2]->getStartLoc(),
5130 "registers must be in range r0-r7 or pc");
5134 bool listContainsBase;
5135 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
5137 return Error(Operands[2]->getStartLoc(),
5138 "registers must be in range r0-r7 or lr");
5141 case ARM::tSTMIA_UPD: {
5142 bool listContainsBase;
5143 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
5144 return Error(Operands[4]->getStartLoc(),
5145 "registers must be in range r0-r7");
5153 static unsigned getRealVSTLNOpcode(unsigned Opc, unsigned &Spacing) {
5155 default: assert(0 && "unexpected opcode!");
5157 case ARM::VST1LNdWB_fixed_Asm_8: case ARM::VST1LNdWB_fixed_Asm_P8:
5158 case ARM::VST1LNdWB_fixed_Asm_I8: case ARM::VST1LNdWB_fixed_Asm_S8:
5159 case ARM::VST1LNdWB_fixed_Asm_U8:
5161 return ARM::VST1LNd8_UPD;
5162 case ARM::VST1LNdWB_fixed_Asm_16: case ARM::VST1LNdWB_fixed_Asm_P16:
5163 case ARM::VST1LNdWB_fixed_Asm_I16: case ARM::VST1LNdWB_fixed_Asm_S16:
5164 case ARM::VST1LNdWB_fixed_Asm_U16:
5166 return ARM::VST1LNd16_UPD;
5167 case ARM::VST1LNdWB_fixed_Asm_32: case ARM::VST1LNdWB_fixed_Asm_F:
5168 case ARM::VST1LNdWB_fixed_Asm_F32: case ARM::VST1LNdWB_fixed_Asm_I32:
5169 case ARM::VST1LNdWB_fixed_Asm_S32: case ARM::VST1LNdWB_fixed_Asm_U32:
5171 return ARM::VST1LNd32_UPD;
5172 case ARM::VST1LNdWB_register_Asm_8: case ARM::VST1LNdWB_register_Asm_P8:
5173 case ARM::VST1LNdWB_register_Asm_I8: case ARM::VST1LNdWB_register_Asm_S8:
5174 case ARM::VST1LNdWB_register_Asm_U8:
5176 return ARM::VST1LNd8_UPD;
5177 case ARM::VST1LNdWB_register_Asm_16: case ARM::VST1LNdWB_register_Asm_P16:
5178 case ARM::VST1LNdWB_register_Asm_I16: case ARM::VST1LNdWB_register_Asm_S16:
5179 case ARM::VST1LNdWB_register_Asm_U16:
5181 return ARM::VST1LNd16_UPD;
5182 case ARM::VST1LNdWB_register_Asm_32: case ARM::VST1LNdWB_register_Asm_F:
5183 case ARM::VST1LNdWB_register_Asm_F32: case ARM::VST1LNdWB_register_Asm_I32:
5184 case ARM::VST1LNdWB_register_Asm_S32: case ARM::VST1LNdWB_register_Asm_U32:
5186 return ARM::VST1LNd32_UPD;
5187 case ARM::VST1LNdAsm_8: case ARM::VST1LNdAsm_P8:
5188 case ARM::VST1LNdAsm_I8: case ARM::VST1LNdAsm_S8:
5189 case ARM::VST1LNdAsm_U8:
5191 return ARM::VST1LNd8;
5192 case ARM::VST1LNdAsm_16: case ARM::VST1LNdAsm_P16:
5193 case ARM::VST1LNdAsm_I16: case ARM::VST1LNdAsm_S16:
5194 case ARM::VST1LNdAsm_U16:
5196 return ARM::VST1LNd16;
5197 case ARM::VST1LNdAsm_32: case ARM::VST1LNdAsm_F:
5198 case ARM::VST1LNdAsm_F32: case ARM::VST1LNdAsm_I32:
5199 case ARM::VST1LNdAsm_S32: case ARM::VST1LNdAsm_U32:
5201 return ARM::VST1LNd32;
5204 case ARM::VST2LNdWB_fixed_Asm_8: case ARM::VST2LNdWB_fixed_Asm_P8:
5205 case ARM::VST2LNdWB_fixed_Asm_I8: case ARM::VST2LNdWB_fixed_Asm_S8:
5206 case ARM::VST2LNdWB_fixed_Asm_U8:
5208 return ARM::VST2LNd8_UPD;
5209 case ARM::VST2LNdWB_fixed_Asm_16: case ARM::VST2LNdWB_fixed_Asm_P16:
5210 case ARM::VST2LNdWB_fixed_Asm_I16: case ARM::VST2LNdWB_fixed_Asm_S16:
5211 case ARM::VST2LNdWB_fixed_Asm_U16:
5213 return ARM::VST2LNd16_UPD;
5214 case ARM::VST2LNdWB_fixed_Asm_32: case ARM::VST2LNdWB_fixed_Asm_F:
5215 case ARM::VST2LNdWB_fixed_Asm_F32: case ARM::VST2LNdWB_fixed_Asm_I32:
5216 case ARM::VST2LNdWB_fixed_Asm_S32: case ARM::VST2LNdWB_fixed_Asm_U32:
5218 return ARM::VST2LNd32_UPD;
5219 case ARM::VST2LNqWB_fixed_Asm_16: case ARM::VST2LNqWB_fixed_Asm_P16:
5220 case ARM::VST2LNqWB_fixed_Asm_I16: case ARM::VST2LNqWB_fixed_Asm_S16:
5221 case ARM::VST2LNqWB_fixed_Asm_U16:
5223 return ARM::VST2LNq16_UPD;
5224 case ARM::VST2LNqWB_fixed_Asm_32: case ARM::VST2LNqWB_fixed_Asm_F:
5225 case ARM::VST2LNqWB_fixed_Asm_F32: case ARM::VST2LNqWB_fixed_Asm_I32:
5226 case ARM::VST2LNqWB_fixed_Asm_S32: case ARM::VST2LNqWB_fixed_Asm_U32:
5228 return ARM::VST2LNq32_UPD;
5230 case ARM::VST2LNdWB_register_Asm_8: case ARM::VST2LNdWB_register_Asm_P8:
5231 case ARM::VST2LNdWB_register_Asm_I8: case ARM::VST2LNdWB_register_Asm_S8:
5232 case ARM::VST2LNdWB_register_Asm_U8:
5234 return ARM::VST2LNd8_UPD;
5235 case ARM::VST2LNdWB_register_Asm_16: case ARM::VST2LNdWB_register_Asm_P16:
5236 case ARM::VST2LNdWB_register_Asm_I16: case ARM::VST2LNdWB_register_Asm_S16:
5237 case ARM::VST2LNdWB_register_Asm_U16:
5239 return ARM::VST2LNd16_UPD;
5240 case ARM::VST2LNdWB_register_Asm_32: case ARM::VST2LNdWB_register_Asm_F:
5241 case ARM::VST2LNdWB_register_Asm_F32: case ARM::VST2LNdWB_register_Asm_I32:
5242 case ARM::VST2LNdWB_register_Asm_S32: case ARM::VST2LNdWB_register_Asm_U32:
5244 return ARM::VST2LNd32_UPD;
5245 case ARM::VST2LNqWB_register_Asm_16: case ARM::VST2LNqWB_register_Asm_P16:
5246 case ARM::VST2LNqWB_register_Asm_I16: case ARM::VST2LNqWB_register_Asm_S16:
5247 case ARM::VST2LNqWB_register_Asm_U16:
5249 return ARM::VST2LNq16_UPD;
5250 case ARM::VST2LNqWB_register_Asm_32: case ARM::VST2LNqWB_register_Asm_F:
5251 case ARM::VST2LNqWB_register_Asm_F32: case ARM::VST2LNqWB_register_Asm_I32:
5252 case ARM::VST2LNqWB_register_Asm_S32: case ARM::VST2LNqWB_register_Asm_U32:
5254 return ARM::VST2LNq32_UPD;
5256 case ARM::VST2LNdAsm_8: case ARM::VST2LNdAsm_P8:
5257 case ARM::VST2LNdAsm_I8: case ARM::VST2LNdAsm_S8:
5258 case ARM::VST2LNdAsm_U8:
5260 return ARM::VST2LNd8;
5261 case ARM::VST2LNdAsm_16: case ARM::VST2LNdAsm_P16:
5262 case ARM::VST2LNdAsm_I16: case ARM::VST2LNdAsm_S16:
5263 case ARM::VST2LNdAsm_U16:
5265 return ARM::VST2LNd16;
5266 case ARM::VST2LNdAsm_32: case ARM::VST2LNdAsm_F:
5267 case ARM::VST2LNdAsm_F32: case ARM::VST2LNdAsm_I32:
5268 case ARM::VST2LNdAsm_S32: case ARM::VST2LNdAsm_U32:
5270 return ARM::VST2LNd32;
5271 case ARM::VST2LNqAsm_16: case ARM::VST2LNqAsm_P16:
5272 case ARM::VST2LNqAsm_I16: case ARM::VST2LNqAsm_S16:
5273 case ARM::VST2LNqAsm_U16:
5275 return ARM::VST2LNq16;
5276 case ARM::VST2LNqAsm_32: case ARM::VST2LNqAsm_F:
5277 case ARM::VST2LNqAsm_F32: case ARM::VST2LNqAsm_I32:
5278 case ARM::VST2LNqAsm_S32: case ARM::VST2LNqAsm_U32:
5280 return ARM::VST2LNq32;
5284 static unsigned getRealVLDLNOpcode(unsigned Opc, unsigned &Spacing) {
5286 default: assert(0 && "unexpected opcode!");
5288 case ARM::VLD1LNdWB_fixed_Asm_8: case ARM::VLD1LNdWB_fixed_Asm_P8:
5289 case ARM::VLD1LNdWB_fixed_Asm_I8: case ARM::VLD1LNdWB_fixed_Asm_S8:
5290 case ARM::VLD1LNdWB_fixed_Asm_U8:
5292 return ARM::VLD1LNd8_UPD;
5293 case ARM::VLD1LNdWB_fixed_Asm_16: case ARM::VLD1LNdWB_fixed_Asm_P16:
5294 case ARM::VLD1LNdWB_fixed_Asm_I16: case ARM::VLD1LNdWB_fixed_Asm_S16:
5295 case ARM::VLD1LNdWB_fixed_Asm_U16:
5297 return ARM::VLD1LNd16_UPD;
5298 case ARM::VLD1LNdWB_fixed_Asm_32: case ARM::VLD1LNdWB_fixed_Asm_F:
5299 case ARM::VLD1LNdWB_fixed_Asm_F32: case ARM::VLD1LNdWB_fixed_Asm_I32:
5300 case ARM::VLD1LNdWB_fixed_Asm_S32: case ARM::VLD1LNdWB_fixed_Asm_U32:
5302 return ARM::VLD1LNd32_UPD;
5303 case ARM::VLD1LNdWB_register_Asm_8: case ARM::VLD1LNdWB_register_Asm_P8:
5304 case ARM::VLD1LNdWB_register_Asm_I8: case ARM::VLD1LNdWB_register_Asm_S8:
5305 case ARM::VLD1LNdWB_register_Asm_U8:
5307 return ARM::VLD1LNd8_UPD;
5308 case ARM::VLD1LNdWB_register_Asm_16: case ARM::VLD1LNdWB_register_Asm_P16:
5309 case ARM::VLD1LNdWB_register_Asm_I16: case ARM::VLD1LNdWB_register_Asm_S16:
5310 case ARM::VLD1LNdWB_register_Asm_U16:
5312 return ARM::VLD1LNd16_UPD;
5313 case ARM::VLD1LNdWB_register_Asm_32: case ARM::VLD1LNdWB_register_Asm_F:
5314 case ARM::VLD1LNdWB_register_Asm_F32: case ARM::VLD1LNdWB_register_Asm_I32:
5315 case ARM::VLD1LNdWB_register_Asm_S32: case ARM::VLD1LNdWB_register_Asm_U32:
5317 return ARM::VLD1LNd32_UPD;
5318 case ARM::VLD1LNdAsm_8: case ARM::VLD1LNdAsm_P8:
5319 case ARM::VLD1LNdAsm_I8: case ARM::VLD1LNdAsm_S8:
5320 case ARM::VLD1LNdAsm_U8:
5322 return ARM::VLD1LNd8;
5323 case ARM::VLD1LNdAsm_16: case ARM::VLD1LNdAsm_P16:
5324 case ARM::VLD1LNdAsm_I16: case ARM::VLD1LNdAsm_S16:
5325 case ARM::VLD1LNdAsm_U16:
5327 return ARM::VLD1LNd16;
5328 case ARM::VLD1LNdAsm_32: case ARM::VLD1LNdAsm_F:
5329 case ARM::VLD1LNdAsm_F32: case ARM::VLD1LNdAsm_I32:
5330 case ARM::VLD1LNdAsm_S32: case ARM::VLD1LNdAsm_U32:
5332 return ARM::VLD1LNd32;
5335 case ARM::VLD2LNdWB_fixed_Asm_8: case ARM::VLD2LNdWB_fixed_Asm_P8:
5336 case ARM::VLD2LNdWB_fixed_Asm_I8: case ARM::VLD2LNdWB_fixed_Asm_S8:
5337 case ARM::VLD2LNdWB_fixed_Asm_U8:
5339 return ARM::VLD2LNd8_UPD;
5340 case ARM::VLD2LNdWB_fixed_Asm_16: case ARM::VLD2LNdWB_fixed_Asm_P16:
5341 case ARM::VLD2LNdWB_fixed_Asm_I16: case ARM::VLD2LNdWB_fixed_Asm_S16:
5342 case ARM::VLD2LNdWB_fixed_Asm_U16:
5344 return ARM::VLD2LNd16_UPD;
5345 case ARM::VLD2LNdWB_fixed_Asm_32: case ARM::VLD2LNdWB_fixed_Asm_F:
5346 case ARM::VLD2LNdWB_fixed_Asm_F32: case ARM::VLD2LNdWB_fixed_Asm_I32:
5347 case ARM::VLD2LNdWB_fixed_Asm_S32: case ARM::VLD2LNdWB_fixed_Asm_U32:
5349 return ARM::VLD2LNd32_UPD;
5350 case ARM::VLD2LNqWB_fixed_Asm_16: case ARM::VLD2LNqWB_fixed_Asm_P16:
5351 case ARM::VLD2LNqWB_fixed_Asm_I16: case ARM::VLD2LNqWB_fixed_Asm_S16:
5352 case ARM::VLD2LNqWB_fixed_Asm_U16:
5354 return ARM::VLD2LNq16_UPD;
5355 case ARM::VLD2LNqWB_fixed_Asm_32: case ARM::VLD2LNqWB_fixed_Asm_F:
5356 case ARM::VLD2LNqWB_fixed_Asm_F32: case ARM::VLD2LNqWB_fixed_Asm_I32:
5357 case ARM::VLD2LNqWB_fixed_Asm_S32: case ARM::VLD2LNqWB_fixed_Asm_U32:
5359 return ARM::VLD2LNq32_UPD;
5360 case ARM::VLD2LNdWB_register_Asm_8: case ARM::VLD2LNdWB_register_Asm_P8:
5361 case ARM::VLD2LNdWB_register_Asm_I8: case ARM::VLD2LNdWB_register_Asm_S8:
5362 case ARM::VLD2LNdWB_register_Asm_U8:
5364 return ARM::VLD2LNd8_UPD;
5365 case ARM::VLD2LNdWB_register_Asm_16: case ARM::VLD2LNdWB_register_Asm_P16:
5366 case ARM::VLD2LNdWB_register_Asm_I16: case ARM::VLD2LNdWB_register_Asm_S16:
5367 case ARM::VLD2LNdWB_register_Asm_U16:
5369 return ARM::VLD2LNd16_UPD;
5370 case ARM::VLD2LNdWB_register_Asm_32: case ARM::VLD2LNdWB_register_Asm_F:
5371 case ARM::VLD2LNdWB_register_Asm_F32: case ARM::VLD2LNdWB_register_Asm_I32:
5372 case ARM::VLD2LNdWB_register_Asm_S32: case ARM::VLD2LNdWB_register_Asm_U32:
5374 return ARM::VLD2LNd32_UPD;
5375 case ARM::VLD2LNqWB_register_Asm_16: case ARM::VLD2LNqWB_register_Asm_P16:
5376 case ARM::VLD2LNqWB_register_Asm_I16: case ARM::VLD2LNqWB_register_Asm_S16:
5377 case ARM::VLD2LNqWB_register_Asm_U16:
5379 return ARM::VLD2LNq16_UPD;
5380 case ARM::VLD2LNqWB_register_Asm_32: case ARM::VLD2LNqWB_register_Asm_F:
5381 case ARM::VLD2LNqWB_register_Asm_F32: case ARM::VLD2LNqWB_register_Asm_I32:
5382 case ARM::VLD2LNqWB_register_Asm_S32: case ARM::VLD2LNqWB_register_Asm_U32:
5384 return ARM::VLD2LNq32_UPD;
5385 case ARM::VLD2LNdAsm_8: case ARM::VLD2LNdAsm_P8:
5386 case ARM::VLD2LNdAsm_I8: case ARM::VLD2LNdAsm_S8:
5387 case ARM::VLD2LNdAsm_U8:
5389 return ARM::VLD2LNd8;
5390 case ARM::VLD2LNdAsm_16: case ARM::VLD2LNdAsm_P16:
5391 case ARM::VLD2LNdAsm_I16: case ARM::VLD2LNdAsm_S16:
5392 case ARM::VLD2LNdAsm_U16:
5394 return ARM::VLD2LNd16;
5395 case ARM::VLD2LNdAsm_32: case ARM::VLD2LNdAsm_F:
5396 case ARM::VLD2LNdAsm_F32: case ARM::VLD2LNdAsm_I32:
5397 case ARM::VLD2LNdAsm_S32: case ARM::VLD2LNdAsm_U32:
5399 return ARM::VLD2LNd32;
5400 case ARM::VLD2LNqAsm_16: case ARM::VLD2LNqAsm_P16:
5401 case ARM::VLD2LNqAsm_I16: case ARM::VLD2LNqAsm_S16:
5402 case ARM::VLD2LNqAsm_U16:
5404 return ARM::VLD2LNq16;
5405 case ARM::VLD2LNqAsm_32: case ARM::VLD2LNqAsm_F:
5406 case ARM::VLD2LNqAsm_F32: case ARM::VLD2LNqAsm_I32:
5407 case ARM::VLD2LNqAsm_S32: case ARM::VLD2LNqAsm_U32:
5409 return ARM::VLD2LNq32;
5414 processInstruction(MCInst &Inst,
5415 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5416 switch (Inst.getOpcode()) {
5417 // Handle NEON VST complex aliases.
5418 case ARM::VST1LNdWB_register_Asm_8: case ARM::VST1LNdWB_register_Asm_P8:
5419 case ARM::VST1LNdWB_register_Asm_I8: case ARM::VST1LNdWB_register_Asm_S8:
5420 case ARM::VST1LNdWB_register_Asm_U8: case ARM::VST1LNdWB_register_Asm_16:
5421 case ARM::VST1LNdWB_register_Asm_P16: case ARM::VST1LNdWB_register_Asm_I16:
5422 case ARM::VST1LNdWB_register_Asm_S16: case ARM::VST1LNdWB_register_Asm_U16:
5423 case ARM::VST1LNdWB_register_Asm_32: case ARM::VST1LNdWB_register_Asm_F:
5424 case ARM::VST1LNdWB_register_Asm_F32: case ARM::VST1LNdWB_register_Asm_I32:
5425 case ARM::VST1LNdWB_register_Asm_S32: case ARM::VST1LNdWB_register_Asm_U32: {
5427 // Shuffle the operands around so the lane index operand is in the
5430 TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing));
5431 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5432 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5433 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5434 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5435 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5436 TmpInst.addOperand(Inst.getOperand(1)); // lane
5437 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5438 TmpInst.addOperand(Inst.getOperand(6));
5443 case ARM::VST2LNdWB_register_Asm_8: case ARM::VST2LNdWB_register_Asm_P8:
5444 case ARM::VST2LNdWB_register_Asm_I8: case ARM::VST2LNdWB_register_Asm_S8:
5445 case ARM::VST2LNdWB_register_Asm_U8: case ARM::VST2LNdWB_register_Asm_16:
5446 case ARM::VST2LNdWB_register_Asm_P16: case ARM::VST2LNdWB_register_Asm_I16:
5447 case ARM::VST2LNdWB_register_Asm_S16: case ARM::VST2LNdWB_register_Asm_U16:
5448 case ARM::VST2LNdWB_register_Asm_32: case ARM::VST2LNdWB_register_Asm_F:
5449 case ARM::VST2LNdWB_register_Asm_F32: case ARM::VST2LNdWB_register_Asm_I32:
5450 case ARM::VST2LNdWB_register_Asm_S32: case ARM::VST2LNdWB_register_Asm_U32:
5451 case ARM::VST2LNqWB_register_Asm_16: case ARM::VST2LNqWB_register_Asm_P16:
5452 case ARM::VST2LNqWB_register_Asm_I16: case ARM::VST2LNqWB_register_Asm_S16:
5453 case ARM::VST2LNqWB_register_Asm_U16: case ARM::VST2LNqWB_register_Asm_32:
5454 case ARM::VST2LNqWB_register_Asm_F: case ARM::VST2LNqWB_register_Asm_F32:
5455 case ARM::VST2LNqWB_register_Asm_I32: case ARM::VST2LNqWB_register_Asm_S32:
5456 case ARM::VST2LNqWB_register_Asm_U32: {
5458 // Shuffle the operands around so the lane index operand is in the
5461 TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing));
5462 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5463 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5464 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5465 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5466 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5467 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5469 TmpInst.addOperand(Inst.getOperand(1)); // lane
5470 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5471 TmpInst.addOperand(Inst.getOperand(6));
5475 case ARM::VST1LNdWB_fixed_Asm_8: case ARM::VST1LNdWB_fixed_Asm_P8:
5476 case ARM::VST1LNdWB_fixed_Asm_I8: case ARM::VST1LNdWB_fixed_Asm_S8:
5477 case ARM::VST1LNdWB_fixed_Asm_U8: case ARM::VST1LNdWB_fixed_Asm_16:
5478 case ARM::VST1LNdWB_fixed_Asm_P16: case ARM::VST1LNdWB_fixed_Asm_I16:
5479 case ARM::VST1LNdWB_fixed_Asm_S16: case ARM::VST1LNdWB_fixed_Asm_U16:
5480 case ARM::VST1LNdWB_fixed_Asm_32: case ARM::VST1LNdWB_fixed_Asm_F:
5481 case ARM::VST1LNdWB_fixed_Asm_F32: case ARM::VST1LNdWB_fixed_Asm_I32:
5482 case ARM::VST1LNdWB_fixed_Asm_S32: case ARM::VST1LNdWB_fixed_Asm_U32: {
5484 // Shuffle the operands around so the lane index operand is in the
5487 TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing));
5488 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5489 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5490 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5491 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5492 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5493 TmpInst.addOperand(Inst.getOperand(1)); // lane
5494 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5495 TmpInst.addOperand(Inst.getOperand(5));
5500 case ARM::VST2LNdWB_fixed_Asm_8: case ARM::VST2LNdWB_fixed_Asm_P8:
5501 case ARM::VST2LNdWB_fixed_Asm_I8: case ARM::VST2LNdWB_fixed_Asm_S8:
5502 case ARM::VST2LNdWB_fixed_Asm_U8: case ARM::VST2LNdWB_fixed_Asm_16:
5503 case ARM::VST2LNdWB_fixed_Asm_P16: case ARM::VST2LNdWB_fixed_Asm_I16:
5504 case ARM::VST2LNdWB_fixed_Asm_S16: case ARM::VST2LNdWB_fixed_Asm_U16:
5505 case ARM::VST2LNdWB_fixed_Asm_32: case ARM::VST2LNdWB_fixed_Asm_F:
5506 case ARM::VST2LNdWB_fixed_Asm_F32: case ARM::VST2LNdWB_fixed_Asm_I32:
5507 case ARM::VST2LNdWB_fixed_Asm_S32: case ARM::VST2LNdWB_fixed_Asm_U32:
5508 case ARM::VST2LNqWB_fixed_Asm_16: case ARM::VST2LNqWB_fixed_Asm_P16:
5509 case ARM::VST2LNqWB_fixed_Asm_I16: case ARM::VST2LNqWB_fixed_Asm_S16:
5510 case ARM::VST2LNqWB_fixed_Asm_U16: case ARM::VST2LNqWB_fixed_Asm_32:
5511 case ARM::VST2LNqWB_fixed_Asm_F: case ARM::VST2LNqWB_fixed_Asm_F32:
5512 case ARM::VST2LNqWB_fixed_Asm_I32: case ARM::VST2LNqWB_fixed_Asm_S32:
5513 case ARM::VST2LNqWB_fixed_Asm_U32: {
5515 // Shuffle the operands around so the lane index operand is in the
5518 TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing));
5519 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5520 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5521 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5522 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5523 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5524 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5526 TmpInst.addOperand(Inst.getOperand(1)); // lane
5527 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5528 TmpInst.addOperand(Inst.getOperand(5));
5532 case ARM::VST1LNdAsm_8: case ARM::VST1LNdAsm_P8: case ARM::VST1LNdAsm_I8:
5533 case ARM::VST1LNdAsm_S8: case ARM::VST1LNdAsm_U8: case ARM::VST1LNdAsm_16:
5534 case ARM::VST1LNdAsm_P16: case ARM::VST1LNdAsm_I16: case ARM::VST1LNdAsm_S16:
5535 case ARM::VST1LNdAsm_U16: case ARM::VST1LNdAsm_32: case ARM::VST1LNdAsm_F:
5536 case ARM::VST1LNdAsm_F32: case ARM::VST1LNdAsm_I32: case ARM::VST1LNdAsm_S32:
5537 case ARM::VST1LNdAsm_U32: {
5539 // Shuffle the operands around so the lane index operand is in the
5542 TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing));
5543 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5544 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5545 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5546 TmpInst.addOperand(Inst.getOperand(1)); // lane
5547 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5548 TmpInst.addOperand(Inst.getOperand(5));
5553 case ARM::VST2LNdAsm_8: case ARM::VST2LNdAsm_P8: case ARM::VST2LNdAsm_I8:
5554 case ARM::VST2LNdAsm_S8: case ARM::VST2LNdAsm_U8: case ARM::VST2LNdAsm_16:
5555 case ARM::VST2LNdAsm_P16: case ARM::VST2LNdAsm_I16: case ARM::VST2LNdAsm_S16:
5556 case ARM::VST2LNdAsm_U16: case ARM::VST2LNdAsm_32: case ARM::VST2LNdAsm_F:
5557 case ARM::VST2LNdAsm_F32: case ARM::VST2LNdAsm_I32: case ARM::VST2LNdAsm_S32:
5558 case ARM::VST2LNdAsm_U32: case ARM::VST2LNqAsm_16: case ARM::VST2LNqAsm_P16:
5559 case ARM::VST2LNqAsm_I16: case ARM::VST2LNqAsm_S16: case ARM::VST2LNqAsm_U16:
5560 case ARM::VST2LNqAsm_32: case ARM::VST2LNqAsm_F: case ARM::VST2LNqAsm_F32:
5561 case ARM::VST2LNqAsm_I32: case ARM::VST2LNqAsm_S32: case ARM::VST2LNqAsm_U32:{
5563 // Shuffle the operands around so the lane index operand is in the
5566 TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode(), Spacing));
5567 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5568 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5569 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5570 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5572 TmpInst.addOperand(Inst.getOperand(1)); // lane
5573 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5574 TmpInst.addOperand(Inst.getOperand(5));
5578 // Handle NEON VLD complex aliases.
5579 case ARM::VLD1LNdWB_register_Asm_8: case ARM::VLD1LNdWB_register_Asm_P8:
5580 case ARM::VLD1LNdWB_register_Asm_I8: case ARM::VLD1LNdWB_register_Asm_S8:
5581 case ARM::VLD1LNdWB_register_Asm_U8: case ARM::VLD1LNdWB_register_Asm_16:
5582 case ARM::VLD1LNdWB_register_Asm_P16: case ARM::VLD1LNdWB_register_Asm_I16:
5583 case ARM::VLD1LNdWB_register_Asm_S16: case ARM::VLD1LNdWB_register_Asm_U16:
5584 case ARM::VLD1LNdWB_register_Asm_32: case ARM::VLD1LNdWB_register_Asm_F:
5585 case ARM::VLD1LNdWB_register_Asm_F32: case ARM::VLD1LNdWB_register_Asm_I32:
5586 case ARM::VLD1LNdWB_register_Asm_S32: case ARM::VLD1LNdWB_register_Asm_U32: {
5588 // Shuffle the operands around so the lane index operand is in the
5591 TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing));
5592 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5593 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5594 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5595 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5596 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5597 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5598 TmpInst.addOperand(Inst.getOperand(1)); // lane
5599 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5600 TmpInst.addOperand(Inst.getOperand(6));
5605 case ARM::VLD2LNdWB_register_Asm_8: case ARM::VLD2LNdWB_register_Asm_P8:
5606 case ARM::VLD2LNdWB_register_Asm_I8: case ARM::VLD2LNdWB_register_Asm_S8:
5607 case ARM::VLD2LNdWB_register_Asm_U8: case ARM::VLD2LNdWB_register_Asm_16:
5608 case ARM::VLD2LNdWB_register_Asm_P16: case ARM::VLD2LNdWB_register_Asm_I16:
5609 case ARM::VLD2LNdWB_register_Asm_S16: case ARM::VLD2LNdWB_register_Asm_U16:
5610 case ARM::VLD2LNdWB_register_Asm_32: case ARM::VLD2LNdWB_register_Asm_F:
5611 case ARM::VLD2LNdWB_register_Asm_F32: case ARM::VLD2LNdWB_register_Asm_I32:
5612 case ARM::VLD2LNdWB_register_Asm_S32: case ARM::VLD2LNdWB_register_Asm_U32:
5613 case ARM::VLD2LNqWB_register_Asm_16: case ARM::VLD2LNqWB_register_Asm_P16:
5614 case ARM::VLD2LNqWB_register_Asm_I16: case ARM::VLD2LNqWB_register_Asm_S16:
5615 case ARM::VLD2LNqWB_register_Asm_U16: case ARM::VLD2LNqWB_register_Asm_32:
5616 case ARM::VLD2LNqWB_register_Asm_F: case ARM::VLD2LNqWB_register_Asm_F32:
5617 case ARM::VLD2LNqWB_register_Asm_I32: case ARM::VLD2LNqWB_register_Asm_S32:
5618 case ARM::VLD2LNqWB_register_Asm_U32: {
5620 // Shuffle the operands around so the lane index operand is in the
5623 TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing));
5624 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5625 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5627 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5628 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5629 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5630 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5631 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5632 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5634 TmpInst.addOperand(Inst.getOperand(1)); // lane
5635 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5636 TmpInst.addOperand(Inst.getOperand(6));
5641 case ARM::VLD1LNdWB_fixed_Asm_8: case ARM::VLD1LNdWB_fixed_Asm_P8:
5642 case ARM::VLD1LNdWB_fixed_Asm_I8: case ARM::VLD1LNdWB_fixed_Asm_S8:
5643 case ARM::VLD1LNdWB_fixed_Asm_U8: case ARM::VLD1LNdWB_fixed_Asm_16:
5644 case ARM::VLD1LNdWB_fixed_Asm_P16: case ARM::VLD1LNdWB_fixed_Asm_I16:
5645 case ARM::VLD1LNdWB_fixed_Asm_S16: case ARM::VLD1LNdWB_fixed_Asm_U16:
5646 case ARM::VLD1LNdWB_fixed_Asm_32: case ARM::VLD1LNdWB_fixed_Asm_F:
5647 case ARM::VLD1LNdWB_fixed_Asm_F32: case ARM::VLD1LNdWB_fixed_Asm_I32:
5648 case ARM::VLD1LNdWB_fixed_Asm_S32: case ARM::VLD1LNdWB_fixed_Asm_U32: {
5650 // Shuffle the operands around so the lane index operand is in the
5653 TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing));
5654 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5655 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5656 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5657 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5658 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5659 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5660 TmpInst.addOperand(Inst.getOperand(1)); // lane
5661 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5662 TmpInst.addOperand(Inst.getOperand(5));
5667 case ARM::VLD2LNdWB_fixed_Asm_8: case ARM::VLD2LNdWB_fixed_Asm_P8:
5668 case ARM::VLD2LNdWB_fixed_Asm_I8: case ARM::VLD2LNdWB_fixed_Asm_S8:
5669 case ARM::VLD2LNdWB_fixed_Asm_U8: case ARM::VLD2LNdWB_fixed_Asm_16:
5670 case ARM::VLD2LNdWB_fixed_Asm_P16: case ARM::VLD2LNdWB_fixed_Asm_I16:
5671 case ARM::VLD2LNdWB_fixed_Asm_S16: case ARM::VLD2LNdWB_fixed_Asm_U16:
5672 case ARM::VLD2LNdWB_fixed_Asm_32: case ARM::VLD2LNdWB_fixed_Asm_F:
5673 case ARM::VLD2LNdWB_fixed_Asm_F32: case ARM::VLD2LNdWB_fixed_Asm_I32:
5674 case ARM::VLD2LNdWB_fixed_Asm_S32: case ARM::VLD2LNdWB_fixed_Asm_U32:
5675 case ARM::VLD2LNqWB_fixed_Asm_16: case ARM::VLD2LNqWB_fixed_Asm_P16:
5676 case ARM::VLD2LNqWB_fixed_Asm_I16: case ARM::VLD2LNqWB_fixed_Asm_S16:
5677 case ARM::VLD2LNqWB_fixed_Asm_U16: case ARM::VLD2LNqWB_fixed_Asm_32:
5678 case ARM::VLD2LNqWB_fixed_Asm_F: case ARM::VLD2LNqWB_fixed_Asm_F32:
5679 case ARM::VLD2LNqWB_fixed_Asm_I32: case ARM::VLD2LNqWB_fixed_Asm_S32:
5680 case ARM::VLD2LNqWB_fixed_Asm_U32: {
5682 // Shuffle the operands around so the lane index operand is in the
5685 TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing));
5686 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5687 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5689 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5690 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5691 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5692 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5693 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5694 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5696 TmpInst.addOperand(Inst.getOperand(1)); // lane
5697 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5698 TmpInst.addOperand(Inst.getOperand(5));
5703 case ARM::VLD1LNdAsm_8: case ARM::VLD1LNdAsm_P8: case ARM::VLD1LNdAsm_I8:
5704 case ARM::VLD1LNdAsm_S8: case ARM::VLD1LNdAsm_U8: case ARM::VLD1LNdAsm_16:
5705 case ARM::VLD1LNdAsm_P16: case ARM::VLD1LNdAsm_I16: case ARM::VLD1LNdAsm_S16:
5706 case ARM::VLD1LNdAsm_U16: case ARM::VLD1LNdAsm_32: case ARM::VLD1LNdAsm_F:
5707 case ARM::VLD1LNdAsm_F32: case ARM::VLD1LNdAsm_I32: case ARM::VLD1LNdAsm_S32:
5708 case ARM::VLD1LNdAsm_U32: {
5710 // Shuffle the operands around so the lane index operand is in the
5713 TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing));
5714 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5715 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5716 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5717 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5718 TmpInst.addOperand(Inst.getOperand(1)); // lane
5719 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5720 TmpInst.addOperand(Inst.getOperand(5));
5725 case ARM::VLD2LNdAsm_8: case ARM::VLD2LNdAsm_P8: case ARM::VLD2LNdAsm_I8:
5726 case ARM::VLD2LNdAsm_S8: case ARM::VLD2LNdAsm_U8: case ARM::VLD2LNdAsm_16:
5727 case ARM::VLD2LNdAsm_P16: case ARM::VLD2LNdAsm_I16: case ARM::VLD2LNdAsm_S16:
5728 case ARM::VLD2LNdAsm_U16: case ARM::VLD2LNdAsm_32: case ARM::VLD2LNdAsm_F:
5729 case ARM::VLD2LNdAsm_F32: case ARM::VLD2LNdAsm_I32: case ARM::VLD2LNdAsm_S32:
5730 case ARM::VLD2LNdAsm_U32: case ARM::VLD2LNqAsm_16: case ARM::VLD2LNqAsm_P16:
5731 case ARM::VLD2LNqAsm_I16: case ARM::VLD2LNqAsm_S16: case ARM::VLD2LNqAsm_U16:
5732 case ARM::VLD2LNqAsm_32: case ARM::VLD2LNqAsm_F: case ARM::VLD2LNqAsm_F32:
5733 case ARM::VLD2LNqAsm_I32: case ARM::VLD2LNqAsm_S32:
5734 case ARM::VLD2LNqAsm_U32: {
5736 // Shuffle the operands around so the lane index operand is in the
5739 TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode(), Spacing));
5740 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5741 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5743 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5744 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5745 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5746 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5748 TmpInst.addOperand(Inst.getOperand(1)); // lane
5749 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5750 TmpInst.addOperand(Inst.getOperand(5));
5754 // Handle the Thumb2 mode MOV complex aliases.
5756 case ARM::t2MOVSsr: {
5757 // Which instruction to expand to depends on the CCOut operand and
5758 // whether we're in an IT block if the register operands are low
5760 bool isNarrow = false;
5761 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
5762 isARMLowRegister(Inst.getOperand(1).getReg()) &&
5763 isARMLowRegister(Inst.getOperand(2).getReg()) &&
5764 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
5765 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
5769 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
5770 default: llvm_unreachable("unexpected opcode!");
5771 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
5772 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
5773 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
5774 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
5776 TmpInst.setOpcode(newOpc);
5777 TmpInst.addOperand(Inst.getOperand(0)); // Rd
5779 TmpInst.addOperand(MCOperand::CreateReg(
5780 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
5781 TmpInst.addOperand(Inst.getOperand(1)); // Rn
5782 TmpInst.addOperand(Inst.getOperand(2)); // Rm
5783 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5784 TmpInst.addOperand(Inst.getOperand(5));
5786 TmpInst.addOperand(MCOperand::CreateReg(
5787 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
5792 case ARM::t2MOVSsi: {
5793 // Which instruction to expand to depends on the CCOut operand and
5794 // whether we're in an IT block if the register operands are low
5796 bool isNarrow = false;
5797 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
5798 isARMLowRegister(Inst.getOperand(1).getReg()) &&
5799 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
5803 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
5804 default: llvm_unreachable("unexpected opcode!");
5805 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
5806 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
5807 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
5808 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
5809 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
5811 unsigned Ammount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
5812 if (Ammount == 32) Ammount = 0;
5813 TmpInst.setOpcode(newOpc);
5814 TmpInst.addOperand(Inst.getOperand(0)); // Rd
5816 TmpInst.addOperand(MCOperand::CreateReg(
5817 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
5818 TmpInst.addOperand(Inst.getOperand(1)); // Rn
5819 if (newOpc != ARM::t2RRX)
5820 TmpInst.addOperand(MCOperand::CreateImm(Ammount));
5821 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
5822 TmpInst.addOperand(Inst.getOperand(4));
5824 TmpInst.addOperand(MCOperand::CreateReg(
5825 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
5829 // Handle the ARM mode MOV complex aliases.
5834 ARM_AM::ShiftOpc ShiftTy;
5835 switch(Inst.getOpcode()) {
5836 default: llvm_unreachable("unexpected opcode!");
5837 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
5838 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
5839 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
5840 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
5842 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
5844 TmpInst.setOpcode(ARM::MOVsr);
5845 TmpInst.addOperand(Inst.getOperand(0)); // Rd
5846 TmpInst.addOperand(Inst.getOperand(1)); // Rn
5847 TmpInst.addOperand(Inst.getOperand(2)); // Rm
5848 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
5849 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
5850 TmpInst.addOperand(Inst.getOperand(4));
5851 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
5859 ARM_AM::ShiftOpc ShiftTy;
5860 switch(Inst.getOpcode()) {
5861 default: llvm_unreachable("unexpected opcode!");
5862 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
5863 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
5864 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
5865 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
5867 // A shift by zero is a plain MOVr, not a MOVsi.
5868 unsigned Amt = Inst.getOperand(2).getImm();
5869 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
5870 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
5872 TmpInst.setOpcode(Opc);
5873 TmpInst.addOperand(Inst.getOperand(0)); // Rd
5874 TmpInst.addOperand(Inst.getOperand(1)); // Rn
5875 if (Opc == ARM::MOVsi)
5876 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
5877 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
5878 TmpInst.addOperand(Inst.getOperand(4));
5879 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
5884 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
5886 TmpInst.setOpcode(ARM::MOVsi);
5887 TmpInst.addOperand(Inst.getOperand(0)); // Rd
5888 TmpInst.addOperand(Inst.getOperand(1)); // Rn
5889 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
5890 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
5891 TmpInst.addOperand(Inst.getOperand(3));
5892 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
5896 case ARM::t2LDMIA_UPD: {
5897 // If this is a load of a single register, then we should use
5898 // a post-indexed LDR instruction instead, per the ARM ARM.
5899 if (Inst.getNumOperands() != 5)
5902 TmpInst.setOpcode(ARM::t2LDR_POST);
5903 TmpInst.addOperand(Inst.getOperand(4)); // Rt
5904 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
5905 TmpInst.addOperand(Inst.getOperand(1)); // Rn
5906 TmpInst.addOperand(MCOperand::CreateImm(4));
5907 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
5908 TmpInst.addOperand(Inst.getOperand(3));
5912 case ARM::t2STMDB_UPD: {
5913 // If this is a store of a single register, then we should use
5914 // a pre-indexed STR instruction instead, per the ARM ARM.
5915 if (Inst.getNumOperands() != 5)
5918 TmpInst.setOpcode(ARM::t2STR_PRE);
5919 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
5920 TmpInst.addOperand(Inst.getOperand(4)); // Rt
5921 TmpInst.addOperand(Inst.getOperand(1)); // Rn
5922 TmpInst.addOperand(MCOperand::CreateImm(-4));
5923 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
5924 TmpInst.addOperand(Inst.getOperand(3));
5928 case ARM::LDMIA_UPD:
5929 // If this is a load of a single register via a 'pop', then we should use
5930 // a post-indexed LDR instruction instead, per the ARM ARM.
5931 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
5932 Inst.getNumOperands() == 5) {
5934 TmpInst.setOpcode(ARM::LDR_POST_IMM);
5935 TmpInst.addOperand(Inst.getOperand(4)); // Rt
5936 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
5937 TmpInst.addOperand(Inst.getOperand(1)); // Rn
5938 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
5939 TmpInst.addOperand(MCOperand::CreateImm(4));
5940 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
5941 TmpInst.addOperand(Inst.getOperand(3));
5946 case ARM::STMDB_UPD:
5947 // If this is a store of a single register via a 'push', then we should use
5948 // a pre-indexed STR instruction instead, per the ARM ARM.
5949 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
5950 Inst.getNumOperands() == 5) {
5952 TmpInst.setOpcode(ARM::STR_PRE_IMM);
5953 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
5954 TmpInst.addOperand(Inst.getOperand(4)); // Rt
5955 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
5956 TmpInst.addOperand(MCOperand::CreateImm(-4));
5957 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
5958 TmpInst.addOperand(Inst.getOperand(3));
5962 case ARM::t2ADDri12:
5963 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
5964 // mnemonic was used (not "addw"), encoding T3 is preferred.
5965 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
5966 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
5968 Inst.setOpcode(ARM::t2ADDri);
5969 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
5971 case ARM::t2SUBri12:
5972 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
5973 // mnemonic was used (not "subw"), encoding T3 is preferred.
5974 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
5975 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
5977 Inst.setOpcode(ARM::t2SUBri);
5978 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
5981 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
5982 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
5983 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
5984 // to encoding T1 if <Rd> is omitted."
5985 if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
5986 Inst.setOpcode(ARM::tADDi3);
5991 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
5992 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
5993 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
5994 // to encoding T1 if <Rd> is omitted."
5995 if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
5996 Inst.setOpcode(ARM::tSUBi3);
6000 case ARM::t2ADDrr: {
6001 // If the destination and first source operand are the same, and
6002 // there's no setting of the flags, use encoding T2 instead of T3.
6003 // Note that this is only for ADD, not SUB. This mirrors the system
6004 // 'as' behaviour. Make sure the wide encoding wasn't explicit.
6005 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
6006 Inst.getOperand(5).getReg() != 0 ||
6007 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
6008 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
6011 TmpInst.setOpcode(ARM::tADDhirr);
6012 TmpInst.addOperand(Inst.getOperand(0));
6013 TmpInst.addOperand(Inst.getOperand(0));
6014 TmpInst.addOperand(Inst.getOperand(2));
6015 TmpInst.addOperand(Inst.getOperand(3));
6016 TmpInst.addOperand(Inst.getOperand(4));
6021 // A Thumb conditional branch outside of an IT block is a tBcc.
6022 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
6023 Inst.setOpcode(ARM::tBcc);
6028 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
6029 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
6030 Inst.setOpcode(ARM::t2Bcc);
6035 // If the conditional is AL or we're in an IT block, we really want t2B.
6036 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
6037 Inst.setOpcode(ARM::t2B);
6042 // If the conditional is AL, we really want tB.
6043 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
6044 Inst.setOpcode(ARM::tB);
6049 // If the register list contains any high registers, or if the writeback
6050 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
6051 // instead if we're in Thumb2. Otherwise, this should have generated
6052 // an error in validateInstruction().
6053 unsigned Rn = Inst.getOperand(0).getReg();
6054 bool hasWritebackToken =
6055 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
6056 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
6057 bool listContainsBase;
6058 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
6059 (!listContainsBase && !hasWritebackToken) ||
6060 (listContainsBase && hasWritebackToken)) {
6061 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
6062 assert (isThumbTwo());
6063 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
6064 // If we're switching to the updating version, we need to insert
6065 // the writeback tied operand.
6066 if (hasWritebackToken)
6067 Inst.insert(Inst.begin(),
6068 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
6073 case ARM::tSTMIA_UPD: {
6074 // If the register list contains any high registers, we need to use
6075 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
6076 // should have generated an error in validateInstruction().
6077 unsigned Rn = Inst.getOperand(0).getReg();
6078 bool listContainsBase;
6079 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
6080 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
6081 assert (isThumbTwo());
6082 Inst.setOpcode(ARM::t2STMIA_UPD);
6088 bool listContainsBase;
6089 // If the register list contains any high registers, we need to use
6090 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
6091 // should have generated an error in validateInstruction().
6092 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
6094 assert (isThumbTwo());
6095 Inst.setOpcode(ARM::t2LDMIA_UPD);
6096 // Add the base register and writeback operands.
6097 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
6098 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
6102 bool listContainsBase;
6103 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
6105 assert (isThumbTwo());
6106 Inst.setOpcode(ARM::t2STMDB_UPD);
6107 // Add the base register and writeback operands.
6108 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
6109 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
6113 // If we can use the 16-bit encoding and the user didn't explicitly
6114 // request the 32-bit variant, transform it here.
6115 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6116 Inst.getOperand(1).getImm() <= 255 &&
6117 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
6118 Inst.getOperand(4).getReg() == ARM::CPSR) ||
6119 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
6120 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
6121 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
6122 // The operands aren't in the same order for tMOVi8...
6124 TmpInst.setOpcode(ARM::tMOVi8);
6125 TmpInst.addOperand(Inst.getOperand(0));
6126 TmpInst.addOperand(Inst.getOperand(4));
6127 TmpInst.addOperand(Inst.getOperand(1));
6128 TmpInst.addOperand(Inst.getOperand(2));
6129 TmpInst.addOperand(Inst.getOperand(3));
6136 // If we can use the 16-bit encoding and the user didn't explicitly
6137 // request the 32-bit variant, transform it here.
6138 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6139 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6140 Inst.getOperand(2).getImm() == ARMCC::AL &&
6141 Inst.getOperand(4).getReg() == ARM::CPSR &&
6142 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
6143 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
6144 // The operands aren't the same for tMOV[S]r... (no cc_out)
6146 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
6147 TmpInst.addOperand(Inst.getOperand(0));
6148 TmpInst.addOperand(Inst.getOperand(1));
6149 TmpInst.addOperand(Inst.getOperand(2));
6150 TmpInst.addOperand(Inst.getOperand(3));
6160 // If we can use the 16-bit encoding and the user didn't explicitly
6161 // request the 32-bit variant, transform it here.
6162 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6163 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6164 Inst.getOperand(2).getImm() == 0 &&
6165 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
6166 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
6168 switch (Inst.getOpcode()) {
6169 default: llvm_unreachable("Illegal opcode!");
6170 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
6171 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
6172 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
6173 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
6175 // The operands aren't the same for thumb1 (no rotate operand).
6177 TmpInst.setOpcode(NewOpc);
6178 TmpInst.addOperand(Inst.getOperand(0));
6179 TmpInst.addOperand(Inst.getOperand(1));
6180 TmpInst.addOperand(Inst.getOperand(3));
6181 TmpInst.addOperand(Inst.getOperand(4));
6188 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
6189 if (SOpc == ARM_AM::rrx) return false;
6190 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
6191 // Shifting by zero is accepted as a vanilla 'MOVr'
6193 TmpInst.setOpcode(ARM::MOVr);
6194 TmpInst.addOperand(Inst.getOperand(0));
6195 TmpInst.addOperand(Inst.getOperand(1));
6196 TmpInst.addOperand(Inst.getOperand(3));
6197 TmpInst.addOperand(Inst.getOperand(4));
6198 TmpInst.addOperand(Inst.getOperand(5));
6211 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
6212 if (SOpc == ARM_AM::rrx) return false;
6213 switch (Inst.getOpcode()) {
6214 default: assert("unexpected opcode!");
6215 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
6216 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
6217 case ARM::EORrsi: newOpc = ARM::EORrr; break;
6218 case ARM::BICrsi: newOpc = ARM::BICrr; break;
6219 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
6220 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
6222 // If the shift is by zero, use the non-shifted instruction definition.
6223 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0) {
6225 TmpInst.setOpcode(newOpc);
6226 TmpInst.addOperand(Inst.getOperand(0));
6227 TmpInst.addOperand(Inst.getOperand(1));
6228 TmpInst.addOperand(Inst.getOperand(2));
6229 TmpInst.addOperand(Inst.getOperand(4));
6230 TmpInst.addOperand(Inst.getOperand(5));
6231 TmpInst.addOperand(Inst.getOperand(6));
6238 // The mask bits for all but the first condition are represented as
6239 // the low bit of the condition code value implies 't'. We currently
6240 // always have 1 implies 't', so XOR toggle the bits if the low bit
6241 // of the condition code is zero. The encoding also expects the low
6242 // bit of the condition to be encoded as bit 4 of the mask operand,
6243 // so mask that in if needed
6244 MCOperand &MO = Inst.getOperand(1);
6245 unsigned Mask = MO.getImm();
6246 unsigned OrigMask = Mask;
6247 unsigned TZ = CountTrailingZeros_32(Mask);
6248 if ((Inst.getOperand(0).getImm() & 1) == 0) {
6249 assert(Mask && TZ <= 3 && "illegal IT mask value!");
6250 for (unsigned i = 3; i != TZ; --i)
6256 // Set up the IT block state according to the IT instruction we just
6258 assert(!inITBlock() && "nested IT blocks?!");
6259 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
6260 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
6261 ITState.CurPosition = 0;
6262 ITState.FirstCond = true;
6269 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
6270 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
6271 // suffix depending on whether they're in an IT block or not.
6272 unsigned Opc = Inst.getOpcode();
6273 const MCInstrDesc &MCID = getInstDesc(Opc);
6274 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
6275 assert(MCID.hasOptionalDef() &&
6276 "optionally flag setting instruction missing optional def operand");
6277 assert(MCID.NumOperands == Inst.getNumOperands() &&
6278 "operand count mismatch!");
6279 // Find the optional-def operand (cc_out).
6282 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
6285 // If we're parsing Thumb1, reject it completely.
6286 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
6287 return Match_MnemonicFail;
6288 // If we're parsing Thumb2, which form is legal depends on whether we're
6290 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
6292 return Match_RequiresITBlock;
6293 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
6295 return Match_RequiresNotITBlock;
6297 // Some high-register supporting Thumb1 encodings only allow both registers
6298 // to be from r0-r7 when in Thumb2.
6299 else if (Opc == ARM::tADDhirr && isThumbOne() &&
6300 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6301 isARMLowRegister(Inst.getOperand(2).getReg()))
6302 return Match_RequiresThumb2;
6303 // Others only require ARMv6 or later.
6304 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
6305 isARMLowRegister(Inst.getOperand(0).getReg()) &&
6306 isARMLowRegister(Inst.getOperand(1).getReg()))
6307 return Match_RequiresV6;
6308 return Match_Success;
6312 MatchAndEmitInstruction(SMLoc IDLoc,
6313 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
6317 unsigned MatchResult;
6318 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
6319 switch (MatchResult) {
6322 // Context sensitive operand constraints aren't handled by the matcher,
6323 // so check them here.
6324 if (validateInstruction(Inst, Operands)) {
6325 // Still progress the IT block, otherwise one wrong condition causes
6326 // nasty cascading errors.
6327 forwardITPosition();
6331 // Some instructions need post-processing to, for example, tweak which
6332 // encoding is selected. Loop on it while changes happen so the
6333 // individual transformations can chain off each other. E.g.,
6334 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
6335 while (processInstruction(Inst, Operands))
6338 // Only move forward at the very end so that everything in validate
6339 // and process gets a consistent answer about whether we're in an IT
6341 forwardITPosition();
6343 Out.EmitInstruction(Inst);
6345 case Match_MissingFeature:
6346 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
6348 case Match_InvalidOperand: {
6349 SMLoc ErrorLoc = IDLoc;
6350 if (ErrorInfo != ~0U) {
6351 if (ErrorInfo >= Operands.size())
6352 return Error(IDLoc, "too few operands for instruction");
6354 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
6355 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
6358 return Error(ErrorLoc, "invalid operand for instruction");
6360 case Match_MnemonicFail:
6361 return Error(IDLoc, "invalid instruction");
6362 case Match_ConversionFail:
6363 // The converter function will have already emited a diagnostic.
6365 case Match_RequiresNotITBlock:
6366 return Error(IDLoc, "flag setting instruction only valid outside IT block");
6367 case Match_RequiresITBlock:
6368 return Error(IDLoc, "instruction only valid inside IT block");
6369 case Match_RequiresV6:
6370 return Error(IDLoc, "instruction variant requires ARMv6 or later");
6371 case Match_RequiresThumb2:
6372 return Error(IDLoc, "instruction variant requires Thumb2");
6375 llvm_unreachable("Implement any new match types added!");
6379 /// parseDirective parses the arm specific directives
6380 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
6381 StringRef IDVal = DirectiveID.getIdentifier();
6382 if (IDVal == ".word")
6383 return parseDirectiveWord(4, DirectiveID.getLoc());
6384 else if (IDVal == ".thumb")
6385 return parseDirectiveThumb(DirectiveID.getLoc());
6386 else if (IDVal == ".arm")
6387 return parseDirectiveARM(DirectiveID.getLoc());
6388 else if (IDVal == ".thumb_func")
6389 return parseDirectiveThumbFunc(DirectiveID.getLoc());
6390 else if (IDVal == ".code")
6391 return parseDirectiveCode(DirectiveID.getLoc());
6392 else if (IDVal == ".syntax")
6393 return parseDirectiveSyntax(DirectiveID.getLoc());
6394 else if (IDVal == ".unreq")
6395 return parseDirectiveUnreq(DirectiveID.getLoc());
6396 else if (IDVal == ".arch")
6397 return parseDirectiveArch(DirectiveID.getLoc());
6398 else if (IDVal == ".eabi_attribute")
6399 return parseDirectiveEabiAttr(DirectiveID.getLoc());
6403 /// parseDirectiveWord
6404 /// ::= .word [ expression (, expression)* ]
6405 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
6406 if (getLexer().isNot(AsmToken::EndOfStatement)) {
6408 const MCExpr *Value;
6409 if (getParser().ParseExpression(Value))
6412 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
6414 if (getLexer().is(AsmToken::EndOfStatement))
6417 // FIXME: Improve diagnostic.
6418 if (getLexer().isNot(AsmToken::Comma))
6419 return Error(L, "unexpected token in directive");
6428 /// parseDirectiveThumb
6430 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
6431 if (getLexer().isNot(AsmToken::EndOfStatement))
6432 return Error(L, "unexpected token in directive");
6437 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
6441 /// parseDirectiveARM
6443 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
6444 if (getLexer().isNot(AsmToken::EndOfStatement))
6445 return Error(L, "unexpected token in directive");
6450 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
6454 /// parseDirectiveThumbFunc
6455 /// ::= .thumbfunc symbol_name
6456 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
6457 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
6458 bool isMachO = MAI.hasSubsectionsViaSymbols();
6460 bool needFuncName = true;
6462 // Darwin asm has (optionally) function name after .thumb_func direction
6465 const AsmToken &Tok = Parser.getTok();
6466 if (Tok.isNot(AsmToken::EndOfStatement)) {
6467 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
6468 return Error(L, "unexpected token in .thumb_func directive");
6469 Name = Tok.getIdentifier();
6470 Parser.Lex(); // Consume the identifier token.
6471 needFuncName = false;
6475 if (getLexer().isNot(AsmToken::EndOfStatement))
6476 return Error(L, "unexpected token in directive");
6478 // Eat the end of statement and any blank lines that follow.
6479 while (getLexer().is(AsmToken::EndOfStatement))
6482 // FIXME: assuming function name will be the line following .thumb_func
6483 // We really should be checking the next symbol definition even if there's
6484 // stuff in between.
6486 Name = Parser.getTok().getIdentifier();
6489 // Mark symbol as a thumb symbol.
6490 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
6491 getParser().getStreamer().EmitThumbFunc(Func);
6495 /// parseDirectiveSyntax
6496 /// ::= .syntax unified | divided
6497 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
6498 const AsmToken &Tok = Parser.getTok();
6499 if (Tok.isNot(AsmToken::Identifier))
6500 return Error(L, "unexpected token in .syntax directive");
6501 StringRef Mode = Tok.getString();
6502 if (Mode == "unified" || Mode == "UNIFIED")
6504 else if (Mode == "divided" || Mode == "DIVIDED")
6505 return Error(L, "'.syntax divided' arm asssembly not supported");
6507 return Error(L, "unrecognized syntax mode in .syntax directive");
6509 if (getLexer().isNot(AsmToken::EndOfStatement))
6510 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
6513 // TODO tell the MC streamer the mode
6514 // getParser().getStreamer().Emit???();
6518 /// parseDirectiveCode
6519 /// ::= .code 16 | 32
6520 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
6521 const AsmToken &Tok = Parser.getTok();
6522 if (Tok.isNot(AsmToken::Integer))
6523 return Error(L, "unexpected token in .code directive");
6524 int64_t Val = Parser.getTok().getIntVal();
6530 return Error(L, "invalid operand to .code directive");
6532 if (getLexer().isNot(AsmToken::EndOfStatement))
6533 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
6539 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
6543 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
6549 /// parseDirectiveReq
6550 /// ::= name .req registername
6551 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
6552 Parser.Lex(); // Eat the '.req' token.
6554 SMLoc SRegLoc, ERegLoc;
6555 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
6556 Parser.EatToEndOfStatement();
6557 return Error(SRegLoc, "register name expected");
6560 // Shouldn't be anything else.
6561 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
6562 Parser.EatToEndOfStatement();
6563 return Error(Parser.getTok().getLoc(),
6564 "unexpected input in .req directive.");
6567 Parser.Lex(); // Consume the EndOfStatement
6569 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg)
6570 return Error(SRegLoc, "redefinition of '" + Name +
6571 "' does not match original.");
6576 /// parseDirectiveUneq
6577 /// ::= .unreq registername
6578 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
6579 if (Parser.getTok().isNot(AsmToken::Identifier)) {
6580 Parser.EatToEndOfStatement();
6581 return Error(L, "unexpected input in .unreq directive.");
6583 RegisterReqs.erase(Parser.getTok().getIdentifier());
6584 Parser.Lex(); // Eat the identifier.
6588 /// parseDirectiveArch
6590 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
6594 /// parseDirectiveEabiAttr
6595 /// ::= .eabi_attribute int, int
6596 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
6600 extern "C" void LLVMInitializeARMAsmLexer();
6602 /// Force static initialization.
6603 extern "C" void LLVMInitializeARMAsmParser() {
6604 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
6605 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
6606 LLVMInitializeARMAsmLexer();
6609 #define GET_REGISTER_MATCHER
6610 #define GET_MATCHER_IMPLEMENTATION
6611 #include "ARMGenAsmMatcher.inc"