1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMSubtarget.h"
12 #include "llvm/MC/MCParser/MCAsmLexer.h"
13 #include "llvm/MC/MCParser/MCAsmParser.h"
14 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
15 #include "llvm/MC/MCStreamer.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/Target/TargetRegistry.h"
19 #include "llvm/Target/TargetAsmParser.h"
20 #include "llvm/Support/SourceMgr.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/ADT/OwningPtr.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/StringSwitch.h"
25 #include "llvm/ADT/Twine.h"
31 // The shift types for register controlled shifts in arm memory addressing
40 class ARMAsmParser : public TargetAsmParser {
45 MCAsmParser &getParser() const { return Parser; }
47 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
49 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
51 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
53 bool MaybeParseRegister(OwningPtr<ARMOperand> &Op, bool ParseWriteBack);
55 bool ParseRegisterList(OwningPtr<ARMOperand> &Op);
57 bool ParseMemory(OwningPtr<ARMOperand> &Op);
59 bool ParseMemoryOffsetReg(bool &Negative,
60 bool &OffsetRegShifted,
61 enum ShiftType &ShiftType,
62 const MCExpr *&ShiftAmount,
63 const MCExpr *&Offset,
68 bool ParseShift(enum ShiftType &St, const MCExpr *&ShiftAmount, SMLoc &E);
70 bool ParseOperand(OwningPtr<ARMOperand> &Op);
72 bool ParseDirectiveWord(unsigned Size, SMLoc L);
74 bool ParseDirectiveThumb(SMLoc L);
76 bool ParseDirectiveThumbFunc(SMLoc L);
78 bool ParseDirectiveCode(SMLoc L);
80 bool ParseDirectiveSyntax(SMLoc L);
82 bool MatchAndEmitInstruction(SMLoc IDLoc,
83 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
87 if (MatchInstructionImpl(Operands, Inst, ErrorInfo) == Match_Success) {
88 Out.EmitInstruction(Inst);
92 // FIXME: We should give nicer diagnostics about the exact failure.
93 Error(IDLoc, "unrecognized instruction");
97 /// @name Auto-generated Match Functions
100 #define GET_ASSEMBLER_HEADER
101 #include "ARMGenAsmMatcher.inc"
107 ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
108 : TargetAsmParser(T), Parser(_Parser), TM(_TM) {}
110 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
111 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
113 virtual bool ParseDirective(AsmToken DirectiveID);
116 /// ARMOperand - Instances of this class represent a parsed ARM machine
118 struct ARMOperand : public MCParsedAsmOperand {
130 SMLoc StartLoc, EndLoc;
134 ARMCC::CondCodes Val;
151 // This is for all forms of ARM address expressions
154 unsigned OffsetRegNum; // used when OffsetIsReg is true
155 const MCExpr *Offset; // used when OffsetIsReg is false
156 const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
157 enum ShiftType ShiftType; // used when OffsetRegShifted is true
159 OffsetRegShifted : 1, // only used when OffsetIsReg is true
163 Negative : 1, // only used when OffsetIsReg is true
169 //ARMOperand(KindTy K, SMLoc S, SMLoc E)
170 // : Kind(K), StartLoc(S), EndLoc(E) {}
172 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
174 StartLoc = o.StartLoc;
195 /// getStartLoc - Get the location of the first token of this operand.
196 SMLoc getStartLoc() const { return StartLoc; }
197 /// getEndLoc - Get the location of the last token of this operand.
198 SMLoc getEndLoc() const { return EndLoc; }
200 ARMCC::CondCodes getCondCode() const {
201 assert(Kind == CondCode && "Invalid access!");
205 StringRef getToken() const {
206 assert(Kind == Token && "Invalid access!");
207 return StringRef(Tok.Data, Tok.Length);
210 unsigned getReg() const {
211 assert(Kind == Register && "Invalid access!");
215 const MCExpr *getImm() const {
216 assert(Kind == Immediate && "Invalid access!");
220 bool isCondCode() const { return Kind == CondCode; }
222 bool isImm() const { return Kind == Immediate; }
224 bool isReg() const { return Kind == Register; }
226 bool isToken() const {return Kind == Token; }
228 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
229 // Add as immediates when possible.
230 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
231 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
233 Inst.addOperand(MCOperand::CreateExpr(Expr));
236 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
237 assert(N == 2 && "Invalid number of operands!");
238 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
239 // FIXME: What belongs here?
240 Inst.addOperand(MCOperand::CreateReg(0));
243 void addRegOperands(MCInst &Inst, unsigned N) const {
244 assert(N == 1 && "Invalid number of operands!");
245 Inst.addOperand(MCOperand::CreateReg(getReg()));
248 void addImmOperands(MCInst &Inst, unsigned N) const {
249 assert(N == 1 && "Invalid number of operands!");
250 addExpr(Inst, getImm());
253 virtual void dump(raw_ostream &OS) const;
255 static void CreateCondCode(OwningPtr<ARMOperand> &Op, ARMCC::CondCodes CC,
257 Op.reset(new ARMOperand);
264 static void CreateToken(OwningPtr<ARMOperand> &Op, StringRef Str,
266 Op.reset(new ARMOperand);
268 Op->Tok.Data = Str.data();
269 Op->Tok.Length = Str.size();
274 static void CreateReg(OwningPtr<ARMOperand> &Op, unsigned RegNum,
275 bool Writeback, SMLoc S, SMLoc E) {
276 Op.reset(new ARMOperand);
278 Op->Reg.RegNum = RegNum;
279 Op->Reg.Writeback = Writeback;
285 static void CreateImm(OwningPtr<ARMOperand> &Op, const MCExpr *Val,
287 Op.reset(new ARMOperand);
288 Op->Kind = Immediate;
295 static void CreateMem(OwningPtr<ARMOperand> &Op,
296 unsigned BaseRegNum, bool OffsetIsReg,
297 const MCExpr *Offset, unsigned OffsetRegNum,
298 bool OffsetRegShifted, enum ShiftType ShiftType,
299 const MCExpr *ShiftAmount, bool Preindexed,
300 bool Postindexed, bool Negative, bool Writeback,
302 Op.reset(new ARMOperand);
304 Op->Mem.BaseRegNum = BaseRegNum;
305 Op->Mem.OffsetIsReg = OffsetIsReg;
306 Op->Mem.Offset = Offset;
307 Op->Mem.OffsetRegNum = OffsetRegNum;
308 Op->Mem.OffsetRegShifted = OffsetRegShifted;
309 Op->Mem.ShiftType = ShiftType;
310 Op->Mem.ShiftAmount = ShiftAmount;
311 Op->Mem.Preindexed = Preindexed;
312 Op->Mem.Postindexed = Postindexed;
313 Op->Mem.Negative = Negative;
314 Op->Mem.Writeback = Writeback;
321 } // end anonymous namespace.
323 void ARMOperand::dump(raw_ostream &OS) const {
326 OS << ARMCondCodeToString(getCondCode());
335 OS << "<register " << getReg() << ">";
338 OS << "'" << getToken() << "'";
343 /// @name Auto-generated Match Functions
346 static unsigned MatchRegisterName(StringRef Name);
350 /// Try to parse a register name. The token must be an Identifier when called,
351 /// and if it is a register name a Reg operand is created, the token is eaten
352 /// and false is returned. Else true is returned and no token is eaten.
353 /// TODO this is likely to change to allow different register types and or to
354 /// parse for a specific register type.
355 bool ARMAsmParser::MaybeParseRegister
356 (OwningPtr<ARMOperand> &Op, bool ParseWriteBack) {
358 const AsmToken &Tok = Parser.getTok();
359 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
361 // FIXME: Validate register for the current architecture; we have to do
362 // validation later, so maybe there is no need for this here.
365 RegNum = MatchRegisterName(Tok.getString());
371 Parser.Lex(); // Eat identifier token.
373 E = Parser.getTok().getLoc();
375 bool Writeback = false;
376 if (ParseWriteBack) {
377 const AsmToken &ExclaimTok = Parser.getTok();
378 if (ExclaimTok.is(AsmToken::Exclaim)) {
379 E = ExclaimTok.getLoc();
381 Parser.Lex(); // Eat exclaim token
385 ARMOperand::CreateReg(Op, RegNum, Writeback, S, E);
390 /// Parse a register list, return false if successful else return true or an
391 /// error. The first token must be a '{' when called.
392 bool ARMAsmParser::ParseRegisterList(OwningPtr<ARMOperand> &Op) {
394 assert(Parser.getTok().is(AsmToken::LCurly) &&
395 "Token is not an Left Curly Brace");
396 S = Parser.getTok().getLoc();
397 Parser.Lex(); // Eat left curly brace token.
399 const AsmToken &RegTok = Parser.getTok();
400 SMLoc RegLoc = RegTok.getLoc();
401 if (RegTok.isNot(AsmToken::Identifier))
402 return Error(RegLoc, "register expected");
403 int RegNum = MatchRegisterName(RegTok.getString());
405 return Error(RegLoc, "register expected");
406 Parser.Lex(); // Eat identifier token.
407 unsigned RegList = 1 << RegNum;
409 int HighRegNum = RegNum;
410 // TODO ranges like "{Rn-Rm}"
411 while (Parser.getTok().is(AsmToken::Comma)) {
412 Parser.Lex(); // Eat comma token.
414 const AsmToken &RegTok = Parser.getTok();
415 SMLoc RegLoc = RegTok.getLoc();
416 if (RegTok.isNot(AsmToken::Identifier))
417 return Error(RegLoc, "register expected");
418 int RegNum = MatchRegisterName(RegTok.getString());
420 return Error(RegLoc, "register expected");
422 if (RegList & (1 << RegNum))
423 Warning(RegLoc, "register duplicated in register list");
424 else if (RegNum <= HighRegNum)
425 Warning(RegLoc, "register not in ascending order in register list");
426 RegList |= 1 << RegNum;
429 Parser.Lex(); // Eat identifier token.
431 const AsmToken &RCurlyTok = Parser.getTok();
432 if (RCurlyTok.isNot(AsmToken::RCurly))
433 return Error(RCurlyTok.getLoc(), "'}' expected");
434 E = RCurlyTok.getLoc();
435 Parser.Lex(); // Eat left curly brace token.
440 /// Parse an arm memory expression, return false if successful else return true
441 /// or an error. The first token must be a '[' when called.
442 /// TODO Only preindexing and postindexing addressing are started, unindexed
443 /// with option, etc are still to do.
444 bool ARMAsmParser::ParseMemory(OwningPtr<ARMOperand> &Op) {
446 assert(Parser.getTok().is(AsmToken::LBrac) &&
447 "Token is not an Left Bracket");
448 S = Parser.getTok().getLoc();
449 Parser.Lex(); // Eat left bracket token.
451 const AsmToken &BaseRegTok = Parser.getTok();
452 if (BaseRegTok.isNot(AsmToken::Identifier))
453 return Error(BaseRegTok.getLoc(), "register expected");
454 if (MaybeParseRegister(Op, false))
455 return Error(BaseRegTok.getLoc(), "register expected");
456 int BaseRegNum = Op->getReg();
458 bool Preindexed = false;
459 bool Postindexed = false;
460 bool OffsetIsReg = false;
461 bool Negative = false;
462 bool Writeback = false;
464 // First look for preindexed address forms, that is after the "[Rn" we now
465 // have to see if the next token is a comma.
466 const AsmToken &Tok = Parser.getTok();
467 if (Tok.is(AsmToken::Comma)) {
469 Parser.Lex(); // Eat comma token.
471 bool OffsetRegShifted;
472 enum ShiftType ShiftType;
473 const MCExpr *ShiftAmount;
474 const MCExpr *Offset;
475 if(ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
476 Offset, OffsetIsReg, OffsetRegNum, E))
478 const AsmToken &RBracTok = Parser.getTok();
479 if (RBracTok.isNot(AsmToken::RBrac))
480 return Error(RBracTok.getLoc(), "']' expected");
481 E = RBracTok.getLoc();
482 Parser.Lex(); // Eat right bracket token.
484 const AsmToken &ExclaimTok = Parser.getTok();
485 if (ExclaimTok.is(AsmToken::Exclaim)) {
486 E = ExclaimTok.getLoc();
488 Parser.Lex(); // Eat exclaim token
490 ARMOperand::CreateMem(Op, BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
491 OffsetRegShifted, ShiftType, ShiftAmount,
492 Preindexed, Postindexed, Negative, Writeback, S, E);
495 // The "[Rn" we have so far was not followed by a comma.
496 else if (Tok.is(AsmToken::RBrac)) {
497 // This is a post indexing addressing forms, that is a ']' follows after
502 Parser.Lex(); // Eat right bracket token.
504 int OffsetRegNum = 0;
505 bool OffsetRegShifted = false;
506 enum ShiftType ShiftType;
507 const MCExpr *ShiftAmount;
508 const MCExpr *Offset;
510 const AsmToken &NextTok = Parser.getTok();
511 if (NextTok.isNot(AsmToken::EndOfStatement)) {
512 if (NextTok.isNot(AsmToken::Comma))
513 return Error(NextTok.getLoc(), "',' expected");
514 Parser.Lex(); // Eat comma token.
515 if(ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
516 ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
521 ARMOperand::CreateMem(Op, BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
522 OffsetRegShifted, ShiftType, ShiftAmount,
523 Preindexed, Postindexed, Negative, Writeback, S, E);
530 /// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
531 /// we will parse the following (were +/- means that a plus or minus is
536 /// we return false on success or an error otherwise.
537 bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
538 bool &OffsetRegShifted,
539 enum ShiftType &ShiftType,
540 const MCExpr *&ShiftAmount,
541 const MCExpr *&Offset,
545 OwningPtr<ARMOperand> Op;
547 OffsetRegShifted = false;
550 const AsmToken &NextTok = Parser.getTok();
551 E = NextTok.getLoc();
552 if (NextTok.is(AsmToken::Plus))
553 Parser.Lex(); // Eat plus token.
554 else if (NextTok.is(AsmToken::Minus)) {
556 Parser.Lex(); // Eat minus token
558 // See if there is a register following the "[Rn," or "[Rn]," we have so far.
559 const AsmToken &OffsetRegTok = Parser.getTok();
560 if (OffsetRegTok.is(AsmToken::Identifier)) {
561 OffsetIsReg = !MaybeParseRegister(Op, false);
564 OffsetRegNum = Op->getReg();
567 // If we parsed a register as the offset then their can be a shift after that
568 if (OffsetRegNum != -1) {
569 // Look for a comma then a shift
570 const AsmToken &Tok = Parser.getTok();
571 if (Tok.is(AsmToken::Comma)) {
572 Parser.Lex(); // Eat comma token.
574 const AsmToken &Tok = Parser.getTok();
575 if (ParseShift(ShiftType, ShiftAmount, E))
576 return Error(Tok.getLoc(), "shift expected");
577 OffsetRegShifted = true;
580 else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
581 // Look for #offset following the "[Rn," or "[Rn],"
582 const AsmToken &HashTok = Parser.getTok();
583 if (HashTok.isNot(AsmToken::Hash))
584 return Error(HashTok.getLoc(), "'#' expected");
586 Parser.Lex(); // Eat hash token.
588 if (getParser().ParseExpression(Offset))
590 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
595 /// ParseShift as one of these two:
596 /// ( lsl | lsr | asr | ror ) , # shift_amount
598 /// and returns true if it parses a shift otherwise it returns false.
599 bool ARMAsmParser::ParseShift(ShiftType &St,
600 const MCExpr *&ShiftAmount,
602 const AsmToken &Tok = Parser.getTok();
603 if (Tok.isNot(AsmToken::Identifier))
605 StringRef ShiftName = Tok.getString();
606 if (ShiftName == "lsl" || ShiftName == "LSL")
608 else if (ShiftName == "lsr" || ShiftName == "LSR")
610 else if (ShiftName == "asr" || ShiftName == "ASR")
612 else if (ShiftName == "ror" || ShiftName == "ROR")
614 else if (ShiftName == "rrx" || ShiftName == "RRX")
618 Parser.Lex(); // Eat shift type token.
624 // Otherwise, there must be a '#' and a shift amount.
625 const AsmToken &HashTok = Parser.getTok();
626 if (HashTok.isNot(AsmToken::Hash))
627 return Error(HashTok.getLoc(), "'#' expected");
628 Parser.Lex(); // Eat hash token.
630 if (getParser().ParseExpression(ShiftAmount))
636 /// Parse a arm instruction operand. For now this parses the operand regardless
638 bool ARMAsmParser::ParseOperand(OwningPtr<ARMOperand> &Op) {
641 switch (getLexer().getKind()) {
642 case AsmToken::Identifier:
643 if (!MaybeParseRegister(Op, true))
645 // This was not a register so parse other operands that start with an
646 // identifier (like labels) as expressions and create them as immediates.
648 S = Parser.getTok().getLoc();
649 if (getParser().ParseExpression(IdVal))
651 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
652 ARMOperand::CreateImm(Op, IdVal, S, E);
654 case AsmToken::LBrac:
655 return ParseMemory(Op);
656 case AsmToken::LCurly:
657 return ParseRegisterList(Op);
660 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
661 S = Parser.getTok().getLoc();
663 const MCExpr *ImmVal;
664 if (getParser().ParseExpression(ImmVal))
666 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
667 ARMOperand::CreateImm(Op, ImmVal, S, E);
670 return Error(Parser.getTok().getLoc(), "unexpected token in operand");
674 /// Parse an arm instruction mnemonic followed by its operands.
675 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
676 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
677 OwningPtr<ARMOperand> Op;
679 // Create the leading tokens for the mnemonic, split by '.' characters.
680 size_t Start = 0, Next = Name.find('.');
681 StringRef Head = Name.slice(Start, Next);
683 // Determine the predicate, if any.
685 // FIXME: We need a way to check whether a prefix supports predication,
686 // otherwise we will end up with an ambiguity for instructions that happen to
687 // end with a predicate name.
688 unsigned CC = StringSwitch<unsigned>(Head.substr(Head.size()-2))
689 .Case("eq", ARMCC::EQ)
690 .Case("ne", ARMCC::NE)
691 .Case("hs", ARMCC::HS)
692 .Case("lo", ARMCC::LO)
693 .Case("mi", ARMCC::MI)
694 .Case("pl", ARMCC::PL)
695 .Case("vs", ARMCC::VS)
696 .Case("vc", ARMCC::VC)
697 .Case("hi", ARMCC::HI)
698 .Case("ls", ARMCC::LS)
699 .Case("ge", ARMCC::GE)
700 .Case("lt", ARMCC::LT)
701 .Case("gt", ARMCC::GT)
702 .Case("le", ARMCC::LE)
703 .Case("al", ARMCC::AL)
706 Head = Head.slice(0, Head.size() - 2);
710 ARMOperand::CreateToken(Op, Head, NameLoc);
711 Operands.push_back(Op.take());
713 ARMOperand::CreateCondCode(Op, ARMCC::CondCodes(CC), NameLoc);
714 Operands.push_back(Op.take());
716 // Add the remaining tokens in the mnemonic.
717 while (Next != StringRef::npos) {
719 Next = Name.find('.', Start + 1);
720 Head = Name.slice(Start, Next);
722 ARMOperand::CreateToken(Op, Head, NameLoc);
723 Operands.push_back(Op.take());
726 // Read the remaining operands.
727 if (getLexer().isNot(AsmToken::EndOfStatement)) {
728 // Read the first operand.
729 OwningPtr<ARMOperand> Op;
730 if (ParseOperand(Op)) {
731 Parser.EatToEndOfStatement();
734 Operands.push_back(Op.take());
736 while (getLexer().is(AsmToken::Comma)) {
737 Parser.Lex(); // Eat the comma.
739 // Parse and remember the operand.
740 if (ParseOperand(Op)) {
741 Parser.EatToEndOfStatement();
744 Operands.push_back(Op.take());
748 if (getLexer().isNot(AsmToken::EndOfStatement)) {
749 Parser.EatToEndOfStatement();
750 return TokError("unexpected token in argument list");
752 Parser.Lex(); // Consume the EndOfStatement
756 /// ParseDirective parses the arm specific directives
757 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
758 StringRef IDVal = DirectiveID.getIdentifier();
759 if (IDVal == ".word")
760 return ParseDirectiveWord(4, DirectiveID.getLoc());
761 else if (IDVal == ".thumb")
762 return ParseDirectiveThumb(DirectiveID.getLoc());
763 else if (IDVal == ".thumb_func")
764 return ParseDirectiveThumbFunc(DirectiveID.getLoc());
765 else if (IDVal == ".code")
766 return ParseDirectiveCode(DirectiveID.getLoc());
767 else if (IDVal == ".syntax")
768 return ParseDirectiveSyntax(DirectiveID.getLoc());
772 /// ParseDirectiveWord
773 /// ::= .word [ expression (, expression)* ]
774 bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
775 if (getLexer().isNot(AsmToken::EndOfStatement)) {
778 if (getParser().ParseExpression(Value))
781 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
783 if (getLexer().is(AsmToken::EndOfStatement))
786 // FIXME: Improve diagnostic.
787 if (getLexer().isNot(AsmToken::Comma))
788 return Error(L, "unexpected token in directive");
797 /// ParseDirectiveThumb
799 bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
800 if (getLexer().isNot(AsmToken::EndOfStatement))
801 return Error(L, "unexpected token in directive");
804 // TODO: set thumb mode
805 // TODO: tell the MC streamer the mode
806 // getParser().getStreamer().Emit???();
810 /// ParseDirectiveThumbFunc
811 /// ::= .thumbfunc symbol_name
812 bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
813 const AsmToken &Tok = Parser.getTok();
814 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
815 return Error(L, "unexpected token in .syntax directive");
816 Parser.Lex(); // Consume the identifier token.
818 if (getLexer().isNot(AsmToken::EndOfStatement))
819 return Error(L, "unexpected token in directive");
822 // TODO: mark symbol as a thumb symbol
823 // getParser().getStreamer().Emit???();
827 /// ParseDirectiveSyntax
828 /// ::= .syntax unified | divided
829 bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
830 const AsmToken &Tok = Parser.getTok();
831 if (Tok.isNot(AsmToken::Identifier))
832 return Error(L, "unexpected token in .syntax directive");
833 StringRef Mode = Tok.getString();
834 if (Mode == "unified" || Mode == "UNIFIED")
836 else if (Mode == "divided" || Mode == "DIVIDED")
839 return Error(L, "unrecognized syntax mode in .syntax directive");
841 if (getLexer().isNot(AsmToken::EndOfStatement))
842 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
845 // TODO tell the MC streamer the mode
846 // getParser().getStreamer().Emit???();
850 /// ParseDirectiveCode
851 /// ::= .code 16 | 32
852 bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
853 const AsmToken &Tok = Parser.getTok();
854 if (Tok.isNot(AsmToken::Integer))
855 return Error(L, "unexpected token in .code directive");
856 int64_t Val = Parser.getTok().getIntVal();
862 return Error(L, "invalid operand to .code directive");
864 if (getLexer().isNot(AsmToken::EndOfStatement))
865 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
868 // TODO tell the MC streamer the mode
869 // getParser().getStreamer().Emit???();
873 extern "C" void LLVMInitializeARMAsmLexer();
875 /// Force static initialization.
876 extern "C" void LLVMInitializeARMAsmParser() {
877 RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
878 RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
879 LLVMInitializeARMAsmLexer();
882 #define GET_REGISTER_MATCHER
883 #define GET_MATCHER_IMPLEMENTATION
884 #include "ARMGenAsmMatcher.inc"