1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMBaseInfo.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMMCExpr.h"
13 #include "llvm/MC/MCParser/MCAsmLexer.h"
14 #include "llvm/MC/MCParser/MCAsmParser.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCAsmInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCTargetAsmParser.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/SourceMgr.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/ADT/BitVector.h"
30 #include "llvm/ADT/OwningPtr.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/StringExtras.h"
34 #include "llvm/ADT/StringSwitch.h"
35 #include "llvm/ADT/Twine.h"
43 class ARMAsmParser : public MCTargetAsmParser {
48 ARMCC::CondCodes Cond; // Condition for IT block.
49 unsigned Mask:4; // Condition mask for instructions.
50 // Starting at first 1 (from lsb).
51 // '1' condition as indicated in IT.
52 // '0' inverse of condition (else).
53 // Count of instructions in IT block is
54 // 4 - trailingzeroes(mask)
56 bool FirstCond; // Explicit flag for when we're parsing the
57 // First instruction in the IT block. It's
58 // implied in the mask, so needs special
61 unsigned CurPosition; // Current position in parsing of IT
62 // block. In range [0,3]. Initialized
63 // according to count of instructions in block.
64 // ~0U if no active IT block.
66 bool inITBlock() { return ITState.CurPosition != ~0U;}
67 void forwardITPosition() {
68 if (!inITBlock()) return;
69 // Move to the next instruction in the IT block, if there is one. If not,
70 // mark the block as done.
71 unsigned TZ = CountTrailingZeros_32(ITState.Mask);
72 if (++ITState.CurPosition == 5 - TZ)
73 ITState.CurPosition = ~0U; // Done with the IT block after this.
77 MCAsmParser &getParser() const { return Parser; }
78 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
80 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
81 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
83 int tryParseRegister();
84 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
85 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
86 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
87 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
88 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
89 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
90 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
91 unsigned &ShiftAmount);
92 bool parseDirectiveWord(unsigned Size, SMLoc L);
93 bool parseDirectiveThumb(SMLoc L);
94 bool parseDirectiveThumbFunc(SMLoc L);
95 bool parseDirectiveCode(SMLoc L);
96 bool parseDirectiveSyntax(SMLoc L);
98 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
99 bool &CarrySetting, unsigned &ProcessorIMod,
101 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
102 bool &CanAcceptPredicationCode);
104 bool isThumb() const {
105 // FIXME: Can tablegen auto-generate this?
106 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
108 bool isThumbOne() const {
109 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
111 bool isThumbTwo() const {
112 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
114 bool hasV6Ops() const {
115 return STI.getFeatureBits() & ARM::HasV6Ops;
118 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
119 setAvailableFeatures(FB);
122 /// @name Auto-generated Match Functions
125 #define GET_ASSEMBLER_HEADER
126 #include "ARMGenAsmMatcher.inc"
130 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
131 OperandMatchResultTy parseCoprocNumOperand(
132 SmallVectorImpl<MCParsedAsmOperand*>&);
133 OperandMatchResultTy parseCoprocRegOperand(
134 SmallVectorImpl<MCParsedAsmOperand*>&);
135 OperandMatchResultTy parseMemBarrierOptOperand(
136 SmallVectorImpl<MCParsedAsmOperand*>&);
137 OperandMatchResultTy parseProcIFlagsOperand(
138 SmallVectorImpl<MCParsedAsmOperand*>&);
139 OperandMatchResultTy parseMSRMaskOperand(
140 SmallVectorImpl<MCParsedAsmOperand*>&);
141 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
142 StringRef Op, int Low, int High);
143 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
144 return parsePKHImm(O, "lsl", 0, 31);
146 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
147 return parsePKHImm(O, "asr", 1, 32);
149 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
150 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
151 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
152 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
153 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
154 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
156 // Asm Match Converter Methods
157 bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
158 const SmallVectorImpl<MCParsedAsmOperand*> &);
159 bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
160 const SmallVectorImpl<MCParsedAsmOperand*> &);
161 bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
162 const SmallVectorImpl<MCParsedAsmOperand*> &);
163 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
164 const SmallVectorImpl<MCParsedAsmOperand*> &);
165 bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
166 const SmallVectorImpl<MCParsedAsmOperand*> &);
167 bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
168 const SmallVectorImpl<MCParsedAsmOperand*> &);
169 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
170 const SmallVectorImpl<MCParsedAsmOperand*> &);
171 bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
172 const SmallVectorImpl<MCParsedAsmOperand*> &);
173 bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
174 const SmallVectorImpl<MCParsedAsmOperand*> &);
175 bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
176 const SmallVectorImpl<MCParsedAsmOperand*> &);
177 bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
178 const SmallVectorImpl<MCParsedAsmOperand*> &);
179 bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
180 const SmallVectorImpl<MCParsedAsmOperand*> &);
181 bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
182 const SmallVectorImpl<MCParsedAsmOperand*> &);
183 bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
184 const SmallVectorImpl<MCParsedAsmOperand*> &);
185 bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
186 const SmallVectorImpl<MCParsedAsmOperand*> &);
187 bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
188 const SmallVectorImpl<MCParsedAsmOperand*> &);
190 bool validateInstruction(MCInst &Inst,
191 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
192 void processInstruction(MCInst &Inst,
193 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
194 bool shouldOmitCCOutOperand(StringRef Mnemonic,
195 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
198 enum ARMMatchResultTy {
199 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
200 Match_RequiresNotITBlock,
205 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
206 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
207 MCAsmParserExtension::Initialize(_Parser);
209 // Initialize the set of available features.
210 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
212 // Not in an ITBlock to start with.
213 ITState.CurPosition = ~0U;
216 // Implementation of the MCTargetAsmParser interface:
217 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
218 bool ParseInstruction(StringRef Name, SMLoc NameLoc,
219 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
220 bool ParseDirective(AsmToken DirectiveID);
222 unsigned checkTargetMatchPredicate(MCInst &Inst);
224 bool MatchAndEmitInstruction(SMLoc IDLoc,
225 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
228 } // end anonymous namespace
232 /// ARMOperand - Instances of this class represent a parsed ARM machine
234 class ARMOperand : public MCParsedAsmOperand {
259 SMLoc StartLoc, EndLoc;
260 SmallVector<unsigned, 8> Registers;
264 ARMCC::CondCodes Val;
280 ARM_PROC::IFlags Val;
300 /// Combined record for all forms of ARM address expressions.
303 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
305 const MCConstantExpr *OffsetImm; // Offset immediate value
306 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
307 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
308 unsigned ShiftImm; // shift for OffsetReg.
309 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
315 ARM_AM::ShiftOpc ShiftTy;
324 ARM_AM::ShiftOpc ShiftTy;
330 ARM_AM::ShiftOpc ShiftTy;
343 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
345 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
347 StartLoc = o.StartLoc;
364 case DPRRegisterList:
365 case SPRRegisterList:
366 Registers = o.Registers;
381 case PostIndexRegister:
382 PostIdxReg = o.PostIdxReg;
390 case ShifterImmediate:
391 ShifterImm = o.ShifterImm;
393 case ShiftedRegister:
394 RegShiftedReg = o.RegShiftedReg;
396 case ShiftedImmediate:
397 RegShiftedImm = o.RegShiftedImm;
399 case RotateImmediate:
402 case BitfieldDescriptor:
403 Bitfield = o.Bitfield;
408 /// getStartLoc - Get the location of the first token of this operand.
409 SMLoc getStartLoc() const { return StartLoc; }
410 /// getEndLoc - Get the location of the last token of this operand.
411 SMLoc getEndLoc() const { return EndLoc; }
413 ARMCC::CondCodes getCondCode() const {
414 assert(Kind == CondCode && "Invalid access!");
418 unsigned getCoproc() const {
419 assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
423 StringRef getToken() const {
424 assert(Kind == Token && "Invalid access!");
425 return StringRef(Tok.Data, Tok.Length);
428 unsigned getReg() const {
429 assert((Kind == Register || Kind == CCOut) && "Invalid access!");
433 const SmallVectorImpl<unsigned> &getRegList() const {
434 assert((Kind == RegisterList || Kind == DPRRegisterList ||
435 Kind == SPRRegisterList) && "Invalid access!");
439 const MCExpr *getImm() const {
440 assert(Kind == Immediate && "Invalid access!");
444 ARM_MB::MemBOpt getMemBarrierOpt() const {
445 assert(Kind == MemBarrierOpt && "Invalid access!");
449 ARM_PROC::IFlags getProcIFlags() const {
450 assert(Kind == ProcIFlags && "Invalid access!");
454 unsigned getMSRMask() const {
455 assert(Kind == MSRMask && "Invalid access!");
459 bool isCoprocNum() const { return Kind == CoprocNum; }
460 bool isCoprocReg() const { return Kind == CoprocReg; }
461 bool isCondCode() const { return Kind == CondCode; }
462 bool isCCOut() const { return Kind == CCOut; }
463 bool isITMask() const { return Kind == ITCondMask; }
464 bool isITCondCode() const { return Kind == CondCode; }
465 bool isImm() const { return Kind == Immediate; }
466 bool isImm8s4() const {
467 if (Kind != Immediate)
469 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
470 if (!CE) return false;
471 int64_t Value = CE->getValue();
472 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
474 bool isImm0_1020s4() const {
475 if (Kind != Immediate)
477 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
478 if (!CE) return false;
479 int64_t Value = CE->getValue();
480 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
482 bool isImm0_508s4() const {
483 if (Kind != Immediate)
485 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
486 if (!CE) return false;
487 int64_t Value = CE->getValue();
488 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
490 bool isImm0_255() const {
491 if (Kind != Immediate)
493 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
494 if (!CE) return false;
495 int64_t Value = CE->getValue();
496 return Value >= 0 && Value < 256;
498 bool isImm0_7() const {
499 if (Kind != Immediate)
501 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
502 if (!CE) return false;
503 int64_t Value = CE->getValue();
504 return Value >= 0 && Value < 8;
506 bool isImm0_15() const {
507 if (Kind != Immediate)
509 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
510 if (!CE) return false;
511 int64_t Value = CE->getValue();
512 return Value >= 0 && Value < 16;
514 bool isImm0_31() const {
515 if (Kind != Immediate)
517 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
518 if (!CE) return false;
519 int64_t Value = CE->getValue();
520 return Value >= 0 && Value < 32;
522 bool isImm1_16() const {
523 if (Kind != Immediate)
525 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
526 if (!CE) return false;
527 int64_t Value = CE->getValue();
528 return Value > 0 && Value < 17;
530 bool isImm1_32() const {
531 if (Kind != Immediate)
533 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
534 if (!CE) return false;
535 int64_t Value = CE->getValue();
536 return Value > 0 && Value < 33;
538 bool isImm0_65535() const {
539 if (Kind != Immediate)
541 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
542 if (!CE) return false;
543 int64_t Value = CE->getValue();
544 return Value >= 0 && Value < 65536;
546 bool isImm0_65535Expr() const {
547 if (Kind != Immediate)
549 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
550 // If it's not a constant expression, it'll generate a fixup and be
552 if (!CE) return true;
553 int64_t Value = CE->getValue();
554 return Value >= 0 && Value < 65536;
556 bool isImm24bit() const {
557 if (Kind != Immediate)
559 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
560 if (!CE) return false;
561 int64_t Value = CE->getValue();
562 return Value >= 0 && Value <= 0xffffff;
564 bool isImmThumbSR() const {
565 if (Kind != Immediate)
567 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
568 if (!CE) return false;
569 int64_t Value = CE->getValue();
570 return Value > 0 && Value < 33;
572 bool isPKHLSLImm() const {
573 if (Kind != Immediate)
575 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
576 if (!CE) return false;
577 int64_t Value = CE->getValue();
578 return Value >= 0 && Value < 32;
580 bool isPKHASRImm() const {
581 if (Kind != Immediate)
583 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
584 if (!CE) return false;
585 int64_t Value = CE->getValue();
586 return Value > 0 && Value <= 32;
588 bool isARMSOImm() const {
589 if (Kind != Immediate)
591 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
592 if (!CE) return false;
593 int64_t Value = CE->getValue();
594 return ARM_AM::getSOImmVal(Value) != -1;
596 bool isT2SOImm() const {
597 if (Kind != Immediate)
599 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
600 if (!CE) return false;
601 int64_t Value = CE->getValue();
602 return ARM_AM::getT2SOImmVal(Value) != -1;
604 bool isSetEndImm() const {
605 if (Kind != Immediate)
607 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
608 if (!CE) return false;
609 int64_t Value = CE->getValue();
610 return Value == 1 || Value == 0;
612 bool isReg() const { return Kind == Register; }
613 bool isRegList() const { return Kind == RegisterList; }
614 bool isDPRRegList() const { return Kind == DPRRegisterList; }
615 bool isSPRRegList() const { return Kind == SPRRegisterList; }
616 bool isToken() const { return Kind == Token; }
617 bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
618 bool isMemory() const { return Kind == Memory; }
619 bool isShifterImm() const { return Kind == ShifterImmediate; }
620 bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
621 bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
622 bool isRotImm() const { return Kind == RotateImmediate; }
623 bool isBitfield() const { return Kind == BitfieldDescriptor; }
624 bool isPostIdxRegShifted() const { return Kind == PostIndexRegister; }
625 bool isPostIdxReg() const {
626 return Kind == PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
628 bool isMemNoOffset() const {
631 // No offset of any kind.
632 return Mem.OffsetRegNum == 0 && Mem.OffsetImm == 0;
634 bool isAddrMode2() const {
637 // Check for register offset.
638 if (Mem.OffsetRegNum) return true;
639 // Immediate offset in range [-4095, 4095].
640 if (!Mem.OffsetImm) return true;
641 int64_t Val = Mem.OffsetImm->getValue();
642 return Val > -4096 && Val < 4096;
644 bool isAM2OffsetImm() const {
645 if (Kind != Immediate)
647 // Immediate offset in range [-4095, 4095].
648 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
649 if (!CE) return false;
650 int64_t Val = CE->getValue();
651 return Val > -4096 && Val < 4096;
653 bool isAddrMode3() const {
656 // No shifts are legal for AM3.
657 if (Mem.ShiftType != ARM_AM::no_shift) return false;
658 // Check for register offset.
659 if (Mem.OffsetRegNum) return true;
660 // Immediate offset in range [-255, 255].
661 if (!Mem.OffsetImm) return true;
662 int64_t Val = Mem.OffsetImm->getValue();
663 return Val > -256 && Val < 256;
665 bool isAM3Offset() const {
666 if (Kind != Immediate && Kind != PostIndexRegister)
668 if (Kind == PostIndexRegister)
669 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
670 // Immediate offset in range [-255, 255].
671 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
672 if (!CE) return false;
673 int64_t Val = CE->getValue();
674 // Special case, #-0 is INT32_MIN.
675 return (Val > -256 && Val < 256) || Val == INT32_MIN;
677 bool isAddrMode5() const {
680 // Check for register offset.
681 if (Mem.OffsetRegNum) return false;
682 // Immediate offset in range [-1020, 1020] and a multiple of 4.
683 if (!Mem.OffsetImm) return true;
684 int64_t Val = Mem.OffsetImm->getValue();
685 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
688 bool isMemRegOffset() const {
689 if (Kind != Memory || !Mem.OffsetRegNum)
693 bool isT2MemRegOffset() const {
694 if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative)
696 // Only lsl #{0, 1, 2, 3} allowed.
697 if (Mem.ShiftType == ARM_AM::no_shift)
699 if (Mem.ShiftType != ARM_AM::lsl || Mem.ShiftImm > 3)
703 bool isMemThumbRR() const {
704 // Thumb reg+reg addressing is simple. Just two registers, a base and
705 // an offset. No shifts, negations or any other complicating factors.
706 if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative ||
707 Mem.ShiftType != ARM_AM::no_shift)
709 return isARMLowRegister(Mem.BaseRegNum) &&
710 (!Mem.OffsetRegNum || isARMLowRegister(Mem.OffsetRegNum));
712 bool isMemThumbRIs4() const {
713 if (Kind != Memory || Mem.OffsetRegNum != 0 ||
714 !isARMLowRegister(Mem.BaseRegNum))
716 // Immediate offset, multiple of 4 in range [0, 124].
717 if (!Mem.OffsetImm) return true;
718 int64_t Val = Mem.OffsetImm->getValue();
719 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
721 bool isMemThumbRIs2() const {
722 if (Kind != Memory || Mem.OffsetRegNum != 0 ||
723 !isARMLowRegister(Mem.BaseRegNum))
725 // Immediate offset, multiple of 4 in range [0, 62].
726 if (!Mem.OffsetImm) return true;
727 int64_t Val = Mem.OffsetImm->getValue();
728 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
730 bool isMemThumbRIs1() const {
731 if (Kind != Memory || Mem.OffsetRegNum != 0 ||
732 !isARMLowRegister(Mem.BaseRegNum))
734 // Immediate offset in range [0, 31].
735 if (!Mem.OffsetImm) return true;
736 int64_t Val = Mem.OffsetImm->getValue();
737 return Val >= 0 && Val <= 31;
739 bool isMemThumbSPI() const {
740 if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP)
742 // Immediate offset, multiple of 4 in range [0, 1020].
743 if (!Mem.OffsetImm) return true;
744 int64_t Val = Mem.OffsetImm->getValue();
745 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
747 bool isMemImm8s4Offset() const {
748 if (Kind != Memory || Mem.OffsetRegNum != 0)
750 // Immediate offset a multiple of 4 in range [-1020, 1020].
751 if (!Mem.OffsetImm) return true;
752 int64_t Val = Mem.OffsetImm->getValue();
753 return Val >= -1020 && Val <= 1020 && (Val & 3) == 0;
755 bool isMemImm0_1020s4Offset() const {
756 if (Kind != Memory || Mem.OffsetRegNum != 0)
758 // Immediate offset a multiple of 4 in range [0, 1020].
759 if (!Mem.OffsetImm) return true;
760 int64_t Val = Mem.OffsetImm->getValue();
761 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
763 bool isMemImm8Offset() const {
764 if (Kind != Memory || Mem.OffsetRegNum != 0)
766 // Immediate offset in range [-255, 255].
767 if (!Mem.OffsetImm) return true;
768 int64_t Val = Mem.OffsetImm->getValue();
769 return Val > -256 && Val < 256;
771 bool isMemPosImm8Offset() const {
772 if (Kind != Memory || Mem.OffsetRegNum != 0)
774 // Immediate offset in range [0, 255].
775 if (!Mem.OffsetImm) return true;
776 int64_t Val = Mem.OffsetImm->getValue();
777 return Val >= 0 && Val < 256;
779 bool isMemNegImm8Offset() const {
780 if (Kind != Memory || Mem.OffsetRegNum != 0)
782 // Immediate offset in range [-255, -1].
783 if (!Mem.OffsetImm) return true;
784 int64_t Val = Mem.OffsetImm->getValue();
785 return Val > -256 && Val < 0;
787 bool isMemUImm12Offset() const {
788 // If we have an immediate that's not a constant, treat it as a label
789 // reference needing a fixup. If it is a constant, it's something else
791 if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
794 if (Kind != Memory || Mem.OffsetRegNum != 0)
796 // Immediate offset in range [0, 4095].
797 if (!Mem.OffsetImm) return true;
798 int64_t Val = Mem.OffsetImm->getValue();
799 return (Val >= 0 && Val < 4096);
801 bool isMemImm12Offset() const {
802 // If we have an immediate that's not a constant, treat it as a label
803 // reference needing a fixup. If it is a constant, it's something else
805 if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
808 if (Kind != Memory || Mem.OffsetRegNum != 0)
810 // Immediate offset in range [-4095, 4095].
811 if (!Mem.OffsetImm) return true;
812 int64_t Val = Mem.OffsetImm->getValue();
813 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
815 bool isPostIdxImm8() const {
816 if (Kind != Immediate)
818 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
819 if (!CE) return false;
820 int64_t Val = CE->getValue();
821 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
824 bool isMSRMask() const { return Kind == MSRMask; }
825 bool isProcIFlags() const { return Kind == ProcIFlags; }
827 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
828 // Add as immediates when possible. Null MCExpr = 0.
830 Inst.addOperand(MCOperand::CreateImm(0));
831 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
832 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
834 Inst.addOperand(MCOperand::CreateExpr(Expr));
837 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
838 assert(N == 2 && "Invalid number of operands!");
839 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
840 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
841 Inst.addOperand(MCOperand::CreateReg(RegNum));
844 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
845 assert(N == 1 && "Invalid number of operands!");
846 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
849 void addITMaskOperands(MCInst &Inst, unsigned N) const {
850 assert(N == 1 && "Invalid number of operands!");
851 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
854 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
855 assert(N == 1 && "Invalid number of operands!");
856 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
859 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
860 assert(N == 1 && "Invalid number of operands!");
861 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
864 void addCCOutOperands(MCInst &Inst, unsigned N) const {
865 assert(N == 1 && "Invalid number of operands!");
866 Inst.addOperand(MCOperand::CreateReg(getReg()));
869 void addRegOperands(MCInst &Inst, unsigned N) const {
870 assert(N == 1 && "Invalid number of operands!");
871 Inst.addOperand(MCOperand::CreateReg(getReg()));
874 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
875 assert(N == 3 && "Invalid number of operands!");
876 assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
877 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
878 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
879 Inst.addOperand(MCOperand::CreateImm(
880 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
883 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
884 assert(N == 2 && "Invalid number of operands!");
885 assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
886 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
887 Inst.addOperand(MCOperand::CreateImm(
888 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
891 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
892 assert(N == 1 && "Invalid number of operands!");
893 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
897 void addRegListOperands(MCInst &Inst, unsigned N) const {
898 assert(N == 1 && "Invalid number of operands!");
899 const SmallVectorImpl<unsigned> &RegList = getRegList();
900 for (SmallVectorImpl<unsigned>::const_iterator
901 I = RegList.begin(), E = RegList.end(); I != E; ++I)
902 Inst.addOperand(MCOperand::CreateReg(*I));
905 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
906 addRegListOperands(Inst, N);
909 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
910 addRegListOperands(Inst, N);
913 void addRotImmOperands(MCInst &Inst, unsigned N) const {
914 assert(N == 1 && "Invalid number of operands!");
915 // Encoded as val>>3. The printer handles display as 8, 16, 24.
916 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
919 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
920 assert(N == 1 && "Invalid number of operands!");
921 // Munge the lsb/width into a bitfield mask.
922 unsigned lsb = Bitfield.LSB;
923 unsigned width = Bitfield.Width;
924 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
925 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
926 (32 - (lsb + width)));
927 Inst.addOperand(MCOperand::CreateImm(Mask));
930 void addImmOperands(MCInst &Inst, unsigned N) const {
931 assert(N == 1 && "Invalid number of operands!");
932 addExpr(Inst, getImm());
935 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
936 assert(N == 1 && "Invalid number of operands!");
937 // FIXME: We really want to scale the value here, but the LDRD/STRD
938 // instruction don't encode operands that way yet.
939 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
940 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
943 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
944 assert(N == 1 && "Invalid number of operands!");
945 // The immediate is scaled by four in the encoding and is stored
946 // in the MCInst as such. Lop off the low two bits here.
947 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
948 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
951 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
952 assert(N == 1 && "Invalid number of operands!");
953 // The immediate is scaled by four in the encoding and is stored
954 // in the MCInst as such. Lop off the low two bits here.
955 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
956 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
959 void addImm0_255Operands(MCInst &Inst, unsigned N) const {
960 assert(N == 1 && "Invalid number of operands!");
961 addExpr(Inst, getImm());
964 void addImm0_7Operands(MCInst &Inst, unsigned N) const {
965 assert(N == 1 && "Invalid number of operands!");
966 addExpr(Inst, getImm());
969 void addImm0_15Operands(MCInst &Inst, unsigned N) const {
970 assert(N == 1 && "Invalid number of operands!");
971 addExpr(Inst, getImm());
974 void addImm0_31Operands(MCInst &Inst, unsigned N) const {
975 assert(N == 1 && "Invalid number of operands!");
976 addExpr(Inst, getImm());
979 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
980 assert(N == 1 && "Invalid number of operands!");
981 // The constant encodes as the immediate-1, and we store in the instruction
982 // the bits as encoded, so subtract off one here.
983 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
984 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
987 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
988 assert(N == 1 && "Invalid number of operands!");
989 // The constant encodes as the immediate-1, and we store in the instruction
990 // the bits as encoded, so subtract off one here.
991 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
992 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
995 void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
996 assert(N == 1 && "Invalid number of operands!");
997 addExpr(Inst, getImm());
1000 void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
1001 assert(N == 1 && "Invalid number of operands!");
1002 addExpr(Inst, getImm());
1005 void addImm24bitOperands(MCInst &Inst, unsigned N) const {
1006 assert(N == 1 && "Invalid number of operands!");
1007 addExpr(Inst, getImm());
1010 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1011 assert(N == 1 && "Invalid number of operands!");
1012 // The constant encodes as the immediate, except for 32, which encodes as
1014 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1015 unsigned Imm = CE->getValue();
1016 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1019 void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
1020 assert(N == 1 && "Invalid number of operands!");
1021 addExpr(Inst, getImm());
1024 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1025 assert(N == 1 && "Invalid number of operands!");
1026 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1027 // the instruction as well.
1028 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1029 int Val = CE->getValue();
1030 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1033 void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
1034 assert(N == 1 && "Invalid number of operands!");
1035 addExpr(Inst, getImm());
1038 void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
1039 assert(N == 1 && "Invalid number of operands!");
1040 addExpr(Inst, getImm());
1043 void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
1044 assert(N == 1 && "Invalid number of operands!");
1045 addExpr(Inst, getImm());
1048 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1049 assert(N == 1 && "Invalid number of operands!");
1050 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1053 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1054 assert(N == 1 && "Invalid number of operands!");
1055 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1058 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1059 assert(N == 3 && "Invalid number of operands!");
1060 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1061 if (!Mem.OffsetRegNum) {
1062 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1063 // Special case for #-0
1064 if (Val == INT32_MIN) Val = 0;
1065 if (Val < 0) Val = -Val;
1066 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1068 // For register offset, we encode the shift type and negation flag
1070 Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
1071 Mem.ShiftImm, Mem.ShiftType);
1073 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1074 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1075 Inst.addOperand(MCOperand::CreateImm(Val));
1078 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1079 assert(N == 2 && "Invalid number of operands!");
1080 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1081 assert(CE && "non-constant AM2OffsetImm operand!");
1082 int32_t Val = CE->getValue();
1083 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1084 // Special case for #-0
1085 if (Val == INT32_MIN) Val = 0;
1086 if (Val < 0) Val = -Val;
1087 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1088 Inst.addOperand(MCOperand::CreateReg(0));
1089 Inst.addOperand(MCOperand::CreateImm(Val));
1092 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1093 assert(N == 3 && "Invalid number of operands!");
1094 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1095 if (!Mem.OffsetRegNum) {
1096 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1097 // Special case for #-0
1098 if (Val == INT32_MIN) Val = 0;
1099 if (Val < 0) Val = -Val;
1100 Val = ARM_AM::getAM3Opc(AddSub, Val);
1102 // For register offset, we encode the shift type and negation flag
1104 Val = ARM_AM::getAM3Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1106 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1107 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1108 Inst.addOperand(MCOperand::CreateImm(Val));
1111 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1112 assert(N == 2 && "Invalid number of operands!");
1113 if (Kind == PostIndexRegister) {
1115 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1116 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1117 Inst.addOperand(MCOperand::CreateImm(Val));
1122 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1123 int32_t Val = CE->getValue();
1124 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1125 // Special case for #-0
1126 if (Val == INT32_MIN) Val = 0;
1127 if (Val < 0) Val = -Val;
1128 Val = ARM_AM::getAM3Opc(AddSub, Val);
1129 Inst.addOperand(MCOperand::CreateReg(0));
1130 Inst.addOperand(MCOperand::CreateImm(Val));
1133 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1134 assert(N == 2 && "Invalid number of operands!");
1135 // The lower two bits are always zero and as such are not encoded.
1136 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0;
1137 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1138 // Special case for #-0
1139 if (Val == INT32_MIN) Val = 0;
1140 if (Val < 0) Val = -Val;
1141 Val = ARM_AM::getAM5Opc(AddSub, Val);
1142 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1143 Inst.addOperand(MCOperand::CreateImm(Val));
1146 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1147 assert(N == 2 && "Invalid number of operands!");
1148 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1149 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1150 Inst.addOperand(MCOperand::CreateImm(Val));
1153 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1154 assert(N == 2 && "Invalid number of operands!");
1155 // The lower two bits are always zero and as such are not encoded.
1156 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0;
1157 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1158 Inst.addOperand(MCOperand::CreateImm(Val));
1161 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1162 assert(N == 2 && "Invalid number of operands!");
1163 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1164 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1165 Inst.addOperand(MCOperand::CreateImm(Val));
1168 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1169 addMemImm8OffsetOperands(Inst, N);
1172 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1173 addMemImm8OffsetOperands(Inst, N);
1176 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1177 assert(N == 2 && "Invalid number of operands!");
1178 // If this is an immediate, it's a label reference.
1179 if (Kind == Immediate) {
1180 addExpr(Inst, getImm());
1181 Inst.addOperand(MCOperand::CreateImm(0));
1185 // Otherwise, it's a normal memory reg+offset.
1186 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1187 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1188 Inst.addOperand(MCOperand::CreateImm(Val));
1191 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1192 assert(N == 2 && "Invalid number of operands!");
1193 // If this is an immediate, it's a label reference.
1194 if (Kind == Immediate) {
1195 addExpr(Inst, getImm());
1196 Inst.addOperand(MCOperand::CreateImm(0));
1200 // Otherwise, it's a normal memory reg+offset.
1201 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1202 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1203 Inst.addOperand(MCOperand::CreateImm(Val));
1206 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1207 assert(N == 3 && "Invalid number of operands!");
1208 unsigned Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
1209 Mem.ShiftImm, Mem.ShiftType);
1210 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1211 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1212 Inst.addOperand(MCOperand::CreateImm(Val));
1215 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1216 assert(N == 3 && "Invalid number of operands!");
1217 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1218 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1219 Inst.addOperand(MCOperand::CreateImm(Mem.ShiftImm));
1222 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1223 assert(N == 2 && "Invalid number of operands!");
1224 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1225 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1228 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1229 assert(N == 2 && "Invalid number of operands!");
1230 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1231 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1232 Inst.addOperand(MCOperand::CreateImm(Val));
1235 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1236 assert(N == 2 && "Invalid number of operands!");
1237 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 2) : 0;
1238 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1239 Inst.addOperand(MCOperand::CreateImm(Val));
1242 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1243 assert(N == 2 && "Invalid number of operands!");
1244 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue()) : 0;
1245 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1246 Inst.addOperand(MCOperand::CreateImm(Val));
1249 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1250 assert(N == 2 && "Invalid number of operands!");
1251 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1252 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1253 Inst.addOperand(MCOperand::CreateImm(Val));
1256 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1257 assert(N == 1 && "Invalid number of operands!");
1258 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1259 assert(CE && "non-constant post-idx-imm8 operand!");
1260 int Imm = CE->getValue();
1261 bool isAdd = Imm >= 0;
1262 if (Imm == INT32_MIN) Imm = 0;
1263 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1264 Inst.addOperand(MCOperand::CreateImm(Imm));
1267 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1268 assert(N == 2 && "Invalid number of operands!");
1269 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1270 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1273 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1274 assert(N == 2 && "Invalid number of operands!");
1275 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1276 // The sign, shift type, and shift amount are encoded in a single operand
1277 // using the AM2 encoding helpers.
1278 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1279 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1280 PostIdxReg.ShiftTy);
1281 Inst.addOperand(MCOperand::CreateImm(Imm));
1284 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1285 assert(N == 1 && "Invalid number of operands!");
1286 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1289 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1290 assert(N == 1 && "Invalid number of operands!");
1291 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1294 virtual void print(raw_ostream &OS) const;
1296 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
1297 ARMOperand *Op = new ARMOperand(ITCondMask);
1298 Op->ITMask.Mask = Mask;
1304 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1305 ARMOperand *Op = new ARMOperand(CondCode);
1312 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1313 ARMOperand *Op = new ARMOperand(CoprocNum);
1314 Op->Cop.Val = CopVal;
1320 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1321 ARMOperand *Op = new ARMOperand(CoprocReg);
1322 Op->Cop.Val = CopVal;
1328 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1329 ARMOperand *Op = new ARMOperand(CCOut);
1330 Op->Reg.RegNum = RegNum;
1336 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1337 ARMOperand *Op = new ARMOperand(Token);
1338 Op->Tok.Data = Str.data();
1339 Op->Tok.Length = Str.size();
1345 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1346 ARMOperand *Op = new ARMOperand(Register);
1347 Op->Reg.RegNum = RegNum;
1353 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1358 ARMOperand *Op = new ARMOperand(ShiftedRegister);
1359 Op->RegShiftedReg.ShiftTy = ShTy;
1360 Op->RegShiftedReg.SrcReg = SrcReg;
1361 Op->RegShiftedReg.ShiftReg = ShiftReg;
1362 Op->RegShiftedReg.ShiftImm = ShiftImm;
1368 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1372 ARMOperand *Op = new ARMOperand(ShiftedImmediate);
1373 Op->RegShiftedImm.ShiftTy = ShTy;
1374 Op->RegShiftedImm.SrcReg = SrcReg;
1375 Op->RegShiftedImm.ShiftImm = ShiftImm;
1381 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1383 ARMOperand *Op = new ARMOperand(ShifterImmediate);
1384 Op->ShifterImm.isASR = isASR;
1385 Op->ShifterImm.Imm = Imm;
1391 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1392 ARMOperand *Op = new ARMOperand(RotateImmediate);
1393 Op->RotImm.Imm = Imm;
1399 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1401 ARMOperand *Op = new ARMOperand(BitfieldDescriptor);
1402 Op->Bitfield.LSB = LSB;
1403 Op->Bitfield.Width = Width;
1410 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1411 SMLoc StartLoc, SMLoc EndLoc) {
1412 KindTy Kind = RegisterList;
1414 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
1415 Kind = DPRRegisterList;
1416 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
1417 contains(Regs.front().first))
1418 Kind = SPRRegisterList;
1420 ARMOperand *Op = new ARMOperand(Kind);
1421 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1422 I = Regs.begin(), E = Regs.end(); I != E; ++I)
1423 Op->Registers.push_back(I->first);
1424 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1425 Op->StartLoc = StartLoc;
1426 Op->EndLoc = EndLoc;
1430 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1431 ARMOperand *Op = new ARMOperand(Immediate);
1438 static ARMOperand *CreateMem(unsigned BaseRegNum,
1439 const MCConstantExpr *OffsetImm,
1440 unsigned OffsetRegNum,
1441 ARM_AM::ShiftOpc ShiftType,
1445 ARMOperand *Op = new ARMOperand(Memory);
1446 Op->Mem.BaseRegNum = BaseRegNum;
1447 Op->Mem.OffsetImm = OffsetImm;
1448 Op->Mem.OffsetRegNum = OffsetRegNum;
1449 Op->Mem.ShiftType = ShiftType;
1450 Op->Mem.ShiftImm = ShiftImm;
1451 Op->Mem.isNegative = isNegative;
1457 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1458 ARM_AM::ShiftOpc ShiftTy,
1461 ARMOperand *Op = new ARMOperand(PostIndexRegister);
1462 Op->PostIdxReg.RegNum = RegNum;
1463 Op->PostIdxReg.isAdd = isAdd;
1464 Op->PostIdxReg.ShiftTy = ShiftTy;
1465 Op->PostIdxReg.ShiftImm = ShiftImm;
1471 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1472 ARMOperand *Op = new ARMOperand(MemBarrierOpt);
1473 Op->MBOpt.Val = Opt;
1479 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1480 ARMOperand *Op = new ARMOperand(ProcIFlags);
1481 Op->IFlags.Val = IFlags;
1487 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1488 ARMOperand *Op = new ARMOperand(MSRMask);
1489 Op->MMask.Val = MMask;
1496 } // end anonymous namespace.
1498 void ARMOperand::print(raw_ostream &OS) const {
1501 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1504 OS << "<ccout " << getReg() << ">";
1507 static char MaskStr[][6] = { "()", "(t)", "(e)", "(tt)", "(et)", "(te)",
1508 "(ee)", "(ttt)", "(ett)", "(tet)", "(eet)", "(tte)", "(ete)",
1510 assert((ITMask.Mask & 0xf) == ITMask.Mask);
1511 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
1515 OS << "<coprocessor number: " << getCoproc() << ">";
1518 OS << "<coprocessor register: " << getCoproc() << ">";
1521 OS << "<mask: " << getMSRMask() << ">";
1524 getImm()->print(OS);
1527 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1531 << " base:" << Mem.BaseRegNum;
1534 case PostIndexRegister:
1535 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
1536 << PostIdxReg.RegNum;
1537 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1538 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1539 << PostIdxReg.ShiftImm;
1543 OS << "<ARM_PROC::";
1544 unsigned IFlags = getProcIFlags();
1545 for (int i=2; i >= 0; --i)
1546 if (IFlags & (1 << i))
1547 OS << ARM_PROC::IFlagsToString(1 << i);
1552 OS << "<register " << getReg() << ">";
1554 case ShifterImmediate:
1555 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1556 << " #" << ShifterImm.Imm << ">";
1558 case ShiftedRegister:
1559 OS << "<so_reg_reg "
1560 << RegShiftedReg.SrcReg
1561 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1562 << ", " << RegShiftedReg.ShiftReg << ", "
1563 << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1566 case ShiftedImmediate:
1567 OS << "<so_reg_imm "
1568 << RegShiftedImm.SrcReg
1569 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1570 << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
1573 case RotateImmediate:
1574 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
1576 case BitfieldDescriptor:
1577 OS << "<bitfield " << "lsb: " << Bitfield.LSB
1578 << ", width: " << Bitfield.Width << ">";
1581 case DPRRegisterList:
1582 case SPRRegisterList: {
1583 OS << "<register_list ";
1585 const SmallVectorImpl<unsigned> &RegList = getRegList();
1586 for (SmallVectorImpl<unsigned>::const_iterator
1587 I = RegList.begin(), E = RegList.end(); I != E; ) {
1589 if (++I < E) OS << ", ";
1596 OS << "'" << getToken() << "'";
1601 /// @name Auto-generated Match Functions
1604 static unsigned MatchRegisterName(StringRef Name);
1608 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
1609 SMLoc &StartLoc, SMLoc &EndLoc) {
1610 RegNo = tryParseRegister();
1612 return (RegNo == (unsigned)-1);
1615 /// Try to parse a register name. The token must be an Identifier when called,
1616 /// and if it is a register name the token is eaten and the register number is
1617 /// returned. Otherwise return -1.
1619 int ARMAsmParser::tryParseRegister() {
1620 const AsmToken &Tok = Parser.getTok();
1621 if (Tok.isNot(AsmToken::Identifier)) return -1;
1623 // FIXME: Validate register for the current architecture; we have to do
1624 // validation later, so maybe there is no need for this here.
1625 std::string upperCase = Tok.getString().str();
1626 std::string lowerCase = LowercaseString(upperCase);
1627 unsigned RegNum = MatchRegisterName(lowerCase);
1629 RegNum = StringSwitch<unsigned>(lowerCase)
1630 .Case("r13", ARM::SP)
1631 .Case("r14", ARM::LR)
1632 .Case("r15", ARM::PC)
1633 .Case("ip", ARM::R12)
1636 if (!RegNum) return -1;
1638 Parser.Lex(); // Eat identifier token.
1642 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
1643 // If a recoverable error occurs, return 1. If an irrecoverable error
1644 // occurs, return -1. An irrecoverable error is one where tokens have been
1645 // consumed in the process of trying to parse the shifter (i.e., when it is
1646 // indeed a shifter operand, but malformed).
1647 int ARMAsmParser::tryParseShiftRegister(
1648 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1649 SMLoc S = Parser.getTok().getLoc();
1650 const AsmToken &Tok = Parser.getTok();
1651 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1653 std::string upperCase = Tok.getString().str();
1654 std::string lowerCase = LowercaseString(upperCase);
1655 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
1656 .Case("lsl", ARM_AM::lsl)
1657 .Case("lsr", ARM_AM::lsr)
1658 .Case("asr", ARM_AM::asr)
1659 .Case("ror", ARM_AM::ror)
1660 .Case("rrx", ARM_AM::rrx)
1661 .Default(ARM_AM::no_shift);
1663 if (ShiftTy == ARM_AM::no_shift)
1666 Parser.Lex(); // Eat the operator.
1668 // The source register for the shift has already been added to the
1669 // operand list, so we need to pop it off and combine it into the shifted
1670 // register operand instead.
1671 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
1672 if (!PrevOp->isReg())
1673 return Error(PrevOp->getStartLoc(), "shift must be of a register");
1674 int SrcReg = PrevOp->getReg();
1677 if (ShiftTy == ARM_AM::rrx) {
1678 // RRX Doesn't have an explicit shift amount. The encoder expects
1679 // the shift register to be the same as the source register. Seems odd,
1683 // Figure out if this is shifted by a constant or a register (for non-RRX).
1684 if (Parser.getTok().is(AsmToken::Hash)) {
1685 Parser.Lex(); // Eat hash.
1686 SMLoc ImmLoc = Parser.getTok().getLoc();
1687 const MCExpr *ShiftExpr = 0;
1688 if (getParser().ParseExpression(ShiftExpr)) {
1689 Error(ImmLoc, "invalid immediate shift value");
1692 // The expression must be evaluatable as an immediate.
1693 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
1695 Error(ImmLoc, "invalid immediate shift value");
1698 // Range check the immediate.
1699 // lsl, ror: 0 <= imm <= 31
1700 // lsr, asr: 0 <= imm <= 32
1701 Imm = CE->getValue();
1703 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
1704 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
1705 Error(ImmLoc, "immediate shift value out of range");
1708 } else if (Parser.getTok().is(AsmToken::Identifier)) {
1709 ShiftReg = tryParseRegister();
1710 SMLoc L = Parser.getTok().getLoc();
1711 if (ShiftReg == -1) {
1712 Error (L, "expected immediate or register in shift operand");
1716 Error (Parser.getTok().getLoc(),
1717 "expected immediate or register in shift operand");
1722 if (ShiftReg && ShiftTy != ARM_AM::rrx)
1723 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
1725 S, Parser.getTok().getLoc()));
1727 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
1728 S, Parser.getTok().getLoc()));
1734 /// Try to parse a register name. The token must be an Identifier when called.
1735 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
1736 /// if there is a "writeback". 'true' if it's not a register.
1738 /// TODO this is likely to change to allow different register types and or to
1739 /// parse for a specific register type.
1741 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1742 SMLoc S = Parser.getTok().getLoc();
1743 int RegNo = tryParseRegister();
1747 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1749 const AsmToken &ExclaimTok = Parser.getTok();
1750 if (ExclaimTok.is(AsmToken::Exclaim)) {
1751 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
1752 ExclaimTok.getLoc()));
1753 Parser.Lex(); // Eat exclaim token
1759 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
1760 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
1762 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
1763 // Use the same layout as the tablegen'erated register name matcher. Ugly,
1765 switch (Name.size()) {
1768 if (Name[0] != CoprocOp)
1785 if (Name[0] != CoprocOp || Name[1] != '1')
1789 case '0': return 10;
1790 case '1': return 11;
1791 case '2': return 12;
1792 case '3': return 13;
1793 case '4': return 14;
1794 case '5': return 15;
1802 /// parseITCondCode - Try to parse a condition code for an IT instruction.
1803 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1804 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1805 SMLoc S = Parser.getTok().getLoc();
1806 const AsmToken &Tok = Parser.getTok();
1807 if (!Tok.is(AsmToken::Identifier))
1808 return MatchOperand_NoMatch;
1809 unsigned CC = StringSwitch<unsigned>(Tok.getString())
1810 .Case("eq", ARMCC::EQ)
1811 .Case("ne", ARMCC::NE)
1812 .Case("hs", ARMCC::HS)
1813 .Case("cs", ARMCC::HS)
1814 .Case("lo", ARMCC::LO)
1815 .Case("cc", ARMCC::LO)
1816 .Case("mi", ARMCC::MI)
1817 .Case("pl", ARMCC::PL)
1818 .Case("vs", ARMCC::VS)
1819 .Case("vc", ARMCC::VC)
1820 .Case("hi", ARMCC::HI)
1821 .Case("ls", ARMCC::LS)
1822 .Case("ge", ARMCC::GE)
1823 .Case("lt", ARMCC::LT)
1824 .Case("gt", ARMCC::GT)
1825 .Case("le", ARMCC::LE)
1826 .Case("al", ARMCC::AL)
1829 return MatchOperand_NoMatch;
1830 Parser.Lex(); // Eat the token.
1832 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
1834 return MatchOperand_Success;
1837 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
1838 /// token must be an Identifier when called, and if it is a coprocessor
1839 /// number, the token is eaten and the operand is added to the operand list.
1840 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1841 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1842 SMLoc S = Parser.getTok().getLoc();
1843 const AsmToken &Tok = Parser.getTok();
1844 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1846 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
1848 return MatchOperand_NoMatch;
1850 Parser.Lex(); // Eat identifier token.
1851 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
1852 return MatchOperand_Success;
1855 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
1856 /// token must be an Identifier when called, and if it is a coprocessor
1857 /// number, the token is eaten and the operand is added to the operand list.
1858 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1859 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1860 SMLoc S = Parser.getTok().getLoc();
1861 const AsmToken &Tok = Parser.getTok();
1862 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1864 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
1866 return MatchOperand_NoMatch;
1868 Parser.Lex(); // Eat identifier token.
1869 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
1870 return MatchOperand_Success;
1873 // For register list parsing, we need to map from raw GPR register numbering
1874 // to the enumeration values. The enumeration values aren't sorted by
1875 // register number due to our using "sp", "lr" and "pc" as canonical names.
1876 static unsigned getNextRegister(unsigned Reg) {
1877 // If this is a GPR, we need to do it manually, otherwise we can rely
1878 // on the sort ordering of the enumeration since the other reg-classes
1880 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
1883 default: assert(0 && "Invalid GPR number!");
1884 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
1885 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
1886 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
1887 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
1888 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
1889 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
1890 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
1891 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
1895 /// Parse a register list.
1897 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1898 assert(Parser.getTok().is(AsmToken::LCurly) &&
1899 "Token is not a Left Curly Brace");
1900 SMLoc S = Parser.getTok().getLoc();
1901 Parser.Lex(); // Eat '{' token.
1902 SMLoc RegLoc = Parser.getTok().getLoc();
1904 // Check the first register in the list to see what register class
1905 // this is a list of.
1906 int Reg = tryParseRegister();
1908 return Error(RegLoc, "register expected");
1910 MCRegisterClass *RC;
1911 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
1912 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
1913 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
1914 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
1915 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
1916 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
1918 return Error(RegLoc, "invalid register in register list");
1920 // The reglist instructions have at most 16 registers, so reserve
1921 // space for that many.
1922 SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
1923 // Store the first register.
1924 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
1926 // This starts immediately after the first register token in the list,
1927 // so we can see either a comma or a minus (range separator) as a legal
1929 while (Parser.getTok().is(AsmToken::Comma) ||
1930 Parser.getTok().is(AsmToken::Minus)) {
1931 if (Parser.getTok().is(AsmToken::Minus)) {
1932 Parser.Lex(); // Eat the comma.
1933 SMLoc EndLoc = Parser.getTok().getLoc();
1934 int EndReg = tryParseRegister();
1936 return Error(EndLoc, "register expected");
1937 // If the register is the same as the start reg, there's nothing
1941 // The register must be in the same register class as the first.
1942 if (!RC->contains(EndReg))
1943 return Error(EndLoc, "invalid register in register list");
1944 // Ranges must go from low to high.
1945 if (getARMRegisterNumbering(Reg) > getARMRegisterNumbering(EndReg))
1946 return Error(EndLoc, "bad range in register list");
1948 // Add all the registers in the range to the register list.
1949 while (Reg != EndReg) {
1950 Reg = getNextRegister(Reg);
1951 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
1955 Parser.Lex(); // Eat the comma.
1956 RegLoc = Parser.getTok().getLoc();
1958 Reg = tryParseRegister();
1960 return Error(RegLoc, "register expected");
1961 // The register must be in the same register class as the first.
1962 if (!RC->contains(Reg))
1963 return Error(RegLoc, "invalid register in register list");
1964 // List must be monotonically increasing.
1965 if (getARMRegisterNumbering(Reg) <= getARMRegisterNumbering(OldReg))
1966 return Error(RegLoc, "register list not in ascending order");
1967 // VFP register lists must also be contiguous.
1968 // It's OK to use the enumeration values directly here rather, as the
1969 // VFP register classes have the enum sorted properly.
1970 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
1972 return Error(RegLoc, "non-contiguous register range");
1973 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
1976 SMLoc E = Parser.getTok().getLoc();
1977 if (Parser.getTok().isNot(AsmToken::RCurly))
1978 return Error(E, "'}' expected");
1979 Parser.Lex(); // Eat '}' token.
1981 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
1985 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
1986 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1987 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1988 SMLoc S = Parser.getTok().getLoc();
1989 const AsmToken &Tok = Parser.getTok();
1990 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1991 StringRef OptStr = Tok.getString();
1993 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
1994 .Case("sy", ARM_MB::SY)
1995 .Case("st", ARM_MB::ST)
1996 .Case("sh", ARM_MB::ISH)
1997 .Case("ish", ARM_MB::ISH)
1998 .Case("shst", ARM_MB::ISHST)
1999 .Case("ishst", ARM_MB::ISHST)
2000 .Case("nsh", ARM_MB::NSH)
2001 .Case("un", ARM_MB::NSH)
2002 .Case("nshst", ARM_MB::NSHST)
2003 .Case("unst", ARM_MB::NSHST)
2004 .Case("osh", ARM_MB::OSH)
2005 .Case("oshst", ARM_MB::OSHST)
2009 return MatchOperand_NoMatch;
2011 Parser.Lex(); // Eat identifier token.
2012 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
2013 return MatchOperand_Success;
2016 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
2017 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2018 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2019 SMLoc S = Parser.getTok().getLoc();
2020 const AsmToken &Tok = Parser.getTok();
2021 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2022 StringRef IFlagsStr = Tok.getString();
2024 unsigned IFlags = 0;
2025 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
2026 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
2027 .Case("a", ARM_PROC::A)
2028 .Case("i", ARM_PROC::I)
2029 .Case("f", ARM_PROC::F)
2032 // If some specific iflag is already set, it means that some letter is
2033 // present more than once, this is not acceptable.
2034 if (Flag == ~0U || (IFlags & Flag))
2035 return MatchOperand_NoMatch;
2040 Parser.Lex(); // Eat identifier token.
2041 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
2042 return MatchOperand_Success;
2045 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
2046 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2047 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2048 SMLoc S = Parser.getTok().getLoc();
2049 const AsmToken &Tok = Parser.getTok();
2050 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2051 StringRef Mask = Tok.getString();
2053 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
2054 size_t Start = 0, Next = Mask.find('_');
2055 StringRef Flags = "";
2056 std::string SpecReg = LowercaseString(Mask.slice(Start, Next));
2057 if (Next != StringRef::npos)
2058 Flags = Mask.slice(Next+1, Mask.size());
2060 // FlagsVal contains the complete mask:
2062 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
2063 unsigned FlagsVal = 0;
2065 if (SpecReg == "apsr") {
2066 FlagsVal = StringSwitch<unsigned>(Flags)
2067 .Case("nzcvq", 0x8) // same as CPSR_f
2068 .Case("g", 0x4) // same as CPSR_s
2069 .Case("nzcvqg", 0xc) // same as CPSR_fs
2072 if (FlagsVal == ~0U) {
2074 return MatchOperand_NoMatch;
2076 FlagsVal = 8; // No flag
2078 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
2079 if (Flags == "all") // cpsr_all is an alias for cpsr_fc
2081 for (int i = 0, e = Flags.size(); i != e; ++i) {
2082 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
2089 // If some specific flag is already set, it means that some letter is
2090 // present more than once, this is not acceptable.
2091 if (FlagsVal == ~0U || (FlagsVal & Flag))
2092 return MatchOperand_NoMatch;
2095 } else // No match for special register.
2096 return MatchOperand_NoMatch;
2098 // Special register without flags are equivalent to "fc" flags.
2102 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
2103 if (SpecReg == "spsr")
2106 Parser.Lex(); // Eat identifier token.
2107 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
2108 return MatchOperand_Success;
2111 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2112 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
2113 int Low, int High) {
2114 const AsmToken &Tok = Parser.getTok();
2115 if (Tok.isNot(AsmToken::Identifier)) {
2116 Error(Parser.getTok().getLoc(), Op + " operand expected.");
2117 return MatchOperand_ParseFail;
2119 StringRef ShiftName = Tok.getString();
2120 std::string LowerOp = LowercaseString(Op);
2121 std::string UpperOp = UppercaseString(Op);
2122 if (ShiftName != LowerOp && ShiftName != UpperOp) {
2123 Error(Parser.getTok().getLoc(), Op + " operand expected.");
2124 return MatchOperand_ParseFail;
2126 Parser.Lex(); // Eat shift type token.
2128 // There must be a '#' and a shift amount.
2129 if (Parser.getTok().isNot(AsmToken::Hash)) {
2130 Error(Parser.getTok().getLoc(), "'#' expected");
2131 return MatchOperand_ParseFail;
2133 Parser.Lex(); // Eat hash token.
2135 const MCExpr *ShiftAmount;
2136 SMLoc Loc = Parser.getTok().getLoc();
2137 if (getParser().ParseExpression(ShiftAmount)) {
2138 Error(Loc, "illegal expression");
2139 return MatchOperand_ParseFail;
2141 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2143 Error(Loc, "constant expression expected");
2144 return MatchOperand_ParseFail;
2146 int Val = CE->getValue();
2147 if (Val < Low || Val > High) {
2148 Error(Loc, "immediate value out of range");
2149 return MatchOperand_ParseFail;
2152 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
2154 return MatchOperand_Success;
2157 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2158 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2159 const AsmToken &Tok = Parser.getTok();
2160 SMLoc S = Tok.getLoc();
2161 if (Tok.isNot(AsmToken::Identifier)) {
2162 Error(Tok.getLoc(), "'be' or 'le' operand expected");
2163 return MatchOperand_ParseFail;
2165 int Val = StringSwitch<int>(Tok.getString())
2169 Parser.Lex(); // Eat the token.
2172 Error(Tok.getLoc(), "'be' or 'le' operand expected");
2173 return MatchOperand_ParseFail;
2175 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
2177 S, Parser.getTok().getLoc()));
2178 return MatchOperand_Success;
2181 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
2182 /// instructions. Legal values are:
2183 /// lsl #n 'n' in [0,31]
2184 /// asr #n 'n' in [1,32]
2185 /// n == 32 encoded as n == 0.
2186 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2187 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2188 const AsmToken &Tok = Parser.getTok();
2189 SMLoc S = Tok.getLoc();
2190 if (Tok.isNot(AsmToken::Identifier)) {
2191 Error(S, "shift operator 'asr' or 'lsl' expected");
2192 return MatchOperand_ParseFail;
2194 StringRef ShiftName = Tok.getString();
2196 if (ShiftName == "lsl" || ShiftName == "LSL")
2198 else if (ShiftName == "asr" || ShiftName == "ASR")
2201 Error(S, "shift operator 'asr' or 'lsl' expected");
2202 return MatchOperand_ParseFail;
2204 Parser.Lex(); // Eat the operator.
2206 // A '#' and a shift amount.
2207 if (Parser.getTok().isNot(AsmToken::Hash)) {
2208 Error(Parser.getTok().getLoc(), "'#' expected");
2209 return MatchOperand_ParseFail;
2211 Parser.Lex(); // Eat hash token.
2213 const MCExpr *ShiftAmount;
2214 SMLoc E = Parser.getTok().getLoc();
2215 if (getParser().ParseExpression(ShiftAmount)) {
2216 Error(E, "malformed shift expression");
2217 return MatchOperand_ParseFail;
2219 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2221 Error(E, "shift amount must be an immediate");
2222 return MatchOperand_ParseFail;
2225 int64_t Val = CE->getValue();
2227 // Shift amount must be in [1,32]
2228 if (Val < 1 || Val > 32) {
2229 Error(E, "'asr' shift amount must be in range [1,32]");
2230 return MatchOperand_ParseFail;
2232 // asr #32 encoded as asr #0.
2233 if (Val == 32) Val = 0;
2235 // Shift amount must be in [1,32]
2236 if (Val < 0 || Val > 31) {
2237 Error(E, "'lsr' shift amount must be in range [0,31]");
2238 return MatchOperand_ParseFail;
2242 E = Parser.getTok().getLoc();
2243 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
2245 return MatchOperand_Success;
2248 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
2249 /// of instructions. Legal values are:
2250 /// ror #n 'n' in {0, 8, 16, 24}
2251 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2252 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2253 const AsmToken &Tok = Parser.getTok();
2254 SMLoc S = Tok.getLoc();
2255 if (Tok.isNot(AsmToken::Identifier)) {
2256 Error(S, "rotate operator 'ror' expected");
2257 return MatchOperand_ParseFail;
2259 StringRef ShiftName = Tok.getString();
2260 if (ShiftName != "ror" && ShiftName != "ROR") {
2261 Error(S, "rotate operator 'ror' expected");
2262 return MatchOperand_ParseFail;
2264 Parser.Lex(); // Eat the operator.
2266 // A '#' and a rotate amount.
2267 if (Parser.getTok().isNot(AsmToken::Hash)) {
2268 Error(Parser.getTok().getLoc(), "'#' expected");
2269 return MatchOperand_ParseFail;
2271 Parser.Lex(); // Eat hash token.
2273 const MCExpr *ShiftAmount;
2274 SMLoc E = Parser.getTok().getLoc();
2275 if (getParser().ParseExpression(ShiftAmount)) {
2276 Error(E, "malformed rotate expression");
2277 return MatchOperand_ParseFail;
2279 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2281 Error(E, "rotate amount must be an immediate");
2282 return MatchOperand_ParseFail;
2285 int64_t Val = CE->getValue();
2286 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
2287 // normally, zero is represented in asm by omitting the rotate operand
2289 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
2290 Error(E, "'ror' rotate amount must be 8, 16, or 24");
2291 return MatchOperand_ParseFail;
2294 E = Parser.getTok().getLoc();
2295 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
2297 return MatchOperand_Success;
2300 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2301 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2302 SMLoc S = Parser.getTok().getLoc();
2303 // The bitfield descriptor is really two operands, the LSB and the width.
2304 if (Parser.getTok().isNot(AsmToken::Hash)) {
2305 Error(Parser.getTok().getLoc(), "'#' expected");
2306 return MatchOperand_ParseFail;
2308 Parser.Lex(); // Eat hash token.
2310 const MCExpr *LSBExpr;
2311 SMLoc E = Parser.getTok().getLoc();
2312 if (getParser().ParseExpression(LSBExpr)) {
2313 Error(E, "malformed immediate expression");
2314 return MatchOperand_ParseFail;
2316 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
2318 Error(E, "'lsb' operand must be an immediate");
2319 return MatchOperand_ParseFail;
2322 int64_t LSB = CE->getValue();
2323 // The LSB must be in the range [0,31]
2324 if (LSB < 0 || LSB > 31) {
2325 Error(E, "'lsb' operand must be in the range [0,31]");
2326 return MatchOperand_ParseFail;
2328 E = Parser.getTok().getLoc();
2330 // Expect another immediate operand.
2331 if (Parser.getTok().isNot(AsmToken::Comma)) {
2332 Error(Parser.getTok().getLoc(), "too few operands");
2333 return MatchOperand_ParseFail;
2335 Parser.Lex(); // Eat hash token.
2336 if (Parser.getTok().isNot(AsmToken::Hash)) {
2337 Error(Parser.getTok().getLoc(), "'#' expected");
2338 return MatchOperand_ParseFail;
2340 Parser.Lex(); // Eat hash token.
2342 const MCExpr *WidthExpr;
2343 if (getParser().ParseExpression(WidthExpr)) {
2344 Error(E, "malformed immediate expression");
2345 return MatchOperand_ParseFail;
2347 CE = dyn_cast<MCConstantExpr>(WidthExpr);
2349 Error(E, "'width' operand must be an immediate");
2350 return MatchOperand_ParseFail;
2353 int64_t Width = CE->getValue();
2354 // The LSB must be in the range [1,32-lsb]
2355 if (Width < 1 || Width > 32 - LSB) {
2356 Error(E, "'width' operand must be in the range [1,32-lsb]");
2357 return MatchOperand_ParseFail;
2359 E = Parser.getTok().getLoc();
2361 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
2363 return MatchOperand_Success;
2366 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2367 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2368 // Check for a post-index addressing register operand. Specifically:
2369 // postidx_reg := '+' register {, shift}
2370 // | '-' register {, shift}
2371 // | register {, shift}
2373 // This method must return MatchOperand_NoMatch without consuming any tokens
2374 // in the case where there is no match, as other alternatives take other
2376 AsmToken Tok = Parser.getTok();
2377 SMLoc S = Tok.getLoc();
2378 bool haveEaten = false;
2381 if (Tok.is(AsmToken::Plus)) {
2382 Parser.Lex(); // Eat the '+' token.
2384 } else if (Tok.is(AsmToken::Minus)) {
2385 Parser.Lex(); // Eat the '-' token.
2389 if (Parser.getTok().is(AsmToken::Identifier))
2390 Reg = tryParseRegister();
2393 return MatchOperand_NoMatch;
2394 Error(Parser.getTok().getLoc(), "register expected");
2395 return MatchOperand_ParseFail;
2397 SMLoc E = Parser.getTok().getLoc();
2399 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
2400 unsigned ShiftImm = 0;
2401 if (Parser.getTok().is(AsmToken::Comma)) {
2402 Parser.Lex(); // Eat the ','.
2403 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
2404 return MatchOperand_ParseFail;
2407 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
2410 return MatchOperand_Success;
2413 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2414 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2415 // Check for a post-index addressing register operand. Specifically:
2416 // am3offset := '+' register
2423 // This method must return MatchOperand_NoMatch without consuming any tokens
2424 // in the case where there is no match, as other alternatives take other
2426 AsmToken Tok = Parser.getTok();
2427 SMLoc S = Tok.getLoc();
2429 // Do immediates first, as we always parse those if we have a '#'.
2430 if (Parser.getTok().is(AsmToken::Hash)) {
2431 Parser.Lex(); // Eat the '#'.
2432 // Explicitly look for a '-', as we need to encode negative zero
2434 bool isNegative = Parser.getTok().is(AsmToken::Minus);
2435 const MCExpr *Offset;
2436 if (getParser().ParseExpression(Offset))
2437 return MatchOperand_ParseFail;
2438 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2440 Error(S, "constant expression expected");
2441 return MatchOperand_ParseFail;
2443 SMLoc E = Tok.getLoc();
2444 // Negative zero is encoded as the flag value INT32_MIN.
2445 int32_t Val = CE->getValue();
2446 if (isNegative && Val == 0)
2450 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
2452 return MatchOperand_Success;
2456 bool haveEaten = false;
2459 if (Tok.is(AsmToken::Plus)) {
2460 Parser.Lex(); // Eat the '+' token.
2462 } else if (Tok.is(AsmToken::Minus)) {
2463 Parser.Lex(); // Eat the '-' token.
2467 if (Parser.getTok().is(AsmToken::Identifier))
2468 Reg = tryParseRegister();
2471 return MatchOperand_NoMatch;
2472 Error(Parser.getTok().getLoc(), "register expected");
2473 return MatchOperand_ParseFail;
2475 SMLoc E = Parser.getTok().getLoc();
2477 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
2480 return MatchOperand_Success;
2483 /// cvtT2LdrdPre - Convert parsed operands to MCInst.
2484 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2485 /// when they refer multiple MIOperands inside a single one.
2487 cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
2488 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2490 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2491 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2492 // Create a writeback register dummy placeholder.
2493 Inst.addOperand(MCOperand::CreateReg(0));
2495 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
2497 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2501 /// cvtT2StrdPre - Convert parsed operands to MCInst.
2502 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2503 /// when they refer multiple MIOperands inside a single one.
2505 cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
2506 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2507 // Create a writeback register dummy placeholder.
2508 Inst.addOperand(MCOperand::CreateReg(0));
2510 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2511 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2513 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
2515 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2519 /// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
2520 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2521 /// when they refer multiple MIOperands inside a single one.
2523 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
2524 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2525 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2527 // Create a writeback register dummy placeholder.
2528 Inst.addOperand(MCOperand::CreateImm(0));
2530 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
2531 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2535 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2536 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2537 /// when they refer multiple MIOperands inside a single one.
2539 cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2540 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2541 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2543 // Create a writeback register dummy placeholder.
2544 Inst.addOperand(MCOperand::CreateImm(0));
2546 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2547 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2551 /// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2552 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2553 /// when they refer multiple MIOperands inside a single one.
2555 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2556 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2557 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2559 // Create a writeback register dummy placeholder.
2560 Inst.addOperand(MCOperand::CreateImm(0));
2562 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2563 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2568 /// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2569 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2570 /// when they refer multiple MIOperands inside a single one.
2572 cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2573 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2574 // Create a writeback register dummy placeholder.
2575 Inst.addOperand(MCOperand::CreateImm(0));
2576 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2577 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2578 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2582 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2583 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2584 /// when they refer multiple MIOperands inside a single one.
2586 cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2587 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2588 // Create a writeback register dummy placeholder.
2589 Inst.addOperand(MCOperand::CreateImm(0));
2590 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2591 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2592 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2596 /// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2597 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2598 /// when they refer multiple MIOperands inside a single one.
2600 cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2601 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2602 // Create a writeback register dummy placeholder.
2603 Inst.addOperand(MCOperand::CreateImm(0));
2604 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2605 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2606 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2610 /// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
2611 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2612 /// when they refer multiple MIOperands inside a single one.
2614 cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2615 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2617 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2618 // Create a writeback register dummy placeholder.
2619 Inst.addOperand(MCOperand::CreateImm(0));
2621 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2623 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2625 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2629 /// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
2630 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2631 /// when they refer multiple MIOperands inside a single one.
2633 cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2634 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2636 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2637 // Create a writeback register dummy placeholder.
2638 Inst.addOperand(MCOperand::CreateImm(0));
2640 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2642 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2644 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2648 /// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
2649 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2650 /// when they refer multiple MIOperands inside a single one.
2652 cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2653 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2654 // Create a writeback register dummy placeholder.
2655 Inst.addOperand(MCOperand::CreateImm(0));
2657 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2659 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2661 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2663 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2667 /// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
2668 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2669 /// when they refer multiple MIOperands inside a single one.
2671 cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2672 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2673 // Create a writeback register dummy placeholder.
2674 Inst.addOperand(MCOperand::CreateImm(0));
2676 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2678 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2680 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2682 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2686 /// cvtLdrdPre - Convert parsed operands to MCInst.
2687 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2688 /// when they refer multiple MIOperands inside a single one.
2690 cvtLdrdPre(MCInst &Inst, unsigned Opcode,
2691 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2693 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2694 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2695 // Create a writeback register dummy placeholder.
2696 Inst.addOperand(MCOperand::CreateImm(0));
2698 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2700 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2704 /// cvtStrdPre - Convert parsed operands to MCInst.
2705 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2706 /// when they refer multiple MIOperands inside a single one.
2708 cvtStrdPre(MCInst &Inst, unsigned Opcode,
2709 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2710 // Create a writeback register dummy placeholder.
2711 Inst.addOperand(MCOperand::CreateImm(0));
2713 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2714 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2716 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2718 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2722 /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2723 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2724 /// when they refer multiple MIOperands inside a single one.
2726 cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2727 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2728 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2729 // Create a writeback register dummy placeholder.
2730 Inst.addOperand(MCOperand::CreateImm(0));
2731 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2732 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2736 /// cvtThumbMultiple- Convert parsed operands to MCInst.
2737 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2738 /// when they refer multiple MIOperands inside a single one.
2740 cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
2741 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2742 // The second source operand must be the same register as the destination
2744 if (Operands.size() == 6 &&
2745 (((ARMOperand*)Operands[3])->getReg() !=
2746 ((ARMOperand*)Operands[5])->getReg()) &&
2747 (((ARMOperand*)Operands[3])->getReg() !=
2748 ((ARMOperand*)Operands[4])->getReg())) {
2749 Error(Operands[3]->getStartLoc(),
2750 "destination register must match source register");
2753 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2754 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
2755 ((ARMOperand*)Operands[4])->addRegOperands(Inst, 1);
2756 // If we have a three-operand form, use that, else the second source operand
2757 // is just the destination operand again.
2758 if (Operands.size() == 6)
2759 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
2761 Inst.addOperand(Inst.getOperand(0));
2762 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
2767 /// Parse an ARM memory expression, return false if successful else return true
2768 /// or an error. The first token must be a '[' when called.
2770 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2772 assert(Parser.getTok().is(AsmToken::LBrac) &&
2773 "Token is not a Left Bracket");
2774 S = Parser.getTok().getLoc();
2775 Parser.Lex(); // Eat left bracket token.
2777 const AsmToken &BaseRegTok = Parser.getTok();
2778 int BaseRegNum = tryParseRegister();
2779 if (BaseRegNum == -1)
2780 return Error(BaseRegTok.getLoc(), "register expected");
2782 // The next token must either be a comma or a closing bracket.
2783 const AsmToken &Tok = Parser.getTok();
2784 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
2785 return Error(Tok.getLoc(), "malformed memory operand");
2787 if (Tok.is(AsmToken::RBrac)) {
2789 Parser.Lex(); // Eat right bracket token.
2791 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
2797 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
2798 Parser.Lex(); // Eat the comma.
2800 // If we have a '#' it's an immediate offset, else assume it's a register
2802 if (Parser.getTok().is(AsmToken::Hash)) {
2803 Parser.Lex(); // Eat the '#'.
2804 E = Parser.getTok().getLoc();
2806 bool isNegative = getParser().getTok().is(AsmToken::Minus);
2807 const MCExpr *Offset;
2808 if (getParser().ParseExpression(Offset))
2811 // The expression has to be a constant. Memory references with relocations
2812 // don't come through here, as they use the <label> forms of the relevant
2814 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2816 return Error (E, "constant expression expected");
2818 // If the constant was #-0, represent it as INT32_MIN.
2819 int32_t Val = CE->getValue();
2820 if (isNegative && Val == 0)
2821 CE = MCConstantExpr::Create(INT32_MIN, getContext());
2823 // Now we should have the closing ']'
2824 E = Parser.getTok().getLoc();
2825 if (Parser.getTok().isNot(AsmToken::RBrac))
2826 return Error(E, "']' expected");
2827 Parser.Lex(); // Eat right bracket token.
2829 // Don't worry about range checking the value here. That's handled by
2830 // the is*() predicates.
2831 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
2832 ARM_AM::no_shift, 0, false, S,E));
2834 // If there's a pre-indexing writeback marker, '!', just add it as a token
2836 if (Parser.getTok().is(AsmToken::Exclaim)) {
2837 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2838 Parser.Lex(); // Eat the '!'.
2844 // The register offset is optionally preceded by a '+' or '-'
2845 bool isNegative = false;
2846 if (Parser.getTok().is(AsmToken::Minus)) {
2848 Parser.Lex(); // Eat the '-'.
2849 } else if (Parser.getTok().is(AsmToken::Plus)) {
2851 Parser.Lex(); // Eat the '+'.
2854 E = Parser.getTok().getLoc();
2855 int OffsetRegNum = tryParseRegister();
2856 if (OffsetRegNum == -1)
2857 return Error(E, "register expected");
2859 // If there's a shift operator, handle it.
2860 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
2861 unsigned ShiftImm = 0;
2862 if (Parser.getTok().is(AsmToken::Comma)) {
2863 Parser.Lex(); // Eat the ','.
2864 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
2868 // Now we should have the closing ']'
2869 E = Parser.getTok().getLoc();
2870 if (Parser.getTok().isNot(AsmToken::RBrac))
2871 return Error(E, "']' expected");
2872 Parser.Lex(); // Eat right bracket token.
2874 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
2875 ShiftType, ShiftImm, isNegative,
2878 // If there's a pre-indexing writeback marker, '!', just add it as a token
2880 if (Parser.getTok().is(AsmToken::Exclaim)) {
2881 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2882 Parser.Lex(); // Eat the '!'.
2888 /// parseMemRegOffsetShift - one of these two:
2889 /// ( lsl | lsr | asr | ror ) , # shift_amount
2891 /// return true if it parses a shift otherwise it returns false.
2892 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
2894 SMLoc Loc = Parser.getTok().getLoc();
2895 const AsmToken &Tok = Parser.getTok();
2896 if (Tok.isNot(AsmToken::Identifier))
2898 StringRef ShiftName = Tok.getString();
2899 if (ShiftName == "lsl" || ShiftName == "LSL")
2901 else if (ShiftName == "lsr" || ShiftName == "LSR")
2903 else if (ShiftName == "asr" || ShiftName == "ASR")
2905 else if (ShiftName == "ror" || ShiftName == "ROR")
2907 else if (ShiftName == "rrx" || ShiftName == "RRX")
2910 return Error(Loc, "illegal shift operator");
2911 Parser.Lex(); // Eat shift type token.
2913 // rrx stands alone.
2915 if (St != ARM_AM::rrx) {
2916 Loc = Parser.getTok().getLoc();
2917 // A '#' and a shift amount.
2918 const AsmToken &HashTok = Parser.getTok();
2919 if (HashTok.isNot(AsmToken::Hash))
2920 return Error(HashTok.getLoc(), "'#' expected");
2921 Parser.Lex(); // Eat hash token.
2924 if (getParser().ParseExpression(Expr))
2926 // Range check the immediate.
2927 // lsl, ror: 0 <= imm <= 31
2928 // lsr, asr: 0 <= imm <= 32
2929 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2931 return Error(Loc, "shift amount must be an immediate");
2932 int64_t Imm = CE->getValue();
2934 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
2935 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
2936 return Error(Loc, "immediate shift value out of range");
2943 /// Parse a arm instruction operand. For now this parses the operand regardless
2944 /// of the mnemonic.
2945 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2946 StringRef Mnemonic) {
2949 // Check if the current operand has a custom associated parser, if so, try to
2950 // custom parse the operand, or fallback to the general approach.
2951 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
2952 if (ResTy == MatchOperand_Success)
2954 // If there wasn't a custom match, try the generic matcher below. Otherwise,
2955 // there was a match, but an error occurred, in which case, just return that
2956 // the operand parsing failed.
2957 if (ResTy == MatchOperand_ParseFail)
2960 switch (getLexer().getKind()) {
2962 Error(Parser.getTok().getLoc(), "unexpected token in operand");
2964 case AsmToken::Identifier: {
2965 if (!tryParseRegisterWithWriteBack(Operands))
2967 int Res = tryParseShiftRegister(Operands);
2968 if (Res == 0) // success
2970 else if (Res == -1) // irrecoverable error
2973 // Fall though for the Identifier case that is not a register or a
2976 case AsmToken::Integer: // things like 1f and 2b as a branch targets
2977 case AsmToken::Dot: { // . as a branch target
2978 // This was not a register so parse other operands that start with an
2979 // identifier (like labels) as expressions and create them as immediates.
2980 const MCExpr *IdVal;
2981 S = Parser.getTok().getLoc();
2982 if (getParser().ParseExpression(IdVal))
2984 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2985 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
2988 case AsmToken::LBrac:
2989 return parseMemory(Operands);
2990 case AsmToken::LCurly:
2991 return parseRegisterList(Operands);
2992 case AsmToken::Hash: {
2993 // #42 -> immediate.
2994 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
2995 S = Parser.getTok().getLoc();
2997 bool isNegative = Parser.getTok().is(AsmToken::Minus);
2998 const MCExpr *ImmVal;
2999 if (getParser().ParseExpression(ImmVal))
3001 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
3003 Error(S, "constant expression expected");
3004 return MatchOperand_ParseFail;
3006 int32_t Val = CE->getValue();
3007 if (isNegative && Val == 0)
3008 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
3009 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3010 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
3013 case AsmToken::Colon: {
3014 // ":lower16:" and ":upper16:" expression prefixes
3015 // FIXME: Check it's an expression prefix,
3016 // e.g. (FOO - :lower16:BAR) isn't legal.
3017 ARMMCExpr::VariantKind RefKind;
3018 if (parsePrefix(RefKind))
3021 const MCExpr *SubExprVal;
3022 if (getParser().ParseExpression(SubExprVal))
3025 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
3027 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3028 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
3034 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
3035 // :lower16: and :upper16:.
3036 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
3037 RefKind = ARMMCExpr::VK_ARM_None;
3039 // :lower16: and :upper16: modifiers
3040 assert(getLexer().is(AsmToken::Colon) && "expected a :");
3041 Parser.Lex(); // Eat ':'
3043 if (getLexer().isNot(AsmToken::Identifier)) {
3044 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
3048 StringRef IDVal = Parser.getTok().getIdentifier();
3049 if (IDVal == "lower16") {
3050 RefKind = ARMMCExpr::VK_ARM_LO16;
3051 } else if (IDVal == "upper16") {
3052 RefKind = ARMMCExpr::VK_ARM_HI16;
3054 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
3059 if (getLexer().isNot(AsmToken::Colon)) {
3060 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
3063 Parser.Lex(); // Eat the last ':'
3067 /// \brief Given a mnemonic, split out possible predication code and carry
3068 /// setting letters to form a canonical mnemonic and flags.
3070 // FIXME: Would be nice to autogen this.
3071 // FIXME: This is a bit of a maze of special cases.
3072 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
3073 unsigned &PredicationCode,
3075 unsigned &ProcessorIMod,
3076 StringRef &ITMask) {
3077 PredicationCode = ARMCC::AL;
3078 CarrySetting = false;
3081 // Ignore some mnemonics we know aren't predicated forms.
3083 // FIXME: Would be nice to autogen this.
3084 if ((Mnemonic == "movs" && isThumb()) ||
3085 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
3086 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
3087 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
3088 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
3089 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
3090 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
3091 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
3094 // First, split out any predication code. Ignore mnemonics we know aren't
3095 // predicated but do have a carry-set and so weren't caught above.
3096 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
3097 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
3098 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
3099 Mnemonic != "sbcs" && Mnemonic != "rscs") {
3100 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
3101 .Case("eq", ARMCC::EQ)
3102 .Case("ne", ARMCC::NE)
3103 .Case("hs", ARMCC::HS)
3104 .Case("cs", ARMCC::HS)
3105 .Case("lo", ARMCC::LO)
3106 .Case("cc", ARMCC::LO)
3107 .Case("mi", ARMCC::MI)
3108 .Case("pl", ARMCC::PL)
3109 .Case("vs", ARMCC::VS)
3110 .Case("vc", ARMCC::VC)
3111 .Case("hi", ARMCC::HI)
3112 .Case("ls", ARMCC::LS)
3113 .Case("ge", ARMCC::GE)
3114 .Case("lt", ARMCC::LT)
3115 .Case("gt", ARMCC::GT)
3116 .Case("le", ARMCC::LE)
3117 .Case("al", ARMCC::AL)
3120 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
3121 PredicationCode = CC;
3125 // Next, determine if we have a carry setting bit. We explicitly ignore all
3126 // the instructions we know end in 's'.
3127 if (Mnemonic.endswith("s") &&
3128 !(Mnemonic == "cps" || Mnemonic == "mls" ||
3129 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
3130 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
3131 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
3132 Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
3133 (Mnemonic == "movs" && isThumb()))) {
3134 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
3135 CarrySetting = true;
3138 // The "cps" instruction can have a interrupt mode operand which is glued into
3139 // the mnemonic. Check if this is the case, split it and parse the imod op
3140 if (Mnemonic.startswith("cps")) {
3141 // Split out any imod code.
3143 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
3144 .Case("ie", ARM_PROC::IE)
3145 .Case("id", ARM_PROC::ID)
3148 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
3149 ProcessorIMod = IMod;
3153 // The "it" instruction has the condition mask on the end of the mnemonic.
3154 if (Mnemonic.startswith("it")) {
3155 ITMask = Mnemonic.slice(2, Mnemonic.size());
3156 Mnemonic = Mnemonic.slice(0, 2);
3162 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
3163 /// inclusion of carry set or predication code operands.
3165 // FIXME: It would be nice to autogen this.
3167 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
3168 bool &CanAcceptPredicationCode) {
3169 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
3170 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
3171 Mnemonic == "add" || Mnemonic == "adc" ||
3172 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
3173 Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" ||
3174 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
3175 Mnemonic == "sbc" || Mnemonic == "umull" || Mnemonic == "eor" ||
3176 Mnemonic == "neg" ||
3177 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
3178 Mnemonic == "mla" || Mnemonic == "smlal"))) {
3179 CanAcceptCarrySet = true;
3181 CanAcceptCarrySet = false;
3183 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
3184 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
3185 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
3186 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
3187 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
3188 (Mnemonic == "clrex" && !isThumb()) ||
3189 (Mnemonic == "nop" && isThumbOne()) ||
3190 ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw") &&
3192 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
3194 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
3195 CanAcceptPredicationCode = false;
3197 CanAcceptPredicationCode = true;
3200 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
3201 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
3202 CanAcceptPredicationCode = false;
3206 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
3207 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3208 // FIXME: This is all horribly hacky. We really need a better way to deal
3209 // with optional operands like this in the matcher table.
3211 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
3212 // another does not. Specifically, the MOVW instruction does not. So we
3213 // special case it here and remove the defaulted (non-setting) cc_out
3214 // operand if that's the instruction we're trying to match.
3216 // We do this as post-processing of the explicit operands rather than just
3217 // conditionally adding the cc_out in the first place because we need
3218 // to check the type of the parsed immediate operand.
3219 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
3220 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
3221 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
3222 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3225 // Register-register 'add' for thumb does not have a cc_out operand
3226 // when there are only two register operands.
3227 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
3228 static_cast<ARMOperand*>(Operands[3])->isReg() &&
3229 static_cast<ARMOperand*>(Operands[4])->isReg() &&
3230 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3232 // Register-register 'add' for thumb does not have a cc_out operand
3233 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
3234 // have to check the immediate range here since Thumb2 has a variant
3235 // that can handle a different range and has a cc_out operand.
3236 if (isThumb() && Mnemonic == "add" && Operands.size() == 6 &&
3237 static_cast<ARMOperand*>(Operands[3])->isReg() &&
3238 static_cast<ARMOperand*>(Operands[4])->isReg() &&
3239 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
3240 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
3241 (static_cast<ARMOperand*>(Operands[5])->isReg() ||
3242 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
3244 // For Thumb2, add immediate does not have a cc_out operand for the
3245 // imm0_4096 variant. That's the least-preferred variant when
3246 // selecting via the generic "add" mnemonic, so to know that we
3247 // should remove the cc_out operand, we have to explicitly check that
3248 // it's not one of the other variants. Ugh.
3249 if (isThumbTwo() && Mnemonic == "add" && Operands.size() == 6 &&
3250 static_cast<ARMOperand*>(Operands[3])->isReg() &&
3251 static_cast<ARMOperand*>(Operands[4])->isReg() &&
3252 static_cast<ARMOperand*>(Operands[5])->isImm()) {
3253 // Nest conditions rather than one big 'if' statement for readability.
3255 // If either register is a high reg, it's either one of the SP
3256 // variants (handled above) or a 32-bit encoding, so we just
3257 // check against T3.
3258 if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
3259 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
3260 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
3262 // If both registers are low, we're in an IT block, and the immediate is
3263 // in range, we should use encoding T1 instead, which has a cc_out.
3265 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
3266 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
3267 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
3270 // Otherwise, we use encoding T4, which does not have a cc_out
3275 // The thumb2 multiply instruction doesn't have a CCOut register, so
3276 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
3277 // use the 16-bit encoding or not.
3278 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
3279 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
3280 static_cast<ARMOperand*>(Operands[3])->isReg() &&
3281 static_cast<ARMOperand*>(Operands[4])->isReg() &&
3282 static_cast<ARMOperand*>(Operands[5])->isReg() &&
3283 // If the registers aren't low regs, the destination reg isn't the
3284 // same as one of the source regs, or the cc_out operand is zero
3285 // outside of an IT block, we have to use the 32-bit encoding, so
3286 // remove the cc_out operand.
3287 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
3288 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
3290 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
3291 static_cast<ARMOperand*>(Operands[5])->getReg() &&
3292 static_cast<ARMOperand*>(Operands[3])->getReg() !=
3293 static_cast<ARMOperand*>(Operands[4])->getReg())))
3298 // Register-register 'add/sub' for thumb does not have a cc_out operand
3299 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
3300 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
3301 // right, this will result in better diagnostics (which operand is off)
3303 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
3304 (Operands.size() == 5 || Operands.size() == 6) &&
3305 static_cast<ARMOperand*>(Operands[3])->isReg() &&
3306 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
3307 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3313 /// Parse an arm instruction mnemonic followed by its operands.
3314 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
3315 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3316 // Create the leading tokens for the mnemonic, split by '.' characters.
3317 size_t Start = 0, Next = Name.find('.');
3318 StringRef Mnemonic = Name.slice(Start, Next);
3320 // Split out the predication code and carry setting flag from the mnemonic.
3321 unsigned PredicationCode;
3322 unsigned ProcessorIMod;
3325 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
3326 ProcessorIMod, ITMask);
3328 // In Thumb1, only the branch (B) instruction can be predicated.
3329 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
3330 Parser.EatToEndOfStatement();
3331 return Error(NameLoc, "conditional execution not supported in Thumb1");
3334 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
3336 // Handle the IT instruction ITMask. Convert it to a bitmask. This
3337 // is the mask as it will be for the IT encoding if the conditional
3338 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
3339 // where the conditional bit0 is zero, the instruction post-processing
3340 // will adjust the mask accordingly.
3341 if (Mnemonic == "it") {
3342 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
3343 if (ITMask.size() > 3) {
3344 Parser.EatToEndOfStatement();
3345 return Error(Loc, "too many conditions on IT instruction");
3348 for (unsigned i = ITMask.size(); i != 0; --i) {
3349 char pos = ITMask[i - 1];
3350 if (pos != 't' && pos != 'e') {
3351 Parser.EatToEndOfStatement();
3352 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
3355 if (ITMask[i - 1] == 't')
3358 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
3361 // FIXME: This is all a pretty gross hack. We should automatically handle
3362 // optional operands like this via tblgen.
3364 // Next, add the CCOut and ConditionCode operands, if needed.
3366 // For mnemonics which can ever incorporate a carry setting bit or predication
3367 // code, our matching model involves us always generating CCOut and
3368 // ConditionCode operands to match the mnemonic "as written" and then we let
3369 // the matcher deal with finding the right instruction or generating an
3370 // appropriate error.
3371 bool CanAcceptCarrySet, CanAcceptPredicationCode;
3372 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
3374 // If we had a carry-set on an instruction that can't do that, issue an
3376 if (!CanAcceptCarrySet && CarrySetting) {
3377 Parser.EatToEndOfStatement();
3378 return Error(NameLoc, "instruction '" + Mnemonic +
3379 "' can not set flags, but 's' suffix specified");
3381 // If we had a predication code on an instruction that can't do that, issue an
3383 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
3384 Parser.EatToEndOfStatement();
3385 return Error(NameLoc, "instruction '" + Mnemonic +
3386 "' is not predicable, but condition code specified");
3389 // Add the carry setting operand, if necessary.
3390 if (CanAcceptCarrySet) {
3391 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
3392 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
3396 // Add the predication code operand, if necessary.
3397 if (CanAcceptPredicationCode) {
3398 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
3400 Operands.push_back(ARMOperand::CreateCondCode(
3401 ARMCC::CondCodes(PredicationCode), Loc));
3404 // Add the processor imod operand, if necessary.
3405 if (ProcessorIMod) {
3406 Operands.push_back(ARMOperand::CreateImm(
3407 MCConstantExpr::Create(ProcessorIMod, getContext()),
3411 // Add the remaining tokens in the mnemonic.
3412 while (Next != StringRef::npos) {
3414 Next = Name.find('.', Start + 1);
3415 StringRef ExtraToken = Name.slice(Start, Next);
3417 // For now, we're only parsing Thumb1 (for the most part), so
3418 // just ignore ".n" qualifiers. We'll use them to restrict
3419 // matching when we do Thumb2.
3420 if (ExtraToken != ".n") {
3421 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
3422 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
3426 // Read the remaining operands.
3427 if (getLexer().isNot(AsmToken::EndOfStatement)) {
3428 // Read the first operand.
3429 if (parseOperand(Operands, Mnemonic)) {
3430 Parser.EatToEndOfStatement();
3434 while (getLexer().is(AsmToken::Comma)) {
3435 Parser.Lex(); // Eat the comma.
3437 // Parse and remember the operand.
3438 if (parseOperand(Operands, Mnemonic)) {
3439 Parser.EatToEndOfStatement();
3445 if (getLexer().isNot(AsmToken::EndOfStatement)) {
3446 Parser.EatToEndOfStatement();
3447 return TokError("unexpected token in argument list");
3450 Parser.Lex(); // Consume the EndOfStatement
3452 // Some instructions, mostly Thumb, have forms for the same mnemonic that
3453 // do and don't have a cc_out optional-def operand. With some spot-checks
3454 // of the operand list, we can figure out which variant we're trying to
3455 // parse and adjust accordingly before actually matching. We shouldn't ever
3456 // try to remove a cc_out operand that was explicitly set on the the
3457 // mnemonic, of course (CarrySetting == true). Reason number #317 the
3458 // table driven matcher doesn't fit well with the ARM instruction set.
3459 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
3460 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3461 Operands.erase(Operands.begin() + 1);
3465 // ARM mode 'blx' need special handling, as the register operand version
3466 // is predicable, but the label operand version is not. So, we can't rely
3467 // on the Mnemonic based checking to correctly figure out when to put
3468 // a CondCode operand in the list. If we're trying to match the label
3469 // version, remove the CondCode operand here.
3470 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
3471 static_cast<ARMOperand*>(Operands[2])->isImm()) {
3472 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3473 Operands.erase(Operands.begin() + 1);
3477 // The vector-compare-to-zero instructions have a literal token "#0" at
3478 // the end that comes to here as an immediate operand. Convert it to a
3479 // token to play nicely with the matcher.
3480 if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
3481 Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
3482 static_cast<ARMOperand*>(Operands[5])->isImm()) {
3483 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
3484 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
3485 if (CE && CE->getValue() == 0) {
3486 Operands.erase(Operands.begin() + 5);
3487 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3491 // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
3492 // end. Convert it to a token here.
3493 if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
3494 static_cast<ARMOperand*>(Operands[5])->isImm()) {
3495 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
3496 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
3497 if (CE && CE->getValue() == 0) {
3498 Operands.erase(Operands.begin() + 5);
3499 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3507 // Validate context-sensitive operand constraints.
3509 // return 'true' if register list contains non-low GPR registers,
3510 // 'false' otherwise. If Reg is in the register list or is HiReg, set
3511 // 'containsReg' to true.
3512 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
3513 unsigned HiReg, bool &containsReg) {
3514 containsReg = false;
3515 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
3516 unsigned OpReg = Inst.getOperand(i).getReg();
3519 // Anything other than a low register isn't legal here.
3520 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
3526 // Check if the specified regisgter is in the register list of the inst,
3527 // starting at the indicated operand number.
3528 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
3529 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
3530 unsigned OpReg = Inst.getOperand(i).getReg();
3537 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around
3538 // the ARMInsts array) instead. Getting that here requires awkward
3539 // API changes, though. Better way?
3541 extern MCInstrDesc ARMInsts[];
3543 static MCInstrDesc &getInstDesc(unsigned Opcode) {
3544 return ARMInsts[Opcode];
3547 // FIXME: We would really like to be able to tablegen'erate this.
3549 validateInstruction(MCInst &Inst,
3550 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3551 MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
3552 SMLoc Loc = Operands[0]->getStartLoc();
3553 // Check the IT block state first.
3554 // NOTE: In Thumb mode, the BKPT instruction has the interesting property of
3555 // being allowed in IT blocks, but not being predicable. It just always
3557 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT) {
3559 if (ITState.FirstCond)
3560 ITState.FirstCond = false;
3562 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
3563 // The instruction must be predicable.
3564 if (!MCID.isPredicable())
3565 return Error(Loc, "instructions in IT block must be predicable");
3566 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
3567 unsigned ITCond = bit ? ITState.Cond :
3568 ARMCC::getOppositeCondition(ITState.Cond);
3569 if (Cond != ITCond) {
3570 // Find the condition code Operand to get its SMLoc information.
3572 for (unsigned i = 1; i < Operands.size(); ++i)
3573 if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
3574 CondLoc = Operands[i]->getStartLoc();
3575 return Error(CondLoc, "incorrect condition in IT block; got '" +
3576 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
3577 "', but expected '" +
3578 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
3580 // Check for non-'al' condition codes outside of the IT block.
3581 } else if (isThumbTwo() && MCID.isPredicable() &&
3582 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
3583 ARMCC::AL && Inst.getOpcode() != ARM::tB &&
3584 Inst.getOpcode() != ARM::t2B)
3585 return Error(Loc, "predicated instructions must be in IT block");
3587 switch (Inst.getOpcode()) {
3590 case ARM::LDRD_POST:
3592 // Rt2 must be Rt + 1.
3593 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3594 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3596 return Error(Operands[3]->getStartLoc(),
3597 "destination operands must be sequential");
3601 // Rt2 must be Rt + 1.
3602 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3603 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3605 return Error(Operands[3]->getStartLoc(),
3606 "source operands must be sequential");
3610 case ARM::STRD_POST:
3612 // Rt2 must be Rt + 1.
3613 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3614 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
3616 return Error(Operands[3]->getStartLoc(),
3617 "source operands must be sequential");
3622 // width must be in range [1, 32-lsb]
3623 unsigned lsb = Inst.getOperand(2).getImm();
3624 unsigned widthm1 = Inst.getOperand(3).getImm();
3625 if (widthm1 >= 32 - lsb)
3626 return Error(Operands[5]->getStartLoc(),
3627 "bitfield width must be in range [1,32-lsb]");
3631 // If we're parsing Thumb2, the .w variant is available and handles
3632 // most cases that are normally illegal for a Thumb1 LDM
3633 // instruction. We'll make the transformation in processInstruction()
3636 // Thumb LDM instructions are writeback iff the base register is not
3637 // in the register list.
3638 unsigned Rn = Inst.getOperand(0).getReg();
3639 bool hasWritebackToken =
3640 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
3641 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
3642 bool listContainsBase;
3643 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
3644 return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
3645 "registers must be in range r0-r7");
3646 // If we should have writeback, then there should be a '!' token.
3647 if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
3648 return Error(Operands[2]->getStartLoc(),
3649 "writeback operator '!' expected");
3650 // If we should not have writeback, there must not be a '!'. This is
3651 // true even for the 32-bit wide encodings.
3652 if (listContainsBase && hasWritebackToken)
3653 return Error(Operands[3]->getStartLoc(),
3654 "writeback operator '!' not allowed when base register "
3655 "in register list");
3659 case ARM::t2LDMIA_UPD: {
3660 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
3661 return Error(Operands[4]->getStartLoc(),
3662 "writeback operator '!' not allowed when base register "
3663 "in register list");
3667 bool listContainsBase;
3668 if (checkLowRegisterList(Inst, 3, 0, ARM::PC, listContainsBase))
3669 return Error(Operands[2]->getStartLoc(),
3670 "registers must be in range r0-r7 or pc");
3674 bool listContainsBase;
3675 if (checkLowRegisterList(Inst, 3, 0, ARM::LR, listContainsBase))
3676 return Error(Operands[2]->getStartLoc(),
3677 "registers must be in range r0-r7 or lr");
3680 case ARM::tSTMIA_UPD: {
3681 bool listContainsBase;
3682 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase))
3683 return Error(Operands[4]->getStartLoc(),
3684 "registers must be in range r0-r7");
3693 processInstruction(MCInst &Inst,
3694 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3695 switch (Inst.getOpcode()) {
3696 case ARM::LDMIA_UPD:
3697 // If this is a load of a single register via a 'pop', then we should use
3698 // a post-indexed LDR instruction instead, per the ARM ARM.
3699 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
3700 Inst.getNumOperands() == 5) {
3702 TmpInst.setOpcode(ARM::LDR_POST_IMM);
3703 TmpInst.addOperand(Inst.getOperand(4)); // Rt
3704 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3705 TmpInst.addOperand(Inst.getOperand(1)); // Rn
3706 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
3707 TmpInst.addOperand(MCOperand::CreateImm(4));
3708 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3709 TmpInst.addOperand(Inst.getOperand(3));
3713 case ARM::STMDB_UPD:
3714 // If this is a store of a single register via a 'push', then we should use
3715 // a pre-indexed STR instruction instead, per the ARM ARM.
3716 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
3717 Inst.getNumOperands() == 5) {
3719 TmpInst.setOpcode(ARM::STR_PRE_IMM);
3720 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3721 TmpInst.addOperand(Inst.getOperand(4)); // Rt
3722 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
3723 TmpInst.addOperand(MCOperand::CreateImm(-4));
3724 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3725 TmpInst.addOperand(Inst.getOperand(3));
3730 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
3731 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
3732 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
3733 // to encoding T1 if <Rd> is omitted."
3734 if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6)
3735 Inst.setOpcode(ARM::tADDi3);
3738 // A Thumb conditional branch outside of an IT block is a tBcc.
3739 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock())
3740 Inst.setOpcode(ARM::tBcc);
3743 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
3744 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock())
3745 Inst.setOpcode(ARM::t2Bcc);
3748 // If the conditional is AL or we're in an IT block, we really want t2B.
3749 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock())
3750 Inst.setOpcode(ARM::t2B);
3753 // If the conditional is AL, we really want tB.
3754 if (Inst.getOperand(1).getImm() == ARMCC::AL)
3755 Inst.setOpcode(ARM::tB);
3758 // If the register list contains any high registers, or if the writeback
3759 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
3760 // instead if we're in Thumb2. Otherwise, this should have generated
3761 // an error in validateInstruction().
3762 unsigned Rn = Inst.getOperand(0).getReg();
3763 bool hasWritebackToken =
3764 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
3765 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
3766 bool listContainsBase;
3767 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
3768 (!listContainsBase && !hasWritebackToken) ||
3769 (listContainsBase && hasWritebackToken)) {
3770 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
3771 assert (isThumbTwo());
3772 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
3773 // If we're switching to the updating version, we need to insert
3774 // the writeback tied operand.
3775 if (hasWritebackToken)
3776 Inst.insert(Inst.begin(),
3777 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
3782 // If we can use the 16-bit encoding and the user didn't explicitly
3783 // request the 32-bit variant, transform it here.
3784 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
3785 Inst.getOperand(1).getImm() <= 255 &&
3786 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
3787 Inst.getOperand(4).getReg() == ARM::CPSR) ||
3788 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
3789 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
3790 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
3791 // The operands aren't in the same order for tMOVi8...
3793 TmpInst.setOpcode(ARM::tMOVi8);
3794 TmpInst.addOperand(Inst.getOperand(0));
3795 TmpInst.addOperand(Inst.getOperand(4));
3796 TmpInst.addOperand(Inst.getOperand(1));
3797 TmpInst.addOperand(Inst.getOperand(2));
3798 TmpInst.addOperand(Inst.getOperand(3));
3804 // If we can use the 16-bit encoding and the user didn't explicitly
3805 // request the 32-bit variant, transform it here.
3806 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
3807 isARMLowRegister(Inst.getOperand(1).getReg()) &&
3808 Inst.getOperand(2).getImm() == ARMCC::AL &&
3809 Inst.getOperand(4).getReg() == ARM::CPSR &&
3810 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
3811 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
3812 // The operands aren't the same for tMOV[S]r... (no cc_out)
3814 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
3815 TmpInst.addOperand(Inst.getOperand(0));
3816 TmpInst.addOperand(Inst.getOperand(1));
3817 TmpInst.addOperand(Inst.getOperand(2));
3818 TmpInst.addOperand(Inst.getOperand(3));
3824 // The mask bits for all but the first condition are represented as
3825 // the low bit of the condition code value implies 't'. We currently
3826 // always have 1 implies 't', so XOR toggle the bits if the low bit
3827 // of the condition code is zero. The encoding also expects the low
3828 // bit of the condition to be encoded as bit 4 of the mask operand,
3829 // so mask that in if needed
3830 MCOperand &MO = Inst.getOperand(1);
3831 unsigned Mask = MO.getImm();
3832 unsigned OrigMask = Mask;
3833 unsigned TZ = CountTrailingZeros_32(Mask);
3834 if ((Inst.getOperand(0).getImm() & 1) == 0) {
3835 assert(Mask && TZ <= 3 && "illegal IT mask value!");
3836 for (unsigned i = 3; i != TZ; --i)
3842 // Set up the IT block state according to the IT instruction we just
3844 assert(!inITBlock() && "nested IT blocks?!");
3845 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
3846 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
3847 ITState.CurPosition = 0;
3848 ITState.FirstCond = true;
3854 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
3855 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
3856 // suffix depending on whether they're in an IT block or not.
3857 unsigned Opc = Inst.getOpcode();
3858 MCInstrDesc &MCID = getInstDesc(Opc);
3859 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
3860 assert(MCID.hasOptionalDef() &&
3861 "optionally flag setting instruction missing optional def operand");
3862 assert(MCID.NumOperands == Inst.getNumOperands() &&
3863 "operand count mismatch!");
3864 // Find the optional-def operand (cc_out).
3867 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
3870 // If we're parsing Thumb1, reject it completely.
3871 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3872 return Match_MnemonicFail;
3873 // If we're parsing Thumb2, which form is legal depends on whether we're
3875 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
3877 return Match_RequiresITBlock;
3878 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
3880 return Match_RequiresNotITBlock;
3882 // Some high-register supporting Thumb1 encodings only allow both registers
3883 // to be from r0-r7 when in Thumb2.
3884 else if (Opc == ARM::tADDhirr && isThumbOne() &&
3885 isARMLowRegister(Inst.getOperand(1).getReg()) &&
3886 isARMLowRegister(Inst.getOperand(2).getReg()))
3887 return Match_RequiresThumb2;
3888 // Others only require ARMv6 or later.
3889 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
3890 isARMLowRegister(Inst.getOperand(0).getReg()) &&
3891 isARMLowRegister(Inst.getOperand(1).getReg()))
3892 return Match_RequiresV6;
3893 return Match_Success;
3897 MatchAndEmitInstruction(SMLoc IDLoc,
3898 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
3902 unsigned MatchResult;
3903 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
3904 switch (MatchResult) {
3907 // Context sensitive operand constraints aren't handled by the matcher,
3908 // so check them here.
3909 if (validateInstruction(Inst, Operands)) {
3910 // Still progress the IT block, otherwise one wrong condition causes
3911 // nasty cascading errors.
3912 forwardITPosition();
3916 // Some instructions need post-processing to, for example, tweak which
3917 // encoding is selected.
3918 processInstruction(Inst, Operands);
3920 // Only move forward at the very end so that everything in validate
3921 // and process gets a consistent answer about whether we're in an IT
3923 forwardITPosition();
3925 Out.EmitInstruction(Inst);
3927 case Match_MissingFeature:
3928 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
3930 case Match_InvalidOperand: {
3931 SMLoc ErrorLoc = IDLoc;
3932 if (ErrorInfo != ~0U) {
3933 if (ErrorInfo >= Operands.size())
3934 return Error(IDLoc, "too few operands for instruction");
3936 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
3937 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
3940 return Error(ErrorLoc, "invalid operand for instruction");
3942 case Match_MnemonicFail:
3943 return Error(IDLoc, "invalid instruction");
3944 case Match_ConversionFail:
3945 // The converter function will have already emited a diagnostic.
3947 case Match_RequiresNotITBlock:
3948 return Error(IDLoc, "flag setting instruction only valid outside IT block");
3949 case Match_RequiresITBlock:
3950 return Error(IDLoc, "instruction only valid inside IT block");
3951 case Match_RequiresV6:
3952 return Error(IDLoc, "instruction variant requires ARMv6 or later");
3953 case Match_RequiresThumb2:
3954 return Error(IDLoc, "instruction variant requires Thumb2");
3957 llvm_unreachable("Implement any new match types added!");
3961 /// parseDirective parses the arm specific directives
3962 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
3963 StringRef IDVal = DirectiveID.getIdentifier();
3964 if (IDVal == ".word")
3965 return parseDirectiveWord(4, DirectiveID.getLoc());
3966 else if (IDVal == ".thumb")
3967 return parseDirectiveThumb(DirectiveID.getLoc());
3968 else if (IDVal == ".thumb_func")
3969 return parseDirectiveThumbFunc(DirectiveID.getLoc());
3970 else if (IDVal == ".code")
3971 return parseDirectiveCode(DirectiveID.getLoc());
3972 else if (IDVal == ".syntax")
3973 return parseDirectiveSyntax(DirectiveID.getLoc());
3977 /// parseDirectiveWord
3978 /// ::= .word [ expression (, expression)* ]
3979 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
3980 if (getLexer().isNot(AsmToken::EndOfStatement)) {
3982 const MCExpr *Value;
3983 if (getParser().ParseExpression(Value))
3986 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
3988 if (getLexer().is(AsmToken::EndOfStatement))
3991 // FIXME: Improve diagnostic.
3992 if (getLexer().isNot(AsmToken::Comma))
3993 return Error(L, "unexpected token in directive");
4002 /// parseDirectiveThumb
4004 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
4005 if (getLexer().isNot(AsmToken::EndOfStatement))
4006 return Error(L, "unexpected token in directive");
4009 // TODO: set thumb mode
4010 // TODO: tell the MC streamer the mode
4011 // getParser().getStreamer().Emit???();
4015 /// parseDirectiveThumbFunc
4016 /// ::= .thumbfunc symbol_name
4017 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
4018 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
4019 bool isMachO = MAI.hasSubsectionsViaSymbols();
4022 // Darwin asm has function name after .thumb_func direction
4025 const AsmToken &Tok = Parser.getTok();
4026 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
4027 return Error(L, "unexpected token in .thumb_func directive");
4028 Name = Tok.getString();
4029 Parser.Lex(); // Consume the identifier token.
4032 if (getLexer().isNot(AsmToken::EndOfStatement))
4033 return Error(L, "unexpected token in directive");
4036 // FIXME: assuming function name will be the line following .thumb_func
4038 Name = Parser.getTok().getString();
4041 // Mark symbol as a thumb symbol.
4042 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
4043 getParser().getStreamer().EmitThumbFunc(Func);
4047 /// parseDirectiveSyntax
4048 /// ::= .syntax unified | divided
4049 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
4050 const AsmToken &Tok = Parser.getTok();
4051 if (Tok.isNot(AsmToken::Identifier))
4052 return Error(L, "unexpected token in .syntax directive");
4053 StringRef Mode = Tok.getString();
4054 if (Mode == "unified" || Mode == "UNIFIED")
4056 else if (Mode == "divided" || Mode == "DIVIDED")
4057 return Error(L, "'.syntax divided' arm asssembly not supported");
4059 return Error(L, "unrecognized syntax mode in .syntax directive");
4061 if (getLexer().isNot(AsmToken::EndOfStatement))
4062 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
4065 // TODO tell the MC streamer the mode
4066 // getParser().getStreamer().Emit???();
4070 /// parseDirectiveCode
4071 /// ::= .code 16 | 32
4072 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
4073 const AsmToken &Tok = Parser.getTok();
4074 if (Tok.isNot(AsmToken::Integer))
4075 return Error(L, "unexpected token in .code directive");
4076 int64_t Val = Parser.getTok().getIntVal();
4082 return Error(L, "invalid operand to .code directive");
4084 if (getLexer().isNot(AsmToken::EndOfStatement))
4085 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
4091 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
4095 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
4101 extern "C" void LLVMInitializeARMAsmLexer();
4103 /// Force static initialization.
4104 extern "C" void LLVMInitializeARMAsmParser() {
4105 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
4106 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
4107 LLVMInitializeARMAsmLexer();
4110 #define GET_REGISTER_MATCHER
4111 #define GET_MATCHER_IMPLEMENTATION
4112 #include "ARMGenAsmMatcher.inc"