1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMSubtarget.h"
12 #include "llvm/MC/MCParser/MCAsmLexer.h"
13 #include "llvm/MC/MCParser/MCAsmParser.h"
14 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
15 #include "llvm/MC/MCStreamer.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/Target/TargetRegistry.h"
19 #include "llvm/Target/TargetAsmParser.h"
20 #include "llvm/Support/SourceMgr.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/ADT/OwningPtr.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/StringSwitch.h"
25 #include "llvm/ADT/Twine.h"
28 // The shift types for register controlled shifts in arm memory addressing
40 class ARMAsmParser : public TargetAsmParser {
45 MCAsmParser &getParser() const { return Parser; }
47 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
49 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
51 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
53 ARMOperand *MaybeParseRegister(bool ParseWriteBack);
55 bool ParseRegisterList(OwningPtr<ARMOperand> &Op);
57 bool ParseMemory(OwningPtr<ARMOperand> &Op);
59 bool ParseMemoryOffsetReg(bool &Negative,
60 bool &OffsetRegShifted,
61 enum ShiftType &ShiftType,
62 const MCExpr *&ShiftAmount,
63 const MCExpr *&Offset,
68 bool ParseShift(enum ShiftType &St, const MCExpr *&ShiftAmount, SMLoc &E);
70 bool ParseOperand(OwningPtr<ARMOperand> &Op);
72 bool ParseDirectiveWord(unsigned Size, SMLoc L);
74 bool ParseDirectiveThumb(SMLoc L);
76 bool ParseDirectiveThumbFunc(SMLoc L);
78 bool ParseDirectiveCode(SMLoc L);
80 bool ParseDirectiveSyntax(SMLoc L);
82 bool MatchAndEmitInstruction(SMLoc IDLoc,
83 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
87 if (MatchInstructionImpl(Operands, Inst, ErrorInfo) == Match_Success) {
88 Out.EmitInstruction(Inst);
92 // FIXME: We should give nicer diagnostics about the exact failure.
93 Error(IDLoc, "unrecognized instruction");
97 /// @name Auto-generated Match Functions
100 #define GET_ASSEMBLER_HEADER
101 #include "ARMGenAsmMatcher.inc"
107 ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
108 : TargetAsmParser(T), Parser(_Parser), TM(_TM) {}
110 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
111 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
113 virtual bool ParseDirective(AsmToken DirectiveID);
115 } // end anonymous namespace
119 /// ARMOperand - Instances of this class represent a parsed ARM machine
121 struct ARMOperand : public MCParsedAsmOperand {
131 SMLoc StartLoc, EndLoc;
135 ARMCC::CondCodes Val;
152 // This is for all forms of ARM address expressions
155 unsigned OffsetRegNum; // used when OffsetIsReg is true
156 const MCExpr *Offset; // used when OffsetIsReg is false
157 const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
158 enum ShiftType ShiftType; // used when OffsetRegShifted is true
160 OffsetRegShifted : 1, // only used when OffsetIsReg is true
164 Negative : 1, // only used when OffsetIsReg is true
170 //ARMOperand(KindTy K, SMLoc S, SMLoc E)
171 // : Kind(K), StartLoc(S), EndLoc(E) {}
173 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
175 StartLoc = o.StartLoc;
196 /// getStartLoc - Get the location of the first token of this operand.
197 SMLoc getStartLoc() const { return StartLoc; }
198 /// getEndLoc - Get the location of the last token of this operand.
199 SMLoc getEndLoc() const { return EndLoc; }
201 ARMCC::CondCodes getCondCode() const {
202 assert(Kind == CondCode && "Invalid access!");
206 StringRef getToken() const {
207 assert(Kind == Token && "Invalid access!");
208 return StringRef(Tok.Data, Tok.Length);
211 unsigned getReg() const {
212 assert(Kind == Register && "Invalid access!");
216 const MCExpr *getImm() const {
217 assert(Kind == Immediate && "Invalid access!");
221 bool isCondCode() const { return Kind == CondCode; }
223 bool isImm() const { return Kind == Immediate; }
225 bool isReg() const { return Kind == Register; }
227 bool isToken() const {return Kind == Token; }
229 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
230 // Add as immediates when possible.
231 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
232 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
234 Inst.addOperand(MCOperand::CreateExpr(Expr));
237 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
238 assert(N == 2 && "Invalid number of operands!");
239 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
240 // FIXME: What belongs here?
241 Inst.addOperand(MCOperand::CreateReg(0));
244 void addRegOperands(MCInst &Inst, unsigned N) const {
245 assert(N == 1 && "Invalid number of operands!");
246 Inst.addOperand(MCOperand::CreateReg(getReg()));
249 void addImmOperands(MCInst &Inst, unsigned N) const {
250 assert(N == 1 && "Invalid number of operands!");
251 addExpr(Inst, getImm());
254 virtual void dump(raw_ostream &OS) const;
256 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
257 ARMOperand *Op = new ARMOperand(CondCode);
264 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
265 ARMOperand *Op = new ARMOperand(Token);
266 Op->Tok.Data = Str.data();
267 Op->Tok.Length = Str.size();
273 static ARMOperand *CreateReg(unsigned RegNum, bool Writeback, SMLoc S,
275 ARMOperand *Op = new ARMOperand(Register);
276 Op->Reg.RegNum = RegNum;
277 Op->Reg.Writeback = Writeback;
283 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
284 ARMOperand *Op = new ARMOperand(Immediate);
291 static ARMOperand *CreateMem(unsigned BaseRegNum, bool OffsetIsReg,
292 const MCExpr *Offset, unsigned OffsetRegNum,
293 bool OffsetRegShifted, enum ShiftType ShiftType,
294 const MCExpr *ShiftAmount, bool Preindexed,
295 bool Postindexed, bool Negative, bool Writeback,
297 ARMOperand *Op = new ARMOperand(Memory);
298 Op->Mem.BaseRegNum = BaseRegNum;
299 Op->Mem.OffsetIsReg = OffsetIsReg;
300 Op->Mem.Offset = Offset;
301 Op->Mem.OffsetRegNum = OffsetRegNum;
302 Op->Mem.OffsetRegShifted = OffsetRegShifted;
303 Op->Mem.ShiftType = ShiftType;
304 Op->Mem.ShiftAmount = ShiftAmount;
305 Op->Mem.Preindexed = Preindexed;
306 Op->Mem.Postindexed = Postindexed;
307 Op->Mem.Negative = Negative;
308 Op->Mem.Writeback = Writeback;
316 ARMOperand(KindTy K) : Kind(K) {}
319 } // end anonymous namespace.
321 void ARMOperand::dump(raw_ostream &OS) const {
324 OS << ARMCondCodeToString(getCondCode());
333 OS << "<register " << getReg() << ">";
336 OS << "'" << getToken() << "'";
341 /// @name Auto-generated Match Functions
344 static unsigned MatchRegisterName(StringRef Name);
348 /// Try to parse a register name. The token must be an Identifier when called,
349 /// and if it is a register name the token is eaten and a Reg operand is created
350 /// and returned. Otherwise return null.
352 /// TODO this is likely to change to allow different register types and or to
353 /// parse for a specific register type.
354 ARMOperand *ARMAsmParser::MaybeParseRegister(bool ParseWriteBack) {
356 const AsmToken &Tok = Parser.getTok();
357 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
359 // FIXME: Validate register for the current architecture; we have to do
360 // validation later, so maybe there is no need for this here.
363 RegNum = MatchRegisterName(Tok.getString());
369 Parser.Lex(); // Eat identifier token.
371 E = Parser.getTok().getLoc();
373 bool Writeback = false;
374 if (ParseWriteBack) {
375 const AsmToken &ExclaimTok = Parser.getTok();
376 if (ExclaimTok.is(AsmToken::Exclaim)) {
377 E = ExclaimTok.getLoc();
379 Parser.Lex(); // Eat exclaim token
383 return ARMOperand::CreateReg(RegNum, Writeback, S, E);
386 /// Parse a register list, return false if successful else return true or an
387 /// error. The first token must be a '{' when called.
388 bool ARMAsmParser::ParseRegisterList(OwningPtr<ARMOperand> &Op) {
390 assert(Parser.getTok().is(AsmToken::LCurly) &&
391 "Token is not an Left Curly Brace");
392 S = Parser.getTok().getLoc();
393 Parser.Lex(); // Eat left curly brace token.
395 const AsmToken &RegTok = Parser.getTok();
396 SMLoc RegLoc = RegTok.getLoc();
397 if (RegTok.isNot(AsmToken::Identifier))
398 return Error(RegLoc, "register expected");
399 int RegNum = MatchRegisterName(RegTok.getString());
401 return Error(RegLoc, "register expected");
402 Parser.Lex(); // Eat identifier token.
403 unsigned RegList = 1 << RegNum;
405 int HighRegNum = RegNum;
406 // TODO ranges like "{Rn-Rm}"
407 while (Parser.getTok().is(AsmToken::Comma)) {
408 Parser.Lex(); // Eat comma token.
410 const AsmToken &RegTok = Parser.getTok();
411 SMLoc RegLoc = RegTok.getLoc();
412 if (RegTok.isNot(AsmToken::Identifier))
413 return Error(RegLoc, "register expected");
414 int RegNum = MatchRegisterName(RegTok.getString());
416 return Error(RegLoc, "register expected");
418 if (RegList & (1 << RegNum))
419 Warning(RegLoc, "register duplicated in register list");
420 else if (RegNum <= HighRegNum)
421 Warning(RegLoc, "register not in ascending order in register list");
422 RegList |= 1 << RegNum;
425 Parser.Lex(); // Eat identifier token.
427 const AsmToken &RCurlyTok = Parser.getTok();
428 if (RCurlyTok.isNot(AsmToken::RCurly))
429 return Error(RCurlyTok.getLoc(), "'}' expected");
430 E = RCurlyTok.getLoc();
431 Parser.Lex(); // Eat left curly brace token.
436 /// Parse an arm memory expression, return false if successful else return true
437 /// or an error. The first token must be a '[' when called.
438 /// TODO Only preindexing and postindexing addressing are started, unindexed
439 /// with option, etc are still to do.
440 bool ARMAsmParser::ParseMemory(OwningPtr<ARMOperand> &Op) {
442 assert(Parser.getTok().is(AsmToken::LBrac) &&
443 "Token is not an Left Bracket");
444 S = Parser.getTok().getLoc();
445 Parser.Lex(); // Eat left bracket token.
447 const AsmToken &BaseRegTok = Parser.getTok();
448 if (BaseRegTok.isNot(AsmToken::Identifier))
449 return Error(BaseRegTok.getLoc(), "register expected");
450 Op.reset(MaybeParseRegister(false));
452 return Error(BaseRegTok.getLoc(), "register expected");
453 int BaseRegNum = Op->getReg();
455 bool Preindexed = false;
456 bool Postindexed = false;
457 bool OffsetIsReg = false;
458 bool Negative = false;
459 bool Writeback = false;
461 // First look for preindexed address forms, that is after the "[Rn" we now
462 // have to see if the next token is a comma.
463 const AsmToken &Tok = Parser.getTok();
464 if (Tok.is(AsmToken::Comma)) {
466 Parser.Lex(); // Eat comma token.
468 bool OffsetRegShifted;
469 enum ShiftType ShiftType;
470 const MCExpr *ShiftAmount;
471 const MCExpr *Offset;
472 if(ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
473 Offset, OffsetIsReg, OffsetRegNum, E))
475 const AsmToken &RBracTok = Parser.getTok();
476 if (RBracTok.isNot(AsmToken::RBrac))
477 return Error(RBracTok.getLoc(), "']' expected");
478 E = RBracTok.getLoc();
479 Parser.Lex(); // Eat right bracket token.
481 const AsmToken &ExclaimTok = Parser.getTok();
482 if (ExclaimTok.is(AsmToken::Exclaim)) {
483 E = ExclaimTok.getLoc();
485 Parser.Lex(); // Eat exclaim token
488 ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
489 OffsetRegShifted, ShiftType, ShiftAmount,
490 Preindexed, Postindexed, Negative, Writeback, S,E));
493 // The "[Rn" we have so far was not followed by a comma.
494 else if (Tok.is(AsmToken::RBrac)) {
495 // This is a post indexing addressing forms, that is a ']' follows after
500 Parser.Lex(); // Eat right bracket token.
502 int OffsetRegNum = 0;
503 bool OffsetRegShifted = false;
504 enum ShiftType ShiftType;
505 const MCExpr *ShiftAmount;
506 const MCExpr *Offset;
508 const AsmToken &NextTok = Parser.getTok();
509 if (NextTok.isNot(AsmToken::EndOfStatement)) {
510 if (NextTok.isNot(AsmToken::Comma))
511 return Error(NextTok.getLoc(), "',' expected");
512 Parser.Lex(); // Eat comma token.
513 if(ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
514 ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
520 ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
521 OffsetRegShifted, ShiftType, ShiftAmount,
522 Preindexed, Postindexed, Negative, Writeback, S,E));
529 /// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
530 /// we will parse the following (were +/- means that a plus or minus is
535 /// we return false on success or an error otherwise.
536 bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
537 bool &OffsetRegShifted,
538 enum ShiftType &ShiftType,
539 const MCExpr *&ShiftAmount,
540 const MCExpr *&Offset,
544 OwningPtr<ARMOperand> Op;
546 OffsetRegShifted = false;
549 const AsmToken &NextTok = Parser.getTok();
550 E = NextTok.getLoc();
551 if (NextTok.is(AsmToken::Plus))
552 Parser.Lex(); // Eat plus token.
553 else if (NextTok.is(AsmToken::Minus)) {
555 Parser.Lex(); // Eat minus token
557 // See if there is a register following the "[Rn," or "[Rn]," we have so far.
558 const AsmToken &OffsetRegTok = Parser.getTok();
559 if (OffsetRegTok.is(AsmToken::Identifier)) {
560 Op.reset(MaybeParseRegister(false));
561 OffsetIsReg = Op.get() != 0;
564 OffsetRegNum = Op->getReg();
567 // If we parsed a register as the offset then their can be a shift after that
568 if (OffsetRegNum != -1) {
569 // Look for a comma then a shift
570 const AsmToken &Tok = Parser.getTok();
571 if (Tok.is(AsmToken::Comma)) {
572 Parser.Lex(); // Eat comma token.
574 const AsmToken &Tok = Parser.getTok();
575 if (ParseShift(ShiftType, ShiftAmount, E))
576 return Error(Tok.getLoc(), "shift expected");
577 OffsetRegShifted = true;
580 else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
581 // Look for #offset following the "[Rn," or "[Rn],"
582 const AsmToken &HashTok = Parser.getTok();
583 if (HashTok.isNot(AsmToken::Hash))
584 return Error(HashTok.getLoc(), "'#' expected");
586 Parser.Lex(); // Eat hash token.
588 if (getParser().ParseExpression(Offset))
590 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
595 /// ParseShift as one of these two:
596 /// ( lsl | lsr | asr | ror ) , # shift_amount
598 /// and returns true if it parses a shift otherwise it returns false.
599 bool ARMAsmParser::ParseShift(ShiftType &St, const MCExpr *&ShiftAmount,
601 const AsmToken &Tok = Parser.getTok();
602 if (Tok.isNot(AsmToken::Identifier))
604 StringRef ShiftName = Tok.getString();
605 if (ShiftName == "lsl" || ShiftName == "LSL")
607 else if (ShiftName == "lsr" || ShiftName == "LSR")
609 else if (ShiftName == "asr" || ShiftName == "ASR")
611 else if (ShiftName == "ror" || ShiftName == "ROR")
613 else if (ShiftName == "rrx" || ShiftName == "RRX")
617 Parser.Lex(); // Eat shift type token.
623 // Otherwise, there must be a '#' and a shift amount.
624 const AsmToken &HashTok = Parser.getTok();
625 if (HashTok.isNot(AsmToken::Hash))
626 return Error(HashTok.getLoc(), "'#' expected");
627 Parser.Lex(); // Eat hash token.
629 if (getParser().ParseExpression(ShiftAmount))
635 /// Parse a arm instruction operand. For now this parses the operand regardless
637 bool ARMAsmParser::ParseOperand(OwningPtr<ARMOperand> &Op) {
640 switch (getLexer().getKind()) {
641 case AsmToken::Identifier:
642 Op.reset(MaybeParseRegister(true));
645 // This was not a register so parse other operands that start with an
646 // identifier (like labels) as expressions and create them as immediates.
648 S = Parser.getTok().getLoc();
649 if (getParser().ParseExpression(IdVal))
651 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
652 Op.reset(ARMOperand::CreateImm(IdVal, S, E));
654 case AsmToken::LBrac:
655 return ParseMemory(Op);
656 case AsmToken::LCurly:
657 return ParseRegisterList(Op);
660 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
661 S = Parser.getTok().getLoc();
663 const MCExpr *ImmVal;
664 if (getParser().ParseExpression(ImmVal))
666 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
667 Op.reset(ARMOperand::CreateImm(ImmVal, S, E));
670 return Error(Parser.getTok().getLoc(), "unexpected token in operand");
674 /// Parse an arm instruction mnemonic followed by its operands.
675 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
676 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
677 // Create the leading tokens for the mnemonic, split by '.' characters.
678 size_t Start = 0, Next = Name.find('.');
679 StringRef Head = Name.slice(Start, Next);
681 // Determine the predicate, if any.
683 // FIXME: We need a way to check whether a prefix supports predication,
684 // otherwise we will end up with an ambiguity for instructions that happen to
685 // end with a predicate name.
686 unsigned CC = StringSwitch<unsigned>(Head.substr(Head.size()-2))
687 .Case("eq", ARMCC::EQ)
688 .Case("ne", ARMCC::NE)
689 .Case("hs", ARMCC::HS)
690 .Case("lo", ARMCC::LO)
691 .Case("mi", ARMCC::MI)
692 .Case("pl", ARMCC::PL)
693 .Case("vs", ARMCC::VS)
694 .Case("vc", ARMCC::VC)
695 .Case("hi", ARMCC::HI)
696 .Case("ls", ARMCC::LS)
697 .Case("ge", ARMCC::GE)
698 .Case("lt", ARMCC::LT)
699 .Case("gt", ARMCC::GT)
700 .Case("le", ARMCC::LE)
701 .Case("al", ARMCC::AL)
705 Head = Head.slice(0, Head.size() - 2);
709 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
710 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), NameLoc));
712 // Add the remaining tokens in the mnemonic.
713 while (Next != StringRef::npos) {
715 Next = Name.find('.', Start + 1);
716 Head = Name.slice(Start, Next);
718 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
721 // Read the remaining operands.
722 if (getLexer().isNot(AsmToken::EndOfStatement)) {
723 // Read the first operand.
724 OwningPtr<ARMOperand> Op;
725 if (ParseOperand(Op)) {
726 Parser.EatToEndOfStatement();
729 Operands.push_back(Op.take());
731 while (getLexer().is(AsmToken::Comma)) {
732 Parser.Lex(); // Eat the comma.
734 // Parse and remember the operand.
735 if (ParseOperand(Op)) {
736 Parser.EatToEndOfStatement();
739 Operands.push_back(Op.take());
743 if (getLexer().isNot(AsmToken::EndOfStatement)) {
744 Parser.EatToEndOfStatement();
745 return TokError("unexpected token in argument list");
747 Parser.Lex(); // Consume the EndOfStatement
751 /// ParseDirective parses the arm specific directives
752 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
753 StringRef IDVal = DirectiveID.getIdentifier();
754 if (IDVal == ".word")
755 return ParseDirectiveWord(4, DirectiveID.getLoc());
756 else if (IDVal == ".thumb")
757 return ParseDirectiveThumb(DirectiveID.getLoc());
758 else if (IDVal == ".thumb_func")
759 return ParseDirectiveThumbFunc(DirectiveID.getLoc());
760 else if (IDVal == ".code")
761 return ParseDirectiveCode(DirectiveID.getLoc());
762 else if (IDVal == ".syntax")
763 return ParseDirectiveSyntax(DirectiveID.getLoc());
767 /// ParseDirectiveWord
768 /// ::= .word [ expression (, expression)* ]
769 bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
770 if (getLexer().isNot(AsmToken::EndOfStatement)) {
773 if (getParser().ParseExpression(Value))
776 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
778 if (getLexer().is(AsmToken::EndOfStatement))
781 // FIXME: Improve diagnostic.
782 if (getLexer().isNot(AsmToken::Comma))
783 return Error(L, "unexpected token in directive");
792 /// ParseDirectiveThumb
794 bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
795 if (getLexer().isNot(AsmToken::EndOfStatement))
796 return Error(L, "unexpected token in directive");
799 // TODO: set thumb mode
800 // TODO: tell the MC streamer the mode
801 // getParser().getStreamer().Emit???();
805 /// ParseDirectiveThumbFunc
806 /// ::= .thumbfunc symbol_name
807 bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
808 const AsmToken &Tok = Parser.getTok();
809 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
810 return Error(L, "unexpected token in .syntax directive");
811 Parser.Lex(); // Consume the identifier token.
813 if (getLexer().isNot(AsmToken::EndOfStatement))
814 return Error(L, "unexpected token in directive");
817 // TODO: mark symbol as a thumb symbol
818 // getParser().getStreamer().Emit???();
822 /// ParseDirectiveSyntax
823 /// ::= .syntax unified | divided
824 bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
825 const AsmToken &Tok = Parser.getTok();
826 if (Tok.isNot(AsmToken::Identifier))
827 return Error(L, "unexpected token in .syntax directive");
828 StringRef Mode = Tok.getString();
829 if (Mode == "unified" || Mode == "UNIFIED")
831 else if (Mode == "divided" || Mode == "DIVIDED")
834 return Error(L, "unrecognized syntax mode in .syntax directive");
836 if (getLexer().isNot(AsmToken::EndOfStatement))
837 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
840 // TODO tell the MC streamer the mode
841 // getParser().getStreamer().Emit???();
845 /// ParseDirectiveCode
846 /// ::= .code 16 | 32
847 bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
848 const AsmToken &Tok = Parser.getTok();
849 if (Tok.isNot(AsmToken::Integer))
850 return Error(L, "unexpected token in .code directive");
851 int64_t Val = Parser.getTok().getIntVal();
857 return Error(L, "invalid operand to .code directive");
859 if (getLexer().isNot(AsmToken::EndOfStatement))
860 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
863 // TODO tell the MC streamer the mode
864 // getParser().getStreamer().Emit???();
868 extern "C" void LLVMInitializeARMAsmLexer();
870 /// Force static initialization.
871 extern "C" void LLVMInitializeARMAsmParser() {
872 RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
873 RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
874 LLVMInitializeARMAsmLexer();
877 #define GET_REGISTER_MATCHER
878 #define GET_MATCHER_IMPLEMENTATION
879 #include "ARMGenAsmMatcher.inc"