1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMBaseRegisterInfo.h"
12 #include "ARMSubtarget.h"
13 #include "MCTargetDesc/ARMAddressingModes.h"
14 #include "MCTargetDesc/ARMMCExpr.h"
15 #include "llvm/MC/MCParser/MCAsmLexer.h"
16 #include "llvm/MC/MCParser/MCAsmParser.h"
17 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
18 #include "llvm/MC/MCAsmInfo.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCStreamer.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/Target/TargetRegistry.h"
25 #include "llvm/Target/TargetAsmParser.h"
26 #include "llvm/Support/SourceMgr.h"
27 #include "llvm/Support/raw_ostream.h"
28 #include "llvm/ADT/OwningPtr.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/ADT/StringExtras.h"
31 #include "llvm/ADT/StringSwitch.h"
32 #include "llvm/ADT/Twine.h"
40 class ARMAsmParser : public TargetAsmParser {
44 MCAsmParser &getParser() const { return Parser; }
45 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
47 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
48 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
50 int TryParseRegister();
51 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
52 bool TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
53 int TryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
54 bool ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
55 bool ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &,
56 ARMII::AddrMode AddrMode);
57 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
58 bool ParsePrefix(ARMMCExpr::VariantKind &RefKind);
59 const MCExpr *ApplyPrefixToExpr(const MCExpr *E,
60 MCSymbolRefExpr::VariantKind Variant);
63 bool ParseMemoryOffsetReg(bool &Negative,
64 bool &OffsetRegShifted,
65 enum ARM_AM::ShiftOpc &ShiftType,
66 const MCExpr *&ShiftAmount,
67 const MCExpr *&Offset,
71 bool ParseShift(enum ARM_AM::ShiftOpc &St,
72 const MCExpr *&ShiftAmount, SMLoc &E);
73 bool ParseDirectiveWord(unsigned Size, SMLoc L);
74 bool ParseDirectiveThumb(SMLoc L);
75 bool ParseDirectiveThumbFunc(SMLoc L);
76 bool ParseDirectiveCode(SMLoc L);
77 bool ParseDirectiveSyntax(SMLoc L);
79 bool MatchAndEmitInstruction(SMLoc IDLoc,
80 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
82 StringRef SplitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
83 bool &CarrySetting, unsigned &ProcessorIMod);
84 void GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
85 bool &CanAcceptPredicationCode);
87 bool isThumb() const {
88 // FIXME: Can tablegen auto-generate this?
89 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
91 bool isThumbOne() const {
92 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
95 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
96 setAvailableFeatures(FB);
99 /// @name Auto-generated Match Functions
102 #define GET_ASSEMBLER_HEADER
103 #include "ARMGenAsmMatcher.inc"
107 OperandMatchResultTy tryParseCoprocNumOperand(
108 SmallVectorImpl<MCParsedAsmOperand*>&);
109 OperandMatchResultTy tryParseCoprocRegOperand(
110 SmallVectorImpl<MCParsedAsmOperand*>&);
111 OperandMatchResultTy tryParseMemBarrierOptOperand(
112 SmallVectorImpl<MCParsedAsmOperand*>&);
113 OperandMatchResultTy tryParseProcIFlagsOperand(
114 SmallVectorImpl<MCParsedAsmOperand*>&);
115 OperandMatchResultTy tryParseMSRMaskOperand(
116 SmallVectorImpl<MCParsedAsmOperand*>&);
117 OperandMatchResultTy tryParseMemMode2Operand(
118 SmallVectorImpl<MCParsedAsmOperand*>&);
119 OperandMatchResultTy tryParseMemMode3Operand(
120 SmallVectorImpl<MCParsedAsmOperand*>&);
121 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
122 StringRef Op, int Low, int High);
123 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
124 return parsePKHImm(O, "lsl", 0, 31);
126 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
127 return parsePKHImm(O, "asr", 1, 32);
130 // Asm Match Converter Methods
131 bool CvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
132 const SmallVectorImpl<MCParsedAsmOperand*> &);
133 bool CvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
134 const SmallVectorImpl<MCParsedAsmOperand*> &);
135 bool CvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
136 const SmallVectorImpl<MCParsedAsmOperand*> &);
137 bool CvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
138 const SmallVectorImpl<MCParsedAsmOperand*> &);
141 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
142 : TargetAsmParser(), STI(_STI), Parser(_Parser) {
143 MCAsmParserExtension::Initialize(_Parser);
145 // Initialize the set of available features.
146 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
149 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
150 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
151 virtual bool ParseDirective(AsmToken DirectiveID);
153 } // end anonymous namespace
157 /// ARMOperand - Instances of this class represent a parsed ARM machine
159 class ARMOperand : public MCParsedAsmOperand {
180 SMLoc StartLoc, EndLoc;
181 SmallVector<unsigned, 8> Registers;
185 ARMCC::CondCodes Val;
197 ARM_PROC::IFlags Val;
217 /// Combined record for all forms of ARM address expressions.
219 ARMII::AddrMode AddrMode;
222 unsigned RegNum; ///< Offset register num, when OffsetIsReg.
223 const MCExpr *Value; ///< Offset value, when !OffsetIsReg.
225 const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
226 enum ARM_AM::ShiftOpc ShiftType; // used when OffsetRegShifted is true
227 unsigned OffsetRegShifted : 1; // only used when OffsetIsReg is true
228 unsigned Preindexed : 1;
229 unsigned Postindexed : 1;
230 unsigned OffsetIsReg : 1;
231 unsigned Negative : 1; // only used when OffsetIsReg is true
232 unsigned Writeback : 1;
236 ARM_AM::ShiftOpc ShiftTy;
240 ARM_AM::ShiftOpc ShiftTy;
246 ARM_AM::ShiftOpc ShiftTy;
252 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
254 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
256 StartLoc = o.StartLoc;
270 case DPRRegisterList:
271 case SPRRegisterList:
272 Registers = o.Registers;
296 case ShiftedRegister:
297 ShiftedReg = o.ShiftedReg;
299 case ShiftedImmediate:
300 ShiftedImm = o.ShiftedImm;
305 /// getStartLoc - Get the location of the first token of this operand.
306 SMLoc getStartLoc() const { return StartLoc; }
307 /// getEndLoc - Get the location of the last token of this operand.
308 SMLoc getEndLoc() const { return EndLoc; }
310 ARMCC::CondCodes getCondCode() const {
311 assert(Kind == CondCode && "Invalid access!");
315 unsigned getCoproc() const {
316 assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
320 StringRef getToken() const {
321 assert(Kind == Token && "Invalid access!");
322 return StringRef(Tok.Data, Tok.Length);
325 unsigned getReg() const {
326 assert((Kind == Register || Kind == CCOut) && "Invalid access!");
330 const SmallVectorImpl<unsigned> &getRegList() const {
331 assert((Kind == RegisterList || Kind == DPRRegisterList ||
332 Kind == SPRRegisterList) && "Invalid access!");
336 const MCExpr *getImm() const {
337 assert(Kind == Immediate && "Invalid access!");
341 ARM_MB::MemBOpt getMemBarrierOpt() const {
342 assert(Kind == MemBarrierOpt && "Invalid access!");
346 ARM_PROC::IFlags getProcIFlags() const {
347 assert(Kind == ProcIFlags && "Invalid access!");
351 unsigned getMSRMask() const {
352 assert(Kind == MSRMask && "Invalid access!");
356 /// @name Memory Operand Accessors
358 ARMII::AddrMode getMemAddrMode() const {
361 unsigned getMemBaseRegNum() const {
362 return Mem.BaseRegNum;
364 unsigned getMemOffsetRegNum() const {
365 assert(Mem.OffsetIsReg && "Invalid access!");
366 return Mem.Offset.RegNum;
368 const MCExpr *getMemOffset() const {
369 assert(!Mem.OffsetIsReg && "Invalid access!");
370 return Mem.Offset.Value;
372 unsigned getMemOffsetRegShifted() const {
373 assert(Mem.OffsetIsReg && "Invalid access!");
374 return Mem.OffsetRegShifted;
376 const MCExpr *getMemShiftAmount() const {
377 assert(Mem.OffsetIsReg && Mem.OffsetRegShifted && "Invalid access!");
378 return Mem.ShiftAmount;
380 enum ARM_AM::ShiftOpc getMemShiftType() const {
381 assert(Mem.OffsetIsReg && Mem.OffsetRegShifted && "Invalid access!");
382 return Mem.ShiftType;
384 bool getMemPreindexed() const { return Mem.Preindexed; }
385 bool getMemPostindexed() const { return Mem.Postindexed; }
386 bool getMemOffsetIsReg() const { return Mem.OffsetIsReg; }
387 bool getMemNegative() const { return Mem.Negative; }
388 bool getMemWriteback() const { return Mem.Writeback; }
392 bool isCoprocNum() const { return Kind == CoprocNum; }
393 bool isCoprocReg() const { return Kind == CoprocReg; }
394 bool isCondCode() const { return Kind == CondCode; }
395 bool isCCOut() const { return Kind == CCOut; }
396 bool isImm() const { return Kind == Immediate; }
397 bool isImm0_255() const {
398 if (Kind != Immediate)
400 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
401 if (!CE) return false;
402 int64_t Value = CE->getValue();
403 return Value >= 0 && Value < 256;
405 bool isImm0_7() const {
406 if (Kind != Immediate)
408 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
409 if (!CE) return false;
410 int64_t Value = CE->getValue();
411 return Value >= 0 && Value < 8;
413 bool isImm0_15() const {
414 if (Kind != Immediate)
416 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
417 if (!CE) return false;
418 int64_t Value = CE->getValue();
419 return Value >= 0 && Value < 16;
421 bool isImm0_65535() const {
422 if (Kind != Immediate)
424 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
425 if (!CE) return false;
426 int64_t Value = CE->getValue();
427 return Value >= 0 && Value < 65536;
429 bool isImm0_65535Expr() const {
430 if (Kind != Immediate)
432 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
433 // If it's not a constant expression, it'll generate a fixup and be
435 if (!CE) return true;
436 int64_t Value = CE->getValue();
437 return Value >= 0 && Value < 65536;
439 bool isPKHLSLImm() const {
440 if (Kind != Immediate)
442 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
443 if (!CE) return false;
444 int64_t Value = CE->getValue();
445 return Value >= 0 && Value < 32;
447 bool isPKHASRImm() const {
448 if (Kind != Immediate)
450 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
451 if (!CE) return false;
452 int64_t Value = CE->getValue();
453 return Value > 0 && Value <= 32;
455 bool isARMSOImm() const {
456 if (Kind != Immediate)
458 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
459 if (!CE) return false;
460 int64_t Value = CE->getValue();
461 return ARM_AM::getSOImmVal(Value) != -1;
463 bool isT2SOImm() const {
464 if (Kind != Immediate)
466 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
467 if (!CE) return false;
468 int64_t Value = CE->getValue();
469 return ARM_AM::getT2SOImmVal(Value) != -1;
471 bool isReg() const { return Kind == Register; }
472 bool isRegList() const { return Kind == RegisterList; }
473 bool isDPRRegList() const { return Kind == DPRRegisterList; }
474 bool isSPRRegList() const { return Kind == SPRRegisterList; }
475 bool isToken() const { return Kind == Token; }
476 bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
477 bool isMemory() const { return Kind == Memory; }
478 bool isShifter() const { return Kind == Shifter; }
479 bool isShiftedReg() const { return Kind == ShiftedRegister; }
480 bool isShiftedImm() const { return Kind == ShiftedImmediate; }
481 bool isMemMode2() const {
482 if (getMemAddrMode() != ARMII::AddrMode2)
485 if (getMemOffsetIsReg())
488 if (getMemNegative() &&
489 !(getMemPostindexed() || getMemPreindexed()))
492 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
493 if (!CE) return false;
494 int64_t Value = CE->getValue();
496 // The offset must be in the range 0-4095 (imm12).
497 if (Value > 4095 || Value < -4095)
502 bool isMemMode3() const {
503 if (getMemAddrMode() != ARMII::AddrMode3)
506 if (getMemOffsetIsReg()) {
507 if (getMemOffsetRegShifted())
508 return false; // No shift with offset reg allowed
512 if (getMemNegative() &&
513 !(getMemPostindexed() || getMemPreindexed()))
516 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
517 if (!CE) return false;
518 int64_t Value = CE->getValue();
520 // The offset must be in the range 0-255 (imm8).
521 if (Value > 255 || Value < -255)
526 bool isMemMode5() const {
527 if (!isMemory() || getMemOffsetIsReg() || getMemWriteback() ||
531 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
532 if (!CE) return false;
534 // The offset must be a multiple of 4 in the range 0-1020.
535 int64_t Value = CE->getValue();
536 return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020);
538 bool isMemMode7() const {
540 getMemPreindexed() ||
541 getMemPostindexed() ||
542 getMemOffsetIsReg() ||
547 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
548 if (!CE) return false;
555 bool isMemModeRegThumb() const {
556 if (!isMemory() || !getMemOffsetIsReg() || getMemWriteback())
560 bool isMemModeImmThumb() const {
561 if (!isMemory() || getMemOffsetIsReg() || getMemWriteback())
564 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
565 if (!CE) return false;
567 // The offset must be a multiple of 4 in the range 0-124.
568 uint64_t Value = CE->getValue();
569 return ((Value & 0x3) == 0 && Value <= 124);
571 bool isMSRMask() const { return Kind == MSRMask; }
572 bool isProcIFlags() const { return Kind == ProcIFlags; }
574 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
575 // Add as immediates when possible. Null MCExpr = 0.
577 Inst.addOperand(MCOperand::CreateImm(0));
578 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
579 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
581 Inst.addOperand(MCOperand::CreateExpr(Expr));
584 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
585 assert(N == 2 && "Invalid number of operands!");
586 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
587 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
588 Inst.addOperand(MCOperand::CreateReg(RegNum));
591 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
592 assert(N == 1 && "Invalid number of operands!");
593 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
596 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
597 assert(N == 1 && "Invalid number of operands!");
598 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
601 void addCCOutOperands(MCInst &Inst, unsigned N) const {
602 assert(N == 1 && "Invalid number of operands!");
603 Inst.addOperand(MCOperand::CreateReg(getReg()));
606 void addRegOperands(MCInst &Inst, unsigned N) const {
607 assert(N == 1 && "Invalid number of operands!");
608 Inst.addOperand(MCOperand::CreateReg(getReg()));
611 void addShiftedRegOperands(MCInst &Inst, unsigned N) const {
612 assert(N == 3 && "Invalid number of operands!");
613 assert(isShiftedReg() && "addShiftedRegOperands() on non ShiftedReg!");
614 Inst.addOperand(MCOperand::CreateReg(ShiftedReg.SrcReg));
615 Inst.addOperand(MCOperand::CreateReg(ShiftedReg.ShiftReg));
616 Inst.addOperand(MCOperand::CreateImm(
617 ARM_AM::getSORegOpc(ShiftedReg.ShiftTy, ShiftedReg.ShiftImm)));
620 void addShiftedImmOperands(MCInst &Inst, unsigned N) const {
621 assert(N == 3 && "Invalid number of operands!");
622 assert(isShiftedImm() && "addShiftedImmOperands() on non ShiftedImm!");
623 Inst.addOperand(MCOperand::CreateReg(ShiftedImm.SrcReg));
624 if (ShiftedImm.ShiftTy == ARM_AM::rrx)
625 Inst.addOperand(MCOperand::CreateReg(ShiftedImm.SrcReg));
627 Inst.addOperand(MCOperand::CreateReg(0));
628 Inst.addOperand(MCOperand::CreateImm(
629 ARM_AM::getSORegOpc(ShiftedImm.ShiftTy, ShiftedImm.ShiftImm)));
633 void addShifterOperands(MCInst &Inst, unsigned N) const {
634 assert(N == 1 && "Invalid number of operands!");
635 Inst.addOperand(MCOperand::CreateImm(
636 ARM_AM::getSORegOpc(Shift.ShiftTy, 0)));
639 void addRegListOperands(MCInst &Inst, unsigned N) const {
640 assert(N == 1 && "Invalid number of operands!");
641 const SmallVectorImpl<unsigned> &RegList = getRegList();
642 for (SmallVectorImpl<unsigned>::const_iterator
643 I = RegList.begin(), E = RegList.end(); I != E; ++I)
644 Inst.addOperand(MCOperand::CreateReg(*I));
647 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
648 addRegListOperands(Inst, N);
651 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
652 addRegListOperands(Inst, N);
655 void addImmOperands(MCInst &Inst, unsigned N) const {
656 assert(N == 1 && "Invalid number of operands!");
657 addExpr(Inst, getImm());
660 void addImm0_255Operands(MCInst &Inst, unsigned N) const {
661 assert(N == 1 && "Invalid number of operands!");
662 addExpr(Inst, getImm());
665 void addImm0_7Operands(MCInst &Inst, unsigned N) const {
666 assert(N == 1 && "Invalid number of operands!");
667 addExpr(Inst, getImm());
670 void addImm0_15Operands(MCInst &Inst, unsigned N) const {
671 assert(N == 1 && "Invalid number of operands!");
672 addExpr(Inst, getImm());
675 void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
676 assert(N == 1 && "Invalid number of operands!");
677 addExpr(Inst, getImm());
680 void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
681 assert(N == 1 && "Invalid number of operands!");
682 addExpr(Inst, getImm());
685 void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
686 assert(N == 1 && "Invalid number of operands!");
687 addExpr(Inst, getImm());
690 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
691 assert(N == 1 && "Invalid number of operands!");
692 // An ASR value of 32 encodes as 0, so that's how we want to add it to
693 // the instruction as well.
694 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
695 int Val = CE->getValue();
696 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
699 void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
700 assert(N == 1 && "Invalid number of operands!");
701 addExpr(Inst, getImm());
704 void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
705 assert(N == 1 && "Invalid number of operands!");
706 addExpr(Inst, getImm());
709 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
710 assert(N == 1 && "Invalid number of operands!");
711 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
714 void addMemMode7Operands(MCInst &Inst, unsigned N) const {
715 assert(N == 1 && isMemMode7() && "Invalid number of operands!");
716 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
718 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
720 assert((CE || CE->getValue() == 0) &&
721 "No offset operand support in mode 7");
724 void addMemMode2Operands(MCInst &Inst, unsigned N) const {
725 assert(isMemMode2() && "Invalid mode or number of operands!");
726 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
727 unsigned IdxMode = (getMemPreindexed() | getMemPostindexed() << 1);
729 if (getMemOffsetIsReg()) {
730 Inst.addOperand(MCOperand::CreateReg(getMemOffsetRegNum()));
732 ARM_AM::AddrOpc AMOpc = getMemNegative() ? ARM_AM::sub : ARM_AM::add;
733 ARM_AM::ShiftOpc ShOpc = ARM_AM::no_shift;
734 int64_t ShiftAmount = 0;
736 if (getMemOffsetRegShifted()) {
737 ShOpc = getMemShiftType();
738 const MCConstantExpr *CE =
739 dyn_cast<MCConstantExpr>(getMemShiftAmount());
740 ShiftAmount = CE->getValue();
743 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(AMOpc, ShiftAmount,
748 // Create a operand placeholder to always yield the same number of operands.
749 Inst.addOperand(MCOperand::CreateReg(0));
751 // FIXME: #-0 is encoded differently than #0. Does the parser preserve
753 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
754 assert(CE && "Non-constant mode 2 offset operand!");
755 int64_t Offset = CE->getValue();
758 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(ARM_AM::add,
759 Offset, ARM_AM::no_shift, IdxMode)));
761 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(ARM_AM::sub,
762 -Offset, ARM_AM::no_shift, IdxMode)));
765 void addMemMode3Operands(MCInst &Inst, unsigned N) const {
766 assert(isMemMode3() && "Invalid mode or number of operands!");
767 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
768 unsigned IdxMode = (getMemPreindexed() | getMemPostindexed() << 1);
770 if (getMemOffsetIsReg()) {
771 Inst.addOperand(MCOperand::CreateReg(getMemOffsetRegNum()));
773 ARM_AM::AddrOpc AMOpc = getMemNegative() ? ARM_AM::sub : ARM_AM::add;
774 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM3Opc(AMOpc, 0,
779 // Create a operand placeholder to always yield the same number of operands.
780 Inst.addOperand(MCOperand::CreateReg(0));
782 // FIXME: #-0 is encoded differently than #0. Does the parser preserve
784 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
785 assert(CE && "Non-constant mode 3 offset operand!");
786 int64_t Offset = CE->getValue();
789 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM3Opc(ARM_AM::add,
792 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM3Opc(ARM_AM::sub,
796 void addMemMode5Operands(MCInst &Inst, unsigned N) const {
797 assert(N == 2 && isMemMode5() && "Invalid number of operands!");
799 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
800 assert(!getMemOffsetIsReg() && "Invalid mode 5 operand");
802 // FIXME: #-0 is encoded differently than #0. Does the parser preserve
804 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
805 assert(CE && "Non-constant mode 5 offset operand!");
807 // The MCInst offset operand doesn't include the low two bits (like
808 // the instruction encoding).
809 int64_t Offset = CE->getValue() / 4;
811 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add,
814 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub,
818 void addMemModeRegThumbOperands(MCInst &Inst, unsigned N) const {
819 assert(N == 2 && isMemModeRegThumb() && "Invalid number of operands!");
820 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
821 Inst.addOperand(MCOperand::CreateReg(getMemOffsetRegNum()));
824 void addMemModeImmThumbOperands(MCInst &Inst, unsigned N) const {
825 assert(N == 2 && isMemModeImmThumb() && "Invalid number of operands!");
826 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
827 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
828 assert(CE && "Non-constant mode offset operand!");
829 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
832 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
833 assert(N == 1 && "Invalid number of operands!");
834 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
837 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
838 assert(N == 1 && "Invalid number of operands!");
839 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
842 virtual void print(raw_ostream &OS) const;
844 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
845 ARMOperand *Op = new ARMOperand(CondCode);
852 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
853 ARMOperand *Op = new ARMOperand(CoprocNum);
854 Op->Cop.Val = CopVal;
860 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
861 ARMOperand *Op = new ARMOperand(CoprocReg);
862 Op->Cop.Val = CopVal;
868 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
869 ARMOperand *Op = new ARMOperand(CCOut);
870 Op->Reg.RegNum = RegNum;
876 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
877 ARMOperand *Op = new ARMOperand(Token);
878 Op->Tok.Data = Str.data();
879 Op->Tok.Length = Str.size();
885 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
886 ARMOperand *Op = new ARMOperand(Register);
887 Op->Reg.RegNum = RegNum;
893 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
898 ARMOperand *Op = new ARMOperand(ShiftedRegister);
899 Op->ShiftedReg.ShiftTy = ShTy;
900 Op->ShiftedReg.SrcReg = SrcReg;
901 Op->ShiftedReg.ShiftReg = ShiftReg;
902 Op->ShiftedReg.ShiftImm = ShiftImm;
908 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
912 ARMOperand *Op = new ARMOperand(ShiftedImmediate);
913 Op->ShiftedImm.ShiftTy = ShTy;
914 Op->ShiftedImm.SrcReg = SrcReg;
915 Op->ShiftedImm.ShiftImm = ShiftImm;
921 static ARMOperand *CreateShifter(ARM_AM::ShiftOpc ShTy,
923 ARMOperand *Op = new ARMOperand(Shifter);
924 Op->Shift.ShiftTy = ShTy;
931 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
932 SMLoc StartLoc, SMLoc EndLoc) {
933 KindTy Kind = RegisterList;
935 if (ARM::DPRRegClass.contains(Regs.front().first))
936 Kind = DPRRegisterList;
937 else if (ARM::SPRRegClass.contains(Regs.front().first))
938 Kind = SPRRegisterList;
940 ARMOperand *Op = new ARMOperand(Kind);
941 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
942 I = Regs.begin(), E = Regs.end(); I != E; ++I)
943 Op->Registers.push_back(I->first);
944 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
945 Op->StartLoc = StartLoc;
950 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
951 ARMOperand *Op = new ARMOperand(Immediate);
958 static ARMOperand *CreateMem(ARMII::AddrMode AddrMode, unsigned BaseRegNum,
959 bool OffsetIsReg, const MCExpr *Offset,
960 int OffsetRegNum, bool OffsetRegShifted,
961 enum ARM_AM::ShiftOpc ShiftType,
962 const MCExpr *ShiftAmount, bool Preindexed,
963 bool Postindexed, bool Negative, bool Writeback,
965 assert((OffsetRegNum == -1 || OffsetIsReg) &&
966 "OffsetRegNum must imply OffsetIsReg!");
967 assert((!OffsetRegShifted || OffsetIsReg) &&
968 "OffsetRegShifted must imply OffsetIsReg!");
969 assert((Offset || OffsetIsReg) &&
970 "Offset must exists unless register offset is used!");
971 assert((!ShiftAmount || (OffsetIsReg && OffsetRegShifted)) &&
972 "Cannot have shift amount without shifted register offset!");
973 assert((!Offset || !OffsetIsReg) &&
974 "Cannot have expression offset and register offset!");
976 ARMOperand *Op = new ARMOperand(Memory);
977 Op->Mem.AddrMode = AddrMode;
978 Op->Mem.BaseRegNum = BaseRegNum;
979 Op->Mem.OffsetIsReg = OffsetIsReg;
981 Op->Mem.Offset.RegNum = OffsetRegNum;
983 Op->Mem.Offset.Value = Offset;
984 Op->Mem.OffsetRegShifted = OffsetRegShifted;
985 Op->Mem.ShiftType = ShiftType;
986 Op->Mem.ShiftAmount = ShiftAmount;
987 Op->Mem.Preindexed = Preindexed;
988 Op->Mem.Postindexed = Postindexed;
989 Op->Mem.Negative = Negative;
990 Op->Mem.Writeback = Writeback;
997 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
998 ARMOperand *Op = new ARMOperand(MemBarrierOpt);
1005 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1006 ARMOperand *Op = new ARMOperand(ProcIFlags);
1007 Op->IFlags.Val = IFlags;
1013 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1014 ARMOperand *Op = new ARMOperand(MSRMask);
1015 Op->MMask.Val = MMask;
1022 } // end anonymous namespace.
1024 void ARMOperand::print(raw_ostream &OS) const {
1027 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1030 OS << "<ccout " << getReg() << ">";
1033 OS << "<coprocessor number: " << getCoproc() << ">";
1036 OS << "<coprocessor register: " << getCoproc() << ">";
1039 OS << "<mask: " << getMSRMask() << ">";
1042 getImm()->print(OS);
1045 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1049 << "am:" << ARMII::AddrModeToString(getMemAddrMode())
1050 << " base:" << getMemBaseRegNum();
1051 if (getMemOffsetIsReg()) {
1052 OS << " offset:<register " << getMemOffsetRegNum();
1053 if (getMemOffsetRegShifted()) {
1054 OS << " offset-shift-type:" << getMemShiftType();
1055 OS << " offset-shift-amount:" << *getMemShiftAmount();
1058 OS << " offset:" << *getMemOffset();
1060 if (getMemOffsetIsReg())
1061 OS << " (offset-is-reg)";
1062 if (getMemPreindexed())
1063 OS << " (pre-indexed)";
1064 if (getMemPostindexed())
1065 OS << " (post-indexed)";
1066 if (getMemNegative())
1067 OS << " (negative)";
1068 if (getMemWriteback())
1069 OS << " (writeback)";
1073 OS << "<ARM_PROC::";
1074 unsigned IFlags = getProcIFlags();
1075 for (int i=2; i >= 0; --i)
1076 if (IFlags & (1 << i))
1077 OS << ARM_PROC::IFlagsToString(1 << i);
1082 OS << "<register " << getReg() << ">";
1085 OS << "<shifter " << ARM_AM::getShiftOpcStr(Shift.ShiftTy) << ">";
1087 case ShiftedRegister:
1088 OS << "<so_reg_reg "
1089 << ShiftedReg.SrcReg
1090 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(ShiftedReg.ShiftImm))
1091 << ", " << ShiftedReg.ShiftReg << ", "
1092 << ARM_AM::getSORegOffset(ShiftedReg.ShiftImm)
1095 case ShiftedImmediate:
1096 OS << "<so_reg_imm "
1097 << ShiftedImm.SrcReg
1098 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(ShiftedImm.ShiftImm))
1099 << ", " << ARM_AM::getSORegOffset(ShiftedImm.ShiftImm)
1103 case DPRRegisterList:
1104 case SPRRegisterList: {
1105 OS << "<register_list ";
1107 const SmallVectorImpl<unsigned> &RegList = getRegList();
1108 for (SmallVectorImpl<unsigned>::const_iterator
1109 I = RegList.begin(), E = RegList.end(); I != E; ) {
1111 if (++I < E) OS << ", ";
1118 OS << "'" << getToken() << "'";
1123 /// @name Auto-generated Match Functions
1126 static unsigned MatchRegisterName(StringRef Name);
1130 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
1131 SMLoc &StartLoc, SMLoc &EndLoc) {
1132 RegNo = TryParseRegister();
1134 return (RegNo == (unsigned)-1);
1137 /// Try to parse a register name. The token must be an Identifier when called,
1138 /// and if it is a register name the token is eaten and the register number is
1139 /// returned. Otherwise return -1.
1141 int ARMAsmParser::TryParseRegister() {
1142 const AsmToken &Tok = Parser.getTok();
1143 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1145 // FIXME: Validate register for the current architecture; we have to do
1146 // validation later, so maybe there is no need for this here.
1147 std::string upperCase = Tok.getString().str();
1148 std::string lowerCase = LowercaseString(upperCase);
1149 unsigned RegNum = MatchRegisterName(lowerCase);
1151 RegNum = StringSwitch<unsigned>(lowerCase)
1152 .Case("r13", ARM::SP)
1153 .Case("r14", ARM::LR)
1154 .Case("r15", ARM::PC)
1155 .Case("ip", ARM::R12)
1158 if (!RegNum) return -1;
1160 Parser.Lex(); // Eat identifier token.
1164 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
1165 // If a recoverable error occurs, return 1. If an irrecoverable error
1166 // occurs, return -1. An irrecoverable error is one where tokens have been
1167 // consumed in the process of trying to parse the shifter (i.e., when it is
1168 // indeed a shifter operand, but malformed).
1169 int ARMAsmParser::TryParseShiftRegister(
1170 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1171 SMLoc S = Parser.getTok().getLoc();
1172 const AsmToken &Tok = Parser.getTok();
1173 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1175 std::string upperCase = Tok.getString().str();
1176 std::string lowerCase = LowercaseString(upperCase);
1177 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
1178 .Case("lsl", ARM_AM::lsl)
1179 .Case("lsr", ARM_AM::lsr)
1180 .Case("asr", ARM_AM::asr)
1181 .Case("ror", ARM_AM::ror)
1182 .Case("rrx", ARM_AM::rrx)
1183 .Default(ARM_AM::no_shift);
1185 if (ShiftTy == ARM_AM::no_shift)
1188 Parser.Lex(); // Eat the operator.
1190 // The source register for the shift has already been added to the
1191 // operand list, so we need to pop it off and combine it into the shifted
1192 // register operand instead.
1193 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
1194 if (!PrevOp->isReg())
1195 return Error(PrevOp->getStartLoc(), "shift must be of a register");
1196 int SrcReg = PrevOp->getReg();
1199 if (ShiftTy == ARM_AM::rrx) {
1200 // RRX Doesn't have an explicit shift amount. The encoder expects
1201 // the shift register to be the same as the source register. Seems odd,
1205 // Figure out if this is shifted by a constant or a register (for non-RRX).
1206 if (Parser.getTok().is(AsmToken::Hash)) {
1207 Parser.Lex(); // Eat hash.
1208 SMLoc ImmLoc = Parser.getTok().getLoc();
1209 const MCExpr *ShiftExpr = 0;
1210 if (getParser().ParseExpression(ShiftExpr)) {
1211 Error(ImmLoc, "invalid immediate shift value");
1214 // The expression must be evaluatable as an immediate.
1215 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
1217 Error(ImmLoc, "invalid immediate shift value");
1220 // Range check the immediate.
1221 // lsl, ror: 0 <= imm <= 31
1222 // lsr, asr: 0 <= imm <= 32
1223 Imm = CE->getValue();
1225 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
1226 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
1227 Error(ImmLoc, "immediate shift value out of range");
1230 } else if (Parser.getTok().is(AsmToken::Identifier)) {
1231 ShiftReg = TryParseRegister();
1232 SMLoc L = Parser.getTok().getLoc();
1233 if (ShiftReg == -1) {
1234 Error (L, "expected immediate or register in shift operand");
1238 Error (Parser.getTok().getLoc(),
1239 "expected immediate or register in shift operand");
1244 if (ShiftReg && ShiftTy != ARM_AM::rrx)
1245 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
1247 S, Parser.getTok().getLoc()));
1249 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
1250 S, Parser.getTok().getLoc()));
1256 /// Try to parse a register name. The token must be an Identifier when called.
1257 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
1258 /// if there is a "writeback". 'true' if it's not a register.
1260 /// TODO this is likely to change to allow different register types and or to
1261 /// parse for a specific register type.
1263 TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1264 SMLoc S = Parser.getTok().getLoc();
1265 int RegNo = TryParseRegister();
1269 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1271 const AsmToken &ExclaimTok = Parser.getTok();
1272 if (ExclaimTok.is(AsmToken::Exclaim)) {
1273 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
1274 ExclaimTok.getLoc()));
1275 Parser.Lex(); // Eat exclaim token
1281 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
1282 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
1284 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
1285 // Use the same layout as the tablegen'erated register name matcher. Ugly,
1287 switch (Name.size()) {
1290 if (Name[0] != CoprocOp)
1307 if (Name[0] != CoprocOp || Name[1] != '1')
1311 case '0': return 10;
1312 case '1': return 11;
1313 case '2': return 12;
1314 case '3': return 13;
1315 case '4': return 14;
1316 case '5': return 15;
1324 /// tryParseCoprocNumOperand - Try to parse an coprocessor number operand. The
1325 /// token must be an Identifier when called, and if it is a coprocessor
1326 /// number, the token is eaten and the operand is added to the operand list.
1327 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1328 tryParseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1329 SMLoc S = Parser.getTok().getLoc();
1330 const AsmToken &Tok = Parser.getTok();
1331 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1333 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
1335 return MatchOperand_NoMatch;
1337 Parser.Lex(); // Eat identifier token.
1338 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
1339 return MatchOperand_Success;
1342 /// tryParseCoprocRegOperand - Try to parse an coprocessor register operand. The
1343 /// token must be an Identifier when called, and if it is a coprocessor
1344 /// number, the token is eaten and the operand is added to the operand list.
1345 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1346 tryParseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1347 SMLoc S = Parser.getTok().getLoc();
1348 const AsmToken &Tok = Parser.getTok();
1349 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1351 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
1353 return MatchOperand_NoMatch;
1355 Parser.Lex(); // Eat identifier token.
1356 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
1357 return MatchOperand_Success;
1360 /// Parse a register list, return it if successful else return null. The first
1361 /// token must be a '{' when called.
1363 ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1364 assert(Parser.getTok().is(AsmToken::LCurly) &&
1365 "Token is not a Left Curly Brace");
1366 SMLoc S = Parser.getTok().getLoc();
1368 // Read the rest of the registers in the list.
1369 unsigned PrevRegNum = 0;
1370 SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
1373 bool IsRange = Parser.getTok().is(AsmToken::Minus);
1374 Parser.Lex(); // Eat non-identifier token.
1376 const AsmToken &RegTok = Parser.getTok();
1377 SMLoc RegLoc = RegTok.getLoc();
1378 if (RegTok.isNot(AsmToken::Identifier)) {
1379 Error(RegLoc, "register expected");
1383 int RegNum = TryParseRegister();
1385 Error(RegLoc, "register expected");
1390 int Reg = PrevRegNum;
1393 Registers.push_back(std::make_pair(Reg, RegLoc));
1394 } while (Reg != RegNum);
1396 Registers.push_back(std::make_pair(RegNum, RegLoc));
1399 PrevRegNum = RegNum;
1400 } while (Parser.getTok().is(AsmToken::Comma) ||
1401 Parser.getTok().is(AsmToken::Minus));
1403 // Process the right curly brace of the list.
1404 const AsmToken &RCurlyTok = Parser.getTok();
1405 if (RCurlyTok.isNot(AsmToken::RCurly)) {
1406 Error(RCurlyTok.getLoc(), "'}' expected");
1410 SMLoc E = RCurlyTok.getLoc();
1411 Parser.Lex(); // Eat right curly brace token.
1413 // Verify the register list.
1414 SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1415 RI = Registers.begin(), RE = Registers.end();
1417 unsigned HighRegNum = getARMRegisterNumbering(RI->first);
1418 bool EmittedWarning = false;
1420 DenseMap<unsigned, bool> RegMap;
1421 RegMap[HighRegNum] = true;
1423 for (++RI; RI != RE; ++RI) {
1424 const std::pair<unsigned, SMLoc> &RegInfo = *RI;
1425 unsigned Reg = getARMRegisterNumbering(RegInfo.first);
1428 Error(RegInfo.second, "register duplicated in register list");
1432 if (!EmittedWarning && Reg < HighRegNum)
1433 Warning(RegInfo.second,
1434 "register not in ascending order in register list");
1437 HighRegNum = std::max(Reg, HighRegNum);
1440 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
1444 /// tryParseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
1445 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1446 tryParseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1447 SMLoc S = Parser.getTok().getLoc();
1448 const AsmToken &Tok = Parser.getTok();
1449 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1450 StringRef OptStr = Tok.getString();
1452 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
1453 .Case("sy", ARM_MB::SY)
1454 .Case("st", ARM_MB::ST)
1455 .Case("sh", ARM_MB::ISH)
1456 .Case("ish", ARM_MB::ISH)
1457 .Case("shst", ARM_MB::ISHST)
1458 .Case("ishst", ARM_MB::ISHST)
1459 .Case("nsh", ARM_MB::NSH)
1460 .Case("un", ARM_MB::NSH)
1461 .Case("nshst", ARM_MB::NSHST)
1462 .Case("unst", ARM_MB::NSHST)
1463 .Case("osh", ARM_MB::OSH)
1464 .Case("oshst", ARM_MB::OSHST)
1468 return MatchOperand_NoMatch;
1470 Parser.Lex(); // Eat identifier token.
1471 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
1472 return MatchOperand_Success;
1475 /// tryParseProcIFlagsOperand - Try to parse iflags from CPS instruction.
1476 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1477 tryParseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1478 SMLoc S = Parser.getTok().getLoc();
1479 const AsmToken &Tok = Parser.getTok();
1480 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1481 StringRef IFlagsStr = Tok.getString();
1483 unsigned IFlags = 0;
1484 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
1485 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
1486 .Case("a", ARM_PROC::A)
1487 .Case("i", ARM_PROC::I)
1488 .Case("f", ARM_PROC::F)
1491 // If some specific iflag is already set, it means that some letter is
1492 // present more than once, this is not acceptable.
1493 if (Flag == ~0U || (IFlags & Flag))
1494 return MatchOperand_NoMatch;
1499 Parser.Lex(); // Eat identifier token.
1500 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
1501 return MatchOperand_Success;
1504 /// tryParseMSRMaskOperand - Try to parse mask flags from MSR instruction.
1505 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1506 tryParseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1507 SMLoc S = Parser.getTok().getLoc();
1508 const AsmToken &Tok = Parser.getTok();
1509 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1510 StringRef Mask = Tok.getString();
1512 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
1513 size_t Start = 0, Next = Mask.find('_');
1514 StringRef Flags = "";
1515 std::string SpecReg = LowercaseString(Mask.slice(Start, Next));
1516 if (Next != StringRef::npos)
1517 Flags = Mask.slice(Next+1, Mask.size());
1519 // FlagsVal contains the complete mask:
1521 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1522 unsigned FlagsVal = 0;
1524 if (SpecReg == "apsr") {
1525 FlagsVal = StringSwitch<unsigned>(Flags)
1526 .Case("nzcvq", 0x8) // same as CPSR_f
1527 .Case("g", 0x4) // same as CPSR_s
1528 .Case("nzcvqg", 0xc) // same as CPSR_fs
1531 if (FlagsVal == ~0U) {
1533 return MatchOperand_NoMatch;
1535 FlagsVal = 0; // No flag
1537 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
1538 if (Flags == "all") // cpsr_all is an alias for cpsr_fc
1540 for (int i = 0, e = Flags.size(); i != e; ++i) {
1541 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
1548 // If some specific flag is already set, it means that some letter is
1549 // present more than once, this is not acceptable.
1550 if (FlagsVal == ~0U || (FlagsVal & Flag))
1551 return MatchOperand_NoMatch;
1554 } else // No match for special register.
1555 return MatchOperand_NoMatch;
1557 // Special register without flags are equivalent to "fc" flags.
1561 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1562 if (SpecReg == "spsr")
1565 Parser.Lex(); // Eat identifier token.
1566 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
1567 return MatchOperand_Success;
1570 /// tryParseMemMode2Operand - Try to parse memory addressing mode 2 operand.
1571 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1572 tryParseMemMode2Operand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1573 assert(Parser.getTok().is(AsmToken::LBrac) && "Token is not a \"[\"");
1575 if (ParseMemory(Operands, ARMII::AddrMode2))
1576 return MatchOperand_NoMatch;
1578 return MatchOperand_Success;
1581 /// tryParseMemMode3Operand - Try to parse memory addressing mode 3 operand.
1582 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1583 tryParseMemMode3Operand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1584 assert(Parser.getTok().is(AsmToken::LBrac) && "Token is not a \"[\"");
1586 if (ParseMemory(Operands, ARMII::AddrMode3))
1587 return MatchOperand_NoMatch;
1589 return MatchOperand_Success;
1592 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1593 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
1594 int Low, int High) {
1595 const AsmToken &Tok = Parser.getTok();
1596 if (Tok.isNot(AsmToken::Identifier)) {
1597 Error(Parser.getTok().getLoc(), Op + " operand expected.");
1598 return MatchOperand_ParseFail;
1600 StringRef ShiftName = Tok.getString();
1601 std::string LowerOp = LowercaseString(Op);
1602 std::string UpperOp = UppercaseString(Op);
1603 if (ShiftName != LowerOp && ShiftName != UpperOp) {
1604 Error(Parser.getTok().getLoc(), Op + " operand expected.");
1605 return MatchOperand_ParseFail;
1607 Parser.Lex(); // Eat shift type token.
1609 // There must be a '#' and a shift amount.
1610 if (Parser.getTok().isNot(AsmToken::Hash)) {
1611 Error(Parser.getTok().getLoc(), "'#' expected");
1612 return MatchOperand_ParseFail;
1614 Parser.Lex(); // Eat hash token.
1616 const MCExpr *ShiftAmount;
1617 SMLoc Loc = Parser.getTok().getLoc();
1618 if (getParser().ParseExpression(ShiftAmount)) {
1619 Error(Loc, "illegal expression");
1620 return MatchOperand_ParseFail;
1622 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1624 Error(Loc, "constant expression expected");
1625 return MatchOperand_ParseFail;
1627 int Val = CE->getValue();
1628 if (Val < Low || Val > High) {
1629 Error(Loc, "immediate value out of range");
1630 return MatchOperand_ParseFail;
1633 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
1635 return MatchOperand_Success;
1638 /// CvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
1639 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
1640 /// when they refer multiple MIOperands inside a single one.
1642 CvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
1643 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1644 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
1646 // Create a writeback register dummy placeholder.
1647 Inst.addOperand(MCOperand::CreateImm(0));
1649 ((ARMOperand*)Operands[3])->addMemMode2Operands(Inst, 3);
1650 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
1654 /// CvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
1655 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
1656 /// when they refer multiple MIOperands inside a single one.
1658 CvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
1659 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1660 // Create a writeback register dummy placeholder.
1661 Inst.addOperand(MCOperand::CreateImm(0));
1662 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
1663 ((ARMOperand*)Operands[3])->addMemMode2Operands(Inst, 3);
1664 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
1668 /// CvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
1669 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
1670 /// when they refer multiple MIOperands inside a single one.
1672 CvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
1673 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1674 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
1676 // Create a writeback register dummy placeholder.
1677 Inst.addOperand(MCOperand::CreateImm(0));
1679 ((ARMOperand*)Operands[3])->addMemMode3Operands(Inst, 3);
1680 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
1684 /// CvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
1685 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
1686 /// when they refer multiple MIOperands inside a single one.
1688 CvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
1689 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1690 // Create a writeback register dummy placeholder.
1691 Inst.addOperand(MCOperand::CreateImm(0));
1692 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
1693 ((ARMOperand*)Operands[3])->addMemMode3Operands(Inst, 3);
1694 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
1698 /// Parse an ARM memory expression, return false if successful else return true
1699 /// or an error. The first token must be a '[' when called.
1701 /// TODO Only preindexing and postindexing addressing are started, unindexed
1702 /// with option, etc are still to do.
1704 ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1705 ARMII::AddrMode AddrMode = ARMII::AddrModeNone) {
1707 assert(Parser.getTok().is(AsmToken::LBrac) &&
1708 "Token is not a Left Bracket");
1709 S = Parser.getTok().getLoc();
1710 Parser.Lex(); // Eat left bracket token.
1712 const AsmToken &BaseRegTok = Parser.getTok();
1713 if (BaseRegTok.isNot(AsmToken::Identifier)) {
1714 Error(BaseRegTok.getLoc(), "register expected");
1717 int BaseRegNum = TryParseRegister();
1718 if (BaseRegNum == -1) {
1719 Error(BaseRegTok.getLoc(), "register expected");
1723 // The next token must either be a comma or a closing bracket.
1724 const AsmToken &Tok = Parser.getTok();
1725 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
1728 bool Preindexed = false;
1729 bool Postindexed = false;
1730 bool OffsetIsReg = false;
1731 bool Negative = false;
1732 bool Writeback = false;
1733 ARMOperand *WBOp = 0;
1734 int OffsetRegNum = -1;
1735 bool OffsetRegShifted = false;
1736 enum ARM_AM::ShiftOpc ShiftType = ARM_AM::lsl;
1737 const MCExpr *ShiftAmount = 0;
1738 const MCExpr *Offset = 0;
1740 // First look for preindexed address forms, that is after the "[Rn" we now
1741 // have to see if the next token is a comma.
1742 if (Tok.is(AsmToken::Comma)) {
1744 Parser.Lex(); // Eat comma token.
1746 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
1747 Offset, OffsetIsReg, OffsetRegNum, E))
1749 const AsmToken &RBracTok = Parser.getTok();
1750 if (RBracTok.isNot(AsmToken::RBrac)) {
1751 Error(RBracTok.getLoc(), "']' expected");
1754 E = RBracTok.getLoc();
1755 Parser.Lex(); // Eat right bracket token.
1757 const AsmToken &ExclaimTok = Parser.getTok();
1758 if (ExclaimTok.is(AsmToken::Exclaim)) {
1759 // None of addrmode3 instruction uses "!"
1760 if (AddrMode == ARMII::AddrMode3)
1763 WBOp = ARMOperand::CreateToken(ExclaimTok.getString(),
1764 ExclaimTok.getLoc());
1766 Parser.Lex(); // Eat exclaim token
1767 } else { // In addressing mode 2, pre-indexed mode always end with "!"
1768 if (AddrMode == ARMII::AddrMode2)
1772 // The "[Rn" we have so far was not followed by a comma.
1774 // If there's anything other than the right brace, this is a post indexing
1777 Parser.Lex(); // Eat right bracket token.
1779 const AsmToken &NextTok = Parser.getTok();
1781 if (NextTok.isNot(AsmToken::EndOfStatement)) {
1785 if (NextTok.isNot(AsmToken::Comma)) {
1786 Error(NextTok.getLoc(), "',' expected");
1790 Parser.Lex(); // Eat comma token.
1792 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
1793 ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
1799 // Force Offset to exist if used.
1802 Offset = MCConstantExpr::Create(0, getContext());
1804 if (AddrMode == ARMII::AddrMode3 && OffsetRegShifted) {
1805 Error(E, "shift amount not supported");
1810 Operands.push_back(ARMOperand::CreateMem(AddrMode, BaseRegNum, OffsetIsReg,
1811 Offset, OffsetRegNum, OffsetRegShifted,
1812 ShiftType, ShiftAmount, Preindexed,
1813 Postindexed, Negative, Writeback, S, E));
1815 Operands.push_back(WBOp);
1820 /// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
1821 /// we will parse the following (were +/- means that a plus or minus is
1826 /// we return false on success or an error otherwise.
1827 bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
1828 bool &OffsetRegShifted,
1829 enum ARM_AM::ShiftOpc &ShiftType,
1830 const MCExpr *&ShiftAmount,
1831 const MCExpr *&Offset,
1836 OffsetRegShifted = false;
1837 OffsetIsReg = false;
1839 const AsmToken &NextTok = Parser.getTok();
1840 E = NextTok.getLoc();
1841 if (NextTok.is(AsmToken::Plus))
1842 Parser.Lex(); // Eat plus token.
1843 else if (NextTok.is(AsmToken::Minus)) {
1845 Parser.Lex(); // Eat minus token
1847 // See if there is a register following the "[Rn," or "[Rn]," we have so far.
1848 const AsmToken &OffsetRegTok = Parser.getTok();
1849 if (OffsetRegTok.is(AsmToken::Identifier)) {
1850 SMLoc CurLoc = OffsetRegTok.getLoc();
1851 OffsetRegNum = TryParseRegister();
1852 if (OffsetRegNum != -1) {
1858 // If we parsed a register as the offset then there can be a shift after that.
1859 if (OffsetRegNum != -1) {
1860 // Look for a comma then a shift
1861 const AsmToken &Tok = Parser.getTok();
1862 if (Tok.is(AsmToken::Comma)) {
1863 Parser.Lex(); // Eat comma token.
1865 const AsmToken &Tok = Parser.getTok();
1866 if (ParseShift(ShiftType, ShiftAmount, E))
1867 return Error(Tok.getLoc(), "shift expected");
1868 OffsetRegShifted = true;
1871 else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
1872 // Look for #offset following the "[Rn," or "[Rn],"
1873 const AsmToken &HashTok = Parser.getTok();
1874 if (HashTok.isNot(AsmToken::Hash))
1875 return Error(HashTok.getLoc(), "'#' expected");
1877 Parser.Lex(); // Eat hash token.
1879 if (getParser().ParseExpression(Offset))
1881 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1886 /// ParseShift as one of these two:
1887 /// ( lsl | lsr | asr | ror ) , # shift_amount
1889 /// and returns true if it parses a shift otherwise it returns false.
1890 bool ARMAsmParser::ParseShift(ARM_AM::ShiftOpc &St,
1891 const MCExpr *&ShiftAmount, SMLoc &E) {
1892 const AsmToken &Tok = Parser.getTok();
1893 if (Tok.isNot(AsmToken::Identifier))
1895 StringRef ShiftName = Tok.getString();
1896 if (ShiftName == "lsl" || ShiftName == "LSL")
1898 else if (ShiftName == "lsr" || ShiftName == "LSR")
1900 else if (ShiftName == "asr" || ShiftName == "ASR")
1902 else if (ShiftName == "ror" || ShiftName == "ROR")
1904 else if (ShiftName == "rrx" || ShiftName == "RRX")
1908 Parser.Lex(); // Eat shift type token.
1910 // Rrx stands alone.
1911 if (St == ARM_AM::rrx)
1914 // Otherwise, there must be a '#' and a shift amount.
1915 const AsmToken &HashTok = Parser.getTok();
1916 if (HashTok.isNot(AsmToken::Hash))
1917 return Error(HashTok.getLoc(), "'#' expected");
1918 Parser.Lex(); // Eat hash token.
1920 if (getParser().ParseExpression(ShiftAmount))
1926 /// Parse a arm instruction operand. For now this parses the operand regardless
1927 /// of the mnemonic.
1928 bool ARMAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1929 StringRef Mnemonic) {
1932 // Check if the current operand has a custom associated parser, if so, try to
1933 // custom parse the operand, or fallback to the general approach.
1934 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1935 if (ResTy == MatchOperand_Success)
1937 // If there wasn't a custom match, try the generic matcher below. Otherwise,
1938 // there was a match, but an error occurred, in which case, just return that
1939 // the operand parsing failed.
1940 if (ResTy == MatchOperand_ParseFail)
1943 switch (getLexer().getKind()) {
1945 Error(Parser.getTok().getLoc(), "unexpected token in operand");
1947 case AsmToken::Identifier: {
1948 if (!TryParseRegisterWithWriteBack(Operands))
1950 int Res = TryParseShiftRegister(Operands);
1951 if (Res == 0) // success
1953 else if (Res == -1) // irrecoverable error
1956 // Fall though for the Identifier case that is not a register or a
1959 case AsmToken::Integer: // things like 1f and 2b as a branch targets
1960 case AsmToken::Dot: { // . as a branch target
1961 // This was not a register so parse other operands that start with an
1962 // identifier (like labels) as expressions and create them as immediates.
1963 const MCExpr *IdVal;
1964 S = Parser.getTok().getLoc();
1965 if (getParser().ParseExpression(IdVal))
1967 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1968 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
1971 case AsmToken::LBrac:
1972 return ParseMemory(Operands);
1973 case AsmToken::LCurly:
1974 return ParseRegisterList(Operands);
1975 case AsmToken::Hash:
1976 // #42 -> immediate.
1977 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
1978 S = Parser.getTok().getLoc();
1980 const MCExpr *ImmVal;
1981 if (getParser().ParseExpression(ImmVal))
1983 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1984 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
1986 case AsmToken::Colon: {
1987 // ":lower16:" and ":upper16:" expression prefixes
1988 // FIXME: Check it's an expression prefix,
1989 // e.g. (FOO - :lower16:BAR) isn't legal.
1990 ARMMCExpr::VariantKind RefKind;
1991 if (ParsePrefix(RefKind))
1994 const MCExpr *SubExprVal;
1995 if (getParser().ParseExpression(SubExprVal))
1998 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
2000 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2001 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
2007 // ParsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
2008 // :lower16: and :upper16:.
2009 bool ARMAsmParser::ParsePrefix(ARMMCExpr::VariantKind &RefKind) {
2010 RefKind = ARMMCExpr::VK_ARM_None;
2012 // :lower16: and :upper16: modifiers
2013 assert(getLexer().is(AsmToken::Colon) && "expected a :");
2014 Parser.Lex(); // Eat ':'
2016 if (getLexer().isNot(AsmToken::Identifier)) {
2017 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
2021 StringRef IDVal = Parser.getTok().getIdentifier();
2022 if (IDVal == "lower16") {
2023 RefKind = ARMMCExpr::VK_ARM_LO16;
2024 } else if (IDVal == "upper16") {
2025 RefKind = ARMMCExpr::VK_ARM_HI16;
2027 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
2032 if (getLexer().isNot(AsmToken::Colon)) {
2033 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
2036 Parser.Lex(); // Eat the last ':'
2041 ARMAsmParser::ApplyPrefixToExpr(const MCExpr *E,
2042 MCSymbolRefExpr::VariantKind Variant) {
2043 // Recurse over the given expression, rebuilding it to apply the given variant
2044 // to the leftmost symbol.
2045 if (Variant == MCSymbolRefExpr::VK_None)
2048 switch (E->getKind()) {
2049 case MCExpr::Target:
2050 llvm_unreachable("Can't handle target expr yet");
2051 case MCExpr::Constant:
2052 llvm_unreachable("Can't handle lower16/upper16 of constant yet");
2054 case MCExpr::SymbolRef: {
2055 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
2057 if (SRE->getKind() != MCSymbolRefExpr::VK_None)
2060 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext());
2064 llvm_unreachable("Can't handle unary expressions yet");
2066 case MCExpr::Binary: {
2067 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
2068 const MCExpr *LHS = ApplyPrefixToExpr(BE->getLHS(), Variant);
2069 const MCExpr *RHS = BE->getRHS();
2073 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext());
2077 assert(0 && "Invalid expression kind!");
2081 /// \brief Given a mnemonic, split out possible predication code and carry
2082 /// setting letters to form a canonical mnemonic and flags.
2084 // FIXME: Would be nice to autogen this.
2085 StringRef ARMAsmParser::SplitMnemonic(StringRef Mnemonic,
2086 unsigned &PredicationCode,
2088 unsigned &ProcessorIMod) {
2089 PredicationCode = ARMCC::AL;
2090 CarrySetting = false;
2093 // Ignore some mnemonics we know aren't predicated forms.
2095 // FIXME: Would be nice to autogen this.
2096 if ((Mnemonic == "movs" && isThumb()) ||
2097 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
2098 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
2099 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
2100 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
2101 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
2102 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
2103 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
2106 // First, split out any predication code. Ignore mnemonics we know aren't
2107 // predicated but do have a carry-set and so weren't caught above.
2108 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
2109 Mnemonic != "muls") {
2110 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
2111 .Case("eq", ARMCC::EQ)
2112 .Case("ne", ARMCC::NE)
2113 .Case("hs", ARMCC::HS)
2114 .Case("cs", ARMCC::HS)
2115 .Case("lo", ARMCC::LO)
2116 .Case("cc", ARMCC::LO)
2117 .Case("mi", ARMCC::MI)
2118 .Case("pl", ARMCC::PL)
2119 .Case("vs", ARMCC::VS)
2120 .Case("vc", ARMCC::VC)
2121 .Case("hi", ARMCC::HI)
2122 .Case("ls", ARMCC::LS)
2123 .Case("ge", ARMCC::GE)
2124 .Case("lt", ARMCC::LT)
2125 .Case("gt", ARMCC::GT)
2126 .Case("le", ARMCC::LE)
2127 .Case("al", ARMCC::AL)
2130 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
2131 PredicationCode = CC;
2135 // Next, determine if we have a carry setting bit. We explicitly ignore all
2136 // the instructions we know end in 's'.
2137 if (Mnemonic.endswith("s") &&
2138 !(Mnemonic == "asrs" || Mnemonic == "cps" || Mnemonic == "mls" ||
2139 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
2140 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
2141 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
2142 Mnemonic == "vrsqrts" || (Mnemonic == "movs" && isThumb()))) {
2143 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
2144 CarrySetting = true;
2147 // The "cps" instruction can have a interrupt mode operand which is glued into
2148 // the mnemonic. Check if this is the case, split it and parse the imod op
2149 if (Mnemonic.startswith("cps")) {
2150 // Split out any imod code.
2152 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
2153 .Case("ie", ARM_PROC::IE)
2154 .Case("id", ARM_PROC::ID)
2157 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
2158 ProcessorIMod = IMod;
2165 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
2166 /// inclusion of carry set or predication code operands.
2168 // FIXME: It would be nice to autogen this.
2170 GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
2171 bool &CanAcceptPredicationCode) {
2172 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
2173 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
2174 Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
2175 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
2176 Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" ||
2177 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
2178 Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
2179 Mnemonic == "eor" || Mnemonic == "smlal" ||
2180 (Mnemonic == "mov" && !isThumbOne())) {
2181 CanAcceptCarrySet = true;
2183 CanAcceptCarrySet = false;
2186 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
2187 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
2188 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
2189 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
2190 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "clrex" ||
2191 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumb())) {
2192 CanAcceptPredicationCode = false;
2194 CanAcceptPredicationCode = true;
2198 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
2199 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
2200 CanAcceptPredicationCode = false;
2203 /// Parse an arm instruction mnemonic followed by its operands.
2204 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
2205 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2206 // Create the leading tokens for the mnemonic, split by '.' characters.
2207 size_t Start = 0, Next = Name.find('.');
2208 StringRef Mnemonic = Name.slice(Start, Next);
2210 // Split out the predication code and carry setting flag from the mnemonic.
2211 unsigned PredicationCode;
2212 unsigned ProcessorIMod;
2214 Mnemonic = SplitMnemonic(Mnemonic, PredicationCode, CarrySetting,
2217 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
2219 // FIXME: This is all a pretty gross hack. We should automatically handle
2220 // optional operands like this via tblgen.
2222 // Next, add the CCOut and ConditionCode operands, if needed.
2224 // For mnemonics which can ever incorporate a carry setting bit or predication
2225 // code, our matching model involves us always generating CCOut and
2226 // ConditionCode operands to match the mnemonic "as written" and then we let
2227 // the matcher deal with finding the right instruction or generating an
2228 // appropriate error.
2229 bool CanAcceptCarrySet, CanAcceptPredicationCode;
2230 GetMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
2232 // If we had a carry-set on an instruction that can't do that, issue an
2234 if (!CanAcceptCarrySet && CarrySetting) {
2235 Parser.EatToEndOfStatement();
2236 return Error(NameLoc, "instruction '" + Mnemonic +
2237 "' can not set flags, but 's' suffix specified");
2240 // Add the carry setting operand, if necessary.
2242 // FIXME: It would be awesome if we could somehow invent a location such that
2243 // match errors on this operand would print a nice diagnostic about how the
2244 // 's' character in the mnemonic resulted in a CCOut operand.
2245 if (CanAcceptCarrySet)
2246 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
2249 // Add the predication code operand, if necessary.
2250 if (CanAcceptPredicationCode) {
2251 Operands.push_back(ARMOperand::CreateCondCode(
2252 ARMCC::CondCodes(PredicationCode), NameLoc));
2254 // This mnemonic can't ever accept a predication code, but the user wrote
2255 // one (or misspelled another mnemonic).
2257 // FIXME: Issue a nice error.
2260 // Add the processor imod operand, if necessary.
2261 if (ProcessorIMod) {
2262 Operands.push_back(ARMOperand::CreateImm(
2263 MCConstantExpr::Create(ProcessorIMod, getContext()),
2266 // This mnemonic can't ever accept a imod, but the user wrote
2267 // one (or misspelled another mnemonic).
2269 // FIXME: Issue a nice error.
2272 // Add the remaining tokens in the mnemonic.
2273 while (Next != StringRef::npos) {
2275 Next = Name.find('.', Start + 1);
2276 StringRef ExtraToken = Name.slice(Start, Next);
2278 Operands.push_back(ARMOperand::CreateToken(ExtraToken, NameLoc));
2281 // Read the remaining operands.
2282 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2283 // Read the first operand.
2284 if (ParseOperand(Operands, Mnemonic)) {
2285 Parser.EatToEndOfStatement();
2289 while (getLexer().is(AsmToken::Comma)) {
2290 Parser.Lex(); // Eat the comma.
2292 // Parse and remember the operand.
2293 if (ParseOperand(Operands, Mnemonic)) {
2294 Parser.EatToEndOfStatement();
2300 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2301 Parser.EatToEndOfStatement();
2302 return TokError("unexpected token in argument list");
2305 Parser.Lex(); // Consume the EndOfStatement
2308 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
2309 // another does not. Specifically, the MOVW instruction does not. So we
2310 // special case it here and remove the defaulted (non-setting) cc_out
2311 // operand if that's the instruction we're trying to match.
2313 // We do this post-processing of the explicit operands rather than just
2314 // conditionally adding the cc_out in the first place because we need
2315 // to check the type of the parsed immediate operand.
2316 if (Mnemonic == "mov" && Operands.size() > 4 &&
2317 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
2318 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
2319 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) {
2320 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
2321 Operands.erase(Operands.begin() + 1);
2329 MatchAndEmitInstruction(SMLoc IDLoc,
2330 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2334 MatchResultTy MatchResult;
2335 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
2336 switch (MatchResult) {
2338 Out.EmitInstruction(Inst);
2340 case Match_MissingFeature:
2341 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
2343 case Match_InvalidOperand: {
2344 SMLoc ErrorLoc = IDLoc;
2345 if (ErrorInfo != ~0U) {
2346 if (ErrorInfo >= Operands.size())
2347 return Error(IDLoc, "too few operands for instruction");
2349 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
2350 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
2353 return Error(ErrorLoc, "invalid operand for instruction");
2355 case Match_MnemonicFail:
2356 return Error(IDLoc, "unrecognized instruction mnemonic");
2357 case Match_ConversionFail:
2358 return Error(IDLoc, "unable to convert operands to instruction");
2361 llvm_unreachable("Implement any new match types added!");
2365 /// ParseDirective parses the arm specific directives
2366 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
2367 StringRef IDVal = DirectiveID.getIdentifier();
2368 if (IDVal == ".word")
2369 return ParseDirectiveWord(4, DirectiveID.getLoc());
2370 else if (IDVal == ".thumb")
2371 return ParseDirectiveThumb(DirectiveID.getLoc());
2372 else if (IDVal == ".thumb_func")
2373 return ParseDirectiveThumbFunc(DirectiveID.getLoc());
2374 else if (IDVal == ".code")
2375 return ParseDirectiveCode(DirectiveID.getLoc());
2376 else if (IDVal == ".syntax")
2377 return ParseDirectiveSyntax(DirectiveID.getLoc());
2381 /// ParseDirectiveWord
2382 /// ::= .word [ expression (, expression)* ]
2383 bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
2384 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2386 const MCExpr *Value;
2387 if (getParser().ParseExpression(Value))
2390 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
2392 if (getLexer().is(AsmToken::EndOfStatement))
2395 // FIXME: Improve diagnostic.
2396 if (getLexer().isNot(AsmToken::Comma))
2397 return Error(L, "unexpected token in directive");
2406 /// ParseDirectiveThumb
2408 bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
2409 if (getLexer().isNot(AsmToken::EndOfStatement))
2410 return Error(L, "unexpected token in directive");
2413 // TODO: set thumb mode
2414 // TODO: tell the MC streamer the mode
2415 // getParser().getStreamer().Emit???();
2419 /// ParseDirectiveThumbFunc
2420 /// ::= .thumbfunc symbol_name
2421 bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
2422 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
2423 bool isMachO = MAI.hasSubsectionsViaSymbols();
2426 // Darwin asm has function name after .thumb_func direction
2429 const AsmToken &Tok = Parser.getTok();
2430 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
2431 return Error(L, "unexpected token in .thumb_func directive");
2432 Name = Tok.getString();
2433 Parser.Lex(); // Consume the identifier token.
2436 if (getLexer().isNot(AsmToken::EndOfStatement))
2437 return Error(L, "unexpected token in directive");
2440 // FIXME: assuming function name will be the line following .thumb_func
2442 Name = Parser.getTok().getString();
2445 // Mark symbol as a thumb symbol.
2446 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
2447 getParser().getStreamer().EmitThumbFunc(Func);
2451 /// ParseDirectiveSyntax
2452 /// ::= .syntax unified | divided
2453 bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
2454 const AsmToken &Tok = Parser.getTok();
2455 if (Tok.isNot(AsmToken::Identifier))
2456 return Error(L, "unexpected token in .syntax directive");
2457 StringRef Mode = Tok.getString();
2458 if (Mode == "unified" || Mode == "UNIFIED")
2460 else if (Mode == "divided" || Mode == "DIVIDED")
2461 return Error(L, "'.syntax divided' arm asssembly not supported");
2463 return Error(L, "unrecognized syntax mode in .syntax directive");
2465 if (getLexer().isNot(AsmToken::EndOfStatement))
2466 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
2469 // TODO tell the MC streamer the mode
2470 // getParser().getStreamer().Emit???();
2474 /// ParseDirectiveCode
2475 /// ::= .code 16 | 32
2476 bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
2477 const AsmToken &Tok = Parser.getTok();
2478 if (Tok.isNot(AsmToken::Integer))
2479 return Error(L, "unexpected token in .code directive");
2480 int64_t Val = Parser.getTok().getIntVal();
2486 return Error(L, "invalid operand to .code directive");
2488 if (getLexer().isNot(AsmToken::EndOfStatement))
2489 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
2495 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
2499 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
2505 extern "C" void LLVMInitializeARMAsmLexer();
2507 /// Force static initialization.
2508 extern "C" void LLVMInitializeARMAsmParser() {
2509 RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
2510 RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
2511 LLVMInitializeARMAsmLexer();
2514 #define GET_REGISTER_MATCHER
2515 #define GET_MATCHER_IMPLEMENTATION
2516 #include "ARMGenAsmMatcher.inc"