1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "ARMFPUName.h"
11 #include "ARMFeatures.h"
12 #include "MCTargetDesc/ARMAddressingModes.h"
13 #include "MCTargetDesc/ARMArchName.h"
14 #include "MCTargetDesc/ARMBaseInfo.h"
15 #include "MCTargetDesc/ARMMCExpr.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/MapVector.h"
18 #include "llvm/ADT/OwningPtr.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/ADT/StringSwitch.h"
23 #include "llvm/ADT/Twine.h"
24 #include "llvm/MC/MCAsmInfo.h"
25 #include "llvm/MC/MCAssembler.h"
26 #include "llvm/MC/MCContext.h"
27 #include "llvm/MC/MCDisassembler.h"
28 #include "llvm/MC/MCELFStreamer.h"
29 #include "llvm/MC/MCExpr.h"
30 #include "llvm/MC/MCInst.h"
31 #include "llvm/MC/MCInstrDesc.h"
32 #include "llvm/MC/MCInstrInfo.h"
33 #include "llvm/MC/MCParser/MCAsmLexer.h"
34 #include "llvm/MC/MCParser/MCAsmParser.h"
35 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
36 #include "llvm/MC/MCRegisterInfo.h"
37 #include "llvm/MC/MCSection.h"
38 #include "llvm/MC/MCStreamer.h"
39 #include "llvm/MC/MCSubtargetInfo.h"
40 #include "llvm/MC/MCSymbol.h"
41 #include "llvm/MC/MCTargetAsmParser.h"
42 #include "llvm/Support/ARMBuildAttributes.h"
43 #include "llvm/Support/ARMEHABI.h"
44 #include "llvm/Support/Debug.h"
45 #include "llvm/Support/ELF.h"
46 #include "llvm/Support/MathExtras.h"
47 #include "llvm/Support/SourceMgr.h"
48 #include "llvm/Support/TargetRegistry.h"
49 #include "llvm/Support/raw_ostream.h"
57 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
59 // A class to keep track of assembler-generated constant pools that are use to
60 // implement the ldr-pseudo.
62 typedef SmallVector<std::pair<MCSymbol *, const MCExpr *>, 4> EntryVecTy;
66 // Initialize a new empty constant pool
69 // Add a new entry to the constant pool in the next slot.
70 // \param Value is the new entry to put in the constant pool.
72 // \returns a MCExpr that references the newly inserted value
73 const MCExpr *addEntry(const MCExpr *Value, MCContext &Context) {
74 MCSymbol *CPEntryLabel = Context.CreateTempSymbol();
76 Entries.push_back(std::make_pair(CPEntryLabel, Value));
77 return MCSymbolRefExpr::Create(CPEntryLabel, Context);
80 // Emit the contents of the constant pool using the provided streamer.
81 void emitEntries(MCStreamer &Streamer) {
84 Streamer.EmitCodeAlignment(4); // align to 4-byte address
85 Streamer.EmitDataRegion(MCDR_DataRegion);
86 for (EntryVecTy::const_iterator I = Entries.begin(), E = Entries.end();
88 Streamer.EmitLabel(I->first);
89 Streamer.EmitValue(I->second, 4);
91 Streamer.EmitDataRegion(MCDR_DataRegionEnd);
95 // Return true if the constant pool is empty
97 return Entries.empty();
101 // Map type used to keep track of per-Section constant pools used by the
102 // ldr-pseudo opcode. The map associates a section to its constant pool. The
103 // constant pool is a vector of (label, value) pairs. When the ldr
104 // pseudo is parsed we insert a new (label, value) pair into the constant pool
105 // for the current section and add MCSymbolRefExpr to the new label as
106 // an opcode to the ldr. After we have parsed all the user input we
107 // output the (label, value) pairs in each constant pool at the end of the
110 // We use the MapVector for the map type to ensure stable iteration of
111 // the sections at the end of the parse. We need to iterate over the
112 // sections in a stable order to ensure that we have print the
113 // constant pools in a deterministic order when printing an assembly
115 typedef MapVector<const MCSection *, ConstantPool> ConstantPoolMapTy;
117 class UnwindContext {
120 typedef SmallVector<SMLoc, 4> Locs;
124 Locs PersonalityLocs;
125 Locs PersonalityIndexLocs;
126 Locs HandlerDataLocs;
130 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(-1) {}
132 bool hasFnStart() const { return !FnStartLocs.empty(); }
133 bool cantUnwind() const { return !CantUnwindLocs.empty(); }
134 bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
135 bool hasPersonality() const {
136 return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
139 void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
140 void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
141 void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
142 void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
143 void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
145 void saveFPReg(int Reg) { FPReg = Reg; }
146 int getFPReg() const { return FPReg; }
148 void emitFnStartLocNotes() const {
149 for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
151 Parser.Note(*FI, ".fnstart was specified here");
153 void emitCantUnwindLocNotes() const {
154 for (Locs::const_iterator UI = CantUnwindLocs.begin(),
155 UE = CantUnwindLocs.end(); UI != UE; ++UI)
156 Parser.Note(*UI, ".cantunwind was specified here");
158 void emitHandlerDataLocNotes() const {
159 for (Locs::const_iterator HI = HandlerDataLocs.begin(),
160 HE = HandlerDataLocs.end(); HI != HE; ++HI)
161 Parser.Note(*HI, ".handlerdata was specified here");
163 void emitPersonalityLocNotes() const {
164 for (Locs::const_iterator PI = PersonalityLocs.begin(),
165 PE = PersonalityLocs.end(),
166 PII = PersonalityIndexLocs.begin(),
167 PIE = PersonalityIndexLocs.end();
168 PI != PE || PII != PIE;) {
169 if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
170 Parser.Note(*PI++, ".personality was specified here");
171 else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
172 Parser.Note(*PII++, ".personalityindex was specified here");
174 llvm_unreachable(".personality and .personalityindex cannot be "
175 "at the same location");
180 FnStartLocs = Locs();
181 CantUnwindLocs = Locs();
182 PersonalityLocs = Locs();
183 HandlerDataLocs = Locs();
184 PersonalityIndexLocs = Locs();
189 class ARMAsmParser : public MCTargetAsmParser {
190 MCSubtargetInfo &STI;
192 const MCInstrInfo &MII;
193 const MCRegisterInfo *MRI;
194 ConstantPoolMapTy ConstantPools;
197 // Assembler created constant pools for ldr pseudo
198 ConstantPool *getConstantPool(const MCSection *Section) {
199 ConstantPoolMapTy::iterator CP = ConstantPools.find(Section);
200 if (CP == ConstantPools.end())
206 ConstantPool &getOrCreateConstantPool(const MCSection *Section) {
207 return ConstantPools[Section];
210 ARMTargetStreamer &getTargetStreamer() {
211 MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
212 return static_cast<ARMTargetStreamer &>(TS);
215 // Map of register aliases registers via the .req directive.
216 StringMap<unsigned> RegisterReqs;
218 bool NextSymbolIsThumb;
221 ARMCC::CondCodes Cond; // Condition for IT block.
222 unsigned Mask:4; // Condition mask for instructions.
223 // Starting at first 1 (from lsb).
224 // '1' condition as indicated in IT.
225 // '0' inverse of condition (else).
226 // Count of instructions in IT block is
227 // 4 - trailingzeroes(mask)
229 bool FirstCond; // Explicit flag for when we're parsing the
230 // First instruction in the IT block. It's
231 // implied in the mask, so needs special
234 unsigned CurPosition; // Current position in parsing of IT
235 // block. In range [0,3]. Initialized
236 // according to count of instructions in block.
237 // ~0U if no active IT block.
239 bool inITBlock() { return ITState.CurPosition != ~0U;}
240 void forwardITPosition() {
241 if (!inITBlock()) return;
242 // Move to the next instruction in the IT block, if there is one. If not,
243 // mark the block as done.
244 unsigned TZ = countTrailingZeros(ITState.Mask);
245 if (++ITState.CurPosition == 5 - TZ)
246 ITState.CurPosition = ~0U; // Done with the IT block after this.
250 MCAsmParser &getParser() const { return Parser; }
251 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
253 void Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges = None) {
254 return Parser.Note(L, Msg, Ranges);
256 bool Warning(SMLoc L, const Twine &Msg,
257 ArrayRef<SMRange> Ranges = None) {
258 return Parser.Warning(L, Msg, Ranges);
260 bool Error(SMLoc L, const Twine &Msg,
261 ArrayRef<SMRange> Ranges = None) {
262 return Parser.Error(L, Msg, Ranges);
265 int tryParseRegister();
266 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
267 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
268 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
269 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
270 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
271 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
272 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
273 unsigned &ShiftAmount);
274 bool parseDirectiveWord(unsigned Size, SMLoc L);
275 bool parseDirectiveThumb(SMLoc L);
276 bool parseDirectiveARM(SMLoc L);
277 bool parseDirectiveThumbFunc(SMLoc L);
278 bool parseDirectiveCode(SMLoc L);
279 bool parseDirectiveSyntax(SMLoc L);
280 bool parseDirectiveReq(StringRef Name, SMLoc L);
281 bool parseDirectiveUnreq(SMLoc L);
282 bool parseDirectiveArch(SMLoc L);
283 bool parseDirectiveEabiAttr(SMLoc L);
284 bool parseDirectiveCPU(SMLoc L);
285 bool parseDirectiveFPU(SMLoc L);
286 bool parseDirectiveFnStart(SMLoc L);
287 bool parseDirectiveFnEnd(SMLoc L);
288 bool parseDirectiveCantUnwind(SMLoc L);
289 bool parseDirectivePersonality(SMLoc L);
290 bool parseDirectiveHandlerData(SMLoc L);
291 bool parseDirectiveSetFP(SMLoc L);
292 bool parseDirectivePad(SMLoc L);
293 bool parseDirectiveRegSave(SMLoc L, bool IsVector);
294 bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
295 bool parseDirectiveLtorg(SMLoc L);
296 bool parseDirectiveEven(SMLoc L);
297 bool parseDirectivePersonalityIndex(SMLoc L);
298 bool parseDirectiveUnwindRaw(SMLoc L);
300 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
301 bool &CarrySetting, unsigned &ProcessorIMod,
303 void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
304 bool &CanAcceptCarrySet,
305 bool &CanAcceptPredicationCode);
307 bool isThumb() const {
308 // FIXME: Can tablegen auto-generate this?
309 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
311 bool isThumbOne() const {
312 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
314 bool isThumbTwo() const {
315 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
317 bool hasThumb() const {
318 return STI.getFeatureBits() & ARM::HasV4TOps;
320 bool hasV6Ops() const {
321 return STI.getFeatureBits() & ARM::HasV6Ops;
323 bool hasV6MOps() const {
324 return STI.getFeatureBits() & ARM::HasV6MOps;
326 bool hasV7Ops() const {
327 return STI.getFeatureBits() & ARM::HasV7Ops;
329 bool hasV8Ops() const {
330 return STI.getFeatureBits() & ARM::HasV8Ops;
332 bool hasARM() const {
333 return !(STI.getFeatureBits() & ARM::FeatureNoARM);
337 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
338 setAvailableFeatures(FB);
340 bool isMClass() const {
341 return STI.getFeatureBits() & ARM::FeatureMClass;
344 /// @name Auto-generated Match Functions
347 #define GET_ASSEMBLER_HEADER
348 #include "ARMGenAsmMatcher.inc"
352 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
353 OperandMatchResultTy parseCoprocNumOperand(
354 SmallVectorImpl<MCParsedAsmOperand*>&);
355 OperandMatchResultTy parseCoprocRegOperand(
356 SmallVectorImpl<MCParsedAsmOperand*>&);
357 OperandMatchResultTy parseCoprocOptionOperand(
358 SmallVectorImpl<MCParsedAsmOperand*>&);
359 OperandMatchResultTy parseMemBarrierOptOperand(
360 SmallVectorImpl<MCParsedAsmOperand*>&);
361 OperandMatchResultTy parseInstSyncBarrierOptOperand(
362 SmallVectorImpl<MCParsedAsmOperand*>&);
363 OperandMatchResultTy parseProcIFlagsOperand(
364 SmallVectorImpl<MCParsedAsmOperand*>&);
365 OperandMatchResultTy parseMSRMaskOperand(
366 SmallVectorImpl<MCParsedAsmOperand*>&);
367 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
368 StringRef Op, int Low, int High);
369 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
370 return parsePKHImm(O, "lsl", 0, 31);
372 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
373 return parsePKHImm(O, "asr", 1, 32);
375 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
376 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
377 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
378 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
379 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
380 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
381 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
382 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
383 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
386 // Asm Match Converter Methods
387 void cvtThumbMultiply(MCInst &Inst,
388 const SmallVectorImpl<MCParsedAsmOperand*> &);
389 void cvtThumbBranches(MCInst &Inst,
390 const SmallVectorImpl<MCParsedAsmOperand*> &);
392 bool validateInstruction(MCInst &Inst,
393 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
394 bool processInstruction(MCInst &Inst,
395 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
396 bool shouldOmitCCOutOperand(StringRef Mnemonic,
397 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
398 bool shouldOmitPredicateOperand(StringRef Mnemonic,
399 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
401 enum ARMMatchResultTy {
402 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
403 Match_RequiresNotITBlock,
405 Match_RequiresThumb2,
406 #define GET_OPERAND_DIAGNOSTIC_TYPES
407 #include "ARMGenAsmMatcher.inc"
411 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
412 const MCInstrInfo &MII)
413 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(MII), UC(_Parser) {
414 MCAsmParserExtension::Initialize(_Parser);
416 // Cache the MCRegisterInfo.
417 MRI = getContext().getRegisterInfo();
419 // Initialize the set of available features.
420 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
422 // Not in an ITBlock to start with.
423 ITState.CurPosition = ~0U;
425 NextSymbolIsThumb = false;
428 // Implementation of the MCTargetAsmParser interface:
429 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
430 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
432 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
433 bool ParseDirective(AsmToken DirectiveID);
435 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
436 unsigned checkTargetMatchPredicate(MCInst &Inst);
438 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
439 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
440 MCStreamer &Out, unsigned &ErrorInfo,
441 bool MatchingInlineAsm);
442 void onLabelParsed(MCSymbol *Symbol);
445 } // end anonymous namespace
449 /// ARMOperand - Instances of this class represent a parsed ARM machine
451 class ARMOperand : public MCParsedAsmOperand {
461 k_InstSyncBarrierOpt,
472 k_VectorListAllLanes,
478 k_BitfieldDescriptor,
482 SMLoc StartLoc, EndLoc;
483 SmallVector<unsigned, 8> Registers;
486 ARMCC::CondCodes Val;
493 struct CoprocOptionOp {
506 ARM_ISB::InstSyncBOpt Val;
510 ARM_PROC::IFlags Val;
526 // A vector register list is a sequential list of 1 to 4 registers.
527 struct VectorListOp {
534 struct VectorIndexOp {
542 /// Combined record for all forms of ARM address expressions.
545 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
547 const MCConstantExpr *OffsetImm; // Offset immediate value
548 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
549 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
550 unsigned ShiftImm; // shift for OffsetReg.
551 unsigned Alignment; // 0 = no alignment specified
552 // n = alignment in bytes (2, 4, 8, 16, or 32)
553 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
556 struct PostIdxRegOp {
559 ARM_AM::ShiftOpc ShiftTy;
563 struct ShifterImmOp {
568 struct RegShiftedRegOp {
569 ARM_AM::ShiftOpc ShiftTy;
575 struct RegShiftedImmOp {
576 ARM_AM::ShiftOpc ShiftTy;
593 struct CoprocOptionOp CoprocOption;
594 struct MBOptOp MBOpt;
595 struct ISBOptOp ISBOpt;
596 struct ITMaskOp ITMask;
597 struct IFlagsOp IFlags;
598 struct MMaskOp MMask;
601 struct VectorListOp VectorList;
602 struct VectorIndexOp VectorIndex;
604 struct MemoryOp Memory;
605 struct PostIdxRegOp PostIdxReg;
606 struct ShifterImmOp ShifterImm;
607 struct RegShiftedRegOp RegShiftedReg;
608 struct RegShiftedImmOp RegShiftedImm;
609 struct RotImmOp RotImm;
610 struct BitfieldOp Bitfield;
613 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
615 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
617 StartLoc = o.StartLoc;
634 case k_DPRRegisterList:
635 case k_SPRRegisterList:
636 Registers = o.Registers;
639 case k_VectorListAllLanes:
640 case k_VectorListIndexed:
641 VectorList = o.VectorList;
648 CoprocOption = o.CoprocOption;
653 case k_MemBarrierOpt:
656 case k_InstSyncBarrierOpt:
661 case k_PostIndexRegister:
662 PostIdxReg = o.PostIdxReg;
670 case k_ShifterImmediate:
671 ShifterImm = o.ShifterImm;
673 case k_ShiftedRegister:
674 RegShiftedReg = o.RegShiftedReg;
676 case k_ShiftedImmediate:
677 RegShiftedImm = o.RegShiftedImm;
679 case k_RotateImmediate:
682 case k_BitfieldDescriptor:
683 Bitfield = o.Bitfield;
686 VectorIndex = o.VectorIndex;
691 /// getStartLoc - Get the location of the first token of this operand.
692 SMLoc getStartLoc() const { return StartLoc; }
693 /// getEndLoc - Get the location of the last token of this operand.
694 SMLoc getEndLoc() const { return EndLoc; }
695 /// getLocRange - Get the range between the first and last token of this
697 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
699 ARMCC::CondCodes getCondCode() const {
700 assert(Kind == k_CondCode && "Invalid access!");
704 unsigned getCoproc() const {
705 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
709 StringRef getToken() const {
710 assert(Kind == k_Token && "Invalid access!");
711 return StringRef(Tok.Data, Tok.Length);
714 unsigned getReg() const {
715 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
719 const SmallVectorImpl<unsigned> &getRegList() const {
720 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
721 Kind == k_SPRRegisterList) && "Invalid access!");
725 const MCExpr *getImm() const {
726 assert(isImm() && "Invalid access!");
730 unsigned getVectorIndex() const {
731 assert(Kind == k_VectorIndex && "Invalid access!");
732 return VectorIndex.Val;
735 ARM_MB::MemBOpt getMemBarrierOpt() const {
736 assert(Kind == k_MemBarrierOpt && "Invalid access!");
740 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
741 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
745 ARM_PROC::IFlags getProcIFlags() const {
746 assert(Kind == k_ProcIFlags && "Invalid access!");
750 unsigned getMSRMask() const {
751 assert(Kind == k_MSRMask && "Invalid access!");
755 bool isCoprocNum() const { return Kind == k_CoprocNum; }
756 bool isCoprocReg() const { return Kind == k_CoprocReg; }
757 bool isCoprocOption() const { return Kind == k_CoprocOption; }
758 bool isCondCode() const { return Kind == k_CondCode; }
759 bool isCCOut() const { return Kind == k_CCOut; }
760 bool isITMask() const { return Kind == k_ITCondMask; }
761 bool isITCondCode() const { return Kind == k_CondCode; }
762 bool isImm() const { return Kind == k_Immediate; }
763 // checks whether this operand is an unsigned offset which fits is a field
764 // of specified width and scaled by a specific number of bits
765 template<unsigned width, unsigned scale>
766 bool isUnsignedOffset() const {
767 if (!isImm()) return false;
768 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
769 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
770 int64_t Val = CE->getValue();
771 int64_t Align = 1LL << scale;
772 int64_t Max = Align * ((1LL << width) - 1);
773 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
777 // checks whether this operand is an signed offset which fits is a field
778 // of specified width and scaled by a specific number of bits
779 template<unsigned width, unsigned scale>
780 bool isSignedOffset() const {
781 if (!isImm()) return false;
782 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
783 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
784 int64_t Val = CE->getValue();
785 int64_t Align = 1LL << scale;
786 int64_t Max = Align * ((1LL << (width-1)) - 1);
787 int64_t Min = -Align * (1LL << (width-1));
788 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
793 // checks whether this operand is a memory operand computed as an offset
794 // applied to PC. the offset may have 8 bits of magnitude and is represented
795 // with two bits of shift. textually it may be either [pc, #imm], #imm or
796 // relocable expression...
797 bool isThumbMemPC() const {
800 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
801 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
802 if (!CE) return false;
803 Val = CE->getValue();
806 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
807 if(Memory.BaseRegNum != ARM::PC) return false;
808 Val = Memory.OffsetImm->getValue();
811 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
813 bool isFPImm() const {
814 if (!isImm()) return false;
815 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
816 if (!CE) return false;
817 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
820 bool isFBits16() const {
821 if (!isImm()) return false;
822 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
823 if (!CE) return false;
824 int64_t Value = CE->getValue();
825 return Value >= 0 && Value <= 16;
827 bool isFBits32() const {
828 if (!isImm()) return false;
829 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
830 if (!CE) return false;
831 int64_t Value = CE->getValue();
832 return Value >= 1 && Value <= 32;
834 bool isImm8s4() const {
835 if (!isImm()) return false;
836 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
837 if (!CE) return false;
838 int64_t Value = CE->getValue();
839 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
841 bool isImm0_1020s4() const {
842 if (!isImm()) return false;
843 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
844 if (!CE) return false;
845 int64_t Value = CE->getValue();
846 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
848 bool isImm0_508s4() const {
849 if (!isImm()) return false;
850 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
851 if (!CE) return false;
852 int64_t Value = CE->getValue();
853 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
855 bool isImm0_508s4Neg() const {
856 if (!isImm()) return false;
857 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
858 if (!CE) return false;
859 int64_t Value = -CE->getValue();
860 // explicitly exclude zero. we want that to use the normal 0_508 version.
861 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
863 bool isImm0_239() const {
864 if (!isImm()) return false;
865 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
866 if (!CE) return false;
867 int64_t Value = CE->getValue();
868 return Value >= 0 && Value < 240;
870 bool isImm0_255() const {
871 if (!isImm()) return false;
872 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
873 if (!CE) return false;
874 int64_t Value = CE->getValue();
875 return Value >= 0 && Value < 256;
877 bool isImm0_4095() const {
878 if (!isImm()) return false;
879 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
880 if (!CE) return false;
881 int64_t Value = CE->getValue();
882 return Value >= 0 && Value < 4096;
884 bool isImm0_4095Neg() const {
885 if (!isImm()) return false;
886 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
887 if (!CE) return false;
888 int64_t Value = -CE->getValue();
889 return Value > 0 && Value < 4096;
891 bool isImm0_1() const {
892 if (!isImm()) return false;
893 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
894 if (!CE) return false;
895 int64_t Value = CE->getValue();
896 return Value >= 0 && Value < 2;
898 bool isImm0_3() const {
899 if (!isImm()) return false;
900 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
901 if (!CE) return false;
902 int64_t Value = CE->getValue();
903 return Value >= 0 && Value < 4;
905 bool isImm0_7() const {
906 if (!isImm()) return false;
907 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
908 if (!CE) return false;
909 int64_t Value = CE->getValue();
910 return Value >= 0 && Value < 8;
912 bool isImm0_15() const {
913 if (!isImm()) return false;
914 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
915 if (!CE) return false;
916 int64_t Value = CE->getValue();
917 return Value >= 0 && Value < 16;
919 bool isImm0_31() const {
920 if (!isImm()) return false;
921 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
922 if (!CE) return false;
923 int64_t Value = CE->getValue();
924 return Value >= 0 && Value < 32;
926 bool isImm0_63() const {
927 if (!isImm()) return false;
928 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
929 if (!CE) return false;
930 int64_t Value = CE->getValue();
931 return Value >= 0 && Value < 64;
933 bool isImm8() const {
934 if (!isImm()) return false;
935 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
936 if (!CE) return false;
937 int64_t Value = CE->getValue();
940 bool isImm16() const {
941 if (!isImm()) return false;
942 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
943 if (!CE) return false;
944 int64_t Value = CE->getValue();
947 bool isImm32() const {
948 if (!isImm()) return false;
949 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
950 if (!CE) return false;
951 int64_t Value = CE->getValue();
954 bool isShrImm8() const {
955 if (!isImm()) return false;
956 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
957 if (!CE) return false;
958 int64_t Value = CE->getValue();
959 return Value > 0 && Value <= 8;
961 bool isShrImm16() const {
962 if (!isImm()) return false;
963 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
964 if (!CE) return false;
965 int64_t Value = CE->getValue();
966 return Value > 0 && Value <= 16;
968 bool isShrImm32() const {
969 if (!isImm()) return false;
970 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
971 if (!CE) return false;
972 int64_t Value = CE->getValue();
973 return Value > 0 && Value <= 32;
975 bool isShrImm64() const {
976 if (!isImm()) return false;
977 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
978 if (!CE) return false;
979 int64_t Value = CE->getValue();
980 return Value > 0 && Value <= 64;
982 bool isImm1_7() const {
983 if (!isImm()) return false;
984 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
985 if (!CE) return false;
986 int64_t Value = CE->getValue();
987 return Value > 0 && Value < 8;
989 bool isImm1_15() const {
990 if (!isImm()) return false;
991 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
992 if (!CE) return false;
993 int64_t Value = CE->getValue();
994 return Value > 0 && Value < 16;
996 bool isImm1_31() const {
997 if (!isImm()) return false;
998 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
999 if (!CE) return false;
1000 int64_t Value = CE->getValue();
1001 return Value > 0 && Value < 32;
1003 bool isImm1_16() const {
1004 if (!isImm()) return false;
1005 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1006 if (!CE) return false;
1007 int64_t Value = CE->getValue();
1008 return Value > 0 && Value < 17;
1010 bool isImm1_32() const {
1011 if (!isImm()) return false;
1012 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1013 if (!CE) return false;
1014 int64_t Value = CE->getValue();
1015 return Value > 0 && Value < 33;
1017 bool isImm0_32() const {
1018 if (!isImm()) return false;
1019 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1020 if (!CE) return false;
1021 int64_t Value = CE->getValue();
1022 return Value >= 0 && Value < 33;
1024 bool isImm0_65535() const {
1025 if (!isImm()) return false;
1026 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1027 if (!CE) return false;
1028 int64_t Value = CE->getValue();
1029 return Value >= 0 && Value < 65536;
1031 bool isImm256_65535Expr() const {
1032 if (!isImm()) return false;
1033 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1034 // If it's not a constant expression, it'll generate a fixup and be
1036 if (!CE) return true;
1037 int64_t Value = CE->getValue();
1038 return Value >= 256 && Value < 65536;
1040 bool isImm0_65535Expr() const {
1041 if (!isImm()) return false;
1042 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1043 // If it's not a constant expression, it'll generate a fixup and be
1045 if (!CE) return true;
1046 int64_t Value = CE->getValue();
1047 return Value >= 0 && Value < 65536;
1049 bool isImm24bit() const {
1050 if (!isImm()) return false;
1051 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1052 if (!CE) return false;
1053 int64_t Value = CE->getValue();
1054 return Value >= 0 && Value <= 0xffffff;
1056 bool isImmThumbSR() const {
1057 if (!isImm()) return false;
1058 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1059 if (!CE) return false;
1060 int64_t Value = CE->getValue();
1061 return Value > 0 && Value < 33;
1063 bool isPKHLSLImm() const {
1064 if (!isImm()) return false;
1065 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1066 if (!CE) return false;
1067 int64_t Value = CE->getValue();
1068 return Value >= 0 && Value < 32;
1070 bool isPKHASRImm() const {
1071 if (!isImm()) return false;
1072 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1073 if (!CE) return false;
1074 int64_t Value = CE->getValue();
1075 return Value > 0 && Value <= 32;
1077 bool isAdrLabel() const {
1078 // If we have an immediate that's not a constant, treat it as a label
1079 // reference needing a fixup. If it is a constant, but it can't fit
1080 // into shift immediate encoding, we reject it.
1081 if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
1082 else return (isARMSOImm() || isARMSOImmNeg());
1084 bool isARMSOImm() const {
1085 if (!isImm()) return false;
1086 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1087 if (!CE) return false;
1088 int64_t Value = CE->getValue();
1089 return ARM_AM::getSOImmVal(Value) != -1;
1091 bool isARMSOImmNot() const {
1092 if (!isImm()) return false;
1093 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1094 if (!CE) return false;
1095 int64_t Value = CE->getValue();
1096 return ARM_AM::getSOImmVal(~Value) != -1;
1098 bool isARMSOImmNeg() const {
1099 if (!isImm()) return false;
1100 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1101 if (!CE) return false;
1102 int64_t Value = CE->getValue();
1103 // Only use this when not representable as a plain so_imm.
1104 return ARM_AM::getSOImmVal(Value) == -1 &&
1105 ARM_AM::getSOImmVal(-Value) != -1;
1107 bool isT2SOImm() const {
1108 if (!isImm()) return false;
1109 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1110 if (!CE) return false;
1111 int64_t Value = CE->getValue();
1112 return ARM_AM::getT2SOImmVal(Value) != -1;
1114 bool isT2SOImmNot() const {
1115 if (!isImm()) return false;
1116 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1117 if (!CE) return false;
1118 int64_t Value = CE->getValue();
1119 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1120 ARM_AM::getT2SOImmVal(~Value) != -1;
1122 bool isT2SOImmNeg() const {
1123 if (!isImm()) return false;
1124 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1125 if (!CE) return false;
1126 int64_t Value = CE->getValue();
1127 // Only use this when not representable as a plain so_imm.
1128 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1129 ARM_AM::getT2SOImmVal(-Value) != -1;
1131 bool isSetEndImm() const {
1132 if (!isImm()) return false;
1133 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1134 if (!CE) return false;
1135 int64_t Value = CE->getValue();
1136 return Value == 1 || Value == 0;
1138 bool isReg() const { return Kind == k_Register; }
1139 bool isRegList() const { return Kind == k_RegisterList; }
1140 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1141 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1142 bool isToken() const { return Kind == k_Token; }
1143 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1144 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1145 bool isMem() const { return Kind == k_Memory; }
1146 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1147 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
1148 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
1149 bool isRotImm() const { return Kind == k_RotateImmediate; }
1150 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1151 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
1152 bool isPostIdxReg() const {
1153 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
1155 bool isMemNoOffset(bool alignOK = false) const {
1158 // No offset of any kind.
1159 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
1160 (alignOK || Memory.Alignment == 0);
1162 bool isMemPCRelImm12() const {
1163 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1165 // Base register must be PC.
1166 if (Memory.BaseRegNum != ARM::PC)
1168 // Immediate offset in range [-4095, 4095].
1169 if (!Memory.OffsetImm) return true;
1170 int64_t Val = Memory.OffsetImm->getValue();
1171 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1173 bool isAlignedMemory() const {
1174 return isMemNoOffset(true);
1176 bool isAddrMode2() const {
1177 if (!isMem() || Memory.Alignment != 0) return false;
1178 // Check for register offset.
1179 if (Memory.OffsetRegNum) return true;
1180 // Immediate offset in range [-4095, 4095].
1181 if (!Memory.OffsetImm) return true;
1182 int64_t Val = Memory.OffsetImm->getValue();
1183 return Val > -4096 && Val < 4096;
1185 bool isAM2OffsetImm() const {
1186 if (!isImm()) return false;
1187 // Immediate offset in range [-4095, 4095].
1188 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1189 if (!CE) return false;
1190 int64_t Val = CE->getValue();
1191 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1193 bool isAddrMode3() const {
1194 // If we have an immediate that's not a constant, treat it as a label
1195 // reference needing a fixup. If it is a constant, it's something else
1196 // and we reject it.
1197 if (isImm() && !isa<MCConstantExpr>(getImm()))
1199 if (!isMem() || Memory.Alignment != 0) return false;
1200 // No shifts are legal for AM3.
1201 if (Memory.ShiftType != ARM_AM::no_shift) return false;
1202 // Check for register offset.
1203 if (Memory.OffsetRegNum) return true;
1204 // Immediate offset in range [-255, 255].
1205 if (!Memory.OffsetImm) return true;
1206 int64_t Val = Memory.OffsetImm->getValue();
1207 // The #-0 offset is encoded as INT32_MIN, and we have to check
1209 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1211 bool isAM3Offset() const {
1212 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1214 if (Kind == k_PostIndexRegister)
1215 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1216 // Immediate offset in range [-255, 255].
1217 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1218 if (!CE) return false;
1219 int64_t Val = CE->getValue();
1220 // Special case, #-0 is INT32_MIN.
1221 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1223 bool isAddrMode5() const {
1224 // If we have an immediate that's not a constant, treat it as a label
1225 // reference needing a fixup. If it is a constant, it's something else
1226 // and we reject it.
1227 if (isImm() && !isa<MCConstantExpr>(getImm()))
1229 if (!isMem() || Memory.Alignment != 0) return false;
1230 // Check for register offset.
1231 if (Memory.OffsetRegNum) return false;
1232 // Immediate offset in range [-1020, 1020] and a multiple of 4.
1233 if (!Memory.OffsetImm) return true;
1234 int64_t Val = Memory.OffsetImm->getValue();
1235 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1238 bool isMemTBB() const {
1239 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1240 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1244 bool isMemTBH() const {
1245 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1246 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1247 Memory.Alignment != 0 )
1251 bool isMemRegOffset() const {
1252 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1256 bool isT2MemRegOffset() const {
1257 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1258 Memory.Alignment != 0)
1260 // Only lsl #{0, 1, 2, 3} allowed.
1261 if (Memory.ShiftType == ARM_AM::no_shift)
1263 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1267 bool isMemThumbRR() const {
1268 // Thumb reg+reg addressing is simple. Just two registers, a base and
1269 // an offset. No shifts, negations or any other complicating factors.
1270 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1271 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1273 return isARMLowRegister(Memory.BaseRegNum) &&
1274 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1276 bool isMemThumbRIs4() const {
1277 if (!isMem() || Memory.OffsetRegNum != 0 ||
1278 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1280 // Immediate offset, multiple of 4 in range [0, 124].
1281 if (!Memory.OffsetImm) return true;
1282 int64_t Val = Memory.OffsetImm->getValue();
1283 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1285 bool isMemThumbRIs2() const {
1286 if (!isMem() || Memory.OffsetRegNum != 0 ||
1287 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1289 // Immediate offset, multiple of 4 in range [0, 62].
1290 if (!Memory.OffsetImm) return true;
1291 int64_t Val = Memory.OffsetImm->getValue();
1292 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1294 bool isMemThumbRIs1() const {
1295 if (!isMem() || Memory.OffsetRegNum != 0 ||
1296 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1298 // Immediate offset in range [0, 31].
1299 if (!Memory.OffsetImm) return true;
1300 int64_t Val = Memory.OffsetImm->getValue();
1301 return Val >= 0 && Val <= 31;
1303 bool isMemThumbSPI() const {
1304 if (!isMem() || Memory.OffsetRegNum != 0 ||
1305 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1307 // Immediate offset, multiple of 4 in range [0, 1020].
1308 if (!Memory.OffsetImm) return true;
1309 int64_t Val = Memory.OffsetImm->getValue();
1310 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1312 bool isMemImm8s4Offset() const {
1313 // If we have an immediate that's not a constant, treat it as a label
1314 // reference needing a fixup. If it is a constant, it's something else
1315 // and we reject it.
1316 if (isImm() && !isa<MCConstantExpr>(getImm()))
1318 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1320 // Immediate offset a multiple of 4 in range [-1020, 1020].
1321 if (!Memory.OffsetImm) return true;
1322 int64_t Val = Memory.OffsetImm->getValue();
1323 // Special case, #-0 is INT32_MIN.
1324 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1326 bool isMemImm0_1020s4Offset() const {
1327 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1329 // Immediate offset a multiple of 4 in range [0, 1020].
1330 if (!Memory.OffsetImm) return true;
1331 int64_t Val = Memory.OffsetImm->getValue();
1332 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1334 bool isMemImm8Offset() const {
1335 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1337 // Base reg of PC isn't allowed for these encodings.
1338 if (Memory.BaseRegNum == ARM::PC) return false;
1339 // Immediate offset in range [-255, 255].
1340 if (!Memory.OffsetImm) return true;
1341 int64_t Val = Memory.OffsetImm->getValue();
1342 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1344 bool isMemPosImm8Offset() const {
1345 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1347 // Immediate offset in range [0, 255].
1348 if (!Memory.OffsetImm) return true;
1349 int64_t Val = Memory.OffsetImm->getValue();
1350 return Val >= 0 && Val < 256;
1352 bool isMemNegImm8Offset() const {
1353 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1355 // Base reg of PC isn't allowed for these encodings.
1356 if (Memory.BaseRegNum == ARM::PC) return false;
1357 // Immediate offset in range [-255, -1].
1358 if (!Memory.OffsetImm) return false;
1359 int64_t Val = Memory.OffsetImm->getValue();
1360 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1362 bool isMemUImm12Offset() const {
1363 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1365 // Immediate offset in range [0, 4095].
1366 if (!Memory.OffsetImm) return true;
1367 int64_t Val = Memory.OffsetImm->getValue();
1368 return (Val >= 0 && Val < 4096);
1370 bool isMemImm12Offset() const {
1371 // If we have an immediate that's not a constant, treat it as a label
1372 // reference needing a fixup. If it is a constant, it's something else
1373 // and we reject it.
1374 if (isImm() && !isa<MCConstantExpr>(getImm()))
1377 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1379 // Immediate offset in range [-4095, 4095].
1380 if (!Memory.OffsetImm) return true;
1381 int64_t Val = Memory.OffsetImm->getValue();
1382 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1384 bool isPostIdxImm8() const {
1385 if (!isImm()) return false;
1386 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1387 if (!CE) return false;
1388 int64_t Val = CE->getValue();
1389 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1391 bool isPostIdxImm8s4() const {
1392 if (!isImm()) return false;
1393 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1394 if (!CE) return false;
1395 int64_t Val = CE->getValue();
1396 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1400 bool isMSRMask() const { return Kind == k_MSRMask; }
1401 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1404 bool isSingleSpacedVectorList() const {
1405 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1407 bool isDoubleSpacedVectorList() const {
1408 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1410 bool isVecListOneD() const {
1411 if (!isSingleSpacedVectorList()) return false;
1412 return VectorList.Count == 1;
1415 bool isVecListDPair() const {
1416 if (!isSingleSpacedVectorList()) return false;
1417 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1418 .contains(VectorList.RegNum));
1421 bool isVecListThreeD() const {
1422 if (!isSingleSpacedVectorList()) return false;
1423 return VectorList.Count == 3;
1426 bool isVecListFourD() const {
1427 if (!isSingleSpacedVectorList()) return false;
1428 return VectorList.Count == 4;
1431 bool isVecListDPairSpaced() const {
1432 if (isSingleSpacedVectorList()) return false;
1433 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1434 .contains(VectorList.RegNum));
1437 bool isVecListThreeQ() const {
1438 if (!isDoubleSpacedVectorList()) return false;
1439 return VectorList.Count == 3;
1442 bool isVecListFourQ() const {
1443 if (!isDoubleSpacedVectorList()) return false;
1444 return VectorList.Count == 4;
1447 bool isSingleSpacedVectorAllLanes() const {
1448 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1450 bool isDoubleSpacedVectorAllLanes() const {
1451 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1453 bool isVecListOneDAllLanes() const {
1454 if (!isSingleSpacedVectorAllLanes()) return false;
1455 return VectorList.Count == 1;
1458 bool isVecListDPairAllLanes() const {
1459 if (!isSingleSpacedVectorAllLanes()) return false;
1460 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1461 .contains(VectorList.RegNum));
1464 bool isVecListDPairSpacedAllLanes() const {
1465 if (!isDoubleSpacedVectorAllLanes()) return false;
1466 return VectorList.Count == 2;
1469 bool isVecListThreeDAllLanes() const {
1470 if (!isSingleSpacedVectorAllLanes()) return false;
1471 return VectorList.Count == 3;
1474 bool isVecListThreeQAllLanes() const {
1475 if (!isDoubleSpacedVectorAllLanes()) return false;
1476 return VectorList.Count == 3;
1479 bool isVecListFourDAllLanes() const {
1480 if (!isSingleSpacedVectorAllLanes()) return false;
1481 return VectorList.Count == 4;
1484 bool isVecListFourQAllLanes() const {
1485 if (!isDoubleSpacedVectorAllLanes()) return false;
1486 return VectorList.Count == 4;
1489 bool isSingleSpacedVectorIndexed() const {
1490 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1492 bool isDoubleSpacedVectorIndexed() const {
1493 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1495 bool isVecListOneDByteIndexed() const {
1496 if (!isSingleSpacedVectorIndexed()) return false;
1497 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1500 bool isVecListOneDHWordIndexed() const {
1501 if (!isSingleSpacedVectorIndexed()) return false;
1502 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1505 bool isVecListOneDWordIndexed() const {
1506 if (!isSingleSpacedVectorIndexed()) return false;
1507 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1510 bool isVecListTwoDByteIndexed() const {
1511 if (!isSingleSpacedVectorIndexed()) return false;
1512 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1515 bool isVecListTwoDHWordIndexed() const {
1516 if (!isSingleSpacedVectorIndexed()) return false;
1517 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1520 bool isVecListTwoQWordIndexed() const {
1521 if (!isDoubleSpacedVectorIndexed()) return false;
1522 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1525 bool isVecListTwoQHWordIndexed() const {
1526 if (!isDoubleSpacedVectorIndexed()) return false;
1527 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1530 bool isVecListTwoDWordIndexed() const {
1531 if (!isSingleSpacedVectorIndexed()) return false;
1532 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1535 bool isVecListThreeDByteIndexed() const {
1536 if (!isSingleSpacedVectorIndexed()) return false;
1537 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1540 bool isVecListThreeDHWordIndexed() const {
1541 if (!isSingleSpacedVectorIndexed()) return false;
1542 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1545 bool isVecListThreeQWordIndexed() const {
1546 if (!isDoubleSpacedVectorIndexed()) return false;
1547 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1550 bool isVecListThreeQHWordIndexed() const {
1551 if (!isDoubleSpacedVectorIndexed()) return false;
1552 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1555 bool isVecListThreeDWordIndexed() const {
1556 if (!isSingleSpacedVectorIndexed()) return false;
1557 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1560 bool isVecListFourDByteIndexed() const {
1561 if (!isSingleSpacedVectorIndexed()) return false;
1562 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1565 bool isVecListFourDHWordIndexed() const {
1566 if (!isSingleSpacedVectorIndexed()) return false;
1567 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1570 bool isVecListFourQWordIndexed() const {
1571 if (!isDoubleSpacedVectorIndexed()) return false;
1572 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1575 bool isVecListFourQHWordIndexed() const {
1576 if (!isDoubleSpacedVectorIndexed()) return false;
1577 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1580 bool isVecListFourDWordIndexed() const {
1581 if (!isSingleSpacedVectorIndexed()) return false;
1582 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1585 bool isVectorIndex8() const {
1586 if (Kind != k_VectorIndex) return false;
1587 return VectorIndex.Val < 8;
1589 bool isVectorIndex16() const {
1590 if (Kind != k_VectorIndex) return false;
1591 return VectorIndex.Val < 4;
1593 bool isVectorIndex32() const {
1594 if (Kind != k_VectorIndex) return false;
1595 return VectorIndex.Val < 2;
1598 bool isNEONi8splat() const {
1599 if (!isImm()) return false;
1600 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1601 // Must be a constant.
1602 if (!CE) return false;
1603 int64_t Value = CE->getValue();
1604 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1606 return Value >= 0 && Value < 256;
1609 bool isNEONi16splat() const {
1610 if (!isImm()) return false;
1611 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1612 // Must be a constant.
1613 if (!CE) return false;
1614 int64_t Value = CE->getValue();
1615 // i16 value in the range [0,255] or [0x0100, 0xff00]
1616 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1619 bool isNEONi32splat() const {
1620 if (!isImm()) return false;
1621 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1622 // Must be a constant.
1623 if (!CE) return false;
1624 int64_t Value = CE->getValue();
1625 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1626 return (Value >= 0 && Value < 256) ||
1627 (Value >= 0x0100 && Value <= 0xff00) ||
1628 (Value >= 0x010000 && Value <= 0xff0000) ||
1629 (Value >= 0x01000000 && Value <= 0xff000000);
1632 bool isNEONi32vmov() const {
1633 if (!isImm()) return false;
1634 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1635 // Must be a constant.
1636 if (!CE) return false;
1637 int64_t Value = CE->getValue();
1638 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1639 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1640 return (Value >= 0 && Value < 256) ||
1641 (Value >= 0x0100 && Value <= 0xff00) ||
1642 (Value >= 0x010000 && Value <= 0xff0000) ||
1643 (Value >= 0x01000000 && Value <= 0xff000000) ||
1644 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1645 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1647 bool isNEONi32vmovNeg() const {
1648 if (!isImm()) return false;
1649 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1650 // Must be a constant.
1651 if (!CE) return false;
1652 int64_t Value = ~CE->getValue();
1653 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1654 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1655 return (Value >= 0 && Value < 256) ||
1656 (Value >= 0x0100 && Value <= 0xff00) ||
1657 (Value >= 0x010000 && Value <= 0xff0000) ||
1658 (Value >= 0x01000000 && Value <= 0xff000000) ||
1659 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1660 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1663 bool isNEONi64splat() const {
1664 if (!isImm()) return false;
1665 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1666 // Must be a constant.
1667 if (!CE) return false;
1668 uint64_t Value = CE->getValue();
1669 // i64 value with each byte being either 0 or 0xff.
1670 for (unsigned i = 0; i < 8; ++i)
1671 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1675 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1676 // Add as immediates when possible. Null MCExpr = 0.
1678 Inst.addOperand(MCOperand::CreateImm(0));
1679 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1680 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1682 Inst.addOperand(MCOperand::CreateExpr(Expr));
1685 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1686 assert(N == 2 && "Invalid number of operands!");
1687 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1688 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1689 Inst.addOperand(MCOperand::CreateReg(RegNum));
1692 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1693 assert(N == 1 && "Invalid number of operands!");
1694 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1697 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1698 assert(N == 1 && "Invalid number of operands!");
1699 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1702 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1703 assert(N == 1 && "Invalid number of operands!");
1704 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1707 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1708 assert(N == 1 && "Invalid number of operands!");
1709 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1712 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1713 assert(N == 1 && "Invalid number of operands!");
1714 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1717 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1718 assert(N == 1 && "Invalid number of operands!");
1719 Inst.addOperand(MCOperand::CreateReg(getReg()));
1722 void addRegOperands(MCInst &Inst, unsigned N) const {
1723 assert(N == 1 && "Invalid number of operands!");
1724 Inst.addOperand(MCOperand::CreateReg(getReg()));
1727 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1728 assert(N == 3 && "Invalid number of operands!");
1729 assert(isRegShiftedReg() &&
1730 "addRegShiftedRegOperands() on non-RegShiftedReg!");
1731 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1732 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1733 Inst.addOperand(MCOperand::CreateImm(
1734 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1737 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1738 assert(N == 2 && "Invalid number of operands!");
1739 assert(isRegShiftedImm() &&
1740 "addRegShiftedImmOperands() on non-RegShiftedImm!");
1741 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1742 // Shift of #32 is encoded as 0 where permitted
1743 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1744 Inst.addOperand(MCOperand::CreateImm(
1745 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1748 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1749 assert(N == 1 && "Invalid number of operands!");
1750 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1754 void addRegListOperands(MCInst &Inst, unsigned N) const {
1755 assert(N == 1 && "Invalid number of operands!");
1756 const SmallVectorImpl<unsigned> &RegList = getRegList();
1757 for (SmallVectorImpl<unsigned>::const_iterator
1758 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1759 Inst.addOperand(MCOperand::CreateReg(*I));
1762 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1763 addRegListOperands(Inst, N);
1766 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1767 addRegListOperands(Inst, N);
1770 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1771 assert(N == 1 && "Invalid number of operands!");
1772 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1773 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1776 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1777 assert(N == 1 && "Invalid number of operands!");
1778 // Munge the lsb/width into a bitfield mask.
1779 unsigned lsb = Bitfield.LSB;
1780 unsigned width = Bitfield.Width;
1781 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1782 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1783 (32 - (lsb + width)));
1784 Inst.addOperand(MCOperand::CreateImm(Mask));
1787 void addImmOperands(MCInst &Inst, unsigned N) const {
1788 assert(N == 1 && "Invalid number of operands!");
1789 addExpr(Inst, getImm());
1792 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1793 assert(N == 1 && "Invalid number of operands!");
1794 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1795 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1798 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1799 assert(N == 1 && "Invalid number of operands!");
1800 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1801 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1804 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1805 assert(N == 1 && "Invalid number of operands!");
1806 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1807 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1808 Inst.addOperand(MCOperand::CreateImm(Val));
1811 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1812 assert(N == 1 && "Invalid number of operands!");
1813 // FIXME: We really want to scale the value here, but the LDRD/STRD
1814 // instruction don't encode operands that way yet.
1815 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1816 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1819 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1820 assert(N == 1 && "Invalid number of operands!");
1821 // The immediate is scaled by four in the encoding and is stored
1822 // in the MCInst as such. Lop off the low two bits here.
1823 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1824 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1827 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1828 assert(N == 1 && "Invalid number of operands!");
1829 // The immediate is scaled by four in the encoding and is stored
1830 // in the MCInst as such. Lop off the low two bits here.
1831 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1832 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1835 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1836 assert(N == 1 && "Invalid number of operands!");
1837 // The immediate is scaled by four in the encoding and is stored
1838 // in the MCInst as such. Lop off the low two bits here.
1839 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1840 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1843 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1844 assert(N == 1 && "Invalid number of operands!");
1845 // The constant encodes as the immediate-1, and we store in the instruction
1846 // the bits as encoded, so subtract off one here.
1847 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1848 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1851 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1852 assert(N == 1 && "Invalid number of operands!");
1853 // The constant encodes as the immediate-1, and we store in the instruction
1854 // the bits as encoded, so subtract off one here.
1855 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1856 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1859 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1860 assert(N == 1 && "Invalid number of operands!");
1861 // The constant encodes as the immediate, except for 32, which encodes as
1863 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1864 unsigned Imm = CE->getValue();
1865 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1868 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1869 assert(N == 1 && "Invalid number of operands!");
1870 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1871 // the instruction as well.
1872 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1873 int Val = CE->getValue();
1874 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1877 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1878 assert(N == 1 && "Invalid number of operands!");
1879 // The operand is actually a t2_so_imm, but we have its bitwise
1880 // negation in the assembly source, so twiddle it here.
1881 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1882 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1885 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1886 assert(N == 1 && "Invalid number of operands!");
1887 // The operand is actually a t2_so_imm, but we have its
1888 // negation in the assembly source, so twiddle it here.
1889 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1890 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1893 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1894 assert(N == 1 && "Invalid number of operands!");
1895 // The operand is actually an imm0_4095, but we have its
1896 // negation in the assembly source, so twiddle it here.
1897 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1898 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1901 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1902 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1903 Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
1907 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1908 assert(SR && "Unknown value type!");
1909 Inst.addOperand(MCOperand::CreateExpr(SR));
1912 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
1913 assert(N == 1 && "Invalid number of operands!");
1915 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1917 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1921 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1922 assert(SR && "Unknown value type!");
1923 Inst.addOperand(MCOperand::CreateExpr(SR));
1927 assert(isMem() && "Unknown value type!");
1928 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
1929 Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
1932 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1933 assert(N == 1 && "Invalid number of operands!");
1934 // The operand is actually a so_imm, but we have its bitwise
1935 // negation in the assembly source, so twiddle it here.
1936 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1937 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1940 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1941 assert(N == 1 && "Invalid number of operands!");
1942 // The operand is actually a so_imm, but we have its
1943 // negation in the assembly source, so twiddle it here.
1944 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1945 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1948 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1949 assert(N == 1 && "Invalid number of operands!");
1950 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1953 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
1954 assert(N == 1 && "Invalid number of operands!");
1955 Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
1958 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1959 assert(N == 1 && "Invalid number of operands!");
1960 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1963 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1964 assert(N == 1 && "Invalid number of operands!");
1965 int32_t Imm = Memory.OffsetImm->getValue();
1966 Inst.addOperand(MCOperand::CreateImm(Imm));
1969 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1970 assert(N == 1 && "Invalid number of operands!");
1971 assert(isImm() && "Not an immediate!");
1973 // If we have an immediate that's not a constant, treat it as a label
1974 // reference needing a fixup.
1975 if (!isa<MCConstantExpr>(getImm())) {
1976 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1980 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1981 int Val = CE->getValue();
1982 Inst.addOperand(MCOperand::CreateImm(Val));
1985 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1986 assert(N == 2 && "Invalid number of operands!");
1987 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1988 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1991 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1992 assert(N == 3 && "Invalid number of operands!");
1993 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1994 if (!Memory.OffsetRegNum) {
1995 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1996 // Special case for #-0
1997 if (Val == INT32_MIN) Val = 0;
1998 if (Val < 0) Val = -Val;
1999 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2001 // For register offset, we encode the shift type and negation flag
2003 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2004 Memory.ShiftImm, Memory.ShiftType);
2006 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2007 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2008 Inst.addOperand(MCOperand::CreateImm(Val));
2011 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2012 assert(N == 2 && "Invalid number of operands!");
2013 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2014 assert(CE && "non-constant AM2OffsetImm operand!");
2015 int32_t Val = CE->getValue();
2016 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2017 // Special case for #-0
2018 if (Val == INT32_MIN) Val = 0;
2019 if (Val < 0) Val = -Val;
2020 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2021 Inst.addOperand(MCOperand::CreateReg(0));
2022 Inst.addOperand(MCOperand::CreateImm(Val));
2025 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2026 assert(N == 3 && "Invalid number of operands!");
2027 // If we have an immediate that's not a constant, treat it as a label
2028 // reference needing a fixup. If it is a constant, it's something else
2029 // and we reject it.
2031 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2032 Inst.addOperand(MCOperand::CreateReg(0));
2033 Inst.addOperand(MCOperand::CreateImm(0));
2037 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2038 if (!Memory.OffsetRegNum) {
2039 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2040 // Special case for #-0
2041 if (Val == INT32_MIN) Val = 0;
2042 if (Val < 0) Val = -Val;
2043 Val = ARM_AM::getAM3Opc(AddSub, Val);
2045 // For register offset, we encode the shift type and negation flag
2047 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
2049 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2050 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2051 Inst.addOperand(MCOperand::CreateImm(Val));
2054 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
2055 assert(N == 2 && "Invalid number of operands!");
2056 if (Kind == k_PostIndexRegister) {
2058 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
2059 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2060 Inst.addOperand(MCOperand::CreateImm(Val));
2065 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
2066 int32_t Val = CE->getValue();
2067 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2068 // Special case for #-0
2069 if (Val == INT32_MIN) Val = 0;
2070 if (Val < 0) Val = -Val;
2071 Val = ARM_AM::getAM3Opc(AddSub, Val);
2072 Inst.addOperand(MCOperand::CreateReg(0));
2073 Inst.addOperand(MCOperand::CreateImm(Val));
2076 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2077 assert(N == 2 && "Invalid number of operands!");
2078 // If we have an immediate that's not a constant, treat it as a label
2079 // reference needing a fixup. If it is a constant, it's something else
2080 // and we reject it.
2082 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2083 Inst.addOperand(MCOperand::CreateImm(0));
2087 // The lower two bits are always zero and as such are not encoded.
2088 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2089 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2090 // Special case for #-0
2091 if (Val == INT32_MIN) Val = 0;
2092 if (Val < 0) Val = -Val;
2093 Val = ARM_AM::getAM5Opc(AddSub, Val);
2094 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2095 Inst.addOperand(MCOperand::CreateImm(Val));
2098 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2099 assert(N == 2 && "Invalid number of operands!");
2100 // If we have an immediate that's not a constant, treat it as a label
2101 // reference needing a fixup. If it is a constant, it's something else
2102 // and we reject it.
2104 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2105 Inst.addOperand(MCOperand::CreateImm(0));
2109 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2110 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2111 Inst.addOperand(MCOperand::CreateImm(Val));
2114 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2115 assert(N == 2 && "Invalid number of operands!");
2116 // The lower two bits are always zero and as such are not encoded.
2117 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2118 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2119 Inst.addOperand(MCOperand::CreateImm(Val));
2122 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2123 assert(N == 2 && "Invalid number of operands!");
2124 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2125 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2126 Inst.addOperand(MCOperand::CreateImm(Val));
2129 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2130 addMemImm8OffsetOperands(Inst, N);
2133 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2134 addMemImm8OffsetOperands(Inst, N);
2137 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2138 assert(N == 2 && "Invalid number of operands!");
2139 // If this is an immediate, it's a label reference.
2141 addExpr(Inst, getImm());
2142 Inst.addOperand(MCOperand::CreateImm(0));
2146 // Otherwise, it's a normal memory reg+offset.
2147 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2148 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2149 Inst.addOperand(MCOperand::CreateImm(Val));
2152 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2153 assert(N == 2 && "Invalid number of operands!");
2154 // If this is an immediate, it's a label reference.
2156 addExpr(Inst, getImm());
2157 Inst.addOperand(MCOperand::CreateImm(0));
2161 // Otherwise, it's a normal memory reg+offset.
2162 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2163 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2164 Inst.addOperand(MCOperand::CreateImm(Val));
2167 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2168 assert(N == 2 && "Invalid number of operands!");
2169 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2170 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2173 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2174 assert(N == 2 && "Invalid number of operands!");
2175 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2176 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2179 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2180 assert(N == 3 && "Invalid number of operands!");
2182 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2183 Memory.ShiftImm, Memory.ShiftType);
2184 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2185 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2186 Inst.addOperand(MCOperand::CreateImm(Val));
2189 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2190 assert(N == 3 && "Invalid number of operands!");
2191 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2192 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2193 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
2196 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2197 assert(N == 2 && "Invalid number of operands!");
2198 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2199 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2202 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2203 assert(N == 2 && "Invalid number of operands!");
2204 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2205 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2206 Inst.addOperand(MCOperand::CreateImm(Val));
2209 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2210 assert(N == 2 && "Invalid number of operands!");
2211 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2212 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2213 Inst.addOperand(MCOperand::CreateImm(Val));
2216 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2217 assert(N == 2 && "Invalid number of operands!");
2218 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2219 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2220 Inst.addOperand(MCOperand::CreateImm(Val));
2223 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2224 assert(N == 2 && "Invalid number of operands!");
2225 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2226 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2227 Inst.addOperand(MCOperand::CreateImm(Val));
2230 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2231 assert(N == 1 && "Invalid number of operands!");
2232 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2233 assert(CE && "non-constant post-idx-imm8 operand!");
2234 int Imm = CE->getValue();
2235 bool isAdd = Imm >= 0;
2236 if (Imm == INT32_MIN) Imm = 0;
2237 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2238 Inst.addOperand(MCOperand::CreateImm(Imm));
2241 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2242 assert(N == 1 && "Invalid number of operands!");
2243 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2244 assert(CE && "non-constant post-idx-imm8s4 operand!");
2245 int Imm = CE->getValue();
2246 bool isAdd = Imm >= 0;
2247 if (Imm == INT32_MIN) Imm = 0;
2248 // Immediate is scaled by 4.
2249 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2250 Inst.addOperand(MCOperand::CreateImm(Imm));
2253 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2254 assert(N == 2 && "Invalid number of operands!");
2255 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2256 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2259 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2260 assert(N == 2 && "Invalid number of operands!");
2261 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2262 // The sign, shift type, and shift amount are encoded in a single operand
2263 // using the AM2 encoding helpers.
2264 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2265 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2266 PostIdxReg.ShiftTy);
2267 Inst.addOperand(MCOperand::CreateImm(Imm));
2270 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2271 assert(N == 1 && "Invalid number of operands!");
2272 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2275 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2276 assert(N == 1 && "Invalid number of operands!");
2277 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2280 void addVecListOperands(MCInst &Inst, unsigned N) const {
2281 assert(N == 1 && "Invalid number of operands!");
2282 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2285 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2286 assert(N == 2 && "Invalid number of operands!");
2287 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2288 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2291 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2292 assert(N == 1 && "Invalid number of operands!");
2293 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2296 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2297 assert(N == 1 && "Invalid number of operands!");
2298 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2301 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2302 assert(N == 1 && "Invalid number of operands!");
2303 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2306 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2307 assert(N == 1 && "Invalid number of operands!");
2308 // The immediate encodes the type of constant as well as the value.
2309 // Mask in that this is an i8 splat.
2310 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2311 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2314 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2315 assert(N == 1 && "Invalid number of operands!");
2316 // The immediate encodes the type of constant as well as the value.
2317 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2318 unsigned Value = CE->getValue();
2320 Value = (Value >> 8) | 0xa00;
2323 Inst.addOperand(MCOperand::CreateImm(Value));
2326 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2327 assert(N == 1 && "Invalid number of operands!");
2328 // The immediate encodes the type of constant as well as the value.
2329 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2330 unsigned Value = CE->getValue();
2331 if (Value >= 256 && Value <= 0xff00)
2332 Value = (Value >> 8) | 0x200;
2333 else if (Value > 0xffff && Value <= 0xff0000)
2334 Value = (Value >> 16) | 0x400;
2335 else if (Value > 0xffffff)
2336 Value = (Value >> 24) | 0x600;
2337 Inst.addOperand(MCOperand::CreateImm(Value));
2340 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2341 assert(N == 1 && "Invalid number of operands!");
2342 // The immediate encodes the type of constant as well as the value.
2343 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2344 unsigned Value = CE->getValue();
2345 if (Value >= 256 && Value <= 0xffff)
2346 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2347 else if (Value > 0xffff && Value <= 0xffffff)
2348 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2349 else if (Value > 0xffffff)
2350 Value = (Value >> 24) | 0x600;
2351 Inst.addOperand(MCOperand::CreateImm(Value));
2354 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2355 assert(N == 1 && "Invalid number of operands!");
2356 // The immediate encodes the type of constant as well as the value.
2357 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2358 unsigned Value = ~CE->getValue();
2359 if (Value >= 256 && Value <= 0xffff)
2360 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2361 else if (Value > 0xffff && Value <= 0xffffff)
2362 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2363 else if (Value > 0xffffff)
2364 Value = (Value >> 24) | 0x600;
2365 Inst.addOperand(MCOperand::CreateImm(Value));
2368 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2369 assert(N == 1 && "Invalid number of operands!");
2370 // The immediate encodes the type of constant as well as the value.
2371 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2372 uint64_t Value = CE->getValue();
2374 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2375 Imm |= (Value & 1) << i;
2377 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2380 virtual void print(raw_ostream &OS) const;
2382 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2383 ARMOperand *Op = new ARMOperand(k_ITCondMask);
2384 Op->ITMask.Mask = Mask;
2390 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2391 ARMOperand *Op = new ARMOperand(k_CondCode);
2398 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2399 ARMOperand *Op = new ARMOperand(k_CoprocNum);
2400 Op->Cop.Val = CopVal;
2406 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2407 ARMOperand *Op = new ARMOperand(k_CoprocReg);
2408 Op->Cop.Val = CopVal;
2414 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2415 ARMOperand *Op = new ARMOperand(k_CoprocOption);
2422 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2423 ARMOperand *Op = new ARMOperand(k_CCOut);
2424 Op->Reg.RegNum = RegNum;
2430 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2431 ARMOperand *Op = new ARMOperand(k_Token);
2432 Op->Tok.Data = Str.data();
2433 Op->Tok.Length = Str.size();
2439 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2440 ARMOperand *Op = new ARMOperand(k_Register);
2441 Op->Reg.RegNum = RegNum;
2447 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2452 ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2453 Op->RegShiftedReg.ShiftTy = ShTy;
2454 Op->RegShiftedReg.SrcReg = SrcReg;
2455 Op->RegShiftedReg.ShiftReg = ShiftReg;
2456 Op->RegShiftedReg.ShiftImm = ShiftImm;
2462 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2466 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2467 Op->RegShiftedImm.ShiftTy = ShTy;
2468 Op->RegShiftedImm.SrcReg = SrcReg;
2469 Op->RegShiftedImm.ShiftImm = ShiftImm;
2475 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2477 ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2478 Op->ShifterImm.isASR = isASR;
2479 Op->ShifterImm.Imm = Imm;
2485 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2486 ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2487 Op->RotImm.Imm = Imm;
2493 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2495 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2496 Op->Bitfield.LSB = LSB;
2497 Op->Bitfield.Width = Width;
2504 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned> > &Regs,
2505 SMLoc StartLoc, SMLoc EndLoc) {
2506 assert (Regs.size() > 0 && "RegList contains no registers?");
2507 KindTy Kind = k_RegisterList;
2509 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2510 Kind = k_DPRRegisterList;
2511 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2512 contains(Regs.front().second))
2513 Kind = k_SPRRegisterList;
2515 // Sort based on the register encoding values.
2516 array_pod_sort(Regs.begin(), Regs.end());
2518 ARMOperand *Op = new ARMOperand(Kind);
2519 for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2520 I = Regs.begin(), E = Regs.end(); I != E; ++I)
2521 Op->Registers.push_back(I->second);
2522 Op->StartLoc = StartLoc;
2523 Op->EndLoc = EndLoc;
2527 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2528 bool isDoubleSpaced, SMLoc S, SMLoc E) {
2529 ARMOperand *Op = new ARMOperand(k_VectorList);
2530 Op->VectorList.RegNum = RegNum;
2531 Op->VectorList.Count = Count;
2532 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2538 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2539 bool isDoubleSpaced,
2541 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2542 Op->VectorList.RegNum = RegNum;
2543 Op->VectorList.Count = Count;
2544 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2550 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2552 bool isDoubleSpaced,
2554 ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2555 Op->VectorList.RegNum = RegNum;
2556 Op->VectorList.Count = Count;
2557 Op->VectorList.LaneIndex = Index;
2558 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2564 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2566 ARMOperand *Op = new ARMOperand(k_VectorIndex);
2567 Op->VectorIndex.Val = Idx;
2573 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2574 ARMOperand *Op = new ARMOperand(k_Immediate);
2581 static ARMOperand *CreateMem(unsigned BaseRegNum,
2582 const MCConstantExpr *OffsetImm,
2583 unsigned OffsetRegNum,
2584 ARM_AM::ShiftOpc ShiftType,
2589 ARMOperand *Op = new ARMOperand(k_Memory);
2590 Op->Memory.BaseRegNum = BaseRegNum;
2591 Op->Memory.OffsetImm = OffsetImm;
2592 Op->Memory.OffsetRegNum = OffsetRegNum;
2593 Op->Memory.ShiftType = ShiftType;
2594 Op->Memory.ShiftImm = ShiftImm;
2595 Op->Memory.Alignment = Alignment;
2596 Op->Memory.isNegative = isNegative;
2602 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2603 ARM_AM::ShiftOpc ShiftTy,
2606 ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2607 Op->PostIdxReg.RegNum = RegNum;
2608 Op->PostIdxReg.isAdd = isAdd;
2609 Op->PostIdxReg.ShiftTy = ShiftTy;
2610 Op->PostIdxReg.ShiftImm = ShiftImm;
2616 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2617 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2618 Op->MBOpt.Val = Opt;
2624 static ARMOperand *CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt,
2626 ARMOperand *Op = new ARMOperand(k_InstSyncBarrierOpt);
2627 Op->ISBOpt.Val = Opt;
2633 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2634 ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2635 Op->IFlags.Val = IFlags;
2641 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2642 ARMOperand *Op = new ARMOperand(k_MSRMask);
2643 Op->MMask.Val = MMask;
2650 } // end anonymous namespace.
2652 void ARMOperand::print(raw_ostream &OS) const {
2655 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2658 OS << "<ccout " << getReg() << ">";
2660 case k_ITCondMask: {
2661 static const char *const MaskStr[] = {
2662 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2663 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2665 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2666 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2670 OS << "<coprocessor number: " << getCoproc() << ">";
2673 OS << "<coprocessor register: " << getCoproc() << ">";
2675 case k_CoprocOption:
2676 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2679 OS << "<mask: " << getMSRMask() << ">";
2682 getImm()->print(OS);
2684 case k_MemBarrierOpt:
2685 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
2687 case k_InstSyncBarrierOpt:
2688 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2692 << " base:" << Memory.BaseRegNum;
2695 case k_PostIndexRegister:
2696 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2697 << PostIdxReg.RegNum;
2698 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2699 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2700 << PostIdxReg.ShiftImm;
2703 case k_ProcIFlags: {
2704 OS << "<ARM_PROC::";
2705 unsigned IFlags = getProcIFlags();
2706 for (int i=2; i >= 0; --i)
2707 if (IFlags & (1 << i))
2708 OS << ARM_PROC::IFlagsToString(1 << i);
2713 OS << "<register " << getReg() << ">";
2715 case k_ShifterImmediate:
2716 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2717 << " #" << ShifterImm.Imm << ">";
2719 case k_ShiftedRegister:
2720 OS << "<so_reg_reg "
2721 << RegShiftedReg.SrcReg << " "
2722 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2723 << " " << RegShiftedReg.ShiftReg << ">";
2725 case k_ShiftedImmediate:
2726 OS << "<so_reg_imm "
2727 << RegShiftedImm.SrcReg << " "
2728 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2729 << " #" << RegShiftedImm.ShiftImm << ">";
2731 case k_RotateImmediate:
2732 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2734 case k_BitfieldDescriptor:
2735 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2736 << ", width: " << Bitfield.Width << ">";
2738 case k_RegisterList:
2739 case k_DPRRegisterList:
2740 case k_SPRRegisterList: {
2741 OS << "<register_list ";
2743 const SmallVectorImpl<unsigned> &RegList = getRegList();
2744 for (SmallVectorImpl<unsigned>::const_iterator
2745 I = RegList.begin(), E = RegList.end(); I != E; ) {
2747 if (++I < E) OS << ", ";
2754 OS << "<vector_list " << VectorList.Count << " * "
2755 << VectorList.RegNum << ">";
2757 case k_VectorListAllLanes:
2758 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2759 << VectorList.RegNum << ">";
2761 case k_VectorListIndexed:
2762 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2763 << VectorList.Count << " * " << VectorList.RegNum << ">";
2766 OS << "'" << getToken() << "'";
2769 OS << "<vectorindex " << getVectorIndex() << ">";
2774 /// @name Auto-generated Match Functions
2777 static unsigned MatchRegisterName(StringRef Name);
2781 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2782 SMLoc &StartLoc, SMLoc &EndLoc) {
2783 StartLoc = Parser.getTok().getLoc();
2784 EndLoc = Parser.getTok().getEndLoc();
2785 RegNo = tryParseRegister();
2787 return (RegNo == (unsigned)-1);
2790 /// Try to parse a register name. The token must be an Identifier when called,
2791 /// and if it is a register name the token is eaten and the register number is
2792 /// returned. Otherwise return -1.
2794 int ARMAsmParser::tryParseRegister() {
2795 const AsmToken &Tok = Parser.getTok();
2796 if (Tok.isNot(AsmToken::Identifier)) return -1;
2798 std::string lowerCase = Tok.getString().lower();
2799 unsigned RegNum = MatchRegisterName(lowerCase);
2801 RegNum = StringSwitch<unsigned>(lowerCase)
2802 .Case("r13", ARM::SP)
2803 .Case("r14", ARM::LR)
2804 .Case("r15", ARM::PC)
2805 .Case("ip", ARM::R12)
2806 // Additional register name aliases for 'gas' compatibility.
2807 .Case("a1", ARM::R0)
2808 .Case("a2", ARM::R1)
2809 .Case("a3", ARM::R2)
2810 .Case("a4", ARM::R3)
2811 .Case("v1", ARM::R4)
2812 .Case("v2", ARM::R5)
2813 .Case("v3", ARM::R6)
2814 .Case("v4", ARM::R7)
2815 .Case("v5", ARM::R8)
2816 .Case("v6", ARM::R9)
2817 .Case("v7", ARM::R10)
2818 .Case("v8", ARM::R11)
2819 .Case("sb", ARM::R9)
2820 .Case("sl", ARM::R10)
2821 .Case("fp", ARM::R11)
2825 // Check for aliases registered via .req. Canonicalize to lower case.
2826 // That's more consistent since register names are case insensitive, and
2827 // it's how the original entry was passed in from MC/MCParser/AsmParser.
2828 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2829 // If no match, return failure.
2830 if (Entry == RegisterReqs.end())
2832 Parser.Lex(); // Eat identifier token.
2833 return Entry->getValue();
2836 Parser.Lex(); // Eat identifier token.
2841 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
2842 // If a recoverable error occurs, return 1. If an irrecoverable error
2843 // occurs, return -1. An irrecoverable error is one where tokens have been
2844 // consumed in the process of trying to parse the shifter (i.e., when it is
2845 // indeed a shifter operand, but malformed).
2846 int ARMAsmParser::tryParseShiftRegister(
2847 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2848 SMLoc S = Parser.getTok().getLoc();
2849 const AsmToken &Tok = Parser.getTok();
2850 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2852 std::string lowerCase = Tok.getString().lower();
2853 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2854 .Case("asl", ARM_AM::lsl)
2855 .Case("lsl", ARM_AM::lsl)
2856 .Case("lsr", ARM_AM::lsr)
2857 .Case("asr", ARM_AM::asr)
2858 .Case("ror", ARM_AM::ror)
2859 .Case("rrx", ARM_AM::rrx)
2860 .Default(ARM_AM::no_shift);
2862 if (ShiftTy == ARM_AM::no_shift)
2865 Parser.Lex(); // Eat the operator.
2867 // The source register for the shift has already been added to the
2868 // operand list, so we need to pop it off and combine it into the shifted
2869 // register operand instead.
2870 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2871 if (!PrevOp->isReg())
2872 return Error(PrevOp->getStartLoc(), "shift must be of a register");
2873 int SrcReg = PrevOp->getReg();
2878 if (ShiftTy == ARM_AM::rrx) {
2879 // RRX Doesn't have an explicit shift amount. The encoder expects
2880 // the shift register to be the same as the source register. Seems odd,
2884 // Figure out if this is shifted by a constant or a register (for non-RRX).
2885 if (Parser.getTok().is(AsmToken::Hash) ||
2886 Parser.getTok().is(AsmToken::Dollar)) {
2887 Parser.Lex(); // Eat hash.
2888 SMLoc ImmLoc = Parser.getTok().getLoc();
2889 const MCExpr *ShiftExpr = 0;
2890 if (getParser().parseExpression(ShiftExpr, EndLoc)) {
2891 Error(ImmLoc, "invalid immediate shift value");
2894 // The expression must be evaluatable as an immediate.
2895 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2897 Error(ImmLoc, "invalid immediate shift value");
2900 // Range check the immediate.
2901 // lsl, ror: 0 <= imm <= 31
2902 // lsr, asr: 0 <= imm <= 32
2903 Imm = CE->getValue();
2905 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2906 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2907 Error(ImmLoc, "immediate shift value out of range");
2910 // shift by zero is a nop. Always send it through as lsl.
2911 // ('as' compatibility)
2913 ShiftTy = ARM_AM::lsl;
2914 } else if (Parser.getTok().is(AsmToken::Identifier)) {
2915 SMLoc L = Parser.getTok().getLoc();
2916 EndLoc = Parser.getTok().getEndLoc();
2917 ShiftReg = tryParseRegister();
2918 if (ShiftReg == -1) {
2919 Error (L, "expected immediate or register in shift operand");
2923 Error (Parser.getTok().getLoc(),
2924 "expected immediate or register in shift operand");
2929 if (ShiftReg && ShiftTy != ARM_AM::rrx)
2930 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2934 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2941 /// Try to parse a register name. The token must be an Identifier when called.
2942 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
2943 /// if there is a "writeback". 'true' if it's not a register.
2945 /// TODO this is likely to change to allow different register types and or to
2946 /// parse for a specific register type.
2948 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2949 const AsmToken &RegTok = Parser.getTok();
2950 int RegNo = tryParseRegister();
2954 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
2955 RegTok.getEndLoc()));
2957 const AsmToken &ExclaimTok = Parser.getTok();
2958 if (ExclaimTok.is(AsmToken::Exclaim)) {
2959 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2960 ExclaimTok.getLoc()));
2961 Parser.Lex(); // Eat exclaim token
2965 // Also check for an index operand. This is only legal for vector registers,
2966 // but that'll get caught OK in operand matching, so we don't need to
2967 // explicitly filter everything else out here.
2968 if (Parser.getTok().is(AsmToken::LBrac)) {
2969 SMLoc SIdx = Parser.getTok().getLoc();
2970 Parser.Lex(); // Eat left bracket token.
2972 const MCExpr *ImmVal;
2973 if (getParser().parseExpression(ImmVal))
2975 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2977 return TokError("immediate value expected for vector index");
2979 if (Parser.getTok().isNot(AsmToken::RBrac))
2980 return Error(Parser.getTok().getLoc(), "']' expected");
2982 SMLoc E = Parser.getTok().getEndLoc();
2983 Parser.Lex(); // Eat right bracket token.
2985 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2993 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
2994 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2996 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2997 // Use the same layout as the tablegen'erated register name matcher. Ugly,
2999 switch (Name.size()) {
3002 if (Name[0] != CoprocOp)
3018 if (Name[0] != CoprocOp || Name[1] != '1')
3022 // p10 and p11 are invalid for coproc instructions (reserved for FP/NEON)
3023 case '0': return CoprocOp == 'p'? -1: 10;
3024 case '1': return CoprocOp == 'p'? -1: 11;
3025 case '2': return 12;
3026 case '3': return 13;
3027 case '4': return 14;
3028 case '5': return 15;
3033 /// parseITCondCode - Try to parse a condition code for an IT instruction.
3034 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3035 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3036 SMLoc S = Parser.getTok().getLoc();
3037 const AsmToken &Tok = Parser.getTok();
3038 if (!Tok.is(AsmToken::Identifier))
3039 return MatchOperand_NoMatch;
3040 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
3041 .Case("eq", ARMCC::EQ)
3042 .Case("ne", ARMCC::NE)
3043 .Case("hs", ARMCC::HS)
3044 .Case("cs", ARMCC::HS)
3045 .Case("lo", ARMCC::LO)
3046 .Case("cc", ARMCC::LO)
3047 .Case("mi", ARMCC::MI)
3048 .Case("pl", ARMCC::PL)
3049 .Case("vs", ARMCC::VS)
3050 .Case("vc", ARMCC::VC)
3051 .Case("hi", ARMCC::HI)
3052 .Case("ls", ARMCC::LS)
3053 .Case("ge", ARMCC::GE)
3054 .Case("lt", ARMCC::LT)
3055 .Case("gt", ARMCC::GT)
3056 .Case("le", ARMCC::LE)
3057 .Case("al", ARMCC::AL)
3060 return MatchOperand_NoMatch;
3061 Parser.Lex(); // Eat the token.
3063 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
3065 return MatchOperand_Success;
3068 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
3069 /// token must be an Identifier when called, and if it is a coprocessor
3070 /// number, the token is eaten and the operand is added to the operand list.
3071 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3072 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3073 SMLoc S = Parser.getTok().getLoc();
3074 const AsmToken &Tok = Parser.getTok();
3075 if (Tok.isNot(AsmToken::Identifier))
3076 return MatchOperand_NoMatch;
3078 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
3080 return MatchOperand_NoMatch;
3082 Parser.Lex(); // Eat identifier token.
3083 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
3084 return MatchOperand_Success;
3087 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
3088 /// token must be an Identifier when called, and if it is a coprocessor
3089 /// number, the token is eaten and the operand is added to the operand list.
3090 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3091 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3092 SMLoc S = Parser.getTok().getLoc();
3093 const AsmToken &Tok = Parser.getTok();
3094 if (Tok.isNot(AsmToken::Identifier))
3095 return MatchOperand_NoMatch;
3097 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
3099 return MatchOperand_NoMatch;
3101 Parser.Lex(); // Eat identifier token.
3102 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
3103 return MatchOperand_Success;
3106 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
3107 /// coproc_option : '{' imm0_255 '}'
3108 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3109 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3110 SMLoc S = Parser.getTok().getLoc();
3112 // If this isn't a '{', this isn't a coprocessor immediate operand.
3113 if (Parser.getTok().isNot(AsmToken::LCurly))
3114 return MatchOperand_NoMatch;
3115 Parser.Lex(); // Eat the '{'
3118 SMLoc Loc = Parser.getTok().getLoc();
3119 if (getParser().parseExpression(Expr)) {
3120 Error(Loc, "illegal expression");
3121 return MatchOperand_ParseFail;
3123 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3124 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
3125 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
3126 return MatchOperand_ParseFail;
3128 int Val = CE->getValue();
3130 // Check for and consume the closing '}'
3131 if (Parser.getTok().isNot(AsmToken::RCurly))
3132 return MatchOperand_ParseFail;
3133 SMLoc E = Parser.getTok().getEndLoc();
3134 Parser.Lex(); // Eat the '}'
3136 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
3137 return MatchOperand_Success;
3140 // For register list parsing, we need to map from raw GPR register numbering
3141 // to the enumeration values. The enumeration values aren't sorted by
3142 // register number due to our using "sp", "lr" and "pc" as canonical names.
3143 static unsigned getNextRegister(unsigned Reg) {
3144 // If this is a GPR, we need to do it manually, otherwise we can rely
3145 // on the sort ordering of the enumeration since the other reg-classes
3147 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3150 default: llvm_unreachable("Invalid GPR number!");
3151 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
3152 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
3153 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
3154 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
3155 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
3156 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3157 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
3158 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
3162 // Return the low-subreg of a given Q register.
3163 static unsigned getDRegFromQReg(unsigned QReg) {
3165 default: llvm_unreachable("expected a Q register!");
3166 case ARM::Q0: return ARM::D0;
3167 case ARM::Q1: return ARM::D2;
3168 case ARM::Q2: return ARM::D4;
3169 case ARM::Q3: return ARM::D6;
3170 case ARM::Q4: return ARM::D8;
3171 case ARM::Q5: return ARM::D10;
3172 case ARM::Q6: return ARM::D12;
3173 case ARM::Q7: return ARM::D14;
3174 case ARM::Q8: return ARM::D16;
3175 case ARM::Q9: return ARM::D18;
3176 case ARM::Q10: return ARM::D20;
3177 case ARM::Q11: return ARM::D22;
3178 case ARM::Q12: return ARM::D24;
3179 case ARM::Q13: return ARM::D26;
3180 case ARM::Q14: return ARM::D28;
3181 case ARM::Q15: return ARM::D30;
3185 /// Parse a register list.
3187 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3188 assert(Parser.getTok().is(AsmToken::LCurly) &&
3189 "Token is not a Left Curly Brace");
3190 SMLoc S = Parser.getTok().getLoc();
3191 Parser.Lex(); // Eat '{' token.
3192 SMLoc RegLoc = Parser.getTok().getLoc();
3194 // Check the first register in the list to see what register class
3195 // this is a list of.
3196 int Reg = tryParseRegister();
3198 return Error(RegLoc, "register expected");
3200 // The reglist instructions have at most 16 registers, so reserve
3201 // space for that many.
3203 SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3205 // Allow Q regs and just interpret them as the two D sub-registers.
3206 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3207 Reg = getDRegFromQReg(Reg);
3208 EReg = MRI->getEncodingValue(Reg);
3209 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3212 const MCRegisterClass *RC;
3213 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3214 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3215 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3216 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3217 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3218 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3220 return Error(RegLoc, "invalid register in register list");
3222 // Store the register.
3223 EReg = MRI->getEncodingValue(Reg);
3224 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3226 // This starts immediately after the first register token in the list,
3227 // so we can see either a comma or a minus (range separator) as a legal
3229 while (Parser.getTok().is(AsmToken::Comma) ||
3230 Parser.getTok().is(AsmToken::Minus)) {
3231 if (Parser.getTok().is(AsmToken::Minus)) {
3232 Parser.Lex(); // Eat the minus.
3233 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3234 int EndReg = tryParseRegister();
3236 return Error(AfterMinusLoc, "register expected");
3237 // Allow Q regs and just interpret them as the two D sub-registers.
3238 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3239 EndReg = getDRegFromQReg(EndReg) + 1;
3240 // If the register is the same as the start reg, there's nothing
3244 // The register must be in the same register class as the first.
3245 if (!RC->contains(EndReg))
3246 return Error(AfterMinusLoc, "invalid register in register list");
3247 // Ranges must go from low to high.
3248 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3249 return Error(AfterMinusLoc, "bad range in register list");
3251 // Add all the registers in the range to the register list.
3252 while (Reg != EndReg) {
3253 Reg = getNextRegister(Reg);
3254 EReg = MRI->getEncodingValue(Reg);
3255 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3259 Parser.Lex(); // Eat the comma.
3260 RegLoc = Parser.getTok().getLoc();
3262 const AsmToken RegTok = Parser.getTok();
3263 Reg = tryParseRegister();
3265 return Error(RegLoc, "register expected");
3266 // Allow Q regs and just interpret them as the two D sub-registers.
3267 bool isQReg = false;
3268 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3269 Reg = getDRegFromQReg(Reg);
3272 // The register must be in the same register class as the first.
3273 if (!RC->contains(Reg))
3274 return Error(RegLoc, "invalid register in register list");
3275 // List must be monotonically increasing.
3276 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3277 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3278 Warning(RegLoc, "register list not in ascending order");
3280 return Error(RegLoc, "register list not in ascending order");
3282 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3283 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3284 ") in register list");
3287 // VFP register lists must also be contiguous.
3288 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3290 return Error(RegLoc, "non-contiguous register range");
3291 EReg = MRI->getEncodingValue(Reg);
3292 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3294 EReg = MRI->getEncodingValue(++Reg);
3295 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3299 if (Parser.getTok().isNot(AsmToken::RCurly))
3300 return Error(Parser.getTok().getLoc(), "'}' expected");
3301 SMLoc E = Parser.getTok().getEndLoc();
3302 Parser.Lex(); // Eat '}' token.
3304 // Push the register list operand.
3305 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3307 // The ARM system instruction variants for LDM/STM have a '^' token here.
3308 if (Parser.getTok().is(AsmToken::Caret)) {
3309 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3310 Parser.Lex(); // Eat '^' token.
3316 // Helper function to parse the lane index for vector lists.
3317 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3318 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3319 Index = 0; // Always return a defined index value.
3320 if (Parser.getTok().is(AsmToken::LBrac)) {
3321 Parser.Lex(); // Eat the '['.
3322 if (Parser.getTok().is(AsmToken::RBrac)) {
3323 // "Dn[]" is the 'all lanes' syntax.
3324 LaneKind = AllLanes;
3325 EndLoc = Parser.getTok().getEndLoc();
3326 Parser.Lex(); // Eat the ']'.
3327 return MatchOperand_Success;
3330 // There's an optional '#' token here. Normally there wouldn't be, but
3331 // inline assemble puts one in, and it's friendly to accept that.
3332 if (Parser.getTok().is(AsmToken::Hash))
3333 Parser.Lex(); // Eat '#' or '$'.
3335 const MCExpr *LaneIndex;
3336 SMLoc Loc = Parser.getTok().getLoc();
3337 if (getParser().parseExpression(LaneIndex)) {
3338 Error(Loc, "illegal expression");
3339 return MatchOperand_ParseFail;
3341 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3343 Error(Loc, "lane index must be empty or an integer");
3344 return MatchOperand_ParseFail;
3346 if (Parser.getTok().isNot(AsmToken::RBrac)) {
3347 Error(Parser.getTok().getLoc(), "']' expected");
3348 return MatchOperand_ParseFail;
3350 EndLoc = Parser.getTok().getEndLoc();
3351 Parser.Lex(); // Eat the ']'.
3352 int64_t Val = CE->getValue();
3354 // FIXME: Make this range check context sensitive for .8, .16, .32.
3355 if (Val < 0 || Val > 7) {
3356 Error(Parser.getTok().getLoc(), "lane index out of range");
3357 return MatchOperand_ParseFail;
3360 LaneKind = IndexedLane;
3361 return MatchOperand_Success;
3364 return MatchOperand_Success;
3367 // parse a vector register list
3368 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3369 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3370 VectorLaneTy LaneKind;
3372 SMLoc S = Parser.getTok().getLoc();
3373 // As an extension (to match gas), support a plain D register or Q register
3374 // (without encosing curly braces) as a single or double entry list,
3376 if (Parser.getTok().is(AsmToken::Identifier)) {
3377 SMLoc E = Parser.getTok().getEndLoc();
3378 int Reg = tryParseRegister();
3380 return MatchOperand_NoMatch;
3381 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3382 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3383 if (Res != MatchOperand_Success)
3387 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3390 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3394 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3399 return MatchOperand_Success;
3401 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3402 Reg = getDRegFromQReg(Reg);
3403 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3404 if (Res != MatchOperand_Success)
3408 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3409 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3410 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3413 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3414 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3415 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3419 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3424 return MatchOperand_Success;
3426 Error(S, "vector register expected");
3427 return MatchOperand_ParseFail;
3430 if (Parser.getTok().isNot(AsmToken::LCurly))
3431 return MatchOperand_NoMatch;
3433 Parser.Lex(); // Eat '{' token.
3434 SMLoc RegLoc = Parser.getTok().getLoc();
3436 int Reg = tryParseRegister();
3438 Error(RegLoc, "register expected");
3439 return MatchOperand_ParseFail;
3443 unsigned FirstReg = Reg;
3444 // The list is of D registers, but we also allow Q regs and just interpret
3445 // them as the two D sub-registers.
3446 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3447 FirstReg = Reg = getDRegFromQReg(Reg);
3448 Spacing = 1; // double-spacing requires explicit D registers, otherwise
3449 // it's ambiguous with four-register single spaced.
3455 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3456 return MatchOperand_ParseFail;
3458 while (Parser.getTok().is(AsmToken::Comma) ||
3459 Parser.getTok().is(AsmToken::Minus)) {
3460 if (Parser.getTok().is(AsmToken::Minus)) {
3462 Spacing = 1; // Register range implies a single spaced list.
3463 else if (Spacing == 2) {
3464 Error(Parser.getTok().getLoc(),
3465 "sequential registers in double spaced list");
3466 return MatchOperand_ParseFail;
3468 Parser.Lex(); // Eat the minus.
3469 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3470 int EndReg = tryParseRegister();
3472 Error(AfterMinusLoc, "register expected");
3473 return MatchOperand_ParseFail;
3475 // Allow Q regs and just interpret them as the two D sub-registers.
3476 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3477 EndReg = getDRegFromQReg(EndReg) + 1;
3478 // If the register is the same as the start reg, there's nothing
3482 // The register must be in the same register class as the first.
3483 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3484 Error(AfterMinusLoc, "invalid register in register list");
3485 return MatchOperand_ParseFail;
3487 // Ranges must go from low to high.
3489 Error(AfterMinusLoc, "bad range in register list");
3490 return MatchOperand_ParseFail;
3492 // Parse the lane specifier if present.
3493 VectorLaneTy NextLaneKind;
3494 unsigned NextLaneIndex;
3495 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3496 MatchOperand_Success)
3497 return MatchOperand_ParseFail;
3498 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3499 Error(AfterMinusLoc, "mismatched lane index in register list");
3500 return MatchOperand_ParseFail;
3503 // Add all the registers in the range to the register list.
3504 Count += EndReg - Reg;
3508 Parser.Lex(); // Eat the comma.
3509 RegLoc = Parser.getTok().getLoc();
3511 Reg = tryParseRegister();
3513 Error(RegLoc, "register expected");
3514 return MatchOperand_ParseFail;
3516 // vector register lists must be contiguous.
3517 // It's OK to use the enumeration values directly here rather, as the
3518 // VFP register classes have the enum sorted properly.
3520 // The list is of D registers, but we also allow Q regs and just interpret
3521 // them as the two D sub-registers.
3522 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3524 Spacing = 1; // Register range implies a single spaced list.
3525 else if (Spacing == 2) {
3527 "invalid register in double-spaced list (must be 'D' register')");
3528 return MatchOperand_ParseFail;
3530 Reg = getDRegFromQReg(Reg);
3531 if (Reg != OldReg + 1) {
3532 Error(RegLoc, "non-contiguous register range");
3533 return MatchOperand_ParseFail;
3537 // Parse the lane specifier if present.
3538 VectorLaneTy NextLaneKind;
3539 unsigned NextLaneIndex;
3540 SMLoc LaneLoc = Parser.getTok().getLoc();
3541 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3542 MatchOperand_Success)
3543 return MatchOperand_ParseFail;
3544 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3545 Error(LaneLoc, "mismatched lane index in register list");
3546 return MatchOperand_ParseFail;
3550 // Normal D register.
3551 // Figure out the register spacing (single or double) of the list if
3552 // we don't know it already.
3554 Spacing = 1 + (Reg == OldReg + 2);
3556 // Just check that it's contiguous and keep going.
3557 if (Reg != OldReg + Spacing) {
3558 Error(RegLoc, "non-contiguous register range");
3559 return MatchOperand_ParseFail;
3562 // Parse the lane specifier if present.
3563 VectorLaneTy NextLaneKind;
3564 unsigned NextLaneIndex;
3565 SMLoc EndLoc = Parser.getTok().getLoc();
3566 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3567 return MatchOperand_ParseFail;
3568 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3569 Error(EndLoc, "mismatched lane index in register list");
3570 return MatchOperand_ParseFail;
3574 if (Parser.getTok().isNot(AsmToken::RCurly)) {
3575 Error(Parser.getTok().getLoc(), "'}' expected");
3576 return MatchOperand_ParseFail;
3578 E = Parser.getTok().getEndLoc();
3579 Parser.Lex(); // Eat '}' token.
3583 // Two-register operands have been converted to the
3584 // composite register classes.
3586 const MCRegisterClass *RC = (Spacing == 1) ?
3587 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3588 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3589 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3592 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3593 (Spacing == 2), S, E));
3596 // Two-register operands have been converted to the
3597 // composite register classes.
3599 const MCRegisterClass *RC = (Spacing == 1) ?
3600 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3601 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3602 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3604 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3609 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3615 return MatchOperand_Success;
3618 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3619 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3620 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3621 SMLoc S = Parser.getTok().getLoc();
3622 const AsmToken &Tok = Parser.getTok();
3625 if (Tok.is(AsmToken::Identifier)) {
3626 StringRef OptStr = Tok.getString();
3628 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3629 .Case("sy", ARM_MB::SY)
3630 .Case("st", ARM_MB::ST)
3631 .Case("ld", ARM_MB::LD)
3632 .Case("sh", ARM_MB::ISH)
3633 .Case("ish", ARM_MB::ISH)
3634 .Case("shst", ARM_MB::ISHST)
3635 .Case("ishst", ARM_MB::ISHST)
3636 .Case("ishld", ARM_MB::ISHLD)
3637 .Case("nsh", ARM_MB::NSH)
3638 .Case("un", ARM_MB::NSH)
3639 .Case("nshst", ARM_MB::NSHST)
3640 .Case("nshld", ARM_MB::NSHLD)
3641 .Case("unst", ARM_MB::NSHST)
3642 .Case("osh", ARM_MB::OSH)
3643 .Case("oshst", ARM_MB::OSHST)
3644 .Case("oshld", ARM_MB::OSHLD)
3647 // ishld, oshld, nshld and ld are only available from ARMv8.
3648 if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
3649 Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
3653 return MatchOperand_NoMatch;
3655 Parser.Lex(); // Eat identifier token.
3656 } else if (Tok.is(AsmToken::Hash) ||
3657 Tok.is(AsmToken::Dollar) ||
3658 Tok.is(AsmToken::Integer)) {
3659 if (Parser.getTok().isNot(AsmToken::Integer))
3660 Parser.Lex(); // Eat '#' or '$'.
3661 SMLoc Loc = Parser.getTok().getLoc();
3663 const MCExpr *MemBarrierID;
3664 if (getParser().parseExpression(MemBarrierID)) {
3665 Error(Loc, "illegal expression");
3666 return MatchOperand_ParseFail;
3669 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3671 Error(Loc, "constant expression expected");
3672 return MatchOperand_ParseFail;
3675 int Val = CE->getValue();
3677 Error(Loc, "immediate value out of range");
3678 return MatchOperand_ParseFail;
3681 Opt = ARM_MB::RESERVED_0 + Val;
3683 return MatchOperand_ParseFail;
3685 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3686 return MatchOperand_Success;
3689 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3690 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3691 parseInstSyncBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3692 SMLoc S = Parser.getTok().getLoc();
3693 const AsmToken &Tok = Parser.getTok();
3696 if (Tok.is(AsmToken::Identifier)) {
3697 StringRef OptStr = Tok.getString();
3699 if (OptStr.equals_lower("sy"))
3702 return MatchOperand_NoMatch;
3704 Parser.Lex(); // Eat identifier token.
3705 } else if (Tok.is(AsmToken::Hash) ||
3706 Tok.is(AsmToken::Dollar) ||
3707 Tok.is(AsmToken::Integer)) {
3708 if (Parser.getTok().isNot(AsmToken::Integer))
3709 Parser.Lex(); // Eat '#' or '$'.
3710 SMLoc Loc = Parser.getTok().getLoc();
3712 const MCExpr *ISBarrierID;
3713 if (getParser().parseExpression(ISBarrierID)) {
3714 Error(Loc, "illegal expression");
3715 return MatchOperand_ParseFail;
3718 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3720 Error(Loc, "constant expression expected");
3721 return MatchOperand_ParseFail;
3724 int Val = CE->getValue();
3726 Error(Loc, "immediate value out of range");
3727 return MatchOperand_ParseFail;
3730 Opt = ARM_ISB::RESERVED_0 + Val;
3732 return MatchOperand_ParseFail;
3734 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3735 (ARM_ISB::InstSyncBOpt)Opt, S));
3736 return MatchOperand_Success;
3740 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3741 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3742 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3743 SMLoc S = Parser.getTok().getLoc();
3744 const AsmToken &Tok = Parser.getTok();
3745 if (!Tok.is(AsmToken::Identifier))
3746 return MatchOperand_NoMatch;
3747 StringRef IFlagsStr = Tok.getString();
3749 // An iflags string of "none" is interpreted to mean that none of the AIF
3750 // bits are set. Not a terribly useful instruction, but a valid encoding.
3751 unsigned IFlags = 0;
3752 if (IFlagsStr != "none") {
3753 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3754 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3755 .Case("a", ARM_PROC::A)
3756 .Case("i", ARM_PROC::I)
3757 .Case("f", ARM_PROC::F)
3760 // If some specific iflag is already set, it means that some letter is
3761 // present more than once, this is not acceptable.
3762 if (Flag == ~0U || (IFlags & Flag))
3763 return MatchOperand_NoMatch;
3769 Parser.Lex(); // Eat identifier token.
3770 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3771 return MatchOperand_Success;
3774 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3775 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3776 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3777 SMLoc S = Parser.getTok().getLoc();
3778 const AsmToken &Tok = Parser.getTok();
3779 if (!Tok.is(AsmToken::Identifier))
3780 return MatchOperand_NoMatch;
3781 StringRef Mask = Tok.getString();
3784 // See ARMv6-M 10.1.1
3785 std::string Name = Mask.lower();
3786 unsigned FlagsVal = StringSwitch<unsigned>(Name)
3787 // Note: in the documentation:
3788 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3789 // for MSR APSR_nzcvq.
3790 // but we do make it an alias here. This is so to get the "mask encoding"
3791 // bits correct on MSR APSR writes.
3793 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3794 // should really only be allowed when writing a special register. Note
3795 // they get dropped in the MRS instruction reading a special register as
3796 // the SYSm field is only 8 bits.
3798 // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3799 // includes the DSP extension but that is not checked.
3800 .Case("apsr", 0x800)
3801 .Case("apsr_nzcvq", 0x800)
3802 .Case("apsr_g", 0x400)
3803 .Case("apsr_nzcvqg", 0xc00)
3804 .Case("iapsr", 0x801)
3805 .Case("iapsr_nzcvq", 0x801)
3806 .Case("iapsr_g", 0x401)
3807 .Case("iapsr_nzcvqg", 0xc01)
3808 .Case("eapsr", 0x802)
3809 .Case("eapsr_nzcvq", 0x802)
3810 .Case("eapsr_g", 0x402)
3811 .Case("eapsr_nzcvqg", 0xc02)
3812 .Case("xpsr", 0x803)
3813 .Case("xpsr_nzcvq", 0x803)
3814 .Case("xpsr_g", 0x403)
3815 .Case("xpsr_nzcvqg", 0xc03)
3816 .Case("ipsr", 0x805)
3817 .Case("epsr", 0x806)
3818 .Case("iepsr", 0x807)
3821 .Case("primask", 0x810)
3822 .Case("basepri", 0x811)
3823 .Case("basepri_max", 0x812)
3824 .Case("faultmask", 0x813)
3825 .Case("control", 0x814)
3828 if (FlagsVal == ~0U)
3829 return MatchOperand_NoMatch;
3831 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3832 // basepri, basepri_max and faultmask only valid for V7m.
3833 return MatchOperand_NoMatch;
3835 Parser.Lex(); // Eat identifier token.
3836 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3837 return MatchOperand_Success;
3840 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3841 size_t Start = 0, Next = Mask.find('_');
3842 StringRef Flags = "";
3843 std::string SpecReg = Mask.slice(Start, Next).lower();
3844 if (Next != StringRef::npos)
3845 Flags = Mask.slice(Next+1, Mask.size());
3847 // FlagsVal contains the complete mask:
3849 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3850 unsigned FlagsVal = 0;
3852 if (SpecReg == "apsr") {
3853 FlagsVal = StringSwitch<unsigned>(Flags)
3854 .Case("nzcvq", 0x8) // same as CPSR_f
3855 .Case("g", 0x4) // same as CPSR_s
3856 .Case("nzcvqg", 0xc) // same as CPSR_fs
3859 if (FlagsVal == ~0U) {
3861 return MatchOperand_NoMatch;
3863 FlagsVal = 8; // No flag
3865 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3866 // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3867 if (Flags == "all" || Flags == "")
3869 for (int i = 0, e = Flags.size(); i != e; ++i) {
3870 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3877 // If some specific flag is already set, it means that some letter is
3878 // present more than once, this is not acceptable.
3879 if (FlagsVal == ~0U || (FlagsVal & Flag))
3880 return MatchOperand_NoMatch;
3883 } else // No match for special register.
3884 return MatchOperand_NoMatch;
3886 // Special register without flags is NOT equivalent to "fc" flags.
3887 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
3888 // two lines would enable gas compatibility at the expense of breaking
3894 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3895 if (SpecReg == "spsr")
3898 Parser.Lex(); // Eat identifier token.
3899 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3900 return MatchOperand_Success;
3903 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3904 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3905 int Low, int High) {
3906 const AsmToken &Tok = Parser.getTok();
3907 if (Tok.isNot(AsmToken::Identifier)) {
3908 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3909 return MatchOperand_ParseFail;
3911 StringRef ShiftName = Tok.getString();
3912 std::string LowerOp = Op.lower();
3913 std::string UpperOp = Op.upper();
3914 if (ShiftName != LowerOp && ShiftName != UpperOp) {
3915 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3916 return MatchOperand_ParseFail;
3918 Parser.Lex(); // Eat shift type token.
3920 // There must be a '#' and a shift amount.
3921 if (Parser.getTok().isNot(AsmToken::Hash) &&
3922 Parser.getTok().isNot(AsmToken::Dollar)) {
3923 Error(Parser.getTok().getLoc(), "'#' expected");
3924 return MatchOperand_ParseFail;
3926 Parser.Lex(); // Eat hash token.
3928 const MCExpr *ShiftAmount;
3929 SMLoc Loc = Parser.getTok().getLoc();
3931 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3932 Error(Loc, "illegal expression");
3933 return MatchOperand_ParseFail;
3935 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3937 Error(Loc, "constant expression expected");
3938 return MatchOperand_ParseFail;
3940 int Val = CE->getValue();
3941 if (Val < Low || Val > High) {
3942 Error(Loc, "immediate value out of range");
3943 return MatchOperand_ParseFail;
3946 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
3948 return MatchOperand_Success;
3951 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3952 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3953 const AsmToken &Tok = Parser.getTok();
3954 SMLoc S = Tok.getLoc();
3955 if (Tok.isNot(AsmToken::Identifier)) {
3956 Error(S, "'be' or 'le' operand expected");
3957 return MatchOperand_ParseFail;
3959 int Val = StringSwitch<int>(Tok.getString().lower())
3963 Parser.Lex(); // Eat the token.
3966 Error(S, "'be' or 'le' operand expected");
3967 return MatchOperand_ParseFail;
3969 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3971 S, Tok.getEndLoc()));
3972 return MatchOperand_Success;
3975 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3976 /// instructions. Legal values are:
3977 /// lsl #n 'n' in [0,31]
3978 /// asr #n 'n' in [1,32]
3979 /// n == 32 encoded as n == 0.
3980 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3981 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3982 const AsmToken &Tok = Parser.getTok();
3983 SMLoc S = Tok.getLoc();
3984 if (Tok.isNot(AsmToken::Identifier)) {
3985 Error(S, "shift operator 'asr' or 'lsl' expected");
3986 return MatchOperand_ParseFail;
3988 StringRef ShiftName = Tok.getString();
3990 if (ShiftName == "lsl" || ShiftName == "LSL")
3992 else if (ShiftName == "asr" || ShiftName == "ASR")
3995 Error(S, "shift operator 'asr' or 'lsl' expected");
3996 return MatchOperand_ParseFail;
3998 Parser.Lex(); // Eat the operator.
4000 // A '#' and a shift amount.
4001 if (Parser.getTok().isNot(AsmToken::Hash) &&
4002 Parser.getTok().isNot(AsmToken::Dollar)) {
4003 Error(Parser.getTok().getLoc(), "'#' expected");
4004 return MatchOperand_ParseFail;
4006 Parser.Lex(); // Eat hash token.
4007 SMLoc ExLoc = Parser.getTok().getLoc();
4009 const MCExpr *ShiftAmount;
4011 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4012 Error(ExLoc, "malformed shift expression");
4013 return MatchOperand_ParseFail;
4015 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4017 Error(ExLoc, "shift amount must be an immediate");
4018 return MatchOperand_ParseFail;
4021 int64_t Val = CE->getValue();
4023 // Shift amount must be in [1,32]
4024 if (Val < 1 || Val > 32) {
4025 Error(ExLoc, "'asr' shift amount must be in range [1,32]");
4026 return MatchOperand_ParseFail;
4028 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
4029 if (isThumb() && Val == 32) {
4030 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
4031 return MatchOperand_ParseFail;
4033 if (Val == 32) Val = 0;
4035 // Shift amount must be in [1,32]
4036 if (Val < 0 || Val > 31) {
4037 Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
4038 return MatchOperand_ParseFail;
4042 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
4044 return MatchOperand_Success;
4047 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
4048 /// of instructions. Legal values are:
4049 /// ror #n 'n' in {0, 8, 16, 24}
4050 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4051 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4052 const AsmToken &Tok = Parser.getTok();
4053 SMLoc S = Tok.getLoc();
4054 if (Tok.isNot(AsmToken::Identifier))
4055 return MatchOperand_NoMatch;
4056 StringRef ShiftName = Tok.getString();
4057 if (ShiftName != "ror" && ShiftName != "ROR")
4058 return MatchOperand_NoMatch;
4059 Parser.Lex(); // Eat the operator.
4061 // A '#' and a rotate amount.
4062 if (Parser.getTok().isNot(AsmToken::Hash) &&
4063 Parser.getTok().isNot(AsmToken::Dollar)) {
4064 Error(Parser.getTok().getLoc(), "'#' expected");
4065 return MatchOperand_ParseFail;
4067 Parser.Lex(); // Eat hash token.
4068 SMLoc ExLoc = Parser.getTok().getLoc();
4070 const MCExpr *ShiftAmount;
4072 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4073 Error(ExLoc, "malformed rotate expression");
4074 return MatchOperand_ParseFail;
4076 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4078 Error(ExLoc, "rotate amount must be an immediate");
4079 return MatchOperand_ParseFail;
4082 int64_t Val = CE->getValue();
4083 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
4084 // normally, zero is represented in asm by omitting the rotate operand
4086 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
4087 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
4088 return MatchOperand_ParseFail;
4091 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
4093 return MatchOperand_Success;
4096 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4097 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4098 SMLoc S = Parser.getTok().getLoc();
4099 // The bitfield descriptor is really two operands, the LSB and the width.
4100 if (Parser.getTok().isNot(AsmToken::Hash) &&
4101 Parser.getTok().isNot(AsmToken::Dollar)) {
4102 Error(Parser.getTok().getLoc(), "'#' expected");
4103 return MatchOperand_ParseFail;
4105 Parser.Lex(); // Eat hash token.
4107 const MCExpr *LSBExpr;
4108 SMLoc E = Parser.getTok().getLoc();
4109 if (getParser().parseExpression(LSBExpr)) {
4110 Error(E, "malformed immediate expression");
4111 return MatchOperand_ParseFail;
4113 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
4115 Error(E, "'lsb' operand must be an immediate");
4116 return MatchOperand_ParseFail;
4119 int64_t LSB = CE->getValue();
4120 // The LSB must be in the range [0,31]
4121 if (LSB < 0 || LSB > 31) {
4122 Error(E, "'lsb' operand must be in the range [0,31]");
4123 return MatchOperand_ParseFail;
4125 E = Parser.getTok().getLoc();
4127 // Expect another immediate operand.
4128 if (Parser.getTok().isNot(AsmToken::Comma)) {
4129 Error(Parser.getTok().getLoc(), "too few operands");
4130 return MatchOperand_ParseFail;
4132 Parser.Lex(); // Eat hash token.
4133 if (Parser.getTok().isNot(AsmToken::Hash) &&
4134 Parser.getTok().isNot(AsmToken::Dollar)) {
4135 Error(Parser.getTok().getLoc(), "'#' expected");
4136 return MatchOperand_ParseFail;
4138 Parser.Lex(); // Eat hash token.
4140 const MCExpr *WidthExpr;
4142 if (getParser().parseExpression(WidthExpr, EndLoc)) {
4143 Error(E, "malformed immediate expression");
4144 return MatchOperand_ParseFail;
4146 CE = dyn_cast<MCConstantExpr>(WidthExpr);
4148 Error(E, "'width' operand must be an immediate");
4149 return MatchOperand_ParseFail;
4152 int64_t Width = CE->getValue();
4153 // The LSB must be in the range [1,32-lsb]
4154 if (Width < 1 || Width > 32 - LSB) {
4155 Error(E, "'width' operand must be in the range [1,32-lsb]");
4156 return MatchOperand_ParseFail;
4159 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4161 return MatchOperand_Success;
4164 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4165 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4166 // Check for a post-index addressing register operand. Specifically:
4167 // postidx_reg := '+' register {, shift}
4168 // | '-' register {, shift}
4169 // | register {, shift}
4171 // This method must return MatchOperand_NoMatch without consuming any tokens
4172 // in the case where there is no match, as other alternatives take other
4174 AsmToken Tok = Parser.getTok();
4175 SMLoc S = Tok.getLoc();
4176 bool haveEaten = false;
4178 if (Tok.is(AsmToken::Plus)) {
4179 Parser.Lex(); // Eat the '+' token.
4181 } else if (Tok.is(AsmToken::Minus)) {
4182 Parser.Lex(); // Eat the '-' token.
4187 SMLoc E = Parser.getTok().getEndLoc();
4188 int Reg = tryParseRegister();
4191 return MatchOperand_NoMatch;
4192 Error(Parser.getTok().getLoc(), "register expected");
4193 return MatchOperand_ParseFail;
4196 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4197 unsigned ShiftImm = 0;
4198 if (Parser.getTok().is(AsmToken::Comma)) {
4199 Parser.Lex(); // Eat the ','.
4200 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4201 return MatchOperand_ParseFail;
4203 // FIXME: Only approximates end...may include intervening whitespace.
4204 E = Parser.getTok().getLoc();
4207 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4210 return MatchOperand_Success;
4213 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4214 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4215 // Check for a post-index addressing register operand. Specifically:
4216 // am3offset := '+' register
4223 // This method must return MatchOperand_NoMatch without consuming any tokens
4224 // in the case where there is no match, as other alternatives take other
4226 AsmToken Tok = Parser.getTok();
4227 SMLoc S = Tok.getLoc();
4229 // Do immediates first, as we always parse those if we have a '#'.
4230 if (Parser.getTok().is(AsmToken::Hash) ||
4231 Parser.getTok().is(AsmToken::Dollar)) {
4232 Parser.Lex(); // Eat '#' or '$'.
4233 // Explicitly look for a '-', as we need to encode negative zero
4235 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4236 const MCExpr *Offset;
4238 if (getParser().parseExpression(Offset, E))
4239 return MatchOperand_ParseFail;
4240 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4242 Error(S, "constant expression expected");
4243 return MatchOperand_ParseFail;
4245 // Negative zero is encoded as the flag value INT32_MIN.
4246 int32_t Val = CE->getValue();
4247 if (isNegative && Val == 0)
4251 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4253 return MatchOperand_Success;
4257 bool haveEaten = false;
4259 if (Tok.is(AsmToken::Plus)) {
4260 Parser.Lex(); // Eat the '+' token.
4262 } else if (Tok.is(AsmToken::Minus)) {
4263 Parser.Lex(); // Eat the '-' token.
4268 Tok = Parser.getTok();
4269 int Reg = tryParseRegister();
4272 return MatchOperand_NoMatch;
4273 Error(Tok.getLoc(), "register expected");
4274 return MatchOperand_ParseFail;
4277 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4278 0, S, Tok.getEndLoc()));
4280 return MatchOperand_Success;
4283 /// Convert parsed operands to MCInst. Needed here because this instruction
4284 /// only has two register operands, but multiplication is commutative so
4285 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4287 cvtThumbMultiply(MCInst &Inst,
4288 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4289 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4290 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4291 // If we have a three-operand form, make sure to set Rn to be the operand
4292 // that isn't the same as Rd.
4294 if (Operands.size() == 6 &&
4295 ((ARMOperand*)Operands[4])->getReg() ==
4296 ((ARMOperand*)Operands[3])->getReg())
4298 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4299 Inst.addOperand(Inst.getOperand(0));
4300 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4304 cvtThumbBranches(MCInst &Inst,
4305 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4306 int CondOp = -1, ImmOp = -1;
4307 switch(Inst.getOpcode()) {
4309 case ARM::tBcc: CondOp = 1; ImmOp = 2; break;
4312 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4314 default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4316 // first decide whether or not the branch should be conditional
4317 // by looking at it's location relative to an IT block
4319 // inside an IT block we cannot have any conditional branches. any
4320 // such instructions needs to be converted to unconditional form
4321 switch(Inst.getOpcode()) {
4322 case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4323 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4326 // outside IT blocks we can only have unconditional branches with AL
4327 // condition code or conditional branches with non-AL condition code
4328 unsigned Cond = static_cast<ARMOperand*>(Operands[CondOp])->getCondCode();
4329 switch(Inst.getOpcode()) {
4332 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4336 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4341 // now decide on encoding size based on branch target range
4342 switch(Inst.getOpcode()) {
4343 // classify tB as either t2B or t1B based on range of immediate operand
4345 ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4346 if(!op->isSignedOffset<11, 1>() && isThumbTwo())
4347 Inst.setOpcode(ARM::t2B);
4350 // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4352 ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4353 if(!op->isSignedOffset<8, 1>() && isThumbTwo())
4354 Inst.setOpcode(ARM::t2Bcc);
4358 ((ARMOperand*)Operands[ImmOp])->addImmOperands(Inst, 1);
4359 ((ARMOperand*)Operands[CondOp])->addCondCodeOperands(Inst, 2);
4362 /// Parse an ARM memory expression, return false if successful else return true
4363 /// or an error. The first token must be a '[' when called.
4365 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4367 assert(Parser.getTok().is(AsmToken::LBrac) &&
4368 "Token is not a Left Bracket");
4369 S = Parser.getTok().getLoc();
4370 Parser.Lex(); // Eat left bracket token.
4372 const AsmToken &BaseRegTok = Parser.getTok();
4373 int BaseRegNum = tryParseRegister();
4374 if (BaseRegNum == -1)
4375 return Error(BaseRegTok.getLoc(), "register expected");
4377 // The next token must either be a comma, a colon or a closing bracket.
4378 const AsmToken &Tok = Parser.getTok();
4379 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4380 !Tok.is(AsmToken::RBrac))
4381 return Error(Tok.getLoc(), "malformed memory operand");
4383 if (Tok.is(AsmToken::RBrac)) {
4384 E = Tok.getEndLoc();
4385 Parser.Lex(); // Eat right bracket token.
4387 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4388 0, 0, false, S, E));
4390 // If there's a pre-indexing writeback marker, '!', just add it as a token
4391 // operand. It's rather odd, but syntactically valid.
4392 if (Parser.getTok().is(AsmToken::Exclaim)) {
4393 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4394 Parser.Lex(); // Eat the '!'.
4400 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4401 "Lost colon or comma in memory operand?!");
4402 if (Tok.is(AsmToken::Comma)) {
4403 Parser.Lex(); // Eat the comma.
4406 // If we have a ':', it's an alignment specifier.
4407 if (Parser.getTok().is(AsmToken::Colon)) {
4408 Parser.Lex(); // Eat the ':'.
4409 E = Parser.getTok().getLoc();
4412 if (getParser().parseExpression(Expr))
4415 // The expression has to be a constant. Memory references with relocations
4416 // don't come through here, as they use the <label> forms of the relevant
4418 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4420 return Error (E, "constant expression expected");
4423 switch (CE->getValue()) {
4426 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4427 case 16: Align = 2; break;
4428 case 32: Align = 4; break;
4429 case 64: Align = 8; break;
4430 case 128: Align = 16; break;
4431 case 256: Align = 32; break;
4434 // Now we should have the closing ']'
4435 if (Parser.getTok().isNot(AsmToken::RBrac))
4436 return Error(Parser.getTok().getLoc(), "']' expected");
4437 E = Parser.getTok().getEndLoc();
4438 Parser.Lex(); // Eat right bracket token.
4440 // Don't worry about range checking the value here. That's handled by
4441 // the is*() predicates.
4442 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4443 ARM_AM::no_shift, 0, Align,
4446 // If there's a pre-indexing writeback marker, '!', just add it as a token
4448 if (Parser.getTok().is(AsmToken::Exclaim)) {
4449 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4450 Parser.Lex(); // Eat the '!'.
4456 // If we have a '#', it's an immediate offset, else assume it's a register
4457 // offset. Be friendly and also accept a plain integer (without a leading
4458 // hash) for gas compatibility.
4459 if (Parser.getTok().is(AsmToken::Hash) ||
4460 Parser.getTok().is(AsmToken::Dollar) ||
4461 Parser.getTok().is(AsmToken::Integer)) {
4462 if (Parser.getTok().isNot(AsmToken::Integer))
4463 Parser.Lex(); // Eat '#' or '$'.
4464 E = Parser.getTok().getLoc();
4466 bool isNegative = getParser().getTok().is(AsmToken::Minus);
4467 const MCExpr *Offset;
4468 if (getParser().parseExpression(Offset))
4471 // The expression has to be a constant. Memory references with relocations
4472 // don't come through here, as they use the <label> forms of the relevant
4474 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4476 return Error (E, "constant expression expected");
4478 // If the constant was #-0, represent it as INT32_MIN.
4479 int32_t Val = CE->getValue();
4480 if (isNegative && Val == 0)
4481 CE = MCConstantExpr::Create(INT32_MIN, getContext());
4483 // Now we should have the closing ']'
4484 if (Parser.getTok().isNot(AsmToken::RBrac))
4485 return Error(Parser.getTok().getLoc(), "']' expected");
4486 E = Parser.getTok().getEndLoc();
4487 Parser.Lex(); // Eat right bracket token.
4489 // Don't worry about range checking the value here. That's handled by
4490 // the is*() predicates.
4491 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4492 ARM_AM::no_shift, 0, 0,
4495 // If there's a pre-indexing writeback marker, '!', just add it as a token
4497 if (Parser.getTok().is(AsmToken::Exclaim)) {
4498 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4499 Parser.Lex(); // Eat the '!'.
4505 // The register offset is optionally preceded by a '+' or '-'
4506 bool isNegative = false;
4507 if (Parser.getTok().is(AsmToken::Minus)) {
4509 Parser.Lex(); // Eat the '-'.
4510 } else if (Parser.getTok().is(AsmToken::Plus)) {
4512 Parser.Lex(); // Eat the '+'.
4515 E = Parser.getTok().getLoc();
4516 int OffsetRegNum = tryParseRegister();
4517 if (OffsetRegNum == -1)
4518 return Error(E, "register expected");
4520 // If there's a shift operator, handle it.
4521 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4522 unsigned ShiftImm = 0;
4523 if (Parser.getTok().is(AsmToken::Comma)) {
4524 Parser.Lex(); // Eat the ','.
4525 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4529 // Now we should have the closing ']'
4530 if (Parser.getTok().isNot(AsmToken::RBrac))
4531 return Error(Parser.getTok().getLoc(), "']' expected");
4532 E = Parser.getTok().getEndLoc();
4533 Parser.Lex(); // Eat right bracket token.
4535 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4536 ShiftType, ShiftImm, 0, isNegative,
4539 // If there's a pre-indexing writeback marker, '!', just add it as a token
4541 if (Parser.getTok().is(AsmToken::Exclaim)) {
4542 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4543 Parser.Lex(); // Eat the '!'.
4549 /// parseMemRegOffsetShift - one of these two:
4550 /// ( lsl | lsr | asr | ror ) , # shift_amount
4552 /// return true if it parses a shift otherwise it returns false.
4553 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4555 SMLoc Loc = Parser.getTok().getLoc();
4556 const AsmToken &Tok = Parser.getTok();
4557 if (Tok.isNot(AsmToken::Identifier))
4559 StringRef ShiftName = Tok.getString();
4560 if (ShiftName == "lsl" || ShiftName == "LSL" ||
4561 ShiftName == "asl" || ShiftName == "ASL")
4563 else if (ShiftName == "lsr" || ShiftName == "LSR")
4565 else if (ShiftName == "asr" || ShiftName == "ASR")
4567 else if (ShiftName == "ror" || ShiftName == "ROR")
4569 else if (ShiftName == "rrx" || ShiftName == "RRX")
4572 return Error(Loc, "illegal shift operator");
4573 Parser.Lex(); // Eat shift type token.
4575 // rrx stands alone.
4577 if (St != ARM_AM::rrx) {
4578 Loc = Parser.getTok().getLoc();
4579 // A '#' and a shift amount.
4580 const AsmToken &HashTok = Parser.getTok();
4581 if (HashTok.isNot(AsmToken::Hash) &&
4582 HashTok.isNot(AsmToken::Dollar))
4583 return Error(HashTok.getLoc(), "'#' expected");
4584 Parser.Lex(); // Eat hash token.
4587 if (getParser().parseExpression(Expr))
4589 // Range check the immediate.
4590 // lsl, ror: 0 <= imm <= 31
4591 // lsr, asr: 0 <= imm <= 32
4592 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4594 return Error(Loc, "shift amount must be an immediate");
4595 int64_t Imm = CE->getValue();
4597 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4598 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4599 return Error(Loc, "immediate shift value out of range");
4600 // If <ShiftTy> #0, turn it into a no_shift.
4603 // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4612 /// parseFPImm - A floating point immediate expression operand.
4613 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4614 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4615 // Anything that can accept a floating point constant as an operand
4616 // needs to go through here, as the regular parseExpression is
4619 // This routine still creates a generic Immediate operand, containing
4620 // a bitcast of the 64-bit floating point value. The various operands
4621 // that accept floats can check whether the value is valid for them
4622 // via the standard is*() predicates.
4624 SMLoc S = Parser.getTok().getLoc();
4626 if (Parser.getTok().isNot(AsmToken::Hash) &&
4627 Parser.getTok().isNot(AsmToken::Dollar))
4628 return MatchOperand_NoMatch;
4630 // Disambiguate the VMOV forms that can accept an FP immediate.
4631 // vmov.f32 <sreg>, #imm
4632 // vmov.f64 <dreg>, #imm
4633 // vmov.f32 <dreg>, #imm @ vector f32x2
4634 // vmov.f32 <qreg>, #imm @ vector f32x4
4636 // There are also the NEON VMOV instructions which expect an
4637 // integer constant. Make sure we don't try to parse an FPImm
4639 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4640 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4641 bool isVmovf = TyOp->isToken() && (TyOp->getToken() == ".f32" ||
4642 TyOp->getToken() == ".f64");
4643 ARMOperand *Mnemonic = static_cast<ARMOperand*>(Operands[0]);
4644 bool isFconst = Mnemonic->isToken() && (Mnemonic->getToken() == "fconstd" ||
4645 Mnemonic->getToken() == "fconsts");
4646 if (!(isVmovf || isFconst))
4647 return MatchOperand_NoMatch;
4649 Parser.Lex(); // Eat '#' or '$'.
4651 // Handle negation, as that still comes through as a separate token.
4652 bool isNegative = false;
4653 if (Parser.getTok().is(AsmToken::Minus)) {
4657 const AsmToken &Tok = Parser.getTok();
4658 SMLoc Loc = Tok.getLoc();
4659 if (Tok.is(AsmToken::Real) && isVmovf) {
4660 APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4661 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4662 // If we had a '-' in front, toggle the sign bit.
4663 IntVal ^= (uint64_t)isNegative << 31;
4664 Parser.Lex(); // Eat the token.
4665 Operands.push_back(ARMOperand::CreateImm(
4666 MCConstantExpr::Create(IntVal, getContext()),
4667 S, Parser.getTok().getLoc()));
4668 return MatchOperand_Success;
4670 // Also handle plain integers. Instructions which allow floating point
4671 // immediates also allow a raw encoded 8-bit value.
4672 if (Tok.is(AsmToken::Integer) && isFconst) {
4673 int64_t Val = Tok.getIntVal();
4674 Parser.Lex(); // Eat the token.
4675 if (Val > 255 || Val < 0) {
4676 Error(Loc, "encoded floating point value out of range");
4677 return MatchOperand_ParseFail;
4679 float RealVal = ARM_AM::getFPImmFloat(Val);
4680 Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
4682 Operands.push_back(ARMOperand::CreateImm(
4683 MCConstantExpr::Create(Val, getContext()), S,
4684 Parser.getTok().getLoc()));
4685 return MatchOperand_Success;
4688 Error(Loc, "invalid floating point immediate");
4689 return MatchOperand_ParseFail;
4692 /// Parse a arm instruction operand. For now this parses the operand regardless
4693 /// of the mnemonic.
4694 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4695 StringRef Mnemonic) {
4698 // Check if the current operand has a custom associated parser, if so, try to
4699 // custom parse the operand, or fallback to the general approach.
4700 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4701 if (ResTy == MatchOperand_Success)
4703 // If there wasn't a custom match, try the generic matcher below. Otherwise,
4704 // there was a match, but an error occurred, in which case, just return that
4705 // the operand parsing failed.
4706 if (ResTy == MatchOperand_ParseFail)
4709 switch (getLexer().getKind()) {
4711 Error(Parser.getTok().getLoc(), "unexpected token in operand");
4713 case AsmToken::Identifier: {
4714 // If we've seen a branch mnemonic, the next operand must be a label. This
4715 // is true even if the label is a register name. So "br r1" means branch to
4717 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
4719 if (!tryParseRegisterWithWriteBack(Operands))
4721 int Res = tryParseShiftRegister(Operands);
4722 if (Res == 0) // success
4724 else if (Res == -1) // irrecoverable error
4726 // If this is VMRS, check for the apsr_nzcv operand.
4727 if (Mnemonic == "vmrs" &&
4728 Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4729 S = Parser.getTok().getLoc();
4731 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4736 // Fall though for the Identifier case that is not a register or a
4739 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
4740 case AsmToken::Integer: // things like 1f and 2b as a branch targets
4741 case AsmToken::String: // quoted label names.
4742 case AsmToken::Dot: { // . as a branch target
4743 // This was not a register so parse other operands that start with an
4744 // identifier (like labels) as expressions and create them as immediates.
4745 const MCExpr *IdVal;
4746 S = Parser.getTok().getLoc();
4747 if (getParser().parseExpression(IdVal))
4749 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4750 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4753 case AsmToken::LBrac:
4754 return parseMemory(Operands);
4755 case AsmToken::LCurly:
4756 return parseRegisterList(Operands);
4757 case AsmToken::Dollar:
4758 case AsmToken::Hash: {
4759 // #42 -> immediate.
4760 S = Parser.getTok().getLoc();
4763 if (Parser.getTok().isNot(AsmToken::Colon)) {
4764 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4765 const MCExpr *ImmVal;
4766 if (getParser().parseExpression(ImmVal))
4768 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4770 int32_t Val = CE->getValue();
4771 if (isNegative && Val == 0)
4772 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4774 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4775 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4777 // There can be a trailing '!' on operands that we want as a separate
4778 // '!' Token operand. Handle that here. For example, the compatibility
4779 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
4780 if (Parser.getTok().is(AsmToken::Exclaim)) {
4781 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
4782 Parser.getTok().getLoc()));
4783 Parser.Lex(); // Eat exclaim token
4787 // w/ a ':' after the '#', it's just like a plain ':'.
4790 case AsmToken::Colon: {
4791 // ":lower16:" and ":upper16:" expression prefixes
4792 // FIXME: Check it's an expression prefix,
4793 // e.g. (FOO - :lower16:BAR) isn't legal.
4794 ARMMCExpr::VariantKind RefKind;
4795 if (parsePrefix(RefKind))
4798 const MCExpr *SubExprVal;
4799 if (getParser().parseExpression(SubExprVal))
4802 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4804 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4805 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4808 case AsmToken::Equal: {
4809 if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
4810 return Error(Parser.getTok().getLoc(), "unexpected token in operand");
4812 const MCSection *Section =
4813 getParser().getStreamer().getCurrentSection().first;
4815 Parser.Lex(); // Eat '='
4816 const MCExpr *SubExprVal;
4817 if (getParser().parseExpression(SubExprVal))
4819 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4821 const MCExpr *CPLoc =
4822 getOrCreateConstantPool(Section).addEntry(SubExprVal, getContext());
4823 Operands.push_back(ARMOperand::CreateImm(CPLoc, S, E));
4829 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4830 // :lower16: and :upper16:.
4831 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4832 RefKind = ARMMCExpr::VK_ARM_None;
4834 // consume an optional '#' (GNU compatibility)
4835 if (getLexer().is(AsmToken::Hash))
4838 // :lower16: and :upper16: modifiers
4839 assert(getLexer().is(AsmToken::Colon) && "expected a :");
4840 Parser.Lex(); // Eat ':'
4842 if (getLexer().isNot(AsmToken::Identifier)) {
4843 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4847 StringRef IDVal = Parser.getTok().getIdentifier();
4848 if (IDVal == "lower16") {
4849 RefKind = ARMMCExpr::VK_ARM_LO16;
4850 } else if (IDVal == "upper16") {
4851 RefKind = ARMMCExpr::VK_ARM_HI16;
4853 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4858 if (getLexer().isNot(AsmToken::Colon)) {
4859 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4862 Parser.Lex(); // Eat the last ':'
4866 /// \brief Given a mnemonic, split out possible predication code and carry
4867 /// setting letters to form a canonical mnemonic and flags.
4869 // FIXME: Would be nice to autogen this.
4870 // FIXME: This is a bit of a maze of special cases.
4871 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4872 unsigned &PredicationCode,
4874 unsigned &ProcessorIMod,
4875 StringRef &ITMask) {
4876 PredicationCode = ARMCC::AL;
4877 CarrySetting = false;
4880 // Ignore some mnemonics we know aren't predicated forms.
4882 // FIXME: Would be nice to autogen this.
4883 if ((Mnemonic == "movs" && isThumb()) ||
4884 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
4885 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
4886 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
4887 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
4888 Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" ||
4889 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
4890 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
4891 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4892 Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
4893 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" ||
4894 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
4895 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel"))
4898 // First, split out any predication code. Ignore mnemonics we know aren't
4899 // predicated but do have a carry-set and so weren't caught above.
4900 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4901 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4902 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4903 Mnemonic != "sbcs" && Mnemonic != "rscs") {
4904 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4905 .Case("eq", ARMCC::EQ)
4906 .Case("ne", ARMCC::NE)
4907 .Case("hs", ARMCC::HS)
4908 .Case("cs", ARMCC::HS)
4909 .Case("lo", ARMCC::LO)
4910 .Case("cc", ARMCC::LO)
4911 .Case("mi", ARMCC::MI)
4912 .Case("pl", ARMCC::PL)
4913 .Case("vs", ARMCC::VS)
4914 .Case("vc", ARMCC::VC)
4915 .Case("hi", ARMCC::HI)
4916 .Case("ls", ARMCC::LS)
4917 .Case("ge", ARMCC::GE)
4918 .Case("lt", ARMCC::LT)
4919 .Case("gt", ARMCC::GT)
4920 .Case("le", ARMCC::LE)
4921 .Case("al", ARMCC::AL)
4924 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4925 PredicationCode = CC;
4929 // Next, determine if we have a carry setting bit. We explicitly ignore all
4930 // the instructions we know end in 's'.
4931 if (Mnemonic.endswith("s") &&
4932 !(Mnemonic == "cps" || Mnemonic == "mls" ||
4933 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4934 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4935 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4936 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4937 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4938 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4939 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
4940 Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
4941 (Mnemonic == "movs" && isThumb()))) {
4942 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4943 CarrySetting = true;
4946 // The "cps" instruction can have a interrupt mode operand which is glued into
4947 // the mnemonic. Check if this is the case, split it and parse the imod op
4948 if (Mnemonic.startswith("cps")) {
4949 // Split out any imod code.
4951 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4952 .Case("ie", ARM_PROC::IE)
4953 .Case("id", ARM_PROC::ID)
4956 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4957 ProcessorIMod = IMod;
4961 // The "it" instruction has the condition mask on the end of the mnemonic.
4962 if (Mnemonic.startswith("it")) {
4963 ITMask = Mnemonic.slice(2, Mnemonic.size());
4964 Mnemonic = Mnemonic.slice(0, 2);
4970 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
4971 /// inclusion of carry set or predication code operands.
4973 // FIXME: It would be nice to autogen this.
4975 getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
4976 bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) {
4977 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4978 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4979 Mnemonic == "add" || Mnemonic == "adc" ||
4980 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4981 Mnemonic == "orr" || Mnemonic == "mvn" ||
4982 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4983 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4984 Mnemonic == "vfm" || Mnemonic == "vfnm" ||
4985 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4986 Mnemonic == "mla" || Mnemonic == "smlal" ||
4987 Mnemonic == "umlal" || Mnemonic == "umull"))) {
4988 CanAcceptCarrySet = true;
4990 CanAcceptCarrySet = false;
4992 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
4993 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
4994 Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic.startswith("crc32") ||
4995 Mnemonic.startswith("cps") || Mnemonic.startswith("vsel") ||
4996 Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
4997 Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
4998 Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
4999 Mnemonic == "vrintm" || Mnemonic.startswith("aes") ||
5000 Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
5001 (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) {
5002 // These mnemonics are never predicable
5003 CanAcceptPredicationCode = false;
5004 } else if (!isThumb()) {
5005 // Some instructions are only predicable in Thumb mode
5006 CanAcceptPredicationCode
5007 = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
5008 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
5009 Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
5010 Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
5011 Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
5012 Mnemonic != "stc2" && Mnemonic != "stc2l" &&
5013 !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
5014 } else if (isThumbOne()) {
5016 CanAcceptPredicationCode = Mnemonic != "movs";
5018 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
5020 CanAcceptPredicationCode = true;
5023 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
5024 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5025 // FIXME: This is all horribly hacky. We really need a better way to deal
5026 // with optional operands like this in the matcher table.
5028 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
5029 // another does not. Specifically, the MOVW instruction does not. So we
5030 // special case it here and remove the defaulted (non-setting) cc_out
5031 // operand if that's the instruction we're trying to match.
5033 // We do this as post-processing of the explicit operands rather than just
5034 // conditionally adding the cc_out in the first place because we need
5035 // to check the type of the parsed immediate operand.
5036 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
5037 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
5038 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
5039 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
5042 // Register-register 'add' for thumb does not have a cc_out operand
5043 // when there are only two register operands.
5044 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
5045 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5046 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5047 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
5049 // Register-register 'add' for thumb does not have a cc_out operand
5050 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
5051 // have to check the immediate range here since Thumb2 has a variant
5052 // that can handle a different range and has a cc_out operand.
5053 if (((isThumb() && Mnemonic == "add") ||
5054 (isThumbTwo() && Mnemonic == "sub")) &&
5055 Operands.size() == 6 &&
5056 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5057 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5058 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
5059 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5060 ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
5061 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
5063 // For Thumb2, add/sub immediate does not have a cc_out operand for the
5064 // imm0_4095 variant. That's the least-preferred variant when
5065 // selecting via the generic "add" mnemonic, so to know that we
5066 // should remove the cc_out operand, we have to explicitly check that
5067 // it's not one of the other variants. Ugh.
5068 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
5069 Operands.size() == 6 &&
5070 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5071 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5072 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5073 // Nest conditions rather than one big 'if' statement for readability.
5075 // If both registers are low, we're in an IT block, and the immediate is
5076 // in range, we should use encoding T1 instead, which has a cc_out.
5078 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
5079 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
5080 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
5082 // Check against T3. If the second register is the PC, this is an
5083 // alternate form of ADR, which uses encoding T4, so check for that too.
5084 if (static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
5085 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
5088 // Otherwise, we use encoding T4, which does not have a cc_out
5093 // The thumb2 multiply instruction doesn't have a CCOut register, so
5094 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
5095 // use the 16-bit encoding or not.
5096 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5097 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5098 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5099 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5100 static_cast<ARMOperand*>(Operands[5])->isReg() &&
5101 // If the registers aren't low regs, the destination reg isn't the
5102 // same as one of the source regs, or the cc_out operand is zero
5103 // outside of an IT block, we have to use the 32-bit encoding, so
5104 // remove the cc_out operand.
5105 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
5106 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
5107 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
5109 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
5110 static_cast<ARMOperand*>(Operands[5])->getReg() &&
5111 static_cast<ARMOperand*>(Operands[3])->getReg() !=
5112 static_cast<ARMOperand*>(Operands[4])->getReg())))
5115 // Also check the 'mul' syntax variant that doesn't specify an explicit
5116 // destination register.
5117 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5118 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5119 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5120 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5121 // If the registers aren't low regs or the cc_out operand is zero
5122 // outside of an IT block, we have to use the 32-bit encoding, so
5123 // remove the cc_out operand.
5124 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
5125 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
5131 // Register-register 'add/sub' for thumb does not have a cc_out operand
5132 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5133 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
5134 // right, this will result in better diagnostics (which operand is off)
5136 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
5137 (Operands.size() == 5 || Operands.size() == 6) &&
5138 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5139 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
5140 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5141 (static_cast<ARMOperand*>(Operands[4])->isImm() ||
5142 (Operands.size() == 6 &&
5143 static_cast<ARMOperand*>(Operands[5])->isImm())))
5149 bool ARMAsmParser::shouldOmitPredicateOperand(
5150 StringRef Mnemonic, SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
5151 // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
5152 unsigned RegIdx = 3;
5153 if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
5154 static_cast<ARMOperand *>(Operands[2])->getToken() == ".f32") {
5155 if (static_cast<ARMOperand *>(Operands[3])->isToken() &&
5156 static_cast<ARMOperand *>(Operands[3])->getToken() == ".f32")
5159 if (static_cast<ARMOperand *>(Operands[RegIdx])->isReg() &&
5160 (ARMMCRegisterClasses[ARM::DPRRegClassID]
5161 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg()) ||
5162 ARMMCRegisterClasses[ARM::QPRRegClassID]
5163 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg())))
5169 static bool isDataTypeToken(StringRef Tok) {
5170 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5171 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5172 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5173 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5174 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5175 Tok == ".f" || Tok == ".d";
5178 // FIXME: This bit should probably be handled via an explicit match class
5179 // in the .td files that matches the suffix instead of having it be
5180 // a literal string token the way it is now.
5181 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5182 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5184 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
5185 unsigned VariantID);
5187 static bool RequiresVFPRegListValidation(StringRef Inst,
5188 bool &AcceptSinglePrecisionOnly,
5189 bool &AcceptDoublePrecisionOnly) {
5190 if (Inst.size() < 7)
5193 if (Inst.startswith("fldm") || Inst.startswith("fstm")) {
5194 StringRef AddressingMode = Inst.substr(4, 2);
5195 if (AddressingMode == "ia" || AddressingMode == "db" ||
5196 AddressingMode == "ea" || AddressingMode == "fd") {
5197 AcceptSinglePrecisionOnly = Inst[6] == 's';
5198 AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x';
5206 /// Parse an arm instruction mnemonic followed by its operands.
5207 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5209 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5210 // FIXME: Can this be done via tablegen in some fashion?
5211 bool RequireVFPRegisterListCheck;
5212 bool AcceptSinglePrecisionOnly;
5213 bool AcceptDoublePrecisionOnly;
5214 RequireVFPRegisterListCheck =
5215 RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly,
5216 AcceptDoublePrecisionOnly);
5218 // Apply mnemonic aliases before doing anything else, as the destination
5219 // mnemonic may include suffices and we want to handle them normally.
5220 // The generic tblgen'erated code does this later, at the start of
5221 // MatchInstructionImpl(), but that's too late for aliases that include
5222 // any sort of suffix.
5223 unsigned AvailableFeatures = getAvailableFeatures();
5224 unsigned AssemblerDialect = getParser().getAssemblerDialect();
5225 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5227 // First check for the ARM-specific .req directive.
5228 if (Parser.getTok().is(AsmToken::Identifier) &&
5229 Parser.getTok().getIdentifier() == ".req") {
5230 parseDirectiveReq(Name, NameLoc);
5231 // We always return 'error' for this, as we're done with this
5232 // statement and don't need to match the 'instruction."
5236 // Create the leading tokens for the mnemonic, split by '.' characters.
5237 size_t Start = 0, Next = Name.find('.');
5238 StringRef Mnemonic = Name.slice(Start, Next);
5240 // Split out the predication code and carry setting flag from the mnemonic.
5241 unsigned PredicationCode;
5242 unsigned ProcessorIMod;
5245 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5246 ProcessorIMod, ITMask);
5248 // In Thumb1, only the branch (B) instruction can be predicated.
5249 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5250 Parser.eatToEndOfStatement();
5251 return Error(NameLoc, "conditional execution not supported in Thumb1");
5254 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5256 // Handle the IT instruction ITMask. Convert it to a bitmask. This
5257 // is the mask as it will be for the IT encoding if the conditional
5258 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5259 // where the conditional bit0 is zero, the instruction post-processing
5260 // will adjust the mask accordingly.
5261 if (Mnemonic == "it") {
5262 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5263 if (ITMask.size() > 3) {
5264 Parser.eatToEndOfStatement();
5265 return Error(Loc, "too many conditions on IT instruction");
5268 for (unsigned i = ITMask.size(); i != 0; --i) {
5269 char pos = ITMask[i - 1];
5270 if (pos != 't' && pos != 'e') {
5271 Parser.eatToEndOfStatement();
5272 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5275 if (ITMask[i - 1] == 't')
5278 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5281 // FIXME: This is all a pretty gross hack. We should automatically handle
5282 // optional operands like this via tblgen.
5284 // Next, add the CCOut and ConditionCode operands, if needed.
5286 // For mnemonics which can ever incorporate a carry setting bit or predication
5287 // code, our matching model involves us always generating CCOut and
5288 // ConditionCode operands to match the mnemonic "as written" and then we let
5289 // the matcher deal with finding the right instruction or generating an
5290 // appropriate error.
5291 bool CanAcceptCarrySet, CanAcceptPredicationCode;
5292 getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
5294 // If we had a carry-set on an instruction that can't do that, issue an
5296 if (!CanAcceptCarrySet && CarrySetting) {
5297 Parser.eatToEndOfStatement();
5298 return Error(NameLoc, "instruction '" + Mnemonic +
5299 "' can not set flags, but 's' suffix specified");
5301 // If we had a predication code on an instruction that can't do that, issue an
5303 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5304 Parser.eatToEndOfStatement();
5305 return Error(NameLoc, "instruction '" + Mnemonic +
5306 "' is not predicable, but condition code specified");
5309 // Add the carry setting operand, if necessary.
5310 if (CanAcceptCarrySet) {
5311 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5312 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5316 // Add the predication code operand, if necessary.
5317 if (CanAcceptPredicationCode) {
5318 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5320 Operands.push_back(ARMOperand::CreateCondCode(
5321 ARMCC::CondCodes(PredicationCode), Loc));
5324 // Add the processor imod operand, if necessary.
5325 if (ProcessorIMod) {
5326 Operands.push_back(ARMOperand::CreateImm(
5327 MCConstantExpr::Create(ProcessorIMod, getContext()),
5331 // Add the remaining tokens in the mnemonic.
5332 while (Next != StringRef::npos) {
5334 Next = Name.find('.', Start + 1);
5335 StringRef ExtraToken = Name.slice(Start, Next);
5337 // Some NEON instructions have an optional datatype suffix that is
5338 // completely ignored. Check for that.
5339 if (isDataTypeToken(ExtraToken) &&
5340 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5343 // For for ARM mode generate an error if the .n qualifier is used.
5344 if (ExtraToken == ".n" && !isThumb()) {
5345 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5346 Parser.eatToEndOfStatement();
5347 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5351 // The .n qualifier is always discarded as that is what the tables
5352 // and matcher expect. In ARM mode the .w qualifier has no effect,
5353 // so discard it to avoid errors that can be caused by the matcher.
5354 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5355 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5356 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5360 // Read the remaining operands.
5361 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5362 // Read the first operand.
5363 if (parseOperand(Operands, Mnemonic)) {
5364 Parser.eatToEndOfStatement();
5368 while (getLexer().is(AsmToken::Comma)) {
5369 Parser.Lex(); // Eat the comma.
5371 // Parse and remember the operand.
5372 if (parseOperand(Operands, Mnemonic)) {
5373 Parser.eatToEndOfStatement();
5379 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5380 SMLoc Loc = getLexer().getLoc();
5381 Parser.eatToEndOfStatement();
5382 return Error(Loc, "unexpected token in argument list");
5385 Parser.Lex(); // Consume the EndOfStatement
5387 if (RequireVFPRegisterListCheck) {
5388 ARMOperand *Op = static_cast<ARMOperand*>(Operands.back());
5389 if (AcceptSinglePrecisionOnly && !Op->isSPRRegList())
5390 return Error(Op->getStartLoc(),
5391 "VFP/Neon single precision register expected");
5392 if (AcceptDoublePrecisionOnly && !Op->isDPRRegList())
5393 return Error(Op->getStartLoc(),
5394 "VFP/Neon double precision register expected");
5397 // Some instructions, mostly Thumb, have forms for the same mnemonic that
5398 // do and don't have a cc_out optional-def operand. With some spot-checks
5399 // of the operand list, we can figure out which variant we're trying to
5400 // parse and adjust accordingly before actually matching. We shouldn't ever
5401 // try to remove a cc_out operand that was explicitly set on the the
5402 // mnemonic, of course (CarrySetting == true). Reason number #317 the
5403 // table driven matcher doesn't fit well with the ARM instruction set.
5404 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5405 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5406 Operands.erase(Operands.begin() + 1);
5410 // Some instructions have the same mnemonic, but don't always
5411 // have a predicate. Distinguish them here and delete the
5412 // predicate if needed.
5413 if (shouldOmitPredicateOperand(Mnemonic, Operands)) {
5414 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5415 Operands.erase(Operands.begin() + 1);
5419 // ARM mode 'blx' need special handling, as the register operand version
5420 // is predicable, but the label operand version is not. So, we can't rely
5421 // on the Mnemonic based checking to correctly figure out when to put
5422 // a k_CondCode operand in the list. If we're trying to match the label
5423 // version, remove the k_CondCode operand here.
5424 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5425 static_cast<ARMOperand*>(Operands[2])->isImm()) {
5426 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5427 Operands.erase(Operands.begin() + 1);
5431 // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5432 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5433 // a single GPRPair reg operand is used in the .td file to replace the two
5434 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5435 // expressed as a GPRPair, so we have to manually merge them.
5436 // FIXME: We would really like to be able to tablegen'erate this.
5437 if (!isThumb() && Operands.size() > 4 &&
5438 (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
5439 Mnemonic == "stlexd")) {
5440 bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
5441 unsigned Idx = isLoad ? 2 : 3;
5442 ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]);
5443 ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]);
5445 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5446 // Adjust only if Op1 and Op2 are GPRs.
5447 if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) &&
5448 MRC.contains(Op2->getReg())) {
5449 unsigned Reg1 = Op1->getReg();
5450 unsigned Reg2 = Op2->getReg();
5451 unsigned Rt = MRI->getEncodingValue(Reg1);
5452 unsigned Rt2 = MRI->getEncodingValue(Reg2);
5454 // Rt2 must be Rt + 1 and Rt must be even.
5455 if (Rt + 1 != Rt2 || (Rt & 1)) {
5456 Error(Op2->getStartLoc(), isLoad ?
5457 "destination operands must be sequential" :
5458 "source operands must be sequential");
5461 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5462 &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5463 Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2);
5464 Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg(
5465 NewReg, Op1->getStartLoc(), Op2->getEndLoc()));
5471 // GNU Assembler extension (compatibility)
5472 if ((Mnemonic == "ldrd" || Mnemonic == "strd") && !isThumb() &&
5473 Operands.size() == 4) {
5474 ARMOperand *Op = static_cast<ARMOperand *>(Operands[2]);
5475 assert(Op->isReg() && "expected register argument");
5476 assert(MRI->getMatchingSuperReg(Op->getReg(), ARM::gsub_0,
5477 &MRI->getRegClass(ARM::GPRPairRegClassID))
5478 && "expected register pair");
5479 Operands.insert(Operands.begin() + 3,
5480 ARMOperand::CreateReg(Op->getReg() + 1, Op->getStartLoc(),
5484 // FIXME: As said above, this is all a pretty gross hack. This instruction
5485 // does not fit with other "subs" and tblgen.
5486 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
5487 // so the Mnemonic is the original name "subs" and delete the predicate
5488 // operand so it will match the table entry.
5489 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
5490 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5491 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::PC &&
5492 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5493 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::LR &&
5494 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5495 ARMOperand *Op0 = static_cast<ARMOperand*>(Operands[0]);
5496 Operands.erase(Operands.begin());
5498 Operands.insert(Operands.begin(), ARMOperand::CreateToken(Name, NameLoc));
5500 ARMOperand *Op1 = static_cast<ARMOperand*>(Operands[1]);
5501 Operands.erase(Operands.begin() + 1);
5507 // Validate context-sensitive operand constraints.
5509 // return 'true' if register list contains non-low GPR registers,
5510 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5511 // 'containsReg' to true.
5512 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5513 unsigned HiReg, bool &containsReg) {
5514 containsReg = false;
5515 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5516 unsigned OpReg = Inst.getOperand(i).getReg();
5519 // Anything other than a low register isn't legal here.
5520 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5526 // Check if the specified regisgter is in the register list of the inst,
5527 // starting at the indicated operand number.
5528 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5529 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5530 unsigned OpReg = Inst.getOperand(i).getReg();
5537 // Return true if instruction has the interesting property of being
5538 // allowed in IT blocks, but not being predicable.
5539 static bool instIsBreakpoint(const MCInst &Inst) {
5540 return Inst.getOpcode() == ARM::tBKPT ||
5541 Inst.getOpcode() == ARM::BKPT ||
5542 Inst.getOpcode() == ARM::tHLT ||
5543 Inst.getOpcode() == ARM::HLT;
5547 // FIXME: We would really like to be able to tablegen'erate this.
5549 validateInstruction(MCInst &Inst,
5550 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5551 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
5552 SMLoc Loc = Operands[0]->getStartLoc();
5554 // Check the IT block state first.
5555 // NOTE: BKPT and HLT instructions have the interesting property of being
5556 // allowed in IT blocks, but not being predicable. They just always execute.
5557 if (inITBlock() && !instIsBreakpoint(Inst)) {
5559 if (ITState.FirstCond)
5560 ITState.FirstCond = false;
5562 Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5563 // The instruction must be predicable.
5564 if (!MCID.isPredicable())
5565 return Error(Loc, "instructions in IT block must be predicable");
5566 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5567 unsigned ITCond = Bit ? ITState.Cond :
5568 ARMCC::getOppositeCondition(ITState.Cond);
5569 if (Cond != ITCond) {
5570 // Find the condition code Operand to get its SMLoc information.
5572 for (unsigned I = 1; I < Operands.size(); ++I)
5573 if (static_cast<ARMOperand*>(Operands[I])->isCondCode())
5574 CondLoc = Operands[I]->getStartLoc();
5575 return Error(CondLoc, "incorrect condition in IT block; got '" +
5576 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5577 "', but expected '" +
5578 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5580 // Check for non-'al' condition codes outside of the IT block.
5581 } else if (isThumbTwo() && MCID.isPredicable() &&
5582 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5583 ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
5584 Inst.getOpcode() != ARM::t2Bcc)
5585 return Error(Loc, "predicated instructions must be in IT block");
5587 const unsigned Opcode = Inst.getOpcode();
5591 case ARM::LDRD_POST: {
5592 const unsigned RtReg = Inst.getOperand(0).getReg();
5595 if (RtReg == ARM::LR)
5596 return Error(Operands[3]->getStartLoc(),
5599 const unsigned Rt = MRI->getEncodingValue(RtReg);
5600 // Rt must be even-numbered.
5602 return Error(Operands[3]->getStartLoc(),
5603 "Rt must be even-numbered");
5605 // Rt2 must be Rt + 1.
5606 const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5608 return Error(Operands[3]->getStartLoc(),
5609 "destination operands must be sequential");
5611 if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) {
5612 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
5613 // For addressing modes with writeback, the base register needs to be
5614 // different from the destination registers.
5615 if (Rn == Rt || Rn == Rt2)
5616 return Error(Operands[3]->getStartLoc(),
5617 "base register needs to be different from destination "
5624 case ARM::t2LDRD_PRE:
5625 case ARM::t2LDRD_POST: {
5626 // Rt2 must be different from Rt.
5627 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5628 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5630 return Error(Operands[3]->getStartLoc(),
5631 "destination operands can't be identical");
5635 // Rt2 must be Rt + 1.
5636 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5637 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5639 return Error(Operands[3]->getStartLoc(),
5640 "source operands must be sequential");
5644 case ARM::STRD_POST: {
5645 // Rt2 must be Rt + 1.
5646 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5647 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5649 return Error(Operands[3]->getStartLoc(),
5650 "source operands must be sequential");
5655 // Width must be in range [1, 32-lsb].
5656 unsigned LSB = Inst.getOperand(2).getImm();
5657 unsigned Widthm1 = Inst.getOperand(3).getImm();
5658 if (Widthm1 >= 32 - LSB)
5659 return Error(Operands[5]->getStartLoc(),
5660 "bitfield width must be in range [1,32-lsb]");
5663 // Notionally handles ARM::tLDMIA_UPD too.
5665 // If we're parsing Thumb2, the .w variant is available and handles
5666 // most cases that are normally illegal for a Thumb1 LDM instruction.
5667 // We'll make the transformation in processInstruction() if necessary.
5669 // Thumb LDM instructions are writeback iff the base register is not
5670 // in the register list.
5671 unsigned Rn = Inst.getOperand(0).getReg();
5672 bool HasWritebackToken =
5673 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5674 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5675 bool ListContainsBase;
5676 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
5677 return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
5678 "registers must be in range r0-r7");
5679 // If we should have writeback, then there should be a '!' token.
5680 if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
5681 return Error(Operands[2]->getStartLoc(),
5682 "writeback operator '!' expected");
5683 // If we should not have writeback, there must not be a '!'. This is
5684 // true even for the 32-bit wide encodings.
5685 if (ListContainsBase && HasWritebackToken)
5686 return Error(Operands[3]->getStartLoc(),
5687 "writeback operator '!' not allowed when base register "
5688 "in register list");
5692 case ARM::LDMIA_UPD:
5693 case ARM::LDMDB_UPD:
5694 case ARM::LDMIB_UPD:
5695 case ARM::LDMDA_UPD:
5696 // ARM variants loading and updating the same register are only officially
5697 // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
5701 case ARM::t2LDMIA_UPD:
5702 case ARM::t2LDMDB_UPD:
5703 case ARM::t2STMIA_UPD:
5704 case ARM::t2STMDB_UPD: {
5705 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5706 return Error(Operands.back()->getStartLoc(),
5707 "writeback register not allowed in register list");
5710 case ARM::sysLDMIA_UPD:
5711 case ARM::sysLDMDA_UPD:
5712 case ARM::sysLDMDB_UPD:
5713 case ARM::sysLDMIB_UPD:
5714 if (!listContainsReg(Inst, 3, ARM::PC))
5715 return Error(Operands[4]->getStartLoc(),
5716 "writeback register only allowed on system LDM "
5717 "if PC in register-list");
5719 case ARM::sysSTMIA_UPD:
5720 case ARM::sysSTMDA_UPD:
5721 case ARM::sysSTMDB_UPD:
5722 case ARM::sysSTMIB_UPD:
5723 return Error(Operands[2]->getStartLoc(),
5724 "system STM cannot have writeback register");
5727 // The second source operand must be the same register as the destination
5730 // In this case, we must directly check the parsed operands because the
5731 // cvtThumbMultiply() function is written in such a way that it guarantees
5732 // this first statement is always true for the new Inst. Essentially, the
5733 // destination is unconditionally copied into the second source operand
5734 // without checking to see if it matches what we actually parsed.
5735 if (Operands.size() == 6 &&
5736 (((ARMOperand*)Operands[3])->getReg() !=
5737 ((ARMOperand*)Operands[5])->getReg()) &&
5738 (((ARMOperand*)Operands[3])->getReg() !=
5739 ((ARMOperand*)Operands[4])->getReg())) {
5740 return Error(Operands[3]->getStartLoc(),
5741 "destination register must match source register");
5745 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5746 // so only issue a diagnostic for thumb1. The instructions will be
5747 // switched to the t2 encodings in processInstruction() if necessary.
5749 bool ListContainsBase;
5750 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
5752 return Error(Operands[2]->getStartLoc(),
5753 "registers must be in range r0-r7 or pc");
5757 bool ListContainsBase;
5758 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
5760 return Error(Operands[2]->getStartLoc(),
5761 "registers must be in range r0-r7 or lr");
5764 case ARM::tSTMIA_UPD: {
5765 bool ListContainsBase, InvalidLowList;
5766 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
5767 0, ListContainsBase);
5768 if (InvalidLowList && !isThumbTwo())
5769 return Error(Operands[4]->getStartLoc(),
5770 "registers must be in range r0-r7");
5772 // This would be converted to a 32-bit stm, but that's not valid if the
5773 // writeback register is in the list.
5774 if (InvalidLowList && ListContainsBase)
5775 return Error(Operands[4]->getStartLoc(),
5776 "writeback operator '!' not allowed when base register "
5777 "in register list");
5780 case ARM::tADDrSP: {
5781 // If the non-SP source operand and the destination operand are not the
5782 // same, we need thumb2 (for the wide encoding), or we have an error.
5783 if (!isThumbTwo() &&
5784 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5785 return Error(Operands[4]->getStartLoc(),
5786 "source register must be the same as destination");
5790 // Final range checking for Thumb unconditional branch instructions.
5792 if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<11, 1>())
5793 return Error(Operands[2]->getStartLoc(), "branch target out of range");
5796 int op = (Operands[2]->isImm()) ? 2 : 3;
5797 if (!(static_cast<ARMOperand*>(Operands[op]))->isSignedOffset<24, 1>())
5798 return Error(Operands[op]->getStartLoc(), "branch target out of range");
5801 // Final range checking for Thumb conditional branch instructions.
5803 if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<8, 1>())
5804 return Error(Operands[2]->getStartLoc(), "branch target out of range");
5807 int Op = (Operands[2]->isImm()) ? 2 : 3;
5808 if (!(static_cast<ARMOperand*>(Operands[Op]))->isSignedOffset<20, 1>())
5809 return Error(Operands[Op]->getStartLoc(), "branch target out of range");
5817 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5819 default: llvm_unreachable("unexpected opcode!");
5821 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5822 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5823 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5824 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5825 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5826 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5827 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
5828 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5829 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5832 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5833 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5834 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5835 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5836 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5838 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5839 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5840 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5841 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5842 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5844 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
5845 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5846 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5847 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5848 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5851 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5852 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5853 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5854 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5855 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5856 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5857 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5858 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5859 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5860 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5861 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
5862 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5863 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5864 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5865 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5868 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5869 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5870 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5871 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5872 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5873 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5874 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5875 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5876 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5877 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5878 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5879 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5880 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
5881 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5882 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5883 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
5884 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5885 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5888 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5889 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5890 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5891 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5892 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5893 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5894 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5895 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5896 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5897 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5898 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
5899 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5900 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5901 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5902 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5905 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5906 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5907 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5908 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5909 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5910 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5911 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5912 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5913 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5914 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5915 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5916 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5917 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
5918 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5919 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5920 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
5921 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5922 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5926 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
5928 default: llvm_unreachable("unexpected opcode!");
5930 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5931 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5932 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5933 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5934 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5935 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5936 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
5937 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5938 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5941 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5942 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5943 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5944 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5945 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5946 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5947 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5948 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5949 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5950 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5951 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
5952 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5953 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5954 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5955 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5958 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5959 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5960 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5961 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5962 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5963 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5964 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5965 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5966 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5967 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5968 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5969 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5970 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
5971 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5972 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5973 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5974 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5975 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5978 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5979 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5980 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5981 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5982 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5983 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5984 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5985 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5986 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5987 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5988 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
5989 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5990 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5991 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5992 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5995 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5996 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5997 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5998 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5999 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6000 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6001 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
6002 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6003 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6004 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
6005 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6006 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6007 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
6008 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
6009 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
6010 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
6011 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
6012 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
6015 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
6016 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6017 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6018 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
6019 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6020 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
6021 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6022 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6023 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6024 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6025 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
6026 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
6027 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
6028 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
6029 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
6032 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
6033 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6034 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6035 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
6036 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
6037 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6038 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
6039 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6040 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6041 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
6042 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
6043 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6044 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
6045 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
6046 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
6047 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
6048 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
6049 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
6052 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
6053 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6054 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6055 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
6056 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6057 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6058 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
6059 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6060 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6061 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
6062 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6063 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6064 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
6065 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
6066 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
6067 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
6068 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
6069 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
6074 processInstruction(MCInst &Inst,
6075 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
6076 switch (Inst.getOpcode()) {
6077 // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
6078 case ARM::LDRT_POST:
6079 case ARM::LDRBT_POST: {
6080 const unsigned Opcode =
6081 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
6082 : ARM::LDRBT_POST_IMM;
6084 TmpInst.setOpcode(Opcode);
6085 TmpInst.addOperand(Inst.getOperand(0));
6086 TmpInst.addOperand(Inst.getOperand(1));
6087 TmpInst.addOperand(Inst.getOperand(1));
6088 TmpInst.addOperand(MCOperand::CreateReg(0));
6089 TmpInst.addOperand(MCOperand::CreateImm(0));
6090 TmpInst.addOperand(Inst.getOperand(2));
6091 TmpInst.addOperand(Inst.getOperand(3));
6095 // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
6096 case ARM::STRT_POST:
6097 case ARM::STRBT_POST: {
6098 const unsigned Opcode =
6099 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
6100 : ARM::STRBT_POST_IMM;
6102 TmpInst.setOpcode(Opcode);
6103 TmpInst.addOperand(Inst.getOperand(1));
6104 TmpInst.addOperand(Inst.getOperand(0));
6105 TmpInst.addOperand(Inst.getOperand(1));
6106 TmpInst.addOperand(MCOperand::CreateReg(0));
6107 TmpInst.addOperand(MCOperand::CreateImm(0));
6108 TmpInst.addOperand(Inst.getOperand(2));
6109 TmpInst.addOperand(Inst.getOperand(3));
6113 // Alias for alternate form of 'ADR Rd, #imm' instruction.
6115 if (Inst.getOperand(1).getReg() != ARM::PC ||
6116 Inst.getOperand(5).getReg() != 0)
6119 TmpInst.setOpcode(ARM::ADR);
6120 TmpInst.addOperand(Inst.getOperand(0));
6121 TmpInst.addOperand(Inst.getOperand(2));
6122 TmpInst.addOperand(Inst.getOperand(3));
6123 TmpInst.addOperand(Inst.getOperand(4));
6127 // Aliases for alternate PC+imm syntax of LDR instructions.
6128 case ARM::t2LDRpcrel:
6129 // Select the narrow version if the immediate will fit.
6130 if (Inst.getOperand(1).getImm() > 0 &&
6131 Inst.getOperand(1).getImm() <= 0xff &&
6132 !(static_cast<ARMOperand*>(Operands[2])->isToken() &&
6133 static_cast<ARMOperand*>(Operands[2])->getToken() == ".w"))
6134 Inst.setOpcode(ARM::tLDRpci);
6136 Inst.setOpcode(ARM::t2LDRpci);
6138 case ARM::t2LDRBpcrel:
6139 Inst.setOpcode(ARM::t2LDRBpci);
6141 case ARM::t2LDRHpcrel:
6142 Inst.setOpcode(ARM::t2LDRHpci);
6144 case ARM::t2LDRSBpcrel:
6145 Inst.setOpcode(ARM::t2LDRSBpci);
6147 case ARM::t2LDRSHpcrel:
6148 Inst.setOpcode(ARM::t2LDRSHpci);
6150 // Handle NEON VST complex aliases.
6151 case ARM::VST1LNdWB_register_Asm_8:
6152 case ARM::VST1LNdWB_register_Asm_16:
6153 case ARM::VST1LNdWB_register_Asm_32: {
6155 // Shuffle the operands around so the lane index operand is in the
6158 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6159 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6160 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6161 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6162 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6163 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6164 TmpInst.addOperand(Inst.getOperand(1)); // lane
6165 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6166 TmpInst.addOperand(Inst.getOperand(6));
6171 case ARM::VST2LNdWB_register_Asm_8:
6172 case ARM::VST2LNdWB_register_Asm_16:
6173 case ARM::VST2LNdWB_register_Asm_32:
6174 case ARM::VST2LNqWB_register_Asm_16:
6175 case ARM::VST2LNqWB_register_Asm_32: {
6177 // Shuffle the operands around so the lane index operand is in the
6180 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6181 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6182 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6183 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6184 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6185 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6186 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6188 TmpInst.addOperand(Inst.getOperand(1)); // lane
6189 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6190 TmpInst.addOperand(Inst.getOperand(6));
6195 case ARM::VST3LNdWB_register_Asm_8:
6196 case ARM::VST3LNdWB_register_Asm_16:
6197 case ARM::VST3LNdWB_register_Asm_32:
6198 case ARM::VST3LNqWB_register_Asm_16:
6199 case ARM::VST3LNqWB_register_Asm_32: {
6201 // Shuffle the operands around so the lane index operand is in the
6204 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6205 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6206 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6207 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6208 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6209 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6210 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6212 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6214 TmpInst.addOperand(Inst.getOperand(1)); // lane
6215 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6216 TmpInst.addOperand(Inst.getOperand(6));
6221 case ARM::VST4LNdWB_register_Asm_8:
6222 case ARM::VST4LNdWB_register_Asm_16:
6223 case ARM::VST4LNdWB_register_Asm_32:
6224 case ARM::VST4LNqWB_register_Asm_16:
6225 case ARM::VST4LNqWB_register_Asm_32: {
6227 // Shuffle the operands around so the lane index operand is in the
6230 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6231 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6232 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6233 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6234 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6235 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6236 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6238 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6240 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6242 TmpInst.addOperand(Inst.getOperand(1)); // lane
6243 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6244 TmpInst.addOperand(Inst.getOperand(6));
6249 case ARM::VST1LNdWB_fixed_Asm_8:
6250 case ARM::VST1LNdWB_fixed_Asm_16:
6251 case ARM::VST1LNdWB_fixed_Asm_32: {
6253 // Shuffle the operands around so the lane index operand is in the
6256 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6257 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6258 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6259 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6260 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6261 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6262 TmpInst.addOperand(Inst.getOperand(1)); // lane
6263 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6264 TmpInst.addOperand(Inst.getOperand(5));
6269 case ARM::VST2LNdWB_fixed_Asm_8:
6270 case ARM::VST2LNdWB_fixed_Asm_16:
6271 case ARM::VST2LNdWB_fixed_Asm_32:
6272 case ARM::VST2LNqWB_fixed_Asm_16:
6273 case ARM::VST2LNqWB_fixed_Asm_32: {
6275 // Shuffle the operands around so the lane index operand is in the
6278 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6279 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6280 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6281 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6282 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6283 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6284 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6286 TmpInst.addOperand(Inst.getOperand(1)); // lane
6287 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6288 TmpInst.addOperand(Inst.getOperand(5));
6293 case ARM::VST3LNdWB_fixed_Asm_8:
6294 case ARM::VST3LNdWB_fixed_Asm_16:
6295 case ARM::VST3LNdWB_fixed_Asm_32:
6296 case ARM::VST3LNqWB_fixed_Asm_16:
6297 case ARM::VST3LNqWB_fixed_Asm_32: {
6299 // Shuffle the operands around so the lane index operand is in the
6302 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6303 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6304 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6305 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6306 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6307 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6308 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6310 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6312 TmpInst.addOperand(Inst.getOperand(1)); // lane
6313 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6314 TmpInst.addOperand(Inst.getOperand(5));
6319 case ARM::VST4LNdWB_fixed_Asm_8:
6320 case ARM::VST4LNdWB_fixed_Asm_16:
6321 case ARM::VST4LNdWB_fixed_Asm_32:
6322 case ARM::VST4LNqWB_fixed_Asm_16:
6323 case ARM::VST4LNqWB_fixed_Asm_32: {
6325 // Shuffle the operands around so the lane index operand is in the
6328 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6329 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6330 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6331 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6332 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6333 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6334 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6336 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6338 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6340 TmpInst.addOperand(Inst.getOperand(1)); // lane
6341 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6342 TmpInst.addOperand(Inst.getOperand(5));
6347 case ARM::VST1LNdAsm_8:
6348 case ARM::VST1LNdAsm_16:
6349 case ARM::VST1LNdAsm_32: {
6351 // Shuffle the operands around so the lane index operand is in the
6354 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6355 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6356 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6357 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6358 TmpInst.addOperand(Inst.getOperand(1)); // lane
6359 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6360 TmpInst.addOperand(Inst.getOperand(5));
6365 case ARM::VST2LNdAsm_8:
6366 case ARM::VST2LNdAsm_16:
6367 case ARM::VST2LNdAsm_32:
6368 case ARM::VST2LNqAsm_16:
6369 case ARM::VST2LNqAsm_32: {
6371 // Shuffle the operands around so the lane index operand is in the
6374 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6375 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6376 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6377 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6378 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6380 TmpInst.addOperand(Inst.getOperand(1)); // lane
6381 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6382 TmpInst.addOperand(Inst.getOperand(5));
6387 case ARM::VST3LNdAsm_8:
6388 case ARM::VST3LNdAsm_16:
6389 case ARM::VST3LNdAsm_32:
6390 case ARM::VST3LNqAsm_16:
6391 case ARM::VST3LNqAsm_32: {
6393 // Shuffle the operands around so the lane index operand is in the
6396 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6397 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6398 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6399 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6400 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6402 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6404 TmpInst.addOperand(Inst.getOperand(1)); // lane
6405 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6406 TmpInst.addOperand(Inst.getOperand(5));
6411 case ARM::VST4LNdAsm_8:
6412 case ARM::VST4LNdAsm_16:
6413 case ARM::VST4LNdAsm_32:
6414 case ARM::VST4LNqAsm_16:
6415 case ARM::VST4LNqAsm_32: {
6417 // Shuffle the operands around so the lane index operand is in the
6420 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6421 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6422 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6423 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6424 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6426 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6428 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6430 TmpInst.addOperand(Inst.getOperand(1)); // lane
6431 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6432 TmpInst.addOperand(Inst.getOperand(5));
6437 // Handle NEON VLD complex aliases.
6438 case ARM::VLD1LNdWB_register_Asm_8:
6439 case ARM::VLD1LNdWB_register_Asm_16:
6440 case ARM::VLD1LNdWB_register_Asm_32: {
6442 // Shuffle the operands around so the lane index operand is in the
6445 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6446 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6447 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6448 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6449 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6450 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6451 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6452 TmpInst.addOperand(Inst.getOperand(1)); // lane
6453 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6454 TmpInst.addOperand(Inst.getOperand(6));
6459 case ARM::VLD2LNdWB_register_Asm_8:
6460 case ARM::VLD2LNdWB_register_Asm_16:
6461 case ARM::VLD2LNdWB_register_Asm_32:
6462 case ARM::VLD2LNqWB_register_Asm_16:
6463 case ARM::VLD2LNqWB_register_Asm_32: {
6465 // Shuffle the operands around so the lane index operand is in the
6468 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6469 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6470 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6472 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6473 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6474 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6475 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6476 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6477 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6479 TmpInst.addOperand(Inst.getOperand(1)); // lane
6480 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6481 TmpInst.addOperand(Inst.getOperand(6));
6486 case ARM::VLD3LNdWB_register_Asm_8:
6487 case ARM::VLD3LNdWB_register_Asm_16:
6488 case ARM::VLD3LNdWB_register_Asm_32:
6489 case ARM::VLD3LNqWB_register_Asm_16:
6490 case ARM::VLD3LNqWB_register_Asm_32: {
6492 // Shuffle the operands around so the lane index operand is in the
6495 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6496 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6497 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6499 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6501 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6502 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6503 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6504 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6505 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6506 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6508 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6510 TmpInst.addOperand(Inst.getOperand(1)); // lane
6511 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6512 TmpInst.addOperand(Inst.getOperand(6));
6517 case ARM::VLD4LNdWB_register_Asm_8:
6518 case ARM::VLD4LNdWB_register_Asm_16:
6519 case ARM::VLD4LNdWB_register_Asm_32:
6520 case ARM::VLD4LNqWB_register_Asm_16:
6521 case ARM::VLD4LNqWB_register_Asm_32: {
6523 // Shuffle the operands around so the lane index operand is in the
6526 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6527 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6528 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6530 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6532 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6534 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6535 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6536 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6537 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6538 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6539 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6541 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6543 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6545 TmpInst.addOperand(Inst.getOperand(1)); // lane
6546 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6547 TmpInst.addOperand(Inst.getOperand(6));
6552 case ARM::VLD1LNdWB_fixed_Asm_8:
6553 case ARM::VLD1LNdWB_fixed_Asm_16:
6554 case ARM::VLD1LNdWB_fixed_Asm_32: {
6556 // Shuffle the operands around so the lane index operand is in the
6559 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6560 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6561 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6562 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6563 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6564 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6565 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6566 TmpInst.addOperand(Inst.getOperand(1)); // lane
6567 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6568 TmpInst.addOperand(Inst.getOperand(5));
6573 case ARM::VLD2LNdWB_fixed_Asm_8:
6574 case ARM::VLD2LNdWB_fixed_Asm_16:
6575 case ARM::VLD2LNdWB_fixed_Asm_32:
6576 case ARM::VLD2LNqWB_fixed_Asm_16:
6577 case ARM::VLD2LNqWB_fixed_Asm_32: {
6579 // Shuffle the operands around so the lane index operand is in the
6582 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6583 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6584 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6586 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6587 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6588 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6589 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6590 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6591 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6593 TmpInst.addOperand(Inst.getOperand(1)); // lane
6594 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6595 TmpInst.addOperand(Inst.getOperand(5));
6600 case ARM::VLD3LNdWB_fixed_Asm_8:
6601 case ARM::VLD3LNdWB_fixed_Asm_16:
6602 case ARM::VLD3LNdWB_fixed_Asm_32:
6603 case ARM::VLD3LNqWB_fixed_Asm_16:
6604 case ARM::VLD3LNqWB_fixed_Asm_32: {
6606 // Shuffle the operands around so the lane index operand is in the
6609 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6610 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6611 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6613 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6615 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6616 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6617 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6618 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6619 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6620 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6622 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6624 TmpInst.addOperand(Inst.getOperand(1)); // lane
6625 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6626 TmpInst.addOperand(Inst.getOperand(5));
6631 case ARM::VLD4LNdWB_fixed_Asm_8:
6632 case ARM::VLD4LNdWB_fixed_Asm_16:
6633 case ARM::VLD4LNdWB_fixed_Asm_32:
6634 case ARM::VLD4LNqWB_fixed_Asm_16:
6635 case ARM::VLD4LNqWB_fixed_Asm_32: {
6637 // Shuffle the operands around so the lane index operand is in the
6640 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6641 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6642 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6644 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6646 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6648 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6649 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6650 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6651 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6652 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6653 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6655 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6657 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6659 TmpInst.addOperand(Inst.getOperand(1)); // lane
6660 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6661 TmpInst.addOperand(Inst.getOperand(5));
6666 case ARM::VLD1LNdAsm_8:
6667 case ARM::VLD1LNdAsm_16:
6668 case ARM::VLD1LNdAsm_32: {
6670 // Shuffle the operands around so the lane index operand is in the
6673 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6674 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6675 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6676 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6677 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6678 TmpInst.addOperand(Inst.getOperand(1)); // lane
6679 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6680 TmpInst.addOperand(Inst.getOperand(5));
6685 case ARM::VLD2LNdAsm_8:
6686 case ARM::VLD2LNdAsm_16:
6687 case ARM::VLD2LNdAsm_32:
6688 case ARM::VLD2LNqAsm_16:
6689 case ARM::VLD2LNqAsm_32: {
6691 // Shuffle the operands around so the lane index operand is in the
6694 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6695 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6696 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6698 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6699 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6700 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6701 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6703 TmpInst.addOperand(Inst.getOperand(1)); // lane
6704 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6705 TmpInst.addOperand(Inst.getOperand(5));
6710 case ARM::VLD3LNdAsm_8:
6711 case ARM::VLD3LNdAsm_16:
6712 case ARM::VLD3LNdAsm_32:
6713 case ARM::VLD3LNqAsm_16:
6714 case ARM::VLD3LNqAsm_32: {
6716 // Shuffle the operands around so the lane index operand is in the
6719 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6720 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6721 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6723 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6725 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6726 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6727 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6728 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6730 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6732 TmpInst.addOperand(Inst.getOperand(1)); // lane
6733 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6734 TmpInst.addOperand(Inst.getOperand(5));
6739 case ARM::VLD4LNdAsm_8:
6740 case ARM::VLD4LNdAsm_16:
6741 case ARM::VLD4LNdAsm_32:
6742 case ARM::VLD4LNqAsm_16:
6743 case ARM::VLD4LNqAsm_32: {
6745 // Shuffle the operands around so the lane index operand is in the
6748 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6749 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6750 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6752 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6754 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6756 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6757 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6758 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6759 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6761 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6763 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6765 TmpInst.addOperand(Inst.getOperand(1)); // lane
6766 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6767 TmpInst.addOperand(Inst.getOperand(5));
6772 // VLD3DUP single 3-element structure to all lanes instructions.
6773 case ARM::VLD3DUPdAsm_8:
6774 case ARM::VLD3DUPdAsm_16:
6775 case ARM::VLD3DUPdAsm_32:
6776 case ARM::VLD3DUPqAsm_8:
6777 case ARM::VLD3DUPqAsm_16:
6778 case ARM::VLD3DUPqAsm_32: {
6781 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6782 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6783 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6785 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6787 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6788 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6789 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6790 TmpInst.addOperand(Inst.getOperand(4));
6795 case ARM::VLD3DUPdWB_fixed_Asm_8:
6796 case ARM::VLD3DUPdWB_fixed_Asm_16:
6797 case ARM::VLD3DUPdWB_fixed_Asm_32:
6798 case ARM::VLD3DUPqWB_fixed_Asm_8:
6799 case ARM::VLD3DUPqWB_fixed_Asm_16:
6800 case ARM::VLD3DUPqWB_fixed_Asm_32: {
6803 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6804 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6805 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6807 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6809 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6810 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6811 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6812 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6813 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6814 TmpInst.addOperand(Inst.getOperand(4));
6819 case ARM::VLD3DUPdWB_register_Asm_8:
6820 case ARM::VLD3DUPdWB_register_Asm_16:
6821 case ARM::VLD3DUPdWB_register_Asm_32:
6822 case ARM::VLD3DUPqWB_register_Asm_8:
6823 case ARM::VLD3DUPqWB_register_Asm_16:
6824 case ARM::VLD3DUPqWB_register_Asm_32: {
6827 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6828 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6829 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6831 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6833 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6834 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6835 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6836 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6837 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6838 TmpInst.addOperand(Inst.getOperand(5));
6843 // VLD3 multiple 3-element structure instructions.
6844 case ARM::VLD3dAsm_8:
6845 case ARM::VLD3dAsm_16:
6846 case ARM::VLD3dAsm_32:
6847 case ARM::VLD3qAsm_8:
6848 case ARM::VLD3qAsm_16:
6849 case ARM::VLD3qAsm_32: {
6852 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6853 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6854 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6856 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6858 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6859 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6860 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6861 TmpInst.addOperand(Inst.getOperand(4));
6866 case ARM::VLD3dWB_fixed_Asm_8:
6867 case ARM::VLD3dWB_fixed_Asm_16:
6868 case ARM::VLD3dWB_fixed_Asm_32:
6869 case ARM::VLD3qWB_fixed_Asm_8:
6870 case ARM::VLD3qWB_fixed_Asm_16:
6871 case ARM::VLD3qWB_fixed_Asm_32: {
6874 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6875 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6876 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6878 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6880 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6881 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6882 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6883 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6884 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6885 TmpInst.addOperand(Inst.getOperand(4));
6890 case ARM::VLD3dWB_register_Asm_8:
6891 case ARM::VLD3dWB_register_Asm_16:
6892 case ARM::VLD3dWB_register_Asm_32:
6893 case ARM::VLD3qWB_register_Asm_8:
6894 case ARM::VLD3qWB_register_Asm_16:
6895 case ARM::VLD3qWB_register_Asm_32: {
6898 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6899 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6900 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6902 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6904 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6905 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6906 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6907 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6908 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6909 TmpInst.addOperand(Inst.getOperand(5));
6914 // VLD4DUP single 3-element structure to all lanes instructions.
6915 case ARM::VLD4DUPdAsm_8:
6916 case ARM::VLD4DUPdAsm_16:
6917 case ARM::VLD4DUPdAsm_32:
6918 case ARM::VLD4DUPqAsm_8:
6919 case ARM::VLD4DUPqAsm_16:
6920 case ARM::VLD4DUPqAsm_32: {
6923 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6924 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6925 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6927 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6929 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6931 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6932 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6933 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6934 TmpInst.addOperand(Inst.getOperand(4));
6939 case ARM::VLD4DUPdWB_fixed_Asm_8:
6940 case ARM::VLD4DUPdWB_fixed_Asm_16:
6941 case ARM::VLD4DUPdWB_fixed_Asm_32:
6942 case ARM::VLD4DUPqWB_fixed_Asm_8:
6943 case ARM::VLD4DUPqWB_fixed_Asm_16:
6944 case ARM::VLD4DUPqWB_fixed_Asm_32: {
6947 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6948 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6949 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6951 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6953 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6955 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6956 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6957 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6958 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6959 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6960 TmpInst.addOperand(Inst.getOperand(4));
6965 case ARM::VLD4DUPdWB_register_Asm_8:
6966 case ARM::VLD4DUPdWB_register_Asm_16:
6967 case ARM::VLD4DUPdWB_register_Asm_32:
6968 case ARM::VLD4DUPqWB_register_Asm_8:
6969 case ARM::VLD4DUPqWB_register_Asm_16:
6970 case ARM::VLD4DUPqWB_register_Asm_32: {
6973 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6974 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6975 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6977 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6979 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6981 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6982 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6983 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6984 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6985 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6986 TmpInst.addOperand(Inst.getOperand(5));
6991 // VLD4 multiple 4-element structure instructions.
6992 case ARM::VLD4dAsm_8:
6993 case ARM::VLD4dAsm_16:
6994 case ARM::VLD4dAsm_32:
6995 case ARM::VLD4qAsm_8:
6996 case ARM::VLD4qAsm_16:
6997 case ARM::VLD4qAsm_32: {
7000 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7001 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7002 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7004 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7006 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7008 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7009 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7010 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7011 TmpInst.addOperand(Inst.getOperand(4));
7016 case ARM::VLD4dWB_fixed_Asm_8:
7017 case ARM::VLD4dWB_fixed_Asm_16:
7018 case ARM::VLD4dWB_fixed_Asm_32:
7019 case ARM::VLD4qWB_fixed_Asm_8:
7020 case ARM::VLD4qWB_fixed_Asm_16:
7021 case ARM::VLD4qWB_fixed_Asm_32: {
7024 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7025 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7026 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7028 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7030 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7032 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7033 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7034 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7035 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7036 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7037 TmpInst.addOperand(Inst.getOperand(4));
7042 case ARM::VLD4dWB_register_Asm_8:
7043 case ARM::VLD4dWB_register_Asm_16:
7044 case ARM::VLD4dWB_register_Asm_32:
7045 case ARM::VLD4qWB_register_Asm_8:
7046 case ARM::VLD4qWB_register_Asm_16:
7047 case ARM::VLD4qWB_register_Asm_32: {
7050 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7051 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7052 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7054 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7056 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7058 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7059 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7060 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7061 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7062 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7063 TmpInst.addOperand(Inst.getOperand(5));
7068 // VST3 multiple 3-element structure instructions.
7069 case ARM::VST3dAsm_8:
7070 case ARM::VST3dAsm_16:
7071 case ARM::VST3dAsm_32:
7072 case ARM::VST3qAsm_8:
7073 case ARM::VST3qAsm_16:
7074 case ARM::VST3qAsm_32: {
7077 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7078 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7079 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7080 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7081 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7083 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7085 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7086 TmpInst.addOperand(Inst.getOperand(4));
7091 case ARM::VST3dWB_fixed_Asm_8:
7092 case ARM::VST3dWB_fixed_Asm_16:
7093 case ARM::VST3dWB_fixed_Asm_32:
7094 case ARM::VST3qWB_fixed_Asm_8:
7095 case ARM::VST3qWB_fixed_Asm_16:
7096 case ARM::VST3qWB_fixed_Asm_32: {
7099 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7100 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7101 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7102 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7103 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7104 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7105 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7107 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7109 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7110 TmpInst.addOperand(Inst.getOperand(4));
7115 case ARM::VST3dWB_register_Asm_8:
7116 case ARM::VST3dWB_register_Asm_16:
7117 case ARM::VST3dWB_register_Asm_32:
7118 case ARM::VST3qWB_register_Asm_8:
7119 case ARM::VST3qWB_register_Asm_16:
7120 case ARM::VST3qWB_register_Asm_32: {
7123 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7124 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7125 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7126 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7127 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7128 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7129 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7131 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7133 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7134 TmpInst.addOperand(Inst.getOperand(5));
7139 // VST4 multiple 3-element structure instructions.
7140 case ARM::VST4dAsm_8:
7141 case ARM::VST4dAsm_16:
7142 case ARM::VST4dAsm_32:
7143 case ARM::VST4qAsm_8:
7144 case ARM::VST4qAsm_16:
7145 case ARM::VST4qAsm_32: {
7148 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7149 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7150 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7151 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7152 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7154 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7156 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7158 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7159 TmpInst.addOperand(Inst.getOperand(4));
7164 case ARM::VST4dWB_fixed_Asm_8:
7165 case ARM::VST4dWB_fixed_Asm_16:
7166 case ARM::VST4dWB_fixed_Asm_32:
7167 case ARM::VST4qWB_fixed_Asm_8:
7168 case ARM::VST4qWB_fixed_Asm_16:
7169 case ARM::VST4qWB_fixed_Asm_32: {
7172 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7173 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7174 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7175 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7176 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7177 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7178 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7180 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7182 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7184 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7185 TmpInst.addOperand(Inst.getOperand(4));
7190 case ARM::VST4dWB_register_Asm_8:
7191 case ARM::VST4dWB_register_Asm_16:
7192 case ARM::VST4dWB_register_Asm_32:
7193 case ARM::VST4qWB_register_Asm_8:
7194 case ARM::VST4qWB_register_Asm_16:
7195 case ARM::VST4qWB_register_Asm_32: {
7198 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7199 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7200 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7201 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7202 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7203 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7204 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7206 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7208 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7210 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7211 TmpInst.addOperand(Inst.getOperand(5));
7216 // Handle encoding choice for the shift-immediate instructions.
7219 case ARM::t2ASRri: {
7220 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7221 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7222 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
7223 !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
7224 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
7226 switch (Inst.getOpcode()) {
7227 default: llvm_unreachable("unexpected opcode");
7228 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
7229 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
7230 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
7232 // The Thumb1 operands aren't in the same order. Awesome, eh?
7234 TmpInst.setOpcode(NewOpc);
7235 TmpInst.addOperand(Inst.getOperand(0));
7236 TmpInst.addOperand(Inst.getOperand(5));
7237 TmpInst.addOperand(Inst.getOperand(1));
7238 TmpInst.addOperand(Inst.getOperand(2));
7239 TmpInst.addOperand(Inst.getOperand(3));
7240 TmpInst.addOperand(Inst.getOperand(4));
7247 // Handle the Thumb2 mode MOV complex aliases.
7249 case ARM::t2MOVSsr: {
7250 // Which instruction to expand to depends on the CCOut operand and
7251 // whether we're in an IT block if the register operands are low
7253 bool isNarrow = false;
7254 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7255 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7256 isARMLowRegister(Inst.getOperand(2).getReg()) &&
7257 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7258 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
7262 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
7263 default: llvm_unreachable("unexpected opcode!");
7264 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7265 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7266 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7267 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
7269 TmpInst.setOpcode(newOpc);
7270 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7272 TmpInst.addOperand(MCOperand::CreateReg(
7273 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7274 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7275 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7276 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7277 TmpInst.addOperand(Inst.getOperand(5));
7279 TmpInst.addOperand(MCOperand::CreateReg(
7280 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7285 case ARM::t2MOVSsi: {
7286 // Which instruction to expand to depends on the CCOut operand and
7287 // whether we're in an IT block if the register operands are low
7289 bool isNarrow = false;
7290 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7291 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7292 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
7296 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
7297 default: llvm_unreachable("unexpected opcode!");
7298 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7299 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7300 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7301 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7302 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7304 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
7305 if (Amount == 32) Amount = 0;
7306 TmpInst.setOpcode(newOpc);
7307 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7309 TmpInst.addOperand(MCOperand::CreateReg(
7310 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7311 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7312 if (newOpc != ARM::t2RRX)
7313 TmpInst.addOperand(MCOperand::CreateImm(Amount));
7314 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7315 TmpInst.addOperand(Inst.getOperand(4));
7317 TmpInst.addOperand(MCOperand::CreateReg(
7318 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7322 // Handle the ARM mode MOV complex aliases.
7327 ARM_AM::ShiftOpc ShiftTy;
7328 switch(Inst.getOpcode()) {
7329 default: llvm_unreachable("unexpected opcode!");
7330 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
7331 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
7332 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
7333 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
7335 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
7337 TmpInst.setOpcode(ARM::MOVsr);
7338 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7339 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7340 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7341 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7342 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7343 TmpInst.addOperand(Inst.getOperand(4));
7344 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7352 ARM_AM::ShiftOpc ShiftTy;
7353 switch(Inst.getOpcode()) {
7354 default: llvm_unreachable("unexpected opcode!");
7355 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
7356 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
7357 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7358 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
7360 // A shift by zero is a plain MOVr, not a MOVsi.
7361 unsigned Amt = Inst.getOperand(2).getImm();
7362 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
7363 // A shift by 32 should be encoded as 0 when permitted
7364 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
7366 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
7368 TmpInst.setOpcode(Opc);
7369 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7370 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7371 if (Opc == ARM::MOVsi)
7372 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7373 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7374 TmpInst.addOperand(Inst.getOperand(4));
7375 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7380 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
7382 TmpInst.setOpcode(ARM::MOVsi);
7383 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7384 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7385 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7386 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7387 TmpInst.addOperand(Inst.getOperand(3));
7388 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7392 case ARM::t2LDMIA_UPD: {
7393 // If this is a load of a single register, then we should use
7394 // a post-indexed LDR instruction instead, per the ARM ARM.
7395 if (Inst.getNumOperands() != 5)
7398 TmpInst.setOpcode(ARM::t2LDR_POST);
7399 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7400 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7401 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7402 TmpInst.addOperand(MCOperand::CreateImm(4));
7403 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7404 TmpInst.addOperand(Inst.getOperand(3));
7408 case ARM::t2STMDB_UPD: {
7409 // If this is a store of a single register, then we should use
7410 // a pre-indexed STR instruction instead, per the ARM ARM.
7411 if (Inst.getNumOperands() != 5)
7414 TmpInst.setOpcode(ARM::t2STR_PRE);
7415 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7416 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7417 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7418 TmpInst.addOperand(MCOperand::CreateImm(-4));
7419 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7420 TmpInst.addOperand(Inst.getOperand(3));
7424 case ARM::LDMIA_UPD:
7425 // If this is a load of a single register via a 'pop', then we should use
7426 // a post-indexed LDR instruction instead, per the ARM ARM.
7427 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
7428 Inst.getNumOperands() == 5) {
7430 TmpInst.setOpcode(ARM::LDR_POST_IMM);
7431 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7432 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7433 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7434 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
7435 TmpInst.addOperand(MCOperand::CreateImm(4));
7436 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7437 TmpInst.addOperand(Inst.getOperand(3));
7442 case ARM::STMDB_UPD:
7443 // If this is a store of a single register via a 'push', then we should use
7444 // a pre-indexed STR instruction instead, per the ARM ARM.
7445 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
7446 Inst.getNumOperands() == 5) {
7448 TmpInst.setOpcode(ARM::STR_PRE_IMM);
7449 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7450 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7451 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7452 TmpInst.addOperand(MCOperand::CreateImm(-4));
7453 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7454 TmpInst.addOperand(Inst.getOperand(3));
7458 case ARM::t2ADDri12:
7459 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7460 // mnemonic was used (not "addw"), encoding T3 is preferred.
7461 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
7462 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7464 Inst.setOpcode(ARM::t2ADDri);
7465 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7467 case ARM::t2SUBri12:
7468 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7469 // mnemonic was used (not "subw"), encoding T3 is preferred.
7470 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7471 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7473 Inst.setOpcode(ARM::t2SUBri);
7474 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7477 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7478 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7479 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7480 // to encoding T1 if <Rd> is omitted."
7481 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7482 Inst.setOpcode(ARM::tADDi3);
7487 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7488 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7489 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7490 // to encoding T1 if <Rd> is omitted."
7491 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7492 Inst.setOpcode(ARM::tSUBi3);
7497 case ARM::t2SUBri: {
7498 // If the destination and first source operand are the same, and
7499 // the flags are compatible with the current IT status, use encoding T2
7500 // instead of T3. For compatibility with the system 'as'. Make sure the
7501 // wide encoding wasn't explicit.
7502 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7503 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7504 (unsigned)Inst.getOperand(2).getImm() > 255 ||
7505 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7506 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7507 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7508 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7511 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7512 ARM::tADDi8 : ARM::tSUBi8);
7513 TmpInst.addOperand(Inst.getOperand(0));
7514 TmpInst.addOperand(Inst.getOperand(5));
7515 TmpInst.addOperand(Inst.getOperand(0));
7516 TmpInst.addOperand(Inst.getOperand(2));
7517 TmpInst.addOperand(Inst.getOperand(3));
7518 TmpInst.addOperand(Inst.getOperand(4));
7522 case ARM::t2ADDrr: {
7523 // If the destination and first source operand are the same, and
7524 // there's no setting of the flags, use encoding T2 instead of T3.
7525 // Note that this is only for ADD, not SUB. This mirrors the system
7526 // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7527 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7528 Inst.getOperand(5).getReg() != 0 ||
7529 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7530 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7533 TmpInst.setOpcode(ARM::tADDhirr);
7534 TmpInst.addOperand(Inst.getOperand(0));
7535 TmpInst.addOperand(Inst.getOperand(0));
7536 TmpInst.addOperand(Inst.getOperand(2));
7537 TmpInst.addOperand(Inst.getOperand(3));
7538 TmpInst.addOperand(Inst.getOperand(4));
7542 case ARM::tADDrSP: {
7543 // If the non-SP source operand and the destination operand are not the
7544 // same, we need to use the 32-bit encoding if it's available.
7545 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7546 Inst.setOpcode(ARM::t2ADDrr);
7547 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7553 // A Thumb conditional branch outside of an IT block is a tBcc.
7554 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7555 Inst.setOpcode(ARM::tBcc);
7560 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7561 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7562 Inst.setOpcode(ARM::t2Bcc);
7567 // If the conditional is AL or we're in an IT block, we really want t2B.
7568 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7569 Inst.setOpcode(ARM::t2B);
7574 // If the conditional is AL, we really want tB.
7575 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7576 Inst.setOpcode(ARM::tB);
7581 // If the register list contains any high registers, or if the writeback
7582 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7583 // instead if we're in Thumb2. Otherwise, this should have generated
7584 // an error in validateInstruction().
7585 unsigned Rn = Inst.getOperand(0).getReg();
7586 bool hasWritebackToken =
7587 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7588 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7589 bool listContainsBase;
7590 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7591 (!listContainsBase && !hasWritebackToken) ||
7592 (listContainsBase && hasWritebackToken)) {
7593 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7594 assert (isThumbTwo());
7595 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7596 // If we're switching to the updating version, we need to insert
7597 // the writeback tied operand.
7598 if (hasWritebackToken)
7599 Inst.insert(Inst.begin(),
7600 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7605 case ARM::tSTMIA_UPD: {
7606 // If the register list contains any high registers, we need to use
7607 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7608 // should have generated an error in validateInstruction().
7609 unsigned Rn = Inst.getOperand(0).getReg();
7610 bool listContainsBase;
7611 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7612 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7613 assert (isThumbTwo());
7614 Inst.setOpcode(ARM::t2STMIA_UPD);
7620 bool listContainsBase;
7621 // If the register list contains any high registers, we need to use
7622 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7623 // should have generated an error in validateInstruction().
7624 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7626 assert (isThumbTwo());
7627 Inst.setOpcode(ARM::t2LDMIA_UPD);
7628 // Add the base register and writeback operands.
7629 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7630 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7634 bool listContainsBase;
7635 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7637 assert (isThumbTwo());
7638 Inst.setOpcode(ARM::t2STMDB_UPD);
7639 // Add the base register and writeback operands.
7640 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7641 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7645 // If we can use the 16-bit encoding and the user didn't explicitly
7646 // request the 32-bit variant, transform it here.
7647 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7648 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7649 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7650 Inst.getOperand(4).getReg() == ARM::CPSR) ||
7651 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7652 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7653 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7654 // The operands aren't in the same order for tMOVi8...
7656 TmpInst.setOpcode(ARM::tMOVi8);
7657 TmpInst.addOperand(Inst.getOperand(0));
7658 TmpInst.addOperand(Inst.getOperand(4));
7659 TmpInst.addOperand(Inst.getOperand(1));
7660 TmpInst.addOperand(Inst.getOperand(2));
7661 TmpInst.addOperand(Inst.getOperand(3));
7668 // If we can use the 16-bit encoding and the user didn't explicitly
7669 // request the 32-bit variant, transform it here.
7670 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7671 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7672 Inst.getOperand(2).getImm() == ARMCC::AL &&
7673 Inst.getOperand(4).getReg() == ARM::CPSR &&
7674 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7675 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7676 // The operands aren't the same for tMOV[S]r... (no cc_out)
7678 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7679 TmpInst.addOperand(Inst.getOperand(0));
7680 TmpInst.addOperand(Inst.getOperand(1));
7681 TmpInst.addOperand(Inst.getOperand(2));
7682 TmpInst.addOperand(Inst.getOperand(3));
7692 // If we can use the 16-bit encoding and the user didn't explicitly
7693 // request the 32-bit variant, transform it here.
7694 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7695 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7696 Inst.getOperand(2).getImm() == 0 &&
7697 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7698 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7700 switch (Inst.getOpcode()) {
7701 default: llvm_unreachable("Illegal opcode!");
7702 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7703 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7704 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7705 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7707 // The operands aren't the same for thumb1 (no rotate operand).
7709 TmpInst.setOpcode(NewOpc);
7710 TmpInst.addOperand(Inst.getOperand(0));
7711 TmpInst.addOperand(Inst.getOperand(1));
7712 TmpInst.addOperand(Inst.getOperand(3));
7713 TmpInst.addOperand(Inst.getOperand(4));
7720 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7721 // rrx shifts and asr/lsr of #32 is encoded as 0
7722 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7724 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7725 // Shifting by zero is accepted as a vanilla 'MOVr'
7727 TmpInst.setOpcode(ARM::MOVr);
7728 TmpInst.addOperand(Inst.getOperand(0));
7729 TmpInst.addOperand(Inst.getOperand(1));
7730 TmpInst.addOperand(Inst.getOperand(3));
7731 TmpInst.addOperand(Inst.getOperand(4));
7732 TmpInst.addOperand(Inst.getOperand(5));
7745 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7746 if (SOpc == ARM_AM::rrx) return false;
7747 switch (Inst.getOpcode()) {
7748 default: llvm_unreachable("unexpected opcode!");
7749 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7750 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7751 case ARM::EORrsi: newOpc = ARM::EORrr; break;
7752 case ARM::BICrsi: newOpc = ARM::BICrr; break;
7753 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7754 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7756 // If the shift is by zero, use the non-shifted instruction definition.
7757 // The exception is for right shifts, where 0 == 32
7758 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7759 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7761 TmpInst.setOpcode(newOpc);
7762 TmpInst.addOperand(Inst.getOperand(0));
7763 TmpInst.addOperand(Inst.getOperand(1));
7764 TmpInst.addOperand(Inst.getOperand(2));
7765 TmpInst.addOperand(Inst.getOperand(4));
7766 TmpInst.addOperand(Inst.getOperand(5));
7767 TmpInst.addOperand(Inst.getOperand(6));
7775 // The mask bits for all but the first condition are represented as
7776 // the low bit of the condition code value implies 't'. We currently
7777 // always have 1 implies 't', so XOR toggle the bits if the low bit
7778 // of the condition code is zero.
7779 MCOperand &MO = Inst.getOperand(1);
7780 unsigned Mask = MO.getImm();
7781 unsigned OrigMask = Mask;
7782 unsigned TZ = countTrailingZeros(Mask);
7783 if ((Inst.getOperand(0).getImm() & 1) == 0) {
7784 assert(Mask && TZ <= 3 && "illegal IT mask value!");
7785 Mask ^= (0xE << TZ) & 0xF;
7789 // Set up the IT block state according to the IT instruction we just
7791 assert(!inITBlock() && "nested IT blocks?!");
7792 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7793 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7794 ITState.CurPosition = 0;
7795 ITState.FirstCond = true;
7805 // Assemblers should use the narrow encodings of these instructions when permissible.
7806 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7807 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7808 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7809 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7810 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7811 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7812 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7814 switch (Inst.getOpcode()) {
7815 default: llvm_unreachable("unexpected opcode");
7816 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7817 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7818 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7819 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7820 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7821 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7824 TmpInst.setOpcode(NewOpc);
7825 TmpInst.addOperand(Inst.getOperand(0));
7826 TmpInst.addOperand(Inst.getOperand(5));
7827 TmpInst.addOperand(Inst.getOperand(1));
7828 TmpInst.addOperand(Inst.getOperand(2));
7829 TmpInst.addOperand(Inst.getOperand(3));
7830 TmpInst.addOperand(Inst.getOperand(4));
7841 // Assemblers should use the narrow encodings of these instructions when permissible.
7842 // These instructions are special in that they are commutable, so shorter encodings
7843 // are available more often.
7844 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7845 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7846 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7847 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7848 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7849 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7850 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7851 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7853 switch (Inst.getOpcode()) {
7854 default: llvm_unreachable("unexpected opcode");
7855 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7856 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7857 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7858 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7861 TmpInst.setOpcode(NewOpc);
7862 TmpInst.addOperand(Inst.getOperand(0));
7863 TmpInst.addOperand(Inst.getOperand(5));
7864 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7865 TmpInst.addOperand(Inst.getOperand(1));
7866 TmpInst.addOperand(Inst.getOperand(2));
7868 TmpInst.addOperand(Inst.getOperand(2));
7869 TmpInst.addOperand(Inst.getOperand(1));
7871 TmpInst.addOperand(Inst.getOperand(3));
7872 TmpInst.addOperand(Inst.getOperand(4));
7882 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7883 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7884 // suffix depending on whether they're in an IT block or not.
7885 unsigned Opc = Inst.getOpcode();
7886 const MCInstrDesc &MCID = MII.get(Opc);
7887 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7888 assert(MCID.hasOptionalDef() &&
7889 "optionally flag setting instruction missing optional def operand");
7890 assert(MCID.NumOperands == Inst.getNumOperands() &&
7891 "operand count mismatch!");
7892 // Find the optional-def operand (cc_out).
7895 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7898 // If we're parsing Thumb1, reject it completely.
7899 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7900 return Match_MnemonicFail;
7901 // If we're parsing Thumb2, which form is legal depends on whether we're
7903 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7905 return Match_RequiresITBlock;
7906 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7908 return Match_RequiresNotITBlock;
7910 // Some high-register supporting Thumb1 encodings only allow both registers
7911 // to be from r0-r7 when in Thumb2.
7912 else if (Opc == ARM::tADDhirr && isThumbOne() &&
7913 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7914 isARMLowRegister(Inst.getOperand(2).getReg()))
7915 return Match_RequiresThumb2;
7916 // Others only require ARMv6 or later.
7917 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7918 isARMLowRegister(Inst.getOperand(0).getReg()) &&
7919 isARMLowRegister(Inst.getOperand(1).getReg()))
7920 return Match_RequiresV6;
7921 return Match_Success;
7924 static const char *getSubtargetFeatureName(unsigned Val);
7926 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
7927 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
7928 MCStreamer &Out, unsigned &ErrorInfo,
7929 bool MatchingInlineAsm) {
7931 unsigned MatchResult;
7933 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
7935 switch (MatchResult) {
7938 // Context sensitive operand constraints aren't handled by the matcher,
7939 // so check them here.
7940 if (validateInstruction(Inst, Operands)) {
7941 // Still progress the IT block, otherwise one wrong condition causes
7942 // nasty cascading errors.
7943 forwardITPosition();
7947 { // processInstruction() updates inITBlock state, we need to save it away
7948 bool wasInITBlock = inITBlock();
7950 // Some instructions need post-processing to, for example, tweak which
7951 // encoding is selected. Loop on it while changes happen so the
7952 // individual transformations can chain off each other. E.g.,
7953 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
7954 while (processInstruction(Inst, Operands))
7957 // Only after the instruction is fully processed, we can validate it
7958 if (wasInITBlock && hasV8Ops() && isThumb() &&
7959 !isV8EligibleForIT(&Inst)) {
7960 Warning(IDLoc, "deprecated instruction in IT block");
7964 // Only move forward at the very end so that everything in validate
7965 // and process gets a consistent answer about whether we're in an IT
7967 forwardITPosition();
7969 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7970 // doesn't actually encode.
7971 if (Inst.getOpcode() == ARM::ITasm)
7975 Out.EmitInstruction(Inst);
7977 case Match_MissingFeature: {
7978 assert(ErrorInfo && "Unknown missing feature!");
7979 // Special case the error message for the very common case where only
7980 // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
7981 std::string Msg = "instruction requires:";
7983 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
7984 if (ErrorInfo & Mask) {
7986 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
7990 return Error(IDLoc, Msg);
7992 case Match_InvalidOperand: {
7993 SMLoc ErrorLoc = IDLoc;
7994 if (ErrorInfo != ~0U) {
7995 if (ErrorInfo >= Operands.size())
7996 return Error(IDLoc, "too few operands for instruction");
7998 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7999 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8002 return Error(ErrorLoc, "invalid operand for instruction");
8004 case Match_MnemonicFail:
8005 return Error(IDLoc, "invalid instruction",
8006 ((ARMOperand*)Operands[0])->getLocRange());
8007 case Match_RequiresNotITBlock:
8008 return Error(IDLoc, "flag setting instruction only valid outside IT block");
8009 case Match_RequiresITBlock:
8010 return Error(IDLoc, "instruction only valid inside IT block");
8011 case Match_RequiresV6:
8012 return Error(IDLoc, "instruction variant requires ARMv6 or later");
8013 case Match_RequiresThumb2:
8014 return Error(IDLoc, "instruction variant requires Thumb2");
8015 case Match_ImmRange0_15: {
8016 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
8017 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8018 return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
8020 case Match_ImmRange0_239: {
8021 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
8022 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8023 return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
8027 llvm_unreachable("Implement any new match types added!");
8030 /// parseDirective parses the arm specific directives
8031 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
8032 StringRef IDVal = DirectiveID.getIdentifier();
8033 if (IDVal == ".word")
8034 return parseDirectiveWord(4, DirectiveID.getLoc());
8035 else if (IDVal == ".thumb")
8036 return parseDirectiveThumb(DirectiveID.getLoc());
8037 else if (IDVal == ".arm")
8038 return parseDirectiveARM(DirectiveID.getLoc());
8039 else if (IDVal == ".thumb_func")
8040 return parseDirectiveThumbFunc(DirectiveID.getLoc());
8041 else if (IDVal == ".code")
8042 return parseDirectiveCode(DirectiveID.getLoc());
8043 else if (IDVal == ".syntax")
8044 return parseDirectiveSyntax(DirectiveID.getLoc());
8045 else if (IDVal == ".unreq")
8046 return parseDirectiveUnreq(DirectiveID.getLoc());
8047 else if (IDVal == ".arch")
8048 return parseDirectiveArch(DirectiveID.getLoc());
8049 else if (IDVal == ".eabi_attribute")
8050 return parseDirectiveEabiAttr(DirectiveID.getLoc());
8051 else if (IDVal == ".cpu")
8052 return parseDirectiveCPU(DirectiveID.getLoc());
8053 else if (IDVal == ".fpu")
8054 return parseDirectiveFPU(DirectiveID.getLoc());
8055 else if (IDVal == ".fnstart")
8056 return parseDirectiveFnStart(DirectiveID.getLoc());
8057 else if (IDVal == ".fnend")
8058 return parseDirectiveFnEnd(DirectiveID.getLoc());
8059 else if (IDVal == ".cantunwind")
8060 return parseDirectiveCantUnwind(DirectiveID.getLoc());
8061 else if (IDVal == ".personality")
8062 return parseDirectivePersonality(DirectiveID.getLoc());
8063 else if (IDVal == ".handlerdata")
8064 return parseDirectiveHandlerData(DirectiveID.getLoc());
8065 else if (IDVal == ".setfp")
8066 return parseDirectiveSetFP(DirectiveID.getLoc());
8067 else if (IDVal == ".pad")
8068 return parseDirectivePad(DirectiveID.getLoc());
8069 else if (IDVal == ".save")
8070 return parseDirectiveRegSave(DirectiveID.getLoc(), false);
8071 else if (IDVal == ".vsave")
8072 return parseDirectiveRegSave(DirectiveID.getLoc(), true);
8073 else if (IDVal == ".inst")
8074 return parseDirectiveInst(DirectiveID.getLoc());
8075 else if (IDVal == ".inst.n")
8076 return parseDirectiveInst(DirectiveID.getLoc(), 'n');
8077 else if (IDVal == ".inst.w")
8078 return parseDirectiveInst(DirectiveID.getLoc(), 'w');
8079 else if (IDVal == ".ltorg" || IDVal == ".pool")
8080 return parseDirectiveLtorg(DirectiveID.getLoc());
8081 else if (IDVal == ".even")
8082 return parseDirectiveEven(DirectiveID.getLoc());
8083 else if (IDVal == ".personalityindex")
8084 return parseDirectivePersonalityIndex(DirectiveID.getLoc());
8085 else if (IDVal == ".unwind_raw")
8086 return parseDirectiveUnwindRaw(DirectiveID.getLoc());
8090 /// parseDirectiveWord
8091 /// ::= .word [ expression (, expression)* ]
8092 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
8093 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8095 const MCExpr *Value;
8096 if (getParser().parseExpression(Value)) {
8097 Parser.eatToEndOfStatement();
8101 getParser().getStreamer().EmitValue(Value, Size);
8103 if (getLexer().is(AsmToken::EndOfStatement))
8106 // FIXME: Improve diagnostic.
8107 if (getLexer().isNot(AsmToken::Comma)) {
8108 Error(L, "unexpected token in directive");
8119 /// parseDirectiveThumb
8121 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
8122 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8123 Error(L, "unexpected token in directive");
8129 Error(L, "target does not support Thumb mode");
8135 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8139 /// parseDirectiveARM
8141 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
8142 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8143 Error(L, "unexpected token in directive");
8149 Error(L, "target does not support ARM mode");
8155 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8159 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
8160 if (NextSymbolIsThumb) {
8161 getParser().getStreamer().EmitThumbFunc(Symbol);
8162 NextSymbolIsThumb = false;
8166 /// parseDirectiveThumbFunc
8167 /// ::= .thumbfunc symbol_name
8168 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
8169 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
8170 bool isMachO = MAI->hasSubsectionsViaSymbols();
8172 // Darwin asm has (optionally) function name after .thumb_func direction
8175 const AsmToken &Tok = Parser.getTok();
8176 if (Tok.isNot(AsmToken::EndOfStatement)) {
8177 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) {
8178 Error(L, "unexpected token in .thumb_func directive");
8183 getParser().getContext().GetOrCreateSymbol(Tok.getIdentifier());
8184 getParser().getStreamer().EmitThumbFunc(Func);
8185 Parser.Lex(); // Consume the identifier token.
8190 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8191 Error(L, "unexpected token in directive");
8195 NextSymbolIsThumb = true;
8199 /// parseDirectiveSyntax
8200 /// ::= .syntax unified | divided
8201 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
8202 const AsmToken &Tok = Parser.getTok();
8203 if (Tok.isNot(AsmToken::Identifier)) {
8204 Error(L, "unexpected token in .syntax directive");
8208 StringRef Mode = Tok.getString();
8209 if (Mode == "unified" || Mode == "UNIFIED") {
8211 } else if (Mode == "divided" || Mode == "DIVIDED") {
8212 Error(L, "'.syntax divided' arm asssembly not supported");
8215 Error(L, "unrecognized syntax mode in .syntax directive");
8219 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8220 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8225 // TODO tell the MC streamer the mode
8226 // getParser().getStreamer().Emit???();
8230 /// parseDirectiveCode
8231 /// ::= .code 16 | 32
8232 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
8233 const AsmToken &Tok = Parser.getTok();
8234 if (Tok.isNot(AsmToken::Integer)) {
8235 Error(L, "unexpected token in .code directive");
8238 int64_t Val = Parser.getTok().getIntVal();
8239 if (Val != 16 && Val != 32) {
8240 Error(L, "invalid operand to .code directive");
8245 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8246 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8253 Error(L, "target does not support Thumb mode");
8259 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8262 Error(L, "target does not support ARM mode");
8268 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8274 /// parseDirectiveReq
8275 /// ::= name .req registername
8276 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
8277 Parser.Lex(); // Eat the '.req' token.
8279 SMLoc SRegLoc, ERegLoc;
8280 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
8281 Parser.eatToEndOfStatement();
8282 Error(SRegLoc, "register name expected");
8286 // Shouldn't be anything else.
8287 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
8288 Parser.eatToEndOfStatement();
8289 Error(Parser.getTok().getLoc(), "unexpected input in .req directive.");
8293 Parser.Lex(); // Consume the EndOfStatement
8295 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg) {
8296 Error(SRegLoc, "redefinition of '" + Name + "' does not match original.");
8303 /// parseDirectiveUneq
8304 /// ::= .unreq registername
8305 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
8306 if (Parser.getTok().isNot(AsmToken::Identifier)) {
8307 Parser.eatToEndOfStatement();
8308 Error(L, "unexpected input in .unreq directive.");
8311 RegisterReqs.erase(Parser.getTok().getIdentifier());
8312 Parser.Lex(); // Eat the identifier.
8316 /// parseDirectiveArch
8318 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
8319 StringRef Arch = getParser().parseStringToEndOfStatement().trim();
8321 unsigned ID = StringSwitch<unsigned>(Arch)
8322 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
8323 .Case(NAME, ARM::ID)
8324 #define ARM_ARCH_ALIAS(NAME, ID) \
8325 .Case(NAME, ARM::ID)
8326 #include "MCTargetDesc/ARMArchName.def"
8327 .Default(ARM::INVALID_ARCH);
8329 if (ID == ARM::INVALID_ARCH) {
8330 Error(L, "Unknown arch name");
8334 getTargetStreamer().emitArch(ID);
8338 /// parseDirectiveEabiAttr
8339 /// ::= .eabi_attribute int, int [, "str"]
8340 /// ::= .eabi_attribute Tag_name, int [, "str"]
8341 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
8345 TagLoc = Parser.getTok().getLoc();
8346 if (Parser.getTok().is(AsmToken::Identifier)) {
8347 StringRef Name = Parser.getTok().getIdentifier();
8348 Tag = ARMBuildAttrs::AttrTypeFromString(Name);
8350 Error(TagLoc, "attribute name not recognised: " + Name);
8351 Parser.eatToEndOfStatement();
8356 const MCExpr *AttrExpr;
8358 TagLoc = Parser.getTok().getLoc();
8359 if (Parser.parseExpression(AttrExpr)) {
8360 Parser.eatToEndOfStatement();
8364 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
8366 Error(TagLoc, "expected numeric constant");
8367 Parser.eatToEndOfStatement();
8371 Tag = CE->getValue();
8374 if (Parser.getTok().isNot(AsmToken::Comma)) {
8375 Error(Parser.getTok().getLoc(), "comma expected");
8376 Parser.eatToEndOfStatement();
8379 Parser.Lex(); // skip comma
8381 StringRef StringValue = "";
8382 bool IsStringValue = false;
8384 int64_t IntegerValue = 0;
8385 bool IsIntegerValue = false;
8387 if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
8388 IsStringValue = true;
8389 else if (Tag == ARMBuildAttrs::compatibility) {
8390 IsStringValue = true;
8391 IsIntegerValue = true;
8392 } else if (Tag < 32 || Tag % 2 == 0)
8393 IsIntegerValue = true;
8394 else if (Tag % 2 == 1)
8395 IsStringValue = true;
8397 llvm_unreachable("invalid tag type");
8399 if (IsIntegerValue) {
8400 const MCExpr *ValueExpr;
8401 SMLoc ValueExprLoc = Parser.getTok().getLoc();
8402 if (Parser.parseExpression(ValueExpr)) {
8403 Parser.eatToEndOfStatement();
8407 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
8409 Error(ValueExprLoc, "expected numeric constant");
8410 Parser.eatToEndOfStatement();
8414 IntegerValue = CE->getValue();
8417 if (Tag == ARMBuildAttrs::compatibility) {
8418 if (Parser.getTok().isNot(AsmToken::Comma))
8419 IsStringValue = false;
8424 if (IsStringValue) {
8425 if (Parser.getTok().isNot(AsmToken::String)) {
8426 Error(Parser.getTok().getLoc(), "bad string constant");
8427 Parser.eatToEndOfStatement();
8431 StringValue = Parser.getTok().getStringContents();
8435 if (IsIntegerValue && IsStringValue) {
8436 assert(Tag == ARMBuildAttrs::compatibility);
8437 getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
8438 } else if (IsIntegerValue)
8439 getTargetStreamer().emitAttribute(Tag, IntegerValue);
8440 else if (IsStringValue)
8441 getTargetStreamer().emitTextAttribute(Tag, StringValue);
8445 /// parseDirectiveCPU
8447 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
8448 StringRef CPU = getParser().parseStringToEndOfStatement().trim();
8449 getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
8453 /// parseDirectiveFPU
8455 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
8456 StringRef FPU = getParser().parseStringToEndOfStatement().trim();
8458 unsigned ID = StringSwitch<unsigned>(FPU)
8459 #define ARM_FPU_NAME(NAME, ID) .Case(NAME, ARM::ID)
8460 #include "ARMFPUName.def"
8461 .Default(ARM::INVALID_FPU);
8463 if (ID == ARM::INVALID_FPU) {
8464 Error(L, "Unknown FPU name");
8468 getTargetStreamer().emitFPU(ID);
8472 /// parseDirectiveFnStart
8474 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
8475 if (UC.hasFnStart()) {
8476 Error(L, ".fnstart starts before the end of previous one");
8477 UC.emitFnStartLocNotes();
8481 // Reset the unwind directives parser state
8484 getTargetStreamer().emitFnStart();
8486 UC.recordFnStart(L);
8490 /// parseDirectiveFnEnd
8492 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
8493 // Check the ordering of unwind directives
8494 if (!UC.hasFnStart()) {
8495 Error(L, ".fnstart must precede .fnend directive");
8499 // Reset the unwind directives parser state
8500 getTargetStreamer().emitFnEnd();
8506 /// parseDirectiveCantUnwind
8508 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
8509 UC.recordCantUnwind(L);
8511 // Check the ordering of unwind directives
8512 if (!UC.hasFnStart()) {
8513 Error(L, ".fnstart must precede .cantunwind directive");
8516 if (UC.hasHandlerData()) {
8517 Error(L, ".cantunwind can't be used with .handlerdata directive");
8518 UC.emitHandlerDataLocNotes();
8521 if (UC.hasPersonality()) {
8522 Error(L, ".cantunwind can't be used with .personality directive");
8523 UC.emitPersonalityLocNotes();
8527 getTargetStreamer().emitCantUnwind();
8531 /// parseDirectivePersonality
8532 /// ::= .personality name
8533 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
8534 bool HasExistingPersonality = UC.hasPersonality();
8536 UC.recordPersonality(L);
8538 // Check the ordering of unwind directives
8539 if (!UC.hasFnStart()) {
8540 Error(L, ".fnstart must precede .personality directive");
8543 if (UC.cantUnwind()) {
8544 Error(L, ".personality can't be used with .cantunwind directive");
8545 UC.emitCantUnwindLocNotes();
8548 if (UC.hasHandlerData()) {
8549 Error(L, ".personality must precede .handlerdata directive");
8550 UC.emitHandlerDataLocNotes();
8553 if (HasExistingPersonality) {
8554 Parser.eatToEndOfStatement();
8555 Error(L, "multiple personality directives");
8556 UC.emitPersonalityLocNotes();
8560 // Parse the name of the personality routine
8561 if (Parser.getTok().isNot(AsmToken::Identifier)) {
8562 Parser.eatToEndOfStatement();
8563 Error(L, "unexpected input in .personality directive.");
8566 StringRef Name(Parser.getTok().getIdentifier());
8569 MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
8570 getTargetStreamer().emitPersonality(PR);
8574 /// parseDirectiveHandlerData
8575 /// ::= .handlerdata
8576 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
8577 UC.recordHandlerData(L);
8579 // Check the ordering of unwind directives
8580 if (!UC.hasFnStart()) {
8581 Error(L, ".fnstart must precede .personality directive");
8584 if (UC.cantUnwind()) {
8585 Error(L, ".handlerdata can't be used with .cantunwind directive");
8586 UC.emitCantUnwindLocNotes();
8590 getTargetStreamer().emitHandlerData();
8594 /// parseDirectiveSetFP
8595 /// ::= .setfp fpreg, spreg [, offset]
8596 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
8597 // Check the ordering of unwind directives
8598 if (!UC.hasFnStart()) {
8599 Error(L, ".fnstart must precede .setfp directive");
8602 if (UC.hasHandlerData()) {
8603 Error(L, ".setfp must precede .handlerdata directive");
8608 SMLoc FPRegLoc = Parser.getTok().getLoc();
8609 int FPReg = tryParseRegister();
8611 Error(FPRegLoc, "frame pointer register expected");
8616 if (!Parser.getTok().is(AsmToken::Comma)) {
8617 Error(Parser.getTok().getLoc(), "comma expected");
8620 Parser.Lex(); // skip comma
8623 SMLoc SPRegLoc = Parser.getTok().getLoc();
8624 int SPReg = tryParseRegister();
8626 Error(SPRegLoc, "stack pointer register expected");
8630 if (SPReg != ARM::SP && SPReg != UC.getFPReg()) {
8631 Error(SPRegLoc, "register should be either $sp or the latest fp register");
8635 // Update the frame pointer register
8636 UC.saveFPReg(FPReg);
8640 if (Parser.getTok().is(AsmToken::Comma)) {
8641 Parser.Lex(); // skip comma
8643 if (Parser.getTok().isNot(AsmToken::Hash) &&
8644 Parser.getTok().isNot(AsmToken::Dollar)) {
8645 Error(Parser.getTok().getLoc(), "'#' expected");
8648 Parser.Lex(); // skip hash token.
8650 const MCExpr *OffsetExpr;
8651 SMLoc ExLoc = Parser.getTok().getLoc();
8653 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
8654 Error(ExLoc, "malformed setfp offset");
8657 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8659 Error(ExLoc, "setfp offset must be an immediate");
8663 Offset = CE->getValue();
8666 getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
8667 static_cast<unsigned>(SPReg), Offset);
8673 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
8674 // Check the ordering of unwind directives
8675 if (!UC.hasFnStart()) {
8676 Error(L, ".fnstart must precede .pad directive");
8679 if (UC.hasHandlerData()) {
8680 Error(L, ".pad must precede .handlerdata directive");
8685 if (Parser.getTok().isNot(AsmToken::Hash) &&
8686 Parser.getTok().isNot(AsmToken::Dollar)) {
8687 Error(Parser.getTok().getLoc(), "'#' expected");
8690 Parser.Lex(); // skip hash token.
8692 const MCExpr *OffsetExpr;
8693 SMLoc ExLoc = Parser.getTok().getLoc();
8695 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
8696 Error(ExLoc, "malformed pad offset");
8699 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8701 Error(ExLoc, "pad offset must be an immediate");
8705 getTargetStreamer().emitPad(CE->getValue());
8709 /// parseDirectiveRegSave
8710 /// ::= .save { registers }
8711 /// ::= .vsave { registers }
8712 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
8713 // Check the ordering of unwind directives
8714 if (!UC.hasFnStart()) {
8715 Error(L, ".fnstart must precede .save or .vsave directives");
8718 if (UC.hasHandlerData()) {
8719 Error(L, ".save or .vsave must precede .handlerdata directive");
8723 // RAII object to make sure parsed operands are deleted.
8724 struct CleanupObject {
8725 SmallVector<MCParsedAsmOperand *, 1> Operands;
8727 for (unsigned I = 0, E = Operands.size(); I != E; ++I)
8732 // Parse the register list
8733 if (parseRegisterList(CO.Operands))
8735 ARMOperand *Op = (ARMOperand*)CO.Operands[0];
8736 if (!IsVector && !Op->isRegList()) {
8737 Error(L, ".save expects GPR registers");
8740 if (IsVector && !Op->isDPRRegList()) {
8741 Error(L, ".vsave expects DPR registers");
8745 getTargetStreamer().emitRegSave(Op->getRegList(), IsVector);
8749 /// parseDirectiveInst
8750 /// ::= .inst opcode [, ...]
8751 /// ::= .inst.n opcode [, ...]
8752 /// ::= .inst.w opcode [, ...]
8753 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
8765 Parser.eatToEndOfStatement();
8766 Error(Loc, "cannot determine Thumb instruction size, "
8767 "use inst.n/inst.w instead");
8772 Parser.eatToEndOfStatement();
8773 Error(Loc, "width suffixes are invalid in ARM mode");
8779 if (getLexer().is(AsmToken::EndOfStatement)) {
8780 Parser.eatToEndOfStatement();
8781 Error(Loc, "expected expression following directive");
8788 if (getParser().parseExpression(Expr)) {
8789 Error(Loc, "expected expression");
8793 const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
8795 Error(Loc, "expected constant expression");
8801 if (Value->getValue() > 0xffff) {
8802 Error(Loc, "inst.n operand is too big, use inst.w instead");
8807 if (Value->getValue() > 0xffffffff) {
8809 StringRef(Suffix ? "inst.w" : "inst") + " operand is too big");
8814 llvm_unreachable("only supported widths are 2 and 4");
8817 getTargetStreamer().emitInst(Value->getValue(), Suffix);
8819 if (getLexer().is(AsmToken::EndOfStatement))
8822 if (getLexer().isNot(AsmToken::Comma)) {
8823 Error(Loc, "unexpected token in directive");
8834 /// parseDirectiveLtorg
8835 /// ::= .ltorg | .pool
8836 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
8837 MCStreamer &Streamer = getParser().getStreamer();
8838 const MCSection *Section = Streamer.getCurrentSection().first;
8840 if (ConstantPool *CP = getConstantPool(Section)) {
8842 CP->emitEntries(Streamer);
8847 bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
8848 const MCSection *Section = getStreamer().getCurrentSection().first;
8850 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8851 TokError("unexpected token in directive");
8856 getStreamer().InitSections();
8857 Section = getStreamer().getCurrentSection().first;
8860 if (Section->UseCodeAlign())
8861 getStreamer().EmitCodeAlignment(2, 0);
8863 getStreamer().EmitValueToAlignment(2, 0, 1, 0);
8868 /// parseDirectivePersonalityIndex
8869 /// ::= .personalityindex index
8870 bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) {
8871 bool HasExistingPersonality = UC.hasPersonality();
8873 UC.recordPersonalityIndex(L);
8875 if (!UC.hasFnStart()) {
8876 Parser.eatToEndOfStatement();
8877 Error(L, ".fnstart must precede .personalityindex directive");
8880 if (UC.cantUnwind()) {
8881 Parser.eatToEndOfStatement();
8882 Error(L, ".personalityindex cannot be used with .cantunwind");
8883 UC.emitCantUnwindLocNotes();
8886 if (UC.hasHandlerData()) {
8887 Parser.eatToEndOfStatement();
8888 Error(L, ".personalityindex must precede .handlerdata directive");
8889 UC.emitHandlerDataLocNotes();
8892 if (HasExistingPersonality) {
8893 Parser.eatToEndOfStatement();
8894 Error(L, "multiple personality directives");
8895 UC.emitPersonalityLocNotes();
8899 const MCExpr *IndexExpression;
8900 SMLoc IndexLoc = Parser.getTok().getLoc();
8901 if (Parser.parseExpression(IndexExpression)) {
8902 Parser.eatToEndOfStatement();
8906 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
8908 Parser.eatToEndOfStatement();
8909 Error(IndexLoc, "index must be a constant number");
8912 if (CE->getValue() < 0 ||
8913 CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) {
8914 Parser.eatToEndOfStatement();
8915 Error(IndexLoc, "personality routine index should be in range [0-3]");
8919 getTargetStreamer().emitPersonalityIndex(CE->getValue());
8923 /// parseDirectiveUnwindRaw
8924 /// ::= .unwind_raw offset, opcode [, opcode...]
8925 bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
8926 if (!UC.hasFnStart()) {
8927 Parser.eatToEndOfStatement();
8928 Error(L, ".fnstart must precede .unwind_raw directives");
8932 int64_t StackOffset;
8934 const MCExpr *OffsetExpr;
8935 SMLoc OffsetLoc = getLexer().getLoc();
8936 if (getLexer().is(AsmToken::EndOfStatement) ||
8937 getParser().parseExpression(OffsetExpr)) {
8938 Error(OffsetLoc, "expected expression");
8939 Parser.eatToEndOfStatement();
8943 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8945 Error(OffsetLoc, "offset must be a constant");
8946 Parser.eatToEndOfStatement();
8950 StackOffset = CE->getValue();
8952 if (getLexer().isNot(AsmToken::Comma)) {
8953 Error(getLexer().getLoc(), "expected comma");
8954 Parser.eatToEndOfStatement();
8959 SmallVector<uint8_t, 16> Opcodes;
8963 SMLoc OpcodeLoc = getLexer().getLoc();
8964 if (getLexer().is(AsmToken::EndOfStatement) || Parser.parseExpression(OE)) {
8965 Error(OpcodeLoc, "expected opcode expression");
8966 Parser.eatToEndOfStatement();
8970 const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
8972 Error(OpcodeLoc, "opcode value must be a constant");
8973 Parser.eatToEndOfStatement();
8977 const int64_t Opcode = OC->getValue();
8978 if (Opcode & ~0xff) {
8979 Error(OpcodeLoc, "invalid opcode");
8980 Parser.eatToEndOfStatement();
8984 Opcodes.push_back(uint8_t(Opcode));
8986 if (getLexer().is(AsmToken::EndOfStatement))
8989 if (getLexer().isNot(AsmToken::Comma)) {
8990 Error(getLexer().getLoc(), "unexpected token in directive");
8991 Parser.eatToEndOfStatement();
8998 getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes);
9004 /// Force static initialization.
9005 extern "C" void LLVMInitializeARMAsmParser() {
9006 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
9007 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
9010 #define GET_REGISTER_MATCHER
9011 #define GET_SUBTARGET_FEATURE_NAME
9012 #define GET_MATCHER_IMPLEMENTATION
9013 #include "ARMGenAsmMatcher.inc"
9015 // Define this matcher function after the auto-generated include so we
9016 // have the match class enum definitions.
9017 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
9019 ARMOperand *Op = static_cast<ARMOperand*>(AsmOp);
9020 // If the kind is a token for a literal immediate, check if our asm
9021 // operand matches. This is for InstAliases which have a fixed-value
9022 // immediate in the syntax.
9027 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()))
9028 if (CE->getValue() == 0)
9029 return Match_Success;
9033 const MCExpr *SOExpr = Op->getImm();
9035 if (!SOExpr->EvaluateAsAbsolute(Value))
9036 return Match_Success;
9037 assert((Value >= INT32_MIN && Value <= INT32_MAX) &&
9038 "expression value must be representiable in 32 bits");
9043 MRI->getRegClass(ARM::GPRRegClassID).contains(Op->getReg()))
9044 return Match_Success;
9047 return Match_InvalidOperand;
9050 void ARMAsmParser::finishParse() {
9051 // Dump contents of assembler constant pools.
9052 MCStreamer &Streamer = getParser().getStreamer();
9053 for (ConstantPoolMapTy::iterator CPI = ConstantPools.begin(),
9054 CPE = ConstantPools.end();
9055 CPI != CPE; ++CPI) {
9056 const MCSection *Section = CPI->first;
9057 ConstantPool &CP = CPI->second;
9059 // Dump non-empty assembler constant pools at the end of the section.
9061 Streamer.SwitchSection(Section);
9062 CP.emitEntries(Streamer);