1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMSubtarget.h"
12 #include "llvm/MC/MCParser/MCAsmLexer.h"
13 #include "llvm/MC/MCParser/MCAsmParser.h"
14 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
15 #include "llvm/MC/MCStreamer.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/Target/TargetRegistry.h"
19 #include "llvm/Target/TargetAsmParser.h"
20 #include "llvm/Support/SourceMgr.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/StringSwitch.h"
24 #include "llvm/ADT/Twine.h"
27 // The shift types for register controlled shifts in arm memory addressing
39 class ARMAsmParser : public TargetAsmParser {
44 MCAsmParser &getParser() const { return Parser; }
46 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
48 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
50 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
52 ARMOperand *MaybeParseRegister(bool ParseWriteBack);
53 ARMOperand *ParseRegisterList();
54 ARMOperand *ParseMemory();
56 bool ParseMemoryOffsetReg(bool &Negative,
57 bool &OffsetRegShifted,
58 enum ShiftType &ShiftType,
59 const MCExpr *&ShiftAmount,
60 const MCExpr *&Offset,
65 bool ParseShift(enum ShiftType &St, const MCExpr *&ShiftAmount, SMLoc &E);
67 ARMOperand *ParseOperand();
69 bool ParseDirectiveWord(unsigned Size, SMLoc L);
71 bool ParseDirectiveThumb(SMLoc L);
73 bool ParseDirectiveThumbFunc(SMLoc L);
75 bool ParseDirectiveCode(SMLoc L);
77 bool ParseDirectiveSyntax(SMLoc L);
79 bool MatchAndEmitInstruction(SMLoc IDLoc,
80 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
83 /// @name Auto-generated Match Functions
86 #define GET_ASSEMBLER_HEADER
87 #include "ARMGenAsmMatcher.inc"
93 ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
94 : TargetAsmParser(T), Parser(_Parser), TM(_TM) {}
96 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
97 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
99 virtual bool ParseDirective(AsmToken DirectiveID);
101 } // end anonymous namespace
105 /// ARMOperand - Instances of this class represent a parsed ARM machine
107 struct ARMOperand : public MCParsedAsmOperand {
117 SMLoc StartLoc, EndLoc;
121 ARMCC::CondCodes Val;
138 // This is for all forms of ARM address expressions
141 unsigned OffsetRegNum; // used when OffsetIsReg is true
142 const MCExpr *Offset; // used when OffsetIsReg is false
143 const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
144 enum ShiftType ShiftType; // used when OffsetRegShifted is true
146 OffsetRegShifted : 1, // only used when OffsetIsReg is true
150 Negative : 1, // only used when OffsetIsReg is true
156 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
158 StartLoc = o.StartLoc;
179 /// getStartLoc - Get the location of the first token of this operand.
180 SMLoc getStartLoc() const { return StartLoc; }
181 /// getEndLoc - Get the location of the last token of this operand.
182 SMLoc getEndLoc() const { return EndLoc; }
184 ARMCC::CondCodes getCondCode() const {
185 assert(Kind == CondCode && "Invalid access!");
189 StringRef getToken() const {
190 assert(Kind == Token && "Invalid access!");
191 return StringRef(Tok.Data, Tok.Length);
194 unsigned getReg() const {
195 assert(Kind == Register && "Invalid access!");
199 const MCExpr *getImm() const {
200 assert(Kind == Immediate && "Invalid access!");
204 bool isCondCode() const { return Kind == CondCode; }
205 bool isImm() const { return Kind == Immediate; }
206 bool isReg() const { return Kind == Register; }
207 bool isToken() const { return Kind == Token; }
208 bool isMemory() const { return Kind == Memory; }
210 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
211 // Add as immediates when possible. Null MCExpr = 0.
213 Inst.addOperand(MCOperand::CreateImm(0));
214 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
215 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
217 Inst.addOperand(MCOperand::CreateExpr(Expr));
220 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
221 assert(N == 2 && "Invalid number of operands!");
222 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
223 // FIXME: What belongs here?
224 Inst.addOperand(MCOperand::CreateReg(0));
227 void addRegOperands(MCInst &Inst, unsigned N) const {
228 assert(N == 1 && "Invalid number of operands!");
229 Inst.addOperand(MCOperand::CreateReg(getReg()));
232 void addImmOperands(MCInst &Inst, unsigned N) const {
233 assert(N == 1 && "Invalid number of operands!");
234 addExpr(Inst, getImm());
238 bool isMemMode5() const {
239 if (!isMemory() || Mem.OffsetIsReg || Mem.OffsetRegShifted ||
240 Mem.Writeback || Mem.Negative)
242 // If there is an offset expression, make sure it's valid.
245 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
248 // The offset must be a multiple of 4 in the range 0-1020.
249 int64_t Value = CE->getValue();
250 return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020);
253 void addMemMode5Operands(MCInst &Inst, unsigned N) const {
254 assert(N == 2 && isMemMode5() && "Invalid number of operands!");
256 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
257 assert(!Mem.OffsetIsReg && "invalid mode 5 operand");
258 // FIXME: #-0 is encoded differently than #0. Does the parser preserve
261 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
262 assert (CE && "non-constant mode 5 offset operand!");
263 // The MCInst offset operand doesn't include the low two bits (like
264 // the instruction encoding).
265 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
267 Inst.addOperand(MCOperand::CreateImm(0));
270 virtual void dump(raw_ostream &OS) const;
272 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
273 ARMOperand *Op = new ARMOperand(CondCode);
280 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
281 ARMOperand *Op = new ARMOperand(Token);
282 Op->Tok.Data = Str.data();
283 Op->Tok.Length = Str.size();
289 static ARMOperand *CreateReg(unsigned RegNum, bool Writeback, SMLoc S,
291 ARMOperand *Op = new ARMOperand(Register);
292 Op->Reg.RegNum = RegNum;
293 Op->Reg.Writeback = Writeback;
299 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
300 ARMOperand *Op = new ARMOperand(Immediate);
307 static ARMOperand *CreateMem(unsigned BaseRegNum, bool OffsetIsReg,
308 const MCExpr *Offset, unsigned OffsetRegNum,
309 bool OffsetRegShifted, enum ShiftType ShiftType,
310 const MCExpr *ShiftAmount, bool Preindexed,
311 bool Postindexed, bool Negative, bool Writeback,
313 ARMOperand *Op = new ARMOperand(Memory);
314 Op->Mem.BaseRegNum = BaseRegNum;
315 Op->Mem.OffsetIsReg = OffsetIsReg;
316 Op->Mem.Offset = Offset;
317 Op->Mem.OffsetRegNum = OffsetRegNum;
318 Op->Mem.OffsetRegShifted = OffsetRegShifted;
319 Op->Mem.ShiftType = ShiftType;
320 Op->Mem.ShiftAmount = ShiftAmount;
321 Op->Mem.Preindexed = Preindexed;
322 Op->Mem.Postindexed = Postindexed;
323 Op->Mem.Negative = Negative;
324 Op->Mem.Writeback = Writeback;
332 ARMOperand(KindTy K) : Kind(K) {}
335 } // end anonymous namespace.
337 void ARMOperand::dump(raw_ostream &OS) const {
340 OS << ARMCondCodeToString(getCondCode());
349 OS << "<register " << getReg() << ">";
352 OS << "'" << getToken() << "'";
357 /// @name Auto-generated Match Functions
360 static unsigned MatchRegisterName(StringRef Name);
364 /// Try to parse a register name. The token must be an Identifier when called,
365 /// and if it is a register name the token is eaten and a Reg operand is created
366 /// and returned. Otherwise return null.
368 /// TODO this is likely to change to allow different register types and or to
369 /// parse for a specific register type.
370 ARMOperand *ARMAsmParser::MaybeParseRegister(bool ParseWriteBack) {
372 const AsmToken &Tok = Parser.getTok();
373 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
375 // FIXME: Validate register for the current architecture; we have to do
376 // validation later, so maybe there is no need for this here.
379 RegNum = MatchRegisterName(Tok.getString());
385 Parser.Lex(); // Eat identifier token.
387 E = Parser.getTok().getLoc();
389 bool Writeback = false;
390 if (ParseWriteBack) {
391 const AsmToken &ExclaimTok = Parser.getTok();
392 if (ExclaimTok.is(AsmToken::Exclaim)) {
393 E = ExclaimTok.getLoc();
395 Parser.Lex(); // Eat exclaim token
399 return ARMOperand::CreateReg(RegNum, Writeback, S, E);
402 /// Parse a register list, return it if successful else return null. The first
403 /// token must be a '{' when called.
404 ARMOperand *ARMAsmParser::ParseRegisterList() {
406 assert(Parser.getTok().is(AsmToken::LCurly) &&
407 "Token is not an Left Curly Brace");
408 S = Parser.getTok().getLoc();
409 Parser.Lex(); // Eat left curly brace token.
411 const AsmToken &RegTok = Parser.getTok();
412 SMLoc RegLoc = RegTok.getLoc();
413 if (RegTok.isNot(AsmToken::Identifier)) {
414 Error(RegLoc, "register expected");
417 int RegNum = MatchRegisterName(RegTok.getString());
419 Error(RegLoc, "register expected");
423 Parser.Lex(); // Eat identifier token.
424 unsigned RegList = 1 << RegNum;
426 int HighRegNum = RegNum;
427 // TODO ranges like "{Rn-Rm}"
428 while (Parser.getTok().is(AsmToken::Comma)) {
429 Parser.Lex(); // Eat comma token.
431 const AsmToken &RegTok = Parser.getTok();
432 SMLoc RegLoc = RegTok.getLoc();
433 if (RegTok.isNot(AsmToken::Identifier)) {
434 Error(RegLoc, "register expected");
437 int RegNum = MatchRegisterName(RegTok.getString());
439 Error(RegLoc, "register expected");
443 if (RegList & (1 << RegNum))
444 Warning(RegLoc, "register duplicated in register list");
445 else if (RegNum <= HighRegNum)
446 Warning(RegLoc, "register not in ascending order in register list");
447 RegList |= 1 << RegNum;
450 Parser.Lex(); // Eat identifier token.
452 const AsmToken &RCurlyTok = Parser.getTok();
453 if (RCurlyTok.isNot(AsmToken::RCurly)) {
454 Error(RCurlyTok.getLoc(), "'}' expected");
457 E = RCurlyTok.getLoc();
458 Parser.Lex(); // Eat left curly brace token.
460 // FIXME: Need to return an operand!
461 Error(E, "FIXME: register list parsing not implemented");
465 /// Parse an arm memory expression, return false if successful else return true
466 /// or an error. The first token must be a '[' when called.
467 /// TODO Only preindexing and postindexing addressing are started, unindexed
468 /// with option, etc are still to do.
469 ARMOperand *ARMAsmParser::ParseMemory() {
471 assert(Parser.getTok().is(AsmToken::LBrac) &&
472 "Token is not an Left Bracket");
473 S = Parser.getTok().getLoc();
474 Parser.Lex(); // Eat left bracket token.
476 const AsmToken &BaseRegTok = Parser.getTok();
477 if (BaseRegTok.isNot(AsmToken::Identifier)) {
478 Error(BaseRegTok.getLoc(), "register expected");
482 if (ARMOperand *Op = MaybeParseRegister(false)) {
483 BaseRegNum = Op->getReg();
486 Error(BaseRegTok.getLoc(), "register expected");
490 bool Preindexed = false;
491 bool Postindexed = false;
492 bool OffsetIsReg = false;
493 bool Negative = false;
494 bool Writeback = false;
496 // First look for preindexed address forms, that is after the "[Rn" we now
497 // have to see if the next token is a comma.
498 const AsmToken &Tok = Parser.getTok();
499 if (Tok.is(AsmToken::Comma)) {
501 Parser.Lex(); // Eat comma token.
503 bool OffsetRegShifted;
504 enum ShiftType ShiftType;
505 const MCExpr *ShiftAmount;
506 const MCExpr *Offset;
507 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
508 Offset, OffsetIsReg, OffsetRegNum, E))
510 const AsmToken &RBracTok = Parser.getTok();
511 if (RBracTok.isNot(AsmToken::RBrac)) {
512 Error(RBracTok.getLoc(), "']' expected");
515 E = RBracTok.getLoc();
516 Parser.Lex(); // Eat right bracket token.
518 const AsmToken &ExclaimTok = Parser.getTok();
519 if (ExclaimTok.is(AsmToken::Exclaim)) {
520 E = ExclaimTok.getLoc();
522 Parser.Lex(); // Eat exclaim token
524 return ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
525 OffsetRegShifted, ShiftType, ShiftAmount,
526 Preindexed, Postindexed, Negative, Writeback,
529 // The "[Rn" we have so far was not followed by a comma.
530 else if (Tok.is(AsmToken::RBrac)) {
531 // If there's anything other than the right brace, this is a post indexing
534 Parser.Lex(); // Eat right bracket token.
536 int OffsetRegNum = 0;
537 bool OffsetRegShifted = false;
538 enum ShiftType ShiftType;
539 const MCExpr *ShiftAmount;
540 const MCExpr *Offset = 0;
542 const AsmToken &NextTok = Parser.getTok();
543 if (NextTok.isNot(AsmToken::EndOfStatement)) {
546 if (NextTok.isNot(AsmToken::Comma)) {
547 Error(NextTok.getLoc(), "',' expected");
550 Parser.Lex(); // Eat comma token.
551 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
552 ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
557 return ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
558 OffsetRegShifted, ShiftType, ShiftAmount,
559 Preindexed, Postindexed, Negative, Writeback,
566 /// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
567 /// we will parse the following (were +/- means that a plus or minus is
572 /// we return false on success or an error otherwise.
573 bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
574 bool &OffsetRegShifted,
575 enum ShiftType &ShiftType,
576 const MCExpr *&ShiftAmount,
577 const MCExpr *&Offset,
582 OffsetRegShifted = false;
585 const AsmToken &NextTok = Parser.getTok();
586 E = NextTok.getLoc();
587 if (NextTok.is(AsmToken::Plus))
588 Parser.Lex(); // Eat plus token.
589 else if (NextTok.is(AsmToken::Minus)) {
591 Parser.Lex(); // Eat minus token
593 // See if there is a register following the "[Rn," or "[Rn]," we have so far.
594 const AsmToken &OffsetRegTok = Parser.getTok();
595 if (OffsetRegTok.is(AsmToken::Identifier)) {
596 if (ARMOperand *Op = MaybeParseRegister(false)) {
599 OffsetRegNum = Op->getReg();
603 // If we parsed a register as the offset then their can be a shift after that
604 if (OffsetRegNum != -1) {
605 // Look for a comma then a shift
606 const AsmToken &Tok = Parser.getTok();
607 if (Tok.is(AsmToken::Comma)) {
608 Parser.Lex(); // Eat comma token.
610 const AsmToken &Tok = Parser.getTok();
611 if (ParseShift(ShiftType, ShiftAmount, E))
612 return Error(Tok.getLoc(), "shift expected");
613 OffsetRegShifted = true;
616 else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
617 // Look for #offset following the "[Rn," or "[Rn],"
618 const AsmToken &HashTok = Parser.getTok();
619 if (HashTok.isNot(AsmToken::Hash))
620 return Error(HashTok.getLoc(), "'#' expected");
622 Parser.Lex(); // Eat hash token.
624 if (getParser().ParseExpression(Offset))
626 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
631 /// ParseShift as one of these two:
632 /// ( lsl | lsr | asr | ror ) , # shift_amount
634 /// and returns true if it parses a shift otherwise it returns false.
635 bool ARMAsmParser::ParseShift(ShiftType &St, const MCExpr *&ShiftAmount,
637 const AsmToken &Tok = Parser.getTok();
638 if (Tok.isNot(AsmToken::Identifier))
640 StringRef ShiftName = Tok.getString();
641 if (ShiftName == "lsl" || ShiftName == "LSL")
643 else if (ShiftName == "lsr" || ShiftName == "LSR")
645 else if (ShiftName == "asr" || ShiftName == "ASR")
647 else if (ShiftName == "ror" || ShiftName == "ROR")
649 else if (ShiftName == "rrx" || ShiftName == "RRX")
653 Parser.Lex(); // Eat shift type token.
659 // Otherwise, there must be a '#' and a shift amount.
660 const AsmToken &HashTok = Parser.getTok();
661 if (HashTok.isNot(AsmToken::Hash))
662 return Error(HashTok.getLoc(), "'#' expected");
663 Parser.Lex(); // Eat hash token.
665 if (getParser().ParseExpression(ShiftAmount))
671 /// Parse a arm instruction operand. For now this parses the operand regardless
673 ARMOperand *ARMAsmParser::ParseOperand() {
676 switch (getLexer().getKind()) {
677 case AsmToken::Identifier:
678 if (ARMOperand *Op = MaybeParseRegister(true))
681 // This was not a register so parse other operands that start with an
682 // identifier (like labels) as expressions and create them as immediates.
684 S = Parser.getTok().getLoc();
685 if (getParser().ParseExpression(IdVal))
687 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
688 return ARMOperand::CreateImm(IdVal, S, E);
689 case AsmToken::LBrac:
690 return ParseMemory();
691 case AsmToken::LCurly:
692 return ParseRegisterList();
695 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
696 S = Parser.getTok().getLoc();
698 const MCExpr *ImmVal;
699 if (getParser().ParseExpression(ImmVal))
701 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
702 return ARMOperand::CreateImm(ImmVal, S, E);
704 Error(Parser.getTok().getLoc(), "unexpected token in operand");
709 /// Parse an arm instruction mnemonic followed by its operands.
710 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
711 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
712 // Create the leading tokens for the mnemonic, split by '.' characters.
713 size_t Start = 0, Next = Name.find('.');
714 StringRef Head = Name.slice(Start, Next);
716 // Determine the predicate, if any.
718 // FIXME: We need a way to check whether a prefix supports predication,
719 // otherwise we will end up with an ambiguity for instructions that happen to
720 // end with a predicate name.
721 // FIXME: Likewise, some arithmetic instructions have an 's' prefix which
722 // indicates to update the condition codes. Those instructions have an
723 // additional immediate operand which encodes the prefix as reg0 or CPSR.
724 // Just checking for a suffix of 's' definitely creates ambiguities; e.g,
725 // the SMMLS instruction.
726 unsigned CC = StringSwitch<unsigned>(Head.substr(Head.size()-2))
727 .Case("eq", ARMCC::EQ)
728 .Case("ne", ARMCC::NE)
729 .Case("hs", ARMCC::HS)
730 .Case("lo", ARMCC::LO)
731 .Case("mi", ARMCC::MI)
732 .Case("pl", ARMCC::PL)
733 .Case("vs", ARMCC::VS)
734 .Case("vc", ARMCC::VC)
735 .Case("hi", ARMCC::HI)
736 .Case("ls", ARMCC::LS)
737 .Case("ge", ARMCC::GE)
738 .Case("lt", ARMCC::LT)
739 .Case("gt", ARMCC::GT)
740 .Case("le", ARMCC::LE)
741 .Case("al", ARMCC::AL)
745 if (CC == ARMCC::LS &&
746 (Head.compare("vmls") == 0 || Head.compare("vnmls") == 0)) {
749 Head = Head.slice(0, Head.size() - 2);
755 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
756 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), NameLoc));
758 // Add the remaining tokens in the mnemonic.
759 while (Next != StringRef::npos) {
761 Next = Name.find('.', Start + 1);
762 Head = Name.slice(Start, Next);
764 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
767 // Read the remaining operands.
768 if (getLexer().isNot(AsmToken::EndOfStatement)) {
769 // Read the first operand.
770 if (ARMOperand *Op = ParseOperand())
771 Operands.push_back(Op);
773 Parser.EatToEndOfStatement();
777 while (getLexer().is(AsmToken::Comma)) {
778 Parser.Lex(); // Eat the comma.
780 // Parse and remember the operand.
781 if (ARMOperand *Op = ParseOperand())
782 Operands.push_back(Op);
784 Parser.EatToEndOfStatement();
790 if (getLexer().isNot(AsmToken::EndOfStatement)) {
791 Parser.EatToEndOfStatement();
792 return TokError("unexpected token in argument list");
794 Parser.Lex(); // Consume the EndOfStatement
799 MatchAndEmitInstruction(SMLoc IDLoc,
800 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
804 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo)) {
806 Out.EmitInstruction(Inst);
809 case Match_MissingFeature:
810 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
812 case Match_InvalidOperand: {
813 SMLoc ErrorLoc = IDLoc;
814 if (ErrorInfo != ~0U) {
815 if (ErrorInfo >= Operands.size())
816 return Error(IDLoc, "too few operands for instruction");
818 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
819 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
822 return Error(ErrorLoc, "invalid operand for instruction");
824 case Match_MnemonicFail:
825 return Error(IDLoc, "unrecognized instruction mnemonic");
828 llvm_unreachable("Implement any new match types added!");
833 /// ParseDirective parses the arm specific directives
834 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
835 StringRef IDVal = DirectiveID.getIdentifier();
836 if (IDVal == ".word")
837 return ParseDirectiveWord(4, DirectiveID.getLoc());
838 else if (IDVal == ".thumb")
839 return ParseDirectiveThumb(DirectiveID.getLoc());
840 else if (IDVal == ".thumb_func")
841 return ParseDirectiveThumbFunc(DirectiveID.getLoc());
842 else if (IDVal == ".code")
843 return ParseDirectiveCode(DirectiveID.getLoc());
844 else if (IDVal == ".syntax")
845 return ParseDirectiveSyntax(DirectiveID.getLoc());
849 /// ParseDirectiveWord
850 /// ::= .word [ expression (, expression)* ]
851 bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
852 if (getLexer().isNot(AsmToken::EndOfStatement)) {
855 if (getParser().ParseExpression(Value))
858 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
860 if (getLexer().is(AsmToken::EndOfStatement))
863 // FIXME: Improve diagnostic.
864 if (getLexer().isNot(AsmToken::Comma))
865 return Error(L, "unexpected token in directive");
874 /// ParseDirectiveThumb
876 bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
877 if (getLexer().isNot(AsmToken::EndOfStatement))
878 return Error(L, "unexpected token in directive");
881 // TODO: set thumb mode
882 // TODO: tell the MC streamer the mode
883 // getParser().getStreamer().Emit???();
887 /// ParseDirectiveThumbFunc
888 /// ::= .thumbfunc symbol_name
889 bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
890 const AsmToken &Tok = Parser.getTok();
891 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
892 return Error(L, "unexpected token in .syntax directive");
893 Parser.Lex(); // Consume the identifier token.
895 if (getLexer().isNot(AsmToken::EndOfStatement))
896 return Error(L, "unexpected token in directive");
899 // TODO: mark symbol as a thumb symbol
900 // getParser().getStreamer().Emit???();
904 /// ParseDirectiveSyntax
905 /// ::= .syntax unified | divided
906 bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
907 const AsmToken &Tok = Parser.getTok();
908 if (Tok.isNot(AsmToken::Identifier))
909 return Error(L, "unexpected token in .syntax directive");
910 StringRef Mode = Tok.getString();
911 if (Mode == "unified" || Mode == "UNIFIED")
913 else if (Mode == "divided" || Mode == "DIVIDED")
916 return Error(L, "unrecognized syntax mode in .syntax directive");
918 if (getLexer().isNot(AsmToken::EndOfStatement))
919 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
922 // TODO tell the MC streamer the mode
923 // getParser().getStreamer().Emit???();
927 /// ParseDirectiveCode
928 /// ::= .code 16 | 32
929 bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
930 const AsmToken &Tok = Parser.getTok();
931 if (Tok.isNot(AsmToken::Integer))
932 return Error(L, "unexpected token in .code directive");
933 int64_t Val = Parser.getTok().getIntVal();
939 return Error(L, "invalid operand to .code directive");
941 if (getLexer().isNot(AsmToken::EndOfStatement))
942 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
945 // TODO tell the MC streamer the mode
946 // getParser().getStreamer().Emit???();
950 extern "C" void LLVMInitializeARMAsmLexer();
952 /// Force static initialization.
953 extern "C" void LLVMInitializeARMAsmParser() {
954 RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
955 RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
956 LLVMInitializeARMAsmLexer();
959 #define GET_REGISTER_MATCHER
960 #define GET_MATCHER_IMPLEMENTATION
961 #include "ARMGenAsmMatcher.inc"