1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMAddressingModes.h"
12 #include "ARMSubtarget.h"
13 #include "llvm/MC/MCParser/MCAsmLexer.h"
14 #include "llvm/MC/MCParser/MCAsmParser.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/Target/TargetRegistry.h"
21 #include "llvm/Target/TargetAsmParser.h"
22 #include "llvm/Support/SourceMgr.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/ADT/StringSwitch.h"
26 #include "llvm/ADT/Twine.h"
29 // The shift types for register controlled shifts in arm memory addressing
42 class ARMAsmParser : public TargetAsmParser {
46 MCAsmParser &getParser() const { return Parser; }
47 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
49 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
50 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
52 int TryParseRegister();
53 ARMOperand *TryParseRegisterWithWriteBack();
54 ARMOperand *ParseRegisterList();
55 ARMOperand *ParseMemory();
56 ARMOperand *ParseOperand();
58 bool ParseMemoryOffsetReg(bool &Negative,
59 bool &OffsetRegShifted,
60 enum ShiftType &ShiftType,
61 const MCExpr *&ShiftAmount,
62 const MCExpr *&Offset,
66 bool ParseShift(enum ShiftType &St, const MCExpr *&ShiftAmount, SMLoc &E);
67 bool ParseDirectiveWord(unsigned Size, SMLoc L);
68 bool ParseDirectiveThumb(SMLoc L);
69 bool ParseDirectiveThumbFunc(SMLoc L);
70 bool ParseDirectiveCode(SMLoc L);
71 bool ParseDirectiveSyntax(SMLoc L);
73 bool MatchAndEmitInstruction(SMLoc IDLoc,
74 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
77 /// @name Auto-generated Match Functions
80 #define GET_ASSEMBLER_HEADER
81 #include "ARMGenAsmMatcher.inc"
86 ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
87 : TargetAsmParser(T), Parser(_Parser), TM(_TM) {
88 // Initialize the set of available features.
89 setAvailableFeatures(ComputeAvailableFeatures(
90 &TM.getSubtarget<ARMSubtarget>()));
93 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
94 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
95 virtual bool ParseDirective(AsmToken DirectiveID);
97 } // end anonymous namespace
101 /// ARMOperand - Instances of this class represent a parsed ARM machine
103 class ARMOperand : public MCParsedAsmOperand {
113 SMLoc StartLoc, EndLoc;
117 ARMCC::CondCodes Val;
131 SmallVector<unsigned, 32> *Registers;
138 // This is for all forms of ARM address expressions
141 unsigned OffsetRegNum; // used when OffsetIsReg is true
142 const MCExpr *Offset; // used when OffsetIsReg is false
143 const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
144 enum ShiftType ShiftType; // used when OffsetRegShifted is true
145 unsigned OffsetRegShifted : 1; // only used when OffsetIsReg is true
146 unsigned Preindexed : 1;
147 unsigned Postindexed : 1;
148 unsigned OffsetIsReg : 1;
149 unsigned Negative : 1; // only used when OffsetIsReg is true
150 unsigned Writeback : 1;
154 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
156 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
158 StartLoc = o.StartLoc;
183 delete RegList.Registers;
186 /// getStartLoc - Get the location of the first token of this operand.
187 SMLoc getStartLoc() const { return StartLoc; }
188 /// getEndLoc - Get the location of the last token of this operand.
189 SMLoc getEndLoc() const { return EndLoc; }
191 ARMCC::CondCodes getCondCode() const {
192 assert(Kind == CondCode && "Invalid access!");
196 StringRef getToken() const {
197 assert(Kind == Token && "Invalid access!");
198 return StringRef(Tok.Data, Tok.Length);
201 unsigned getReg() const {
202 assert(Kind == Register && "Invalid access!");
206 const SmallVectorImpl<unsigned> &getRegList() const {
207 assert(Kind == RegisterList && "Invalid access!");
208 return *RegList.Registers;
211 const MCExpr *getImm() const {
212 assert(Kind == Immediate && "Invalid access!");
216 bool isCondCode() const { return Kind == CondCode; }
217 bool isImm() const { return Kind == Immediate; }
218 bool isReg() const { return Kind == Register; }
219 bool isRegList() const { return Kind == RegisterList; }
220 bool isToken() const { return Kind == Token; }
221 bool isMemory() const { return Kind == Memory; }
222 bool isMemMode5() const {
223 if (!isMemory() || Mem.OffsetIsReg || Mem.OffsetRegShifted ||
224 Mem.Writeback || Mem.Negative)
226 // If there is an offset expression, make sure it's valid.
229 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
232 // The offset must be a multiple of 4 in the range 0-1020.
233 int64_t Value = CE->getValue();
234 return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020);
237 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
238 // Add as immediates when possible. Null MCExpr = 0.
240 Inst.addOperand(MCOperand::CreateImm(0));
241 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
242 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
244 Inst.addOperand(MCOperand::CreateExpr(Expr));
247 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
248 assert(N == 2 && "Invalid number of operands!");
249 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
250 // FIXME: What belongs here?
251 Inst.addOperand(MCOperand::CreateReg(0));
254 void addRegOperands(MCInst &Inst, unsigned N) const {
255 assert(N == 1 && "Invalid number of operands!");
256 Inst.addOperand(MCOperand::CreateReg(getReg()));
259 void addRegListOperands(MCInst &Inst, unsigned N) const {
260 assert(N == 1 && "Invalid number of operands!");
261 const SmallVectorImpl<unsigned> &RegList = getRegList();
262 for (SmallVectorImpl<unsigned>::const_iterator
263 I = RegList.begin(), E = RegList.end(); I != E; ++I)
264 Inst.addOperand(MCOperand::CreateReg(*I));
267 void addImmOperands(MCInst &Inst, unsigned N) const {
268 assert(N == 1 && "Invalid number of operands!");
269 addExpr(Inst, getImm());
272 void addMemMode5Operands(MCInst &Inst, unsigned N) const {
273 assert(N == 2 && isMemMode5() && "Invalid number of operands!");
275 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
276 assert(!Mem.OffsetIsReg && "Invalid mode 5 operand");
278 // FIXME: #-0 is encoded differently than #0. Does the parser preserve
281 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
282 assert(CE && "Non-constant mode 5 offset operand!");
284 // The MCInst offset operand doesn't include the low two bits (like
285 // the instruction encoding).
286 int64_t Offset = CE->getValue() / 4;
288 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add,
291 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub,
294 Inst.addOperand(MCOperand::CreateImm(0));
298 virtual void dump(raw_ostream &OS) const;
300 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
301 ARMOperand *Op = new ARMOperand(CondCode);
308 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
309 ARMOperand *Op = new ARMOperand(Token);
310 Op->Tok.Data = Str.data();
311 Op->Tok.Length = Str.size();
317 static ARMOperand *CreateReg(unsigned RegNum, bool Writeback, SMLoc S,
319 ARMOperand *Op = new ARMOperand(Register);
320 Op->Reg.RegNum = RegNum;
321 Op->Reg.Writeback = Writeback;
328 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
330 ARMOperand *Op = new ARMOperand(RegisterList);
331 Op->RegList.Registers = new SmallVector<unsigned, 32>();
332 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
333 I = Regs.begin(), E = Regs.end(); I != E; ++I)
334 Op->RegList.Registers->push_back(I->first);
335 std::sort(Op->RegList.Registers->begin(), Op->RegList.Registers->end());
341 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
342 ARMOperand *Op = new ARMOperand(Immediate);
349 static ARMOperand *CreateMem(unsigned BaseRegNum, bool OffsetIsReg,
350 const MCExpr *Offset, unsigned OffsetRegNum,
351 bool OffsetRegShifted, enum ShiftType ShiftType,
352 const MCExpr *ShiftAmount, bool Preindexed,
353 bool Postindexed, bool Negative, bool Writeback,
355 ARMOperand *Op = new ARMOperand(Memory);
356 Op->Mem.BaseRegNum = BaseRegNum;
357 Op->Mem.OffsetIsReg = OffsetIsReg;
358 Op->Mem.Offset = Offset;
359 Op->Mem.OffsetRegNum = OffsetRegNum;
360 Op->Mem.OffsetRegShifted = OffsetRegShifted;
361 Op->Mem.ShiftType = ShiftType;
362 Op->Mem.ShiftAmount = ShiftAmount;
363 Op->Mem.Preindexed = Preindexed;
364 Op->Mem.Postindexed = Postindexed;
365 Op->Mem.Negative = Negative;
366 Op->Mem.Writeback = Writeback;
374 } // end anonymous namespace.
376 void ARMOperand::dump(raw_ostream &OS) const {
379 OS << ARMCondCodeToString(getCondCode());
388 OS << "<register " << getReg() << ">";
391 OS << "<register_list ";
393 const SmallVectorImpl<unsigned> &RegList = getRegList();
394 for (SmallVectorImpl<unsigned>::const_iterator
395 I = RegList.begin(), E = RegList.end(); I != E; ) {
397 if (++I < E) OS << ", ";
404 OS << "'" << getToken() << "'";
409 /// @name Auto-generated Match Functions
412 static unsigned MatchRegisterName(StringRef Name);
416 /// Try to parse a register name. The token must be an Identifier when called,
417 /// and if it is a register name the token is eaten and the register number is
418 /// returned. Otherwise return -1.
420 int ARMAsmParser::TryParseRegister() {
421 const AsmToken &Tok = Parser.getTok();
422 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
424 // FIXME: Validate register for the current architecture; we have to do
425 // validation later, so maybe there is no need for this here.
426 unsigned RegNum = MatchRegisterName(Tok.getString());
429 Parser.Lex(); // Eat identifier token.
434 /// Try to parse a register name. The token must be an Identifier when called,
435 /// and if it is a register name the token is eaten and the register number is
436 /// returned. Otherwise return -1.
438 /// TODO this is likely to change to allow different register types and or to
439 /// parse for a specific register type.
440 ARMOperand *ARMAsmParser::TryParseRegisterWithWriteBack() {
441 SMLoc S = Parser.getTok().getLoc();
442 int RegNo = TryParseRegister();
446 SMLoc E = Parser.getTok().getLoc();
448 bool Writeback = false;
449 const AsmToken &ExclaimTok = Parser.getTok();
450 if (ExclaimTok.is(AsmToken::Exclaim)) {
451 E = ExclaimTok.getLoc();
453 Parser.Lex(); // Eat exclaim token
456 return ARMOperand::CreateReg(RegNo, Writeback, S, E);
459 /// Parse a register list, return it if successful else return null. The first
460 /// token must be a '{' when called.
461 ARMOperand *ARMAsmParser::ParseRegisterList() {
462 assert(Parser.getTok().is(AsmToken::LCurly) &&
463 "Token is not a Left Curly Brace");
464 SMLoc S = Parser.getTok().getLoc();
466 // Read the rest of the registers in the list.
467 unsigned PrevRegNum = 0;
468 SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
471 bool IsRange = Parser.getTok().is(AsmToken::Minus);
472 Parser.Lex(); // Eat non-identifier token.
474 const AsmToken &RegTok = Parser.getTok();
475 SMLoc RegLoc = RegTok.getLoc();
476 if (RegTok.isNot(AsmToken::Identifier)) {
477 Error(RegLoc, "register expected");
481 int RegNum = TryParseRegister();
483 Error(RegLoc, "register expected");
488 int Reg = PrevRegNum;
491 Registers.push_back(std::make_pair(Reg, RegLoc));
492 } while (Reg != RegNum);
494 Registers.push_back(std::make_pair(RegNum, RegLoc));
498 } while (Parser.getTok().is(AsmToken::Comma) ||
499 Parser.getTok().is(AsmToken::Minus));
501 // Process the right curly brace of the list.
502 const AsmToken &RCurlyTok = Parser.getTok();
503 if (RCurlyTok.isNot(AsmToken::RCurly)) {
504 Error(RCurlyTok.getLoc(), "'}' expected");
508 SMLoc E = RCurlyTok.getLoc();
509 Parser.Lex(); // Eat right curly brace token.
511 // Verify the register list.
512 SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
513 RI = Registers.begin(), RE = Registers.end();
515 unsigned HighRegNum = RI->first;
516 DenseMap<unsigned, bool> RegMap;
517 RegMap[RI->first] = true;
519 for (++RI; RI != RE; ++RI) {
520 const std::pair<unsigned, SMLoc> &RegInfo = *RI;
522 if (RegMap[RegInfo.first]) {
523 Error(RegInfo.second, "register duplicated in register list");
527 if (RegInfo.first < HighRegNum)
528 Warning(RegInfo.second,
529 "register not in ascending order in register list");
531 RegMap[RegInfo.first] = true;
532 HighRegNum = std::max(RegInfo.first, HighRegNum);
535 return ARMOperand::CreateRegList(Registers, S, E);
538 /// Parse an ARM memory expression, return false if successful else return true
539 /// or an error. The first token must be a '[' when called.
540 /// TODO Only preindexing and postindexing addressing are started, unindexed
541 /// with option, etc are still to do.
542 ARMOperand *ARMAsmParser::ParseMemory() {
544 assert(Parser.getTok().is(AsmToken::LBrac) &&
545 "Token is not a Left Bracket");
546 S = Parser.getTok().getLoc();
547 Parser.Lex(); // Eat left bracket token.
549 const AsmToken &BaseRegTok = Parser.getTok();
550 if (BaseRegTok.isNot(AsmToken::Identifier)) {
551 Error(BaseRegTok.getLoc(), "register expected");
554 int BaseRegNum = TryParseRegister();
555 if (BaseRegNum == -1) {
556 Error(BaseRegTok.getLoc(), "register expected");
560 bool Preindexed = false;
561 bool Postindexed = false;
562 bool OffsetIsReg = false;
563 bool Negative = false;
564 bool Writeback = false;
566 // First look for preindexed address forms, that is after the "[Rn" we now
567 // have to see if the next token is a comma.
568 const AsmToken &Tok = Parser.getTok();
569 if (Tok.is(AsmToken::Comma)) {
571 Parser.Lex(); // Eat comma token.
573 bool OffsetRegShifted;
574 enum ShiftType ShiftType;
575 const MCExpr *ShiftAmount;
576 const MCExpr *Offset;
577 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
578 Offset, OffsetIsReg, OffsetRegNum, E))
580 const AsmToken &RBracTok = Parser.getTok();
581 if (RBracTok.isNot(AsmToken::RBrac)) {
582 Error(RBracTok.getLoc(), "']' expected");
585 E = RBracTok.getLoc();
586 Parser.Lex(); // Eat right bracket token.
588 const AsmToken &ExclaimTok = Parser.getTok();
589 if (ExclaimTok.is(AsmToken::Exclaim)) {
590 E = ExclaimTok.getLoc();
592 Parser.Lex(); // Eat exclaim token
594 return ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
595 OffsetRegShifted, ShiftType, ShiftAmount,
596 Preindexed, Postindexed, Negative, Writeback,
599 // The "[Rn" we have so far was not followed by a comma.
600 else if (Tok.is(AsmToken::RBrac)) {
601 // If there's anything other than the right brace, this is a post indexing
604 Parser.Lex(); // Eat right bracket token.
606 int OffsetRegNum = 0;
607 bool OffsetRegShifted = false;
608 enum ShiftType ShiftType;
609 const MCExpr *ShiftAmount;
610 const MCExpr *Offset = 0;
612 const AsmToken &NextTok = Parser.getTok();
613 if (NextTok.isNot(AsmToken::EndOfStatement)) {
616 if (NextTok.isNot(AsmToken::Comma)) {
617 Error(NextTok.getLoc(), "',' expected");
620 Parser.Lex(); // Eat comma token.
621 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
622 ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
627 return ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
628 OffsetRegShifted, ShiftType, ShiftAmount,
629 Preindexed, Postindexed, Negative, Writeback,
636 /// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
637 /// we will parse the following (were +/- means that a plus or minus is
642 /// we return false on success or an error otherwise.
643 bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
644 bool &OffsetRegShifted,
645 enum ShiftType &ShiftType,
646 const MCExpr *&ShiftAmount,
647 const MCExpr *&Offset,
652 OffsetRegShifted = false;
655 const AsmToken &NextTok = Parser.getTok();
656 E = NextTok.getLoc();
657 if (NextTok.is(AsmToken::Plus))
658 Parser.Lex(); // Eat plus token.
659 else if (NextTok.is(AsmToken::Minus)) {
661 Parser.Lex(); // Eat minus token
663 // See if there is a register following the "[Rn," or "[Rn]," we have so far.
664 const AsmToken &OffsetRegTok = Parser.getTok();
665 if (OffsetRegTok.is(AsmToken::Identifier)) {
666 SMLoc CurLoc = OffsetRegTok.getLoc();
667 OffsetRegNum = TryParseRegister();
668 if (OffsetRegNum != -1) {
674 // If we parsed a register as the offset then there can be a shift after that.
675 if (OffsetRegNum != -1) {
676 // Look for a comma then a shift
677 const AsmToken &Tok = Parser.getTok();
678 if (Tok.is(AsmToken::Comma)) {
679 Parser.Lex(); // Eat comma token.
681 const AsmToken &Tok = Parser.getTok();
682 if (ParseShift(ShiftType, ShiftAmount, E))
683 return Error(Tok.getLoc(), "shift expected");
684 OffsetRegShifted = true;
687 else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
688 // Look for #offset following the "[Rn," or "[Rn],"
689 const AsmToken &HashTok = Parser.getTok();
690 if (HashTok.isNot(AsmToken::Hash))
691 return Error(HashTok.getLoc(), "'#' expected");
693 Parser.Lex(); // Eat hash token.
695 if (getParser().ParseExpression(Offset))
697 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
702 /// ParseShift as one of these two:
703 /// ( lsl | lsr | asr | ror ) , # shift_amount
705 /// and returns true if it parses a shift otherwise it returns false.
706 bool ARMAsmParser::ParseShift(ShiftType &St, const MCExpr *&ShiftAmount,
708 const AsmToken &Tok = Parser.getTok();
709 if (Tok.isNot(AsmToken::Identifier))
711 StringRef ShiftName = Tok.getString();
712 if (ShiftName == "lsl" || ShiftName == "LSL")
714 else if (ShiftName == "lsr" || ShiftName == "LSR")
716 else if (ShiftName == "asr" || ShiftName == "ASR")
718 else if (ShiftName == "ror" || ShiftName == "ROR")
720 else if (ShiftName == "rrx" || ShiftName == "RRX")
724 Parser.Lex(); // Eat shift type token.
730 // Otherwise, there must be a '#' and a shift amount.
731 const AsmToken &HashTok = Parser.getTok();
732 if (HashTok.isNot(AsmToken::Hash))
733 return Error(HashTok.getLoc(), "'#' expected");
734 Parser.Lex(); // Eat hash token.
736 if (getParser().ParseExpression(ShiftAmount))
742 /// Parse a arm instruction operand. For now this parses the operand regardless
744 ARMOperand *ARMAsmParser::ParseOperand() {
746 switch (getLexer().getKind()) {
748 Error(Parser.getTok().getLoc(), "unexpected token in operand");
750 case AsmToken::Identifier:
751 if (ARMOperand *Op = TryParseRegisterWithWriteBack())
754 // This was not a register so parse other operands that start with an
755 // identifier (like labels) as expressions and create them as immediates.
757 S = Parser.getTok().getLoc();
758 if (getParser().ParseExpression(IdVal))
760 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
761 return ARMOperand::CreateImm(IdVal, S, E);
762 case AsmToken::LBrac:
763 return ParseMemory();
764 case AsmToken::LCurly:
765 return ParseRegisterList();
768 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
769 S = Parser.getTok().getLoc();
771 const MCExpr *ImmVal;
772 if (getParser().ParseExpression(ImmVal))
774 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
775 return ARMOperand::CreateImm(ImmVal, S, E);
779 /// Parse an arm instruction mnemonic followed by its operands.
780 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
781 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
782 // Create the leading tokens for the mnemonic, split by '.' characters.
783 size_t Start = 0, Next = Name.find('.');
784 StringRef Head = Name.slice(Start, Next);
786 // Determine the predicate, if any.
788 // FIXME: We need a way to check whether a prefix supports predication,
789 // otherwise we will end up with an ambiguity for instructions that happen to
790 // end with a predicate name.
791 // FIXME: Likewise, some arithmetic instructions have an 's' prefix which
792 // indicates to update the condition codes. Those instructions have an
793 // additional immediate operand which encodes the prefix as reg0 or CPSR.
794 // Just checking for a suffix of 's' definitely creates ambiguities; e.g,
795 // the SMMLS instruction.
796 unsigned CC = StringSwitch<unsigned>(Head.substr(Head.size()-2))
797 .Case("eq", ARMCC::EQ)
798 .Case("ne", ARMCC::NE)
799 .Case("hs", ARMCC::HS)
800 .Case("lo", ARMCC::LO)
801 .Case("mi", ARMCC::MI)
802 .Case("pl", ARMCC::PL)
803 .Case("vs", ARMCC::VS)
804 .Case("vc", ARMCC::VC)
805 .Case("hi", ARMCC::HI)
806 .Case("ls", ARMCC::LS)
807 .Case("ge", ARMCC::GE)
808 .Case("lt", ARMCC::LT)
809 .Case("gt", ARMCC::GT)
810 .Case("le", ARMCC::LE)
811 .Case("al", ARMCC::AL)
815 (CC == ARMCC::LS && (Head == "vmls" || Head == "vnmls"))) {
818 Head = Head.slice(0, Head.size() - 2);
821 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
822 // FIXME: Should only add this operand for predicated instructions
823 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), NameLoc));
825 // Add the remaining tokens in the mnemonic.
826 while (Next != StringRef::npos) {
828 Next = Name.find('.', Start + 1);
829 Head = Name.slice(Start, Next);
831 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
834 // Read the remaining operands.
835 if (getLexer().isNot(AsmToken::EndOfStatement)) {
836 // Read the first operand.
837 if (ARMOperand *Op = ParseOperand())
838 Operands.push_back(Op);
840 Parser.EatToEndOfStatement();
844 while (getLexer().is(AsmToken::Comma)) {
845 Parser.Lex(); // Eat the comma.
847 // Parse and remember the operand.
848 if (ARMOperand *Op = ParseOperand())
849 Operands.push_back(Op);
851 Parser.EatToEndOfStatement();
857 if (getLexer().isNot(AsmToken::EndOfStatement)) {
858 Parser.EatToEndOfStatement();
859 return TokError("unexpected token in argument list");
862 Parser.Lex(); // Consume the EndOfStatement
867 MatchAndEmitInstruction(SMLoc IDLoc,
868 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
872 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo)) {
874 Out.EmitInstruction(Inst);
876 case Match_MissingFeature:
877 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
879 case Match_InvalidOperand: {
880 SMLoc ErrorLoc = IDLoc;
881 if (ErrorInfo != ~0U) {
882 if (ErrorInfo >= Operands.size())
883 return Error(IDLoc, "too few operands for instruction");
885 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
886 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
889 return Error(ErrorLoc, "invalid operand for instruction");
891 case Match_MnemonicFail:
892 return Error(IDLoc, "unrecognized instruction mnemonic");
895 llvm_unreachable("Implement any new match types added!");
899 /// ParseDirective parses the arm specific directives
900 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
901 StringRef IDVal = DirectiveID.getIdentifier();
902 if (IDVal == ".word")
903 return ParseDirectiveWord(4, DirectiveID.getLoc());
904 else if (IDVal == ".thumb")
905 return ParseDirectiveThumb(DirectiveID.getLoc());
906 else if (IDVal == ".thumb_func")
907 return ParseDirectiveThumbFunc(DirectiveID.getLoc());
908 else if (IDVal == ".code")
909 return ParseDirectiveCode(DirectiveID.getLoc());
910 else if (IDVal == ".syntax")
911 return ParseDirectiveSyntax(DirectiveID.getLoc());
915 /// ParseDirectiveWord
916 /// ::= .word [ expression (, expression)* ]
917 bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
918 if (getLexer().isNot(AsmToken::EndOfStatement)) {
921 if (getParser().ParseExpression(Value))
924 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
926 if (getLexer().is(AsmToken::EndOfStatement))
929 // FIXME: Improve diagnostic.
930 if (getLexer().isNot(AsmToken::Comma))
931 return Error(L, "unexpected token in directive");
940 /// ParseDirectiveThumb
942 bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
943 if (getLexer().isNot(AsmToken::EndOfStatement))
944 return Error(L, "unexpected token in directive");
947 // TODO: set thumb mode
948 // TODO: tell the MC streamer the mode
949 // getParser().getStreamer().Emit???();
953 /// ParseDirectiveThumbFunc
954 /// ::= .thumbfunc symbol_name
955 bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
956 const AsmToken &Tok = Parser.getTok();
957 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
958 return Error(L, "unexpected token in .thumb_func directive");
959 StringRef Name = Tok.getString();
960 Parser.Lex(); // Consume the identifier token.
961 if (getLexer().isNot(AsmToken::EndOfStatement))
962 return Error(L, "unexpected token in directive");
965 // Mark symbol as a thumb symbol.
966 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
967 getParser().getStreamer().EmitThumbFunc(Func);
971 /// ParseDirectiveSyntax
972 /// ::= .syntax unified | divided
973 bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
974 const AsmToken &Tok = Parser.getTok();
975 if (Tok.isNot(AsmToken::Identifier))
976 return Error(L, "unexpected token in .syntax directive");
977 StringRef Mode = Tok.getString();
978 if (Mode == "unified" || Mode == "UNIFIED")
980 else if (Mode == "divided" || Mode == "DIVIDED")
983 return Error(L, "unrecognized syntax mode in .syntax directive");
985 if (getLexer().isNot(AsmToken::EndOfStatement))
986 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
989 // TODO tell the MC streamer the mode
990 // getParser().getStreamer().Emit???();
994 /// ParseDirectiveCode
995 /// ::= .code 16 | 32
996 bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
997 const AsmToken &Tok = Parser.getTok();
998 if (Tok.isNot(AsmToken::Integer))
999 return Error(L, "unexpected token in .code directive");
1000 int64_t Val = Parser.getTok().getIntVal();
1006 return Error(L, "invalid operand to .code directive");
1008 if (getLexer().isNot(AsmToken::EndOfStatement))
1009 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
1013 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
1015 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
1020 extern "C" void LLVMInitializeARMAsmLexer();
1022 /// Force static initialization.
1023 extern "C" void LLVMInitializeARMAsmParser() {
1024 RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
1025 RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
1026 LLVMInitializeARMAsmLexer();
1029 #define GET_REGISTER_MATCHER
1030 #define GET_MATCHER_IMPLEMENTATION
1031 #include "ARMGenAsmMatcher.inc"