1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMAddressingModes.h"
12 #include "ARMSubtarget.h"
13 #include "llvm/MC/MCParser/MCAsmLexer.h"
14 #include "llvm/MC/MCParser/MCAsmParser.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/Target/TargetRegistry.h"
21 #include "llvm/Target/TargetAsmParser.h"
22 #include "llvm/Support/SourceMgr.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/ADT/StringSwitch.h"
26 #include "llvm/ADT/Twine.h"
29 // The shift types for register controlled shifts in arm memory addressing
41 class ARMAsmParser : public TargetAsmParser {
46 MCAsmParser &getParser() const { return Parser; }
48 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
50 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
52 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
54 int TryParseRegister();
55 ARMOperand *TryParseRegisterWithWriteBack();
56 ARMOperand *ParseRegisterList();
57 ARMOperand *ParseMemory();
59 bool ParseMemoryOffsetReg(bool &Negative,
60 bool &OffsetRegShifted,
61 enum ShiftType &ShiftType,
62 const MCExpr *&ShiftAmount,
63 const MCExpr *&Offset,
68 bool ParseShift(enum ShiftType &St, const MCExpr *&ShiftAmount, SMLoc &E);
70 ARMOperand *ParseOperand();
72 bool ParseDirectiveWord(unsigned Size, SMLoc L);
74 bool ParseDirectiveThumb(SMLoc L);
76 bool ParseDirectiveThumbFunc(SMLoc L);
78 bool ParseDirectiveCode(SMLoc L);
80 bool ParseDirectiveSyntax(SMLoc L);
82 bool MatchAndEmitInstruction(SMLoc IDLoc,
83 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
86 /// @name Auto-generated Match Functions
89 #define GET_ASSEMBLER_HEADER
90 #include "ARMGenAsmMatcher.inc"
96 ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
97 : TargetAsmParser(T), Parser(_Parser), TM(_TM) {
98 // Initialize the set of available features.
99 setAvailableFeatures(ComputeAvailableFeatures(
100 &TM.getSubtarget<ARMSubtarget>()));
103 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
104 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
106 virtual bool ParseDirective(AsmToken DirectiveID);
108 } // end anonymous namespace
112 /// ARMOperand - Instances of this class represent a parsed ARM machine
114 struct ARMOperand : public MCParsedAsmOperand {
124 SMLoc StartLoc, EndLoc;
128 ARMCC::CondCodes Val;
145 // This is for all forms of ARM address expressions
148 unsigned OffsetRegNum; // used when OffsetIsReg is true
149 const MCExpr *Offset; // used when OffsetIsReg is false
150 const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
151 enum ShiftType ShiftType; // used when OffsetRegShifted is true
153 OffsetRegShifted : 1, // only used when OffsetIsReg is true
157 Negative : 1, // only used when OffsetIsReg is true
163 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
165 StartLoc = o.StartLoc;
186 /// getStartLoc - Get the location of the first token of this operand.
187 SMLoc getStartLoc() const { return StartLoc; }
188 /// getEndLoc - Get the location of the last token of this operand.
189 SMLoc getEndLoc() const { return EndLoc; }
191 ARMCC::CondCodes getCondCode() const {
192 assert(Kind == CondCode && "Invalid access!");
196 StringRef getToken() const {
197 assert(Kind == Token && "Invalid access!");
198 return StringRef(Tok.Data, Tok.Length);
201 unsigned getReg() const {
202 assert(Kind == Register && "Invalid access!");
206 const MCExpr *getImm() const {
207 assert(Kind == Immediate && "Invalid access!");
211 bool isCondCode() const { return Kind == CondCode; }
212 bool isImm() const { return Kind == Immediate; }
213 bool isReg() const { return Kind == Register; }
214 bool isToken() const { return Kind == Token; }
215 bool isMemory() const { return Kind == Memory; }
217 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
218 // Add as immediates when possible. Null MCExpr = 0.
220 Inst.addOperand(MCOperand::CreateImm(0));
221 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
222 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
224 Inst.addOperand(MCOperand::CreateExpr(Expr));
227 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
228 assert(N == 2 && "Invalid number of operands!");
229 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
230 // FIXME: What belongs here?
231 Inst.addOperand(MCOperand::CreateReg(0));
234 void addRegOperands(MCInst &Inst, unsigned N) const {
235 assert(N == 1 && "Invalid number of operands!");
236 Inst.addOperand(MCOperand::CreateReg(getReg()));
239 void addImmOperands(MCInst &Inst, unsigned N) const {
240 assert(N == 1 && "Invalid number of operands!");
241 addExpr(Inst, getImm());
245 bool isMemMode5() const {
246 if (!isMemory() || Mem.OffsetIsReg || Mem.OffsetRegShifted ||
247 Mem.Writeback || Mem.Negative)
249 // If there is an offset expression, make sure it's valid.
252 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
255 // The offset must be a multiple of 4 in the range 0-1020.
256 int64_t Value = CE->getValue();
257 return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020);
260 void addMemMode5Operands(MCInst &Inst, unsigned N) const {
261 assert(N == 2 && isMemMode5() && "Invalid number of operands!");
263 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
264 assert(!Mem.OffsetIsReg && "invalid mode 5 operand");
266 // FIXME: #-0 is encoded differently than #0. Does the parser preserve
269 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
270 assert(CE && "Non-constant mode 5 offset operand!");
272 // The MCInst offset operand doesn't include the low two bits (like
273 // the instruction encoding).
274 int64_t Offset = CE->getValue() / 4;
276 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add,
279 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub,
282 Inst.addOperand(MCOperand::CreateImm(0));
286 virtual void dump(raw_ostream &OS) const;
288 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
289 ARMOperand *Op = new ARMOperand(CondCode);
296 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
297 ARMOperand *Op = new ARMOperand(Token);
298 Op->Tok.Data = Str.data();
299 Op->Tok.Length = Str.size();
305 static ARMOperand *CreateReg(unsigned RegNum, bool Writeback, SMLoc S,
307 ARMOperand *Op = new ARMOperand(Register);
308 Op->Reg.RegNum = RegNum;
309 Op->Reg.Writeback = Writeback;
315 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
316 ARMOperand *Op = new ARMOperand(Immediate);
323 static ARMOperand *CreateMem(unsigned BaseRegNum, bool OffsetIsReg,
324 const MCExpr *Offset, unsigned OffsetRegNum,
325 bool OffsetRegShifted, enum ShiftType ShiftType,
326 const MCExpr *ShiftAmount, bool Preindexed,
327 bool Postindexed, bool Negative, bool Writeback,
329 ARMOperand *Op = new ARMOperand(Memory);
330 Op->Mem.BaseRegNum = BaseRegNum;
331 Op->Mem.OffsetIsReg = OffsetIsReg;
332 Op->Mem.Offset = Offset;
333 Op->Mem.OffsetRegNum = OffsetRegNum;
334 Op->Mem.OffsetRegShifted = OffsetRegShifted;
335 Op->Mem.ShiftType = ShiftType;
336 Op->Mem.ShiftAmount = ShiftAmount;
337 Op->Mem.Preindexed = Preindexed;
338 Op->Mem.Postindexed = Postindexed;
339 Op->Mem.Negative = Negative;
340 Op->Mem.Writeback = Writeback;
348 ARMOperand(KindTy K) : Kind(K) {}
351 } // end anonymous namespace.
353 void ARMOperand::dump(raw_ostream &OS) const {
356 OS << ARMCondCodeToString(getCondCode());
365 OS << "<register " << getReg() << ">";
368 OS << "'" << getToken() << "'";
373 /// @name Auto-generated Match Functions
376 static unsigned MatchRegisterName(StringRef Name);
380 /// Try to parse a register name. The token must be an Identifier when called,
381 /// and if it is a register name the token is eaten and the register number is
382 /// returned. Otherwise return -1.
384 int ARMAsmParser::TryParseRegister() {
385 const AsmToken &Tok = Parser.getTok();
386 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
388 // FIXME: Validate register for the current architecture; we have to do
389 // validation later, so maybe there is no need for this here.
390 int RegNum = MatchRegisterName(Tok.getString());
393 Parser.Lex(); // Eat identifier token.
398 /// Try to parse a register name. The token must be an Identifier when called,
399 /// and if it is a register name the token is eaten and the register number is
400 /// returned. Otherwise return -1.
402 /// TODO this is likely to change to allow different register types and or to
403 /// parse for a specific register type.
404 ARMOperand *ARMAsmParser::TryParseRegisterWithWriteBack() {
405 SMLoc S = Parser.getTok().getLoc();
406 int RegNo = TryParseRegister();
407 if (RegNo == -1) return 0;
409 SMLoc E = Parser.getTok().getLoc();
411 bool Writeback = false;
412 const AsmToken &ExclaimTok = Parser.getTok();
413 if (ExclaimTok.is(AsmToken::Exclaim)) {
414 E = ExclaimTok.getLoc();
416 Parser.Lex(); // Eat exclaim token
419 return ARMOperand::CreateReg(RegNo, Writeback, S, E);
422 /// Parse a register list, return it if successful else return null. The first
423 /// token must be a '{' when called.
424 ARMOperand *ARMAsmParser::ParseRegisterList() {
426 assert(Parser.getTok().is(AsmToken::LCurly) &&
427 "Token is not an Left Curly Brace");
428 S = Parser.getTok().getLoc();
429 Parser.Lex(); // Eat left curly brace token.
431 const AsmToken &RegTok = Parser.getTok();
432 SMLoc RegLoc = RegTok.getLoc();
433 if (RegTok.isNot(AsmToken::Identifier)) {
434 Error(RegLoc, "register expected");
437 int RegNum = MatchRegisterName(RegTok.getString());
439 Error(RegLoc, "register expected");
443 Parser.Lex(); // Eat identifier token.
444 unsigned RegList = 1 << RegNum;
446 int HighRegNum = RegNum;
447 // TODO ranges like "{Rn-Rm}"
448 while (Parser.getTok().is(AsmToken::Comma)) {
449 Parser.Lex(); // Eat comma token.
451 const AsmToken &RegTok = Parser.getTok();
452 SMLoc RegLoc = RegTok.getLoc();
453 if (RegTok.isNot(AsmToken::Identifier)) {
454 Error(RegLoc, "register expected");
457 int RegNum = MatchRegisterName(RegTok.getString());
459 Error(RegLoc, "register expected");
463 if (RegList & (1 << RegNum))
464 Warning(RegLoc, "register duplicated in register list");
465 else if (RegNum <= HighRegNum)
466 Warning(RegLoc, "register not in ascending order in register list");
467 RegList |= 1 << RegNum;
470 Parser.Lex(); // Eat identifier token.
472 const AsmToken &RCurlyTok = Parser.getTok();
473 if (RCurlyTok.isNot(AsmToken::RCurly)) {
474 Error(RCurlyTok.getLoc(), "'}' expected");
477 E = RCurlyTok.getLoc();
478 Parser.Lex(); // Eat left curly brace token.
480 // FIXME: Need to return an operand!
481 Error(E, "FIXME: register list parsing not implemented");
485 /// Parse an arm memory expression, return false if successful else return true
486 /// or an error. The first token must be a '[' when called.
487 /// TODO Only preindexing and postindexing addressing are started, unindexed
488 /// with option, etc are still to do.
489 ARMOperand *ARMAsmParser::ParseMemory() {
491 assert(Parser.getTok().is(AsmToken::LBrac) &&
492 "Token is not an Left Bracket");
493 S = Parser.getTok().getLoc();
494 Parser.Lex(); // Eat left bracket token.
496 const AsmToken &BaseRegTok = Parser.getTok();
497 if (BaseRegTok.isNot(AsmToken::Identifier)) {
498 Error(BaseRegTok.getLoc(), "register expected");
501 int BaseRegNum = TryParseRegister();
502 if (BaseRegNum == -1) {
503 Error(BaseRegTok.getLoc(), "register expected");
507 bool Preindexed = false;
508 bool Postindexed = false;
509 bool OffsetIsReg = false;
510 bool Negative = false;
511 bool Writeback = false;
513 // First look for preindexed address forms, that is after the "[Rn" we now
514 // have to see if the next token is a comma.
515 const AsmToken &Tok = Parser.getTok();
516 if (Tok.is(AsmToken::Comma)) {
518 Parser.Lex(); // Eat comma token.
520 bool OffsetRegShifted;
521 enum ShiftType ShiftType;
522 const MCExpr *ShiftAmount;
523 const MCExpr *Offset;
524 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
525 Offset, OffsetIsReg, OffsetRegNum, E))
527 const AsmToken &RBracTok = Parser.getTok();
528 if (RBracTok.isNot(AsmToken::RBrac)) {
529 Error(RBracTok.getLoc(), "']' expected");
532 E = RBracTok.getLoc();
533 Parser.Lex(); // Eat right bracket token.
535 const AsmToken &ExclaimTok = Parser.getTok();
536 if (ExclaimTok.is(AsmToken::Exclaim)) {
537 E = ExclaimTok.getLoc();
539 Parser.Lex(); // Eat exclaim token
541 return ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
542 OffsetRegShifted, ShiftType, ShiftAmount,
543 Preindexed, Postindexed, Negative, Writeback,
546 // The "[Rn" we have so far was not followed by a comma.
547 else if (Tok.is(AsmToken::RBrac)) {
548 // If there's anything other than the right brace, this is a post indexing
551 Parser.Lex(); // Eat right bracket token.
553 int OffsetRegNum = 0;
554 bool OffsetRegShifted = false;
555 enum ShiftType ShiftType;
556 const MCExpr *ShiftAmount;
557 const MCExpr *Offset = 0;
559 const AsmToken &NextTok = Parser.getTok();
560 if (NextTok.isNot(AsmToken::EndOfStatement)) {
563 if (NextTok.isNot(AsmToken::Comma)) {
564 Error(NextTok.getLoc(), "',' expected");
567 Parser.Lex(); // Eat comma token.
568 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
569 ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
574 return ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
575 OffsetRegShifted, ShiftType, ShiftAmount,
576 Preindexed, Postindexed, Negative, Writeback,
583 /// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
584 /// we will parse the following (were +/- means that a plus or minus is
589 /// we return false on success or an error otherwise.
590 bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
591 bool &OffsetRegShifted,
592 enum ShiftType &ShiftType,
593 const MCExpr *&ShiftAmount,
594 const MCExpr *&Offset,
599 OffsetRegShifted = false;
602 const AsmToken &NextTok = Parser.getTok();
603 E = NextTok.getLoc();
604 if (NextTok.is(AsmToken::Plus))
605 Parser.Lex(); // Eat plus token.
606 else if (NextTok.is(AsmToken::Minus)) {
608 Parser.Lex(); // Eat minus token
610 // See if there is a register following the "[Rn," or "[Rn]," we have so far.
611 const AsmToken &OffsetRegTok = Parser.getTok();
612 if (OffsetRegTok.is(AsmToken::Identifier)) {
613 SMLoc CurLoc = OffsetRegTok.getLoc();
614 OffsetRegNum = TryParseRegister();
615 if (OffsetRegNum != -1) {
621 // If we parsed a register as the offset then their can be a shift after that
622 if (OffsetRegNum != -1) {
623 // Look for a comma then a shift
624 const AsmToken &Tok = Parser.getTok();
625 if (Tok.is(AsmToken::Comma)) {
626 Parser.Lex(); // Eat comma token.
628 const AsmToken &Tok = Parser.getTok();
629 if (ParseShift(ShiftType, ShiftAmount, E))
630 return Error(Tok.getLoc(), "shift expected");
631 OffsetRegShifted = true;
634 else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
635 // Look for #offset following the "[Rn," or "[Rn],"
636 const AsmToken &HashTok = Parser.getTok();
637 if (HashTok.isNot(AsmToken::Hash))
638 return Error(HashTok.getLoc(), "'#' expected");
640 Parser.Lex(); // Eat hash token.
642 if (getParser().ParseExpression(Offset))
644 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
649 /// ParseShift as one of these two:
650 /// ( lsl | lsr | asr | ror ) , # shift_amount
652 /// and returns true if it parses a shift otherwise it returns false.
653 bool ARMAsmParser::ParseShift(ShiftType &St, const MCExpr *&ShiftAmount,
655 const AsmToken &Tok = Parser.getTok();
656 if (Tok.isNot(AsmToken::Identifier))
658 StringRef ShiftName = Tok.getString();
659 if (ShiftName == "lsl" || ShiftName == "LSL")
661 else if (ShiftName == "lsr" || ShiftName == "LSR")
663 else if (ShiftName == "asr" || ShiftName == "ASR")
665 else if (ShiftName == "ror" || ShiftName == "ROR")
667 else if (ShiftName == "rrx" || ShiftName == "RRX")
671 Parser.Lex(); // Eat shift type token.
677 // Otherwise, there must be a '#' and a shift amount.
678 const AsmToken &HashTok = Parser.getTok();
679 if (HashTok.isNot(AsmToken::Hash))
680 return Error(HashTok.getLoc(), "'#' expected");
681 Parser.Lex(); // Eat hash token.
683 if (getParser().ParseExpression(ShiftAmount))
689 /// Parse a arm instruction operand. For now this parses the operand regardless
691 ARMOperand *ARMAsmParser::ParseOperand() {
694 switch (getLexer().getKind()) {
695 case AsmToken::Identifier:
696 if (ARMOperand *Op = TryParseRegisterWithWriteBack())
699 // This was not a register so parse other operands that start with an
700 // identifier (like labels) as expressions and create them as immediates.
702 S = Parser.getTok().getLoc();
703 if (getParser().ParseExpression(IdVal))
705 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
706 return ARMOperand::CreateImm(IdVal, S, E);
707 case AsmToken::LBrac:
708 return ParseMemory();
709 case AsmToken::LCurly:
710 return ParseRegisterList();
713 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
714 S = Parser.getTok().getLoc();
716 const MCExpr *ImmVal;
717 if (getParser().ParseExpression(ImmVal))
719 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
720 return ARMOperand::CreateImm(ImmVal, S, E);
722 Error(Parser.getTok().getLoc(), "unexpected token in operand");
727 /// Parse an arm instruction mnemonic followed by its operands.
728 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
729 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
730 // Create the leading tokens for the mnemonic, split by '.' characters.
731 size_t Start = 0, Next = Name.find('.');
732 StringRef Head = Name.slice(Start, Next);
734 // Determine the predicate, if any.
736 // FIXME: We need a way to check whether a prefix supports predication,
737 // otherwise we will end up with an ambiguity for instructions that happen to
738 // end with a predicate name.
739 // FIXME: Likewise, some arithmetic instructions have an 's' prefix which
740 // indicates to update the condition codes. Those instructions have an
741 // additional immediate operand which encodes the prefix as reg0 or CPSR.
742 // Just checking for a suffix of 's' definitely creates ambiguities; e.g,
743 // the SMMLS instruction.
744 unsigned CC = StringSwitch<unsigned>(Head.substr(Head.size()-2))
745 .Case("eq", ARMCC::EQ)
746 .Case("ne", ARMCC::NE)
747 .Case("hs", ARMCC::HS)
748 .Case("lo", ARMCC::LO)
749 .Case("mi", ARMCC::MI)
750 .Case("pl", ARMCC::PL)
751 .Case("vs", ARMCC::VS)
752 .Case("vc", ARMCC::VC)
753 .Case("hi", ARMCC::HI)
754 .Case("ls", ARMCC::LS)
755 .Case("ge", ARMCC::GE)
756 .Case("lt", ARMCC::LT)
757 .Case("gt", ARMCC::GT)
758 .Case("le", ARMCC::LE)
759 .Case("al", ARMCC::AL)
763 (CC == ARMCC::LS && (Head == "vmls" || Head == "vnmls"))) {
766 Head = Head.slice(0, Head.size() - 2);
769 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
770 // FIXME: Should only add this operand for predicated instructions
771 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), NameLoc));
773 // Add the remaining tokens in the mnemonic.
774 while (Next != StringRef::npos) {
776 Next = Name.find('.', Start + 1);
777 Head = Name.slice(Start, Next);
779 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
782 // Read the remaining operands.
783 if (getLexer().isNot(AsmToken::EndOfStatement)) {
784 // Read the first operand.
785 if (ARMOperand *Op = ParseOperand())
786 Operands.push_back(Op);
788 Parser.EatToEndOfStatement();
792 while (getLexer().is(AsmToken::Comma)) {
793 Parser.Lex(); // Eat the comma.
795 // Parse and remember the operand.
796 if (ARMOperand *Op = ParseOperand())
797 Operands.push_back(Op);
799 Parser.EatToEndOfStatement();
805 if (getLexer().isNot(AsmToken::EndOfStatement)) {
806 Parser.EatToEndOfStatement();
807 return TokError("unexpected token in argument list");
809 Parser.Lex(); // Consume the EndOfStatement
814 MatchAndEmitInstruction(SMLoc IDLoc,
815 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
819 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo)) {
821 Out.EmitInstruction(Inst);
824 case Match_MissingFeature:
825 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
827 case Match_InvalidOperand: {
828 SMLoc ErrorLoc = IDLoc;
829 if (ErrorInfo != ~0U) {
830 if (ErrorInfo >= Operands.size())
831 return Error(IDLoc, "too few operands for instruction");
833 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
834 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
837 return Error(ErrorLoc, "invalid operand for instruction");
839 case Match_MnemonicFail:
840 return Error(IDLoc, "unrecognized instruction mnemonic");
843 llvm_unreachable("Implement any new match types added!");
848 /// ParseDirective parses the arm specific directives
849 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
850 StringRef IDVal = DirectiveID.getIdentifier();
851 if (IDVal == ".word")
852 return ParseDirectiveWord(4, DirectiveID.getLoc());
853 else if (IDVal == ".thumb")
854 return ParseDirectiveThumb(DirectiveID.getLoc());
855 else if (IDVal == ".thumb_func")
856 return ParseDirectiveThumbFunc(DirectiveID.getLoc());
857 else if (IDVal == ".code")
858 return ParseDirectiveCode(DirectiveID.getLoc());
859 else if (IDVal == ".syntax")
860 return ParseDirectiveSyntax(DirectiveID.getLoc());
864 /// ParseDirectiveWord
865 /// ::= .word [ expression (, expression)* ]
866 bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
867 if (getLexer().isNot(AsmToken::EndOfStatement)) {
870 if (getParser().ParseExpression(Value))
873 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
875 if (getLexer().is(AsmToken::EndOfStatement))
878 // FIXME: Improve diagnostic.
879 if (getLexer().isNot(AsmToken::Comma))
880 return Error(L, "unexpected token in directive");
889 /// ParseDirectiveThumb
891 bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
892 if (getLexer().isNot(AsmToken::EndOfStatement))
893 return Error(L, "unexpected token in directive");
896 // TODO: set thumb mode
897 // TODO: tell the MC streamer the mode
898 // getParser().getStreamer().Emit???();
902 /// ParseDirectiveThumbFunc
903 /// ::= .thumbfunc symbol_name
904 bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
905 const AsmToken &Tok = Parser.getTok();
906 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
907 return Error(L, "unexpected token in .thumb_func directive");
908 StringRef Name = Tok.getString();
909 Parser.Lex(); // Consume the identifier token.
910 if (getLexer().isNot(AsmToken::EndOfStatement))
911 return Error(L, "unexpected token in directive");
914 // Mark symbol as a thumb symbol.
915 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
916 getParser().getStreamer().EmitThumbFunc(Func);
920 /// ParseDirectiveSyntax
921 /// ::= .syntax unified | divided
922 bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
923 const AsmToken &Tok = Parser.getTok();
924 if (Tok.isNot(AsmToken::Identifier))
925 return Error(L, "unexpected token in .syntax directive");
926 StringRef Mode = Tok.getString();
927 if (Mode == "unified" || Mode == "UNIFIED")
929 else if (Mode == "divided" || Mode == "DIVIDED")
932 return Error(L, "unrecognized syntax mode in .syntax directive");
934 if (getLexer().isNot(AsmToken::EndOfStatement))
935 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
938 // TODO tell the MC streamer the mode
939 // getParser().getStreamer().Emit???();
943 /// ParseDirectiveCode
944 /// ::= .code 16 | 32
945 bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
946 const AsmToken &Tok = Parser.getTok();
947 if (Tok.isNot(AsmToken::Integer))
948 return Error(L, "unexpected token in .code directive");
949 int64_t Val = Parser.getTok().getIntVal();
955 return Error(L, "invalid operand to .code directive");
957 if (getLexer().isNot(AsmToken::EndOfStatement))
958 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
961 // TODO tell the MC streamer the mode
962 // getParser().getStreamer().Emit???();
966 extern "C" void LLVMInitializeARMAsmLexer();
968 /// Force static initialization.
969 extern "C" void LLVMInitializeARMAsmParser() {
970 RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
971 RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
972 LLVMInitializeARMAsmLexer();
975 #define GET_REGISTER_MATCHER
976 #define GET_MATCHER_IMPLEMENTATION
977 #include "ARMGenAsmMatcher.inc"