1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "ARMFPUName.h"
11 #include "ARMFeatures.h"
12 #include "llvm/MC/MCTargetAsmParser.h"
13 #include "MCTargetDesc/ARMAddressingModes.h"
14 #include "MCTargetDesc/ARMBuildAttrs.h"
15 #include "MCTargetDesc/ARMArchName.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "MCTargetDesc/ARMMCExpr.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/MapVector.h"
20 #include "llvm/ADT/OwningPtr.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/StringExtras.h"
24 #include "llvm/ADT/StringSwitch.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/MC/MCAsmInfo.h"
27 #include "llvm/MC/MCAssembler.h"
28 #include "llvm/MC/MCContext.h"
29 #include "llvm/MC/MCDisassembler.h"
30 #include "llvm/MC/MCELFStreamer.h"
31 #include "llvm/MC/MCExpr.h"
32 #include "llvm/MC/MCInst.h"
33 #include "llvm/MC/MCInstrDesc.h"
34 #include "llvm/MC/MCInstrInfo.h"
35 #include "llvm/MC/MCSection.h"
36 #include "llvm/MC/MCParser/MCAsmLexer.h"
37 #include "llvm/MC/MCParser/MCAsmParser.h"
38 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
39 #include "llvm/MC/MCRegisterInfo.h"
40 #include "llvm/MC/MCStreamer.h"
41 #include "llvm/MC/MCSubtargetInfo.h"
42 #include "llvm/MC/MCSymbol.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/ELF.h"
45 #include "llvm/Support/MathExtras.h"
46 #include "llvm/Support/SourceMgr.h"
47 #include "llvm/Support/TargetRegistry.h"
48 #include "llvm/Support/raw_ostream.h"
56 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
58 // A class to keep track of assembler-generated constant pools that are use to
59 // implement the ldr-pseudo.
61 typedef SmallVector<std::pair<MCSymbol *, const MCExpr *>, 4> EntryVecTy;
65 // Initialize a new empty constant pool
68 // Add a new entry to the constant pool in the next slot.
69 // \param Value is the new entry to put in the constant pool.
71 // \returns a MCExpr that references the newly inserted value
72 const MCExpr *addEntry(const MCExpr *Value, MCContext &Context) {
73 MCSymbol *CPEntryLabel = Context.CreateTempSymbol();
75 Entries.push_back(std::make_pair(CPEntryLabel, Value));
76 return MCSymbolRefExpr::Create(CPEntryLabel, Context);
79 // Emit the contents of the constant pool using the provided streamer.
80 void emitEntries(MCStreamer &Streamer) {
83 Streamer.EmitCodeAlignment(4); // align to 4-byte address
84 Streamer.EmitDataRegion(MCDR_DataRegion);
85 for (EntryVecTy::const_iterator I = Entries.begin(), E = Entries.end();
87 Streamer.EmitLabel(I->first);
88 Streamer.EmitValue(I->second, 4);
90 Streamer.EmitDataRegion(MCDR_DataRegionEnd);
94 // Return true if the constant pool is empty
96 return Entries.empty();
100 // Map type used to keep track of per-Section constant pools used by the
101 // ldr-pseudo opcode. The map associates a section to its constant pool. The
102 // constant pool is a vector of (label, value) pairs. When the ldr
103 // pseudo is parsed we insert a new (label, value) pair into the constant pool
104 // for the current section and add MCSymbolRefExpr to the new label as
105 // an opcode to the ldr. After we have parsed all the user input we
106 // output the (label, value) pairs in each constant pool at the end of the
109 // We use the MapVector for the map type to ensure stable iteration of
110 // the sections at the end of the parse. We need to iterate over the
111 // sections in a stable order to ensure that we have print the
112 // constant pools in a deterministic order when printing an assembly
114 typedef MapVector<const MCSection *, ConstantPool> ConstantPoolMapTy;
116 class UnwindContext {
119 typedef SmallVector<SMLoc, 4> Locs;
123 Locs PersonalityLocs;
124 Locs HandlerDataLocs;
128 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(-1) {}
130 bool hasFnStart() const { return !FnStartLocs.empty(); }
131 bool cantUnwind() const { return !CantUnwindLocs.empty(); }
132 bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
133 bool hasPersonality() const { return !PersonalityLocs.empty(); }
135 void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
136 void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
137 void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
138 void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
140 void saveFPReg(int Reg) { FPReg = Reg; }
141 int getFPReg() const { return FPReg; }
143 void emitFnStartLocNotes() const {
144 for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
146 Parser.Note(*FI, ".fnstart was specified here");
148 void emitCantUnwindLocNotes() const {
149 for (Locs::const_iterator UI = CantUnwindLocs.begin(),
150 UE = CantUnwindLocs.end(); UI != UE; ++UI)
151 Parser.Note(*UI, ".cantunwind was specified here");
153 void emitHandlerDataLocNotes() const {
154 for (Locs::const_iterator HI = HandlerDataLocs.begin(),
155 HE = HandlerDataLocs.end(); HI != HE; ++HI)
156 Parser.Note(*HI, ".handlerdata was specified here");
158 void emitPersonalityLocNotes() const {
159 for (Locs::const_iterator PI = PersonalityLocs.begin(),
160 PE = PersonalityLocs.end(); PI != PE; ++PI)
161 Parser.Note(*PI, ".personality was specified here");
165 FnStartLocs = Locs();
166 CantUnwindLocs = Locs();
167 PersonalityLocs = Locs();
168 HandlerDataLocs = Locs();
173 class ARMAsmParser : public MCTargetAsmParser {
174 MCSubtargetInfo &STI;
176 const MCInstrInfo &MII;
177 const MCRegisterInfo *MRI;
178 ConstantPoolMapTy ConstantPools;
181 // Assembler created constant pools for ldr pseudo
182 ConstantPool *getConstantPool(const MCSection *Section) {
183 ConstantPoolMapTy::iterator CP = ConstantPools.find(Section);
184 if (CP == ConstantPools.end())
190 ConstantPool &getOrCreateConstantPool(const MCSection *Section) {
191 return ConstantPools[Section];
194 ARMTargetStreamer &getTargetStreamer() {
195 MCTargetStreamer &TS = getParser().getStreamer().getTargetStreamer();
196 return static_cast<ARMTargetStreamer &>(TS);
199 // Map of register aliases registers via the .req directive.
200 StringMap<unsigned> RegisterReqs;
202 bool NextSymbolIsThumb;
205 ARMCC::CondCodes Cond; // Condition for IT block.
206 unsigned Mask:4; // Condition mask for instructions.
207 // Starting at first 1 (from lsb).
208 // '1' condition as indicated in IT.
209 // '0' inverse of condition (else).
210 // Count of instructions in IT block is
211 // 4 - trailingzeroes(mask)
213 bool FirstCond; // Explicit flag for when we're parsing the
214 // First instruction in the IT block. It's
215 // implied in the mask, so needs special
218 unsigned CurPosition; // Current position in parsing of IT
219 // block. In range [0,3]. Initialized
220 // according to count of instructions in block.
221 // ~0U if no active IT block.
223 bool inITBlock() { return ITState.CurPosition != ~0U;}
224 void forwardITPosition() {
225 if (!inITBlock()) return;
226 // Move to the next instruction in the IT block, if there is one. If not,
227 // mark the block as done.
228 unsigned TZ = countTrailingZeros(ITState.Mask);
229 if (++ITState.CurPosition == 5 - TZ)
230 ITState.CurPosition = ~0U; // Done with the IT block after this.
234 MCAsmParser &getParser() const { return Parser; }
235 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
237 void Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges = None) {
238 return Parser.Note(L, Msg, Ranges);
240 bool Warning(SMLoc L, const Twine &Msg,
241 ArrayRef<SMRange> Ranges = None) {
242 return Parser.Warning(L, Msg, Ranges);
244 bool Error(SMLoc L, const Twine &Msg,
245 ArrayRef<SMRange> Ranges = None) {
246 return Parser.Error(L, Msg, Ranges);
249 int tryParseRegister();
250 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
251 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
252 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
253 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
254 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
255 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
256 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
257 unsigned &ShiftAmount);
258 bool parseDirectiveWord(unsigned Size, SMLoc L);
259 bool parseDirectiveThumb(SMLoc L);
260 bool parseDirectiveARM(SMLoc L);
261 bool parseDirectiveThumbFunc(SMLoc L);
262 bool parseDirectiveCode(SMLoc L);
263 bool parseDirectiveSyntax(SMLoc L);
264 bool parseDirectiveReq(StringRef Name, SMLoc L);
265 bool parseDirectiveUnreq(SMLoc L);
266 bool parseDirectiveArch(SMLoc L);
267 bool parseDirectiveEabiAttr(SMLoc L);
268 bool parseDirectiveCPU(SMLoc L);
269 bool parseDirectiveFPU(SMLoc L);
270 bool parseDirectiveFnStart(SMLoc L);
271 bool parseDirectiveFnEnd(SMLoc L);
272 bool parseDirectiveCantUnwind(SMLoc L);
273 bool parseDirectivePersonality(SMLoc L);
274 bool parseDirectiveHandlerData(SMLoc L);
275 bool parseDirectiveSetFP(SMLoc L);
276 bool parseDirectivePad(SMLoc L);
277 bool parseDirectiveRegSave(SMLoc L, bool IsVector);
278 bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
279 bool parseDirectiveLtorg(SMLoc L);
280 bool parseDirectiveEven(SMLoc L);
282 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
283 bool &CarrySetting, unsigned &ProcessorIMod,
285 void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
286 bool &CanAcceptCarrySet,
287 bool &CanAcceptPredicationCode);
289 bool isThumb() const {
290 // FIXME: Can tablegen auto-generate this?
291 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
293 bool isThumbOne() const {
294 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
296 bool isThumbTwo() const {
297 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
299 bool hasThumb() const {
300 return STI.getFeatureBits() & ARM::HasV4TOps;
302 bool hasV6Ops() const {
303 return STI.getFeatureBits() & ARM::HasV6Ops;
305 bool hasV6MOps() const {
306 return STI.getFeatureBits() & ARM::HasV6MOps;
308 bool hasV7Ops() const {
309 return STI.getFeatureBits() & ARM::HasV7Ops;
311 bool hasV8Ops() const {
312 return STI.getFeatureBits() & ARM::HasV8Ops;
314 bool hasARM() const {
315 return !(STI.getFeatureBits() & ARM::FeatureNoARM);
319 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
320 setAvailableFeatures(FB);
322 bool isMClass() const {
323 return STI.getFeatureBits() & ARM::FeatureMClass;
326 /// @name Auto-generated Match Functions
329 #define GET_ASSEMBLER_HEADER
330 #include "ARMGenAsmMatcher.inc"
334 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
335 OperandMatchResultTy parseCoprocNumOperand(
336 SmallVectorImpl<MCParsedAsmOperand*>&);
337 OperandMatchResultTy parseCoprocRegOperand(
338 SmallVectorImpl<MCParsedAsmOperand*>&);
339 OperandMatchResultTy parseCoprocOptionOperand(
340 SmallVectorImpl<MCParsedAsmOperand*>&);
341 OperandMatchResultTy parseMemBarrierOptOperand(
342 SmallVectorImpl<MCParsedAsmOperand*>&);
343 OperandMatchResultTy parseInstSyncBarrierOptOperand(
344 SmallVectorImpl<MCParsedAsmOperand*>&);
345 OperandMatchResultTy parseProcIFlagsOperand(
346 SmallVectorImpl<MCParsedAsmOperand*>&);
347 OperandMatchResultTy parseMSRMaskOperand(
348 SmallVectorImpl<MCParsedAsmOperand*>&);
349 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
350 StringRef Op, int Low, int High);
351 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
352 return parsePKHImm(O, "lsl", 0, 31);
354 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
355 return parsePKHImm(O, "asr", 1, 32);
357 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
358 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
359 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
360 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
361 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
362 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
363 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
364 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
365 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
368 // Asm Match Converter Methods
369 void cvtThumbMultiply(MCInst &Inst,
370 const SmallVectorImpl<MCParsedAsmOperand*> &);
371 void cvtThumbBranches(MCInst &Inst,
372 const SmallVectorImpl<MCParsedAsmOperand*> &);
374 bool validateInstruction(MCInst &Inst,
375 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
376 bool processInstruction(MCInst &Inst,
377 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
378 bool shouldOmitCCOutOperand(StringRef Mnemonic,
379 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
380 bool shouldOmitPredicateOperand(StringRef Mnemonic,
381 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
383 enum ARMMatchResultTy {
384 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
385 Match_RequiresNotITBlock,
387 Match_RequiresThumb2,
388 #define GET_OPERAND_DIAGNOSTIC_TYPES
389 #include "ARMGenAsmMatcher.inc"
393 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
394 const MCInstrInfo &MII)
395 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(MII), UC(_Parser) {
396 MCAsmParserExtension::Initialize(_Parser);
398 // Cache the MCRegisterInfo.
399 MRI = getContext().getRegisterInfo();
401 // Initialize the set of available features.
402 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
404 // Not in an ITBlock to start with.
405 ITState.CurPosition = ~0U;
407 NextSymbolIsThumb = false;
410 // Implementation of the MCTargetAsmParser interface:
411 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
412 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
414 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
415 bool ParseDirective(AsmToken DirectiveID);
417 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
418 unsigned checkTargetMatchPredicate(MCInst &Inst);
420 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
421 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
422 MCStreamer &Out, unsigned &ErrorInfo,
423 bool MatchingInlineAsm);
424 void onLabelParsed(MCSymbol *Symbol);
427 } // end anonymous namespace
431 /// ARMOperand - Instances of this class represent a parsed ARM machine
433 class ARMOperand : public MCParsedAsmOperand {
443 k_InstSyncBarrierOpt,
454 k_VectorListAllLanes,
460 k_BitfieldDescriptor,
464 SMLoc StartLoc, EndLoc;
465 SmallVector<unsigned, 8> Registers;
468 ARMCC::CondCodes Val;
475 struct CoprocOptionOp {
488 ARM_ISB::InstSyncBOpt Val;
492 ARM_PROC::IFlags Val;
508 // A vector register list is a sequential list of 1 to 4 registers.
509 struct VectorListOp {
516 struct VectorIndexOp {
524 /// Combined record for all forms of ARM address expressions.
527 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
529 const MCConstantExpr *OffsetImm; // Offset immediate value
530 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
531 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
532 unsigned ShiftImm; // shift for OffsetReg.
533 unsigned Alignment; // 0 = no alignment specified
534 // n = alignment in bytes (2, 4, 8, 16, or 32)
535 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
538 struct PostIdxRegOp {
541 ARM_AM::ShiftOpc ShiftTy;
545 struct ShifterImmOp {
550 struct RegShiftedRegOp {
551 ARM_AM::ShiftOpc ShiftTy;
557 struct RegShiftedImmOp {
558 ARM_AM::ShiftOpc ShiftTy;
575 struct CoprocOptionOp CoprocOption;
576 struct MBOptOp MBOpt;
577 struct ISBOptOp ISBOpt;
578 struct ITMaskOp ITMask;
579 struct IFlagsOp IFlags;
580 struct MMaskOp MMask;
583 struct VectorListOp VectorList;
584 struct VectorIndexOp VectorIndex;
586 struct MemoryOp Memory;
587 struct PostIdxRegOp PostIdxReg;
588 struct ShifterImmOp ShifterImm;
589 struct RegShiftedRegOp RegShiftedReg;
590 struct RegShiftedImmOp RegShiftedImm;
591 struct RotImmOp RotImm;
592 struct BitfieldOp Bitfield;
595 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
597 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
599 StartLoc = o.StartLoc;
616 case k_DPRRegisterList:
617 case k_SPRRegisterList:
618 Registers = o.Registers;
621 case k_VectorListAllLanes:
622 case k_VectorListIndexed:
623 VectorList = o.VectorList;
630 CoprocOption = o.CoprocOption;
635 case k_MemBarrierOpt:
638 case k_InstSyncBarrierOpt:
643 case k_PostIndexRegister:
644 PostIdxReg = o.PostIdxReg;
652 case k_ShifterImmediate:
653 ShifterImm = o.ShifterImm;
655 case k_ShiftedRegister:
656 RegShiftedReg = o.RegShiftedReg;
658 case k_ShiftedImmediate:
659 RegShiftedImm = o.RegShiftedImm;
661 case k_RotateImmediate:
664 case k_BitfieldDescriptor:
665 Bitfield = o.Bitfield;
668 VectorIndex = o.VectorIndex;
673 /// getStartLoc - Get the location of the first token of this operand.
674 SMLoc getStartLoc() const { return StartLoc; }
675 /// getEndLoc - Get the location of the last token of this operand.
676 SMLoc getEndLoc() const { return EndLoc; }
677 /// getLocRange - Get the range between the first and last token of this
679 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
681 ARMCC::CondCodes getCondCode() const {
682 assert(Kind == k_CondCode && "Invalid access!");
686 unsigned getCoproc() const {
687 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
691 StringRef getToken() const {
692 assert(Kind == k_Token && "Invalid access!");
693 return StringRef(Tok.Data, Tok.Length);
696 unsigned getReg() const {
697 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
701 const SmallVectorImpl<unsigned> &getRegList() const {
702 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
703 Kind == k_SPRRegisterList) && "Invalid access!");
707 const MCExpr *getImm() const {
708 assert(isImm() && "Invalid access!");
712 unsigned getVectorIndex() const {
713 assert(Kind == k_VectorIndex && "Invalid access!");
714 return VectorIndex.Val;
717 ARM_MB::MemBOpt getMemBarrierOpt() const {
718 assert(Kind == k_MemBarrierOpt && "Invalid access!");
722 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
723 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
727 ARM_PROC::IFlags getProcIFlags() const {
728 assert(Kind == k_ProcIFlags && "Invalid access!");
732 unsigned getMSRMask() const {
733 assert(Kind == k_MSRMask && "Invalid access!");
737 bool isCoprocNum() const { return Kind == k_CoprocNum; }
738 bool isCoprocReg() const { return Kind == k_CoprocReg; }
739 bool isCoprocOption() const { return Kind == k_CoprocOption; }
740 bool isCondCode() const { return Kind == k_CondCode; }
741 bool isCCOut() const { return Kind == k_CCOut; }
742 bool isITMask() const { return Kind == k_ITCondMask; }
743 bool isITCondCode() const { return Kind == k_CondCode; }
744 bool isImm() const { return Kind == k_Immediate; }
745 // checks whether this operand is an unsigned offset which fits is a field
746 // of specified width and scaled by a specific number of bits
747 template<unsigned width, unsigned scale>
748 bool isUnsignedOffset() const {
749 if (!isImm()) return false;
750 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
751 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
752 int64_t Val = CE->getValue();
753 int64_t Align = 1LL << scale;
754 int64_t Max = Align * ((1LL << width) - 1);
755 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
759 // checks whether this operand is an signed offset which fits is a field
760 // of specified width and scaled by a specific number of bits
761 template<unsigned width, unsigned scale>
762 bool isSignedOffset() const {
763 if (!isImm()) return false;
764 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
765 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
766 int64_t Val = CE->getValue();
767 int64_t Align = 1LL << scale;
768 int64_t Max = Align * ((1LL << (width-1)) - 1);
769 int64_t Min = -Align * (1LL << (width-1));
770 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
775 // checks whether this operand is a memory operand computed as an offset
776 // applied to PC. the offset may have 8 bits of magnitude and is represented
777 // with two bits of shift. textually it may be either [pc, #imm], #imm or
778 // relocable expression...
779 bool isThumbMemPC() const {
782 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
783 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
784 if (!CE) return false;
785 Val = CE->getValue();
788 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
789 if(Memory.BaseRegNum != ARM::PC) return false;
790 Val = Memory.OffsetImm->getValue();
793 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
795 bool isFPImm() const {
796 if (!isImm()) return false;
797 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
798 if (!CE) return false;
799 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
802 bool isFBits16() const {
803 if (!isImm()) return false;
804 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
805 if (!CE) return false;
806 int64_t Value = CE->getValue();
807 return Value >= 0 && Value <= 16;
809 bool isFBits32() const {
810 if (!isImm()) return false;
811 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
812 if (!CE) return false;
813 int64_t Value = CE->getValue();
814 return Value >= 1 && Value <= 32;
816 bool isImm8s4() const {
817 if (!isImm()) return false;
818 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
819 if (!CE) return false;
820 int64_t Value = CE->getValue();
821 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
823 bool isImm0_1020s4() const {
824 if (!isImm()) return false;
825 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
826 if (!CE) return false;
827 int64_t Value = CE->getValue();
828 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
830 bool isImm0_508s4() const {
831 if (!isImm()) return false;
832 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
833 if (!CE) return false;
834 int64_t Value = CE->getValue();
835 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
837 bool isImm0_508s4Neg() const {
838 if (!isImm()) return false;
839 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
840 if (!CE) return false;
841 int64_t Value = -CE->getValue();
842 // explicitly exclude zero. we want that to use the normal 0_508 version.
843 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
845 bool isImm0_239() const {
846 if (!isImm()) return false;
847 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
848 if (!CE) return false;
849 int64_t Value = CE->getValue();
850 return Value >= 0 && Value < 240;
852 bool isImm0_255() const {
853 if (!isImm()) return false;
854 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
855 if (!CE) return false;
856 int64_t Value = CE->getValue();
857 return Value >= 0 && Value < 256;
859 bool isImm0_4095() const {
860 if (!isImm()) return false;
861 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
862 if (!CE) return false;
863 int64_t Value = CE->getValue();
864 return Value >= 0 && Value < 4096;
866 bool isImm0_4095Neg() const {
867 if (!isImm()) return false;
868 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
869 if (!CE) return false;
870 int64_t Value = -CE->getValue();
871 return Value > 0 && Value < 4096;
873 bool isImm0_1() const {
874 if (!isImm()) return false;
875 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
876 if (!CE) return false;
877 int64_t Value = CE->getValue();
878 return Value >= 0 && Value < 2;
880 bool isImm0_3() const {
881 if (!isImm()) return false;
882 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
883 if (!CE) return false;
884 int64_t Value = CE->getValue();
885 return Value >= 0 && Value < 4;
887 bool isImm0_7() const {
888 if (!isImm()) return false;
889 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
890 if (!CE) return false;
891 int64_t Value = CE->getValue();
892 return Value >= 0 && Value < 8;
894 bool isImm0_15() const {
895 if (!isImm()) return false;
896 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
897 if (!CE) return false;
898 int64_t Value = CE->getValue();
899 return Value >= 0 && Value < 16;
901 bool isImm0_31() const {
902 if (!isImm()) return false;
903 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
904 if (!CE) return false;
905 int64_t Value = CE->getValue();
906 return Value >= 0 && Value < 32;
908 bool isImm0_63() const {
909 if (!isImm()) return false;
910 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
911 if (!CE) return false;
912 int64_t Value = CE->getValue();
913 return Value >= 0 && Value < 64;
915 bool isImm8() const {
916 if (!isImm()) return false;
917 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
918 if (!CE) return false;
919 int64_t Value = CE->getValue();
922 bool isImm16() const {
923 if (!isImm()) return false;
924 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
925 if (!CE) return false;
926 int64_t Value = CE->getValue();
929 bool isImm32() const {
930 if (!isImm()) return false;
931 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
932 if (!CE) return false;
933 int64_t Value = CE->getValue();
936 bool isShrImm8() const {
937 if (!isImm()) return false;
938 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
939 if (!CE) return false;
940 int64_t Value = CE->getValue();
941 return Value > 0 && Value <= 8;
943 bool isShrImm16() const {
944 if (!isImm()) return false;
945 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
946 if (!CE) return false;
947 int64_t Value = CE->getValue();
948 return Value > 0 && Value <= 16;
950 bool isShrImm32() const {
951 if (!isImm()) return false;
952 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
953 if (!CE) return false;
954 int64_t Value = CE->getValue();
955 return Value > 0 && Value <= 32;
957 bool isShrImm64() const {
958 if (!isImm()) return false;
959 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
960 if (!CE) return false;
961 int64_t Value = CE->getValue();
962 return Value > 0 && Value <= 64;
964 bool isImm1_7() const {
965 if (!isImm()) return false;
966 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
967 if (!CE) return false;
968 int64_t Value = CE->getValue();
969 return Value > 0 && Value < 8;
971 bool isImm1_15() const {
972 if (!isImm()) return false;
973 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
974 if (!CE) return false;
975 int64_t Value = CE->getValue();
976 return Value > 0 && Value < 16;
978 bool isImm1_31() const {
979 if (!isImm()) return false;
980 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
981 if (!CE) return false;
982 int64_t Value = CE->getValue();
983 return Value > 0 && Value < 32;
985 bool isImm1_16() const {
986 if (!isImm()) return false;
987 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
988 if (!CE) return false;
989 int64_t Value = CE->getValue();
990 return Value > 0 && Value < 17;
992 bool isImm1_32() const {
993 if (!isImm()) return false;
994 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
995 if (!CE) return false;
996 int64_t Value = CE->getValue();
997 return Value > 0 && Value < 33;
999 bool isImm0_32() const {
1000 if (!isImm()) return false;
1001 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1002 if (!CE) return false;
1003 int64_t Value = CE->getValue();
1004 return Value >= 0 && Value < 33;
1006 bool isImm0_65535() const {
1007 if (!isImm()) return false;
1008 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1009 if (!CE) return false;
1010 int64_t Value = CE->getValue();
1011 return Value >= 0 && Value < 65536;
1013 bool isImm256_65535Expr() const {
1014 if (!isImm()) return false;
1015 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1016 // If it's not a constant expression, it'll generate a fixup and be
1018 if (!CE) return true;
1019 int64_t Value = CE->getValue();
1020 return Value >= 256 && Value < 65536;
1022 bool isImm0_65535Expr() const {
1023 if (!isImm()) return false;
1024 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1025 // If it's not a constant expression, it'll generate a fixup and be
1027 if (!CE) return true;
1028 int64_t Value = CE->getValue();
1029 return Value >= 0 && Value < 65536;
1031 bool isImm24bit() const {
1032 if (!isImm()) return false;
1033 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1034 if (!CE) return false;
1035 int64_t Value = CE->getValue();
1036 return Value >= 0 && Value <= 0xffffff;
1038 bool isImmThumbSR() const {
1039 if (!isImm()) return false;
1040 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1041 if (!CE) return false;
1042 int64_t Value = CE->getValue();
1043 return Value > 0 && Value < 33;
1045 bool isPKHLSLImm() const {
1046 if (!isImm()) return false;
1047 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1048 if (!CE) return false;
1049 int64_t Value = CE->getValue();
1050 return Value >= 0 && Value < 32;
1052 bool isPKHASRImm() const {
1053 if (!isImm()) return false;
1054 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1055 if (!CE) return false;
1056 int64_t Value = CE->getValue();
1057 return Value > 0 && Value <= 32;
1059 bool isAdrLabel() const {
1060 // If we have an immediate that's not a constant, treat it as a label
1061 // reference needing a fixup. If it is a constant, but it can't fit
1062 // into shift immediate encoding, we reject it.
1063 if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
1064 else return (isARMSOImm() || isARMSOImmNeg());
1066 bool isARMSOImm() const {
1067 if (!isImm()) return false;
1068 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1069 if (!CE) return false;
1070 int64_t Value = CE->getValue();
1071 return ARM_AM::getSOImmVal(Value) != -1;
1073 bool isARMSOImmNot() const {
1074 if (!isImm()) return false;
1075 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1076 if (!CE) return false;
1077 int64_t Value = CE->getValue();
1078 return ARM_AM::getSOImmVal(~Value) != -1;
1080 bool isARMSOImmNeg() const {
1081 if (!isImm()) return false;
1082 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1083 if (!CE) return false;
1084 int64_t Value = CE->getValue();
1085 // Only use this when not representable as a plain so_imm.
1086 return ARM_AM::getSOImmVal(Value) == -1 &&
1087 ARM_AM::getSOImmVal(-Value) != -1;
1089 bool isT2SOImm() const {
1090 if (!isImm()) return false;
1091 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1092 if (!CE) return false;
1093 int64_t Value = CE->getValue();
1094 return ARM_AM::getT2SOImmVal(Value) != -1;
1096 bool isT2SOImmNot() const {
1097 if (!isImm()) return false;
1098 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1099 if (!CE) return false;
1100 int64_t Value = CE->getValue();
1101 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1102 ARM_AM::getT2SOImmVal(~Value) != -1;
1104 bool isT2SOImmNeg() const {
1105 if (!isImm()) return false;
1106 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1107 if (!CE) return false;
1108 int64_t Value = CE->getValue();
1109 // Only use this when not representable as a plain so_imm.
1110 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1111 ARM_AM::getT2SOImmVal(-Value) != -1;
1113 bool isSetEndImm() const {
1114 if (!isImm()) return false;
1115 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1116 if (!CE) return false;
1117 int64_t Value = CE->getValue();
1118 return Value == 1 || Value == 0;
1120 bool isReg() const { return Kind == k_Register; }
1121 bool isRegList() const { return Kind == k_RegisterList; }
1122 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1123 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1124 bool isToken() const { return Kind == k_Token; }
1125 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1126 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1127 bool isMem() const { return Kind == k_Memory; }
1128 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1129 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
1130 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
1131 bool isRotImm() const { return Kind == k_RotateImmediate; }
1132 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1133 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
1134 bool isPostIdxReg() const {
1135 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
1137 bool isMemNoOffset(bool alignOK = false) const {
1140 // No offset of any kind.
1141 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
1142 (alignOK || Memory.Alignment == 0);
1144 bool isMemPCRelImm12() const {
1145 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1147 // Base register must be PC.
1148 if (Memory.BaseRegNum != ARM::PC)
1150 // Immediate offset in range [-4095, 4095].
1151 if (!Memory.OffsetImm) return true;
1152 int64_t Val = Memory.OffsetImm->getValue();
1153 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1155 bool isAlignedMemory() const {
1156 return isMemNoOffset(true);
1158 bool isAddrMode2() const {
1159 if (!isMem() || Memory.Alignment != 0) return false;
1160 // Check for register offset.
1161 if (Memory.OffsetRegNum) return true;
1162 // Immediate offset in range [-4095, 4095].
1163 if (!Memory.OffsetImm) return true;
1164 int64_t Val = Memory.OffsetImm->getValue();
1165 return Val > -4096 && Val < 4096;
1167 bool isAM2OffsetImm() const {
1168 if (!isImm()) return false;
1169 // Immediate offset in range [-4095, 4095].
1170 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1171 if (!CE) return false;
1172 int64_t Val = CE->getValue();
1173 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1175 bool isAddrMode3() const {
1176 // If we have an immediate that's not a constant, treat it as a label
1177 // reference needing a fixup. If it is a constant, it's something else
1178 // and we reject it.
1179 if (isImm() && !isa<MCConstantExpr>(getImm()))
1181 if (!isMem() || Memory.Alignment != 0) return false;
1182 // No shifts are legal for AM3.
1183 if (Memory.ShiftType != ARM_AM::no_shift) return false;
1184 // Check for register offset.
1185 if (Memory.OffsetRegNum) return true;
1186 // Immediate offset in range [-255, 255].
1187 if (!Memory.OffsetImm) return true;
1188 int64_t Val = Memory.OffsetImm->getValue();
1189 // The #-0 offset is encoded as INT32_MIN, and we have to check
1191 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1193 bool isAM3Offset() const {
1194 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1196 if (Kind == k_PostIndexRegister)
1197 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1198 // Immediate offset in range [-255, 255].
1199 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1200 if (!CE) return false;
1201 int64_t Val = CE->getValue();
1202 // Special case, #-0 is INT32_MIN.
1203 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1205 bool isAddrMode5() const {
1206 // If we have an immediate that's not a constant, treat it as a label
1207 // reference needing a fixup. If it is a constant, it's something else
1208 // and we reject it.
1209 if (isImm() && !isa<MCConstantExpr>(getImm()))
1211 if (!isMem() || Memory.Alignment != 0) return false;
1212 // Check for register offset.
1213 if (Memory.OffsetRegNum) return false;
1214 // Immediate offset in range [-1020, 1020] and a multiple of 4.
1215 if (!Memory.OffsetImm) return true;
1216 int64_t Val = Memory.OffsetImm->getValue();
1217 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1220 bool isMemTBB() const {
1221 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1222 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1226 bool isMemTBH() const {
1227 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1228 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1229 Memory.Alignment != 0 )
1233 bool isMemRegOffset() const {
1234 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1238 bool isT2MemRegOffset() const {
1239 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1240 Memory.Alignment != 0)
1242 // Only lsl #{0, 1, 2, 3} allowed.
1243 if (Memory.ShiftType == ARM_AM::no_shift)
1245 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1249 bool isMemThumbRR() const {
1250 // Thumb reg+reg addressing is simple. Just two registers, a base and
1251 // an offset. No shifts, negations or any other complicating factors.
1252 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1253 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1255 return isARMLowRegister(Memory.BaseRegNum) &&
1256 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1258 bool isMemThumbRIs4() const {
1259 if (!isMem() || Memory.OffsetRegNum != 0 ||
1260 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1262 // Immediate offset, multiple of 4 in range [0, 124].
1263 if (!Memory.OffsetImm) return true;
1264 int64_t Val = Memory.OffsetImm->getValue();
1265 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1267 bool isMemThumbRIs2() const {
1268 if (!isMem() || Memory.OffsetRegNum != 0 ||
1269 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1271 // Immediate offset, multiple of 4 in range [0, 62].
1272 if (!Memory.OffsetImm) return true;
1273 int64_t Val = Memory.OffsetImm->getValue();
1274 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1276 bool isMemThumbRIs1() const {
1277 if (!isMem() || Memory.OffsetRegNum != 0 ||
1278 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1280 // Immediate offset in range [0, 31].
1281 if (!Memory.OffsetImm) return true;
1282 int64_t Val = Memory.OffsetImm->getValue();
1283 return Val >= 0 && Val <= 31;
1285 bool isMemThumbSPI() const {
1286 if (!isMem() || Memory.OffsetRegNum != 0 ||
1287 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1289 // Immediate offset, multiple of 4 in range [0, 1020].
1290 if (!Memory.OffsetImm) return true;
1291 int64_t Val = Memory.OffsetImm->getValue();
1292 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1294 bool isMemImm8s4Offset() const {
1295 // If we have an immediate that's not a constant, treat it as a label
1296 // reference needing a fixup. If it is a constant, it's something else
1297 // and we reject it.
1298 if (isImm() && !isa<MCConstantExpr>(getImm()))
1300 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1302 // Immediate offset a multiple of 4 in range [-1020, 1020].
1303 if (!Memory.OffsetImm) return true;
1304 int64_t Val = Memory.OffsetImm->getValue();
1305 // Special case, #-0 is INT32_MIN.
1306 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1308 bool isMemImm0_1020s4Offset() const {
1309 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1311 // Immediate offset a multiple of 4 in range [0, 1020].
1312 if (!Memory.OffsetImm) return true;
1313 int64_t Val = Memory.OffsetImm->getValue();
1314 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1316 bool isMemImm8Offset() const {
1317 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1319 // Base reg of PC isn't allowed for these encodings.
1320 if (Memory.BaseRegNum == ARM::PC) return false;
1321 // Immediate offset in range [-255, 255].
1322 if (!Memory.OffsetImm) return true;
1323 int64_t Val = Memory.OffsetImm->getValue();
1324 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1326 bool isMemPosImm8Offset() const {
1327 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1329 // Immediate offset in range [0, 255].
1330 if (!Memory.OffsetImm) return true;
1331 int64_t Val = Memory.OffsetImm->getValue();
1332 return Val >= 0 && Val < 256;
1334 bool isMemNegImm8Offset() const {
1335 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1337 // Base reg of PC isn't allowed for these encodings.
1338 if (Memory.BaseRegNum == ARM::PC) return false;
1339 // Immediate offset in range [-255, -1].
1340 if (!Memory.OffsetImm) return false;
1341 int64_t Val = Memory.OffsetImm->getValue();
1342 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1344 bool isMemUImm12Offset() const {
1345 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1347 // Immediate offset in range [0, 4095].
1348 if (!Memory.OffsetImm) return true;
1349 int64_t Val = Memory.OffsetImm->getValue();
1350 return (Val >= 0 && Val < 4096);
1352 bool isMemImm12Offset() const {
1353 // If we have an immediate that's not a constant, treat it as a label
1354 // reference needing a fixup. If it is a constant, it's something else
1355 // and we reject it.
1356 if (isImm() && !isa<MCConstantExpr>(getImm()))
1359 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1361 // Immediate offset in range [-4095, 4095].
1362 if (!Memory.OffsetImm) return true;
1363 int64_t Val = Memory.OffsetImm->getValue();
1364 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1366 bool isPostIdxImm8() const {
1367 if (!isImm()) return false;
1368 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1369 if (!CE) return false;
1370 int64_t Val = CE->getValue();
1371 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1373 bool isPostIdxImm8s4() const {
1374 if (!isImm()) return false;
1375 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1376 if (!CE) return false;
1377 int64_t Val = CE->getValue();
1378 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1382 bool isMSRMask() const { return Kind == k_MSRMask; }
1383 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1386 bool isSingleSpacedVectorList() const {
1387 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1389 bool isDoubleSpacedVectorList() const {
1390 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1392 bool isVecListOneD() const {
1393 if (!isSingleSpacedVectorList()) return false;
1394 return VectorList.Count == 1;
1397 bool isVecListDPair() const {
1398 if (!isSingleSpacedVectorList()) return false;
1399 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1400 .contains(VectorList.RegNum));
1403 bool isVecListThreeD() const {
1404 if (!isSingleSpacedVectorList()) return false;
1405 return VectorList.Count == 3;
1408 bool isVecListFourD() const {
1409 if (!isSingleSpacedVectorList()) return false;
1410 return VectorList.Count == 4;
1413 bool isVecListDPairSpaced() const {
1414 if (isSingleSpacedVectorList()) return false;
1415 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1416 .contains(VectorList.RegNum));
1419 bool isVecListThreeQ() const {
1420 if (!isDoubleSpacedVectorList()) return false;
1421 return VectorList.Count == 3;
1424 bool isVecListFourQ() const {
1425 if (!isDoubleSpacedVectorList()) return false;
1426 return VectorList.Count == 4;
1429 bool isSingleSpacedVectorAllLanes() const {
1430 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1432 bool isDoubleSpacedVectorAllLanes() const {
1433 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1435 bool isVecListOneDAllLanes() const {
1436 if (!isSingleSpacedVectorAllLanes()) return false;
1437 return VectorList.Count == 1;
1440 bool isVecListDPairAllLanes() const {
1441 if (!isSingleSpacedVectorAllLanes()) return false;
1442 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1443 .contains(VectorList.RegNum));
1446 bool isVecListDPairSpacedAllLanes() const {
1447 if (!isDoubleSpacedVectorAllLanes()) return false;
1448 return VectorList.Count == 2;
1451 bool isVecListThreeDAllLanes() const {
1452 if (!isSingleSpacedVectorAllLanes()) return false;
1453 return VectorList.Count == 3;
1456 bool isVecListThreeQAllLanes() const {
1457 if (!isDoubleSpacedVectorAllLanes()) return false;
1458 return VectorList.Count == 3;
1461 bool isVecListFourDAllLanes() const {
1462 if (!isSingleSpacedVectorAllLanes()) return false;
1463 return VectorList.Count == 4;
1466 bool isVecListFourQAllLanes() const {
1467 if (!isDoubleSpacedVectorAllLanes()) return false;
1468 return VectorList.Count == 4;
1471 bool isSingleSpacedVectorIndexed() const {
1472 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1474 bool isDoubleSpacedVectorIndexed() const {
1475 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1477 bool isVecListOneDByteIndexed() const {
1478 if (!isSingleSpacedVectorIndexed()) return false;
1479 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1482 bool isVecListOneDHWordIndexed() const {
1483 if (!isSingleSpacedVectorIndexed()) return false;
1484 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1487 bool isVecListOneDWordIndexed() const {
1488 if (!isSingleSpacedVectorIndexed()) return false;
1489 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1492 bool isVecListTwoDByteIndexed() const {
1493 if (!isSingleSpacedVectorIndexed()) return false;
1494 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1497 bool isVecListTwoDHWordIndexed() const {
1498 if (!isSingleSpacedVectorIndexed()) return false;
1499 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1502 bool isVecListTwoQWordIndexed() const {
1503 if (!isDoubleSpacedVectorIndexed()) return false;
1504 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1507 bool isVecListTwoQHWordIndexed() const {
1508 if (!isDoubleSpacedVectorIndexed()) return false;
1509 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1512 bool isVecListTwoDWordIndexed() const {
1513 if (!isSingleSpacedVectorIndexed()) return false;
1514 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1517 bool isVecListThreeDByteIndexed() const {
1518 if (!isSingleSpacedVectorIndexed()) return false;
1519 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1522 bool isVecListThreeDHWordIndexed() const {
1523 if (!isSingleSpacedVectorIndexed()) return false;
1524 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1527 bool isVecListThreeQWordIndexed() const {
1528 if (!isDoubleSpacedVectorIndexed()) return false;
1529 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1532 bool isVecListThreeQHWordIndexed() const {
1533 if (!isDoubleSpacedVectorIndexed()) return false;
1534 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1537 bool isVecListThreeDWordIndexed() const {
1538 if (!isSingleSpacedVectorIndexed()) return false;
1539 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1542 bool isVecListFourDByteIndexed() const {
1543 if (!isSingleSpacedVectorIndexed()) return false;
1544 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1547 bool isVecListFourDHWordIndexed() const {
1548 if (!isSingleSpacedVectorIndexed()) return false;
1549 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1552 bool isVecListFourQWordIndexed() const {
1553 if (!isDoubleSpacedVectorIndexed()) return false;
1554 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1557 bool isVecListFourQHWordIndexed() const {
1558 if (!isDoubleSpacedVectorIndexed()) return false;
1559 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1562 bool isVecListFourDWordIndexed() const {
1563 if (!isSingleSpacedVectorIndexed()) return false;
1564 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1567 bool isVectorIndex8() const {
1568 if (Kind != k_VectorIndex) return false;
1569 return VectorIndex.Val < 8;
1571 bool isVectorIndex16() const {
1572 if (Kind != k_VectorIndex) return false;
1573 return VectorIndex.Val < 4;
1575 bool isVectorIndex32() const {
1576 if (Kind != k_VectorIndex) return false;
1577 return VectorIndex.Val < 2;
1580 bool isNEONi8splat() const {
1581 if (!isImm()) return false;
1582 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1583 // Must be a constant.
1584 if (!CE) return false;
1585 int64_t Value = CE->getValue();
1586 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1588 return Value >= 0 && Value < 256;
1591 bool isNEONi16splat() const {
1592 if (!isImm()) return false;
1593 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1594 // Must be a constant.
1595 if (!CE) return false;
1596 int64_t Value = CE->getValue();
1597 // i16 value in the range [0,255] or [0x0100, 0xff00]
1598 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1601 bool isNEONi32splat() const {
1602 if (!isImm()) return false;
1603 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1604 // Must be a constant.
1605 if (!CE) return false;
1606 int64_t Value = CE->getValue();
1607 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1608 return (Value >= 0 && Value < 256) ||
1609 (Value >= 0x0100 && Value <= 0xff00) ||
1610 (Value >= 0x010000 && Value <= 0xff0000) ||
1611 (Value >= 0x01000000 && Value <= 0xff000000);
1614 bool isNEONi32vmov() const {
1615 if (!isImm()) return false;
1616 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1617 // Must be a constant.
1618 if (!CE) return false;
1619 int64_t Value = CE->getValue();
1620 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1621 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1622 return (Value >= 0 && Value < 256) ||
1623 (Value >= 0x0100 && Value <= 0xff00) ||
1624 (Value >= 0x010000 && Value <= 0xff0000) ||
1625 (Value >= 0x01000000 && Value <= 0xff000000) ||
1626 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1627 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1629 bool isNEONi32vmovNeg() const {
1630 if (!isImm()) return false;
1631 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1632 // Must be a constant.
1633 if (!CE) return false;
1634 int64_t Value = ~CE->getValue();
1635 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1636 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1637 return (Value >= 0 && Value < 256) ||
1638 (Value >= 0x0100 && Value <= 0xff00) ||
1639 (Value >= 0x010000 && Value <= 0xff0000) ||
1640 (Value >= 0x01000000 && Value <= 0xff000000) ||
1641 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1642 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1645 bool isNEONi64splat() const {
1646 if (!isImm()) return false;
1647 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1648 // Must be a constant.
1649 if (!CE) return false;
1650 uint64_t Value = CE->getValue();
1651 // i64 value with each byte being either 0 or 0xff.
1652 for (unsigned i = 0; i < 8; ++i)
1653 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1657 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1658 // Add as immediates when possible. Null MCExpr = 0.
1660 Inst.addOperand(MCOperand::CreateImm(0));
1661 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1662 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1664 Inst.addOperand(MCOperand::CreateExpr(Expr));
1667 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1668 assert(N == 2 && "Invalid number of operands!");
1669 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1670 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1671 Inst.addOperand(MCOperand::CreateReg(RegNum));
1674 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1675 assert(N == 1 && "Invalid number of operands!");
1676 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1679 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1680 assert(N == 1 && "Invalid number of operands!");
1681 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1684 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1685 assert(N == 1 && "Invalid number of operands!");
1686 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1689 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1690 assert(N == 1 && "Invalid number of operands!");
1691 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1694 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1695 assert(N == 1 && "Invalid number of operands!");
1696 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1699 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1700 assert(N == 1 && "Invalid number of operands!");
1701 Inst.addOperand(MCOperand::CreateReg(getReg()));
1704 void addRegOperands(MCInst &Inst, unsigned N) const {
1705 assert(N == 1 && "Invalid number of operands!");
1706 Inst.addOperand(MCOperand::CreateReg(getReg()));
1709 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1710 assert(N == 3 && "Invalid number of operands!");
1711 assert(isRegShiftedReg() &&
1712 "addRegShiftedRegOperands() on non-RegShiftedReg!");
1713 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1714 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1715 Inst.addOperand(MCOperand::CreateImm(
1716 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1719 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1720 assert(N == 2 && "Invalid number of operands!");
1721 assert(isRegShiftedImm() &&
1722 "addRegShiftedImmOperands() on non-RegShiftedImm!");
1723 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1724 // Shift of #32 is encoded as 0 where permitted
1725 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1726 Inst.addOperand(MCOperand::CreateImm(
1727 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1730 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1731 assert(N == 1 && "Invalid number of operands!");
1732 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1736 void addRegListOperands(MCInst &Inst, unsigned N) const {
1737 assert(N == 1 && "Invalid number of operands!");
1738 const SmallVectorImpl<unsigned> &RegList = getRegList();
1739 for (SmallVectorImpl<unsigned>::const_iterator
1740 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1741 Inst.addOperand(MCOperand::CreateReg(*I));
1744 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1745 addRegListOperands(Inst, N);
1748 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1749 addRegListOperands(Inst, N);
1752 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1753 assert(N == 1 && "Invalid number of operands!");
1754 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1755 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1758 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1759 assert(N == 1 && "Invalid number of operands!");
1760 // Munge the lsb/width into a bitfield mask.
1761 unsigned lsb = Bitfield.LSB;
1762 unsigned width = Bitfield.Width;
1763 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1764 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1765 (32 - (lsb + width)));
1766 Inst.addOperand(MCOperand::CreateImm(Mask));
1769 void addImmOperands(MCInst &Inst, unsigned N) const {
1770 assert(N == 1 && "Invalid number of operands!");
1771 addExpr(Inst, getImm());
1774 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1775 assert(N == 1 && "Invalid number of operands!");
1776 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1777 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1780 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1781 assert(N == 1 && "Invalid number of operands!");
1782 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1783 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1786 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1787 assert(N == 1 && "Invalid number of operands!");
1788 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1789 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1790 Inst.addOperand(MCOperand::CreateImm(Val));
1793 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1794 assert(N == 1 && "Invalid number of operands!");
1795 // FIXME: We really want to scale the value here, but the LDRD/STRD
1796 // instruction don't encode operands that way yet.
1797 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1798 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1801 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1802 assert(N == 1 && "Invalid number of operands!");
1803 // The immediate is scaled by four in the encoding and is stored
1804 // in the MCInst as such. Lop off the low two bits here.
1805 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1806 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1809 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1810 assert(N == 1 && "Invalid number of operands!");
1811 // The immediate is scaled by four in the encoding and is stored
1812 // in the MCInst as such. Lop off the low two bits here.
1813 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1814 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1817 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1818 assert(N == 1 && "Invalid number of operands!");
1819 // The immediate is scaled by four in the encoding and is stored
1820 // in the MCInst as such. Lop off the low two bits here.
1821 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1822 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1825 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1826 assert(N == 1 && "Invalid number of operands!");
1827 // The constant encodes as the immediate-1, and we store in the instruction
1828 // the bits as encoded, so subtract off one here.
1829 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1830 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1833 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1834 assert(N == 1 && "Invalid number of operands!");
1835 // The constant encodes as the immediate-1, and we store in the instruction
1836 // the bits as encoded, so subtract off one here.
1837 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1838 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1841 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1842 assert(N == 1 && "Invalid number of operands!");
1843 // The constant encodes as the immediate, except for 32, which encodes as
1845 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1846 unsigned Imm = CE->getValue();
1847 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1850 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1851 assert(N == 1 && "Invalid number of operands!");
1852 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1853 // the instruction as well.
1854 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1855 int Val = CE->getValue();
1856 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1859 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1860 assert(N == 1 && "Invalid number of operands!");
1861 // The operand is actually a t2_so_imm, but we have its bitwise
1862 // negation in the assembly source, so twiddle it here.
1863 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1864 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1867 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1868 assert(N == 1 && "Invalid number of operands!");
1869 // The operand is actually a t2_so_imm, but we have its
1870 // negation in the assembly source, so twiddle it here.
1871 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1872 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1875 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1876 assert(N == 1 && "Invalid number of operands!");
1877 // The operand is actually an imm0_4095, but we have its
1878 // negation in the assembly source, so twiddle it here.
1879 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1880 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1883 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1884 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1885 Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
1889 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1890 assert(SR && "Unknown value type!");
1891 Inst.addOperand(MCOperand::CreateExpr(SR));
1894 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
1895 assert(N == 1 && "Invalid number of operands!");
1897 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1899 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1903 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1904 assert(SR && "Unknown value type!");
1905 Inst.addOperand(MCOperand::CreateExpr(SR));
1909 assert(isMem() && "Unknown value type!");
1910 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
1911 Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
1914 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1915 assert(N == 1 && "Invalid number of operands!");
1916 // The operand is actually a so_imm, but we have its bitwise
1917 // negation in the assembly source, so twiddle it here.
1918 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1919 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1922 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1923 assert(N == 1 && "Invalid number of operands!");
1924 // The operand is actually a so_imm, but we have its
1925 // negation in the assembly source, so twiddle it here.
1926 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1927 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1930 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1931 assert(N == 1 && "Invalid number of operands!");
1932 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1935 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
1936 assert(N == 1 && "Invalid number of operands!");
1937 Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
1940 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1941 assert(N == 1 && "Invalid number of operands!");
1942 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1945 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1946 assert(N == 1 && "Invalid number of operands!");
1947 int32_t Imm = Memory.OffsetImm->getValue();
1948 Inst.addOperand(MCOperand::CreateImm(Imm));
1951 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1952 assert(N == 1 && "Invalid number of operands!");
1953 assert(isImm() && "Not an immediate!");
1955 // If we have an immediate that's not a constant, treat it as a label
1956 // reference needing a fixup.
1957 if (!isa<MCConstantExpr>(getImm())) {
1958 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1962 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1963 int Val = CE->getValue();
1964 Inst.addOperand(MCOperand::CreateImm(Val));
1967 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1968 assert(N == 2 && "Invalid number of operands!");
1969 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1970 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1973 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1974 assert(N == 3 && "Invalid number of operands!");
1975 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1976 if (!Memory.OffsetRegNum) {
1977 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1978 // Special case for #-0
1979 if (Val == INT32_MIN) Val = 0;
1980 if (Val < 0) Val = -Val;
1981 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1983 // For register offset, we encode the shift type and negation flag
1985 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1986 Memory.ShiftImm, Memory.ShiftType);
1988 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1989 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1990 Inst.addOperand(MCOperand::CreateImm(Val));
1993 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1994 assert(N == 2 && "Invalid number of operands!");
1995 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1996 assert(CE && "non-constant AM2OffsetImm operand!");
1997 int32_t Val = CE->getValue();
1998 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1999 // Special case for #-0
2000 if (Val == INT32_MIN) Val = 0;
2001 if (Val < 0) Val = -Val;
2002 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2003 Inst.addOperand(MCOperand::CreateReg(0));
2004 Inst.addOperand(MCOperand::CreateImm(Val));
2007 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2008 assert(N == 3 && "Invalid number of operands!");
2009 // If we have an immediate that's not a constant, treat it as a label
2010 // reference needing a fixup. If it is a constant, it's something else
2011 // and we reject it.
2013 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2014 Inst.addOperand(MCOperand::CreateReg(0));
2015 Inst.addOperand(MCOperand::CreateImm(0));
2019 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2020 if (!Memory.OffsetRegNum) {
2021 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2022 // Special case for #-0
2023 if (Val == INT32_MIN) Val = 0;
2024 if (Val < 0) Val = -Val;
2025 Val = ARM_AM::getAM3Opc(AddSub, Val);
2027 // For register offset, we encode the shift type and negation flag
2029 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
2031 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2032 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2033 Inst.addOperand(MCOperand::CreateImm(Val));
2036 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
2037 assert(N == 2 && "Invalid number of operands!");
2038 if (Kind == k_PostIndexRegister) {
2040 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
2041 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2042 Inst.addOperand(MCOperand::CreateImm(Val));
2047 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
2048 int32_t Val = CE->getValue();
2049 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2050 // Special case for #-0
2051 if (Val == INT32_MIN) Val = 0;
2052 if (Val < 0) Val = -Val;
2053 Val = ARM_AM::getAM3Opc(AddSub, Val);
2054 Inst.addOperand(MCOperand::CreateReg(0));
2055 Inst.addOperand(MCOperand::CreateImm(Val));
2058 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2059 assert(N == 2 && "Invalid number of operands!");
2060 // If we have an immediate that's not a constant, treat it as a label
2061 // reference needing a fixup. If it is a constant, it's something else
2062 // and we reject it.
2064 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2065 Inst.addOperand(MCOperand::CreateImm(0));
2069 // The lower two bits are always zero and as such are not encoded.
2070 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2071 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2072 // Special case for #-0
2073 if (Val == INT32_MIN) Val = 0;
2074 if (Val < 0) Val = -Val;
2075 Val = ARM_AM::getAM5Opc(AddSub, Val);
2076 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2077 Inst.addOperand(MCOperand::CreateImm(Val));
2080 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2081 assert(N == 2 && "Invalid number of operands!");
2082 // If we have an immediate that's not a constant, treat it as a label
2083 // reference needing a fixup. If it is a constant, it's something else
2084 // and we reject it.
2086 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2087 Inst.addOperand(MCOperand::CreateImm(0));
2091 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2092 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2093 Inst.addOperand(MCOperand::CreateImm(Val));
2096 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2097 assert(N == 2 && "Invalid number of operands!");
2098 // The lower two bits are always zero and as such are not encoded.
2099 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2100 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2101 Inst.addOperand(MCOperand::CreateImm(Val));
2104 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2105 assert(N == 2 && "Invalid number of operands!");
2106 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2107 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2108 Inst.addOperand(MCOperand::CreateImm(Val));
2111 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2112 addMemImm8OffsetOperands(Inst, N);
2115 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2116 addMemImm8OffsetOperands(Inst, N);
2119 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2120 assert(N == 2 && "Invalid number of operands!");
2121 // If this is an immediate, it's a label reference.
2123 addExpr(Inst, getImm());
2124 Inst.addOperand(MCOperand::CreateImm(0));
2128 // Otherwise, it's a normal memory reg+offset.
2129 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2130 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2131 Inst.addOperand(MCOperand::CreateImm(Val));
2134 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2135 assert(N == 2 && "Invalid number of operands!");
2136 // If this is an immediate, it's a label reference.
2138 addExpr(Inst, getImm());
2139 Inst.addOperand(MCOperand::CreateImm(0));
2143 // Otherwise, it's a normal memory reg+offset.
2144 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2145 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2146 Inst.addOperand(MCOperand::CreateImm(Val));
2149 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2150 assert(N == 2 && "Invalid number of operands!");
2151 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2152 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2155 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2156 assert(N == 2 && "Invalid number of operands!");
2157 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2158 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2161 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2162 assert(N == 3 && "Invalid number of operands!");
2164 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2165 Memory.ShiftImm, Memory.ShiftType);
2166 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2167 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2168 Inst.addOperand(MCOperand::CreateImm(Val));
2171 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2172 assert(N == 3 && "Invalid number of operands!");
2173 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2174 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2175 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
2178 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2179 assert(N == 2 && "Invalid number of operands!");
2180 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2181 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2184 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2185 assert(N == 2 && "Invalid number of operands!");
2186 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2187 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2188 Inst.addOperand(MCOperand::CreateImm(Val));
2191 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2192 assert(N == 2 && "Invalid number of operands!");
2193 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2194 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2195 Inst.addOperand(MCOperand::CreateImm(Val));
2198 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2199 assert(N == 2 && "Invalid number of operands!");
2200 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2201 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2202 Inst.addOperand(MCOperand::CreateImm(Val));
2205 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2206 assert(N == 2 && "Invalid number of operands!");
2207 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2208 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2209 Inst.addOperand(MCOperand::CreateImm(Val));
2212 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2213 assert(N == 1 && "Invalid number of operands!");
2214 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2215 assert(CE && "non-constant post-idx-imm8 operand!");
2216 int Imm = CE->getValue();
2217 bool isAdd = Imm >= 0;
2218 if (Imm == INT32_MIN) Imm = 0;
2219 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2220 Inst.addOperand(MCOperand::CreateImm(Imm));
2223 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2224 assert(N == 1 && "Invalid number of operands!");
2225 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2226 assert(CE && "non-constant post-idx-imm8s4 operand!");
2227 int Imm = CE->getValue();
2228 bool isAdd = Imm >= 0;
2229 if (Imm == INT32_MIN) Imm = 0;
2230 // Immediate is scaled by 4.
2231 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2232 Inst.addOperand(MCOperand::CreateImm(Imm));
2235 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2236 assert(N == 2 && "Invalid number of operands!");
2237 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2238 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2241 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2242 assert(N == 2 && "Invalid number of operands!");
2243 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2244 // The sign, shift type, and shift amount are encoded in a single operand
2245 // using the AM2 encoding helpers.
2246 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2247 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2248 PostIdxReg.ShiftTy);
2249 Inst.addOperand(MCOperand::CreateImm(Imm));
2252 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2253 assert(N == 1 && "Invalid number of operands!");
2254 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2257 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2258 assert(N == 1 && "Invalid number of operands!");
2259 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2262 void addVecListOperands(MCInst &Inst, unsigned N) const {
2263 assert(N == 1 && "Invalid number of operands!");
2264 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2267 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2268 assert(N == 2 && "Invalid number of operands!");
2269 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2270 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2273 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2274 assert(N == 1 && "Invalid number of operands!");
2275 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2278 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2279 assert(N == 1 && "Invalid number of operands!");
2280 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2283 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2284 assert(N == 1 && "Invalid number of operands!");
2285 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2288 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2289 assert(N == 1 && "Invalid number of operands!");
2290 // The immediate encodes the type of constant as well as the value.
2291 // Mask in that this is an i8 splat.
2292 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2293 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2296 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2297 assert(N == 1 && "Invalid number of operands!");
2298 // The immediate encodes the type of constant as well as the value.
2299 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2300 unsigned Value = CE->getValue();
2302 Value = (Value >> 8) | 0xa00;
2305 Inst.addOperand(MCOperand::CreateImm(Value));
2308 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2309 assert(N == 1 && "Invalid number of operands!");
2310 // The immediate encodes the type of constant as well as the value.
2311 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2312 unsigned Value = CE->getValue();
2313 if (Value >= 256 && Value <= 0xff00)
2314 Value = (Value >> 8) | 0x200;
2315 else if (Value > 0xffff && Value <= 0xff0000)
2316 Value = (Value >> 16) | 0x400;
2317 else if (Value > 0xffffff)
2318 Value = (Value >> 24) | 0x600;
2319 Inst.addOperand(MCOperand::CreateImm(Value));
2322 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2323 assert(N == 1 && "Invalid number of operands!");
2324 // The immediate encodes the type of constant as well as the value.
2325 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2326 unsigned Value = CE->getValue();
2327 if (Value >= 256 && Value <= 0xffff)
2328 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2329 else if (Value > 0xffff && Value <= 0xffffff)
2330 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2331 else if (Value > 0xffffff)
2332 Value = (Value >> 24) | 0x600;
2333 Inst.addOperand(MCOperand::CreateImm(Value));
2336 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2337 assert(N == 1 && "Invalid number of operands!");
2338 // The immediate encodes the type of constant as well as the value.
2339 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2340 unsigned Value = ~CE->getValue();
2341 if (Value >= 256 && Value <= 0xffff)
2342 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2343 else if (Value > 0xffff && Value <= 0xffffff)
2344 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2345 else if (Value > 0xffffff)
2346 Value = (Value >> 24) | 0x600;
2347 Inst.addOperand(MCOperand::CreateImm(Value));
2350 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2351 assert(N == 1 && "Invalid number of operands!");
2352 // The immediate encodes the type of constant as well as the value.
2353 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2354 uint64_t Value = CE->getValue();
2356 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2357 Imm |= (Value & 1) << i;
2359 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2362 virtual void print(raw_ostream &OS) const;
2364 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2365 ARMOperand *Op = new ARMOperand(k_ITCondMask);
2366 Op->ITMask.Mask = Mask;
2372 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2373 ARMOperand *Op = new ARMOperand(k_CondCode);
2380 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2381 ARMOperand *Op = new ARMOperand(k_CoprocNum);
2382 Op->Cop.Val = CopVal;
2388 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2389 ARMOperand *Op = new ARMOperand(k_CoprocReg);
2390 Op->Cop.Val = CopVal;
2396 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2397 ARMOperand *Op = new ARMOperand(k_CoprocOption);
2404 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2405 ARMOperand *Op = new ARMOperand(k_CCOut);
2406 Op->Reg.RegNum = RegNum;
2412 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2413 ARMOperand *Op = new ARMOperand(k_Token);
2414 Op->Tok.Data = Str.data();
2415 Op->Tok.Length = Str.size();
2421 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2422 ARMOperand *Op = new ARMOperand(k_Register);
2423 Op->Reg.RegNum = RegNum;
2429 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2434 ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2435 Op->RegShiftedReg.ShiftTy = ShTy;
2436 Op->RegShiftedReg.SrcReg = SrcReg;
2437 Op->RegShiftedReg.ShiftReg = ShiftReg;
2438 Op->RegShiftedReg.ShiftImm = ShiftImm;
2444 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2448 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2449 Op->RegShiftedImm.ShiftTy = ShTy;
2450 Op->RegShiftedImm.SrcReg = SrcReg;
2451 Op->RegShiftedImm.ShiftImm = ShiftImm;
2457 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2459 ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2460 Op->ShifterImm.isASR = isASR;
2461 Op->ShifterImm.Imm = Imm;
2467 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2468 ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2469 Op->RotImm.Imm = Imm;
2475 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2477 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2478 Op->Bitfield.LSB = LSB;
2479 Op->Bitfield.Width = Width;
2486 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned> > &Regs,
2487 SMLoc StartLoc, SMLoc EndLoc) {
2488 assert (Regs.size() > 0 && "RegList contains no registers?");
2489 KindTy Kind = k_RegisterList;
2491 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2492 Kind = k_DPRRegisterList;
2493 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2494 contains(Regs.front().second))
2495 Kind = k_SPRRegisterList;
2497 // Sort based on the register encoding values.
2498 array_pod_sort(Regs.begin(), Regs.end());
2500 ARMOperand *Op = new ARMOperand(Kind);
2501 for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2502 I = Regs.begin(), E = Regs.end(); I != E; ++I)
2503 Op->Registers.push_back(I->second);
2504 Op->StartLoc = StartLoc;
2505 Op->EndLoc = EndLoc;
2509 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2510 bool isDoubleSpaced, SMLoc S, SMLoc E) {
2511 ARMOperand *Op = new ARMOperand(k_VectorList);
2512 Op->VectorList.RegNum = RegNum;
2513 Op->VectorList.Count = Count;
2514 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2520 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2521 bool isDoubleSpaced,
2523 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2524 Op->VectorList.RegNum = RegNum;
2525 Op->VectorList.Count = Count;
2526 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2532 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2534 bool isDoubleSpaced,
2536 ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2537 Op->VectorList.RegNum = RegNum;
2538 Op->VectorList.Count = Count;
2539 Op->VectorList.LaneIndex = Index;
2540 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2546 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2548 ARMOperand *Op = new ARMOperand(k_VectorIndex);
2549 Op->VectorIndex.Val = Idx;
2555 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2556 ARMOperand *Op = new ARMOperand(k_Immediate);
2563 static ARMOperand *CreateMem(unsigned BaseRegNum,
2564 const MCConstantExpr *OffsetImm,
2565 unsigned OffsetRegNum,
2566 ARM_AM::ShiftOpc ShiftType,
2571 ARMOperand *Op = new ARMOperand(k_Memory);
2572 Op->Memory.BaseRegNum = BaseRegNum;
2573 Op->Memory.OffsetImm = OffsetImm;
2574 Op->Memory.OffsetRegNum = OffsetRegNum;
2575 Op->Memory.ShiftType = ShiftType;
2576 Op->Memory.ShiftImm = ShiftImm;
2577 Op->Memory.Alignment = Alignment;
2578 Op->Memory.isNegative = isNegative;
2584 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2585 ARM_AM::ShiftOpc ShiftTy,
2588 ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2589 Op->PostIdxReg.RegNum = RegNum;
2590 Op->PostIdxReg.isAdd = isAdd;
2591 Op->PostIdxReg.ShiftTy = ShiftTy;
2592 Op->PostIdxReg.ShiftImm = ShiftImm;
2598 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2599 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2600 Op->MBOpt.Val = Opt;
2606 static ARMOperand *CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt,
2608 ARMOperand *Op = new ARMOperand(k_InstSyncBarrierOpt);
2609 Op->ISBOpt.Val = Opt;
2615 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2616 ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2617 Op->IFlags.Val = IFlags;
2623 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2624 ARMOperand *Op = new ARMOperand(k_MSRMask);
2625 Op->MMask.Val = MMask;
2632 } // end anonymous namespace.
2634 void ARMOperand::print(raw_ostream &OS) const {
2637 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2640 OS << "<ccout " << getReg() << ">";
2642 case k_ITCondMask: {
2643 static const char *const MaskStr[] = {
2644 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2645 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2647 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2648 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2652 OS << "<coprocessor number: " << getCoproc() << ">";
2655 OS << "<coprocessor register: " << getCoproc() << ">";
2657 case k_CoprocOption:
2658 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2661 OS << "<mask: " << getMSRMask() << ">";
2664 getImm()->print(OS);
2666 case k_MemBarrierOpt:
2667 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
2669 case k_InstSyncBarrierOpt:
2670 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2674 << " base:" << Memory.BaseRegNum;
2677 case k_PostIndexRegister:
2678 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2679 << PostIdxReg.RegNum;
2680 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2681 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2682 << PostIdxReg.ShiftImm;
2685 case k_ProcIFlags: {
2686 OS << "<ARM_PROC::";
2687 unsigned IFlags = getProcIFlags();
2688 for (int i=2; i >= 0; --i)
2689 if (IFlags & (1 << i))
2690 OS << ARM_PROC::IFlagsToString(1 << i);
2695 OS << "<register " << getReg() << ">";
2697 case k_ShifterImmediate:
2698 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2699 << " #" << ShifterImm.Imm << ">";
2701 case k_ShiftedRegister:
2702 OS << "<so_reg_reg "
2703 << RegShiftedReg.SrcReg << " "
2704 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2705 << " " << RegShiftedReg.ShiftReg << ">";
2707 case k_ShiftedImmediate:
2708 OS << "<so_reg_imm "
2709 << RegShiftedImm.SrcReg << " "
2710 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2711 << " #" << RegShiftedImm.ShiftImm << ">";
2713 case k_RotateImmediate:
2714 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2716 case k_BitfieldDescriptor:
2717 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2718 << ", width: " << Bitfield.Width << ">";
2720 case k_RegisterList:
2721 case k_DPRRegisterList:
2722 case k_SPRRegisterList: {
2723 OS << "<register_list ";
2725 const SmallVectorImpl<unsigned> &RegList = getRegList();
2726 for (SmallVectorImpl<unsigned>::const_iterator
2727 I = RegList.begin(), E = RegList.end(); I != E; ) {
2729 if (++I < E) OS << ", ";
2736 OS << "<vector_list " << VectorList.Count << " * "
2737 << VectorList.RegNum << ">";
2739 case k_VectorListAllLanes:
2740 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2741 << VectorList.RegNum << ">";
2743 case k_VectorListIndexed:
2744 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2745 << VectorList.Count << " * " << VectorList.RegNum << ">";
2748 OS << "'" << getToken() << "'";
2751 OS << "<vectorindex " << getVectorIndex() << ">";
2756 /// @name Auto-generated Match Functions
2759 static unsigned MatchRegisterName(StringRef Name);
2763 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2764 SMLoc &StartLoc, SMLoc &EndLoc) {
2765 StartLoc = Parser.getTok().getLoc();
2766 EndLoc = Parser.getTok().getEndLoc();
2767 RegNo = tryParseRegister();
2769 return (RegNo == (unsigned)-1);
2772 /// Try to parse a register name. The token must be an Identifier when called,
2773 /// and if it is a register name the token is eaten and the register number is
2774 /// returned. Otherwise return -1.
2776 int ARMAsmParser::tryParseRegister() {
2777 const AsmToken &Tok = Parser.getTok();
2778 if (Tok.isNot(AsmToken::Identifier)) return -1;
2780 std::string lowerCase = Tok.getString().lower();
2781 unsigned RegNum = MatchRegisterName(lowerCase);
2783 RegNum = StringSwitch<unsigned>(lowerCase)
2784 .Case("r13", ARM::SP)
2785 .Case("r14", ARM::LR)
2786 .Case("r15", ARM::PC)
2787 .Case("ip", ARM::R12)
2788 // Additional register name aliases for 'gas' compatibility.
2789 .Case("a1", ARM::R0)
2790 .Case("a2", ARM::R1)
2791 .Case("a3", ARM::R2)
2792 .Case("a4", ARM::R3)
2793 .Case("v1", ARM::R4)
2794 .Case("v2", ARM::R5)
2795 .Case("v3", ARM::R6)
2796 .Case("v4", ARM::R7)
2797 .Case("v5", ARM::R8)
2798 .Case("v6", ARM::R9)
2799 .Case("v7", ARM::R10)
2800 .Case("v8", ARM::R11)
2801 .Case("sb", ARM::R9)
2802 .Case("sl", ARM::R10)
2803 .Case("fp", ARM::R11)
2807 // Check for aliases registered via .req. Canonicalize to lower case.
2808 // That's more consistent since register names are case insensitive, and
2809 // it's how the original entry was passed in from MC/MCParser/AsmParser.
2810 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2811 // If no match, return failure.
2812 if (Entry == RegisterReqs.end())
2814 Parser.Lex(); // Eat identifier token.
2815 return Entry->getValue();
2818 Parser.Lex(); // Eat identifier token.
2823 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
2824 // If a recoverable error occurs, return 1. If an irrecoverable error
2825 // occurs, return -1. An irrecoverable error is one where tokens have been
2826 // consumed in the process of trying to parse the shifter (i.e., when it is
2827 // indeed a shifter operand, but malformed).
2828 int ARMAsmParser::tryParseShiftRegister(
2829 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2830 SMLoc S = Parser.getTok().getLoc();
2831 const AsmToken &Tok = Parser.getTok();
2832 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2834 std::string lowerCase = Tok.getString().lower();
2835 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2836 .Case("asl", ARM_AM::lsl)
2837 .Case("lsl", ARM_AM::lsl)
2838 .Case("lsr", ARM_AM::lsr)
2839 .Case("asr", ARM_AM::asr)
2840 .Case("ror", ARM_AM::ror)
2841 .Case("rrx", ARM_AM::rrx)
2842 .Default(ARM_AM::no_shift);
2844 if (ShiftTy == ARM_AM::no_shift)
2847 Parser.Lex(); // Eat the operator.
2849 // The source register for the shift has already been added to the
2850 // operand list, so we need to pop it off and combine it into the shifted
2851 // register operand instead.
2852 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2853 if (!PrevOp->isReg())
2854 return Error(PrevOp->getStartLoc(), "shift must be of a register");
2855 int SrcReg = PrevOp->getReg();
2860 if (ShiftTy == ARM_AM::rrx) {
2861 // RRX Doesn't have an explicit shift amount. The encoder expects
2862 // the shift register to be the same as the source register. Seems odd,
2866 // Figure out if this is shifted by a constant or a register (for non-RRX).
2867 if (Parser.getTok().is(AsmToken::Hash) ||
2868 Parser.getTok().is(AsmToken::Dollar)) {
2869 Parser.Lex(); // Eat hash.
2870 SMLoc ImmLoc = Parser.getTok().getLoc();
2871 const MCExpr *ShiftExpr = 0;
2872 if (getParser().parseExpression(ShiftExpr, EndLoc)) {
2873 Error(ImmLoc, "invalid immediate shift value");
2876 // The expression must be evaluatable as an immediate.
2877 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2879 Error(ImmLoc, "invalid immediate shift value");
2882 // Range check the immediate.
2883 // lsl, ror: 0 <= imm <= 31
2884 // lsr, asr: 0 <= imm <= 32
2885 Imm = CE->getValue();
2887 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2888 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2889 Error(ImmLoc, "immediate shift value out of range");
2892 // shift by zero is a nop. Always send it through as lsl.
2893 // ('as' compatibility)
2895 ShiftTy = ARM_AM::lsl;
2896 } else if (Parser.getTok().is(AsmToken::Identifier)) {
2897 SMLoc L = Parser.getTok().getLoc();
2898 EndLoc = Parser.getTok().getEndLoc();
2899 ShiftReg = tryParseRegister();
2900 if (ShiftReg == -1) {
2901 Error (L, "expected immediate or register in shift operand");
2905 Error (Parser.getTok().getLoc(),
2906 "expected immediate or register in shift operand");
2911 if (ShiftReg && ShiftTy != ARM_AM::rrx)
2912 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2916 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2923 /// Try to parse a register name. The token must be an Identifier when called.
2924 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
2925 /// if there is a "writeback". 'true' if it's not a register.
2927 /// TODO this is likely to change to allow different register types and or to
2928 /// parse for a specific register type.
2930 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2931 const AsmToken &RegTok = Parser.getTok();
2932 int RegNo = tryParseRegister();
2936 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
2937 RegTok.getEndLoc()));
2939 const AsmToken &ExclaimTok = Parser.getTok();
2940 if (ExclaimTok.is(AsmToken::Exclaim)) {
2941 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2942 ExclaimTok.getLoc()));
2943 Parser.Lex(); // Eat exclaim token
2947 // Also check for an index operand. This is only legal for vector registers,
2948 // but that'll get caught OK in operand matching, so we don't need to
2949 // explicitly filter everything else out here.
2950 if (Parser.getTok().is(AsmToken::LBrac)) {
2951 SMLoc SIdx = Parser.getTok().getLoc();
2952 Parser.Lex(); // Eat left bracket token.
2954 const MCExpr *ImmVal;
2955 if (getParser().parseExpression(ImmVal))
2957 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2959 return TokError("immediate value expected for vector index");
2961 if (Parser.getTok().isNot(AsmToken::RBrac))
2962 return Error(Parser.getTok().getLoc(), "']' expected");
2964 SMLoc E = Parser.getTok().getEndLoc();
2965 Parser.Lex(); // Eat right bracket token.
2967 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2975 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
2976 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2978 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2979 // Use the same layout as the tablegen'erated register name matcher. Ugly,
2981 switch (Name.size()) {
2984 if (Name[0] != CoprocOp)
3000 if (Name[0] != CoprocOp || Name[1] != '1')
3004 // p10 and p11 are invalid for coproc instructions (reserved for FP/NEON)
3005 case '0': return CoprocOp == 'p'? -1: 10;
3006 case '1': return CoprocOp == 'p'? -1: 11;
3007 case '2': return 12;
3008 case '3': return 13;
3009 case '4': return 14;
3010 case '5': return 15;
3015 /// parseITCondCode - Try to parse a condition code for an IT instruction.
3016 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3017 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3018 SMLoc S = Parser.getTok().getLoc();
3019 const AsmToken &Tok = Parser.getTok();
3020 if (!Tok.is(AsmToken::Identifier))
3021 return MatchOperand_NoMatch;
3022 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
3023 .Case("eq", ARMCC::EQ)
3024 .Case("ne", ARMCC::NE)
3025 .Case("hs", ARMCC::HS)
3026 .Case("cs", ARMCC::HS)
3027 .Case("lo", ARMCC::LO)
3028 .Case("cc", ARMCC::LO)
3029 .Case("mi", ARMCC::MI)
3030 .Case("pl", ARMCC::PL)
3031 .Case("vs", ARMCC::VS)
3032 .Case("vc", ARMCC::VC)
3033 .Case("hi", ARMCC::HI)
3034 .Case("ls", ARMCC::LS)
3035 .Case("ge", ARMCC::GE)
3036 .Case("lt", ARMCC::LT)
3037 .Case("gt", ARMCC::GT)
3038 .Case("le", ARMCC::LE)
3039 .Case("al", ARMCC::AL)
3042 return MatchOperand_NoMatch;
3043 Parser.Lex(); // Eat the token.
3045 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
3047 return MatchOperand_Success;
3050 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
3051 /// token must be an Identifier when called, and if it is a coprocessor
3052 /// number, the token is eaten and the operand is added to the operand list.
3053 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3054 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3055 SMLoc S = Parser.getTok().getLoc();
3056 const AsmToken &Tok = Parser.getTok();
3057 if (Tok.isNot(AsmToken::Identifier))
3058 return MatchOperand_NoMatch;
3060 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
3062 return MatchOperand_NoMatch;
3064 Parser.Lex(); // Eat identifier token.
3065 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
3066 return MatchOperand_Success;
3069 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
3070 /// token must be an Identifier when called, and if it is a coprocessor
3071 /// number, the token is eaten and the operand is added to the operand list.
3072 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3073 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3074 SMLoc S = Parser.getTok().getLoc();
3075 const AsmToken &Tok = Parser.getTok();
3076 if (Tok.isNot(AsmToken::Identifier))
3077 return MatchOperand_NoMatch;
3079 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
3081 return MatchOperand_NoMatch;
3083 Parser.Lex(); // Eat identifier token.
3084 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
3085 return MatchOperand_Success;
3088 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
3089 /// coproc_option : '{' imm0_255 '}'
3090 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3091 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3092 SMLoc S = Parser.getTok().getLoc();
3094 // If this isn't a '{', this isn't a coprocessor immediate operand.
3095 if (Parser.getTok().isNot(AsmToken::LCurly))
3096 return MatchOperand_NoMatch;
3097 Parser.Lex(); // Eat the '{'
3100 SMLoc Loc = Parser.getTok().getLoc();
3101 if (getParser().parseExpression(Expr)) {
3102 Error(Loc, "illegal expression");
3103 return MatchOperand_ParseFail;
3105 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3106 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
3107 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
3108 return MatchOperand_ParseFail;
3110 int Val = CE->getValue();
3112 // Check for and consume the closing '}'
3113 if (Parser.getTok().isNot(AsmToken::RCurly))
3114 return MatchOperand_ParseFail;
3115 SMLoc E = Parser.getTok().getEndLoc();
3116 Parser.Lex(); // Eat the '}'
3118 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
3119 return MatchOperand_Success;
3122 // For register list parsing, we need to map from raw GPR register numbering
3123 // to the enumeration values. The enumeration values aren't sorted by
3124 // register number due to our using "sp", "lr" and "pc" as canonical names.
3125 static unsigned getNextRegister(unsigned Reg) {
3126 // If this is a GPR, we need to do it manually, otherwise we can rely
3127 // on the sort ordering of the enumeration since the other reg-classes
3129 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3132 default: llvm_unreachable("Invalid GPR number!");
3133 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
3134 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
3135 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
3136 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
3137 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
3138 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3139 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
3140 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
3144 // Return the low-subreg of a given Q register.
3145 static unsigned getDRegFromQReg(unsigned QReg) {
3147 default: llvm_unreachable("expected a Q register!");
3148 case ARM::Q0: return ARM::D0;
3149 case ARM::Q1: return ARM::D2;
3150 case ARM::Q2: return ARM::D4;
3151 case ARM::Q3: return ARM::D6;
3152 case ARM::Q4: return ARM::D8;
3153 case ARM::Q5: return ARM::D10;
3154 case ARM::Q6: return ARM::D12;
3155 case ARM::Q7: return ARM::D14;
3156 case ARM::Q8: return ARM::D16;
3157 case ARM::Q9: return ARM::D18;
3158 case ARM::Q10: return ARM::D20;
3159 case ARM::Q11: return ARM::D22;
3160 case ARM::Q12: return ARM::D24;
3161 case ARM::Q13: return ARM::D26;
3162 case ARM::Q14: return ARM::D28;
3163 case ARM::Q15: return ARM::D30;
3167 /// Parse a register list.
3169 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3170 assert(Parser.getTok().is(AsmToken::LCurly) &&
3171 "Token is not a Left Curly Brace");
3172 SMLoc S = Parser.getTok().getLoc();
3173 Parser.Lex(); // Eat '{' token.
3174 SMLoc RegLoc = Parser.getTok().getLoc();
3176 // Check the first register in the list to see what register class
3177 // this is a list of.
3178 int Reg = tryParseRegister();
3180 return Error(RegLoc, "register expected");
3182 // The reglist instructions have at most 16 registers, so reserve
3183 // space for that many.
3185 SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3187 // Allow Q regs and just interpret them as the two D sub-registers.
3188 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3189 Reg = getDRegFromQReg(Reg);
3190 EReg = MRI->getEncodingValue(Reg);
3191 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3194 const MCRegisterClass *RC;
3195 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3196 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3197 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3198 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3199 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3200 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3202 return Error(RegLoc, "invalid register in register list");
3204 // Store the register.
3205 EReg = MRI->getEncodingValue(Reg);
3206 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3208 // This starts immediately after the first register token in the list,
3209 // so we can see either a comma or a minus (range separator) as a legal
3211 while (Parser.getTok().is(AsmToken::Comma) ||
3212 Parser.getTok().is(AsmToken::Minus)) {
3213 if (Parser.getTok().is(AsmToken::Minus)) {
3214 Parser.Lex(); // Eat the minus.
3215 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3216 int EndReg = tryParseRegister();
3218 return Error(AfterMinusLoc, "register expected");
3219 // Allow Q regs and just interpret them as the two D sub-registers.
3220 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3221 EndReg = getDRegFromQReg(EndReg) + 1;
3222 // If the register is the same as the start reg, there's nothing
3226 // The register must be in the same register class as the first.
3227 if (!RC->contains(EndReg))
3228 return Error(AfterMinusLoc, "invalid register in register list");
3229 // Ranges must go from low to high.
3230 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3231 return Error(AfterMinusLoc, "bad range in register list");
3233 // Add all the registers in the range to the register list.
3234 while (Reg != EndReg) {
3235 Reg = getNextRegister(Reg);
3236 EReg = MRI->getEncodingValue(Reg);
3237 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3241 Parser.Lex(); // Eat the comma.
3242 RegLoc = Parser.getTok().getLoc();
3244 const AsmToken RegTok = Parser.getTok();
3245 Reg = tryParseRegister();
3247 return Error(RegLoc, "register expected");
3248 // Allow Q regs and just interpret them as the two D sub-registers.
3249 bool isQReg = false;
3250 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3251 Reg = getDRegFromQReg(Reg);
3254 // The register must be in the same register class as the first.
3255 if (!RC->contains(Reg))
3256 return Error(RegLoc, "invalid register in register list");
3257 // List must be monotonically increasing.
3258 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3259 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3260 Warning(RegLoc, "register list not in ascending order");
3262 return Error(RegLoc, "register list not in ascending order");
3264 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3265 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3266 ") in register list");
3269 // VFP register lists must also be contiguous.
3270 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3272 return Error(RegLoc, "non-contiguous register range");
3273 EReg = MRI->getEncodingValue(Reg);
3274 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3276 EReg = MRI->getEncodingValue(++Reg);
3277 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3281 if (Parser.getTok().isNot(AsmToken::RCurly))
3282 return Error(Parser.getTok().getLoc(), "'}' expected");
3283 SMLoc E = Parser.getTok().getEndLoc();
3284 Parser.Lex(); // Eat '}' token.
3286 // Push the register list operand.
3287 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3289 // The ARM system instruction variants for LDM/STM have a '^' token here.
3290 if (Parser.getTok().is(AsmToken::Caret)) {
3291 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3292 Parser.Lex(); // Eat '^' token.
3298 // Helper function to parse the lane index for vector lists.
3299 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3300 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3301 Index = 0; // Always return a defined index value.
3302 if (Parser.getTok().is(AsmToken::LBrac)) {
3303 Parser.Lex(); // Eat the '['.
3304 if (Parser.getTok().is(AsmToken::RBrac)) {
3305 // "Dn[]" is the 'all lanes' syntax.
3306 LaneKind = AllLanes;
3307 EndLoc = Parser.getTok().getEndLoc();
3308 Parser.Lex(); // Eat the ']'.
3309 return MatchOperand_Success;
3312 // There's an optional '#' token here. Normally there wouldn't be, but
3313 // inline assemble puts one in, and it's friendly to accept that.
3314 if (Parser.getTok().is(AsmToken::Hash))
3315 Parser.Lex(); // Eat '#' or '$'.
3317 const MCExpr *LaneIndex;
3318 SMLoc Loc = Parser.getTok().getLoc();
3319 if (getParser().parseExpression(LaneIndex)) {
3320 Error(Loc, "illegal expression");
3321 return MatchOperand_ParseFail;
3323 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3325 Error(Loc, "lane index must be empty or an integer");
3326 return MatchOperand_ParseFail;
3328 if (Parser.getTok().isNot(AsmToken::RBrac)) {
3329 Error(Parser.getTok().getLoc(), "']' expected");
3330 return MatchOperand_ParseFail;
3332 EndLoc = Parser.getTok().getEndLoc();
3333 Parser.Lex(); // Eat the ']'.
3334 int64_t Val = CE->getValue();
3336 // FIXME: Make this range check context sensitive for .8, .16, .32.
3337 if (Val < 0 || Val > 7) {
3338 Error(Parser.getTok().getLoc(), "lane index out of range");
3339 return MatchOperand_ParseFail;
3342 LaneKind = IndexedLane;
3343 return MatchOperand_Success;
3346 return MatchOperand_Success;
3349 // parse a vector register list
3350 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3351 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3352 VectorLaneTy LaneKind;
3354 SMLoc S = Parser.getTok().getLoc();
3355 // As an extension (to match gas), support a plain D register or Q register
3356 // (without encosing curly braces) as a single or double entry list,
3358 if (Parser.getTok().is(AsmToken::Identifier)) {
3359 SMLoc E = Parser.getTok().getEndLoc();
3360 int Reg = tryParseRegister();
3362 return MatchOperand_NoMatch;
3363 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3364 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3365 if (Res != MatchOperand_Success)
3369 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3372 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3376 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3381 return MatchOperand_Success;
3383 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3384 Reg = getDRegFromQReg(Reg);
3385 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3386 if (Res != MatchOperand_Success)
3390 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3391 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3392 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3395 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3396 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3397 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3401 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3406 return MatchOperand_Success;
3408 Error(S, "vector register expected");
3409 return MatchOperand_ParseFail;
3412 if (Parser.getTok().isNot(AsmToken::LCurly))
3413 return MatchOperand_NoMatch;
3415 Parser.Lex(); // Eat '{' token.
3416 SMLoc RegLoc = Parser.getTok().getLoc();
3418 int Reg = tryParseRegister();
3420 Error(RegLoc, "register expected");
3421 return MatchOperand_ParseFail;
3425 unsigned FirstReg = Reg;
3426 // The list is of D registers, but we also allow Q regs and just interpret
3427 // them as the two D sub-registers.
3428 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3429 FirstReg = Reg = getDRegFromQReg(Reg);
3430 Spacing = 1; // double-spacing requires explicit D registers, otherwise
3431 // it's ambiguous with four-register single spaced.
3437 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3438 return MatchOperand_ParseFail;
3440 while (Parser.getTok().is(AsmToken::Comma) ||
3441 Parser.getTok().is(AsmToken::Minus)) {
3442 if (Parser.getTok().is(AsmToken::Minus)) {
3444 Spacing = 1; // Register range implies a single spaced list.
3445 else if (Spacing == 2) {
3446 Error(Parser.getTok().getLoc(),
3447 "sequential registers in double spaced list");
3448 return MatchOperand_ParseFail;
3450 Parser.Lex(); // Eat the minus.
3451 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3452 int EndReg = tryParseRegister();
3454 Error(AfterMinusLoc, "register expected");
3455 return MatchOperand_ParseFail;
3457 // Allow Q regs and just interpret them as the two D sub-registers.
3458 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3459 EndReg = getDRegFromQReg(EndReg) + 1;
3460 // If the register is the same as the start reg, there's nothing
3464 // The register must be in the same register class as the first.
3465 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3466 Error(AfterMinusLoc, "invalid register in register list");
3467 return MatchOperand_ParseFail;
3469 // Ranges must go from low to high.
3471 Error(AfterMinusLoc, "bad range in register list");
3472 return MatchOperand_ParseFail;
3474 // Parse the lane specifier if present.
3475 VectorLaneTy NextLaneKind;
3476 unsigned NextLaneIndex;
3477 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3478 MatchOperand_Success)
3479 return MatchOperand_ParseFail;
3480 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3481 Error(AfterMinusLoc, "mismatched lane index in register list");
3482 return MatchOperand_ParseFail;
3485 // Add all the registers in the range to the register list.
3486 Count += EndReg - Reg;
3490 Parser.Lex(); // Eat the comma.
3491 RegLoc = Parser.getTok().getLoc();
3493 Reg = tryParseRegister();
3495 Error(RegLoc, "register expected");
3496 return MatchOperand_ParseFail;
3498 // vector register lists must be contiguous.
3499 // It's OK to use the enumeration values directly here rather, as the
3500 // VFP register classes have the enum sorted properly.
3502 // The list is of D registers, but we also allow Q regs and just interpret
3503 // them as the two D sub-registers.
3504 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3506 Spacing = 1; // Register range implies a single spaced list.
3507 else if (Spacing == 2) {
3509 "invalid register in double-spaced list (must be 'D' register')");
3510 return MatchOperand_ParseFail;
3512 Reg = getDRegFromQReg(Reg);
3513 if (Reg != OldReg + 1) {
3514 Error(RegLoc, "non-contiguous register range");
3515 return MatchOperand_ParseFail;
3519 // Parse the lane specifier if present.
3520 VectorLaneTy NextLaneKind;
3521 unsigned NextLaneIndex;
3522 SMLoc LaneLoc = Parser.getTok().getLoc();
3523 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3524 MatchOperand_Success)
3525 return MatchOperand_ParseFail;
3526 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3527 Error(LaneLoc, "mismatched lane index in register list");
3528 return MatchOperand_ParseFail;
3532 // Normal D register.
3533 // Figure out the register spacing (single or double) of the list if
3534 // we don't know it already.
3536 Spacing = 1 + (Reg == OldReg + 2);
3538 // Just check that it's contiguous and keep going.
3539 if (Reg != OldReg + Spacing) {
3540 Error(RegLoc, "non-contiguous register range");
3541 return MatchOperand_ParseFail;
3544 // Parse the lane specifier if present.
3545 VectorLaneTy NextLaneKind;
3546 unsigned NextLaneIndex;
3547 SMLoc EndLoc = Parser.getTok().getLoc();
3548 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3549 return MatchOperand_ParseFail;
3550 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3551 Error(EndLoc, "mismatched lane index in register list");
3552 return MatchOperand_ParseFail;
3556 if (Parser.getTok().isNot(AsmToken::RCurly)) {
3557 Error(Parser.getTok().getLoc(), "'}' expected");
3558 return MatchOperand_ParseFail;
3560 E = Parser.getTok().getEndLoc();
3561 Parser.Lex(); // Eat '}' token.
3565 // Two-register operands have been converted to the
3566 // composite register classes.
3568 const MCRegisterClass *RC = (Spacing == 1) ?
3569 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3570 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3571 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3574 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3575 (Spacing == 2), S, E));
3578 // Two-register operands have been converted to the
3579 // composite register classes.
3581 const MCRegisterClass *RC = (Spacing == 1) ?
3582 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3583 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3584 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3586 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3591 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3597 return MatchOperand_Success;
3600 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3601 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3602 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3603 SMLoc S = Parser.getTok().getLoc();
3604 const AsmToken &Tok = Parser.getTok();
3607 if (Tok.is(AsmToken::Identifier)) {
3608 StringRef OptStr = Tok.getString();
3610 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3611 .Case("sy", ARM_MB::SY)
3612 .Case("st", ARM_MB::ST)
3613 .Case("ld", ARM_MB::LD)
3614 .Case("sh", ARM_MB::ISH)
3615 .Case("ish", ARM_MB::ISH)
3616 .Case("shst", ARM_MB::ISHST)
3617 .Case("ishst", ARM_MB::ISHST)
3618 .Case("ishld", ARM_MB::ISHLD)
3619 .Case("nsh", ARM_MB::NSH)
3620 .Case("un", ARM_MB::NSH)
3621 .Case("nshst", ARM_MB::NSHST)
3622 .Case("nshld", ARM_MB::NSHLD)
3623 .Case("unst", ARM_MB::NSHST)
3624 .Case("osh", ARM_MB::OSH)
3625 .Case("oshst", ARM_MB::OSHST)
3626 .Case("oshld", ARM_MB::OSHLD)
3629 // ishld, oshld, nshld and ld are only available from ARMv8.
3630 if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
3631 Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
3635 return MatchOperand_NoMatch;
3637 Parser.Lex(); // Eat identifier token.
3638 } else if (Tok.is(AsmToken::Hash) ||
3639 Tok.is(AsmToken::Dollar) ||
3640 Tok.is(AsmToken::Integer)) {
3641 if (Parser.getTok().isNot(AsmToken::Integer))
3642 Parser.Lex(); // Eat '#' or '$'.
3643 SMLoc Loc = Parser.getTok().getLoc();
3645 const MCExpr *MemBarrierID;
3646 if (getParser().parseExpression(MemBarrierID)) {
3647 Error(Loc, "illegal expression");
3648 return MatchOperand_ParseFail;
3651 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3653 Error(Loc, "constant expression expected");
3654 return MatchOperand_ParseFail;
3657 int Val = CE->getValue();
3659 Error(Loc, "immediate value out of range");
3660 return MatchOperand_ParseFail;
3663 Opt = ARM_MB::RESERVED_0 + Val;
3665 return MatchOperand_ParseFail;
3667 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3668 return MatchOperand_Success;
3671 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3672 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3673 parseInstSyncBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3674 SMLoc S = Parser.getTok().getLoc();
3675 const AsmToken &Tok = Parser.getTok();
3678 if (Tok.is(AsmToken::Identifier)) {
3679 StringRef OptStr = Tok.getString();
3681 if (OptStr.equals_lower("sy"))
3684 return MatchOperand_NoMatch;
3686 Parser.Lex(); // Eat identifier token.
3687 } else if (Tok.is(AsmToken::Hash) ||
3688 Tok.is(AsmToken::Dollar) ||
3689 Tok.is(AsmToken::Integer)) {
3690 if (Parser.getTok().isNot(AsmToken::Integer))
3691 Parser.Lex(); // Eat '#' or '$'.
3692 SMLoc Loc = Parser.getTok().getLoc();
3694 const MCExpr *ISBarrierID;
3695 if (getParser().parseExpression(ISBarrierID)) {
3696 Error(Loc, "illegal expression");
3697 return MatchOperand_ParseFail;
3700 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3702 Error(Loc, "constant expression expected");
3703 return MatchOperand_ParseFail;
3706 int Val = CE->getValue();
3708 Error(Loc, "immediate value out of range");
3709 return MatchOperand_ParseFail;
3712 Opt = ARM_ISB::RESERVED_0 + Val;
3714 return MatchOperand_ParseFail;
3716 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3717 (ARM_ISB::InstSyncBOpt)Opt, S));
3718 return MatchOperand_Success;
3722 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3723 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3724 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3725 SMLoc S = Parser.getTok().getLoc();
3726 const AsmToken &Tok = Parser.getTok();
3727 if (!Tok.is(AsmToken::Identifier))
3728 return MatchOperand_NoMatch;
3729 StringRef IFlagsStr = Tok.getString();
3731 // An iflags string of "none" is interpreted to mean that none of the AIF
3732 // bits are set. Not a terribly useful instruction, but a valid encoding.
3733 unsigned IFlags = 0;
3734 if (IFlagsStr != "none") {
3735 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3736 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3737 .Case("a", ARM_PROC::A)
3738 .Case("i", ARM_PROC::I)
3739 .Case("f", ARM_PROC::F)
3742 // If some specific iflag is already set, it means that some letter is
3743 // present more than once, this is not acceptable.
3744 if (Flag == ~0U || (IFlags & Flag))
3745 return MatchOperand_NoMatch;
3751 Parser.Lex(); // Eat identifier token.
3752 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3753 return MatchOperand_Success;
3756 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3757 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3758 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3759 SMLoc S = Parser.getTok().getLoc();
3760 const AsmToken &Tok = Parser.getTok();
3761 if (!Tok.is(AsmToken::Identifier))
3762 return MatchOperand_NoMatch;
3763 StringRef Mask = Tok.getString();
3766 // See ARMv6-M 10.1.1
3767 std::string Name = Mask.lower();
3768 unsigned FlagsVal = StringSwitch<unsigned>(Name)
3769 // Note: in the documentation:
3770 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3771 // for MSR APSR_nzcvq.
3772 // but we do make it an alias here. This is so to get the "mask encoding"
3773 // bits correct on MSR APSR writes.
3775 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3776 // should really only be allowed when writing a special register. Note
3777 // they get dropped in the MRS instruction reading a special register as
3778 // the SYSm field is only 8 bits.
3780 // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3781 // includes the DSP extension but that is not checked.
3782 .Case("apsr", 0x800)
3783 .Case("apsr_nzcvq", 0x800)
3784 .Case("apsr_g", 0x400)
3785 .Case("apsr_nzcvqg", 0xc00)
3786 .Case("iapsr", 0x801)
3787 .Case("iapsr_nzcvq", 0x801)
3788 .Case("iapsr_g", 0x401)
3789 .Case("iapsr_nzcvqg", 0xc01)
3790 .Case("eapsr", 0x802)
3791 .Case("eapsr_nzcvq", 0x802)
3792 .Case("eapsr_g", 0x402)
3793 .Case("eapsr_nzcvqg", 0xc02)
3794 .Case("xpsr", 0x803)
3795 .Case("xpsr_nzcvq", 0x803)
3796 .Case("xpsr_g", 0x403)
3797 .Case("xpsr_nzcvqg", 0xc03)
3798 .Case("ipsr", 0x805)
3799 .Case("epsr", 0x806)
3800 .Case("iepsr", 0x807)
3803 .Case("primask", 0x810)
3804 .Case("basepri", 0x811)
3805 .Case("basepri_max", 0x812)
3806 .Case("faultmask", 0x813)
3807 .Case("control", 0x814)
3810 if (FlagsVal == ~0U)
3811 return MatchOperand_NoMatch;
3813 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3814 // basepri, basepri_max and faultmask only valid for V7m.
3815 return MatchOperand_NoMatch;
3817 Parser.Lex(); // Eat identifier token.
3818 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3819 return MatchOperand_Success;
3822 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3823 size_t Start = 0, Next = Mask.find('_');
3824 StringRef Flags = "";
3825 std::string SpecReg = Mask.slice(Start, Next).lower();
3826 if (Next != StringRef::npos)
3827 Flags = Mask.slice(Next+1, Mask.size());
3829 // FlagsVal contains the complete mask:
3831 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3832 unsigned FlagsVal = 0;
3834 if (SpecReg == "apsr") {
3835 FlagsVal = StringSwitch<unsigned>(Flags)
3836 .Case("nzcvq", 0x8) // same as CPSR_f
3837 .Case("g", 0x4) // same as CPSR_s
3838 .Case("nzcvqg", 0xc) // same as CPSR_fs
3841 if (FlagsVal == ~0U) {
3843 return MatchOperand_NoMatch;
3845 FlagsVal = 8; // No flag
3847 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3848 // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3849 if (Flags == "all" || Flags == "")
3851 for (int i = 0, e = Flags.size(); i != e; ++i) {
3852 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3859 // If some specific flag is already set, it means that some letter is
3860 // present more than once, this is not acceptable.
3861 if (FlagsVal == ~0U || (FlagsVal & Flag))
3862 return MatchOperand_NoMatch;
3865 } else // No match for special register.
3866 return MatchOperand_NoMatch;
3868 // Special register without flags is NOT equivalent to "fc" flags.
3869 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
3870 // two lines would enable gas compatibility at the expense of breaking
3876 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3877 if (SpecReg == "spsr")
3880 Parser.Lex(); // Eat identifier token.
3881 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3882 return MatchOperand_Success;
3885 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3886 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3887 int Low, int High) {
3888 const AsmToken &Tok = Parser.getTok();
3889 if (Tok.isNot(AsmToken::Identifier)) {
3890 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3891 return MatchOperand_ParseFail;
3893 StringRef ShiftName = Tok.getString();
3894 std::string LowerOp = Op.lower();
3895 std::string UpperOp = Op.upper();
3896 if (ShiftName != LowerOp && ShiftName != UpperOp) {
3897 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3898 return MatchOperand_ParseFail;
3900 Parser.Lex(); // Eat shift type token.
3902 // There must be a '#' and a shift amount.
3903 if (Parser.getTok().isNot(AsmToken::Hash) &&
3904 Parser.getTok().isNot(AsmToken::Dollar)) {
3905 Error(Parser.getTok().getLoc(), "'#' expected");
3906 return MatchOperand_ParseFail;
3908 Parser.Lex(); // Eat hash token.
3910 const MCExpr *ShiftAmount;
3911 SMLoc Loc = Parser.getTok().getLoc();
3913 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3914 Error(Loc, "illegal expression");
3915 return MatchOperand_ParseFail;
3917 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3919 Error(Loc, "constant expression expected");
3920 return MatchOperand_ParseFail;
3922 int Val = CE->getValue();
3923 if (Val < Low || Val > High) {
3924 Error(Loc, "immediate value out of range");
3925 return MatchOperand_ParseFail;
3928 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
3930 return MatchOperand_Success;
3933 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3934 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3935 const AsmToken &Tok = Parser.getTok();
3936 SMLoc S = Tok.getLoc();
3937 if (Tok.isNot(AsmToken::Identifier)) {
3938 Error(S, "'be' or 'le' operand expected");
3939 return MatchOperand_ParseFail;
3941 int Val = StringSwitch<int>(Tok.getString().lower())
3945 Parser.Lex(); // Eat the token.
3948 Error(S, "'be' or 'le' operand expected");
3949 return MatchOperand_ParseFail;
3951 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3953 S, Tok.getEndLoc()));
3954 return MatchOperand_Success;
3957 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3958 /// instructions. Legal values are:
3959 /// lsl #n 'n' in [0,31]
3960 /// asr #n 'n' in [1,32]
3961 /// n == 32 encoded as n == 0.
3962 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3963 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3964 const AsmToken &Tok = Parser.getTok();
3965 SMLoc S = Tok.getLoc();
3966 if (Tok.isNot(AsmToken::Identifier)) {
3967 Error(S, "shift operator 'asr' or 'lsl' expected");
3968 return MatchOperand_ParseFail;
3970 StringRef ShiftName = Tok.getString();
3972 if (ShiftName == "lsl" || ShiftName == "LSL")
3974 else if (ShiftName == "asr" || ShiftName == "ASR")
3977 Error(S, "shift operator 'asr' or 'lsl' expected");
3978 return MatchOperand_ParseFail;
3980 Parser.Lex(); // Eat the operator.
3982 // A '#' and a shift amount.
3983 if (Parser.getTok().isNot(AsmToken::Hash) &&
3984 Parser.getTok().isNot(AsmToken::Dollar)) {
3985 Error(Parser.getTok().getLoc(), "'#' expected");
3986 return MatchOperand_ParseFail;
3988 Parser.Lex(); // Eat hash token.
3989 SMLoc ExLoc = Parser.getTok().getLoc();
3991 const MCExpr *ShiftAmount;
3993 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3994 Error(ExLoc, "malformed shift expression");
3995 return MatchOperand_ParseFail;
3997 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3999 Error(ExLoc, "shift amount must be an immediate");
4000 return MatchOperand_ParseFail;
4003 int64_t Val = CE->getValue();
4005 // Shift amount must be in [1,32]
4006 if (Val < 1 || Val > 32) {
4007 Error(ExLoc, "'asr' shift amount must be in range [1,32]");
4008 return MatchOperand_ParseFail;
4010 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
4011 if (isThumb() && Val == 32) {
4012 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
4013 return MatchOperand_ParseFail;
4015 if (Val == 32) Val = 0;
4017 // Shift amount must be in [1,32]
4018 if (Val < 0 || Val > 31) {
4019 Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
4020 return MatchOperand_ParseFail;
4024 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
4026 return MatchOperand_Success;
4029 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
4030 /// of instructions. Legal values are:
4031 /// ror #n 'n' in {0, 8, 16, 24}
4032 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4033 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4034 const AsmToken &Tok = Parser.getTok();
4035 SMLoc S = Tok.getLoc();
4036 if (Tok.isNot(AsmToken::Identifier))
4037 return MatchOperand_NoMatch;
4038 StringRef ShiftName = Tok.getString();
4039 if (ShiftName != "ror" && ShiftName != "ROR")
4040 return MatchOperand_NoMatch;
4041 Parser.Lex(); // Eat the operator.
4043 // A '#' and a rotate amount.
4044 if (Parser.getTok().isNot(AsmToken::Hash) &&
4045 Parser.getTok().isNot(AsmToken::Dollar)) {
4046 Error(Parser.getTok().getLoc(), "'#' expected");
4047 return MatchOperand_ParseFail;
4049 Parser.Lex(); // Eat hash token.
4050 SMLoc ExLoc = Parser.getTok().getLoc();
4052 const MCExpr *ShiftAmount;
4054 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4055 Error(ExLoc, "malformed rotate expression");
4056 return MatchOperand_ParseFail;
4058 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4060 Error(ExLoc, "rotate amount must be an immediate");
4061 return MatchOperand_ParseFail;
4064 int64_t Val = CE->getValue();
4065 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
4066 // normally, zero is represented in asm by omitting the rotate operand
4068 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
4069 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
4070 return MatchOperand_ParseFail;
4073 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
4075 return MatchOperand_Success;
4078 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4079 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4080 SMLoc S = Parser.getTok().getLoc();
4081 // The bitfield descriptor is really two operands, the LSB and the width.
4082 if (Parser.getTok().isNot(AsmToken::Hash) &&
4083 Parser.getTok().isNot(AsmToken::Dollar)) {
4084 Error(Parser.getTok().getLoc(), "'#' expected");
4085 return MatchOperand_ParseFail;
4087 Parser.Lex(); // Eat hash token.
4089 const MCExpr *LSBExpr;
4090 SMLoc E = Parser.getTok().getLoc();
4091 if (getParser().parseExpression(LSBExpr)) {
4092 Error(E, "malformed immediate expression");
4093 return MatchOperand_ParseFail;
4095 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
4097 Error(E, "'lsb' operand must be an immediate");
4098 return MatchOperand_ParseFail;
4101 int64_t LSB = CE->getValue();
4102 // The LSB must be in the range [0,31]
4103 if (LSB < 0 || LSB > 31) {
4104 Error(E, "'lsb' operand must be in the range [0,31]");
4105 return MatchOperand_ParseFail;
4107 E = Parser.getTok().getLoc();
4109 // Expect another immediate operand.
4110 if (Parser.getTok().isNot(AsmToken::Comma)) {
4111 Error(Parser.getTok().getLoc(), "too few operands");
4112 return MatchOperand_ParseFail;
4114 Parser.Lex(); // Eat hash token.
4115 if (Parser.getTok().isNot(AsmToken::Hash) &&
4116 Parser.getTok().isNot(AsmToken::Dollar)) {
4117 Error(Parser.getTok().getLoc(), "'#' expected");
4118 return MatchOperand_ParseFail;
4120 Parser.Lex(); // Eat hash token.
4122 const MCExpr *WidthExpr;
4124 if (getParser().parseExpression(WidthExpr, EndLoc)) {
4125 Error(E, "malformed immediate expression");
4126 return MatchOperand_ParseFail;
4128 CE = dyn_cast<MCConstantExpr>(WidthExpr);
4130 Error(E, "'width' operand must be an immediate");
4131 return MatchOperand_ParseFail;
4134 int64_t Width = CE->getValue();
4135 // The LSB must be in the range [1,32-lsb]
4136 if (Width < 1 || Width > 32 - LSB) {
4137 Error(E, "'width' operand must be in the range [1,32-lsb]");
4138 return MatchOperand_ParseFail;
4141 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4143 return MatchOperand_Success;
4146 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4147 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4148 // Check for a post-index addressing register operand. Specifically:
4149 // postidx_reg := '+' register {, shift}
4150 // | '-' register {, shift}
4151 // | register {, shift}
4153 // This method must return MatchOperand_NoMatch without consuming any tokens
4154 // in the case where there is no match, as other alternatives take other
4156 AsmToken Tok = Parser.getTok();
4157 SMLoc S = Tok.getLoc();
4158 bool haveEaten = false;
4160 if (Tok.is(AsmToken::Plus)) {
4161 Parser.Lex(); // Eat the '+' token.
4163 } else if (Tok.is(AsmToken::Minus)) {
4164 Parser.Lex(); // Eat the '-' token.
4169 SMLoc E = Parser.getTok().getEndLoc();
4170 int Reg = tryParseRegister();
4173 return MatchOperand_NoMatch;
4174 Error(Parser.getTok().getLoc(), "register expected");
4175 return MatchOperand_ParseFail;
4178 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4179 unsigned ShiftImm = 0;
4180 if (Parser.getTok().is(AsmToken::Comma)) {
4181 Parser.Lex(); // Eat the ','.
4182 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4183 return MatchOperand_ParseFail;
4185 // FIXME: Only approximates end...may include intervening whitespace.
4186 E = Parser.getTok().getLoc();
4189 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4192 return MatchOperand_Success;
4195 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4196 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4197 // Check for a post-index addressing register operand. Specifically:
4198 // am3offset := '+' register
4205 // This method must return MatchOperand_NoMatch without consuming any tokens
4206 // in the case where there is no match, as other alternatives take other
4208 AsmToken Tok = Parser.getTok();
4209 SMLoc S = Tok.getLoc();
4211 // Do immediates first, as we always parse those if we have a '#'.
4212 if (Parser.getTok().is(AsmToken::Hash) ||
4213 Parser.getTok().is(AsmToken::Dollar)) {
4214 Parser.Lex(); // Eat '#' or '$'.
4215 // Explicitly look for a '-', as we need to encode negative zero
4217 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4218 const MCExpr *Offset;
4220 if (getParser().parseExpression(Offset, E))
4221 return MatchOperand_ParseFail;
4222 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4224 Error(S, "constant expression expected");
4225 return MatchOperand_ParseFail;
4227 // Negative zero is encoded as the flag value INT32_MIN.
4228 int32_t Val = CE->getValue();
4229 if (isNegative && Val == 0)
4233 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4235 return MatchOperand_Success;
4239 bool haveEaten = false;
4241 if (Tok.is(AsmToken::Plus)) {
4242 Parser.Lex(); // Eat the '+' token.
4244 } else if (Tok.is(AsmToken::Minus)) {
4245 Parser.Lex(); // Eat the '-' token.
4250 Tok = Parser.getTok();
4251 int Reg = tryParseRegister();
4254 return MatchOperand_NoMatch;
4255 Error(Tok.getLoc(), "register expected");
4256 return MatchOperand_ParseFail;
4259 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4260 0, S, Tok.getEndLoc()));
4262 return MatchOperand_Success;
4265 /// Convert parsed operands to MCInst. Needed here because this instruction
4266 /// only has two register operands, but multiplication is commutative so
4267 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4269 cvtThumbMultiply(MCInst &Inst,
4270 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4271 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4272 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4273 // If we have a three-operand form, make sure to set Rn to be the operand
4274 // that isn't the same as Rd.
4276 if (Operands.size() == 6 &&
4277 ((ARMOperand*)Operands[4])->getReg() ==
4278 ((ARMOperand*)Operands[3])->getReg())
4280 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4281 Inst.addOperand(Inst.getOperand(0));
4282 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4286 cvtThumbBranches(MCInst &Inst,
4287 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4288 int CondOp = -1, ImmOp = -1;
4289 switch(Inst.getOpcode()) {
4291 case ARM::tBcc: CondOp = 1; ImmOp = 2; break;
4294 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4296 default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4298 // first decide whether or not the branch should be conditional
4299 // by looking at it's location relative to an IT block
4301 // inside an IT block we cannot have any conditional branches. any
4302 // such instructions needs to be converted to unconditional form
4303 switch(Inst.getOpcode()) {
4304 case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4305 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4308 // outside IT blocks we can only have unconditional branches with AL
4309 // condition code or conditional branches with non-AL condition code
4310 unsigned Cond = static_cast<ARMOperand*>(Operands[CondOp])->getCondCode();
4311 switch(Inst.getOpcode()) {
4314 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4318 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4323 // now decide on encoding size based on branch target range
4324 switch(Inst.getOpcode()) {
4325 // classify tB as either t2B or t1B based on range of immediate operand
4327 ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4328 if(!op->isSignedOffset<11, 1>() && isThumbTwo())
4329 Inst.setOpcode(ARM::t2B);
4332 // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4334 ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4335 if(!op->isSignedOffset<8, 1>() && isThumbTwo())
4336 Inst.setOpcode(ARM::t2Bcc);
4340 ((ARMOperand*)Operands[ImmOp])->addImmOperands(Inst, 1);
4341 ((ARMOperand*)Operands[CondOp])->addCondCodeOperands(Inst, 2);
4344 /// Parse an ARM memory expression, return false if successful else return true
4345 /// or an error. The first token must be a '[' when called.
4347 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4349 assert(Parser.getTok().is(AsmToken::LBrac) &&
4350 "Token is not a Left Bracket");
4351 S = Parser.getTok().getLoc();
4352 Parser.Lex(); // Eat left bracket token.
4354 const AsmToken &BaseRegTok = Parser.getTok();
4355 int BaseRegNum = tryParseRegister();
4356 if (BaseRegNum == -1)
4357 return Error(BaseRegTok.getLoc(), "register expected");
4359 // The next token must either be a comma, a colon or a closing bracket.
4360 const AsmToken &Tok = Parser.getTok();
4361 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4362 !Tok.is(AsmToken::RBrac))
4363 return Error(Tok.getLoc(), "malformed memory operand");
4365 if (Tok.is(AsmToken::RBrac)) {
4366 E = Tok.getEndLoc();
4367 Parser.Lex(); // Eat right bracket token.
4369 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4370 0, 0, false, S, E));
4372 // If there's a pre-indexing writeback marker, '!', just add it as a token
4373 // operand. It's rather odd, but syntactically valid.
4374 if (Parser.getTok().is(AsmToken::Exclaim)) {
4375 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4376 Parser.Lex(); // Eat the '!'.
4382 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4383 "Lost colon or comma in memory operand?!");
4384 if (Tok.is(AsmToken::Comma)) {
4385 Parser.Lex(); // Eat the comma.
4388 // If we have a ':', it's an alignment specifier.
4389 if (Parser.getTok().is(AsmToken::Colon)) {
4390 Parser.Lex(); // Eat the ':'.
4391 E = Parser.getTok().getLoc();
4394 if (getParser().parseExpression(Expr))
4397 // The expression has to be a constant. Memory references with relocations
4398 // don't come through here, as they use the <label> forms of the relevant
4400 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4402 return Error (E, "constant expression expected");
4405 switch (CE->getValue()) {
4408 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4409 case 16: Align = 2; break;
4410 case 32: Align = 4; break;
4411 case 64: Align = 8; break;
4412 case 128: Align = 16; break;
4413 case 256: Align = 32; break;
4416 // Now we should have the closing ']'
4417 if (Parser.getTok().isNot(AsmToken::RBrac))
4418 return Error(Parser.getTok().getLoc(), "']' expected");
4419 E = Parser.getTok().getEndLoc();
4420 Parser.Lex(); // Eat right bracket token.
4422 // Don't worry about range checking the value here. That's handled by
4423 // the is*() predicates.
4424 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4425 ARM_AM::no_shift, 0, Align,
4428 // If there's a pre-indexing writeback marker, '!', just add it as a token
4430 if (Parser.getTok().is(AsmToken::Exclaim)) {
4431 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4432 Parser.Lex(); // Eat the '!'.
4438 // If we have a '#', it's an immediate offset, else assume it's a register
4439 // offset. Be friendly and also accept a plain integer (without a leading
4440 // hash) for gas compatibility.
4441 if (Parser.getTok().is(AsmToken::Hash) ||
4442 Parser.getTok().is(AsmToken::Dollar) ||
4443 Parser.getTok().is(AsmToken::Integer)) {
4444 if (Parser.getTok().isNot(AsmToken::Integer))
4445 Parser.Lex(); // Eat '#' or '$'.
4446 E = Parser.getTok().getLoc();
4448 bool isNegative = getParser().getTok().is(AsmToken::Minus);
4449 const MCExpr *Offset;
4450 if (getParser().parseExpression(Offset))
4453 // The expression has to be a constant. Memory references with relocations
4454 // don't come through here, as they use the <label> forms of the relevant
4456 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4458 return Error (E, "constant expression expected");
4460 // If the constant was #-0, represent it as INT32_MIN.
4461 int32_t Val = CE->getValue();
4462 if (isNegative && Val == 0)
4463 CE = MCConstantExpr::Create(INT32_MIN, getContext());
4465 // Now we should have the closing ']'
4466 if (Parser.getTok().isNot(AsmToken::RBrac))
4467 return Error(Parser.getTok().getLoc(), "']' expected");
4468 E = Parser.getTok().getEndLoc();
4469 Parser.Lex(); // Eat right bracket token.
4471 // Don't worry about range checking the value here. That's handled by
4472 // the is*() predicates.
4473 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4474 ARM_AM::no_shift, 0, 0,
4477 // If there's a pre-indexing writeback marker, '!', just add it as a token
4479 if (Parser.getTok().is(AsmToken::Exclaim)) {
4480 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4481 Parser.Lex(); // Eat the '!'.
4487 // The register offset is optionally preceded by a '+' or '-'
4488 bool isNegative = false;
4489 if (Parser.getTok().is(AsmToken::Minus)) {
4491 Parser.Lex(); // Eat the '-'.
4492 } else if (Parser.getTok().is(AsmToken::Plus)) {
4494 Parser.Lex(); // Eat the '+'.
4497 E = Parser.getTok().getLoc();
4498 int OffsetRegNum = tryParseRegister();
4499 if (OffsetRegNum == -1)
4500 return Error(E, "register expected");
4502 // If there's a shift operator, handle it.
4503 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4504 unsigned ShiftImm = 0;
4505 if (Parser.getTok().is(AsmToken::Comma)) {
4506 Parser.Lex(); // Eat the ','.
4507 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4511 // Now we should have the closing ']'
4512 if (Parser.getTok().isNot(AsmToken::RBrac))
4513 return Error(Parser.getTok().getLoc(), "']' expected");
4514 E = Parser.getTok().getEndLoc();
4515 Parser.Lex(); // Eat right bracket token.
4517 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4518 ShiftType, ShiftImm, 0, isNegative,
4521 // If there's a pre-indexing writeback marker, '!', just add it as a token
4523 if (Parser.getTok().is(AsmToken::Exclaim)) {
4524 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4525 Parser.Lex(); // Eat the '!'.
4531 /// parseMemRegOffsetShift - one of these two:
4532 /// ( lsl | lsr | asr | ror ) , # shift_amount
4534 /// return true if it parses a shift otherwise it returns false.
4535 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4537 SMLoc Loc = Parser.getTok().getLoc();
4538 const AsmToken &Tok = Parser.getTok();
4539 if (Tok.isNot(AsmToken::Identifier))
4541 StringRef ShiftName = Tok.getString();
4542 if (ShiftName == "lsl" || ShiftName == "LSL" ||
4543 ShiftName == "asl" || ShiftName == "ASL")
4545 else if (ShiftName == "lsr" || ShiftName == "LSR")
4547 else if (ShiftName == "asr" || ShiftName == "ASR")
4549 else if (ShiftName == "ror" || ShiftName == "ROR")
4551 else if (ShiftName == "rrx" || ShiftName == "RRX")
4554 return Error(Loc, "illegal shift operator");
4555 Parser.Lex(); // Eat shift type token.
4557 // rrx stands alone.
4559 if (St != ARM_AM::rrx) {
4560 Loc = Parser.getTok().getLoc();
4561 // A '#' and a shift amount.
4562 const AsmToken &HashTok = Parser.getTok();
4563 if (HashTok.isNot(AsmToken::Hash) &&
4564 HashTok.isNot(AsmToken::Dollar))
4565 return Error(HashTok.getLoc(), "'#' expected");
4566 Parser.Lex(); // Eat hash token.
4569 if (getParser().parseExpression(Expr))
4571 // Range check the immediate.
4572 // lsl, ror: 0 <= imm <= 31
4573 // lsr, asr: 0 <= imm <= 32
4574 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4576 return Error(Loc, "shift amount must be an immediate");
4577 int64_t Imm = CE->getValue();
4579 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4580 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4581 return Error(Loc, "immediate shift value out of range");
4582 // If <ShiftTy> #0, turn it into a no_shift.
4585 // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4594 /// parseFPImm - A floating point immediate expression operand.
4595 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4596 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4597 // Anything that can accept a floating point constant as an operand
4598 // needs to go through here, as the regular parseExpression is
4601 // This routine still creates a generic Immediate operand, containing
4602 // a bitcast of the 64-bit floating point value. The various operands
4603 // that accept floats can check whether the value is valid for them
4604 // via the standard is*() predicates.
4606 SMLoc S = Parser.getTok().getLoc();
4608 if (Parser.getTok().isNot(AsmToken::Hash) &&
4609 Parser.getTok().isNot(AsmToken::Dollar))
4610 return MatchOperand_NoMatch;
4612 // Disambiguate the VMOV forms that can accept an FP immediate.
4613 // vmov.f32 <sreg>, #imm
4614 // vmov.f64 <dreg>, #imm
4615 // vmov.f32 <dreg>, #imm @ vector f32x2
4616 // vmov.f32 <qreg>, #imm @ vector f32x4
4618 // There are also the NEON VMOV instructions which expect an
4619 // integer constant. Make sure we don't try to parse an FPImm
4621 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4622 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4623 if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
4624 TyOp->getToken() != ".f64"))
4625 return MatchOperand_NoMatch;
4627 Parser.Lex(); // Eat '#' or '$'.
4629 // Handle negation, as that still comes through as a separate token.
4630 bool isNegative = false;
4631 if (Parser.getTok().is(AsmToken::Minus)) {
4635 const AsmToken &Tok = Parser.getTok();
4636 SMLoc Loc = Tok.getLoc();
4637 if (Tok.is(AsmToken::Real)) {
4638 APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4639 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4640 // If we had a '-' in front, toggle the sign bit.
4641 IntVal ^= (uint64_t)isNegative << 31;
4642 Parser.Lex(); // Eat the token.
4643 Operands.push_back(ARMOperand::CreateImm(
4644 MCConstantExpr::Create(IntVal, getContext()),
4645 S, Parser.getTok().getLoc()));
4646 return MatchOperand_Success;
4648 // Also handle plain integers. Instructions which allow floating point
4649 // immediates also allow a raw encoded 8-bit value.
4650 if (Tok.is(AsmToken::Integer)) {
4651 int64_t Val = Tok.getIntVal();
4652 Parser.Lex(); // Eat the token.
4653 if (Val > 255 || Val < 0) {
4654 Error(Loc, "encoded floating point value out of range");
4655 return MatchOperand_ParseFail;
4657 double RealVal = ARM_AM::getFPImmFloat(Val);
4658 Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue();
4659 Operands.push_back(ARMOperand::CreateImm(
4660 MCConstantExpr::Create(Val, getContext()), S,
4661 Parser.getTok().getLoc()));
4662 return MatchOperand_Success;
4665 Error(Loc, "invalid floating point immediate");
4666 return MatchOperand_ParseFail;
4669 /// Parse a arm instruction operand. For now this parses the operand regardless
4670 /// of the mnemonic.
4671 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4672 StringRef Mnemonic) {
4675 // Check if the current operand has a custom associated parser, if so, try to
4676 // custom parse the operand, or fallback to the general approach.
4677 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4678 if (ResTy == MatchOperand_Success)
4680 // If there wasn't a custom match, try the generic matcher below. Otherwise,
4681 // there was a match, but an error occurred, in which case, just return that
4682 // the operand parsing failed.
4683 if (ResTy == MatchOperand_ParseFail)
4686 switch (getLexer().getKind()) {
4688 Error(Parser.getTok().getLoc(), "unexpected token in operand");
4690 case AsmToken::Identifier: {
4691 // If we've seen a branch mnemonic, the next operand must be a label. This
4692 // is true even if the label is a register name. So "br r1" means branch to
4694 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
4696 if (!tryParseRegisterWithWriteBack(Operands))
4698 int Res = tryParseShiftRegister(Operands);
4699 if (Res == 0) // success
4701 else if (Res == -1) // irrecoverable error
4703 // If this is VMRS, check for the apsr_nzcv operand.
4704 if (Mnemonic == "vmrs" &&
4705 Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4706 S = Parser.getTok().getLoc();
4708 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4713 // Fall though for the Identifier case that is not a register or a
4716 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
4717 case AsmToken::Integer: // things like 1f and 2b as a branch targets
4718 case AsmToken::String: // quoted label names.
4719 case AsmToken::Dot: { // . as a branch target
4720 // This was not a register so parse other operands that start with an
4721 // identifier (like labels) as expressions and create them as immediates.
4722 const MCExpr *IdVal;
4723 S = Parser.getTok().getLoc();
4724 if (getParser().parseExpression(IdVal))
4726 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4727 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4730 case AsmToken::LBrac:
4731 return parseMemory(Operands);
4732 case AsmToken::LCurly:
4733 return parseRegisterList(Operands);
4734 case AsmToken::Dollar:
4735 case AsmToken::Hash: {
4736 // #42 -> immediate.
4737 S = Parser.getTok().getLoc();
4740 if (Parser.getTok().isNot(AsmToken::Colon)) {
4741 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4742 const MCExpr *ImmVal;
4743 if (getParser().parseExpression(ImmVal))
4745 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4747 int32_t Val = CE->getValue();
4748 if (isNegative && Val == 0)
4749 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4751 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4752 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4754 // There can be a trailing '!' on operands that we want as a separate
4755 // '!' Token operand. Handle that here. For example, the compatibility
4756 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
4757 if (Parser.getTok().is(AsmToken::Exclaim)) {
4758 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
4759 Parser.getTok().getLoc()));
4760 Parser.Lex(); // Eat exclaim token
4764 // w/ a ':' after the '#', it's just like a plain ':'.
4767 case AsmToken::Colon: {
4768 // ":lower16:" and ":upper16:" expression prefixes
4769 // FIXME: Check it's an expression prefix,
4770 // e.g. (FOO - :lower16:BAR) isn't legal.
4771 ARMMCExpr::VariantKind RefKind;
4772 if (parsePrefix(RefKind))
4775 const MCExpr *SubExprVal;
4776 if (getParser().parseExpression(SubExprVal))
4779 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4781 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4782 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4785 case AsmToken::Equal: {
4786 if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
4787 return Error(Parser.getTok().getLoc(), "unexpected token in operand");
4789 const MCSection *Section =
4790 getParser().getStreamer().getCurrentSection().first;
4792 Parser.Lex(); // Eat '='
4793 const MCExpr *SubExprVal;
4794 if (getParser().parseExpression(SubExprVal))
4796 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4798 const MCExpr *CPLoc =
4799 getOrCreateConstantPool(Section).addEntry(SubExprVal, getContext());
4800 Operands.push_back(ARMOperand::CreateImm(CPLoc, S, E));
4806 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4807 // :lower16: and :upper16:.
4808 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4809 RefKind = ARMMCExpr::VK_ARM_None;
4811 // :lower16: and :upper16: modifiers
4812 assert(getLexer().is(AsmToken::Colon) && "expected a :");
4813 Parser.Lex(); // Eat ':'
4815 if (getLexer().isNot(AsmToken::Identifier)) {
4816 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4820 StringRef IDVal = Parser.getTok().getIdentifier();
4821 if (IDVal == "lower16") {
4822 RefKind = ARMMCExpr::VK_ARM_LO16;
4823 } else if (IDVal == "upper16") {
4824 RefKind = ARMMCExpr::VK_ARM_HI16;
4826 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4831 if (getLexer().isNot(AsmToken::Colon)) {
4832 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4835 Parser.Lex(); // Eat the last ':'
4839 /// \brief Given a mnemonic, split out possible predication code and carry
4840 /// setting letters to form a canonical mnemonic and flags.
4842 // FIXME: Would be nice to autogen this.
4843 // FIXME: This is a bit of a maze of special cases.
4844 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4845 unsigned &PredicationCode,
4847 unsigned &ProcessorIMod,
4848 StringRef &ITMask) {
4849 PredicationCode = ARMCC::AL;
4850 CarrySetting = false;
4853 // Ignore some mnemonics we know aren't predicated forms.
4855 // FIXME: Would be nice to autogen this.
4856 if ((Mnemonic == "movs" && isThumb()) ||
4857 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
4858 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
4859 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
4860 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
4861 Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" ||
4862 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
4863 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
4864 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4865 Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
4866 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" ||
4867 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
4868 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel"))
4871 // First, split out any predication code. Ignore mnemonics we know aren't
4872 // predicated but do have a carry-set and so weren't caught above.
4873 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4874 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4875 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4876 Mnemonic != "sbcs" && Mnemonic != "rscs") {
4877 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4878 .Case("eq", ARMCC::EQ)
4879 .Case("ne", ARMCC::NE)
4880 .Case("hs", ARMCC::HS)
4881 .Case("cs", ARMCC::HS)
4882 .Case("lo", ARMCC::LO)
4883 .Case("cc", ARMCC::LO)
4884 .Case("mi", ARMCC::MI)
4885 .Case("pl", ARMCC::PL)
4886 .Case("vs", ARMCC::VS)
4887 .Case("vc", ARMCC::VC)
4888 .Case("hi", ARMCC::HI)
4889 .Case("ls", ARMCC::LS)
4890 .Case("ge", ARMCC::GE)
4891 .Case("lt", ARMCC::LT)
4892 .Case("gt", ARMCC::GT)
4893 .Case("le", ARMCC::LE)
4894 .Case("al", ARMCC::AL)
4897 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4898 PredicationCode = CC;
4902 // Next, determine if we have a carry setting bit. We explicitly ignore all
4903 // the instructions we know end in 's'.
4904 if (Mnemonic.endswith("s") &&
4905 !(Mnemonic == "cps" || Mnemonic == "mls" ||
4906 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4907 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4908 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4909 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4910 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4911 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4912 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
4913 Mnemonic == "vfms" || Mnemonic == "vfnms" ||
4914 (Mnemonic == "movs" && isThumb()))) {
4915 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4916 CarrySetting = true;
4919 // The "cps" instruction can have a interrupt mode operand which is glued into
4920 // the mnemonic. Check if this is the case, split it and parse the imod op
4921 if (Mnemonic.startswith("cps")) {
4922 // Split out any imod code.
4924 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4925 .Case("ie", ARM_PROC::IE)
4926 .Case("id", ARM_PROC::ID)
4929 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4930 ProcessorIMod = IMod;
4934 // The "it" instruction has the condition mask on the end of the mnemonic.
4935 if (Mnemonic.startswith("it")) {
4936 ITMask = Mnemonic.slice(2, Mnemonic.size());
4937 Mnemonic = Mnemonic.slice(0, 2);
4943 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
4944 /// inclusion of carry set or predication code operands.
4946 // FIXME: It would be nice to autogen this.
4948 getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
4949 bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) {
4950 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4951 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4952 Mnemonic == "add" || Mnemonic == "adc" ||
4953 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4954 Mnemonic == "orr" || Mnemonic == "mvn" ||
4955 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4956 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4957 Mnemonic == "vfm" || Mnemonic == "vfnm" ||
4958 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4959 Mnemonic == "mla" || Mnemonic == "smlal" ||
4960 Mnemonic == "umlal" || Mnemonic == "umull"))) {
4961 CanAcceptCarrySet = true;
4963 CanAcceptCarrySet = false;
4965 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
4966 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
4967 Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic.startswith("crc32") ||
4968 Mnemonic.startswith("cps") || Mnemonic.startswith("vsel") ||
4969 Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
4970 Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
4971 Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
4972 Mnemonic == "vrintm" || Mnemonic.startswith("aes") ||
4973 Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
4974 (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) {
4975 // These mnemonics are never predicable
4976 CanAcceptPredicationCode = false;
4977 } else if (!isThumb()) {
4978 // Some instructions are only predicable in Thumb mode
4979 CanAcceptPredicationCode
4980 = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
4981 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
4982 Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
4983 Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
4984 Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
4985 Mnemonic != "stc2" && Mnemonic != "stc2l" &&
4986 !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
4987 } else if (isThumbOne()) {
4989 CanAcceptPredicationCode = Mnemonic != "movs";
4991 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
4993 CanAcceptPredicationCode = true;
4996 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4997 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4998 // FIXME: This is all horribly hacky. We really need a better way to deal
4999 // with optional operands like this in the matcher table.
5001 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
5002 // another does not. Specifically, the MOVW instruction does not. So we
5003 // special case it here and remove the defaulted (non-setting) cc_out
5004 // operand if that's the instruction we're trying to match.
5006 // We do this as post-processing of the explicit operands rather than just
5007 // conditionally adding the cc_out in the first place because we need
5008 // to check the type of the parsed immediate operand.
5009 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
5010 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
5011 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
5012 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
5015 // Register-register 'add' for thumb does not have a cc_out operand
5016 // when there are only two register operands.
5017 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
5018 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5019 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5020 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
5022 // Register-register 'add' for thumb does not have a cc_out operand
5023 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
5024 // have to check the immediate range here since Thumb2 has a variant
5025 // that can handle a different range and has a cc_out operand.
5026 if (((isThumb() && Mnemonic == "add") ||
5027 (isThumbTwo() && Mnemonic == "sub")) &&
5028 Operands.size() == 6 &&
5029 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5030 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5031 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
5032 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5033 ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
5034 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
5036 // For Thumb2, add/sub immediate does not have a cc_out operand for the
5037 // imm0_4095 variant. That's the least-preferred variant when
5038 // selecting via the generic "add" mnemonic, so to know that we
5039 // should remove the cc_out operand, we have to explicitly check that
5040 // it's not one of the other variants. Ugh.
5041 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
5042 Operands.size() == 6 &&
5043 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5044 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5045 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5046 // Nest conditions rather than one big 'if' statement for readability.
5048 // If both registers are low, we're in an IT block, and the immediate is
5049 // in range, we should use encoding T1 instead, which has a cc_out.
5051 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
5052 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
5053 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
5055 // Check against T3. If the second register is the PC, this is an
5056 // alternate form of ADR, which uses encoding T4, so check for that too.
5057 if (static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
5058 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
5061 // Otherwise, we use encoding T4, which does not have a cc_out
5066 // The thumb2 multiply instruction doesn't have a CCOut register, so
5067 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
5068 // use the 16-bit encoding or not.
5069 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5070 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5071 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5072 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5073 static_cast<ARMOperand*>(Operands[5])->isReg() &&
5074 // If the registers aren't low regs, the destination reg isn't the
5075 // same as one of the source regs, or the cc_out operand is zero
5076 // outside of an IT block, we have to use the 32-bit encoding, so
5077 // remove the cc_out operand.
5078 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
5079 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
5080 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
5082 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
5083 static_cast<ARMOperand*>(Operands[5])->getReg() &&
5084 static_cast<ARMOperand*>(Operands[3])->getReg() !=
5085 static_cast<ARMOperand*>(Operands[4])->getReg())))
5088 // Also check the 'mul' syntax variant that doesn't specify an explicit
5089 // destination register.
5090 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5091 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5092 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5093 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5094 // If the registers aren't low regs or the cc_out operand is zero
5095 // outside of an IT block, we have to use the 32-bit encoding, so
5096 // remove the cc_out operand.
5097 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
5098 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
5104 // Register-register 'add/sub' for thumb does not have a cc_out operand
5105 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5106 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
5107 // right, this will result in better diagnostics (which operand is off)
5109 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
5110 (Operands.size() == 5 || Operands.size() == 6) &&
5111 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5112 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
5113 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5114 (static_cast<ARMOperand*>(Operands[4])->isImm() ||
5115 (Operands.size() == 6 &&
5116 static_cast<ARMOperand*>(Operands[5])->isImm())))
5122 bool ARMAsmParser::shouldOmitPredicateOperand(
5123 StringRef Mnemonic, SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
5124 // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
5125 unsigned RegIdx = 3;
5126 if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
5127 static_cast<ARMOperand *>(Operands[2])->getToken() == ".f32") {
5128 if (static_cast<ARMOperand *>(Operands[3])->isToken() &&
5129 static_cast<ARMOperand *>(Operands[3])->getToken() == ".f32")
5132 if (static_cast<ARMOperand *>(Operands[RegIdx])->isReg() &&
5133 (ARMMCRegisterClasses[ARM::DPRRegClassID]
5134 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg()) ||
5135 ARMMCRegisterClasses[ARM::QPRRegClassID]
5136 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg())))
5142 static bool isDataTypeToken(StringRef Tok) {
5143 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5144 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5145 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5146 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5147 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5148 Tok == ".f" || Tok == ".d";
5151 // FIXME: This bit should probably be handled via an explicit match class
5152 // in the .td files that matches the suffix instead of having it be
5153 // a literal string token the way it is now.
5154 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5155 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5157 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
5158 unsigned VariantID);
5160 static bool RequiresVFPRegListValidation(StringRef Inst,
5161 bool &AcceptSinglePrecisionOnly,
5162 bool &AcceptDoublePrecisionOnly) {
5163 if (Inst.size() < 7)
5166 if (Inst.startswith("fldm") || Inst.startswith("fstm")) {
5167 StringRef AddressingMode = Inst.substr(4, 2);
5168 if (AddressingMode == "ia" || AddressingMode == "db" ||
5169 AddressingMode == "ea" || AddressingMode == "fd") {
5170 AcceptSinglePrecisionOnly = Inst[6] == 's';
5171 AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x';
5179 /// Parse an arm instruction mnemonic followed by its operands.
5180 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5182 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5183 // FIXME: Can this be done via tablegen in some fashion?
5184 bool RequireVFPRegisterListCheck;
5185 bool AcceptSinglePrecisionOnly;
5186 bool AcceptDoublePrecisionOnly;
5187 RequireVFPRegisterListCheck =
5188 RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly,
5189 AcceptDoublePrecisionOnly);
5191 // Apply mnemonic aliases before doing anything else, as the destination
5192 // mnemonic may include suffices and we want to handle them normally.
5193 // The generic tblgen'erated code does this later, at the start of
5194 // MatchInstructionImpl(), but that's too late for aliases that include
5195 // any sort of suffix.
5196 unsigned AvailableFeatures = getAvailableFeatures();
5197 unsigned AssemblerDialect = getParser().getAssemblerDialect();
5198 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5200 // First check for the ARM-specific .req directive.
5201 if (Parser.getTok().is(AsmToken::Identifier) &&
5202 Parser.getTok().getIdentifier() == ".req") {
5203 parseDirectiveReq(Name, NameLoc);
5204 // We always return 'error' for this, as we're done with this
5205 // statement and don't need to match the 'instruction."
5209 // Create the leading tokens for the mnemonic, split by '.' characters.
5210 size_t Start = 0, Next = Name.find('.');
5211 StringRef Mnemonic = Name.slice(Start, Next);
5213 // Split out the predication code and carry setting flag from the mnemonic.
5214 unsigned PredicationCode;
5215 unsigned ProcessorIMod;
5218 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5219 ProcessorIMod, ITMask);
5221 // In Thumb1, only the branch (B) instruction can be predicated.
5222 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5223 Parser.eatToEndOfStatement();
5224 return Error(NameLoc, "conditional execution not supported in Thumb1");
5227 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5229 // Handle the IT instruction ITMask. Convert it to a bitmask. This
5230 // is the mask as it will be for the IT encoding if the conditional
5231 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5232 // where the conditional bit0 is zero, the instruction post-processing
5233 // will adjust the mask accordingly.
5234 if (Mnemonic == "it") {
5235 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5236 if (ITMask.size() > 3) {
5237 Parser.eatToEndOfStatement();
5238 return Error(Loc, "too many conditions on IT instruction");
5241 for (unsigned i = ITMask.size(); i != 0; --i) {
5242 char pos = ITMask[i - 1];
5243 if (pos != 't' && pos != 'e') {
5244 Parser.eatToEndOfStatement();
5245 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5248 if (ITMask[i - 1] == 't')
5251 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5254 // FIXME: This is all a pretty gross hack. We should automatically handle
5255 // optional operands like this via tblgen.
5257 // Next, add the CCOut and ConditionCode operands, if needed.
5259 // For mnemonics which can ever incorporate a carry setting bit or predication
5260 // code, our matching model involves us always generating CCOut and
5261 // ConditionCode operands to match the mnemonic "as written" and then we let
5262 // the matcher deal with finding the right instruction or generating an
5263 // appropriate error.
5264 bool CanAcceptCarrySet, CanAcceptPredicationCode;
5265 getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
5267 // If we had a carry-set on an instruction that can't do that, issue an
5269 if (!CanAcceptCarrySet && CarrySetting) {
5270 Parser.eatToEndOfStatement();
5271 return Error(NameLoc, "instruction '" + Mnemonic +
5272 "' can not set flags, but 's' suffix specified");
5274 // If we had a predication code on an instruction that can't do that, issue an
5276 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5277 Parser.eatToEndOfStatement();
5278 return Error(NameLoc, "instruction '" + Mnemonic +
5279 "' is not predicable, but condition code specified");
5282 // Add the carry setting operand, if necessary.
5283 if (CanAcceptCarrySet) {
5284 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5285 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5289 // Add the predication code operand, if necessary.
5290 if (CanAcceptPredicationCode) {
5291 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5293 Operands.push_back(ARMOperand::CreateCondCode(
5294 ARMCC::CondCodes(PredicationCode), Loc));
5297 // Add the processor imod operand, if necessary.
5298 if (ProcessorIMod) {
5299 Operands.push_back(ARMOperand::CreateImm(
5300 MCConstantExpr::Create(ProcessorIMod, getContext()),
5304 // Add the remaining tokens in the mnemonic.
5305 while (Next != StringRef::npos) {
5307 Next = Name.find('.', Start + 1);
5308 StringRef ExtraToken = Name.slice(Start, Next);
5310 // Some NEON instructions have an optional datatype suffix that is
5311 // completely ignored. Check for that.
5312 if (isDataTypeToken(ExtraToken) &&
5313 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5316 // For for ARM mode generate an error if the .n qualifier is used.
5317 if (ExtraToken == ".n" && !isThumb()) {
5318 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5319 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5323 // The .n qualifier is always discarded as that is what the tables
5324 // and matcher expect. In ARM mode the .w qualifier has no effect,
5325 // so discard it to avoid errors that can be caused by the matcher.
5326 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5327 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5328 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5332 // Read the remaining operands.
5333 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5334 // Read the first operand.
5335 if (parseOperand(Operands, Mnemonic)) {
5336 Parser.eatToEndOfStatement();
5340 while (getLexer().is(AsmToken::Comma)) {
5341 Parser.Lex(); // Eat the comma.
5343 // Parse and remember the operand.
5344 if (parseOperand(Operands, Mnemonic)) {
5345 Parser.eatToEndOfStatement();
5351 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5352 SMLoc Loc = getLexer().getLoc();
5353 Parser.eatToEndOfStatement();
5354 return Error(Loc, "unexpected token in argument list");
5357 Parser.Lex(); // Consume the EndOfStatement
5359 if (RequireVFPRegisterListCheck) {
5360 ARMOperand *Op = static_cast<ARMOperand*>(Operands.back());
5361 if (AcceptSinglePrecisionOnly && !Op->isSPRRegList())
5362 return Error(Op->getStartLoc(),
5363 "VFP/Neon single precision register expected");
5364 if (AcceptDoublePrecisionOnly && !Op->isDPRRegList())
5365 return Error(Op->getStartLoc(),
5366 "VFP/Neon double precision register expected");
5369 // Some instructions, mostly Thumb, have forms for the same mnemonic that
5370 // do and don't have a cc_out optional-def operand. With some spot-checks
5371 // of the operand list, we can figure out which variant we're trying to
5372 // parse and adjust accordingly before actually matching. We shouldn't ever
5373 // try to remove a cc_out operand that was explicitly set on the the
5374 // mnemonic, of course (CarrySetting == true). Reason number #317 the
5375 // table driven matcher doesn't fit well with the ARM instruction set.
5376 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5377 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5378 Operands.erase(Operands.begin() + 1);
5382 // Some instructions have the same mnemonic, but don't always
5383 // have a predicate. Distinguish them here and delete the
5384 // predicate if needed.
5385 if (shouldOmitPredicateOperand(Mnemonic, Operands)) {
5386 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5387 Operands.erase(Operands.begin() + 1);
5391 // ARM mode 'blx' need special handling, as the register operand version
5392 // is predicable, but the label operand version is not. So, we can't rely
5393 // on the Mnemonic based checking to correctly figure out when to put
5394 // a k_CondCode operand in the list. If we're trying to match the label
5395 // version, remove the k_CondCode operand here.
5396 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5397 static_cast<ARMOperand*>(Operands[2])->isImm()) {
5398 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5399 Operands.erase(Operands.begin() + 1);
5403 // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5404 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5405 // a single GPRPair reg operand is used in the .td file to replace the two
5406 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5407 // expressed as a GPRPair, so we have to manually merge them.
5408 // FIXME: We would really like to be able to tablegen'erate this.
5409 if (!isThumb() && Operands.size() > 4 &&
5410 (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
5411 Mnemonic == "stlexd")) {
5412 bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
5413 unsigned Idx = isLoad ? 2 : 3;
5414 ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]);
5415 ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]);
5417 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5418 // Adjust only if Op1 and Op2 are GPRs.
5419 if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) &&
5420 MRC.contains(Op2->getReg())) {
5421 unsigned Reg1 = Op1->getReg();
5422 unsigned Reg2 = Op2->getReg();
5423 unsigned Rt = MRI->getEncodingValue(Reg1);
5424 unsigned Rt2 = MRI->getEncodingValue(Reg2);
5426 // Rt2 must be Rt + 1 and Rt must be even.
5427 if (Rt + 1 != Rt2 || (Rt & 1)) {
5428 Error(Op2->getStartLoc(), isLoad ?
5429 "destination operands must be sequential" :
5430 "source operands must be sequential");
5433 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5434 &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5435 Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2);
5436 Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg(
5437 NewReg, Op1->getStartLoc(), Op2->getEndLoc()));
5443 // FIXME: As said above, this is all a pretty gross hack. This instruction
5444 // does not fit with other "subs" and tblgen.
5445 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
5446 // so the Mnemonic is the original name "subs" and delete the predicate
5447 // operand so it will match the table entry.
5448 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
5449 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5450 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::PC &&
5451 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5452 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::LR &&
5453 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5454 ARMOperand *Op0 = static_cast<ARMOperand*>(Operands[0]);
5455 Operands.erase(Operands.begin());
5457 Operands.insert(Operands.begin(), ARMOperand::CreateToken(Name, NameLoc));
5459 ARMOperand *Op1 = static_cast<ARMOperand*>(Operands[1]);
5460 Operands.erase(Operands.begin() + 1);
5466 // Validate context-sensitive operand constraints.
5468 // return 'true' if register list contains non-low GPR registers,
5469 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5470 // 'containsReg' to true.
5471 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5472 unsigned HiReg, bool &containsReg) {
5473 containsReg = false;
5474 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5475 unsigned OpReg = Inst.getOperand(i).getReg();
5478 // Anything other than a low register isn't legal here.
5479 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5485 // Check if the specified regisgter is in the register list of the inst,
5486 // starting at the indicated operand number.
5487 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5488 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5489 unsigned OpReg = Inst.getOperand(i).getReg();
5496 // Return true if instruction has the interesting property of being
5497 // allowed in IT blocks, but not being predicable.
5498 static bool instIsBreakpoint(const MCInst &Inst) {
5499 return Inst.getOpcode() == ARM::tBKPT ||
5500 Inst.getOpcode() == ARM::BKPT ||
5501 Inst.getOpcode() == ARM::tHLT ||
5502 Inst.getOpcode() == ARM::HLT;
5506 // FIXME: We would really like to be able to tablegen'erate this.
5508 validateInstruction(MCInst &Inst,
5509 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5510 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
5511 SMLoc Loc = Operands[0]->getStartLoc();
5513 // Check the IT block state first.
5514 // NOTE: BKPT and HLT instructions have the interesting property of being
5515 // allowed in IT blocks, but not being predicable. They just always execute.
5516 if (inITBlock() && !instIsBreakpoint(Inst)) {
5518 if (ITState.FirstCond)
5519 ITState.FirstCond = false;
5521 Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5522 // The instruction must be predicable.
5523 if (!MCID.isPredicable())
5524 return Error(Loc, "instructions in IT block must be predicable");
5525 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5526 unsigned ITCond = Bit ? ITState.Cond :
5527 ARMCC::getOppositeCondition(ITState.Cond);
5528 if (Cond != ITCond) {
5529 // Find the condition code Operand to get its SMLoc information.
5531 for (unsigned I = 1; I < Operands.size(); ++I)
5532 if (static_cast<ARMOperand*>(Operands[I])->isCondCode())
5533 CondLoc = Operands[I]->getStartLoc();
5534 return Error(CondLoc, "incorrect condition in IT block; got '" +
5535 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5536 "', but expected '" +
5537 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5539 // Check for non-'al' condition codes outside of the IT block.
5540 } else if (isThumbTwo() && MCID.isPredicable() &&
5541 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5542 ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
5543 Inst.getOpcode() != ARM::t2Bcc)
5544 return Error(Loc, "predicated instructions must be in IT block");
5546 const unsigned Opcode = Inst.getOpcode();
5550 case ARM::LDRD_POST: {
5551 const unsigned RtReg = Inst.getOperand(0).getReg();
5554 if (RtReg == ARM::LR)
5555 return Error(Operands[3]->getStartLoc(),
5558 const unsigned Rt = MRI->getEncodingValue(RtReg);
5559 // Rt must be even-numbered.
5561 return Error(Operands[3]->getStartLoc(),
5562 "Rt must be even-numbered");
5564 // Rt2 must be Rt + 1.
5565 const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5567 return Error(Operands[3]->getStartLoc(),
5568 "destination operands must be sequential");
5570 if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) {
5571 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
5572 // For addressing modes with writeback, the base register needs to be
5573 // different from the destination registers.
5574 if (Rn == Rt || Rn == Rt2)
5575 return Error(Operands[3]->getStartLoc(),
5576 "base register needs to be different from destination "
5583 case ARM::t2LDRD_PRE:
5584 case ARM::t2LDRD_POST: {
5585 // Rt2 must be different from Rt.
5586 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5587 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5589 return Error(Operands[3]->getStartLoc(),
5590 "destination operands can't be identical");
5594 // Rt2 must be Rt + 1.
5595 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5596 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5598 return Error(Operands[3]->getStartLoc(),
5599 "source operands must be sequential");
5603 case ARM::STRD_POST: {
5604 // Rt2 must be Rt + 1.
5605 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5606 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5608 return Error(Operands[3]->getStartLoc(),
5609 "source operands must be sequential");
5614 // Width must be in range [1, 32-lsb].
5615 unsigned LSB = Inst.getOperand(2).getImm();
5616 unsigned Widthm1 = Inst.getOperand(3).getImm();
5617 if (Widthm1 >= 32 - LSB)
5618 return Error(Operands[5]->getStartLoc(),
5619 "bitfield width must be in range [1,32-lsb]");
5622 // Notionally handles ARM::tLDMIA_UPD too.
5624 // If we're parsing Thumb2, the .w variant is available and handles
5625 // most cases that are normally illegal for a Thumb1 LDM instruction.
5626 // We'll make the transformation in processInstruction() if necessary.
5628 // Thumb LDM instructions are writeback iff the base register is not
5629 // in the register list.
5630 unsigned Rn = Inst.getOperand(0).getReg();
5631 bool HasWritebackToken =
5632 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5633 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5634 bool ListContainsBase;
5635 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
5636 return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
5637 "registers must be in range r0-r7");
5638 // If we should have writeback, then there should be a '!' token.
5639 if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
5640 return Error(Operands[2]->getStartLoc(),
5641 "writeback operator '!' expected");
5642 // If we should not have writeback, there must not be a '!'. This is
5643 // true even for the 32-bit wide encodings.
5644 if (ListContainsBase && HasWritebackToken)
5645 return Error(Operands[3]->getStartLoc(),
5646 "writeback operator '!' not allowed when base register "
5647 "in register list");
5651 case ARM::LDMIA_UPD:
5652 case ARM::LDMDB_UPD:
5653 case ARM::LDMIB_UPD:
5654 case ARM::LDMDA_UPD:
5655 // ARM variants loading and updating the same register are only officially
5656 // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
5660 case ARM::t2LDMIA_UPD:
5661 case ARM::t2LDMDB_UPD:
5662 case ARM::t2STMIA_UPD:
5663 case ARM::t2STMDB_UPD: {
5664 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5665 return Error(Operands.back()->getStartLoc(),
5666 "writeback register not allowed in register list");
5669 case ARM::sysLDMIA_UPD:
5670 case ARM::sysLDMDA_UPD:
5671 case ARM::sysLDMDB_UPD:
5672 case ARM::sysLDMIB_UPD:
5673 if (!listContainsReg(Inst, 3, ARM::PC))
5674 return Error(Operands[4]->getStartLoc(),
5675 "writeback register only allowed on system LDM "
5676 "if PC in register-list");
5678 case ARM::sysSTMIA_UPD:
5679 case ARM::sysSTMDA_UPD:
5680 case ARM::sysSTMDB_UPD:
5681 case ARM::sysSTMIB_UPD:
5682 return Error(Operands[2]->getStartLoc(),
5683 "system STM cannot have writeback register");
5686 // The second source operand must be the same register as the destination
5689 // In this case, we must directly check the parsed operands because the
5690 // cvtThumbMultiply() function is written in such a way that it guarantees
5691 // this first statement is always true for the new Inst. Essentially, the
5692 // destination is unconditionally copied into the second source operand
5693 // without checking to see if it matches what we actually parsed.
5694 if (Operands.size() == 6 &&
5695 (((ARMOperand*)Operands[3])->getReg() !=
5696 ((ARMOperand*)Operands[5])->getReg()) &&
5697 (((ARMOperand*)Operands[3])->getReg() !=
5698 ((ARMOperand*)Operands[4])->getReg())) {
5699 return Error(Operands[3]->getStartLoc(),
5700 "destination register must match source register");
5704 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5705 // so only issue a diagnostic for thumb1. The instructions will be
5706 // switched to the t2 encodings in processInstruction() if necessary.
5708 bool ListContainsBase;
5709 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
5711 return Error(Operands[2]->getStartLoc(),
5712 "registers must be in range r0-r7 or pc");
5716 bool ListContainsBase;
5717 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
5719 return Error(Operands[2]->getStartLoc(),
5720 "registers must be in range r0-r7 or lr");
5723 case ARM::tSTMIA_UPD: {
5724 bool ListContainsBase, InvalidLowList;
5725 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
5726 0, ListContainsBase);
5727 if (InvalidLowList && !isThumbTwo())
5728 return Error(Operands[4]->getStartLoc(),
5729 "registers must be in range r0-r7");
5731 // This would be converted to a 32-bit stm, but that's not valid if the
5732 // writeback register is in the list.
5733 if (InvalidLowList && ListContainsBase)
5734 return Error(Operands[4]->getStartLoc(),
5735 "writeback operator '!' not allowed when base register "
5736 "in register list");
5739 case ARM::tADDrSP: {
5740 // If the non-SP source operand and the destination operand are not the
5741 // same, we need thumb2 (for the wide encoding), or we have an error.
5742 if (!isThumbTwo() &&
5743 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5744 return Error(Operands[4]->getStartLoc(),
5745 "source register must be the same as destination");
5749 // Final range checking for Thumb unconditional branch instructions.
5751 if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<11, 1>())
5752 return Error(Operands[2]->getStartLoc(), "branch target out of range");
5755 int op = (Operands[2]->isImm()) ? 2 : 3;
5756 if (!(static_cast<ARMOperand*>(Operands[op]))->isSignedOffset<24, 1>())
5757 return Error(Operands[op]->getStartLoc(), "branch target out of range");
5760 // Final range checking for Thumb conditional branch instructions.
5762 if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<8, 1>())
5763 return Error(Operands[2]->getStartLoc(), "branch target out of range");
5766 int Op = (Operands[2]->isImm()) ? 2 : 3;
5767 if (!(static_cast<ARMOperand*>(Operands[Op]))->isSignedOffset<20, 1>())
5768 return Error(Operands[Op]->getStartLoc(), "branch target out of range");
5776 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5778 default: llvm_unreachable("unexpected opcode!");
5780 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5781 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5782 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5783 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5784 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5785 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5786 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
5787 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5788 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5791 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5792 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5793 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5794 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5795 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5797 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5798 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5799 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5800 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5801 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5803 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
5804 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5805 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5806 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5807 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5810 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5811 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5812 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5813 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5814 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5815 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5816 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5817 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5818 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5819 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5820 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
5821 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5822 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5823 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5824 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5827 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5828 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5829 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5830 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5831 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5832 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5833 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5834 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5835 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5836 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5837 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5838 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5839 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
5840 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5841 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5842 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
5843 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5844 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5847 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5848 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5849 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5850 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5851 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5852 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5853 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5854 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5855 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5856 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5857 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
5858 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5859 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5860 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5861 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5864 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5865 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5866 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5867 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5868 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5869 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5870 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5871 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5872 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5873 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5874 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5875 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5876 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
5877 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5878 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5879 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
5880 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5881 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5885 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
5887 default: llvm_unreachable("unexpected opcode!");
5889 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5890 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5891 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5892 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5893 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5894 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5895 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
5896 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5897 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5900 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5901 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5902 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5903 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5904 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5905 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5906 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5907 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5908 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5909 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5910 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
5911 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5912 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5913 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5914 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5917 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5918 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5919 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5920 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5921 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5922 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5923 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5924 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5925 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5926 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5927 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5928 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5929 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
5930 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5931 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5932 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5933 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5934 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5937 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5938 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5939 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5940 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5941 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5942 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5943 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5944 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5945 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5946 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5947 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
5948 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5949 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5950 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5951 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5954 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5955 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5956 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5957 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5958 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5959 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5960 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5961 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5962 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5963 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5964 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5965 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5966 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
5967 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5968 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5969 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
5970 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5971 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
5974 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5975 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5976 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5977 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
5978 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5979 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5980 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5981 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5982 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5983 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5984 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
5985 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5986 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5987 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5988 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5991 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5992 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5993 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5994 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5995 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5996 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5997 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5998 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5999 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6000 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
6001 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
6002 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6003 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
6004 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
6005 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
6006 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
6007 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
6008 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
6011 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
6012 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6013 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6014 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
6015 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6016 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6017 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
6018 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6019 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6020 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
6021 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6022 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6023 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
6024 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
6025 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
6026 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
6027 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
6028 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
6033 processInstruction(MCInst &Inst,
6034 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
6035 switch (Inst.getOpcode()) {
6036 // Alias for alternate form of 'ADR Rd, #imm' instruction.
6038 if (Inst.getOperand(1).getReg() != ARM::PC ||
6039 Inst.getOperand(5).getReg() != 0)
6042 TmpInst.setOpcode(ARM::ADR);
6043 TmpInst.addOperand(Inst.getOperand(0));
6044 TmpInst.addOperand(Inst.getOperand(2));
6045 TmpInst.addOperand(Inst.getOperand(3));
6046 TmpInst.addOperand(Inst.getOperand(4));
6050 // Aliases for alternate PC+imm syntax of LDR instructions.
6051 case ARM::t2LDRpcrel:
6052 // Select the narrow version if the immediate will fit.
6053 if (Inst.getOperand(1).getImm() > 0 &&
6054 Inst.getOperand(1).getImm() <= 0xff &&
6055 !(static_cast<ARMOperand*>(Operands[2])->isToken() &&
6056 static_cast<ARMOperand*>(Operands[2])->getToken() == ".w"))
6057 Inst.setOpcode(ARM::tLDRpci);
6059 Inst.setOpcode(ARM::t2LDRpci);
6061 case ARM::t2LDRBpcrel:
6062 Inst.setOpcode(ARM::t2LDRBpci);
6064 case ARM::t2LDRHpcrel:
6065 Inst.setOpcode(ARM::t2LDRHpci);
6067 case ARM::t2LDRSBpcrel:
6068 Inst.setOpcode(ARM::t2LDRSBpci);
6070 case ARM::t2LDRSHpcrel:
6071 Inst.setOpcode(ARM::t2LDRSHpci);
6073 // Handle NEON VST complex aliases.
6074 case ARM::VST1LNdWB_register_Asm_8:
6075 case ARM::VST1LNdWB_register_Asm_16:
6076 case ARM::VST1LNdWB_register_Asm_32: {
6078 // Shuffle the operands around so the lane index operand is in the
6081 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6082 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6083 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6084 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6085 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6086 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6087 TmpInst.addOperand(Inst.getOperand(1)); // lane
6088 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6089 TmpInst.addOperand(Inst.getOperand(6));
6094 case ARM::VST2LNdWB_register_Asm_8:
6095 case ARM::VST2LNdWB_register_Asm_16:
6096 case ARM::VST2LNdWB_register_Asm_32:
6097 case ARM::VST2LNqWB_register_Asm_16:
6098 case ARM::VST2LNqWB_register_Asm_32: {
6100 // Shuffle the operands around so the lane index operand is in the
6103 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6104 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6105 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6106 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6107 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6108 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6109 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6111 TmpInst.addOperand(Inst.getOperand(1)); // lane
6112 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6113 TmpInst.addOperand(Inst.getOperand(6));
6118 case ARM::VST3LNdWB_register_Asm_8:
6119 case ARM::VST3LNdWB_register_Asm_16:
6120 case ARM::VST3LNdWB_register_Asm_32:
6121 case ARM::VST3LNqWB_register_Asm_16:
6122 case ARM::VST3LNqWB_register_Asm_32: {
6124 // Shuffle the operands around so the lane index operand is in the
6127 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6128 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6129 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6130 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6131 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6132 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6133 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6135 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6137 TmpInst.addOperand(Inst.getOperand(1)); // lane
6138 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6139 TmpInst.addOperand(Inst.getOperand(6));
6144 case ARM::VST4LNdWB_register_Asm_8:
6145 case ARM::VST4LNdWB_register_Asm_16:
6146 case ARM::VST4LNdWB_register_Asm_32:
6147 case ARM::VST4LNqWB_register_Asm_16:
6148 case ARM::VST4LNqWB_register_Asm_32: {
6150 // Shuffle the operands around so the lane index operand is in the
6153 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6154 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6155 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6156 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6157 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6158 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6159 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6161 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6163 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6165 TmpInst.addOperand(Inst.getOperand(1)); // lane
6166 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6167 TmpInst.addOperand(Inst.getOperand(6));
6172 case ARM::VST1LNdWB_fixed_Asm_8:
6173 case ARM::VST1LNdWB_fixed_Asm_16:
6174 case ARM::VST1LNdWB_fixed_Asm_32: {
6176 // Shuffle the operands around so the lane index operand is in the
6179 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6180 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6181 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6182 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6183 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6184 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6185 TmpInst.addOperand(Inst.getOperand(1)); // lane
6186 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6187 TmpInst.addOperand(Inst.getOperand(5));
6192 case ARM::VST2LNdWB_fixed_Asm_8:
6193 case ARM::VST2LNdWB_fixed_Asm_16:
6194 case ARM::VST2LNdWB_fixed_Asm_32:
6195 case ARM::VST2LNqWB_fixed_Asm_16:
6196 case ARM::VST2LNqWB_fixed_Asm_32: {
6198 // Shuffle the operands around so the lane index operand is in the
6201 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6202 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6203 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6204 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6205 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6206 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6207 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6209 TmpInst.addOperand(Inst.getOperand(1)); // lane
6210 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6211 TmpInst.addOperand(Inst.getOperand(5));
6216 case ARM::VST3LNdWB_fixed_Asm_8:
6217 case ARM::VST3LNdWB_fixed_Asm_16:
6218 case ARM::VST3LNdWB_fixed_Asm_32:
6219 case ARM::VST3LNqWB_fixed_Asm_16:
6220 case ARM::VST3LNqWB_fixed_Asm_32: {
6222 // Shuffle the operands around so the lane index operand is in the
6225 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6226 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6227 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6228 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6229 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6230 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6231 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6233 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6235 TmpInst.addOperand(Inst.getOperand(1)); // lane
6236 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6237 TmpInst.addOperand(Inst.getOperand(5));
6242 case ARM::VST4LNdWB_fixed_Asm_8:
6243 case ARM::VST4LNdWB_fixed_Asm_16:
6244 case ARM::VST4LNdWB_fixed_Asm_32:
6245 case ARM::VST4LNqWB_fixed_Asm_16:
6246 case ARM::VST4LNqWB_fixed_Asm_32: {
6248 // Shuffle the operands around so the lane index operand is in the
6251 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6252 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6253 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6254 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6255 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6256 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6257 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6259 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6261 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6263 TmpInst.addOperand(Inst.getOperand(1)); // lane
6264 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6265 TmpInst.addOperand(Inst.getOperand(5));
6270 case ARM::VST1LNdAsm_8:
6271 case ARM::VST1LNdAsm_16:
6272 case ARM::VST1LNdAsm_32: {
6274 // Shuffle the operands around so the lane index operand is in the
6277 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6278 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6279 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6280 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6281 TmpInst.addOperand(Inst.getOperand(1)); // lane
6282 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6283 TmpInst.addOperand(Inst.getOperand(5));
6288 case ARM::VST2LNdAsm_8:
6289 case ARM::VST2LNdAsm_16:
6290 case ARM::VST2LNdAsm_32:
6291 case ARM::VST2LNqAsm_16:
6292 case ARM::VST2LNqAsm_32: {
6294 // Shuffle the operands around so the lane index operand is in the
6297 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6298 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6299 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6300 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6301 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6303 TmpInst.addOperand(Inst.getOperand(1)); // lane
6304 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6305 TmpInst.addOperand(Inst.getOperand(5));
6310 case ARM::VST3LNdAsm_8:
6311 case ARM::VST3LNdAsm_16:
6312 case ARM::VST3LNdAsm_32:
6313 case ARM::VST3LNqAsm_16:
6314 case ARM::VST3LNqAsm_32: {
6316 // Shuffle the operands around so the lane index operand is in the
6319 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6320 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6321 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6322 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6323 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6325 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6327 TmpInst.addOperand(Inst.getOperand(1)); // lane
6328 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6329 TmpInst.addOperand(Inst.getOperand(5));
6334 case ARM::VST4LNdAsm_8:
6335 case ARM::VST4LNdAsm_16:
6336 case ARM::VST4LNdAsm_32:
6337 case ARM::VST4LNqAsm_16:
6338 case ARM::VST4LNqAsm_32: {
6340 // Shuffle the operands around so the lane index operand is in the
6343 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6344 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6345 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6346 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6347 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6349 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6351 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6353 TmpInst.addOperand(Inst.getOperand(1)); // lane
6354 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6355 TmpInst.addOperand(Inst.getOperand(5));
6360 // Handle NEON VLD complex aliases.
6361 case ARM::VLD1LNdWB_register_Asm_8:
6362 case ARM::VLD1LNdWB_register_Asm_16:
6363 case ARM::VLD1LNdWB_register_Asm_32: {
6365 // Shuffle the operands around so the lane index operand is in the
6368 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6369 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6370 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6371 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6372 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6373 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6374 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6375 TmpInst.addOperand(Inst.getOperand(1)); // lane
6376 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6377 TmpInst.addOperand(Inst.getOperand(6));
6382 case ARM::VLD2LNdWB_register_Asm_8:
6383 case ARM::VLD2LNdWB_register_Asm_16:
6384 case ARM::VLD2LNdWB_register_Asm_32:
6385 case ARM::VLD2LNqWB_register_Asm_16:
6386 case ARM::VLD2LNqWB_register_Asm_32: {
6388 // Shuffle the operands around so the lane index operand is in the
6391 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6392 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6393 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6395 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6396 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6397 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6398 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6399 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6400 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6402 TmpInst.addOperand(Inst.getOperand(1)); // lane
6403 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6404 TmpInst.addOperand(Inst.getOperand(6));
6409 case ARM::VLD3LNdWB_register_Asm_8:
6410 case ARM::VLD3LNdWB_register_Asm_16:
6411 case ARM::VLD3LNdWB_register_Asm_32:
6412 case ARM::VLD3LNqWB_register_Asm_16:
6413 case ARM::VLD3LNqWB_register_Asm_32: {
6415 // Shuffle the operands around so the lane index operand is in the
6418 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6419 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6420 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6422 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6424 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6425 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6426 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6427 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6428 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6429 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6431 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6433 TmpInst.addOperand(Inst.getOperand(1)); // lane
6434 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6435 TmpInst.addOperand(Inst.getOperand(6));
6440 case ARM::VLD4LNdWB_register_Asm_8:
6441 case ARM::VLD4LNdWB_register_Asm_16:
6442 case ARM::VLD4LNdWB_register_Asm_32:
6443 case ARM::VLD4LNqWB_register_Asm_16:
6444 case ARM::VLD4LNqWB_register_Asm_32: {
6446 // Shuffle the operands around so the lane index operand is in the
6449 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6450 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6451 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6453 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6455 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6457 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6458 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6459 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6460 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6461 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6462 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6464 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6466 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6468 TmpInst.addOperand(Inst.getOperand(1)); // lane
6469 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6470 TmpInst.addOperand(Inst.getOperand(6));
6475 case ARM::VLD1LNdWB_fixed_Asm_8:
6476 case ARM::VLD1LNdWB_fixed_Asm_16:
6477 case ARM::VLD1LNdWB_fixed_Asm_32: {
6479 // Shuffle the operands around so the lane index operand is in the
6482 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6483 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6484 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6485 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6486 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6487 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6488 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6489 TmpInst.addOperand(Inst.getOperand(1)); // lane
6490 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6491 TmpInst.addOperand(Inst.getOperand(5));
6496 case ARM::VLD2LNdWB_fixed_Asm_8:
6497 case ARM::VLD2LNdWB_fixed_Asm_16:
6498 case ARM::VLD2LNdWB_fixed_Asm_32:
6499 case ARM::VLD2LNqWB_fixed_Asm_16:
6500 case ARM::VLD2LNqWB_fixed_Asm_32: {
6502 // Shuffle the operands around so the lane index operand is in the
6505 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6506 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6507 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6509 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6510 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6511 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6512 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6513 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6514 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6516 TmpInst.addOperand(Inst.getOperand(1)); // lane
6517 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6518 TmpInst.addOperand(Inst.getOperand(5));
6523 case ARM::VLD3LNdWB_fixed_Asm_8:
6524 case ARM::VLD3LNdWB_fixed_Asm_16:
6525 case ARM::VLD3LNdWB_fixed_Asm_32:
6526 case ARM::VLD3LNqWB_fixed_Asm_16:
6527 case ARM::VLD3LNqWB_fixed_Asm_32: {
6529 // Shuffle the operands around so the lane index operand is in the
6532 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6533 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6534 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6536 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6538 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6539 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6540 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6541 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6542 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6543 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6545 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6547 TmpInst.addOperand(Inst.getOperand(1)); // lane
6548 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6549 TmpInst.addOperand(Inst.getOperand(5));
6554 case ARM::VLD4LNdWB_fixed_Asm_8:
6555 case ARM::VLD4LNdWB_fixed_Asm_16:
6556 case ARM::VLD4LNdWB_fixed_Asm_32:
6557 case ARM::VLD4LNqWB_fixed_Asm_16:
6558 case ARM::VLD4LNqWB_fixed_Asm_32: {
6560 // Shuffle the operands around so the lane index operand is in the
6563 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6564 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6565 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6567 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6569 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6571 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6572 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6573 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6574 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6575 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6576 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6578 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6580 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6582 TmpInst.addOperand(Inst.getOperand(1)); // lane
6583 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6584 TmpInst.addOperand(Inst.getOperand(5));
6589 case ARM::VLD1LNdAsm_8:
6590 case ARM::VLD1LNdAsm_16:
6591 case ARM::VLD1LNdAsm_32: {
6593 // Shuffle the operands around so the lane index operand is in the
6596 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6597 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6598 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6599 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6600 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6601 TmpInst.addOperand(Inst.getOperand(1)); // lane
6602 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6603 TmpInst.addOperand(Inst.getOperand(5));
6608 case ARM::VLD2LNdAsm_8:
6609 case ARM::VLD2LNdAsm_16:
6610 case ARM::VLD2LNdAsm_32:
6611 case ARM::VLD2LNqAsm_16:
6612 case ARM::VLD2LNqAsm_32: {
6614 // Shuffle the operands around so the lane index operand is in the
6617 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6618 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6619 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6621 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6622 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6623 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6624 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6626 TmpInst.addOperand(Inst.getOperand(1)); // lane
6627 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6628 TmpInst.addOperand(Inst.getOperand(5));
6633 case ARM::VLD3LNdAsm_8:
6634 case ARM::VLD3LNdAsm_16:
6635 case ARM::VLD3LNdAsm_32:
6636 case ARM::VLD3LNqAsm_16:
6637 case ARM::VLD3LNqAsm_32: {
6639 // Shuffle the operands around so the lane index operand is in the
6642 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6643 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6644 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6646 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6648 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6649 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6650 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6651 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6653 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6655 TmpInst.addOperand(Inst.getOperand(1)); // lane
6656 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6657 TmpInst.addOperand(Inst.getOperand(5));
6662 case ARM::VLD4LNdAsm_8:
6663 case ARM::VLD4LNdAsm_16:
6664 case ARM::VLD4LNdAsm_32:
6665 case ARM::VLD4LNqAsm_16:
6666 case ARM::VLD4LNqAsm_32: {
6668 // Shuffle the operands around so the lane index operand is in the
6671 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6672 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6673 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6675 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6677 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6679 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6680 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6681 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6682 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6684 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6686 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6688 TmpInst.addOperand(Inst.getOperand(1)); // lane
6689 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6690 TmpInst.addOperand(Inst.getOperand(5));
6695 // VLD3DUP single 3-element structure to all lanes instructions.
6696 case ARM::VLD3DUPdAsm_8:
6697 case ARM::VLD3DUPdAsm_16:
6698 case ARM::VLD3DUPdAsm_32:
6699 case ARM::VLD3DUPqAsm_8:
6700 case ARM::VLD3DUPqAsm_16:
6701 case ARM::VLD3DUPqAsm_32: {
6704 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6705 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6706 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6708 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6710 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6711 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6712 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6713 TmpInst.addOperand(Inst.getOperand(4));
6718 case ARM::VLD3DUPdWB_fixed_Asm_8:
6719 case ARM::VLD3DUPdWB_fixed_Asm_16:
6720 case ARM::VLD3DUPdWB_fixed_Asm_32:
6721 case ARM::VLD3DUPqWB_fixed_Asm_8:
6722 case ARM::VLD3DUPqWB_fixed_Asm_16:
6723 case ARM::VLD3DUPqWB_fixed_Asm_32: {
6726 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6727 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6728 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6730 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6732 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6733 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6734 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6735 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6736 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6737 TmpInst.addOperand(Inst.getOperand(4));
6742 case ARM::VLD3DUPdWB_register_Asm_8:
6743 case ARM::VLD3DUPdWB_register_Asm_16:
6744 case ARM::VLD3DUPdWB_register_Asm_32:
6745 case ARM::VLD3DUPqWB_register_Asm_8:
6746 case ARM::VLD3DUPqWB_register_Asm_16:
6747 case ARM::VLD3DUPqWB_register_Asm_32: {
6750 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6751 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6752 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6754 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6756 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6757 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6758 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6759 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6760 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6761 TmpInst.addOperand(Inst.getOperand(5));
6766 // VLD3 multiple 3-element structure instructions.
6767 case ARM::VLD3dAsm_8:
6768 case ARM::VLD3dAsm_16:
6769 case ARM::VLD3dAsm_32:
6770 case ARM::VLD3qAsm_8:
6771 case ARM::VLD3qAsm_16:
6772 case ARM::VLD3qAsm_32: {
6775 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6776 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6777 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6779 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6781 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6782 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6783 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6784 TmpInst.addOperand(Inst.getOperand(4));
6789 case ARM::VLD3dWB_fixed_Asm_8:
6790 case ARM::VLD3dWB_fixed_Asm_16:
6791 case ARM::VLD3dWB_fixed_Asm_32:
6792 case ARM::VLD3qWB_fixed_Asm_8:
6793 case ARM::VLD3qWB_fixed_Asm_16:
6794 case ARM::VLD3qWB_fixed_Asm_32: {
6797 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6798 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6799 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6801 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6803 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6804 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6805 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6806 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6807 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6808 TmpInst.addOperand(Inst.getOperand(4));
6813 case ARM::VLD3dWB_register_Asm_8:
6814 case ARM::VLD3dWB_register_Asm_16:
6815 case ARM::VLD3dWB_register_Asm_32:
6816 case ARM::VLD3qWB_register_Asm_8:
6817 case ARM::VLD3qWB_register_Asm_16:
6818 case ARM::VLD3qWB_register_Asm_32: {
6821 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6822 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6823 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6825 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6827 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6828 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6829 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6830 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6831 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6832 TmpInst.addOperand(Inst.getOperand(5));
6837 // VLD4DUP single 3-element structure to all lanes instructions.
6838 case ARM::VLD4DUPdAsm_8:
6839 case ARM::VLD4DUPdAsm_16:
6840 case ARM::VLD4DUPdAsm_32:
6841 case ARM::VLD4DUPqAsm_8:
6842 case ARM::VLD4DUPqAsm_16:
6843 case ARM::VLD4DUPqAsm_32: {
6846 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6847 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6848 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6850 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6852 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6854 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6855 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6856 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6857 TmpInst.addOperand(Inst.getOperand(4));
6862 case ARM::VLD4DUPdWB_fixed_Asm_8:
6863 case ARM::VLD4DUPdWB_fixed_Asm_16:
6864 case ARM::VLD4DUPdWB_fixed_Asm_32:
6865 case ARM::VLD4DUPqWB_fixed_Asm_8:
6866 case ARM::VLD4DUPqWB_fixed_Asm_16:
6867 case ARM::VLD4DUPqWB_fixed_Asm_32: {
6870 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6871 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6872 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6874 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6876 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6878 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6879 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6880 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6881 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6882 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6883 TmpInst.addOperand(Inst.getOperand(4));
6888 case ARM::VLD4DUPdWB_register_Asm_8:
6889 case ARM::VLD4DUPdWB_register_Asm_16:
6890 case ARM::VLD4DUPdWB_register_Asm_32:
6891 case ARM::VLD4DUPqWB_register_Asm_8:
6892 case ARM::VLD4DUPqWB_register_Asm_16:
6893 case ARM::VLD4DUPqWB_register_Asm_32: {
6896 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6897 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6898 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6900 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6902 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6904 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6905 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6906 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6907 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6908 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6909 TmpInst.addOperand(Inst.getOperand(5));
6914 // VLD4 multiple 4-element structure instructions.
6915 case ARM::VLD4dAsm_8:
6916 case ARM::VLD4dAsm_16:
6917 case ARM::VLD4dAsm_32:
6918 case ARM::VLD4qAsm_8:
6919 case ARM::VLD4qAsm_16:
6920 case ARM::VLD4qAsm_32: {
6923 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6924 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6925 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6927 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6929 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6931 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6932 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6933 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6934 TmpInst.addOperand(Inst.getOperand(4));
6939 case ARM::VLD4dWB_fixed_Asm_8:
6940 case ARM::VLD4dWB_fixed_Asm_16:
6941 case ARM::VLD4dWB_fixed_Asm_32:
6942 case ARM::VLD4qWB_fixed_Asm_8:
6943 case ARM::VLD4qWB_fixed_Asm_16:
6944 case ARM::VLD4qWB_fixed_Asm_32: {
6947 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6948 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6949 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6951 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6953 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6955 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6956 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6957 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6958 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6959 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6960 TmpInst.addOperand(Inst.getOperand(4));
6965 case ARM::VLD4dWB_register_Asm_8:
6966 case ARM::VLD4dWB_register_Asm_16:
6967 case ARM::VLD4dWB_register_Asm_32:
6968 case ARM::VLD4qWB_register_Asm_8:
6969 case ARM::VLD4qWB_register_Asm_16:
6970 case ARM::VLD4qWB_register_Asm_32: {
6973 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6974 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6975 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6977 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6979 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6981 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6982 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6983 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6984 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6985 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6986 TmpInst.addOperand(Inst.getOperand(5));
6991 // VST3 multiple 3-element structure instructions.
6992 case ARM::VST3dAsm_8:
6993 case ARM::VST3dAsm_16:
6994 case ARM::VST3dAsm_32:
6995 case ARM::VST3qAsm_8:
6996 case ARM::VST3qAsm_16:
6997 case ARM::VST3qAsm_32: {
7000 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7001 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7002 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7003 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7004 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7006 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7008 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7009 TmpInst.addOperand(Inst.getOperand(4));
7014 case ARM::VST3dWB_fixed_Asm_8:
7015 case ARM::VST3dWB_fixed_Asm_16:
7016 case ARM::VST3dWB_fixed_Asm_32:
7017 case ARM::VST3qWB_fixed_Asm_8:
7018 case ARM::VST3qWB_fixed_Asm_16:
7019 case ARM::VST3qWB_fixed_Asm_32: {
7022 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7023 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7024 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7025 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7026 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7027 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7028 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7030 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7032 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7033 TmpInst.addOperand(Inst.getOperand(4));
7038 case ARM::VST3dWB_register_Asm_8:
7039 case ARM::VST3dWB_register_Asm_16:
7040 case ARM::VST3dWB_register_Asm_32:
7041 case ARM::VST3qWB_register_Asm_8:
7042 case ARM::VST3qWB_register_Asm_16:
7043 case ARM::VST3qWB_register_Asm_32: {
7046 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7047 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7048 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7049 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7050 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7051 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7052 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7054 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7056 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7057 TmpInst.addOperand(Inst.getOperand(5));
7062 // VST4 multiple 3-element structure instructions.
7063 case ARM::VST4dAsm_8:
7064 case ARM::VST4dAsm_16:
7065 case ARM::VST4dAsm_32:
7066 case ARM::VST4qAsm_8:
7067 case ARM::VST4qAsm_16:
7068 case ARM::VST4qAsm_32: {
7071 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7072 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7073 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7074 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7075 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7077 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7079 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7081 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7082 TmpInst.addOperand(Inst.getOperand(4));
7087 case ARM::VST4dWB_fixed_Asm_8:
7088 case ARM::VST4dWB_fixed_Asm_16:
7089 case ARM::VST4dWB_fixed_Asm_32:
7090 case ARM::VST4qWB_fixed_Asm_8:
7091 case ARM::VST4qWB_fixed_Asm_16:
7092 case ARM::VST4qWB_fixed_Asm_32: {
7095 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7096 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7097 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7098 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7099 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7100 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7101 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7103 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7105 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7107 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7108 TmpInst.addOperand(Inst.getOperand(4));
7113 case ARM::VST4dWB_register_Asm_8:
7114 case ARM::VST4dWB_register_Asm_16:
7115 case ARM::VST4dWB_register_Asm_32:
7116 case ARM::VST4qWB_register_Asm_8:
7117 case ARM::VST4qWB_register_Asm_16:
7118 case ARM::VST4qWB_register_Asm_32: {
7121 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7122 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7123 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7124 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7125 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7126 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7127 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7129 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7131 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7133 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7134 TmpInst.addOperand(Inst.getOperand(5));
7139 // Handle encoding choice for the shift-immediate instructions.
7142 case ARM::t2ASRri: {
7143 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7144 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7145 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
7146 !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
7147 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
7149 switch (Inst.getOpcode()) {
7150 default: llvm_unreachable("unexpected opcode");
7151 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
7152 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
7153 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
7155 // The Thumb1 operands aren't in the same order. Awesome, eh?
7157 TmpInst.setOpcode(NewOpc);
7158 TmpInst.addOperand(Inst.getOperand(0));
7159 TmpInst.addOperand(Inst.getOperand(5));
7160 TmpInst.addOperand(Inst.getOperand(1));
7161 TmpInst.addOperand(Inst.getOperand(2));
7162 TmpInst.addOperand(Inst.getOperand(3));
7163 TmpInst.addOperand(Inst.getOperand(4));
7170 // Handle the Thumb2 mode MOV complex aliases.
7172 case ARM::t2MOVSsr: {
7173 // Which instruction to expand to depends on the CCOut operand and
7174 // whether we're in an IT block if the register operands are low
7176 bool isNarrow = false;
7177 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7178 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7179 isARMLowRegister(Inst.getOperand(2).getReg()) &&
7180 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7181 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
7185 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
7186 default: llvm_unreachable("unexpected opcode!");
7187 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7188 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7189 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7190 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
7192 TmpInst.setOpcode(newOpc);
7193 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7195 TmpInst.addOperand(MCOperand::CreateReg(
7196 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7197 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7198 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7199 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7200 TmpInst.addOperand(Inst.getOperand(5));
7202 TmpInst.addOperand(MCOperand::CreateReg(
7203 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7208 case ARM::t2MOVSsi: {
7209 // Which instruction to expand to depends on the CCOut operand and
7210 // whether we're in an IT block if the register operands are low
7212 bool isNarrow = false;
7213 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7214 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7215 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
7219 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
7220 default: llvm_unreachable("unexpected opcode!");
7221 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7222 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7223 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7224 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7225 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7227 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
7228 if (Amount == 32) Amount = 0;
7229 TmpInst.setOpcode(newOpc);
7230 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7232 TmpInst.addOperand(MCOperand::CreateReg(
7233 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7234 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7235 if (newOpc != ARM::t2RRX)
7236 TmpInst.addOperand(MCOperand::CreateImm(Amount));
7237 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7238 TmpInst.addOperand(Inst.getOperand(4));
7240 TmpInst.addOperand(MCOperand::CreateReg(
7241 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7245 // Handle the ARM mode MOV complex aliases.
7250 ARM_AM::ShiftOpc ShiftTy;
7251 switch(Inst.getOpcode()) {
7252 default: llvm_unreachable("unexpected opcode!");
7253 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
7254 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
7255 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
7256 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
7258 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
7260 TmpInst.setOpcode(ARM::MOVsr);
7261 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7262 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7263 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7264 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7265 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7266 TmpInst.addOperand(Inst.getOperand(4));
7267 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7275 ARM_AM::ShiftOpc ShiftTy;
7276 switch(Inst.getOpcode()) {
7277 default: llvm_unreachable("unexpected opcode!");
7278 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
7279 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
7280 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7281 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
7283 // A shift by zero is a plain MOVr, not a MOVsi.
7284 unsigned Amt = Inst.getOperand(2).getImm();
7285 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
7286 // A shift by 32 should be encoded as 0 when permitted
7287 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
7289 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
7291 TmpInst.setOpcode(Opc);
7292 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7293 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7294 if (Opc == ARM::MOVsi)
7295 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7296 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7297 TmpInst.addOperand(Inst.getOperand(4));
7298 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7303 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
7305 TmpInst.setOpcode(ARM::MOVsi);
7306 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7307 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7308 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7309 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7310 TmpInst.addOperand(Inst.getOperand(3));
7311 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7315 case ARM::t2LDMIA_UPD: {
7316 // If this is a load of a single register, then we should use
7317 // a post-indexed LDR instruction instead, per the ARM ARM.
7318 if (Inst.getNumOperands() != 5)
7321 TmpInst.setOpcode(ARM::t2LDR_POST);
7322 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7323 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7324 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7325 TmpInst.addOperand(MCOperand::CreateImm(4));
7326 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7327 TmpInst.addOperand(Inst.getOperand(3));
7331 case ARM::t2STMDB_UPD: {
7332 // If this is a store of a single register, then we should use
7333 // a pre-indexed STR instruction instead, per the ARM ARM.
7334 if (Inst.getNumOperands() != 5)
7337 TmpInst.setOpcode(ARM::t2STR_PRE);
7338 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7339 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7340 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7341 TmpInst.addOperand(MCOperand::CreateImm(-4));
7342 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7343 TmpInst.addOperand(Inst.getOperand(3));
7347 case ARM::LDMIA_UPD:
7348 // If this is a load of a single register via a 'pop', then we should use
7349 // a post-indexed LDR instruction instead, per the ARM ARM.
7350 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
7351 Inst.getNumOperands() == 5) {
7353 TmpInst.setOpcode(ARM::LDR_POST_IMM);
7354 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7355 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7356 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7357 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
7358 TmpInst.addOperand(MCOperand::CreateImm(4));
7359 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7360 TmpInst.addOperand(Inst.getOperand(3));
7365 case ARM::STMDB_UPD:
7366 // If this is a store of a single register via a 'push', then we should use
7367 // a pre-indexed STR instruction instead, per the ARM ARM.
7368 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
7369 Inst.getNumOperands() == 5) {
7371 TmpInst.setOpcode(ARM::STR_PRE_IMM);
7372 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7373 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7374 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7375 TmpInst.addOperand(MCOperand::CreateImm(-4));
7376 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7377 TmpInst.addOperand(Inst.getOperand(3));
7381 case ARM::t2ADDri12:
7382 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7383 // mnemonic was used (not "addw"), encoding T3 is preferred.
7384 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
7385 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7387 Inst.setOpcode(ARM::t2ADDri);
7388 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7390 case ARM::t2SUBri12:
7391 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7392 // mnemonic was used (not "subw"), encoding T3 is preferred.
7393 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7394 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7396 Inst.setOpcode(ARM::t2SUBri);
7397 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7400 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7401 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7402 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7403 // to encoding T1 if <Rd> is omitted."
7404 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7405 Inst.setOpcode(ARM::tADDi3);
7410 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7411 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7412 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7413 // to encoding T1 if <Rd> is omitted."
7414 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7415 Inst.setOpcode(ARM::tSUBi3);
7420 case ARM::t2SUBri: {
7421 // If the destination and first source operand are the same, and
7422 // the flags are compatible with the current IT status, use encoding T2
7423 // instead of T3. For compatibility with the system 'as'. Make sure the
7424 // wide encoding wasn't explicit.
7425 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7426 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7427 (unsigned)Inst.getOperand(2).getImm() > 255 ||
7428 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7429 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7430 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7431 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7434 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7435 ARM::tADDi8 : ARM::tSUBi8);
7436 TmpInst.addOperand(Inst.getOperand(0));
7437 TmpInst.addOperand(Inst.getOperand(5));
7438 TmpInst.addOperand(Inst.getOperand(0));
7439 TmpInst.addOperand(Inst.getOperand(2));
7440 TmpInst.addOperand(Inst.getOperand(3));
7441 TmpInst.addOperand(Inst.getOperand(4));
7445 case ARM::t2ADDrr: {
7446 // If the destination and first source operand are the same, and
7447 // there's no setting of the flags, use encoding T2 instead of T3.
7448 // Note that this is only for ADD, not SUB. This mirrors the system
7449 // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7450 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7451 Inst.getOperand(5).getReg() != 0 ||
7452 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7453 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7456 TmpInst.setOpcode(ARM::tADDhirr);
7457 TmpInst.addOperand(Inst.getOperand(0));
7458 TmpInst.addOperand(Inst.getOperand(0));
7459 TmpInst.addOperand(Inst.getOperand(2));
7460 TmpInst.addOperand(Inst.getOperand(3));
7461 TmpInst.addOperand(Inst.getOperand(4));
7465 case ARM::tADDrSP: {
7466 // If the non-SP source operand and the destination operand are not the
7467 // same, we need to use the 32-bit encoding if it's available.
7468 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7469 Inst.setOpcode(ARM::t2ADDrr);
7470 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7476 // A Thumb conditional branch outside of an IT block is a tBcc.
7477 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7478 Inst.setOpcode(ARM::tBcc);
7483 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7484 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7485 Inst.setOpcode(ARM::t2Bcc);
7490 // If the conditional is AL or we're in an IT block, we really want t2B.
7491 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7492 Inst.setOpcode(ARM::t2B);
7497 // If the conditional is AL, we really want tB.
7498 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7499 Inst.setOpcode(ARM::tB);
7504 // If the register list contains any high registers, or if the writeback
7505 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7506 // instead if we're in Thumb2. Otherwise, this should have generated
7507 // an error in validateInstruction().
7508 unsigned Rn = Inst.getOperand(0).getReg();
7509 bool hasWritebackToken =
7510 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7511 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7512 bool listContainsBase;
7513 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7514 (!listContainsBase && !hasWritebackToken) ||
7515 (listContainsBase && hasWritebackToken)) {
7516 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7517 assert (isThumbTwo());
7518 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7519 // If we're switching to the updating version, we need to insert
7520 // the writeback tied operand.
7521 if (hasWritebackToken)
7522 Inst.insert(Inst.begin(),
7523 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7528 case ARM::tSTMIA_UPD: {
7529 // If the register list contains any high registers, we need to use
7530 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7531 // should have generated an error in validateInstruction().
7532 unsigned Rn = Inst.getOperand(0).getReg();
7533 bool listContainsBase;
7534 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7535 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7536 assert (isThumbTwo());
7537 Inst.setOpcode(ARM::t2STMIA_UPD);
7543 bool listContainsBase;
7544 // If the register list contains any high registers, we need to use
7545 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7546 // should have generated an error in validateInstruction().
7547 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7549 assert (isThumbTwo());
7550 Inst.setOpcode(ARM::t2LDMIA_UPD);
7551 // Add the base register and writeback operands.
7552 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7553 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7557 bool listContainsBase;
7558 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7560 assert (isThumbTwo());
7561 Inst.setOpcode(ARM::t2STMDB_UPD);
7562 // Add the base register and writeback operands.
7563 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7564 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7568 // If we can use the 16-bit encoding and the user didn't explicitly
7569 // request the 32-bit variant, transform it here.
7570 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7571 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7572 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7573 Inst.getOperand(4).getReg() == ARM::CPSR) ||
7574 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7575 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7576 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7577 // The operands aren't in the same order for tMOVi8...
7579 TmpInst.setOpcode(ARM::tMOVi8);
7580 TmpInst.addOperand(Inst.getOperand(0));
7581 TmpInst.addOperand(Inst.getOperand(4));
7582 TmpInst.addOperand(Inst.getOperand(1));
7583 TmpInst.addOperand(Inst.getOperand(2));
7584 TmpInst.addOperand(Inst.getOperand(3));
7591 // If we can use the 16-bit encoding and the user didn't explicitly
7592 // request the 32-bit variant, transform it here.
7593 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7594 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7595 Inst.getOperand(2).getImm() == ARMCC::AL &&
7596 Inst.getOperand(4).getReg() == ARM::CPSR &&
7597 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7598 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7599 // The operands aren't the same for tMOV[S]r... (no cc_out)
7601 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7602 TmpInst.addOperand(Inst.getOperand(0));
7603 TmpInst.addOperand(Inst.getOperand(1));
7604 TmpInst.addOperand(Inst.getOperand(2));
7605 TmpInst.addOperand(Inst.getOperand(3));
7615 // If we can use the 16-bit encoding and the user didn't explicitly
7616 // request the 32-bit variant, transform it here.
7617 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7618 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7619 Inst.getOperand(2).getImm() == 0 &&
7620 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7621 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7623 switch (Inst.getOpcode()) {
7624 default: llvm_unreachable("Illegal opcode!");
7625 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7626 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7627 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7628 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7630 // The operands aren't the same for thumb1 (no rotate operand).
7632 TmpInst.setOpcode(NewOpc);
7633 TmpInst.addOperand(Inst.getOperand(0));
7634 TmpInst.addOperand(Inst.getOperand(1));
7635 TmpInst.addOperand(Inst.getOperand(3));
7636 TmpInst.addOperand(Inst.getOperand(4));
7643 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7644 // rrx shifts and asr/lsr of #32 is encoded as 0
7645 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7647 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7648 // Shifting by zero is accepted as a vanilla 'MOVr'
7650 TmpInst.setOpcode(ARM::MOVr);
7651 TmpInst.addOperand(Inst.getOperand(0));
7652 TmpInst.addOperand(Inst.getOperand(1));
7653 TmpInst.addOperand(Inst.getOperand(3));
7654 TmpInst.addOperand(Inst.getOperand(4));
7655 TmpInst.addOperand(Inst.getOperand(5));
7668 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7669 if (SOpc == ARM_AM::rrx) return false;
7670 switch (Inst.getOpcode()) {
7671 default: llvm_unreachable("unexpected opcode!");
7672 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7673 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7674 case ARM::EORrsi: newOpc = ARM::EORrr; break;
7675 case ARM::BICrsi: newOpc = ARM::BICrr; break;
7676 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7677 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7679 // If the shift is by zero, use the non-shifted instruction definition.
7680 // The exception is for right shifts, where 0 == 32
7681 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7682 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7684 TmpInst.setOpcode(newOpc);
7685 TmpInst.addOperand(Inst.getOperand(0));
7686 TmpInst.addOperand(Inst.getOperand(1));
7687 TmpInst.addOperand(Inst.getOperand(2));
7688 TmpInst.addOperand(Inst.getOperand(4));
7689 TmpInst.addOperand(Inst.getOperand(5));
7690 TmpInst.addOperand(Inst.getOperand(6));
7698 // The mask bits for all but the first condition are represented as
7699 // the low bit of the condition code value implies 't'. We currently
7700 // always have 1 implies 't', so XOR toggle the bits if the low bit
7701 // of the condition code is zero.
7702 MCOperand &MO = Inst.getOperand(1);
7703 unsigned Mask = MO.getImm();
7704 unsigned OrigMask = Mask;
7705 unsigned TZ = countTrailingZeros(Mask);
7706 if ((Inst.getOperand(0).getImm() & 1) == 0) {
7707 assert(Mask && TZ <= 3 && "illegal IT mask value!");
7708 Mask ^= (0xE << TZ) & 0xF;
7712 // Set up the IT block state according to the IT instruction we just
7714 assert(!inITBlock() && "nested IT blocks?!");
7715 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7716 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7717 ITState.CurPosition = 0;
7718 ITState.FirstCond = true;
7728 // Assemblers should use the narrow encodings of these instructions when permissible.
7729 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7730 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7731 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7732 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7733 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7734 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7735 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7737 switch (Inst.getOpcode()) {
7738 default: llvm_unreachable("unexpected opcode");
7739 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7740 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7741 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7742 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7743 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7744 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7747 TmpInst.setOpcode(NewOpc);
7748 TmpInst.addOperand(Inst.getOperand(0));
7749 TmpInst.addOperand(Inst.getOperand(5));
7750 TmpInst.addOperand(Inst.getOperand(1));
7751 TmpInst.addOperand(Inst.getOperand(2));
7752 TmpInst.addOperand(Inst.getOperand(3));
7753 TmpInst.addOperand(Inst.getOperand(4));
7764 // Assemblers should use the narrow encodings of these instructions when permissible.
7765 // These instructions are special in that they are commutable, so shorter encodings
7766 // are available more often.
7767 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7768 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7769 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7770 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7771 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7772 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7773 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7774 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7776 switch (Inst.getOpcode()) {
7777 default: llvm_unreachable("unexpected opcode");
7778 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7779 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7780 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7781 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7784 TmpInst.setOpcode(NewOpc);
7785 TmpInst.addOperand(Inst.getOperand(0));
7786 TmpInst.addOperand(Inst.getOperand(5));
7787 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7788 TmpInst.addOperand(Inst.getOperand(1));
7789 TmpInst.addOperand(Inst.getOperand(2));
7791 TmpInst.addOperand(Inst.getOperand(2));
7792 TmpInst.addOperand(Inst.getOperand(1));
7794 TmpInst.addOperand(Inst.getOperand(3));
7795 TmpInst.addOperand(Inst.getOperand(4));
7805 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7806 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7807 // suffix depending on whether they're in an IT block or not.
7808 unsigned Opc = Inst.getOpcode();
7809 const MCInstrDesc &MCID = MII.get(Opc);
7810 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7811 assert(MCID.hasOptionalDef() &&
7812 "optionally flag setting instruction missing optional def operand");
7813 assert(MCID.NumOperands == Inst.getNumOperands() &&
7814 "operand count mismatch!");
7815 // Find the optional-def operand (cc_out).
7818 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7821 // If we're parsing Thumb1, reject it completely.
7822 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7823 return Match_MnemonicFail;
7824 // If we're parsing Thumb2, which form is legal depends on whether we're
7826 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7828 return Match_RequiresITBlock;
7829 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7831 return Match_RequiresNotITBlock;
7833 // Some high-register supporting Thumb1 encodings only allow both registers
7834 // to be from r0-r7 when in Thumb2.
7835 else if (Opc == ARM::tADDhirr && isThumbOne() &&
7836 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7837 isARMLowRegister(Inst.getOperand(2).getReg()))
7838 return Match_RequiresThumb2;
7839 // Others only require ARMv6 or later.
7840 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7841 isARMLowRegister(Inst.getOperand(0).getReg()) &&
7842 isARMLowRegister(Inst.getOperand(1).getReg()))
7843 return Match_RequiresV6;
7844 return Match_Success;
7847 static const char *getSubtargetFeatureName(unsigned Val);
7849 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
7850 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
7851 MCStreamer &Out, unsigned &ErrorInfo,
7852 bool MatchingInlineAsm) {
7854 unsigned MatchResult;
7856 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
7858 switch (MatchResult) {
7861 // Context sensitive operand constraints aren't handled by the matcher,
7862 // so check them here.
7863 if (validateInstruction(Inst, Operands)) {
7864 // Still progress the IT block, otherwise one wrong condition causes
7865 // nasty cascading errors.
7866 forwardITPosition();
7870 { // processInstruction() updates inITBlock state, we need to save it away
7871 bool wasInITBlock = inITBlock();
7873 // Some instructions need post-processing to, for example, tweak which
7874 // encoding is selected. Loop on it while changes happen so the
7875 // individual transformations can chain off each other. E.g.,
7876 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
7877 while (processInstruction(Inst, Operands))
7880 // Only after the instruction is fully processed, we can validate it
7881 if (wasInITBlock && hasV8Ops() && isThumb() &&
7882 !isV8EligibleForIT(&Inst, 2)) {
7883 Warning(IDLoc, "deprecated instruction in IT block");
7887 // Only move forward at the very end so that everything in validate
7888 // and process gets a consistent answer about whether we're in an IT
7890 forwardITPosition();
7892 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7893 // doesn't actually encode.
7894 if (Inst.getOpcode() == ARM::ITasm)
7898 Out.EmitInstruction(Inst);
7900 case Match_MissingFeature: {
7901 assert(ErrorInfo && "Unknown missing feature!");
7902 // Special case the error message for the very common case where only
7903 // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
7904 std::string Msg = "instruction requires:";
7906 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
7907 if (ErrorInfo & Mask) {
7909 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
7913 return Error(IDLoc, Msg);
7915 case Match_InvalidOperand: {
7916 SMLoc ErrorLoc = IDLoc;
7917 if (ErrorInfo != ~0U) {
7918 if (ErrorInfo >= Operands.size())
7919 return Error(IDLoc, "too few operands for instruction");
7921 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7922 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7925 return Error(ErrorLoc, "invalid operand for instruction");
7927 case Match_MnemonicFail:
7928 return Error(IDLoc, "invalid instruction",
7929 ((ARMOperand*)Operands[0])->getLocRange());
7930 case Match_RequiresNotITBlock:
7931 return Error(IDLoc, "flag setting instruction only valid outside IT block");
7932 case Match_RequiresITBlock:
7933 return Error(IDLoc, "instruction only valid inside IT block");
7934 case Match_RequiresV6:
7935 return Error(IDLoc, "instruction variant requires ARMv6 or later");
7936 case Match_RequiresThumb2:
7937 return Error(IDLoc, "instruction variant requires Thumb2");
7938 case Match_ImmRange0_15: {
7939 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7940 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7941 return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
7943 case Match_ImmRange0_239: {
7944 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7945 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7946 return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
7950 llvm_unreachable("Implement any new match types added!");
7953 /// parseDirective parses the arm specific directives
7954 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
7955 StringRef IDVal = DirectiveID.getIdentifier();
7956 if (IDVal == ".word")
7957 return parseDirectiveWord(4, DirectiveID.getLoc());
7958 else if (IDVal == ".thumb")
7959 return parseDirectiveThumb(DirectiveID.getLoc());
7960 else if (IDVal == ".arm")
7961 return parseDirectiveARM(DirectiveID.getLoc());
7962 else if (IDVal == ".thumb_func")
7963 return parseDirectiveThumbFunc(DirectiveID.getLoc());
7964 else if (IDVal == ".code")
7965 return parseDirectiveCode(DirectiveID.getLoc());
7966 else if (IDVal == ".syntax")
7967 return parseDirectiveSyntax(DirectiveID.getLoc());
7968 else if (IDVal == ".unreq")
7969 return parseDirectiveUnreq(DirectiveID.getLoc());
7970 else if (IDVal == ".arch")
7971 return parseDirectiveArch(DirectiveID.getLoc());
7972 else if (IDVal == ".eabi_attribute")
7973 return parseDirectiveEabiAttr(DirectiveID.getLoc());
7974 else if (IDVal == ".cpu")
7975 return parseDirectiveCPU(DirectiveID.getLoc());
7976 else if (IDVal == ".fpu")
7977 return parseDirectiveFPU(DirectiveID.getLoc());
7978 else if (IDVal == ".fnstart")
7979 return parseDirectiveFnStart(DirectiveID.getLoc());
7980 else if (IDVal == ".fnend")
7981 return parseDirectiveFnEnd(DirectiveID.getLoc());
7982 else if (IDVal == ".cantunwind")
7983 return parseDirectiveCantUnwind(DirectiveID.getLoc());
7984 else if (IDVal == ".personality")
7985 return parseDirectivePersonality(DirectiveID.getLoc());
7986 else if (IDVal == ".handlerdata")
7987 return parseDirectiveHandlerData(DirectiveID.getLoc());
7988 else if (IDVal == ".setfp")
7989 return parseDirectiveSetFP(DirectiveID.getLoc());
7990 else if (IDVal == ".pad")
7991 return parseDirectivePad(DirectiveID.getLoc());
7992 else if (IDVal == ".save")
7993 return parseDirectiveRegSave(DirectiveID.getLoc(), false);
7994 else if (IDVal == ".vsave")
7995 return parseDirectiveRegSave(DirectiveID.getLoc(), true);
7996 else if (IDVal == ".inst")
7997 return parseDirectiveInst(DirectiveID.getLoc());
7998 else if (IDVal == ".inst.n")
7999 return parseDirectiveInst(DirectiveID.getLoc(), 'n');
8000 else if (IDVal == ".inst.w")
8001 return parseDirectiveInst(DirectiveID.getLoc(), 'w');
8002 else if (IDVal == ".ltorg" || IDVal == ".pool")
8003 return parseDirectiveLtorg(DirectiveID.getLoc());
8004 else if (IDVal == ".even")
8005 return parseDirectiveEven(DirectiveID.getLoc());
8009 /// parseDirectiveWord
8010 /// ::= .word [ expression (, expression)* ]
8011 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
8012 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8014 const MCExpr *Value;
8015 if (getParser().parseExpression(Value))
8018 getParser().getStreamer().EmitValue(Value, Size);
8020 if (getLexer().is(AsmToken::EndOfStatement))
8023 // FIXME: Improve diagnostic.
8024 if (getLexer().isNot(AsmToken::Comma))
8025 return Error(L, "unexpected token in directive");
8034 /// parseDirectiveThumb
8036 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
8037 if (getLexer().isNot(AsmToken::EndOfStatement))
8038 return Error(L, "unexpected token in directive");
8042 return Error(L, "target does not support Thumb mode");
8046 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8050 /// parseDirectiveARM
8052 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
8053 if (getLexer().isNot(AsmToken::EndOfStatement))
8054 return Error(L, "unexpected token in directive");
8058 return Error(L, "target does not support ARM mode");
8062 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8066 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
8067 if (NextSymbolIsThumb) {
8068 getParser().getStreamer().EmitThumbFunc(Symbol);
8069 NextSymbolIsThumb = false;
8073 /// parseDirectiveThumbFunc
8074 /// ::= .thumbfunc symbol_name
8075 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
8076 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
8077 bool isMachO = MAI->hasSubsectionsViaSymbols();
8079 // Darwin asm has (optionally) function name after .thumb_func direction
8082 const AsmToken &Tok = Parser.getTok();
8083 if (Tok.isNot(AsmToken::EndOfStatement)) {
8084 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
8085 return Error(L, "unexpected token in .thumb_func directive");
8087 getParser().getContext().GetOrCreateSymbol(Tok.getIdentifier());
8088 getParser().getStreamer().EmitThumbFunc(Func);
8089 Parser.Lex(); // Consume the identifier token.
8094 if (getLexer().isNot(AsmToken::EndOfStatement))
8095 return Error(L, "unexpected token in directive");
8097 NextSymbolIsThumb = true;
8102 /// parseDirectiveSyntax
8103 /// ::= .syntax unified | divided
8104 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
8105 const AsmToken &Tok = Parser.getTok();
8106 if (Tok.isNot(AsmToken::Identifier))
8107 return Error(L, "unexpected token in .syntax directive");
8108 StringRef Mode = Tok.getString();
8109 if (Mode == "unified" || Mode == "UNIFIED")
8111 else if (Mode == "divided" || Mode == "DIVIDED")
8112 return Error(L, "'.syntax divided' arm asssembly not supported");
8114 return Error(L, "unrecognized syntax mode in .syntax directive");
8116 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8117 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8122 // TODO tell the MC streamer the mode
8123 // getParser().getStreamer().Emit???();
8127 /// parseDirectiveCode
8128 /// ::= .code 16 | 32
8129 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
8130 const AsmToken &Tok = Parser.getTok();
8131 if (Tok.isNot(AsmToken::Integer)) {
8132 Error(L, "unexpected token in .code directive");
8135 int64_t Val = Parser.getTok().getIntVal();
8136 if (Val != 16 && Val != 32) {
8137 Error(L, "invalid operand to .code directive");
8142 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8143 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8150 Error(L, "target does not support Thumb mode");
8156 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8159 Error(L, "target does not support ARM mode");
8165 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8171 /// parseDirectiveReq
8172 /// ::= name .req registername
8173 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
8174 Parser.Lex(); // Eat the '.req' token.
8176 SMLoc SRegLoc, ERegLoc;
8177 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
8178 Parser.eatToEndOfStatement();
8179 Error(SRegLoc, "register name expected");
8183 // Shouldn't be anything else.
8184 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
8185 Parser.eatToEndOfStatement();
8186 Error(Parser.getTok().getLoc(), "unexpected input in .req directive.");
8190 Parser.Lex(); // Consume the EndOfStatement
8192 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg) {
8193 Error(SRegLoc, "redefinition of '" + Name + "' does not match original.");
8200 /// parseDirectiveUneq
8201 /// ::= .unreq registername
8202 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
8203 if (Parser.getTok().isNot(AsmToken::Identifier)) {
8204 Parser.eatToEndOfStatement();
8205 Error(L, "unexpected input in .unreq directive.");
8208 RegisterReqs.erase(Parser.getTok().getIdentifier());
8209 Parser.Lex(); // Eat the identifier.
8213 /// parseDirectiveArch
8215 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
8216 StringRef Arch = getParser().parseStringToEndOfStatement().trim();
8218 unsigned ID = StringSwitch<unsigned>(Arch)
8219 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
8220 .Case(NAME, ARM::ID)
8221 #define ARM_ARCH_ALIAS(NAME, ID) \
8222 .Case(NAME, ARM::ID)
8223 #include "MCTargetDesc/ARMArchName.def"
8224 .Default(ARM::INVALID_ARCH);
8226 if (ID == ARM::INVALID_ARCH) {
8227 Error(L, "Unknown arch name");
8231 getTargetStreamer().emitArch(ID);
8235 /// parseDirectiveEabiAttr
8236 /// ::= .eabi_attribute int, int [, "str"]
8237 /// ::= .eabi_attribute Tag_name, int [, "str"]
8238 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
8242 TagLoc = Parser.getTok().getLoc();
8243 if (Parser.getTok().is(AsmToken::Identifier)) {
8244 StringRef Name = Parser.getTok().getIdentifier();
8245 Tag = ARMBuildAttrs::AttrTypeFromString(Name);
8247 Error(TagLoc, "attribute name not recognised: " + Name);
8248 Parser.eatToEndOfStatement();
8253 const MCExpr *AttrExpr;
8255 TagLoc = Parser.getTok().getLoc();
8256 if (Parser.parseExpression(AttrExpr)) {
8257 Parser.eatToEndOfStatement();
8261 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
8263 Error(TagLoc, "expected numeric constant");
8264 Parser.eatToEndOfStatement();
8268 Tag = CE->getValue();
8271 if (Parser.getTok().isNot(AsmToken::Comma)) {
8272 Error(Parser.getTok().getLoc(), "comma expected");
8273 Parser.eatToEndOfStatement();
8276 Parser.Lex(); // skip comma
8278 StringRef StringValue = "";
8279 bool IsStringValue = false;
8281 int64_t IntegerValue = 0;
8282 bool IsIntegerValue = false;
8284 if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
8285 IsStringValue = true;
8286 else if (Tag == ARMBuildAttrs::compatibility) {
8287 IsStringValue = true;
8288 IsIntegerValue = true;
8289 } else if (Tag == ARMBuildAttrs::nodefaults || Tag < 32 || Tag % 2 == 0)
8290 IsIntegerValue = true;
8291 else if (Tag % 2 == 1)
8292 IsStringValue = true;
8294 llvm_unreachable("invalid tag type");
8296 if (IsIntegerValue) {
8297 const MCExpr *ValueExpr;
8298 SMLoc ValueExprLoc = Parser.getTok().getLoc();
8299 if (Parser.parseExpression(ValueExpr)) {
8300 Parser.eatToEndOfStatement();
8304 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
8306 Error(ValueExprLoc, "expected numeric constant");
8307 Parser.eatToEndOfStatement();
8311 IntegerValue = CE->getValue();
8314 if (Tag == ARMBuildAttrs::compatibility) {
8315 if (Parser.getTok().isNot(AsmToken::Comma))
8316 IsStringValue = false;
8321 if (IsStringValue) {
8322 if (Parser.getTok().isNot(AsmToken::String)) {
8323 Error(Parser.getTok().getLoc(), "bad string constant");
8324 Parser.eatToEndOfStatement();
8328 StringValue = Parser.getTok().getStringContents();
8332 if (IsIntegerValue && IsStringValue) {
8333 assert(Tag == ARMBuildAttrs::compatibility);
8334 getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
8335 } else if (IsIntegerValue)
8336 getTargetStreamer().emitAttribute(Tag, IntegerValue);
8337 else if (IsStringValue)
8338 getTargetStreamer().emitTextAttribute(Tag, StringValue);
8342 /// parseDirectiveCPU
8344 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
8345 StringRef CPU = getParser().parseStringToEndOfStatement().trim();
8346 getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
8350 /// parseDirectiveFPU
8352 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
8353 StringRef FPU = getParser().parseStringToEndOfStatement().trim();
8355 unsigned ID = StringSwitch<unsigned>(FPU)
8356 #define ARM_FPU_NAME(NAME, ID) .Case(NAME, ARM::ID)
8357 #include "ARMFPUName.def"
8358 .Default(ARM::INVALID_FPU);
8360 if (ID == ARM::INVALID_FPU) {
8361 Error(L, "Unknown FPU name");
8365 getTargetStreamer().emitFPU(ID);
8369 /// parseDirectiveFnStart
8371 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
8372 if (UC.hasFnStart()) {
8373 Error(L, ".fnstart starts before the end of previous one");
8374 UC.emitFnStartLocNotes();
8378 getTargetStreamer().emitFnStart();
8380 UC.recordFnStart(L);
8384 /// parseDirectiveFnEnd
8386 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
8387 // Check the ordering of unwind directives
8388 if (!UC.hasFnStart()) {
8389 Error(L, ".fnstart must precede .fnend directive");
8393 // Reset the unwind directives parser state
8394 getTargetStreamer().emitFnEnd();
8400 /// parseDirectiveCantUnwind
8402 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
8403 UC.recordCantUnwind(L);
8405 // Check the ordering of unwind directives
8406 if (!UC.hasFnStart()) {
8407 Error(L, ".fnstart must precede .cantunwind directive");
8410 if (UC.hasHandlerData()) {
8411 Error(L, ".cantunwind can't be used with .handlerdata directive");
8412 UC.emitHandlerDataLocNotes();
8415 if (UC.hasPersonality()) {
8416 Error(L, ".cantunwind can't be used with .personality directive");
8417 UC.emitPersonalityLocNotes();
8421 getTargetStreamer().emitCantUnwind();
8425 /// parseDirectivePersonality
8426 /// ::= .personality name
8427 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
8428 UC.recordPersonality(L);
8430 // Check the ordering of unwind directives
8431 if (!UC.hasFnStart()) {
8432 Error(L, ".fnstart must precede .personality directive");
8435 if (UC.cantUnwind()) {
8436 Error(L, ".personality can't be used with .cantunwind directive");
8437 UC.emitCantUnwindLocNotes();
8440 if (UC.hasHandlerData()) {
8441 Error(L, ".personality must precede .handlerdata directive");
8442 UC.emitHandlerDataLocNotes();
8446 // Parse the name of the personality routine
8447 if (Parser.getTok().isNot(AsmToken::Identifier)) {
8448 Parser.eatToEndOfStatement();
8449 Error(L, "unexpected input in .personality directive.");
8452 StringRef Name(Parser.getTok().getIdentifier());
8455 MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
8456 getTargetStreamer().emitPersonality(PR);
8460 /// parseDirectiveHandlerData
8461 /// ::= .handlerdata
8462 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
8463 UC.recordHandlerData(L);
8465 // Check the ordering of unwind directives
8466 if (!UC.hasFnStart()) {
8467 Error(L, ".fnstart must precede .personality directive");
8470 if (UC.cantUnwind()) {
8471 Error(L, ".handlerdata can't be used with .cantunwind directive");
8472 UC.emitCantUnwindLocNotes();
8476 getTargetStreamer().emitHandlerData();
8480 /// parseDirectiveSetFP
8481 /// ::= .setfp fpreg, spreg [, offset]
8482 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
8483 // Check the ordering of unwind directives
8484 if (!UC.hasFnStart()) {
8485 Error(L, ".fnstart must precede .setfp directive");
8488 if (UC.hasHandlerData()) {
8489 Error(L, ".setfp must precede .handlerdata directive");
8494 SMLoc FPRegLoc = Parser.getTok().getLoc();
8495 int FPReg = tryParseRegister();
8497 Error(FPRegLoc, "frame pointer register expected");
8502 if (!Parser.getTok().is(AsmToken::Comma)) {
8503 Error(Parser.getTok().getLoc(), "comma expected");
8506 Parser.Lex(); // skip comma
8509 SMLoc SPRegLoc = Parser.getTok().getLoc();
8510 int SPReg = tryParseRegister();
8512 Error(SPRegLoc, "stack pointer register expected");
8516 if (SPReg != ARM::SP && SPReg != UC.getFPReg()) {
8517 Error(SPRegLoc, "register should be either $sp or the latest fp register");
8521 // Update the frame pointer register
8522 UC.saveFPReg(FPReg);
8526 if (Parser.getTok().is(AsmToken::Comma)) {
8527 Parser.Lex(); // skip comma
8529 if (Parser.getTok().isNot(AsmToken::Hash) &&
8530 Parser.getTok().isNot(AsmToken::Dollar)) {
8531 Error(Parser.getTok().getLoc(), "'#' expected");
8534 Parser.Lex(); // skip hash token.
8536 const MCExpr *OffsetExpr;
8537 SMLoc ExLoc = Parser.getTok().getLoc();
8539 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
8540 Error(ExLoc, "malformed setfp offset");
8543 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8545 Error(ExLoc, "setfp offset must be an immediate");
8549 Offset = CE->getValue();
8552 getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
8553 static_cast<unsigned>(SPReg), Offset);
8559 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
8560 // Check the ordering of unwind directives
8561 if (!UC.hasFnStart()) {
8562 Error(L, ".fnstart must precede .pad directive");
8565 if (UC.hasHandlerData()) {
8566 Error(L, ".pad must precede .handlerdata directive");
8571 if (Parser.getTok().isNot(AsmToken::Hash) &&
8572 Parser.getTok().isNot(AsmToken::Dollar)) {
8573 Error(Parser.getTok().getLoc(), "'#' expected");
8576 Parser.Lex(); // skip hash token.
8578 const MCExpr *OffsetExpr;
8579 SMLoc ExLoc = Parser.getTok().getLoc();
8581 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
8582 Error(ExLoc, "malformed pad offset");
8585 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8587 Error(ExLoc, "pad offset must be an immediate");
8591 getTargetStreamer().emitPad(CE->getValue());
8595 /// parseDirectiveRegSave
8596 /// ::= .save { registers }
8597 /// ::= .vsave { registers }
8598 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
8599 // Check the ordering of unwind directives
8600 if (!UC.hasFnStart()) {
8601 Error(L, ".fnstart must precede .save or .vsave directives");
8604 if (UC.hasHandlerData()) {
8605 Error(L, ".save or .vsave must precede .handlerdata directive");
8609 // RAII object to make sure parsed operands are deleted.
8610 struct CleanupObject {
8611 SmallVector<MCParsedAsmOperand *, 1> Operands;
8613 for (unsigned I = 0, E = Operands.size(); I != E; ++I)
8618 // Parse the register list
8619 if (parseRegisterList(CO.Operands))
8621 ARMOperand *Op = (ARMOperand*)CO.Operands[0];
8622 if (!IsVector && !Op->isRegList()) {
8623 Error(L, ".save expects GPR registers");
8626 if (IsVector && !Op->isDPRRegList()) {
8627 Error(L, ".vsave expects DPR registers");
8631 getTargetStreamer().emitRegSave(Op->getRegList(), IsVector);
8635 /// parseDirectiveInst
8636 /// ::= .inst opcode [, ...]
8637 /// ::= .inst.n opcode [, ...]
8638 /// ::= .inst.w opcode [, ...]
8639 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
8651 Parser.eatToEndOfStatement();
8652 Error(Loc, "cannot determine Thumb instruction size, "
8653 "use inst.n/inst.w instead");
8658 Parser.eatToEndOfStatement();
8659 Error(Loc, "width suffixes are invalid in ARM mode");
8665 if (getLexer().is(AsmToken::EndOfStatement)) {
8666 Parser.eatToEndOfStatement();
8667 Error(Loc, "expected expression following directive");
8674 if (getParser().parseExpression(Expr)) {
8675 Error(Loc, "expected expression");
8679 const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
8681 Error(Loc, "expected constant expression");
8687 if (Value->getValue() > 0xffff) {
8688 Error(Loc, "inst.n operand is too big, use inst.w instead");
8693 if (Value->getValue() > 0xffffffff) {
8695 StringRef(Suffix ? "inst.w" : "inst") + " operand is too big");
8700 llvm_unreachable("only supported widths are 2 and 4");
8703 getTargetStreamer().emitInst(Value->getValue(), Suffix);
8705 if (getLexer().is(AsmToken::EndOfStatement))
8708 if (getLexer().isNot(AsmToken::Comma)) {
8709 Error(Loc, "unexpected token in directive");
8720 /// parseDirectiveLtorg
8721 /// ::= .ltorg | .pool
8722 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
8723 MCStreamer &Streamer = getParser().getStreamer();
8724 const MCSection *Section = Streamer.getCurrentSection().first;
8726 if (ConstantPool *CP = getConstantPool(Section)) {
8728 CP->emitEntries(Streamer);
8733 bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
8734 const MCSection *Section = getStreamer().getCurrentSection().first;
8736 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8737 TokError("unexpected token in directive");
8742 getStreamer().InitToTextSection();
8743 Section = getStreamer().getCurrentSection().first;
8746 if (Section->UseCodeAlign())
8747 getStreamer().EmitCodeAlignment(2, 0);
8749 getStreamer().EmitValueToAlignment(2, 0, 1, 0);
8754 /// Force static initialization.
8755 extern "C" void LLVMInitializeARMAsmParser() {
8756 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
8757 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
8760 #define GET_REGISTER_MATCHER
8761 #define GET_SUBTARGET_FEATURE_NAME
8762 #define GET_MATCHER_IMPLEMENTATION
8763 #include "ARMGenAsmMatcher.inc"
8765 // Define this matcher function after the auto-generated include so we
8766 // have the match class enum definitions.
8767 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
8769 ARMOperand *Op = static_cast<ARMOperand*>(AsmOp);
8770 // If the kind is a token for a literal immediate, check if our asm
8771 // operand matches. This is for InstAliases which have a fixed-value
8772 // immediate in the syntax.
8773 if (Kind == MCK__35_0 && Op->isImm()) {
8774 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
8776 return Match_InvalidOperand;
8777 if (CE->getValue() == 0)
8778 return Match_Success;
8780 return Match_InvalidOperand;
8783 void ARMAsmParser::finishParse() {
8784 // Dump contents of assembler constant pools.
8785 MCStreamer &Streamer = getParser().getStreamer();
8786 for (ConstantPoolMapTy::iterator CPI = ConstantPools.begin(),
8787 CPE = ConstantPools.end();
8788 CPI != CPE; ++CPI) {
8789 const MCSection *Section = CPI->first;
8790 ConstantPool &CP = CPI->second;
8792 // Dump non-empty assembler constant pools at the end of the section.
8794 Streamer.SwitchSection(Section);
8795 CP.emitEntries(Streamer);