1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMSubtarget.h"
12 #include "llvm/MC/MCParser/MCAsmLexer.h"
13 #include "llvm/MC/MCParser/MCAsmParser.h"
14 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
15 #include "llvm/MC/MCStreamer.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/Target/TargetRegistry.h"
19 #include "llvm/Target/TargetAsmParser.h"
20 #include "llvm/Support/SourceMgr.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/StringSwitch.h"
24 #include "llvm/ADT/Twine.h"
27 // The shift types for register controlled shifts in arm memory addressing
39 class ARMAsmParser : public TargetAsmParser {
44 MCAsmParser &getParser() const { return Parser; }
46 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
48 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
50 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
52 int TryParseRegister();
53 ARMOperand *TryParseRegisterWithWriteBack();
54 ARMOperand *ParseRegisterList();
55 ARMOperand *ParseMemory();
57 bool ParseMemoryOffsetReg(bool &Negative,
58 bool &OffsetRegShifted,
59 enum ShiftType &ShiftType,
60 const MCExpr *&ShiftAmount,
61 const MCExpr *&Offset,
66 bool ParseShift(enum ShiftType &St, const MCExpr *&ShiftAmount, SMLoc &E);
68 ARMOperand *ParseOperand();
70 bool ParseDirectiveWord(unsigned Size, SMLoc L);
72 bool ParseDirectiveThumb(SMLoc L);
74 bool ParseDirectiveThumbFunc(SMLoc L);
76 bool ParseDirectiveCode(SMLoc L);
78 bool ParseDirectiveSyntax(SMLoc L);
80 bool MatchAndEmitInstruction(SMLoc IDLoc,
81 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
84 /// @name Auto-generated Match Functions
87 #define GET_ASSEMBLER_HEADER
88 #include "ARMGenAsmMatcher.inc"
94 ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
95 : TargetAsmParser(T), Parser(_Parser), TM(_TM) {
96 // Initialize the set of available features.
97 setAvailableFeatures(ComputeAvailableFeatures(
98 &TM.getSubtarget<ARMSubtarget>()));
101 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
102 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
104 virtual bool ParseDirective(AsmToken DirectiveID);
106 } // end anonymous namespace
110 /// ARMOperand - Instances of this class represent a parsed ARM machine
112 struct ARMOperand : public MCParsedAsmOperand {
122 SMLoc StartLoc, EndLoc;
126 ARMCC::CondCodes Val;
143 // This is for all forms of ARM address expressions
146 unsigned OffsetRegNum; // used when OffsetIsReg is true
147 const MCExpr *Offset; // used when OffsetIsReg is false
148 const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
149 enum ShiftType ShiftType; // used when OffsetRegShifted is true
151 OffsetRegShifted : 1, // only used when OffsetIsReg is true
155 Negative : 1, // only used when OffsetIsReg is true
161 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
163 StartLoc = o.StartLoc;
184 /// getStartLoc - Get the location of the first token of this operand.
185 SMLoc getStartLoc() const { return StartLoc; }
186 /// getEndLoc - Get the location of the last token of this operand.
187 SMLoc getEndLoc() const { return EndLoc; }
189 ARMCC::CondCodes getCondCode() const {
190 assert(Kind == CondCode && "Invalid access!");
194 StringRef getToken() const {
195 assert(Kind == Token && "Invalid access!");
196 return StringRef(Tok.Data, Tok.Length);
199 unsigned getReg() const {
200 assert(Kind == Register && "Invalid access!");
204 const MCExpr *getImm() const {
205 assert(Kind == Immediate && "Invalid access!");
209 bool isCondCode() const { return Kind == CondCode; }
210 bool isImm() const { return Kind == Immediate; }
211 bool isReg() const { return Kind == Register; }
212 bool isToken() const { return Kind == Token; }
213 bool isMemory() const { return Kind == Memory; }
215 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
216 // Add as immediates when possible. Null MCExpr = 0.
218 Inst.addOperand(MCOperand::CreateImm(0));
219 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
220 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
222 Inst.addOperand(MCOperand::CreateExpr(Expr));
225 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
226 assert(N == 2 && "Invalid number of operands!");
227 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
228 // FIXME: What belongs here?
229 Inst.addOperand(MCOperand::CreateReg(0));
232 void addRegOperands(MCInst &Inst, unsigned N) const {
233 assert(N == 1 && "Invalid number of operands!");
234 Inst.addOperand(MCOperand::CreateReg(getReg()));
237 void addImmOperands(MCInst &Inst, unsigned N) const {
238 assert(N == 1 && "Invalid number of operands!");
239 addExpr(Inst, getImm());
243 bool isMemMode5() const {
244 if (!isMemory() || Mem.OffsetIsReg || Mem.OffsetRegShifted ||
245 Mem.Writeback || Mem.Negative)
247 // If there is an offset expression, make sure it's valid.
250 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
253 // The offset must be a multiple of 4 in the range 0-1020.
254 int64_t Value = CE->getValue();
255 return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020);
258 void addMemMode5Operands(MCInst &Inst, unsigned N) const {
259 assert(N == 2 && isMemMode5() && "Invalid number of operands!");
261 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
262 assert(!Mem.OffsetIsReg && "invalid mode 5 operand");
263 // FIXME: #-0 is encoded differently than #0. Does the parser preserve
266 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
267 assert(CE && "non-constant mode 5 offset operand!");
268 // The MCInst offset operand doesn't include the low two bits (like
269 // the instruction encoding).
270 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
272 Inst.addOperand(MCOperand::CreateImm(0));
275 virtual void dump(raw_ostream &OS) const;
277 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
278 ARMOperand *Op = new ARMOperand(CondCode);
285 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
286 ARMOperand *Op = new ARMOperand(Token);
287 Op->Tok.Data = Str.data();
288 Op->Tok.Length = Str.size();
294 static ARMOperand *CreateReg(unsigned RegNum, bool Writeback, SMLoc S,
296 ARMOperand *Op = new ARMOperand(Register);
297 Op->Reg.RegNum = RegNum;
298 Op->Reg.Writeback = Writeback;
304 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
305 ARMOperand *Op = new ARMOperand(Immediate);
312 static ARMOperand *CreateMem(unsigned BaseRegNum, bool OffsetIsReg,
313 const MCExpr *Offset, unsigned OffsetRegNum,
314 bool OffsetRegShifted, enum ShiftType ShiftType,
315 const MCExpr *ShiftAmount, bool Preindexed,
316 bool Postindexed, bool Negative, bool Writeback,
318 ARMOperand *Op = new ARMOperand(Memory);
319 Op->Mem.BaseRegNum = BaseRegNum;
320 Op->Mem.OffsetIsReg = OffsetIsReg;
321 Op->Mem.Offset = Offset;
322 Op->Mem.OffsetRegNum = OffsetRegNum;
323 Op->Mem.OffsetRegShifted = OffsetRegShifted;
324 Op->Mem.ShiftType = ShiftType;
325 Op->Mem.ShiftAmount = ShiftAmount;
326 Op->Mem.Preindexed = Preindexed;
327 Op->Mem.Postindexed = Postindexed;
328 Op->Mem.Negative = Negative;
329 Op->Mem.Writeback = Writeback;
337 ARMOperand(KindTy K) : Kind(K) {}
340 } // end anonymous namespace.
342 void ARMOperand::dump(raw_ostream &OS) const {
345 OS << ARMCondCodeToString(getCondCode());
354 OS << "<register " << getReg() << ">";
357 OS << "'" << getToken() << "'";
362 /// @name Auto-generated Match Functions
365 static unsigned MatchRegisterName(StringRef Name);
369 /// Try to parse a register name. The token must be an Identifier when called,
370 /// and if it is a register name the token is eaten and the register number is
371 /// returned. Otherwise return -1.
373 int ARMAsmParser::TryParseRegister() {
374 const AsmToken &Tok = Parser.getTok();
375 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
377 // FIXME: Validate register for the current architecture; we have to do
378 // validation later, so maybe there is no need for this here.
379 int RegNum = MatchRegisterName(Tok.getString());
382 Parser.Lex(); // Eat identifier token.
387 /// Try to parse a register name. The token must be an Identifier when called,
388 /// and if it is a register name the token is eaten and the register number is
389 /// returned. Otherwise return -1.
391 /// TODO this is likely to change to allow different register types and or to
392 /// parse for a specific register type.
393 ARMOperand *ARMAsmParser::TryParseRegisterWithWriteBack() {
394 SMLoc S = Parser.getTok().getLoc();
395 int RegNo = TryParseRegister();
396 if (RegNo == -1) return 0;
398 SMLoc E = Parser.getTok().getLoc();
400 bool Writeback = false;
401 const AsmToken &ExclaimTok = Parser.getTok();
402 if (ExclaimTok.is(AsmToken::Exclaim)) {
403 E = ExclaimTok.getLoc();
405 Parser.Lex(); // Eat exclaim token
408 return ARMOperand::CreateReg(RegNo, Writeback, S, E);
411 /// Parse a register list, return it if successful else return null. The first
412 /// token must be a '{' when called.
413 ARMOperand *ARMAsmParser::ParseRegisterList() {
415 assert(Parser.getTok().is(AsmToken::LCurly) &&
416 "Token is not an Left Curly Brace");
417 S = Parser.getTok().getLoc();
418 Parser.Lex(); // Eat left curly brace token.
420 const AsmToken &RegTok = Parser.getTok();
421 SMLoc RegLoc = RegTok.getLoc();
422 if (RegTok.isNot(AsmToken::Identifier)) {
423 Error(RegLoc, "register expected");
426 int RegNum = MatchRegisterName(RegTok.getString());
428 Error(RegLoc, "register expected");
432 Parser.Lex(); // Eat identifier token.
433 unsigned RegList = 1 << RegNum;
435 int HighRegNum = RegNum;
436 // TODO ranges like "{Rn-Rm}"
437 while (Parser.getTok().is(AsmToken::Comma)) {
438 Parser.Lex(); // Eat comma token.
440 const AsmToken &RegTok = Parser.getTok();
441 SMLoc RegLoc = RegTok.getLoc();
442 if (RegTok.isNot(AsmToken::Identifier)) {
443 Error(RegLoc, "register expected");
446 int RegNum = MatchRegisterName(RegTok.getString());
448 Error(RegLoc, "register expected");
452 if (RegList & (1 << RegNum))
453 Warning(RegLoc, "register duplicated in register list");
454 else if (RegNum <= HighRegNum)
455 Warning(RegLoc, "register not in ascending order in register list");
456 RegList |= 1 << RegNum;
459 Parser.Lex(); // Eat identifier token.
461 const AsmToken &RCurlyTok = Parser.getTok();
462 if (RCurlyTok.isNot(AsmToken::RCurly)) {
463 Error(RCurlyTok.getLoc(), "'}' expected");
466 E = RCurlyTok.getLoc();
467 Parser.Lex(); // Eat left curly brace token.
469 // FIXME: Need to return an operand!
470 Error(E, "FIXME: register list parsing not implemented");
474 /// Parse an arm memory expression, return false if successful else return true
475 /// or an error. The first token must be a '[' when called.
476 /// TODO Only preindexing and postindexing addressing are started, unindexed
477 /// with option, etc are still to do.
478 ARMOperand *ARMAsmParser::ParseMemory() {
480 assert(Parser.getTok().is(AsmToken::LBrac) &&
481 "Token is not an Left Bracket");
482 S = Parser.getTok().getLoc();
483 Parser.Lex(); // Eat left bracket token.
485 const AsmToken &BaseRegTok = Parser.getTok();
486 if (BaseRegTok.isNot(AsmToken::Identifier)) {
487 Error(BaseRegTok.getLoc(), "register expected");
490 int BaseRegNum = TryParseRegister();
491 if (BaseRegNum == -1) {
492 Error(BaseRegTok.getLoc(), "register expected");
496 bool Preindexed = false;
497 bool Postindexed = false;
498 bool OffsetIsReg = false;
499 bool Negative = false;
500 bool Writeback = false;
502 // First look for preindexed address forms, that is after the "[Rn" we now
503 // have to see if the next token is a comma.
504 const AsmToken &Tok = Parser.getTok();
505 if (Tok.is(AsmToken::Comma)) {
507 Parser.Lex(); // Eat comma token.
509 bool OffsetRegShifted;
510 enum ShiftType ShiftType;
511 const MCExpr *ShiftAmount;
512 const MCExpr *Offset;
513 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
514 Offset, OffsetIsReg, OffsetRegNum, E))
516 const AsmToken &RBracTok = Parser.getTok();
517 if (RBracTok.isNot(AsmToken::RBrac)) {
518 Error(RBracTok.getLoc(), "']' expected");
521 E = RBracTok.getLoc();
522 Parser.Lex(); // Eat right bracket token.
524 const AsmToken &ExclaimTok = Parser.getTok();
525 if (ExclaimTok.is(AsmToken::Exclaim)) {
526 E = ExclaimTok.getLoc();
528 Parser.Lex(); // Eat exclaim token
530 return ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
531 OffsetRegShifted, ShiftType, ShiftAmount,
532 Preindexed, Postindexed, Negative, Writeback,
535 // The "[Rn" we have so far was not followed by a comma.
536 else if (Tok.is(AsmToken::RBrac)) {
537 // If there's anything other than the right brace, this is a post indexing
540 Parser.Lex(); // Eat right bracket token.
542 int OffsetRegNum = 0;
543 bool OffsetRegShifted = false;
544 enum ShiftType ShiftType;
545 const MCExpr *ShiftAmount;
546 const MCExpr *Offset = 0;
548 const AsmToken &NextTok = Parser.getTok();
549 if (NextTok.isNot(AsmToken::EndOfStatement)) {
552 if (NextTok.isNot(AsmToken::Comma)) {
553 Error(NextTok.getLoc(), "',' expected");
556 Parser.Lex(); // Eat comma token.
557 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
558 ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
563 return ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
564 OffsetRegShifted, ShiftType, ShiftAmount,
565 Preindexed, Postindexed, Negative, Writeback,
572 /// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
573 /// we will parse the following (were +/- means that a plus or minus is
578 /// we return false on success or an error otherwise.
579 bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
580 bool &OffsetRegShifted,
581 enum ShiftType &ShiftType,
582 const MCExpr *&ShiftAmount,
583 const MCExpr *&Offset,
588 OffsetRegShifted = false;
591 const AsmToken &NextTok = Parser.getTok();
592 E = NextTok.getLoc();
593 if (NextTok.is(AsmToken::Plus))
594 Parser.Lex(); // Eat plus token.
595 else if (NextTok.is(AsmToken::Minus)) {
597 Parser.Lex(); // Eat minus token
599 // See if there is a register following the "[Rn," or "[Rn]," we have so far.
600 const AsmToken &OffsetRegTok = Parser.getTok();
601 if (OffsetRegTok.is(AsmToken::Identifier)) {
602 SMLoc CurLoc = OffsetRegTok.getLoc();
603 OffsetRegNum = TryParseRegister();
604 if (OffsetRegNum != -1) {
610 // If we parsed a register as the offset then their can be a shift after that
611 if (OffsetRegNum != -1) {
612 // Look for a comma then a shift
613 const AsmToken &Tok = Parser.getTok();
614 if (Tok.is(AsmToken::Comma)) {
615 Parser.Lex(); // Eat comma token.
617 const AsmToken &Tok = Parser.getTok();
618 if (ParseShift(ShiftType, ShiftAmount, E))
619 return Error(Tok.getLoc(), "shift expected");
620 OffsetRegShifted = true;
623 else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
624 // Look for #offset following the "[Rn," or "[Rn],"
625 const AsmToken &HashTok = Parser.getTok();
626 if (HashTok.isNot(AsmToken::Hash))
627 return Error(HashTok.getLoc(), "'#' expected");
629 Parser.Lex(); // Eat hash token.
631 if (getParser().ParseExpression(Offset))
633 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
638 /// ParseShift as one of these two:
639 /// ( lsl | lsr | asr | ror ) , # shift_amount
641 /// and returns true if it parses a shift otherwise it returns false.
642 bool ARMAsmParser::ParseShift(ShiftType &St, const MCExpr *&ShiftAmount,
644 const AsmToken &Tok = Parser.getTok();
645 if (Tok.isNot(AsmToken::Identifier))
647 StringRef ShiftName = Tok.getString();
648 if (ShiftName == "lsl" || ShiftName == "LSL")
650 else if (ShiftName == "lsr" || ShiftName == "LSR")
652 else if (ShiftName == "asr" || ShiftName == "ASR")
654 else if (ShiftName == "ror" || ShiftName == "ROR")
656 else if (ShiftName == "rrx" || ShiftName == "RRX")
660 Parser.Lex(); // Eat shift type token.
666 // Otherwise, there must be a '#' and a shift amount.
667 const AsmToken &HashTok = Parser.getTok();
668 if (HashTok.isNot(AsmToken::Hash))
669 return Error(HashTok.getLoc(), "'#' expected");
670 Parser.Lex(); // Eat hash token.
672 if (getParser().ParseExpression(ShiftAmount))
678 /// Parse a arm instruction operand. For now this parses the operand regardless
680 ARMOperand *ARMAsmParser::ParseOperand() {
683 switch (getLexer().getKind()) {
684 case AsmToken::Identifier:
685 if (ARMOperand *Op = TryParseRegisterWithWriteBack())
688 // This was not a register so parse other operands that start with an
689 // identifier (like labels) as expressions and create them as immediates.
691 S = Parser.getTok().getLoc();
692 if (getParser().ParseExpression(IdVal))
694 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
695 return ARMOperand::CreateImm(IdVal, S, E);
696 case AsmToken::LBrac:
697 return ParseMemory();
698 case AsmToken::LCurly:
699 return ParseRegisterList();
702 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
703 S = Parser.getTok().getLoc();
705 const MCExpr *ImmVal;
706 if (getParser().ParseExpression(ImmVal))
708 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
709 return ARMOperand::CreateImm(ImmVal, S, E);
711 Error(Parser.getTok().getLoc(), "unexpected token in operand");
716 /// Parse an arm instruction mnemonic followed by its operands.
717 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
718 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
719 // Create the leading tokens for the mnemonic, split by '.' characters.
720 size_t Start = 0, Next = Name.find('.');
721 StringRef Head = Name.slice(Start, Next);
723 // Determine the predicate, if any.
725 // FIXME: We need a way to check whether a prefix supports predication,
726 // otherwise we will end up with an ambiguity for instructions that happen to
727 // end with a predicate name.
728 // FIXME: Likewise, some arithmetic instructions have an 's' prefix which
729 // indicates to update the condition codes. Those instructions have an
730 // additional immediate operand which encodes the prefix as reg0 or CPSR.
731 // Just checking for a suffix of 's' definitely creates ambiguities; e.g,
732 // the SMMLS instruction.
733 unsigned CC = StringSwitch<unsigned>(Head.substr(Head.size()-2))
734 .Case("eq", ARMCC::EQ)
735 .Case("ne", ARMCC::NE)
736 .Case("hs", ARMCC::HS)
737 .Case("lo", ARMCC::LO)
738 .Case("mi", ARMCC::MI)
739 .Case("pl", ARMCC::PL)
740 .Case("vs", ARMCC::VS)
741 .Case("vc", ARMCC::VC)
742 .Case("hi", ARMCC::HI)
743 .Case("ls", ARMCC::LS)
744 .Case("ge", ARMCC::GE)
745 .Case("lt", ARMCC::LT)
746 .Case("gt", ARMCC::GT)
747 .Case("le", ARMCC::LE)
748 .Case("al", ARMCC::AL)
752 (CC == ARMCC::LS && (Head == "vmls" || Head == "vnmls"))) {
755 Head = Head.slice(0, Head.size() - 2);
758 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
759 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), NameLoc));
761 // Add the remaining tokens in the mnemonic.
762 while (Next != StringRef::npos) {
764 Next = Name.find('.', Start + 1);
765 Head = Name.slice(Start, Next);
767 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
770 // Read the remaining operands.
771 if (getLexer().isNot(AsmToken::EndOfStatement)) {
772 // Read the first operand.
773 if (ARMOperand *Op = ParseOperand())
774 Operands.push_back(Op);
776 Parser.EatToEndOfStatement();
780 while (getLexer().is(AsmToken::Comma)) {
781 Parser.Lex(); // Eat the comma.
783 // Parse and remember the operand.
784 if (ARMOperand *Op = ParseOperand())
785 Operands.push_back(Op);
787 Parser.EatToEndOfStatement();
793 if (getLexer().isNot(AsmToken::EndOfStatement)) {
794 Parser.EatToEndOfStatement();
795 return TokError("unexpected token in argument list");
797 Parser.Lex(); // Consume the EndOfStatement
802 MatchAndEmitInstruction(SMLoc IDLoc,
803 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
807 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo)) {
809 Out.EmitInstruction(Inst);
812 case Match_MissingFeature:
813 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
815 case Match_InvalidOperand: {
816 SMLoc ErrorLoc = IDLoc;
817 if (ErrorInfo != ~0U) {
818 if (ErrorInfo >= Operands.size())
819 return Error(IDLoc, "too few operands for instruction");
821 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
822 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
825 return Error(ErrorLoc, "invalid operand for instruction");
827 case Match_MnemonicFail:
828 return Error(IDLoc, "unrecognized instruction mnemonic");
831 llvm_unreachable("Implement any new match types added!");
836 /// ParseDirective parses the arm specific directives
837 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
838 StringRef IDVal = DirectiveID.getIdentifier();
839 if (IDVal == ".word")
840 return ParseDirectiveWord(4, DirectiveID.getLoc());
841 else if (IDVal == ".thumb")
842 return ParseDirectiveThumb(DirectiveID.getLoc());
843 else if (IDVal == ".thumb_func")
844 return ParseDirectiveThumbFunc(DirectiveID.getLoc());
845 else if (IDVal == ".code")
846 return ParseDirectiveCode(DirectiveID.getLoc());
847 else if (IDVal == ".syntax")
848 return ParseDirectiveSyntax(DirectiveID.getLoc());
852 /// ParseDirectiveWord
853 /// ::= .word [ expression (, expression)* ]
854 bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
855 if (getLexer().isNot(AsmToken::EndOfStatement)) {
858 if (getParser().ParseExpression(Value))
861 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
863 if (getLexer().is(AsmToken::EndOfStatement))
866 // FIXME: Improve diagnostic.
867 if (getLexer().isNot(AsmToken::Comma))
868 return Error(L, "unexpected token in directive");
877 /// ParseDirectiveThumb
879 bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
880 if (getLexer().isNot(AsmToken::EndOfStatement))
881 return Error(L, "unexpected token in directive");
884 // TODO: set thumb mode
885 // TODO: tell the MC streamer the mode
886 // getParser().getStreamer().Emit???();
890 /// ParseDirectiveThumbFunc
891 /// ::= .thumbfunc symbol_name
892 bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
893 const AsmToken &Tok = Parser.getTok();
894 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
895 return Error(L, "unexpected token in .syntax directive");
896 Parser.Lex(); // Consume the identifier token.
898 if (getLexer().isNot(AsmToken::EndOfStatement))
899 return Error(L, "unexpected token in directive");
902 // TODO: mark symbol as a thumb symbol
903 // getParser().getStreamer().Emit???();
907 /// ParseDirectiveSyntax
908 /// ::= .syntax unified | divided
909 bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
910 const AsmToken &Tok = Parser.getTok();
911 if (Tok.isNot(AsmToken::Identifier))
912 return Error(L, "unexpected token in .syntax directive");
913 StringRef Mode = Tok.getString();
914 if (Mode == "unified" || Mode == "UNIFIED")
916 else if (Mode == "divided" || Mode == "DIVIDED")
919 return Error(L, "unrecognized syntax mode in .syntax directive");
921 if (getLexer().isNot(AsmToken::EndOfStatement))
922 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
925 // TODO tell the MC streamer the mode
926 // getParser().getStreamer().Emit???();
930 /// ParseDirectiveCode
931 /// ::= .code 16 | 32
932 bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
933 const AsmToken &Tok = Parser.getTok();
934 if (Tok.isNot(AsmToken::Integer))
935 return Error(L, "unexpected token in .code directive");
936 int64_t Val = Parser.getTok().getIntVal();
942 return Error(L, "invalid operand to .code directive");
944 if (getLexer().isNot(AsmToken::EndOfStatement))
945 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
948 // TODO tell the MC streamer the mode
949 // getParser().getStreamer().Emit???();
953 extern "C" void LLVMInitializeARMAsmLexer();
955 /// Force static initialization.
956 extern "C" void LLVMInitializeARMAsmParser() {
957 RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
958 RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
959 LLVMInitializeARMAsmLexer();
962 #define GET_REGISTER_MATCHER
963 #define GET_MATCHER_IMPLEMENTATION
964 #include "ARMGenAsmMatcher.inc"