1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMBaseInfo.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMMCExpr.h"
13 #include "llvm/MC/MCParser/MCAsmLexer.h"
14 #include "llvm/MC/MCParser/MCAsmParser.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCAsmInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCTargetAsmParser.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/SourceMgr.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/ADT/BitVector.h"
30 #include "llvm/ADT/OwningPtr.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/StringSwitch.h"
34 #include "llvm/ADT/Twine.h"
42 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
44 class ARMAsmParser : public MCTargetAsmParser {
49 ARMCC::CondCodes Cond; // Condition for IT block.
50 unsigned Mask:4; // Condition mask for instructions.
51 // Starting at first 1 (from lsb).
52 // '1' condition as indicated in IT.
53 // '0' inverse of condition (else).
54 // Count of instructions in IT block is
55 // 4 - trailingzeroes(mask)
57 bool FirstCond; // Explicit flag for when we're parsing the
58 // First instruction in the IT block. It's
59 // implied in the mask, so needs special
62 unsigned CurPosition; // Current position in parsing of IT
63 // block. In range [0,3]. Initialized
64 // according to count of instructions in block.
65 // ~0U if no active IT block.
67 bool inITBlock() { return ITState.CurPosition != ~0U;}
68 void forwardITPosition() {
69 if (!inITBlock()) return;
70 // Move to the next instruction in the IT block, if there is one. If not,
71 // mark the block as done.
72 unsigned TZ = CountTrailingZeros_32(ITState.Mask);
73 if (++ITState.CurPosition == 5 - TZ)
74 ITState.CurPosition = ~0U; // Done with the IT block after this.
78 MCAsmParser &getParser() const { return Parser; }
79 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
81 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
82 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
84 int tryParseRegister();
85 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
86 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
87 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
88 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
89 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
90 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
91 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
92 unsigned &ShiftAmount);
93 bool parseDirectiveWord(unsigned Size, SMLoc L);
94 bool parseDirectiveThumb(SMLoc L);
95 bool parseDirectiveARM(SMLoc L);
96 bool parseDirectiveThumbFunc(SMLoc L);
97 bool parseDirectiveCode(SMLoc L);
98 bool parseDirectiveSyntax(SMLoc L);
100 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
101 bool &CarrySetting, unsigned &ProcessorIMod,
103 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
104 bool &CanAcceptPredicationCode);
106 bool isThumb() const {
107 // FIXME: Can tablegen auto-generate this?
108 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
110 bool isThumbOne() const {
111 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
113 bool isThumbTwo() const {
114 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
116 bool hasV6Ops() const {
117 return STI.getFeatureBits() & ARM::HasV6Ops;
119 bool hasV7Ops() const {
120 return STI.getFeatureBits() & ARM::HasV7Ops;
123 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
124 setAvailableFeatures(FB);
126 bool isMClass() const {
127 return STI.getFeatureBits() & ARM::FeatureMClass;
130 /// @name Auto-generated Match Functions
133 #define GET_ASSEMBLER_HEADER
134 #include "ARMGenAsmMatcher.inc"
138 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
139 OperandMatchResultTy parseCoprocNumOperand(
140 SmallVectorImpl<MCParsedAsmOperand*>&);
141 OperandMatchResultTy parseCoprocRegOperand(
142 SmallVectorImpl<MCParsedAsmOperand*>&);
143 OperandMatchResultTy parseCoprocOptionOperand(
144 SmallVectorImpl<MCParsedAsmOperand*>&);
145 OperandMatchResultTy parseMemBarrierOptOperand(
146 SmallVectorImpl<MCParsedAsmOperand*>&);
147 OperandMatchResultTy parseProcIFlagsOperand(
148 SmallVectorImpl<MCParsedAsmOperand*>&);
149 OperandMatchResultTy parseMSRMaskOperand(
150 SmallVectorImpl<MCParsedAsmOperand*>&);
151 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
152 StringRef Op, int Low, int High);
153 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
154 return parsePKHImm(O, "lsl", 0, 31);
156 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
157 return parsePKHImm(O, "asr", 1, 32);
159 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
160 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
161 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
162 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
163 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
164 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
165 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
166 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
167 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index);
169 // Asm Match Converter Methods
170 bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
171 const SmallVectorImpl<MCParsedAsmOperand*> &);
172 bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
173 const SmallVectorImpl<MCParsedAsmOperand*> &);
174 bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
175 const SmallVectorImpl<MCParsedAsmOperand*> &);
176 bool cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
177 const SmallVectorImpl<MCParsedAsmOperand*> &);
178 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
179 const SmallVectorImpl<MCParsedAsmOperand*> &);
180 bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
181 const SmallVectorImpl<MCParsedAsmOperand*> &);
182 bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
183 const SmallVectorImpl<MCParsedAsmOperand*> &);
184 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
185 const SmallVectorImpl<MCParsedAsmOperand*> &);
186 bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
187 const SmallVectorImpl<MCParsedAsmOperand*> &);
188 bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
189 const SmallVectorImpl<MCParsedAsmOperand*> &);
190 bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
191 const SmallVectorImpl<MCParsedAsmOperand*> &);
192 bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
193 const SmallVectorImpl<MCParsedAsmOperand*> &);
194 bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
195 const SmallVectorImpl<MCParsedAsmOperand*> &);
196 bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
197 const SmallVectorImpl<MCParsedAsmOperand*> &);
198 bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
199 const SmallVectorImpl<MCParsedAsmOperand*> &);
200 bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
201 const SmallVectorImpl<MCParsedAsmOperand*> &);
202 bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
203 const SmallVectorImpl<MCParsedAsmOperand*> &);
204 bool cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
205 const SmallVectorImpl<MCParsedAsmOperand*> &);
206 bool cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
207 const SmallVectorImpl<MCParsedAsmOperand*> &);
208 bool cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
209 const SmallVectorImpl<MCParsedAsmOperand*> &);
210 bool cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
211 const SmallVectorImpl<MCParsedAsmOperand*> &);
213 bool validateInstruction(MCInst &Inst,
214 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
215 bool processInstruction(MCInst &Inst,
216 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
217 bool shouldOmitCCOutOperand(StringRef Mnemonic,
218 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
221 enum ARMMatchResultTy {
222 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
223 Match_RequiresNotITBlock,
228 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
229 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
230 MCAsmParserExtension::Initialize(_Parser);
232 // Initialize the set of available features.
233 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
235 // Not in an ITBlock to start with.
236 ITState.CurPosition = ~0U;
239 // Implementation of the MCTargetAsmParser interface:
240 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
241 bool ParseInstruction(StringRef Name, SMLoc NameLoc,
242 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
243 bool ParseDirective(AsmToken DirectiveID);
245 unsigned checkTargetMatchPredicate(MCInst &Inst);
247 bool MatchAndEmitInstruction(SMLoc IDLoc,
248 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
251 } // end anonymous namespace
255 /// ARMOperand - Instances of this class represent a parsed ARM machine
257 class ARMOperand : public MCParsedAsmOperand {
278 k_VectorListAllLanes,
284 k_BitfieldDescriptor,
288 SMLoc StartLoc, EndLoc;
289 SmallVector<unsigned, 8> Registers;
293 ARMCC::CondCodes Val;
313 ARM_PROC::IFlags Val;
329 // A vector register list is a sequential list of 1 to 4 registers.
345 unsigned Val; // encoded 8-bit representation
348 /// Combined record for all forms of ARM address expressions.
351 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
353 const MCConstantExpr *OffsetImm; // Offset immediate value
354 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
355 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
356 unsigned ShiftImm; // shift for OffsetReg.
357 unsigned Alignment; // 0 = no alignment specified
358 // n = alignment in bytes (8, 16, or 32)
359 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
365 ARM_AM::ShiftOpc ShiftTy;
374 ARM_AM::ShiftOpc ShiftTy;
380 ARM_AM::ShiftOpc ShiftTy;
393 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
395 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
397 StartLoc = o.StartLoc;
414 case k_DPRRegisterList:
415 case k_SPRRegisterList:
416 Registers = o.Registers;
419 case k_VectorListAllLanes:
420 case k_VectorListIndexed:
421 VectorList = o.VectorList;
428 CoprocOption = o.CoprocOption;
436 case k_MemBarrierOpt:
442 case k_PostIndexRegister:
443 PostIdxReg = o.PostIdxReg;
451 case k_ShifterImmediate:
452 ShifterImm = o.ShifterImm;
454 case k_ShiftedRegister:
455 RegShiftedReg = o.RegShiftedReg;
457 case k_ShiftedImmediate:
458 RegShiftedImm = o.RegShiftedImm;
460 case k_RotateImmediate:
463 case k_BitfieldDescriptor:
464 Bitfield = o.Bitfield;
467 VectorIndex = o.VectorIndex;
472 /// getStartLoc - Get the location of the first token of this operand.
473 SMLoc getStartLoc() const { return StartLoc; }
474 /// getEndLoc - Get the location of the last token of this operand.
475 SMLoc getEndLoc() const { return EndLoc; }
477 ARMCC::CondCodes getCondCode() const {
478 assert(Kind == k_CondCode && "Invalid access!");
482 unsigned getCoproc() const {
483 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
487 StringRef getToken() const {
488 assert(Kind == k_Token && "Invalid access!");
489 return StringRef(Tok.Data, Tok.Length);
492 unsigned getReg() const {
493 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
497 const SmallVectorImpl<unsigned> &getRegList() const {
498 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
499 Kind == k_SPRRegisterList) && "Invalid access!");
503 const MCExpr *getImm() const {
504 assert(Kind == k_Immediate && "Invalid access!");
508 unsigned getFPImm() const {
509 assert(Kind == k_FPImmediate && "Invalid access!");
513 unsigned getVectorIndex() const {
514 assert(Kind == k_VectorIndex && "Invalid access!");
515 return VectorIndex.Val;
518 ARM_MB::MemBOpt getMemBarrierOpt() const {
519 assert(Kind == k_MemBarrierOpt && "Invalid access!");
523 ARM_PROC::IFlags getProcIFlags() const {
524 assert(Kind == k_ProcIFlags && "Invalid access!");
528 unsigned getMSRMask() const {
529 assert(Kind == k_MSRMask && "Invalid access!");
533 bool isCoprocNum() const { return Kind == k_CoprocNum; }
534 bool isCoprocReg() const { return Kind == k_CoprocReg; }
535 bool isCoprocOption() const { return Kind == k_CoprocOption; }
536 bool isCondCode() const { return Kind == k_CondCode; }
537 bool isCCOut() const { return Kind == k_CCOut; }
538 bool isITMask() const { return Kind == k_ITCondMask; }
539 bool isITCondCode() const { return Kind == k_CondCode; }
540 bool isImm() const { return Kind == k_Immediate; }
541 bool isFPImm() const { return Kind == k_FPImmediate; }
542 bool isImm8s4() const {
543 if (Kind != k_Immediate)
545 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
546 if (!CE) return false;
547 int64_t Value = CE->getValue();
548 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
550 bool isImm0_1020s4() const {
551 if (Kind != k_Immediate)
553 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
554 if (!CE) return false;
555 int64_t Value = CE->getValue();
556 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
558 bool isImm0_508s4() const {
559 if (Kind != k_Immediate)
561 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
562 if (!CE) return false;
563 int64_t Value = CE->getValue();
564 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
566 bool isImm0_255() const {
567 if (Kind != k_Immediate)
569 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
570 if (!CE) return false;
571 int64_t Value = CE->getValue();
572 return Value >= 0 && Value < 256;
574 bool isImm0_1() const {
575 if (Kind != k_Immediate)
577 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
578 if (!CE) return false;
579 int64_t Value = CE->getValue();
580 return Value >= 0 && Value < 2;
582 bool isImm0_3() const {
583 if (Kind != k_Immediate)
585 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
586 if (!CE) return false;
587 int64_t Value = CE->getValue();
588 return Value >= 0 && Value < 4;
590 bool isImm0_7() const {
591 if (Kind != k_Immediate)
593 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
594 if (!CE) return false;
595 int64_t Value = CE->getValue();
596 return Value >= 0 && Value < 8;
598 bool isImm0_15() const {
599 if (Kind != k_Immediate)
601 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
602 if (!CE) return false;
603 int64_t Value = CE->getValue();
604 return Value >= 0 && Value < 16;
606 bool isImm0_31() const {
607 if (Kind != k_Immediate)
609 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
610 if (!CE) return false;
611 int64_t Value = CE->getValue();
612 return Value >= 0 && Value < 32;
614 bool isImm0_63() const {
615 if (Kind != k_Immediate)
617 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
618 if (!CE) return false;
619 int64_t Value = CE->getValue();
620 return Value >= 0 && Value < 64;
622 bool isImm8() const {
623 if (Kind != k_Immediate)
625 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
626 if (!CE) return false;
627 int64_t Value = CE->getValue();
630 bool isImm16() const {
631 if (Kind != k_Immediate)
633 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
634 if (!CE) return false;
635 int64_t Value = CE->getValue();
638 bool isImm32() const {
639 if (Kind != k_Immediate)
641 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
642 if (!CE) return false;
643 int64_t Value = CE->getValue();
646 bool isShrImm8() const {
647 if (Kind != k_Immediate)
649 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
650 if (!CE) return false;
651 int64_t Value = CE->getValue();
652 return Value > 0 && Value <= 8;
654 bool isShrImm16() const {
655 if (Kind != k_Immediate)
657 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
658 if (!CE) return false;
659 int64_t Value = CE->getValue();
660 return Value > 0 && Value <= 16;
662 bool isShrImm32() const {
663 if (Kind != k_Immediate)
665 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
666 if (!CE) return false;
667 int64_t Value = CE->getValue();
668 return Value > 0 && Value <= 32;
670 bool isShrImm64() const {
671 if (Kind != k_Immediate)
673 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
674 if (!CE) return false;
675 int64_t Value = CE->getValue();
676 return Value > 0 && Value <= 64;
678 bool isImm1_7() const {
679 if (Kind != k_Immediate)
681 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
682 if (!CE) return false;
683 int64_t Value = CE->getValue();
684 return Value > 0 && Value < 8;
686 bool isImm1_15() const {
687 if (Kind != k_Immediate)
689 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
690 if (!CE) return false;
691 int64_t Value = CE->getValue();
692 return Value > 0 && Value < 16;
694 bool isImm1_31() const {
695 if (Kind != k_Immediate)
697 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
698 if (!CE) return false;
699 int64_t Value = CE->getValue();
700 return Value > 0 && Value < 32;
702 bool isImm1_16() const {
703 if (Kind != k_Immediate)
705 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
706 if (!CE) return false;
707 int64_t Value = CE->getValue();
708 return Value > 0 && Value < 17;
710 bool isImm1_32() const {
711 if (Kind != k_Immediate)
713 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
714 if (!CE) return false;
715 int64_t Value = CE->getValue();
716 return Value > 0 && Value < 33;
718 bool isImm0_32() const {
719 if (Kind != k_Immediate)
721 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
722 if (!CE) return false;
723 int64_t Value = CE->getValue();
724 return Value >= 0 && Value < 33;
726 bool isImm0_65535() const {
727 if (Kind != k_Immediate)
729 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
730 if (!CE) return false;
731 int64_t Value = CE->getValue();
732 return Value >= 0 && Value < 65536;
734 bool isImm0_65535Expr() const {
735 if (Kind != k_Immediate)
737 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
738 // If it's not a constant expression, it'll generate a fixup and be
740 if (!CE) return true;
741 int64_t Value = CE->getValue();
742 return Value >= 0 && Value < 65536;
744 bool isImm24bit() const {
745 if (Kind != k_Immediate)
747 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
748 if (!CE) return false;
749 int64_t Value = CE->getValue();
750 return Value >= 0 && Value <= 0xffffff;
752 bool isImmThumbSR() const {
753 if (Kind != k_Immediate)
755 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
756 if (!CE) return false;
757 int64_t Value = CE->getValue();
758 return Value > 0 && Value < 33;
760 bool isPKHLSLImm() const {
761 if (Kind != k_Immediate)
763 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
764 if (!CE) return false;
765 int64_t Value = CE->getValue();
766 return Value >= 0 && Value < 32;
768 bool isPKHASRImm() const {
769 if (Kind != k_Immediate)
771 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
772 if (!CE) return false;
773 int64_t Value = CE->getValue();
774 return Value > 0 && Value <= 32;
776 bool isARMSOImm() const {
777 if (Kind != k_Immediate)
779 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
780 if (!CE) return false;
781 int64_t Value = CE->getValue();
782 return ARM_AM::getSOImmVal(Value) != -1;
784 bool isARMSOImmNot() const {
785 if (Kind != k_Immediate)
787 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
788 if (!CE) return false;
789 int64_t Value = CE->getValue();
790 return ARM_AM::getSOImmVal(~Value) != -1;
792 bool isARMSOImmNeg() const {
793 if (Kind != k_Immediate)
795 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
796 if (!CE) return false;
797 int64_t Value = CE->getValue();
798 return ARM_AM::getSOImmVal(-Value) != -1;
800 bool isT2SOImm() const {
801 if (Kind != k_Immediate)
803 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
804 if (!CE) return false;
805 int64_t Value = CE->getValue();
806 return ARM_AM::getT2SOImmVal(Value) != -1;
808 bool isT2SOImmNot() const {
809 if (Kind != k_Immediate)
811 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
812 if (!CE) return false;
813 int64_t Value = CE->getValue();
814 return ARM_AM::getT2SOImmVal(~Value) != -1;
816 bool isT2SOImmNeg() const {
817 if (Kind != k_Immediate)
819 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
820 if (!CE) return false;
821 int64_t Value = CE->getValue();
822 return ARM_AM::getT2SOImmVal(-Value) != -1;
824 bool isSetEndImm() const {
825 if (Kind != k_Immediate)
827 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
828 if (!CE) return false;
829 int64_t Value = CE->getValue();
830 return Value == 1 || Value == 0;
832 bool isReg() const { return Kind == k_Register; }
833 bool isRegList() const { return Kind == k_RegisterList; }
834 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
835 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
836 bool isToken() const { return Kind == k_Token; }
837 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
838 bool isMemory() const { return Kind == k_Memory; }
839 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
840 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
841 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
842 bool isRotImm() const { return Kind == k_RotateImmediate; }
843 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
844 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
845 bool isPostIdxReg() const {
846 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
848 bool isMemNoOffset(bool alignOK = false) const {
851 // No offset of any kind.
852 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
853 (alignOK || Memory.Alignment == 0);
855 bool isAlignedMemory() const {
856 return isMemNoOffset(true);
858 bool isAddrMode2() const {
859 if (!isMemory() || Memory.Alignment != 0) return false;
860 // Check for register offset.
861 if (Memory.OffsetRegNum) return true;
862 // Immediate offset in range [-4095, 4095].
863 if (!Memory.OffsetImm) return true;
864 int64_t Val = Memory.OffsetImm->getValue();
865 return Val > -4096 && Val < 4096;
867 bool isAM2OffsetImm() const {
868 if (Kind != k_Immediate)
870 // Immediate offset in range [-4095, 4095].
871 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
872 if (!CE) return false;
873 int64_t Val = CE->getValue();
874 return Val > -4096 && Val < 4096;
876 bool isAddrMode3() const {
877 if (!isMemory() || Memory.Alignment != 0) return false;
878 // No shifts are legal for AM3.
879 if (Memory.ShiftType != ARM_AM::no_shift) return false;
880 // Check for register offset.
881 if (Memory.OffsetRegNum) return true;
882 // Immediate offset in range [-255, 255].
883 if (!Memory.OffsetImm) return true;
884 int64_t Val = Memory.OffsetImm->getValue();
885 return Val > -256 && Val < 256;
887 bool isAM3Offset() const {
888 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
890 if (Kind == k_PostIndexRegister)
891 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
892 // Immediate offset in range [-255, 255].
893 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
894 if (!CE) return false;
895 int64_t Val = CE->getValue();
896 // Special case, #-0 is INT32_MIN.
897 return (Val > -256 && Val < 256) || Val == INT32_MIN;
899 bool isAddrMode5() const {
900 // If we have an immediate that's not a constant, treat it as a label
901 // reference needing a fixup. If it is a constant, it's something else
903 if (Kind == k_Immediate && !isa<MCConstantExpr>(getImm()))
905 if (!isMemory() || Memory.Alignment != 0) return false;
906 // Check for register offset.
907 if (Memory.OffsetRegNum) return false;
908 // Immediate offset in range [-1020, 1020] and a multiple of 4.
909 if (!Memory.OffsetImm) return true;
910 int64_t Val = Memory.OffsetImm->getValue();
911 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
914 bool isMemTBB() const {
915 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
916 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
920 bool isMemTBH() const {
921 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
922 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
923 Memory.Alignment != 0 )
927 bool isMemRegOffset() const {
928 if (!isMemory() || !Memory.OffsetRegNum || Memory.Alignment != 0)
932 bool isT2MemRegOffset() const {
933 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
934 Memory.Alignment != 0)
936 // Only lsl #{0, 1, 2, 3} allowed.
937 if (Memory.ShiftType == ARM_AM::no_shift)
939 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
943 bool isMemThumbRR() const {
944 // Thumb reg+reg addressing is simple. Just two registers, a base and
945 // an offset. No shifts, negations or any other complicating factors.
946 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
947 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
949 return isARMLowRegister(Memory.BaseRegNum) &&
950 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
952 bool isMemThumbRIs4() const {
953 if (!isMemory() || Memory.OffsetRegNum != 0 ||
954 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
956 // Immediate offset, multiple of 4 in range [0, 124].
957 if (!Memory.OffsetImm) return true;
958 int64_t Val = Memory.OffsetImm->getValue();
959 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
961 bool isMemThumbRIs2() const {
962 if (!isMemory() || Memory.OffsetRegNum != 0 ||
963 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
965 // Immediate offset, multiple of 4 in range [0, 62].
966 if (!Memory.OffsetImm) return true;
967 int64_t Val = Memory.OffsetImm->getValue();
968 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
970 bool isMemThumbRIs1() const {
971 if (!isMemory() || Memory.OffsetRegNum != 0 ||
972 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
974 // Immediate offset in range [0, 31].
975 if (!Memory.OffsetImm) return true;
976 int64_t Val = Memory.OffsetImm->getValue();
977 return Val >= 0 && Val <= 31;
979 bool isMemThumbSPI() const {
980 if (!isMemory() || Memory.OffsetRegNum != 0 ||
981 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
983 // Immediate offset, multiple of 4 in range [0, 1020].
984 if (!Memory.OffsetImm) return true;
985 int64_t Val = Memory.OffsetImm->getValue();
986 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
988 bool isMemImm8s4Offset() const {
989 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
991 // Immediate offset a multiple of 4 in range [-1020, 1020].
992 if (!Memory.OffsetImm) return true;
993 int64_t Val = Memory.OffsetImm->getValue();
994 return Val >= -1020 && Val <= 1020 && (Val & 3) == 0;
996 bool isMemImm0_1020s4Offset() const {
997 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
999 // Immediate offset a multiple of 4 in range [0, 1020].
1000 if (!Memory.OffsetImm) return true;
1001 int64_t Val = Memory.OffsetImm->getValue();
1002 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1004 bool isMemImm8Offset() const {
1005 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1007 // Immediate offset in range [-255, 255].
1008 if (!Memory.OffsetImm) return true;
1009 int64_t Val = Memory.OffsetImm->getValue();
1010 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1012 bool isMemPosImm8Offset() const {
1013 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1015 // Immediate offset in range [0, 255].
1016 if (!Memory.OffsetImm) return true;
1017 int64_t Val = Memory.OffsetImm->getValue();
1018 return Val >= 0 && Val < 256;
1020 bool isMemNegImm8Offset() const {
1021 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1023 // Immediate offset in range [-255, -1].
1024 if (!Memory.OffsetImm) return false;
1025 int64_t Val = Memory.OffsetImm->getValue();
1026 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1028 bool isMemUImm12Offset() const {
1029 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1031 // Immediate offset in range [0, 4095].
1032 if (!Memory.OffsetImm) return true;
1033 int64_t Val = Memory.OffsetImm->getValue();
1034 return (Val >= 0 && Val < 4096);
1036 bool isMemImm12Offset() const {
1037 // If we have an immediate that's not a constant, treat it as a label
1038 // reference needing a fixup. If it is a constant, it's something else
1039 // and we reject it.
1040 if (Kind == k_Immediate && !isa<MCConstantExpr>(getImm()))
1043 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1045 // Immediate offset in range [-4095, 4095].
1046 if (!Memory.OffsetImm) return true;
1047 int64_t Val = Memory.OffsetImm->getValue();
1048 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1050 bool isPostIdxImm8() const {
1051 if (Kind != k_Immediate)
1053 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1054 if (!CE) return false;
1055 int64_t Val = CE->getValue();
1056 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1058 bool isPostIdxImm8s4() const {
1059 if (Kind != k_Immediate)
1061 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1062 if (!CE) return false;
1063 int64_t Val = CE->getValue();
1064 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1068 bool isMSRMask() const { return Kind == k_MSRMask; }
1069 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1072 bool isVecListOneD() const {
1073 if (Kind != k_VectorList) return false;
1074 return VectorList.Count == 1;
1077 bool isVecListTwoD() const {
1078 if (Kind != k_VectorList) return false;
1079 return VectorList.Count == 2;
1082 bool isVecListThreeD() const {
1083 if (Kind != k_VectorList) return false;
1084 return VectorList.Count == 3;
1087 bool isVecListFourD() const {
1088 if (Kind != k_VectorList) return false;
1089 return VectorList.Count == 4;
1092 bool isVecListTwoQ() const {
1093 if (Kind != k_VectorList) return false;
1094 //FIXME: We haven't taught the parser to handle by-two register lists
1095 // yet, so don't pretend to know one.
1096 return VectorList.Count == 2 && false;
1099 bool isVecListOneDAllLanes() const {
1100 if (Kind != k_VectorListAllLanes) return false;
1101 return VectorList.Count == 1;
1104 bool isVecListTwoDAllLanes() const {
1105 if (Kind != k_VectorListAllLanes) return false;
1106 return VectorList.Count == 2;
1109 bool isVecListOneDByteIndexed() const {
1110 if (Kind != k_VectorListIndexed) return false;
1111 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1114 bool isVectorIndex8() const {
1115 if (Kind != k_VectorIndex) return false;
1116 return VectorIndex.Val < 8;
1118 bool isVectorIndex16() const {
1119 if (Kind != k_VectorIndex) return false;
1120 return VectorIndex.Val < 4;
1122 bool isVectorIndex32() const {
1123 if (Kind != k_VectorIndex) return false;
1124 return VectorIndex.Val < 2;
1127 bool isNEONi8splat() const {
1128 if (Kind != k_Immediate)
1130 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1131 // Must be a constant.
1132 if (!CE) return false;
1133 int64_t Value = CE->getValue();
1134 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1136 return Value >= 0 && Value < 256;
1139 bool isNEONi16splat() const {
1140 if (Kind != k_Immediate)
1142 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1143 // Must be a constant.
1144 if (!CE) return false;
1145 int64_t Value = CE->getValue();
1146 // i16 value in the range [0,255] or [0x0100, 0xff00]
1147 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1150 bool isNEONi32splat() const {
1151 if (Kind != k_Immediate)
1153 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1154 // Must be a constant.
1155 if (!CE) return false;
1156 int64_t Value = CE->getValue();
1157 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1158 return (Value >= 0 && Value < 256) ||
1159 (Value >= 0x0100 && Value <= 0xff00) ||
1160 (Value >= 0x010000 && Value <= 0xff0000) ||
1161 (Value >= 0x01000000 && Value <= 0xff000000);
1164 bool isNEONi32vmov() const {
1165 if (Kind != k_Immediate)
1167 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1168 // Must be a constant.
1169 if (!CE) return false;
1170 int64_t Value = CE->getValue();
1171 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1172 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1173 return (Value >= 0 && Value < 256) ||
1174 (Value >= 0x0100 && Value <= 0xff00) ||
1175 (Value >= 0x010000 && Value <= 0xff0000) ||
1176 (Value >= 0x01000000 && Value <= 0xff000000) ||
1177 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1178 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1181 bool isNEONi64splat() const {
1182 if (Kind != k_Immediate)
1184 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1185 // Must be a constant.
1186 if (!CE) return false;
1187 uint64_t Value = CE->getValue();
1188 // i64 value with each byte being either 0 or 0xff.
1189 for (unsigned i = 0; i < 8; ++i)
1190 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1194 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1195 // Add as immediates when possible. Null MCExpr = 0.
1197 Inst.addOperand(MCOperand::CreateImm(0));
1198 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1199 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1201 Inst.addOperand(MCOperand::CreateExpr(Expr));
1204 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1205 assert(N == 2 && "Invalid number of operands!");
1206 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1207 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1208 Inst.addOperand(MCOperand::CreateReg(RegNum));
1211 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1212 assert(N == 1 && "Invalid number of operands!");
1213 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1216 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1217 assert(N == 1 && "Invalid number of operands!");
1218 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1221 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1222 assert(N == 1 && "Invalid number of operands!");
1223 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1226 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1227 assert(N == 1 && "Invalid number of operands!");
1228 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1231 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1232 assert(N == 1 && "Invalid number of operands!");
1233 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1236 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1237 assert(N == 1 && "Invalid number of operands!");
1238 Inst.addOperand(MCOperand::CreateReg(getReg()));
1241 void addRegOperands(MCInst &Inst, unsigned N) const {
1242 assert(N == 1 && "Invalid number of operands!");
1243 Inst.addOperand(MCOperand::CreateReg(getReg()));
1246 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1247 assert(N == 3 && "Invalid number of operands!");
1248 assert(isRegShiftedReg() &&
1249 "addRegShiftedRegOperands() on non RegShiftedReg!");
1250 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1251 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1252 Inst.addOperand(MCOperand::CreateImm(
1253 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1256 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1257 assert(N == 2 && "Invalid number of operands!");
1258 assert(isRegShiftedImm() &&
1259 "addRegShiftedImmOperands() on non RegShiftedImm!");
1260 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1261 Inst.addOperand(MCOperand::CreateImm(
1262 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
1265 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1266 assert(N == 1 && "Invalid number of operands!");
1267 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1271 void addRegListOperands(MCInst &Inst, unsigned N) const {
1272 assert(N == 1 && "Invalid number of operands!");
1273 const SmallVectorImpl<unsigned> &RegList = getRegList();
1274 for (SmallVectorImpl<unsigned>::const_iterator
1275 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1276 Inst.addOperand(MCOperand::CreateReg(*I));
1279 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1280 addRegListOperands(Inst, N);
1283 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1284 addRegListOperands(Inst, N);
1287 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1288 assert(N == 1 && "Invalid number of operands!");
1289 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1290 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1293 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1294 assert(N == 1 && "Invalid number of operands!");
1295 // Munge the lsb/width into a bitfield mask.
1296 unsigned lsb = Bitfield.LSB;
1297 unsigned width = Bitfield.Width;
1298 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1299 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1300 (32 - (lsb + width)));
1301 Inst.addOperand(MCOperand::CreateImm(Mask));
1304 void addImmOperands(MCInst &Inst, unsigned N) const {
1305 assert(N == 1 && "Invalid number of operands!");
1306 addExpr(Inst, getImm());
1309 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1310 assert(N == 1 && "Invalid number of operands!");
1311 Inst.addOperand(MCOperand::CreateImm(getFPImm()));
1314 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1315 assert(N == 1 && "Invalid number of operands!");
1316 // FIXME: We really want to scale the value here, but the LDRD/STRD
1317 // instruction don't encode operands that way yet.
1318 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1319 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1322 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1323 assert(N == 1 && "Invalid number of operands!");
1324 // The immediate is scaled by four in the encoding and is stored
1325 // in the MCInst as such. Lop off the low two bits here.
1326 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1327 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1330 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1331 assert(N == 1 && "Invalid number of operands!");
1332 // The immediate is scaled by four in the encoding and is stored
1333 // in the MCInst as such. Lop off the low two bits here.
1334 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1335 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1338 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1339 assert(N == 1 && "Invalid number of operands!");
1340 // The constant encodes as the immediate-1, and we store in the instruction
1341 // the bits as encoded, so subtract off one here.
1342 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1343 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1346 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1347 assert(N == 1 && "Invalid number of operands!");
1348 // The constant encodes as the immediate-1, and we store in the instruction
1349 // the bits as encoded, so subtract off one here.
1350 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1351 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1354 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1355 assert(N == 1 && "Invalid number of operands!");
1356 // The constant encodes as the immediate, except for 32, which encodes as
1358 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1359 unsigned Imm = CE->getValue();
1360 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1363 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1364 assert(N == 1 && "Invalid number of operands!");
1365 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1366 // the instruction as well.
1367 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1368 int Val = CE->getValue();
1369 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1372 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1373 assert(N == 1 && "Invalid number of operands!");
1374 // The operand is actually a t2_so_imm, but we have its bitwise
1375 // negation in the assembly source, so twiddle it here.
1376 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1377 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1380 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1381 assert(N == 1 && "Invalid number of operands!");
1382 // The operand is actually a t2_so_imm, but we have its
1383 // negation in the assembly source, so twiddle it here.
1384 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1385 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1388 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1389 assert(N == 1 && "Invalid number of operands!");
1390 // The operand is actually a so_imm, but we have its bitwise
1391 // negation in the assembly source, so twiddle it here.
1392 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1393 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1396 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1397 assert(N == 1 && "Invalid number of operands!");
1398 // The operand is actually a so_imm, but we have its
1399 // negation in the assembly source, so twiddle it here.
1400 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1401 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1404 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1405 assert(N == 1 && "Invalid number of operands!");
1406 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1409 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1410 assert(N == 1 && "Invalid number of operands!");
1411 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1414 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1415 assert(N == 2 && "Invalid number of operands!");
1416 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1417 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1420 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1421 assert(N == 3 && "Invalid number of operands!");
1422 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1423 if (!Memory.OffsetRegNum) {
1424 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1425 // Special case for #-0
1426 if (Val == INT32_MIN) Val = 0;
1427 if (Val < 0) Val = -Val;
1428 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1430 // For register offset, we encode the shift type and negation flag
1432 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1433 Memory.ShiftImm, Memory.ShiftType);
1435 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1436 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1437 Inst.addOperand(MCOperand::CreateImm(Val));
1440 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1441 assert(N == 2 && "Invalid number of operands!");
1442 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1443 assert(CE && "non-constant AM2OffsetImm operand!");
1444 int32_t Val = CE->getValue();
1445 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1446 // Special case for #-0
1447 if (Val == INT32_MIN) Val = 0;
1448 if (Val < 0) Val = -Val;
1449 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1450 Inst.addOperand(MCOperand::CreateReg(0));
1451 Inst.addOperand(MCOperand::CreateImm(Val));
1454 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1455 assert(N == 3 && "Invalid number of operands!");
1456 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1457 if (!Memory.OffsetRegNum) {
1458 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1459 // Special case for #-0
1460 if (Val == INT32_MIN) Val = 0;
1461 if (Val < 0) Val = -Val;
1462 Val = ARM_AM::getAM3Opc(AddSub, Val);
1464 // For register offset, we encode the shift type and negation flag
1466 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1468 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1469 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1470 Inst.addOperand(MCOperand::CreateImm(Val));
1473 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1474 assert(N == 2 && "Invalid number of operands!");
1475 if (Kind == k_PostIndexRegister) {
1477 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1478 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1479 Inst.addOperand(MCOperand::CreateImm(Val));
1484 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1485 int32_t Val = CE->getValue();
1486 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1487 // Special case for #-0
1488 if (Val == INT32_MIN) Val = 0;
1489 if (Val < 0) Val = -Val;
1490 Val = ARM_AM::getAM3Opc(AddSub, Val);
1491 Inst.addOperand(MCOperand::CreateReg(0));
1492 Inst.addOperand(MCOperand::CreateImm(Val));
1495 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1496 assert(N == 2 && "Invalid number of operands!");
1497 // If we have an immediate that's not a constant, treat it as a label
1498 // reference needing a fixup. If it is a constant, it's something else
1499 // and we reject it.
1501 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1502 Inst.addOperand(MCOperand::CreateImm(0));
1506 // The lower two bits are always zero and as such are not encoded.
1507 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1508 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1509 // Special case for #-0
1510 if (Val == INT32_MIN) Val = 0;
1511 if (Val < 0) Val = -Val;
1512 Val = ARM_AM::getAM5Opc(AddSub, Val);
1513 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1514 Inst.addOperand(MCOperand::CreateImm(Val));
1517 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1518 assert(N == 2 && "Invalid number of operands!");
1519 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1520 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1521 Inst.addOperand(MCOperand::CreateImm(Val));
1524 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1525 assert(N == 2 && "Invalid number of operands!");
1526 // The lower two bits are always zero and as such are not encoded.
1527 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1528 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1529 Inst.addOperand(MCOperand::CreateImm(Val));
1532 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1533 assert(N == 2 && "Invalid number of operands!");
1534 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1535 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1536 Inst.addOperand(MCOperand::CreateImm(Val));
1539 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1540 addMemImm8OffsetOperands(Inst, N);
1543 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1544 addMemImm8OffsetOperands(Inst, N);
1547 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1548 assert(N == 2 && "Invalid number of operands!");
1549 // If this is an immediate, it's a label reference.
1550 if (Kind == k_Immediate) {
1551 addExpr(Inst, getImm());
1552 Inst.addOperand(MCOperand::CreateImm(0));
1556 // Otherwise, it's a normal memory reg+offset.
1557 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1558 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1559 Inst.addOperand(MCOperand::CreateImm(Val));
1562 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1563 assert(N == 2 && "Invalid number of operands!");
1564 // If this is an immediate, it's a label reference.
1565 if (Kind == k_Immediate) {
1566 addExpr(Inst, getImm());
1567 Inst.addOperand(MCOperand::CreateImm(0));
1571 // Otherwise, it's a normal memory reg+offset.
1572 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1573 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1574 Inst.addOperand(MCOperand::CreateImm(Val));
1577 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1578 assert(N == 2 && "Invalid number of operands!");
1579 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1580 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1583 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
1584 assert(N == 2 && "Invalid number of operands!");
1585 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1586 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1589 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1590 assert(N == 3 && "Invalid number of operands!");
1592 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1593 Memory.ShiftImm, Memory.ShiftType);
1594 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1595 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1596 Inst.addOperand(MCOperand::CreateImm(Val));
1599 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1600 assert(N == 3 && "Invalid number of operands!");
1601 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1602 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1603 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
1606 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1607 assert(N == 2 && "Invalid number of operands!");
1608 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1609 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1612 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1613 assert(N == 2 && "Invalid number of operands!");
1614 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1615 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1616 Inst.addOperand(MCOperand::CreateImm(Val));
1619 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1620 assert(N == 2 && "Invalid number of operands!");
1621 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
1622 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1623 Inst.addOperand(MCOperand::CreateImm(Val));
1626 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1627 assert(N == 2 && "Invalid number of operands!");
1628 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
1629 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1630 Inst.addOperand(MCOperand::CreateImm(Val));
1633 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1634 assert(N == 2 && "Invalid number of operands!");
1635 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1636 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1637 Inst.addOperand(MCOperand::CreateImm(Val));
1640 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1641 assert(N == 1 && "Invalid number of operands!");
1642 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1643 assert(CE && "non-constant post-idx-imm8 operand!");
1644 int Imm = CE->getValue();
1645 bool isAdd = Imm >= 0;
1646 if (Imm == INT32_MIN) Imm = 0;
1647 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1648 Inst.addOperand(MCOperand::CreateImm(Imm));
1651 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
1652 assert(N == 1 && "Invalid number of operands!");
1653 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1654 assert(CE && "non-constant post-idx-imm8s4 operand!");
1655 int Imm = CE->getValue();
1656 bool isAdd = Imm >= 0;
1657 if (Imm == INT32_MIN) Imm = 0;
1658 // Immediate is scaled by 4.
1659 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
1660 Inst.addOperand(MCOperand::CreateImm(Imm));
1663 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1664 assert(N == 2 && "Invalid number of operands!");
1665 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1666 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1669 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1670 assert(N == 2 && "Invalid number of operands!");
1671 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1672 // The sign, shift type, and shift amount are encoded in a single operand
1673 // using the AM2 encoding helpers.
1674 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1675 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1676 PostIdxReg.ShiftTy);
1677 Inst.addOperand(MCOperand::CreateImm(Imm));
1680 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1681 assert(N == 1 && "Invalid number of operands!");
1682 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1685 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1686 assert(N == 1 && "Invalid number of operands!");
1687 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1690 void addVecListOperands(MCInst &Inst, unsigned N) const {
1691 assert(N == 1 && "Invalid number of operands!");
1692 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1695 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
1696 assert(N == 2 && "Invalid number of operands!");
1697 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1698 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
1701 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
1702 assert(N == 1 && "Invalid number of operands!");
1703 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1706 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
1707 assert(N == 1 && "Invalid number of operands!");
1708 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1711 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
1712 assert(N == 1 && "Invalid number of operands!");
1713 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1716 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
1717 assert(N == 1 && "Invalid number of operands!");
1718 // The immediate encodes the type of constant as well as the value.
1719 // Mask in that this is an i8 splat.
1720 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1721 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
1724 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
1725 assert(N == 1 && "Invalid number of operands!");
1726 // The immediate encodes the type of constant as well as the value.
1727 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1728 unsigned Value = CE->getValue();
1730 Value = (Value >> 8) | 0xa00;
1733 Inst.addOperand(MCOperand::CreateImm(Value));
1736 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
1737 assert(N == 1 && "Invalid number of operands!");
1738 // The immediate encodes the type of constant as well as the value.
1739 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1740 unsigned Value = CE->getValue();
1741 if (Value >= 256 && Value <= 0xff00)
1742 Value = (Value >> 8) | 0x200;
1743 else if (Value > 0xffff && Value <= 0xff0000)
1744 Value = (Value >> 16) | 0x400;
1745 else if (Value > 0xffffff)
1746 Value = (Value >> 24) | 0x600;
1747 Inst.addOperand(MCOperand::CreateImm(Value));
1750 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
1751 assert(N == 1 && "Invalid number of operands!");
1752 // The immediate encodes the type of constant as well as the value.
1753 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1754 unsigned Value = CE->getValue();
1755 if (Value >= 256 && Value <= 0xffff)
1756 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
1757 else if (Value > 0xffff && Value <= 0xffffff)
1758 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
1759 else if (Value > 0xffffff)
1760 Value = (Value >> 24) | 0x600;
1761 Inst.addOperand(MCOperand::CreateImm(Value));
1764 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
1765 assert(N == 1 && "Invalid number of operands!");
1766 // The immediate encodes the type of constant as well as the value.
1767 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1768 uint64_t Value = CE->getValue();
1770 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
1771 Imm |= (Value & 1) << i;
1773 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
1776 virtual void print(raw_ostream &OS) const;
1778 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
1779 ARMOperand *Op = new ARMOperand(k_ITCondMask);
1780 Op->ITMask.Mask = Mask;
1786 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1787 ARMOperand *Op = new ARMOperand(k_CondCode);
1794 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1795 ARMOperand *Op = new ARMOperand(k_CoprocNum);
1796 Op->Cop.Val = CopVal;
1802 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1803 ARMOperand *Op = new ARMOperand(k_CoprocReg);
1804 Op->Cop.Val = CopVal;
1810 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
1811 ARMOperand *Op = new ARMOperand(k_CoprocOption);
1818 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1819 ARMOperand *Op = new ARMOperand(k_CCOut);
1820 Op->Reg.RegNum = RegNum;
1826 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1827 ARMOperand *Op = new ARMOperand(k_Token);
1828 Op->Tok.Data = Str.data();
1829 Op->Tok.Length = Str.size();
1835 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1836 ARMOperand *Op = new ARMOperand(k_Register);
1837 Op->Reg.RegNum = RegNum;
1843 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1848 ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
1849 Op->RegShiftedReg.ShiftTy = ShTy;
1850 Op->RegShiftedReg.SrcReg = SrcReg;
1851 Op->RegShiftedReg.ShiftReg = ShiftReg;
1852 Op->RegShiftedReg.ShiftImm = ShiftImm;
1858 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1862 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
1863 Op->RegShiftedImm.ShiftTy = ShTy;
1864 Op->RegShiftedImm.SrcReg = SrcReg;
1865 Op->RegShiftedImm.ShiftImm = ShiftImm;
1871 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1873 ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
1874 Op->ShifterImm.isASR = isASR;
1875 Op->ShifterImm.Imm = Imm;
1881 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1882 ARMOperand *Op = new ARMOperand(k_RotateImmediate);
1883 Op->RotImm.Imm = Imm;
1889 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1891 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
1892 Op->Bitfield.LSB = LSB;
1893 Op->Bitfield.Width = Width;
1900 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1901 SMLoc StartLoc, SMLoc EndLoc) {
1902 KindTy Kind = k_RegisterList;
1904 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
1905 Kind = k_DPRRegisterList;
1906 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
1907 contains(Regs.front().first))
1908 Kind = k_SPRRegisterList;
1910 ARMOperand *Op = new ARMOperand(Kind);
1911 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1912 I = Regs.begin(), E = Regs.end(); I != E; ++I)
1913 Op->Registers.push_back(I->first);
1914 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1915 Op->StartLoc = StartLoc;
1916 Op->EndLoc = EndLoc;
1920 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
1922 ARMOperand *Op = new ARMOperand(k_VectorList);
1923 Op->VectorList.RegNum = RegNum;
1924 Op->VectorList.Count = Count;
1930 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
1932 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
1933 Op->VectorList.RegNum = RegNum;
1934 Op->VectorList.Count = Count;
1940 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
1941 unsigned Index, SMLoc S, SMLoc E) {
1942 ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
1943 Op->VectorList.RegNum = RegNum;
1944 Op->VectorList.Count = Count;
1945 Op->VectorList.LaneIndex = Index;
1951 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
1953 ARMOperand *Op = new ARMOperand(k_VectorIndex);
1954 Op->VectorIndex.Val = Idx;
1960 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1961 ARMOperand *Op = new ARMOperand(k_Immediate);
1968 static ARMOperand *CreateFPImm(unsigned Val, SMLoc S, MCContext &Ctx) {
1969 ARMOperand *Op = new ARMOperand(k_FPImmediate);
1970 Op->FPImm.Val = Val;
1976 static ARMOperand *CreateMem(unsigned BaseRegNum,
1977 const MCConstantExpr *OffsetImm,
1978 unsigned OffsetRegNum,
1979 ARM_AM::ShiftOpc ShiftType,
1984 ARMOperand *Op = new ARMOperand(k_Memory);
1985 Op->Memory.BaseRegNum = BaseRegNum;
1986 Op->Memory.OffsetImm = OffsetImm;
1987 Op->Memory.OffsetRegNum = OffsetRegNum;
1988 Op->Memory.ShiftType = ShiftType;
1989 Op->Memory.ShiftImm = ShiftImm;
1990 Op->Memory.Alignment = Alignment;
1991 Op->Memory.isNegative = isNegative;
1997 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1998 ARM_AM::ShiftOpc ShiftTy,
2001 ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2002 Op->PostIdxReg.RegNum = RegNum;
2003 Op->PostIdxReg.isAdd = isAdd;
2004 Op->PostIdxReg.ShiftTy = ShiftTy;
2005 Op->PostIdxReg.ShiftImm = ShiftImm;
2011 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2012 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2013 Op->MBOpt.Val = Opt;
2019 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2020 ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2021 Op->IFlags.Val = IFlags;
2027 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2028 ARMOperand *Op = new ARMOperand(k_MSRMask);
2029 Op->MMask.Val = MMask;
2036 } // end anonymous namespace.
2038 void ARMOperand::print(raw_ostream &OS) const {
2041 OS << "<fpimm " << getFPImm() << "(" << ARM_AM::getFPImmFloat(getFPImm())
2045 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2048 OS << "<ccout " << getReg() << ">";
2050 case k_ITCondMask: {
2051 static const char *MaskStr[] = {
2052 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2053 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2055 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2056 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2060 OS << "<coprocessor number: " << getCoproc() << ">";
2063 OS << "<coprocessor register: " << getCoproc() << ">";
2065 case k_CoprocOption:
2066 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2069 OS << "<mask: " << getMSRMask() << ">";
2072 getImm()->print(OS);
2074 case k_MemBarrierOpt:
2075 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
2079 << " base:" << Memory.BaseRegNum;
2082 case k_PostIndexRegister:
2083 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2084 << PostIdxReg.RegNum;
2085 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2086 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2087 << PostIdxReg.ShiftImm;
2090 case k_ProcIFlags: {
2091 OS << "<ARM_PROC::";
2092 unsigned IFlags = getProcIFlags();
2093 for (int i=2; i >= 0; --i)
2094 if (IFlags & (1 << i))
2095 OS << ARM_PROC::IFlagsToString(1 << i);
2100 OS << "<register " << getReg() << ">";
2102 case k_ShifterImmediate:
2103 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2104 << " #" << ShifterImm.Imm << ">";
2106 case k_ShiftedRegister:
2107 OS << "<so_reg_reg "
2108 << RegShiftedReg.SrcReg << " "
2109 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2110 << " " << RegShiftedReg.ShiftReg << ">";
2112 case k_ShiftedImmediate:
2113 OS << "<so_reg_imm "
2114 << RegShiftedImm.SrcReg << " "
2115 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2116 << " #" << RegShiftedImm.ShiftImm << ">";
2118 case k_RotateImmediate:
2119 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2121 case k_BitfieldDescriptor:
2122 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2123 << ", width: " << Bitfield.Width << ">";
2125 case k_RegisterList:
2126 case k_DPRRegisterList:
2127 case k_SPRRegisterList: {
2128 OS << "<register_list ";
2130 const SmallVectorImpl<unsigned> &RegList = getRegList();
2131 for (SmallVectorImpl<unsigned>::const_iterator
2132 I = RegList.begin(), E = RegList.end(); I != E; ) {
2134 if (++I < E) OS << ", ";
2141 OS << "<vector_list " << VectorList.Count << " * "
2142 << VectorList.RegNum << ">";
2144 case k_VectorListAllLanes:
2145 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2146 << VectorList.RegNum << ">";
2148 case k_VectorListIndexed:
2149 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2150 << VectorList.Count << " * " << VectorList.RegNum << ">";
2153 OS << "'" << getToken() << "'";
2156 OS << "<vectorindex " << getVectorIndex() << ">";
2161 /// @name Auto-generated Match Functions
2164 static unsigned MatchRegisterName(StringRef Name);
2168 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2169 SMLoc &StartLoc, SMLoc &EndLoc) {
2170 RegNo = tryParseRegister();
2172 return (RegNo == (unsigned)-1);
2175 /// Try to parse a register name. The token must be an Identifier when called,
2176 /// and if it is a register name the token is eaten and the register number is
2177 /// returned. Otherwise return -1.
2179 int ARMAsmParser::tryParseRegister() {
2180 const AsmToken &Tok = Parser.getTok();
2181 if (Tok.isNot(AsmToken::Identifier)) return -1;
2183 std::string lowerCase = Tok.getString().lower();
2184 unsigned RegNum = MatchRegisterName(lowerCase);
2186 RegNum = StringSwitch<unsigned>(lowerCase)
2187 .Case("r13", ARM::SP)
2188 .Case("r14", ARM::LR)
2189 .Case("r15", ARM::PC)
2190 .Case("ip", ARM::R12)
2191 // Additional register name aliases for 'gas' compatibility.
2192 .Case("a1", ARM::R0)
2193 .Case("a2", ARM::R1)
2194 .Case("a3", ARM::R2)
2195 .Case("a4", ARM::R3)
2196 .Case("v1", ARM::R4)
2197 .Case("v2", ARM::R5)
2198 .Case("v3", ARM::R6)
2199 .Case("v4", ARM::R7)
2200 .Case("v5", ARM::R8)
2201 .Case("v6", ARM::R9)
2202 .Case("v7", ARM::R10)
2203 .Case("v8", ARM::R11)
2204 .Case("sb", ARM::R9)
2205 .Case("sl", ARM::R10)
2206 .Case("fp", ARM::R11)
2209 if (!RegNum) return -1;
2211 Parser.Lex(); // Eat identifier token.
2216 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
2217 // If a recoverable error occurs, return 1. If an irrecoverable error
2218 // occurs, return -1. An irrecoverable error is one where tokens have been
2219 // consumed in the process of trying to parse the shifter (i.e., when it is
2220 // indeed a shifter operand, but malformed).
2221 int ARMAsmParser::tryParseShiftRegister(
2222 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2223 SMLoc S = Parser.getTok().getLoc();
2224 const AsmToken &Tok = Parser.getTok();
2225 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2227 std::string lowerCase = Tok.getString().lower();
2228 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2229 .Case("asl", ARM_AM::lsl)
2230 .Case("lsl", ARM_AM::lsl)
2231 .Case("lsr", ARM_AM::lsr)
2232 .Case("asr", ARM_AM::asr)
2233 .Case("ror", ARM_AM::ror)
2234 .Case("rrx", ARM_AM::rrx)
2235 .Default(ARM_AM::no_shift);
2237 if (ShiftTy == ARM_AM::no_shift)
2240 Parser.Lex(); // Eat the operator.
2242 // The source register for the shift has already been added to the
2243 // operand list, so we need to pop it off and combine it into the shifted
2244 // register operand instead.
2245 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2246 if (!PrevOp->isReg())
2247 return Error(PrevOp->getStartLoc(), "shift must be of a register");
2248 int SrcReg = PrevOp->getReg();
2251 if (ShiftTy == ARM_AM::rrx) {
2252 // RRX Doesn't have an explicit shift amount. The encoder expects
2253 // the shift register to be the same as the source register. Seems odd,
2257 // Figure out if this is shifted by a constant or a register (for non-RRX).
2258 if (Parser.getTok().is(AsmToken::Hash) ||
2259 Parser.getTok().is(AsmToken::Dollar)) {
2260 Parser.Lex(); // Eat hash.
2261 SMLoc ImmLoc = Parser.getTok().getLoc();
2262 const MCExpr *ShiftExpr = 0;
2263 if (getParser().ParseExpression(ShiftExpr)) {
2264 Error(ImmLoc, "invalid immediate shift value");
2267 // The expression must be evaluatable as an immediate.
2268 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2270 Error(ImmLoc, "invalid immediate shift value");
2273 // Range check the immediate.
2274 // lsl, ror: 0 <= imm <= 31
2275 // lsr, asr: 0 <= imm <= 32
2276 Imm = CE->getValue();
2278 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2279 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2280 Error(ImmLoc, "immediate shift value out of range");
2283 } else if (Parser.getTok().is(AsmToken::Identifier)) {
2284 ShiftReg = tryParseRegister();
2285 SMLoc L = Parser.getTok().getLoc();
2286 if (ShiftReg == -1) {
2287 Error (L, "expected immediate or register in shift operand");
2291 Error (Parser.getTok().getLoc(),
2292 "expected immediate or register in shift operand");
2297 if (ShiftReg && ShiftTy != ARM_AM::rrx)
2298 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2300 S, Parser.getTok().getLoc()));
2302 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2303 S, Parser.getTok().getLoc()));
2309 /// Try to parse a register name. The token must be an Identifier when called.
2310 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
2311 /// if there is a "writeback". 'true' if it's not a register.
2313 /// TODO this is likely to change to allow different register types and or to
2314 /// parse for a specific register type.
2316 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2317 SMLoc S = Parser.getTok().getLoc();
2318 int RegNo = tryParseRegister();
2322 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
2324 const AsmToken &ExclaimTok = Parser.getTok();
2325 if (ExclaimTok.is(AsmToken::Exclaim)) {
2326 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2327 ExclaimTok.getLoc()));
2328 Parser.Lex(); // Eat exclaim token
2332 // Also check for an index operand. This is only legal for vector registers,
2333 // but that'll get caught OK in operand matching, so we don't need to
2334 // explicitly filter everything else out here.
2335 if (Parser.getTok().is(AsmToken::LBrac)) {
2336 SMLoc SIdx = Parser.getTok().getLoc();
2337 Parser.Lex(); // Eat left bracket token.
2339 const MCExpr *ImmVal;
2340 if (getParser().ParseExpression(ImmVal))
2341 return MatchOperand_ParseFail;
2342 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2344 TokError("immediate value expected for vector index");
2345 return MatchOperand_ParseFail;
2348 SMLoc E = Parser.getTok().getLoc();
2349 if (Parser.getTok().isNot(AsmToken::RBrac)) {
2350 Error(E, "']' expected");
2351 return MatchOperand_ParseFail;
2354 Parser.Lex(); // Eat right bracket token.
2356 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2364 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
2365 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2367 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2368 // Use the same layout as the tablegen'erated register name matcher. Ugly,
2370 switch (Name.size()) {
2373 if (Name[0] != CoprocOp)
2390 if (Name[0] != CoprocOp || Name[1] != '1')
2394 case '0': return 10;
2395 case '1': return 11;
2396 case '2': return 12;
2397 case '3': return 13;
2398 case '4': return 14;
2399 case '5': return 15;
2407 /// parseITCondCode - Try to parse a condition code for an IT instruction.
2408 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2409 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2410 SMLoc S = Parser.getTok().getLoc();
2411 const AsmToken &Tok = Parser.getTok();
2412 if (!Tok.is(AsmToken::Identifier))
2413 return MatchOperand_NoMatch;
2414 unsigned CC = StringSwitch<unsigned>(Tok.getString())
2415 .Case("eq", ARMCC::EQ)
2416 .Case("ne", ARMCC::NE)
2417 .Case("hs", ARMCC::HS)
2418 .Case("cs", ARMCC::HS)
2419 .Case("lo", ARMCC::LO)
2420 .Case("cc", ARMCC::LO)
2421 .Case("mi", ARMCC::MI)
2422 .Case("pl", ARMCC::PL)
2423 .Case("vs", ARMCC::VS)
2424 .Case("vc", ARMCC::VC)
2425 .Case("hi", ARMCC::HI)
2426 .Case("ls", ARMCC::LS)
2427 .Case("ge", ARMCC::GE)
2428 .Case("lt", ARMCC::LT)
2429 .Case("gt", ARMCC::GT)
2430 .Case("le", ARMCC::LE)
2431 .Case("al", ARMCC::AL)
2434 return MatchOperand_NoMatch;
2435 Parser.Lex(); // Eat the token.
2437 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2439 return MatchOperand_Success;
2442 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2443 /// token must be an Identifier when called, and if it is a coprocessor
2444 /// number, the token is eaten and the operand is added to the operand list.
2445 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2446 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2447 SMLoc S = Parser.getTok().getLoc();
2448 const AsmToken &Tok = Parser.getTok();
2449 if (Tok.isNot(AsmToken::Identifier))
2450 return MatchOperand_NoMatch;
2452 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2454 return MatchOperand_NoMatch;
2456 Parser.Lex(); // Eat identifier token.
2457 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2458 return MatchOperand_Success;
2461 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2462 /// token must be an Identifier when called, and if it is a coprocessor
2463 /// number, the token is eaten and the operand is added to the operand list.
2464 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2465 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2466 SMLoc S = Parser.getTok().getLoc();
2467 const AsmToken &Tok = Parser.getTok();
2468 if (Tok.isNot(AsmToken::Identifier))
2469 return MatchOperand_NoMatch;
2471 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2473 return MatchOperand_NoMatch;
2475 Parser.Lex(); // Eat identifier token.
2476 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2477 return MatchOperand_Success;
2480 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2481 /// coproc_option : '{' imm0_255 '}'
2482 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2483 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2484 SMLoc S = Parser.getTok().getLoc();
2486 // If this isn't a '{', this isn't a coprocessor immediate operand.
2487 if (Parser.getTok().isNot(AsmToken::LCurly))
2488 return MatchOperand_NoMatch;
2489 Parser.Lex(); // Eat the '{'
2492 SMLoc Loc = Parser.getTok().getLoc();
2493 if (getParser().ParseExpression(Expr)) {
2494 Error(Loc, "illegal expression");
2495 return MatchOperand_ParseFail;
2497 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2498 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2499 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2500 return MatchOperand_ParseFail;
2502 int Val = CE->getValue();
2504 // Check for and consume the closing '}'
2505 if (Parser.getTok().isNot(AsmToken::RCurly))
2506 return MatchOperand_ParseFail;
2507 SMLoc E = Parser.getTok().getLoc();
2508 Parser.Lex(); // Eat the '}'
2510 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2511 return MatchOperand_Success;
2514 // For register list parsing, we need to map from raw GPR register numbering
2515 // to the enumeration values. The enumeration values aren't sorted by
2516 // register number due to our using "sp", "lr" and "pc" as canonical names.
2517 static unsigned getNextRegister(unsigned Reg) {
2518 // If this is a GPR, we need to do it manually, otherwise we can rely
2519 // on the sort ordering of the enumeration since the other reg-classes
2521 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2524 default: assert(0 && "Invalid GPR number!");
2525 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
2526 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
2527 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
2528 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
2529 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
2530 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2531 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
2532 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
2536 // Return the low-subreg of a given Q register.
2537 static unsigned getDRegFromQReg(unsigned QReg) {
2539 default: llvm_unreachable("expected a Q register!");
2540 case ARM::Q0: return ARM::D0;
2541 case ARM::Q1: return ARM::D2;
2542 case ARM::Q2: return ARM::D4;
2543 case ARM::Q3: return ARM::D6;
2544 case ARM::Q4: return ARM::D8;
2545 case ARM::Q5: return ARM::D10;
2546 case ARM::Q6: return ARM::D12;
2547 case ARM::Q7: return ARM::D14;
2548 case ARM::Q8: return ARM::D16;
2549 case ARM::Q9: return ARM::D18;
2550 case ARM::Q10: return ARM::D20;
2551 case ARM::Q11: return ARM::D22;
2552 case ARM::Q12: return ARM::D24;
2553 case ARM::Q13: return ARM::D26;
2554 case ARM::Q14: return ARM::D28;
2555 case ARM::Q15: return ARM::D30;
2559 /// Parse a register list.
2561 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2562 assert(Parser.getTok().is(AsmToken::LCurly) &&
2563 "Token is not a Left Curly Brace");
2564 SMLoc S = Parser.getTok().getLoc();
2565 Parser.Lex(); // Eat '{' token.
2566 SMLoc RegLoc = Parser.getTok().getLoc();
2568 // Check the first register in the list to see what register class
2569 // this is a list of.
2570 int Reg = tryParseRegister();
2572 return Error(RegLoc, "register expected");
2574 // The reglist instructions have at most 16 registers, so reserve
2575 // space for that many.
2576 SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
2578 // Allow Q regs and just interpret them as the two D sub-registers.
2579 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2580 Reg = getDRegFromQReg(Reg);
2581 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2584 const MCRegisterClass *RC;
2585 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2586 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
2587 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
2588 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
2589 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
2590 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
2592 return Error(RegLoc, "invalid register in register list");
2594 // Store the register.
2595 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2597 // This starts immediately after the first register token in the list,
2598 // so we can see either a comma or a minus (range separator) as a legal
2600 while (Parser.getTok().is(AsmToken::Comma) ||
2601 Parser.getTok().is(AsmToken::Minus)) {
2602 if (Parser.getTok().is(AsmToken::Minus)) {
2603 Parser.Lex(); // Eat the minus.
2604 SMLoc EndLoc = Parser.getTok().getLoc();
2605 int EndReg = tryParseRegister();
2607 return Error(EndLoc, "register expected");
2608 // Allow Q regs and just interpret them as the two D sub-registers.
2609 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
2610 EndReg = getDRegFromQReg(EndReg) + 1;
2611 // If the register is the same as the start reg, there's nothing
2615 // The register must be in the same register class as the first.
2616 if (!RC->contains(EndReg))
2617 return Error(EndLoc, "invalid register in register list");
2618 // Ranges must go from low to high.
2619 if (getARMRegisterNumbering(Reg) > getARMRegisterNumbering(EndReg))
2620 return Error(EndLoc, "bad range in register list");
2622 // Add all the registers in the range to the register list.
2623 while (Reg != EndReg) {
2624 Reg = getNextRegister(Reg);
2625 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2629 Parser.Lex(); // Eat the comma.
2630 RegLoc = Parser.getTok().getLoc();
2632 const AsmToken RegTok = Parser.getTok();
2633 Reg = tryParseRegister();
2635 return Error(RegLoc, "register expected");
2636 // Allow Q regs and just interpret them as the two D sub-registers.
2637 bool isQReg = false;
2638 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2639 Reg = getDRegFromQReg(Reg);
2642 // The register must be in the same register class as the first.
2643 if (!RC->contains(Reg))
2644 return Error(RegLoc, "invalid register in register list");
2645 // List must be monotonically increasing.
2646 if (getARMRegisterNumbering(Reg) < getARMRegisterNumbering(OldReg))
2647 return Error(RegLoc, "register list not in ascending order");
2648 if (getARMRegisterNumbering(Reg) == getARMRegisterNumbering(OldReg)) {
2649 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
2650 ") in register list");
2653 // VFP register lists must also be contiguous.
2654 // It's OK to use the enumeration values directly here rather, as the
2655 // VFP register classes have the enum sorted properly.
2656 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
2658 return Error(RegLoc, "non-contiguous register range");
2659 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2661 Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc));
2664 SMLoc E = Parser.getTok().getLoc();
2665 if (Parser.getTok().isNot(AsmToken::RCurly))
2666 return Error(E, "'}' expected");
2667 Parser.Lex(); // Eat '}' token.
2669 // Push the register list operand.
2670 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
2672 // The ARM system instruction variants for LDM/STM have a '^' token here.
2673 if (Parser.getTok().is(AsmToken::Caret)) {
2674 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
2675 Parser.Lex(); // Eat '^' token.
2681 // Helper function to parse the lane index for vector lists.
2682 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2683 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index) {
2684 Index = 0; // Always return a defined index value.
2685 if (Parser.getTok().is(AsmToken::LBrac)) {
2686 Parser.Lex(); // Eat the '['.
2687 if (Parser.getTok().is(AsmToken::RBrac)) {
2688 // "Dn[]" is the 'all lanes' syntax.
2689 LaneKind = AllLanes;
2690 Parser.Lex(); // Eat the ']'.
2691 return MatchOperand_Success;
2693 if (Parser.getTok().is(AsmToken::Integer)) {
2694 int64_t Val = Parser.getTok().getIntVal();
2695 // Make this range check context sensitive for .8, .16, .32.
2696 if (Val < 0 && Val > 7)
2697 Error(Parser.getTok().getLoc(), "lane index out of range");
2699 LaneKind = IndexedLane;
2700 Parser.Lex(); // Eat the token;
2701 if (Parser.getTok().isNot(AsmToken::RBrac))
2702 Error(Parser.getTok().getLoc(), "']' expected");
2703 Parser.Lex(); // Eat the ']'.
2704 return MatchOperand_Success;
2706 Error(Parser.getTok().getLoc(), "lane index must be empty or an integer");
2707 return MatchOperand_ParseFail;
2710 return MatchOperand_Success;
2713 // parse a vector register list
2714 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2715 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2716 VectorLaneTy LaneKind;
2718 SMLoc S = Parser.getTok().getLoc();
2719 // As an extension (to match gas), support a plain D register or Q register
2720 // (without encosing curly braces) as a single or double entry list,
2722 if (Parser.getTok().is(AsmToken::Identifier)) {
2723 int Reg = tryParseRegister();
2725 return MatchOperand_NoMatch;
2726 SMLoc E = Parser.getTok().getLoc();
2727 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
2728 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex);
2729 if (Res != MatchOperand_Success)
2733 assert(0 && "unexpected lane kind!");
2735 E = Parser.getTok().getLoc();
2736 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, S, E));
2739 E = Parser.getTok().getLoc();
2740 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, S, E));
2743 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
2747 return MatchOperand_Success;
2749 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2750 Reg = getDRegFromQReg(Reg);
2751 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex);
2752 if (Res != MatchOperand_Success)
2756 assert(0 && "unexpected lane kind!");
2758 E = Parser.getTok().getLoc();
2759 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, S, E));
2762 E = Parser.getTok().getLoc();
2763 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, S, E));
2766 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
2770 return MatchOperand_Success;
2772 Error(S, "vector register expected");
2773 return MatchOperand_ParseFail;
2776 if (Parser.getTok().isNot(AsmToken::LCurly))
2777 return MatchOperand_NoMatch;
2779 Parser.Lex(); // Eat '{' token.
2780 SMLoc RegLoc = Parser.getTok().getLoc();
2782 int Reg = tryParseRegister();
2784 Error(RegLoc, "register expected");
2785 return MatchOperand_ParseFail;
2788 unsigned FirstReg = Reg;
2789 // The list is of D registers, but we also allow Q regs and just interpret
2790 // them as the two D sub-registers.
2791 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2792 FirstReg = Reg = getDRegFromQReg(Reg);
2796 if (parseVectorLane(LaneKind, LaneIndex) != MatchOperand_Success)
2797 return MatchOperand_ParseFail;
2799 while (Parser.getTok().is(AsmToken::Comma) ||
2800 Parser.getTok().is(AsmToken::Minus)) {
2801 if (Parser.getTok().is(AsmToken::Minus)) {
2802 Parser.Lex(); // Eat the minus.
2803 SMLoc EndLoc = Parser.getTok().getLoc();
2804 int EndReg = tryParseRegister();
2806 Error(EndLoc, "register expected");
2807 return MatchOperand_ParseFail;
2809 // Allow Q regs and just interpret them as the two D sub-registers.
2810 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
2811 EndReg = getDRegFromQReg(EndReg) + 1;
2812 // If the register is the same as the start reg, there's nothing
2816 // The register must be in the same register class as the first.
2817 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
2818 Error(EndLoc, "invalid register in register list");
2819 return MatchOperand_ParseFail;
2821 // Ranges must go from low to high.
2823 Error(EndLoc, "bad range in register list");
2824 return MatchOperand_ParseFail;
2826 // Parse the lane specifier if present.
2827 VectorLaneTy NextLaneKind;
2828 unsigned NextLaneIndex;
2829 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
2830 return MatchOperand_ParseFail;
2831 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
2832 Error(EndLoc, "mismatched lane index in register list");
2833 return MatchOperand_ParseFail;
2835 EndLoc = Parser.getTok().getLoc();
2837 // Add all the registers in the range to the register list.
2838 Count += EndReg - Reg;
2842 Parser.Lex(); // Eat the comma.
2843 RegLoc = Parser.getTok().getLoc();
2845 Reg = tryParseRegister();
2847 Error(RegLoc, "register expected");
2848 return MatchOperand_ParseFail;
2850 // vector register lists must be contiguous.
2851 // It's OK to use the enumeration values directly here rather, as the
2852 // VFP register classes have the enum sorted properly.
2854 // The list is of D registers, but we also allow Q regs and just interpret
2855 // them as the two D sub-registers.
2856 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2857 Reg = getDRegFromQReg(Reg);
2858 if (Reg != OldReg + 1) {
2859 Error(RegLoc, "non-contiguous register range");
2860 return MatchOperand_ParseFail;
2864 // Parse the lane specifier if present.
2865 VectorLaneTy NextLaneKind;
2866 unsigned NextLaneIndex;
2867 SMLoc EndLoc = Parser.getTok().getLoc();
2868 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
2869 return MatchOperand_ParseFail;
2870 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
2871 Error(EndLoc, "mismatched lane index in register list");
2872 return MatchOperand_ParseFail;
2876 // Normal D register. Just check that it's contiguous and keep going.
2877 if (Reg != OldReg + 1) {
2878 Error(RegLoc, "non-contiguous register range");
2879 return MatchOperand_ParseFail;
2882 // Parse the lane specifier if present.
2883 VectorLaneTy NextLaneKind;
2884 unsigned NextLaneIndex;
2885 SMLoc EndLoc = Parser.getTok().getLoc();
2886 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
2887 return MatchOperand_ParseFail;
2888 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
2889 Error(EndLoc, "mismatched lane index in register list");
2890 return MatchOperand_ParseFail;
2894 SMLoc E = Parser.getTok().getLoc();
2895 if (Parser.getTok().isNot(AsmToken::RCurly)) {
2896 Error(E, "'}' expected");
2897 return MatchOperand_ParseFail;
2899 Parser.Lex(); // Eat '}' token.
2903 assert(0 && "unexpected lane kind in register list.");
2905 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, S, E));
2908 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
2912 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
2916 return MatchOperand_Success;
2919 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
2920 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2921 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2922 SMLoc S = Parser.getTok().getLoc();
2923 const AsmToken &Tok = Parser.getTok();
2924 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2925 StringRef OptStr = Tok.getString();
2927 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
2928 .Case("sy", ARM_MB::SY)
2929 .Case("st", ARM_MB::ST)
2930 .Case("sh", ARM_MB::ISH)
2931 .Case("ish", ARM_MB::ISH)
2932 .Case("shst", ARM_MB::ISHST)
2933 .Case("ishst", ARM_MB::ISHST)
2934 .Case("nsh", ARM_MB::NSH)
2935 .Case("un", ARM_MB::NSH)
2936 .Case("nshst", ARM_MB::NSHST)
2937 .Case("unst", ARM_MB::NSHST)
2938 .Case("osh", ARM_MB::OSH)
2939 .Case("oshst", ARM_MB::OSHST)
2943 return MatchOperand_NoMatch;
2945 Parser.Lex(); // Eat identifier token.
2946 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
2947 return MatchOperand_Success;
2950 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
2951 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2952 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2953 SMLoc S = Parser.getTok().getLoc();
2954 const AsmToken &Tok = Parser.getTok();
2955 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2956 StringRef IFlagsStr = Tok.getString();
2958 // An iflags string of "none" is interpreted to mean that none of the AIF
2959 // bits are set. Not a terribly useful instruction, but a valid encoding.
2960 unsigned IFlags = 0;
2961 if (IFlagsStr != "none") {
2962 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
2963 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
2964 .Case("a", ARM_PROC::A)
2965 .Case("i", ARM_PROC::I)
2966 .Case("f", ARM_PROC::F)
2969 // If some specific iflag is already set, it means that some letter is
2970 // present more than once, this is not acceptable.
2971 if (Flag == ~0U || (IFlags & Flag))
2972 return MatchOperand_NoMatch;
2978 Parser.Lex(); // Eat identifier token.
2979 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
2980 return MatchOperand_Success;
2983 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
2984 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2985 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2986 SMLoc S = Parser.getTok().getLoc();
2987 const AsmToken &Tok = Parser.getTok();
2988 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2989 StringRef Mask = Tok.getString();
2992 // See ARMv6-M 10.1.1
2993 unsigned FlagsVal = StringSwitch<unsigned>(Mask)
3003 .Case("primask", 16)
3004 .Case("basepri", 17)
3005 .Case("basepri_max", 18)
3006 .Case("faultmask", 19)
3007 .Case("control", 20)
3010 if (FlagsVal == ~0U)
3011 return MatchOperand_NoMatch;
3013 if (!hasV7Ops() && FlagsVal >= 17 && FlagsVal <= 19)
3014 // basepri, basepri_max and faultmask only valid for V7m.
3015 return MatchOperand_NoMatch;
3017 Parser.Lex(); // Eat identifier token.
3018 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3019 return MatchOperand_Success;
3022 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3023 size_t Start = 0, Next = Mask.find('_');
3024 StringRef Flags = "";
3025 std::string SpecReg = Mask.slice(Start, Next).lower();
3026 if (Next != StringRef::npos)
3027 Flags = Mask.slice(Next+1, Mask.size());
3029 // FlagsVal contains the complete mask:
3031 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3032 unsigned FlagsVal = 0;
3034 if (SpecReg == "apsr") {
3035 FlagsVal = StringSwitch<unsigned>(Flags)
3036 .Case("nzcvq", 0x8) // same as CPSR_f
3037 .Case("g", 0x4) // same as CPSR_s
3038 .Case("nzcvqg", 0xc) // same as CPSR_fs
3041 if (FlagsVal == ~0U) {
3043 return MatchOperand_NoMatch;
3045 FlagsVal = 8; // No flag
3047 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3048 if (Flags == "all") // cpsr_all is an alias for cpsr_fc
3050 for (int i = 0, e = Flags.size(); i != e; ++i) {
3051 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3058 // If some specific flag is already set, it means that some letter is
3059 // present more than once, this is not acceptable.
3060 if (FlagsVal == ~0U || (FlagsVal & Flag))
3061 return MatchOperand_NoMatch;
3064 } else // No match for special register.
3065 return MatchOperand_NoMatch;
3067 // Special register without flags is NOT equivalent to "fc" flags.
3068 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
3069 // two lines would enable gas compatibility at the expense of breaking
3075 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3076 if (SpecReg == "spsr")
3079 Parser.Lex(); // Eat identifier token.
3080 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3081 return MatchOperand_Success;
3084 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3085 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3086 int Low, int High) {
3087 const AsmToken &Tok = Parser.getTok();
3088 if (Tok.isNot(AsmToken::Identifier)) {
3089 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3090 return MatchOperand_ParseFail;
3092 StringRef ShiftName = Tok.getString();
3093 std::string LowerOp = Op.lower();
3094 std::string UpperOp = Op.upper();
3095 if (ShiftName != LowerOp && ShiftName != UpperOp) {
3096 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3097 return MatchOperand_ParseFail;
3099 Parser.Lex(); // Eat shift type token.
3101 // There must be a '#' and a shift amount.
3102 if (Parser.getTok().isNot(AsmToken::Hash) &&
3103 Parser.getTok().isNot(AsmToken::Dollar)) {
3104 Error(Parser.getTok().getLoc(), "'#' expected");
3105 return MatchOperand_ParseFail;
3107 Parser.Lex(); // Eat hash token.
3109 const MCExpr *ShiftAmount;
3110 SMLoc Loc = Parser.getTok().getLoc();
3111 if (getParser().ParseExpression(ShiftAmount)) {
3112 Error(Loc, "illegal expression");
3113 return MatchOperand_ParseFail;
3115 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3117 Error(Loc, "constant expression expected");
3118 return MatchOperand_ParseFail;
3120 int Val = CE->getValue();
3121 if (Val < Low || Val > High) {
3122 Error(Loc, "immediate value out of range");
3123 return MatchOperand_ParseFail;
3126 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
3128 return MatchOperand_Success;
3131 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3132 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3133 const AsmToken &Tok = Parser.getTok();
3134 SMLoc S = Tok.getLoc();
3135 if (Tok.isNot(AsmToken::Identifier)) {
3136 Error(Tok.getLoc(), "'be' or 'le' operand expected");
3137 return MatchOperand_ParseFail;
3139 int Val = StringSwitch<int>(Tok.getString())
3143 Parser.Lex(); // Eat the token.
3146 Error(Tok.getLoc(), "'be' or 'le' operand expected");
3147 return MatchOperand_ParseFail;
3149 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3151 S, Parser.getTok().getLoc()));
3152 return MatchOperand_Success;
3155 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3156 /// instructions. Legal values are:
3157 /// lsl #n 'n' in [0,31]
3158 /// asr #n 'n' in [1,32]
3159 /// n == 32 encoded as n == 0.
3160 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3161 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3162 const AsmToken &Tok = Parser.getTok();
3163 SMLoc S = Tok.getLoc();
3164 if (Tok.isNot(AsmToken::Identifier)) {
3165 Error(S, "shift operator 'asr' or 'lsl' expected");
3166 return MatchOperand_ParseFail;
3168 StringRef ShiftName = Tok.getString();
3170 if (ShiftName == "lsl" || ShiftName == "LSL")
3172 else if (ShiftName == "asr" || ShiftName == "ASR")
3175 Error(S, "shift operator 'asr' or 'lsl' expected");
3176 return MatchOperand_ParseFail;
3178 Parser.Lex(); // Eat the operator.
3180 // A '#' and a shift amount.
3181 if (Parser.getTok().isNot(AsmToken::Hash) &&
3182 Parser.getTok().isNot(AsmToken::Dollar)) {
3183 Error(Parser.getTok().getLoc(), "'#' expected");
3184 return MatchOperand_ParseFail;
3186 Parser.Lex(); // Eat hash token.
3188 const MCExpr *ShiftAmount;
3189 SMLoc E = Parser.getTok().getLoc();
3190 if (getParser().ParseExpression(ShiftAmount)) {
3191 Error(E, "malformed shift expression");
3192 return MatchOperand_ParseFail;
3194 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3196 Error(E, "shift amount must be an immediate");
3197 return MatchOperand_ParseFail;
3200 int64_t Val = CE->getValue();
3202 // Shift amount must be in [1,32]
3203 if (Val < 1 || Val > 32) {
3204 Error(E, "'asr' shift amount must be in range [1,32]");
3205 return MatchOperand_ParseFail;
3207 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3208 if (isThumb() && Val == 32) {
3209 Error(E, "'asr #32' shift amount not allowed in Thumb mode");
3210 return MatchOperand_ParseFail;
3212 if (Val == 32) Val = 0;
3214 // Shift amount must be in [1,32]
3215 if (Val < 0 || Val > 31) {
3216 Error(E, "'lsr' shift amount must be in range [0,31]");
3217 return MatchOperand_ParseFail;
3221 E = Parser.getTok().getLoc();
3222 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
3224 return MatchOperand_Success;
3227 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3228 /// of instructions. Legal values are:
3229 /// ror #n 'n' in {0, 8, 16, 24}
3230 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3231 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3232 const AsmToken &Tok = Parser.getTok();
3233 SMLoc S = Tok.getLoc();
3234 if (Tok.isNot(AsmToken::Identifier))
3235 return MatchOperand_NoMatch;
3236 StringRef ShiftName = Tok.getString();
3237 if (ShiftName != "ror" && ShiftName != "ROR")
3238 return MatchOperand_NoMatch;
3239 Parser.Lex(); // Eat the operator.
3241 // A '#' and a rotate amount.
3242 if (Parser.getTok().isNot(AsmToken::Hash) &&
3243 Parser.getTok().isNot(AsmToken::Dollar)) {
3244 Error(Parser.getTok().getLoc(), "'#' expected");
3245 return MatchOperand_ParseFail;
3247 Parser.Lex(); // Eat hash token.
3249 const MCExpr *ShiftAmount;
3250 SMLoc E = Parser.getTok().getLoc();
3251 if (getParser().ParseExpression(ShiftAmount)) {
3252 Error(E, "malformed rotate expression");
3253 return MatchOperand_ParseFail;
3255 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3257 Error(E, "rotate amount must be an immediate");
3258 return MatchOperand_ParseFail;
3261 int64_t Val = CE->getValue();
3262 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
3263 // normally, zero is represented in asm by omitting the rotate operand
3265 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
3266 Error(E, "'ror' rotate amount must be 8, 16, or 24");
3267 return MatchOperand_ParseFail;
3270 E = Parser.getTok().getLoc();
3271 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
3273 return MatchOperand_Success;
3276 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3277 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3278 SMLoc S = Parser.getTok().getLoc();
3279 // The bitfield descriptor is really two operands, the LSB and the width.
3280 if (Parser.getTok().isNot(AsmToken::Hash) &&
3281 Parser.getTok().isNot(AsmToken::Dollar)) {
3282 Error(Parser.getTok().getLoc(), "'#' expected");
3283 return MatchOperand_ParseFail;
3285 Parser.Lex(); // Eat hash token.
3287 const MCExpr *LSBExpr;
3288 SMLoc E = Parser.getTok().getLoc();
3289 if (getParser().ParseExpression(LSBExpr)) {
3290 Error(E, "malformed immediate expression");
3291 return MatchOperand_ParseFail;
3293 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
3295 Error(E, "'lsb' operand must be an immediate");
3296 return MatchOperand_ParseFail;
3299 int64_t LSB = CE->getValue();
3300 // The LSB must be in the range [0,31]
3301 if (LSB < 0 || LSB > 31) {
3302 Error(E, "'lsb' operand must be in the range [0,31]");
3303 return MatchOperand_ParseFail;
3305 E = Parser.getTok().getLoc();
3307 // Expect another immediate operand.
3308 if (Parser.getTok().isNot(AsmToken::Comma)) {
3309 Error(Parser.getTok().getLoc(), "too few operands");
3310 return MatchOperand_ParseFail;
3312 Parser.Lex(); // Eat hash token.
3313 if (Parser.getTok().isNot(AsmToken::Hash) &&
3314 Parser.getTok().isNot(AsmToken::Dollar)) {
3315 Error(Parser.getTok().getLoc(), "'#' expected");
3316 return MatchOperand_ParseFail;
3318 Parser.Lex(); // Eat hash token.
3320 const MCExpr *WidthExpr;
3321 if (getParser().ParseExpression(WidthExpr)) {
3322 Error(E, "malformed immediate expression");
3323 return MatchOperand_ParseFail;
3325 CE = dyn_cast<MCConstantExpr>(WidthExpr);
3327 Error(E, "'width' operand must be an immediate");
3328 return MatchOperand_ParseFail;
3331 int64_t Width = CE->getValue();
3332 // The LSB must be in the range [1,32-lsb]
3333 if (Width < 1 || Width > 32 - LSB) {
3334 Error(E, "'width' operand must be in the range [1,32-lsb]");
3335 return MatchOperand_ParseFail;
3337 E = Parser.getTok().getLoc();
3339 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
3341 return MatchOperand_Success;
3344 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3345 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3346 // Check for a post-index addressing register operand. Specifically:
3347 // postidx_reg := '+' register {, shift}
3348 // | '-' register {, shift}
3349 // | register {, shift}
3351 // This method must return MatchOperand_NoMatch without consuming any tokens
3352 // in the case where there is no match, as other alternatives take other
3354 AsmToken Tok = Parser.getTok();
3355 SMLoc S = Tok.getLoc();
3356 bool haveEaten = false;
3359 if (Tok.is(AsmToken::Plus)) {
3360 Parser.Lex(); // Eat the '+' token.
3362 } else if (Tok.is(AsmToken::Minus)) {
3363 Parser.Lex(); // Eat the '-' token.
3367 if (Parser.getTok().is(AsmToken::Identifier))
3368 Reg = tryParseRegister();
3371 return MatchOperand_NoMatch;
3372 Error(Parser.getTok().getLoc(), "register expected");
3373 return MatchOperand_ParseFail;
3375 SMLoc E = Parser.getTok().getLoc();
3377 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
3378 unsigned ShiftImm = 0;
3379 if (Parser.getTok().is(AsmToken::Comma)) {
3380 Parser.Lex(); // Eat the ','.
3381 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
3382 return MatchOperand_ParseFail;
3385 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
3388 return MatchOperand_Success;
3391 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3392 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3393 // Check for a post-index addressing register operand. Specifically:
3394 // am3offset := '+' register
3401 // This method must return MatchOperand_NoMatch without consuming any tokens
3402 // in the case where there is no match, as other alternatives take other
3404 AsmToken Tok = Parser.getTok();
3405 SMLoc S = Tok.getLoc();
3407 // Do immediates first, as we always parse those if we have a '#'.
3408 if (Parser.getTok().is(AsmToken::Hash) ||
3409 Parser.getTok().is(AsmToken::Dollar)) {
3410 Parser.Lex(); // Eat the '#'.
3411 // Explicitly look for a '-', as we need to encode negative zero
3413 bool isNegative = Parser.getTok().is(AsmToken::Minus);
3414 const MCExpr *Offset;
3415 if (getParser().ParseExpression(Offset))
3416 return MatchOperand_ParseFail;
3417 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
3419 Error(S, "constant expression expected");
3420 return MatchOperand_ParseFail;
3422 SMLoc E = Tok.getLoc();
3423 // Negative zero is encoded as the flag value INT32_MIN.
3424 int32_t Val = CE->getValue();
3425 if (isNegative && Val == 0)
3429 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
3431 return MatchOperand_Success;
3435 bool haveEaten = false;
3438 if (Tok.is(AsmToken::Plus)) {
3439 Parser.Lex(); // Eat the '+' token.
3441 } else if (Tok.is(AsmToken::Minus)) {
3442 Parser.Lex(); // Eat the '-' token.
3446 if (Parser.getTok().is(AsmToken::Identifier))
3447 Reg = tryParseRegister();
3450 return MatchOperand_NoMatch;
3451 Error(Parser.getTok().getLoc(), "register expected");
3452 return MatchOperand_ParseFail;
3454 SMLoc E = Parser.getTok().getLoc();
3456 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
3459 return MatchOperand_Success;
3462 /// cvtT2LdrdPre - Convert parsed operands to MCInst.
3463 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3464 /// when they refer multiple MIOperands inside a single one.
3466 cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
3467 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3469 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3470 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3471 // Create a writeback register dummy placeholder.
3472 Inst.addOperand(MCOperand::CreateReg(0));
3474 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3476 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3480 /// cvtT2StrdPre - Convert parsed operands to MCInst.
3481 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3482 /// when they refer multiple MIOperands inside a single one.
3484 cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
3485 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3486 // Create a writeback register dummy placeholder.
3487 Inst.addOperand(MCOperand::CreateReg(0));
3489 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3490 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3492 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3494 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3498 /// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3499 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3500 /// when they refer multiple MIOperands inside a single one.
3502 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3503 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3504 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3506 // Create a writeback register dummy placeholder.
3507 Inst.addOperand(MCOperand::CreateImm(0));
3509 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3510 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3514 /// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3515 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3516 /// when they refer multiple MIOperands inside a single one.
3518 cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3519 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3520 // Create a writeback register dummy placeholder.
3521 Inst.addOperand(MCOperand::CreateImm(0));
3522 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3523 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3524 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3528 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3529 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3530 /// when they refer multiple MIOperands inside a single one.
3532 cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3533 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3534 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3536 // Create a writeback register dummy placeholder.
3537 Inst.addOperand(MCOperand::CreateImm(0));
3539 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3540 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3544 /// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3545 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3546 /// when they refer multiple MIOperands inside a single one.
3548 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3549 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3550 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3552 // Create a writeback register dummy placeholder.
3553 Inst.addOperand(MCOperand::CreateImm(0));
3555 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3556 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3561 /// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3562 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3563 /// when they refer multiple MIOperands inside a single one.
3565 cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3566 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3567 // Create a writeback register dummy placeholder.
3568 Inst.addOperand(MCOperand::CreateImm(0));
3569 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3570 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3571 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3575 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3576 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3577 /// when they refer multiple MIOperands inside a single one.
3579 cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3580 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3581 // Create a writeback register dummy placeholder.
3582 Inst.addOperand(MCOperand::CreateImm(0));
3583 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3584 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3585 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3589 /// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
3590 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3591 /// when they refer multiple MIOperands inside a single one.
3593 cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
3594 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3595 // Create a writeback register dummy placeholder.
3596 Inst.addOperand(MCOperand::CreateImm(0));
3597 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3598 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
3599 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3603 /// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
3604 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3605 /// when they refer multiple MIOperands inside a single one.
3607 cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
3608 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3610 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3611 // Create a writeback register dummy placeholder.
3612 Inst.addOperand(MCOperand::CreateImm(0));
3614 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3616 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
3618 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3622 /// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
3623 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3624 /// when they refer multiple MIOperands inside a single one.
3626 cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
3627 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3629 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3630 // Create a writeback register dummy placeholder.
3631 Inst.addOperand(MCOperand::CreateImm(0));
3633 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3635 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
3637 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3641 /// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
3642 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3643 /// when they refer multiple MIOperands inside a single one.
3645 cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
3646 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3647 // Create a writeback register dummy placeholder.
3648 Inst.addOperand(MCOperand::CreateImm(0));
3650 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3652 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3654 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
3656 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3660 /// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
3661 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3662 /// when they refer multiple MIOperands inside a single one.
3664 cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
3665 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3666 // Create a writeback register dummy placeholder.
3667 Inst.addOperand(MCOperand::CreateImm(0));
3669 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3671 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3673 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
3675 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3679 /// cvtLdrdPre - Convert parsed operands to MCInst.
3680 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3681 /// when they refer multiple MIOperands inside a single one.
3683 cvtLdrdPre(MCInst &Inst, unsigned Opcode,
3684 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3686 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3687 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3688 // Create a writeback register dummy placeholder.
3689 Inst.addOperand(MCOperand::CreateImm(0));
3691 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
3693 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3697 /// cvtStrdPre - Convert parsed operands to MCInst.
3698 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3699 /// when they refer multiple MIOperands inside a single one.
3701 cvtStrdPre(MCInst &Inst, unsigned Opcode,
3702 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3703 // Create a writeback register dummy placeholder.
3704 Inst.addOperand(MCOperand::CreateImm(0));
3706 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3707 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3709 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
3711 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3715 /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
3716 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3717 /// when they refer multiple MIOperands inside a single one.
3719 cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
3720 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3721 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3722 // Create a writeback register dummy placeholder.
3723 Inst.addOperand(MCOperand::CreateImm(0));
3724 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
3725 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3729 /// cvtThumbMultiple- Convert parsed operands to MCInst.
3730 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3731 /// when they refer multiple MIOperands inside a single one.
3733 cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
3734 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3735 // The second source operand must be the same register as the destination
3737 if (Operands.size() == 6 &&
3738 (((ARMOperand*)Operands[3])->getReg() !=
3739 ((ARMOperand*)Operands[5])->getReg()) &&
3740 (((ARMOperand*)Operands[3])->getReg() !=
3741 ((ARMOperand*)Operands[4])->getReg())) {
3742 Error(Operands[3]->getStartLoc(),
3743 "destination register must match source register");
3746 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3747 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
3748 // If we have a three-operand form, make sure to set Rn to be the operand
3749 // that isn't the same as Rd.
3751 if (Operands.size() == 6 &&
3752 ((ARMOperand*)Operands[4])->getReg() ==
3753 ((ARMOperand*)Operands[3])->getReg())
3755 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
3756 Inst.addOperand(Inst.getOperand(0));
3757 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
3763 cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
3764 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3766 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
3767 // Create a writeback register dummy placeholder.
3768 Inst.addOperand(MCOperand::CreateImm(0));
3770 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3772 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3777 cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
3778 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3780 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
3781 // Create a writeback register dummy placeholder.
3782 Inst.addOperand(MCOperand::CreateImm(0));
3784 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3786 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
3788 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3793 cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
3794 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3795 // Create a writeback register dummy placeholder.
3796 Inst.addOperand(MCOperand::CreateImm(0));
3798 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3800 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
3802 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3807 cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
3808 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3809 // Create a writeback register dummy placeholder.
3810 Inst.addOperand(MCOperand::CreateImm(0));
3812 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3814 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
3816 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
3818 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3822 /// Parse an ARM memory expression, return false if successful else return true
3823 /// or an error. The first token must be a '[' when called.
3825 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3827 assert(Parser.getTok().is(AsmToken::LBrac) &&
3828 "Token is not a Left Bracket");
3829 S = Parser.getTok().getLoc();
3830 Parser.Lex(); // Eat left bracket token.
3832 const AsmToken &BaseRegTok = Parser.getTok();
3833 int BaseRegNum = tryParseRegister();
3834 if (BaseRegNum == -1)
3835 return Error(BaseRegTok.getLoc(), "register expected");
3837 // The next token must either be a comma or a closing bracket.
3838 const AsmToken &Tok = Parser.getTok();
3839 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
3840 return Error(Tok.getLoc(), "malformed memory operand");
3842 if (Tok.is(AsmToken::RBrac)) {
3844 Parser.Lex(); // Eat right bracket token.
3846 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
3847 0, 0, false, S, E));
3849 // If there's a pre-indexing writeback marker, '!', just add it as a token
3850 // operand. It's rather odd, but syntactically valid.
3851 if (Parser.getTok().is(AsmToken::Exclaim)) {
3852 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3853 Parser.Lex(); // Eat the '!'.
3859 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
3860 Parser.Lex(); // Eat the comma.
3862 // If we have a ':', it's an alignment specifier.
3863 if (Parser.getTok().is(AsmToken::Colon)) {
3864 Parser.Lex(); // Eat the ':'.
3865 E = Parser.getTok().getLoc();
3868 if (getParser().ParseExpression(Expr))
3871 // The expression has to be a constant. Memory references with relocations
3872 // don't come through here, as they use the <label> forms of the relevant
3874 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3876 return Error (E, "constant expression expected");
3879 switch (CE->getValue()) {
3881 return Error(E, "alignment specifier must be 64, 128, or 256 bits");
3882 case 64: Align = 8; break;
3883 case 128: Align = 16; break;
3884 case 256: Align = 32; break;
3887 // Now we should have the closing ']'
3888 E = Parser.getTok().getLoc();
3889 if (Parser.getTok().isNot(AsmToken::RBrac))
3890 return Error(E, "']' expected");
3891 Parser.Lex(); // Eat right bracket token.
3893 // Don't worry about range checking the value here. That's handled by
3894 // the is*() predicates.
3895 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
3896 ARM_AM::no_shift, 0, Align,
3899 // If there's a pre-indexing writeback marker, '!', just add it as a token
3901 if (Parser.getTok().is(AsmToken::Exclaim)) {
3902 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3903 Parser.Lex(); // Eat the '!'.
3909 // If we have a '#', it's an immediate offset, else assume it's a register
3910 // offset. Be friendly and also accept a plain integer (without a leading
3911 // hash) for gas compatibility.
3912 if (Parser.getTok().is(AsmToken::Hash) ||
3913 Parser.getTok().is(AsmToken::Dollar) ||
3914 Parser.getTok().is(AsmToken::Integer)) {
3915 if (Parser.getTok().isNot(AsmToken::Integer))
3916 Parser.Lex(); // Eat the '#'.
3917 E = Parser.getTok().getLoc();
3919 bool isNegative = getParser().getTok().is(AsmToken::Minus);
3920 const MCExpr *Offset;
3921 if (getParser().ParseExpression(Offset))
3924 // The expression has to be a constant. Memory references with relocations
3925 // don't come through here, as they use the <label> forms of the relevant
3927 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
3929 return Error (E, "constant expression expected");
3931 // If the constant was #-0, represent it as INT32_MIN.
3932 int32_t Val = CE->getValue();
3933 if (isNegative && Val == 0)
3934 CE = MCConstantExpr::Create(INT32_MIN, getContext());
3936 // Now we should have the closing ']'
3937 E = Parser.getTok().getLoc();
3938 if (Parser.getTok().isNot(AsmToken::RBrac))
3939 return Error(E, "']' expected");
3940 Parser.Lex(); // Eat right bracket token.
3942 // Don't worry about range checking the value here. That's handled by
3943 // the is*() predicates.
3944 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
3945 ARM_AM::no_shift, 0, 0,
3948 // If there's a pre-indexing writeback marker, '!', just add it as a token
3950 if (Parser.getTok().is(AsmToken::Exclaim)) {
3951 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3952 Parser.Lex(); // Eat the '!'.
3958 // The register offset is optionally preceded by a '+' or '-'
3959 bool isNegative = false;
3960 if (Parser.getTok().is(AsmToken::Minus)) {
3962 Parser.Lex(); // Eat the '-'.
3963 } else if (Parser.getTok().is(AsmToken::Plus)) {
3965 Parser.Lex(); // Eat the '+'.
3968 E = Parser.getTok().getLoc();
3969 int OffsetRegNum = tryParseRegister();
3970 if (OffsetRegNum == -1)
3971 return Error(E, "register expected");
3973 // If there's a shift operator, handle it.
3974 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
3975 unsigned ShiftImm = 0;
3976 if (Parser.getTok().is(AsmToken::Comma)) {
3977 Parser.Lex(); // Eat the ','.
3978 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
3982 // Now we should have the closing ']'
3983 E = Parser.getTok().getLoc();
3984 if (Parser.getTok().isNot(AsmToken::RBrac))
3985 return Error(E, "']' expected");
3986 Parser.Lex(); // Eat right bracket token.
3988 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
3989 ShiftType, ShiftImm, 0, isNegative,
3992 // If there's a pre-indexing writeback marker, '!', just add it as a token
3994 if (Parser.getTok().is(AsmToken::Exclaim)) {
3995 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3996 Parser.Lex(); // Eat the '!'.
4002 /// parseMemRegOffsetShift - one of these two:
4003 /// ( lsl | lsr | asr | ror ) , # shift_amount
4005 /// return true if it parses a shift otherwise it returns false.
4006 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4008 SMLoc Loc = Parser.getTok().getLoc();
4009 const AsmToken &Tok = Parser.getTok();
4010 if (Tok.isNot(AsmToken::Identifier))
4012 StringRef ShiftName = Tok.getString();
4013 if (ShiftName == "lsl" || ShiftName == "LSL" ||
4014 ShiftName == "asl" || ShiftName == "ASL")
4016 else if (ShiftName == "lsr" || ShiftName == "LSR")
4018 else if (ShiftName == "asr" || ShiftName == "ASR")
4020 else if (ShiftName == "ror" || ShiftName == "ROR")
4022 else if (ShiftName == "rrx" || ShiftName == "RRX")
4025 return Error(Loc, "illegal shift operator");
4026 Parser.Lex(); // Eat shift type token.
4028 // rrx stands alone.
4030 if (St != ARM_AM::rrx) {
4031 Loc = Parser.getTok().getLoc();
4032 // A '#' and a shift amount.
4033 const AsmToken &HashTok = Parser.getTok();
4034 if (HashTok.isNot(AsmToken::Hash) &&
4035 HashTok.isNot(AsmToken::Dollar))
4036 return Error(HashTok.getLoc(), "'#' expected");
4037 Parser.Lex(); // Eat hash token.
4040 if (getParser().ParseExpression(Expr))
4042 // Range check the immediate.
4043 // lsl, ror: 0 <= imm <= 31
4044 // lsr, asr: 0 <= imm <= 32
4045 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4047 return Error(Loc, "shift amount must be an immediate");
4048 int64_t Imm = CE->getValue();
4050 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4051 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4052 return Error(Loc, "immediate shift value out of range");
4059 /// parseFPImm - A floating point immediate expression operand.
4060 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4061 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4062 SMLoc S = Parser.getTok().getLoc();
4064 if (Parser.getTok().isNot(AsmToken::Hash) &&
4065 Parser.getTok().isNot(AsmToken::Dollar))
4066 return MatchOperand_NoMatch;
4068 // Disambiguate the VMOV forms that can accept an FP immediate.
4069 // vmov.f32 <sreg>, #imm
4070 // vmov.f64 <dreg>, #imm
4071 // vmov.f32 <dreg>, #imm @ vector f32x2
4072 // vmov.f32 <qreg>, #imm @ vector f32x4
4074 // There are also the NEON VMOV instructions which expect an
4075 // integer constant. Make sure we don't try to parse an FPImm
4077 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4078 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4079 if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
4080 TyOp->getToken() != ".f64"))
4081 return MatchOperand_NoMatch;
4083 Parser.Lex(); // Eat the '#'.
4085 // Handle negation, as that still comes through as a separate token.
4086 bool isNegative = false;
4087 if (Parser.getTok().is(AsmToken::Minus)) {
4091 const AsmToken &Tok = Parser.getTok();
4092 if (Tok.is(AsmToken::Real)) {
4093 APFloat RealVal(APFloat::IEEEdouble, Tok.getString());
4094 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4095 // If we had a '-' in front, toggle the sign bit.
4096 IntVal ^= (uint64_t)isNegative << 63;
4097 int Val = ARM_AM::getFP64Imm(APInt(64, IntVal));
4098 Parser.Lex(); // Eat the token.
4100 TokError("floating point value out of range");
4101 return MatchOperand_ParseFail;
4103 Operands.push_back(ARMOperand::CreateFPImm(Val, S, getContext()));
4104 return MatchOperand_Success;
4106 if (Tok.is(AsmToken::Integer)) {
4107 int64_t Val = Tok.getIntVal();
4108 Parser.Lex(); // Eat the token.
4109 if (Val > 255 || Val < 0) {
4110 TokError("encoded floating point value out of range");
4111 return MatchOperand_ParseFail;
4113 Operands.push_back(ARMOperand::CreateFPImm(Val, S, getContext()));
4114 return MatchOperand_Success;
4117 TokError("invalid floating point immediate");
4118 return MatchOperand_ParseFail;
4120 /// Parse a arm instruction operand. For now this parses the operand regardless
4121 /// of the mnemonic.
4122 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4123 StringRef Mnemonic) {
4126 // Check if the current operand has a custom associated parser, if so, try to
4127 // custom parse the operand, or fallback to the general approach.
4128 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4129 if (ResTy == MatchOperand_Success)
4131 // If there wasn't a custom match, try the generic matcher below. Otherwise,
4132 // there was a match, but an error occurred, in which case, just return that
4133 // the operand parsing failed.
4134 if (ResTy == MatchOperand_ParseFail)
4137 switch (getLexer().getKind()) {
4139 Error(Parser.getTok().getLoc(), "unexpected token in operand");
4141 case AsmToken::Identifier: {
4142 // If this is VMRS, check for the apsr_nzcv operand.
4143 if (!tryParseRegisterWithWriteBack(Operands))
4145 int Res = tryParseShiftRegister(Operands);
4146 if (Res == 0) // success
4148 else if (Res == -1) // irrecoverable error
4150 if (Mnemonic == "vmrs" && Parser.getTok().getString() == "apsr_nzcv") {
4151 S = Parser.getTok().getLoc();
4153 Operands.push_back(ARMOperand::CreateToken("apsr_nzcv", S));
4157 // Fall though for the Identifier case that is not a register or a
4160 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
4161 case AsmToken::Integer: // things like 1f and 2b as a branch targets
4162 case AsmToken::String: // quoted label names.
4163 case AsmToken::Dot: { // . as a branch target
4164 // This was not a register so parse other operands that start with an
4165 // identifier (like labels) as expressions and create them as immediates.
4166 const MCExpr *IdVal;
4167 S = Parser.getTok().getLoc();
4168 if (getParser().ParseExpression(IdVal))
4170 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4171 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4174 case AsmToken::LBrac:
4175 return parseMemory(Operands);
4176 case AsmToken::LCurly:
4177 return parseRegisterList(Operands);
4178 case AsmToken::Dollar:
4179 case AsmToken::Hash: {
4180 // #42 -> immediate.
4181 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
4182 S = Parser.getTok().getLoc();
4184 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4185 const MCExpr *ImmVal;
4186 if (getParser().ParseExpression(ImmVal))
4188 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4190 int32_t Val = CE->getValue();
4191 if (isNegative && Val == 0)
4192 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4194 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4195 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4198 case AsmToken::Colon: {
4199 // ":lower16:" and ":upper16:" expression prefixes
4200 // FIXME: Check it's an expression prefix,
4201 // e.g. (FOO - :lower16:BAR) isn't legal.
4202 ARMMCExpr::VariantKind RefKind;
4203 if (parsePrefix(RefKind))
4206 const MCExpr *SubExprVal;
4207 if (getParser().ParseExpression(SubExprVal))
4210 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4212 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4213 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4219 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4220 // :lower16: and :upper16:.
4221 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4222 RefKind = ARMMCExpr::VK_ARM_None;
4224 // :lower16: and :upper16: modifiers
4225 assert(getLexer().is(AsmToken::Colon) && "expected a :");
4226 Parser.Lex(); // Eat ':'
4228 if (getLexer().isNot(AsmToken::Identifier)) {
4229 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4233 StringRef IDVal = Parser.getTok().getIdentifier();
4234 if (IDVal == "lower16") {
4235 RefKind = ARMMCExpr::VK_ARM_LO16;
4236 } else if (IDVal == "upper16") {
4237 RefKind = ARMMCExpr::VK_ARM_HI16;
4239 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4244 if (getLexer().isNot(AsmToken::Colon)) {
4245 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4248 Parser.Lex(); // Eat the last ':'
4252 /// \brief Given a mnemonic, split out possible predication code and carry
4253 /// setting letters to form a canonical mnemonic and flags.
4255 // FIXME: Would be nice to autogen this.
4256 // FIXME: This is a bit of a maze of special cases.
4257 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4258 unsigned &PredicationCode,
4260 unsigned &ProcessorIMod,
4261 StringRef &ITMask) {
4262 PredicationCode = ARMCC::AL;
4263 CarrySetting = false;
4266 // Ignore some mnemonics we know aren't predicated forms.
4268 // FIXME: Would be nice to autogen this.
4269 if ((Mnemonic == "movs" && isThumb()) ||
4270 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
4271 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
4272 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
4273 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
4274 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
4275 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
4276 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
4279 // First, split out any predication code. Ignore mnemonics we know aren't
4280 // predicated but do have a carry-set and so weren't caught above.
4281 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4282 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4283 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4284 Mnemonic != "sbcs" && Mnemonic != "rscs") {
4285 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4286 .Case("eq", ARMCC::EQ)
4287 .Case("ne", ARMCC::NE)
4288 .Case("hs", ARMCC::HS)
4289 .Case("cs", ARMCC::HS)
4290 .Case("lo", ARMCC::LO)
4291 .Case("cc", ARMCC::LO)
4292 .Case("mi", ARMCC::MI)
4293 .Case("pl", ARMCC::PL)
4294 .Case("vs", ARMCC::VS)
4295 .Case("vc", ARMCC::VC)
4296 .Case("hi", ARMCC::HI)
4297 .Case("ls", ARMCC::LS)
4298 .Case("ge", ARMCC::GE)
4299 .Case("lt", ARMCC::LT)
4300 .Case("gt", ARMCC::GT)
4301 .Case("le", ARMCC::LE)
4302 .Case("al", ARMCC::AL)
4305 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4306 PredicationCode = CC;
4310 // Next, determine if we have a carry setting bit. We explicitly ignore all
4311 // the instructions we know end in 's'.
4312 if (Mnemonic.endswith("s") &&
4313 !(Mnemonic == "cps" || Mnemonic == "mls" ||
4314 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4315 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4316 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4317 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4318 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4319 Mnemonic == "fsts" ||
4320 (Mnemonic == "movs" && isThumb()))) {
4321 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4322 CarrySetting = true;
4325 // The "cps" instruction can have a interrupt mode operand which is glued into
4326 // the mnemonic. Check if this is the case, split it and parse the imod op
4327 if (Mnemonic.startswith("cps")) {
4328 // Split out any imod code.
4330 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4331 .Case("ie", ARM_PROC::IE)
4332 .Case("id", ARM_PROC::ID)
4335 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4336 ProcessorIMod = IMod;
4340 // The "it" instruction has the condition mask on the end of the mnemonic.
4341 if (Mnemonic.startswith("it")) {
4342 ITMask = Mnemonic.slice(2, Mnemonic.size());
4343 Mnemonic = Mnemonic.slice(0, 2);
4349 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
4350 /// inclusion of carry set or predication code operands.
4352 // FIXME: It would be nice to autogen this.
4354 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
4355 bool &CanAcceptPredicationCode) {
4356 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4357 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4358 Mnemonic == "add" || Mnemonic == "adc" ||
4359 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4360 Mnemonic == "orr" || Mnemonic == "mvn" ||
4361 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4362 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4363 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4364 Mnemonic == "mla" || Mnemonic == "smlal" ||
4365 Mnemonic == "umlal" || Mnemonic == "umull"))) {
4366 CanAcceptCarrySet = true;
4368 CanAcceptCarrySet = false;
4370 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
4371 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
4372 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
4373 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
4374 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
4375 (Mnemonic == "clrex" && !isThumb()) ||
4376 (Mnemonic == "nop" && isThumbOne()) ||
4377 ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" ||
4378 Mnemonic == "ldc2" || Mnemonic == "ldc2l" ||
4379 Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) ||
4380 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
4382 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
4383 CanAcceptPredicationCode = false;
4385 CanAcceptPredicationCode = true;
4388 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
4389 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
4390 CanAcceptPredicationCode = false;
4394 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4395 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4396 // FIXME: This is all horribly hacky. We really need a better way to deal
4397 // with optional operands like this in the matcher table.
4399 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4400 // another does not. Specifically, the MOVW instruction does not. So we
4401 // special case it here and remove the defaulted (non-setting) cc_out
4402 // operand if that's the instruction we're trying to match.
4404 // We do this as post-processing of the explicit operands rather than just
4405 // conditionally adding the cc_out in the first place because we need
4406 // to check the type of the parsed immediate operand.
4407 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4408 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4409 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4410 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4413 // Register-register 'add' for thumb does not have a cc_out operand
4414 // when there are only two register operands.
4415 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4416 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4417 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4418 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4420 // Register-register 'add' for thumb does not have a cc_out operand
4421 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4422 // have to check the immediate range here since Thumb2 has a variant
4423 // that can handle a different range and has a cc_out operand.
4424 if (((isThumb() && Mnemonic == "add") ||
4425 (isThumbTwo() && Mnemonic == "sub")) &&
4426 Operands.size() == 6 &&
4427 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4428 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4429 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4430 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4431 (static_cast<ARMOperand*>(Operands[5])->isReg() ||
4432 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4434 // For Thumb2, add/sub immediate does not have a cc_out operand for the
4435 // imm0_4095 variant. That's the least-preferred variant when
4436 // selecting via the generic "add" mnemonic, so to know that we
4437 // should remove the cc_out operand, we have to explicitly check that
4438 // it's not one of the other variants. Ugh.
4439 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4440 Operands.size() == 6 &&
4441 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4442 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4443 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4444 // Nest conditions rather than one big 'if' statement for readability.
4446 // If either register is a high reg, it's either one of the SP
4447 // variants (handled above) or a 32-bit encoding, so we just
4448 // check against T3.
4449 if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4450 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
4451 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
4453 // If both registers are low, we're in an IT block, and the immediate is
4454 // in range, we should use encoding T1 instead, which has a cc_out.
4456 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4457 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4458 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
4461 // Otherwise, we use encoding T4, which does not have a cc_out
4466 // The thumb2 multiply instruction doesn't have a CCOut register, so
4467 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
4468 // use the 16-bit encoding or not.
4469 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
4470 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4471 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4472 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4473 static_cast<ARMOperand*>(Operands[5])->isReg() &&
4474 // If the registers aren't low regs, the destination reg isn't the
4475 // same as one of the source regs, or the cc_out operand is zero
4476 // outside of an IT block, we have to use the 32-bit encoding, so
4477 // remove the cc_out operand.
4478 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4479 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4480 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
4482 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4483 static_cast<ARMOperand*>(Operands[5])->getReg() &&
4484 static_cast<ARMOperand*>(Operands[3])->getReg() !=
4485 static_cast<ARMOperand*>(Operands[4])->getReg())))
4488 // Also check the 'mul' syntax variant that doesn't specify an explicit
4489 // destination register.
4490 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
4491 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4492 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4493 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4494 // If the registers aren't low regs or the cc_out operand is zero
4495 // outside of an IT block, we have to use the 32-bit encoding, so
4496 // remove the cc_out operand.
4497 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4498 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4504 // Register-register 'add/sub' for thumb does not have a cc_out operand
4505 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
4506 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
4507 // right, this will result in better diagnostics (which operand is off)
4509 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
4510 (Operands.size() == 5 || Operands.size() == 6) &&
4511 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4512 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4513 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4519 static bool isDataTypeToken(StringRef Tok) {
4520 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
4521 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
4522 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
4523 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
4524 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
4525 Tok == ".f" || Tok == ".d";
4528 // FIXME: This bit should probably be handled via an explicit match class
4529 // in the .td files that matches the suffix instead of having it be
4530 // a literal string token the way it is now.
4531 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
4532 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
4535 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features);
4536 /// Parse an arm instruction mnemonic followed by its operands.
4537 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
4538 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4539 // Apply mnemonic aliases before doing anything else, as the destination
4540 // mnemnonic may include suffices and we want to handle them normally.
4541 // The generic tblgen'erated code does this later, at the start of
4542 // MatchInstructionImpl(), but that's too late for aliases that include
4543 // any sort of suffix.
4544 unsigned AvailableFeatures = getAvailableFeatures();
4545 applyMnemonicAliases(Name, AvailableFeatures);
4547 // Create the leading tokens for the mnemonic, split by '.' characters.
4548 size_t Start = 0, Next = Name.find('.');
4549 StringRef Mnemonic = Name.slice(Start, Next);
4551 // Split out the predication code and carry setting flag from the mnemonic.
4552 unsigned PredicationCode;
4553 unsigned ProcessorIMod;
4556 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
4557 ProcessorIMod, ITMask);
4559 // In Thumb1, only the branch (B) instruction can be predicated.
4560 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
4561 Parser.EatToEndOfStatement();
4562 return Error(NameLoc, "conditional execution not supported in Thumb1");
4565 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
4567 // Handle the IT instruction ITMask. Convert it to a bitmask. This
4568 // is the mask as it will be for the IT encoding if the conditional
4569 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
4570 // where the conditional bit0 is zero, the instruction post-processing
4571 // will adjust the mask accordingly.
4572 if (Mnemonic == "it") {
4573 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
4574 if (ITMask.size() > 3) {
4575 Parser.EatToEndOfStatement();
4576 return Error(Loc, "too many conditions on IT instruction");
4579 for (unsigned i = ITMask.size(); i != 0; --i) {
4580 char pos = ITMask[i - 1];
4581 if (pos != 't' && pos != 'e') {
4582 Parser.EatToEndOfStatement();
4583 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
4586 if (ITMask[i - 1] == 't')
4589 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
4592 // FIXME: This is all a pretty gross hack. We should automatically handle
4593 // optional operands like this via tblgen.
4595 // Next, add the CCOut and ConditionCode operands, if needed.
4597 // For mnemonics which can ever incorporate a carry setting bit or predication
4598 // code, our matching model involves us always generating CCOut and
4599 // ConditionCode operands to match the mnemonic "as written" and then we let
4600 // the matcher deal with finding the right instruction or generating an
4601 // appropriate error.
4602 bool CanAcceptCarrySet, CanAcceptPredicationCode;
4603 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
4605 // If we had a carry-set on an instruction that can't do that, issue an
4607 if (!CanAcceptCarrySet && CarrySetting) {
4608 Parser.EatToEndOfStatement();
4609 return Error(NameLoc, "instruction '" + Mnemonic +
4610 "' can not set flags, but 's' suffix specified");
4612 // If we had a predication code on an instruction that can't do that, issue an
4614 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
4615 Parser.EatToEndOfStatement();
4616 return Error(NameLoc, "instruction '" + Mnemonic +
4617 "' is not predicable, but condition code specified");
4620 // Add the carry setting operand, if necessary.
4621 if (CanAcceptCarrySet) {
4622 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
4623 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
4627 // Add the predication code operand, if necessary.
4628 if (CanAcceptPredicationCode) {
4629 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
4631 Operands.push_back(ARMOperand::CreateCondCode(
4632 ARMCC::CondCodes(PredicationCode), Loc));
4635 // Add the processor imod operand, if necessary.
4636 if (ProcessorIMod) {
4637 Operands.push_back(ARMOperand::CreateImm(
4638 MCConstantExpr::Create(ProcessorIMod, getContext()),
4642 // Add the remaining tokens in the mnemonic.
4643 while (Next != StringRef::npos) {
4645 Next = Name.find('.', Start + 1);
4646 StringRef ExtraToken = Name.slice(Start, Next);
4648 // Some NEON instructions have an optional datatype suffix that is
4649 // completely ignored. Check for that.
4650 if (isDataTypeToken(ExtraToken) &&
4651 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
4654 if (ExtraToken != ".n") {
4655 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
4656 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
4660 // Read the remaining operands.
4661 if (getLexer().isNot(AsmToken::EndOfStatement)) {
4662 // Read the first operand.
4663 if (parseOperand(Operands, Mnemonic)) {
4664 Parser.EatToEndOfStatement();
4668 while (getLexer().is(AsmToken::Comma)) {
4669 Parser.Lex(); // Eat the comma.
4671 // Parse and remember the operand.
4672 if (parseOperand(Operands, Mnemonic)) {
4673 Parser.EatToEndOfStatement();
4679 if (getLexer().isNot(AsmToken::EndOfStatement)) {
4680 SMLoc Loc = getLexer().getLoc();
4681 Parser.EatToEndOfStatement();
4682 return Error(Loc, "unexpected token in argument list");
4685 Parser.Lex(); // Consume the EndOfStatement
4687 // Some instructions, mostly Thumb, have forms for the same mnemonic that
4688 // do and don't have a cc_out optional-def operand. With some spot-checks
4689 // of the operand list, we can figure out which variant we're trying to
4690 // parse and adjust accordingly before actually matching. We shouldn't ever
4691 // try to remove a cc_out operand that was explicitly set on the the
4692 // mnemonic, of course (CarrySetting == true). Reason number #317 the
4693 // table driven matcher doesn't fit well with the ARM instruction set.
4694 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
4695 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
4696 Operands.erase(Operands.begin() + 1);
4700 // ARM mode 'blx' need special handling, as the register operand version
4701 // is predicable, but the label operand version is not. So, we can't rely
4702 // on the Mnemonic based checking to correctly figure out when to put
4703 // a k_CondCode operand in the list. If we're trying to match the label
4704 // version, remove the k_CondCode operand here.
4705 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
4706 static_cast<ARMOperand*>(Operands[2])->isImm()) {
4707 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
4708 Operands.erase(Operands.begin() + 1);
4712 // The vector-compare-to-zero instructions have a literal token "#0" at
4713 // the end that comes to here as an immediate operand. Convert it to a
4714 // token to play nicely with the matcher.
4715 if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
4716 Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
4717 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4718 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
4719 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4720 if (CE && CE->getValue() == 0) {
4721 Operands.erase(Operands.begin() + 5);
4722 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4726 // VCMP{E} does the same thing, but with a different operand count.
4727 if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 &&
4728 static_cast<ARMOperand*>(Operands[4])->isImm()) {
4729 ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]);
4730 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4731 if (CE && CE->getValue() == 0) {
4732 Operands.erase(Operands.begin() + 4);
4733 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4737 // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
4738 // end. Convert it to a token here. Take care not to convert those
4739 // that should hit the Thumb2 encoding.
4740 if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
4741 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4742 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4743 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4744 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
4745 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4746 if (CE && CE->getValue() == 0 &&
4748 // The cc_out operand matches the IT block.
4749 ((inITBlock() != CarrySetting) &&
4750 // Neither register operand is a high register.
4751 (isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4752 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()))))){
4753 Operands.erase(Operands.begin() + 5);
4754 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4762 // Validate context-sensitive operand constraints.
4764 // return 'true' if register list contains non-low GPR registers,
4765 // 'false' otherwise. If Reg is in the register list or is HiReg, set
4766 // 'containsReg' to true.
4767 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
4768 unsigned HiReg, bool &containsReg) {
4769 containsReg = false;
4770 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
4771 unsigned OpReg = Inst.getOperand(i).getReg();
4774 // Anything other than a low register isn't legal here.
4775 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
4781 // Check if the specified regisgter is in the register list of the inst,
4782 // starting at the indicated operand number.
4783 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
4784 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
4785 unsigned OpReg = Inst.getOperand(i).getReg();
4792 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around
4793 // the ARMInsts array) instead. Getting that here requires awkward
4794 // API changes, though. Better way?
4796 extern const MCInstrDesc ARMInsts[];
4798 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
4799 return ARMInsts[Opcode];
4802 // FIXME: We would really like to be able to tablegen'erate this.
4804 validateInstruction(MCInst &Inst,
4805 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4806 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
4807 SMLoc Loc = Operands[0]->getStartLoc();
4808 // Check the IT block state first.
4809 // NOTE: In Thumb mode, the BKPT instruction has the interesting property of
4810 // being allowed in IT blocks, but not being predicable. It just always
4812 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT) {
4814 if (ITState.FirstCond)
4815 ITState.FirstCond = false;
4817 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
4818 // The instruction must be predicable.
4819 if (!MCID.isPredicable())
4820 return Error(Loc, "instructions in IT block must be predicable");
4821 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
4822 unsigned ITCond = bit ? ITState.Cond :
4823 ARMCC::getOppositeCondition(ITState.Cond);
4824 if (Cond != ITCond) {
4825 // Find the condition code Operand to get its SMLoc information.
4827 for (unsigned i = 1; i < Operands.size(); ++i)
4828 if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
4829 CondLoc = Operands[i]->getStartLoc();
4830 return Error(CondLoc, "incorrect condition in IT block; got '" +
4831 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
4832 "', but expected '" +
4833 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
4835 // Check for non-'al' condition codes outside of the IT block.
4836 } else if (isThumbTwo() && MCID.isPredicable() &&
4837 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
4838 ARMCC::AL && Inst.getOpcode() != ARM::tB &&
4839 Inst.getOpcode() != ARM::t2B)
4840 return Error(Loc, "predicated instructions must be in IT block");
4842 switch (Inst.getOpcode()) {
4845 case ARM::LDRD_POST:
4847 // Rt2 must be Rt + 1.
4848 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
4849 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
4851 return Error(Operands[3]->getStartLoc(),
4852 "destination operands must be sequential");
4856 // Rt2 must be Rt + 1.
4857 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
4858 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
4860 return Error(Operands[3]->getStartLoc(),
4861 "source operands must be sequential");
4865 case ARM::STRD_POST:
4867 // Rt2 must be Rt + 1.
4868 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
4869 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
4871 return Error(Operands[3]->getStartLoc(),
4872 "source operands must be sequential");
4877 // width must be in range [1, 32-lsb]
4878 unsigned lsb = Inst.getOperand(2).getImm();
4879 unsigned widthm1 = Inst.getOperand(3).getImm();
4880 if (widthm1 >= 32 - lsb)
4881 return Error(Operands[5]->getStartLoc(),
4882 "bitfield width must be in range [1,32-lsb]");
4886 // If we're parsing Thumb2, the .w variant is available and handles
4887 // most cases that are normally illegal for a Thumb1 LDM
4888 // instruction. We'll make the transformation in processInstruction()
4891 // Thumb LDM instructions are writeback iff the base register is not
4892 // in the register list.
4893 unsigned Rn = Inst.getOperand(0).getReg();
4894 bool hasWritebackToken =
4895 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
4896 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
4897 bool listContainsBase;
4898 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
4899 return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
4900 "registers must be in range r0-r7");
4901 // If we should have writeback, then there should be a '!' token.
4902 if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
4903 return Error(Operands[2]->getStartLoc(),
4904 "writeback operator '!' expected");
4905 // If we should not have writeback, there must not be a '!'. This is
4906 // true even for the 32-bit wide encodings.
4907 if (listContainsBase && hasWritebackToken)
4908 return Error(Operands[3]->getStartLoc(),
4909 "writeback operator '!' not allowed when base register "
4910 "in register list");
4914 case ARM::t2LDMIA_UPD: {
4915 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
4916 return Error(Operands[4]->getStartLoc(),
4917 "writeback operator '!' not allowed when base register "
4918 "in register list");
4921 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
4922 // so only issue a diagnostic for thumb1. The instructions will be
4923 // switched to the t2 encodings in processInstruction() if necessary.
4925 bool listContainsBase;
4926 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
4928 return Error(Operands[2]->getStartLoc(),
4929 "registers must be in range r0-r7 or pc");
4933 bool listContainsBase;
4934 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
4936 return Error(Operands[2]->getStartLoc(),
4937 "registers must be in range r0-r7 or lr");
4940 case ARM::tSTMIA_UPD: {
4941 bool listContainsBase;
4942 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
4943 return Error(Operands[4]->getStartLoc(),
4944 "registers must be in range r0-r7");
4952 static unsigned getRealVSTLNOpcode(unsigned Opc) {
4954 default: assert(0 && "unexpected opcode!");
4955 case ARM::VST1LNdWB_fixed_Asm_8: return ARM::VST1LNd8_UPD;
4956 case ARM::VST1LNdWB_fixed_Asm_P8: return ARM::VST1LNd8_UPD;
4957 case ARM::VST1LNdWB_fixed_Asm_I8: return ARM::VST1LNd8_UPD;
4958 case ARM::VST1LNdWB_fixed_Asm_S8: return ARM::VST1LNd8_UPD;
4959 case ARM::VST1LNdWB_fixed_Asm_U8: return ARM::VST1LNd8_UPD;
4960 case ARM::VST1LNdWB_fixed_Asm_16: return ARM::VST1LNd16_UPD;
4961 case ARM::VST1LNdWB_fixed_Asm_P16: return ARM::VST1LNd16_UPD;
4962 case ARM::VST1LNdWB_fixed_Asm_I16: return ARM::VST1LNd16_UPD;
4963 case ARM::VST1LNdWB_fixed_Asm_S16: return ARM::VST1LNd16_UPD;
4964 case ARM::VST1LNdWB_fixed_Asm_U16: return ARM::VST1LNd16_UPD;
4965 case ARM::VST1LNdWB_fixed_Asm_32: return ARM::VST1LNd32_UPD;
4966 case ARM::VST1LNdWB_fixed_Asm_F: return ARM::VST1LNd32_UPD;
4967 case ARM::VST1LNdWB_fixed_Asm_F32: return ARM::VST1LNd32_UPD;
4968 case ARM::VST1LNdWB_fixed_Asm_I32: return ARM::VST1LNd32_UPD;
4969 case ARM::VST1LNdWB_fixed_Asm_S32: return ARM::VST1LNd32_UPD;
4970 case ARM::VST1LNdWB_fixed_Asm_U32: return ARM::VST1LNd32_UPD;
4971 case ARM::VST1LNdWB_register_Asm_8: return ARM::VST1LNd8_UPD;
4972 case ARM::VST1LNdWB_register_Asm_P8: return ARM::VST1LNd8_UPD;
4973 case ARM::VST1LNdWB_register_Asm_I8: return ARM::VST1LNd8_UPD;
4974 case ARM::VST1LNdWB_register_Asm_S8: return ARM::VST1LNd8_UPD;
4975 case ARM::VST1LNdWB_register_Asm_U8: return ARM::VST1LNd8_UPD;
4976 case ARM::VST1LNdWB_register_Asm_16: return ARM::VST1LNd16_UPD;
4977 case ARM::VST1LNdWB_register_Asm_P16: return ARM::VST1LNd16_UPD;
4978 case ARM::VST1LNdWB_register_Asm_I16: return ARM::VST1LNd16_UPD;
4979 case ARM::VST1LNdWB_register_Asm_S16: return ARM::VST1LNd16_UPD;
4980 case ARM::VST1LNdWB_register_Asm_U16: return ARM::VST1LNd16_UPD;
4981 case ARM::VST1LNdWB_register_Asm_32: return ARM::VST1LNd32_UPD;
4982 case ARM::VST1LNdWB_register_Asm_F: return ARM::VST1LNd32_UPD;
4983 case ARM::VST1LNdWB_register_Asm_F32: return ARM::VST1LNd32_UPD;
4984 case ARM::VST1LNdWB_register_Asm_I32: return ARM::VST1LNd32_UPD;
4985 case ARM::VST1LNdWB_register_Asm_S32: return ARM::VST1LNd32_UPD;
4986 case ARM::VST1LNdWB_register_Asm_U32: return ARM::VST1LNd32_UPD;
4987 case ARM::VST1LNdAsm_8: return ARM::VST1LNd8;
4988 case ARM::VST1LNdAsm_P8: return ARM::VST1LNd8;
4989 case ARM::VST1LNdAsm_I8: return ARM::VST1LNd8;
4990 case ARM::VST1LNdAsm_S8: return ARM::VST1LNd8;
4991 case ARM::VST1LNdAsm_U8: return ARM::VST1LNd8;
4992 case ARM::VST1LNdAsm_16: return ARM::VST1LNd16;
4993 case ARM::VST1LNdAsm_P16: return ARM::VST1LNd16;
4994 case ARM::VST1LNdAsm_I16: return ARM::VST1LNd16;
4995 case ARM::VST1LNdAsm_S16: return ARM::VST1LNd16;
4996 case ARM::VST1LNdAsm_U16: return ARM::VST1LNd16;
4997 case ARM::VST1LNdAsm_32: return ARM::VST1LNd32;
4998 case ARM::VST1LNdAsm_F: return ARM::VST1LNd32;
4999 case ARM::VST1LNdAsm_F32: return ARM::VST1LNd32;
5000 case ARM::VST1LNdAsm_I32: return ARM::VST1LNd32;
5001 case ARM::VST1LNdAsm_S32: return ARM::VST1LNd32;
5002 case ARM::VST1LNdAsm_U32: return ARM::VST1LNd32;
5006 static unsigned getRealVLDLNOpcode(unsigned Opc) {
5008 default: assert(0 && "unexpected opcode!");
5009 case ARM::VLD1LNdWB_fixed_Asm_8: return ARM::VLD1LNd8_UPD;
5010 case ARM::VLD1LNdWB_fixed_Asm_P8: return ARM::VLD1LNd8_UPD;
5011 case ARM::VLD1LNdWB_fixed_Asm_I8: return ARM::VLD1LNd8_UPD;
5012 case ARM::VLD1LNdWB_fixed_Asm_S8: return ARM::VLD1LNd8_UPD;
5013 case ARM::VLD1LNdWB_fixed_Asm_U8: return ARM::VLD1LNd8_UPD;
5014 case ARM::VLD1LNdWB_fixed_Asm_16: return ARM::VLD1LNd16_UPD;
5015 case ARM::VLD1LNdWB_fixed_Asm_P16: return ARM::VLD1LNd16_UPD;
5016 case ARM::VLD1LNdWB_fixed_Asm_I16: return ARM::VLD1LNd16_UPD;
5017 case ARM::VLD1LNdWB_fixed_Asm_S16: return ARM::VLD1LNd16_UPD;
5018 case ARM::VLD1LNdWB_fixed_Asm_U16: return ARM::VLD1LNd16_UPD;
5019 case ARM::VLD1LNdWB_fixed_Asm_32: return ARM::VLD1LNd32_UPD;
5020 case ARM::VLD1LNdWB_fixed_Asm_F: return ARM::VLD1LNd32_UPD;
5021 case ARM::VLD1LNdWB_fixed_Asm_F32: return ARM::VLD1LNd32_UPD;
5022 case ARM::VLD1LNdWB_fixed_Asm_I32: return ARM::VLD1LNd32_UPD;
5023 case ARM::VLD1LNdWB_fixed_Asm_S32: return ARM::VLD1LNd32_UPD;
5024 case ARM::VLD1LNdWB_fixed_Asm_U32: return ARM::VLD1LNd32_UPD;
5025 case ARM::VLD1LNdWB_register_Asm_8: return ARM::VLD1LNd8_UPD;
5026 case ARM::VLD1LNdWB_register_Asm_P8: return ARM::VLD1LNd8_UPD;
5027 case ARM::VLD1LNdWB_register_Asm_I8: return ARM::VLD1LNd8_UPD;
5028 case ARM::VLD1LNdWB_register_Asm_S8: return ARM::VLD1LNd8_UPD;
5029 case ARM::VLD1LNdWB_register_Asm_U8: return ARM::VLD1LNd8_UPD;
5030 case ARM::VLD1LNdWB_register_Asm_16: return ARM::VLD1LNd16_UPD;
5031 case ARM::VLD1LNdWB_register_Asm_P16: return ARM::VLD1LNd16_UPD;
5032 case ARM::VLD1LNdWB_register_Asm_I16: return ARM::VLD1LNd16_UPD;
5033 case ARM::VLD1LNdWB_register_Asm_S16: return ARM::VLD1LNd16_UPD;
5034 case ARM::VLD1LNdWB_register_Asm_U16: return ARM::VLD1LNd16_UPD;
5035 case ARM::VLD1LNdWB_register_Asm_32: return ARM::VLD1LNd32_UPD;
5036 case ARM::VLD1LNdWB_register_Asm_F: return ARM::VLD1LNd32_UPD;
5037 case ARM::VLD1LNdWB_register_Asm_F32: return ARM::VLD1LNd32_UPD;
5038 case ARM::VLD1LNdWB_register_Asm_I32: return ARM::VLD1LNd32_UPD;
5039 case ARM::VLD1LNdWB_register_Asm_S32: return ARM::VLD1LNd32_UPD;
5040 case ARM::VLD1LNdWB_register_Asm_U32: return ARM::VLD1LNd32_UPD;
5041 case ARM::VLD1LNdAsm_8: return ARM::VLD1LNd8;
5042 case ARM::VLD1LNdAsm_P8: return ARM::VLD1LNd8;
5043 case ARM::VLD1LNdAsm_I8: return ARM::VLD1LNd8;
5044 case ARM::VLD1LNdAsm_S8: return ARM::VLD1LNd8;
5045 case ARM::VLD1LNdAsm_U8: return ARM::VLD1LNd8;
5046 case ARM::VLD1LNdAsm_16: return ARM::VLD1LNd16;
5047 case ARM::VLD1LNdAsm_P16: return ARM::VLD1LNd16;
5048 case ARM::VLD1LNdAsm_I16: return ARM::VLD1LNd16;
5049 case ARM::VLD1LNdAsm_S16: return ARM::VLD1LNd16;
5050 case ARM::VLD1LNdAsm_U16: return ARM::VLD1LNd16;
5051 case ARM::VLD1LNdAsm_32: return ARM::VLD1LNd32;
5052 case ARM::VLD1LNdAsm_F: return ARM::VLD1LNd32;
5053 case ARM::VLD1LNdAsm_F32: return ARM::VLD1LNd32;
5054 case ARM::VLD1LNdAsm_I32: return ARM::VLD1LNd32;
5055 case ARM::VLD1LNdAsm_S32: return ARM::VLD1LNd32;
5056 case ARM::VLD1LNdAsm_U32: return ARM::VLD1LNd32;
5061 processInstruction(MCInst &Inst,
5062 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5063 switch (Inst.getOpcode()) {
5064 // Handle NEON VST1 complex aliases.
5065 case ARM::VST1LNdWB_register_Asm_8:
5066 case ARM::VST1LNdWB_register_Asm_P8:
5067 case ARM::VST1LNdWB_register_Asm_I8:
5068 case ARM::VST1LNdWB_register_Asm_S8:
5069 case ARM::VST1LNdWB_register_Asm_U8:
5070 case ARM::VST1LNdWB_register_Asm_16:
5071 case ARM::VST1LNdWB_register_Asm_P16:
5072 case ARM::VST1LNdWB_register_Asm_I16:
5073 case ARM::VST1LNdWB_register_Asm_S16:
5074 case ARM::VST1LNdWB_register_Asm_U16:
5075 case ARM::VST1LNdWB_register_Asm_32:
5076 case ARM::VST1LNdWB_register_Asm_F:
5077 case ARM::VST1LNdWB_register_Asm_F32:
5078 case ARM::VST1LNdWB_register_Asm_I32:
5079 case ARM::VST1LNdWB_register_Asm_S32:
5080 case ARM::VST1LNdWB_register_Asm_U32: {
5082 // Shuffle the operands around so the lane index operand is in the
5084 TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode()));
5085 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5086 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5087 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5088 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5089 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5090 TmpInst.addOperand(Inst.getOperand(1)); // lane
5091 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5092 TmpInst.addOperand(Inst.getOperand(6));
5096 case ARM::VST1LNdWB_fixed_Asm_8:
5097 case ARM::VST1LNdWB_fixed_Asm_P8:
5098 case ARM::VST1LNdWB_fixed_Asm_I8:
5099 case ARM::VST1LNdWB_fixed_Asm_S8:
5100 case ARM::VST1LNdWB_fixed_Asm_U8:
5101 case ARM::VST1LNdWB_fixed_Asm_16:
5102 case ARM::VST1LNdWB_fixed_Asm_P16:
5103 case ARM::VST1LNdWB_fixed_Asm_I16:
5104 case ARM::VST1LNdWB_fixed_Asm_S16:
5105 case ARM::VST1LNdWB_fixed_Asm_U16:
5106 case ARM::VST1LNdWB_fixed_Asm_32:
5107 case ARM::VST1LNdWB_fixed_Asm_F:
5108 case ARM::VST1LNdWB_fixed_Asm_F32:
5109 case ARM::VST1LNdWB_fixed_Asm_I32:
5110 case ARM::VST1LNdWB_fixed_Asm_S32:
5111 case ARM::VST1LNdWB_fixed_Asm_U32: {
5113 // Shuffle the operands around so the lane index operand is in the
5115 TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode()));
5116 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5117 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5118 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5119 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5120 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5121 TmpInst.addOperand(Inst.getOperand(1)); // lane
5122 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5123 TmpInst.addOperand(Inst.getOperand(5));
5127 case ARM::VST1LNdAsm_8:
5128 case ARM::VST1LNdAsm_P8:
5129 case ARM::VST1LNdAsm_I8:
5130 case ARM::VST1LNdAsm_S8:
5131 case ARM::VST1LNdAsm_U8:
5132 case ARM::VST1LNdAsm_16:
5133 case ARM::VST1LNdAsm_P16:
5134 case ARM::VST1LNdAsm_I16:
5135 case ARM::VST1LNdAsm_S16:
5136 case ARM::VST1LNdAsm_U16:
5137 case ARM::VST1LNdAsm_32:
5138 case ARM::VST1LNdAsm_F:
5139 case ARM::VST1LNdAsm_F32:
5140 case ARM::VST1LNdAsm_I32:
5141 case ARM::VST1LNdAsm_S32:
5142 case ARM::VST1LNdAsm_U32: {
5144 // Shuffle the operands around so the lane index operand is in the
5146 TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode()));
5147 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5148 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5149 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5150 TmpInst.addOperand(Inst.getOperand(1)); // lane
5151 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5152 TmpInst.addOperand(Inst.getOperand(5));
5156 // Handle NEON VLD1 complex aliases.
5157 case ARM::VLD1LNdWB_register_Asm_8:
5158 case ARM::VLD1LNdWB_register_Asm_P8:
5159 case ARM::VLD1LNdWB_register_Asm_I8:
5160 case ARM::VLD1LNdWB_register_Asm_S8:
5161 case ARM::VLD1LNdWB_register_Asm_U8:
5162 case ARM::VLD1LNdWB_register_Asm_16:
5163 case ARM::VLD1LNdWB_register_Asm_P16:
5164 case ARM::VLD1LNdWB_register_Asm_I16:
5165 case ARM::VLD1LNdWB_register_Asm_S16:
5166 case ARM::VLD1LNdWB_register_Asm_U16:
5167 case ARM::VLD1LNdWB_register_Asm_32:
5168 case ARM::VLD1LNdWB_register_Asm_F:
5169 case ARM::VLD1LNdWB_register_Asm_F32:
5170 case ARM::VLD1LNdWB_register_Asm_I32:
5171 case ARM::VLD1LNdWB_register_Asm_S32:
5172 case ARM::VLD1LNdWB_register_Asm_U32: {
5174 // Shuffle the operands around so the lane index operand is in the
5176 TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode()));
5177 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5178 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5179 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5180 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5181 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5182 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5183 TmpInst.addOperand(Inst.getOperand(1)); // lane
5184 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5185 TmpInst.addOperand(Inst.getOperand(6));
5189 case ARM::VLD1LNdWB_fixed_Asm_8:
5190 case ARM::VLD1LNdWB_fixed_Asm_P8:
5191 case ARM::VLD1LNdWB_fixed_Asm_I8:
5192 case ARM::VLD1LNdWB_fixed_Asm_S8:
5193 case ARM::VLD1LNdWB_fixed_Asm_U8:
5194 case ARM::VLD1LNdWB_fixed_Asm_16:
5195 case ARM::VLD1LNdWB_fixed_Asm_P16:
5196 case ARM::VLD1LNdWB_fixed_Asm_I16:
5197 case ARM::VLD1LNdWB_fixed_Asm_S16:
5198 case ARM::VLD1LNdWB_fixed_Asm_U16:
5199 case ARM::VLD1LNdWB_fixed_Asm_32:
5200 case ARM::VLD1LNdWB_fixed_Asm_F:
5201 case ARM::VLD1LNdWB_fixed_Asm_F32:
5202 case ARM::VLD1LNdWB_fixed_Asm_I32:
5203 case ARM::VLD1LNdWB_fixed_Asm_S32:
5204 case ARM::VLD1LNdWB_fixed_Asm_U32: {
5206 // Shuffle the operands around so the lane index operand is in the
5208 TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode()));
5209 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5210 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5211 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5212 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5213 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5214 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5215 TmpInst.addOperand(Inst.getOperand(1)); // lane
5216 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5217 TmpInst.addOperand(Inst.getOperand(5));
5221 case ARM::VLD1LNdAsm_8:
5222 case ARM::VLD1LNdAsm_P8:
5223 case ARM::VLD1LNdAsm_I8:
5224 case ARM::VLD1LNdAsm_S8:
5225 case ARM::VLD1LNdAsm_U8:
5226 case ARM::VLD1LNdAsm_16:
5227 case ARM::VLD1LNdAsm_P16:
5228 case ARM::VLD1LNdAsm_I16:
5229 case ARM::VLD1LNdAsm_S16:
5230 case ARM::VLD1LNdAsm_U16:
5231 case ARM::VLD1LNdAsm_32:
5232 case ARM::VLD1LNdAsm_F:
5233 case ARM::VLD1LNdAsm_F32:
5234 case ARM::VLD1LNdAsm_I32:
5235 case ARM::VLD1LNdAsm_S32:
5236 case ARM::VLD1LNdAsm_U32: {
5238 // Shuffle the operands around so the lane index operand is in the
5240 TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode()));
5241 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5242 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5243 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5244 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5245 TmpInst.addOperand(Inst.getOperand(1)); // lane
5246 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5247 TmpInst.addOperand(Inst.getOperand(5));
5251 // Handle the Thumb2 mode MOV complex aliases.
5253 case ARM::t2MOVSsi: {
5254 // Which instruction to expand to depends on the CCOut operand and
5255 // whether we're in an IT block if the register operands are low
5257 bool isNarrow = false;
5258 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
5259 isARMLowRegister(Inst.getOperand(1).getReg()) &&
5260 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
5264 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
5265 default: llvm_unreachable("unexpected opcode!");
5266 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
5267 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
5268 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
5269 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
5271 unsigned Ammount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
5272 if (Ammount == 32) Ammount = 0;
5273 TmpInst.setOpcode(newOpc);
5274 TmpInst.addOperand(Inst.getOperand(0)); // Rd
5276 TmpInst.addOperand(MCOperand::CreateReg(
5277 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
5278 TmpInst.addOperand(Inst.getOperand(1)); // Rn
5279 TmpInst.addOperand(MCOperand::CreateImm(Ammount));
5280 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
5281 TmpInst.addOperand(Inst.getOperand(4));
5283 TmpInst.addOperand(MCOperand::CreateReg(
5284 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
5288 // Handle the ARM mode MOV complex aliases.
5293 ARM_AM::ShiftOpc ShiftTy;
5294 switch(Inst.getOpcode()) {
5295 default: llvm_unreachable("unexpected opcode!");
5296 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
5297 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
5298 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
5299 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
5301 // A shift by zero is a plain MOVr, not a MOVsi.
5302 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
5304 TmpInst.setOpcode(ARM::MOVsr);
5305 TmpInst.addOperand(Inst.getOperand(0)); // Rd
5306 TmpInst.addOperand(Inst.getOperand(1)); // Rn
5307 TmpInst.addOperand(Inst.getOperand(2)); // Rm
5308 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
5309 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
5310 TmpInst.addOperand(Inst.getOperand(4));
5311 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
5319 ARM_AM::ShiftOpc ShiftTy;
5320 switch(Inst.getOpcode()) {
5321 default: llvm_unreachable("unexpected opcode!");
5322 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
5323 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
5324 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
5325 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
5327 // A shift by zero is a plain MOVr, not a MOVsi.
5328 unsigned Amt = Inst.getOperand(2).getImm();
5329 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
5330 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
5332 TmpInst.setOpcode(Opc);
5333 TmpInst.addOperand(Inst.getOperand(0)); // Rd
5334 TmpInst.addOperand(Inst.getOperand(1)); // Rn
5335 if (Opc == ARM::MOVsi)
5336 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
5337 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
5338 TmpInst.addOperand(Inst.getOperand(4));
5339 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
5344 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
5346 TmpInst.setOpcode(ARM::MOVsi);
5347 TmpInst.addOperand(Inst.getOperand(0)); // Rd
5348 TmpInst.addOperand(Inst.getOperand(1)); // Rn
5349 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
5350 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
5351 TmpInst.addOperand(Inst.getOperand(3));
5352 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
5356 case ARM::t2LDMIA_UPD: {
5357 // If this is a load of a single register, then we should use
5358 // a post-indexed LDR instruction instead, per the ARM ARM.
5359 if (Inst.getNumOperands() != 5)
5362 TmpInst.setOpcode(ARM::t2LDR_POST);
5363 TmpInst.addOperand(Inst.getOperand(4)); // Rt
5364 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
5365 TmpInst.addOperand(Inst.getOperand(1)); // Rn
5366 TmpInst.addOperand(MCOperand::CreateImm(4));
5367 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
5368 TmpInst.addOperand(Inst.getOperand(3));
5372 case ARM::t2STMDB_UPD: {
5373 // If this is a store of a single register, then we should use
5374 // a pre-indexed STR instruction instead, per the ARM ARM.
5375 if (Inst.getNumOperands() != 5)
5378 TmpInst.setOpcode(ARM::t2STR_PRE);
5379 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
5380 TmpInst.addOperand(Inst.getOperand(4)); // Rt
5381 TmpInst.addOperand(Inst.getOperand(1)); // Rn
5382 TmpInst.addOperand(MCOperand::CreateImm(-4));
5383 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
5384 TmpInst.addOperand(Inst.getOperand(3));
5388 case ARM::LDMIA_UPD:
5389 // If this is a load of a single register via a 'pop', then we should use
5390 // a post-indexed LDR instruction instead, per the ARM ARM.
5391 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
5392 Inst.getNumOperands() == 5) {
5394 TmpInst.setOpcode(ARM::LDR_POST_IMM);
5395 TmpInst.addOperand(Inst.getOperand(4)); // Rt
5396 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
5397 TmpInst.addOperand(Inst.getOperand(1)); // Rn
5398 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
5399 TmpInst.addOperand(MCOperand::CreateImm(4));
5400 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
5401 TmpInst.addOperand(Inst.getOperand(3));
5406 case ARM::STMDB_UPD:
5407 // If this is a store of a single register via a 'push', then we should use
5408 // a pre-indexed STR instruction instead, per the ARM ARM.
5409 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
5410 Inst.getNumOperands() == 5) {
5412 TmpInst.setOpcode(ARM::STR_PRE_IMM);
5413 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
5414 TmpInst.addOperand(Inst.getOperand(4)); // Rt
5415 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
5416 TmpInst.addOperand(MCOperand::CreateImm(-4));
5417 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
5418 TmpInst.addOperand(Inst.getOperand(3));
5422 case ARM::t2ADDri12:
5423 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
5424 // mnemonic was used (not "addw"), encoding T3 is preferred.
5425 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
5426 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
5428 Inst.setOpcode(ARM::t2ADDri);
5429 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
5431 case ARM::t2SUBri12:
5432 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
5433 // mnemonic was used (not "subw"), encoding T3 is preferred.
5434 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
5435 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
5437 Inst.setOpcode(ARM::t2SUBri);
5438 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
5441 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
5442 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
5443 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
5444 // to encoding T1 if <Rd> is omitted."
5445 if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
5446 Inst.setOpcode(ARM::tADDi3);
5451 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
5452 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
5453 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
5454 // to encoding T1 if <Rd> is omitted."
5455 if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
5456 Inst.setOpcode(ARM::tSUBi3);
5460 case ARM::t2ADDrr: {
5461 // If the destination and first source operand are the same, and
5462 // there's no setting of the flags, use encoding T2 instead of T3.
5463 // Note that this is only for ADD, not SUB. This mirrors the system
5464 // 'as' behaviour. Make sure the wide encoding wasn't explicit.
5465 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
5466 Inst.getOperand(5).getReg() != 0 ||
5467 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5468 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
5471 TmpInst.setOpcode(ARM::tADDhirr);
5472 TmpInst.addOperand(Inst.getOperand(0));
5473 TmpInst.addOperand(Inst.getOperand(0));
5474 TmpInst.addOperand(Inst.getOperand(2));
5475 TmpInst.addOperand(Inst.getOperand(3));
5476 TmpInst.addOperand(Inst.getOperand(4));
5481 // A Thumb conditional branch outside of an IT block is a tBcc.
5482 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
5483 Inst.setOpcode(ARM::tBcc);
5488 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
5489 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
5490 Inst.setOpcode(ARM::t2Bcc);
5495 // If the conditional is AL or we're in an IT block, we really want t2B.
5496 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
5497 Inst.setOpcode(ARM::t2B);
5502 // If the conditional is AL, we really want tB.
5503 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
5504 Inst.setOpcode(ARM::tB);
5509 // If the register list contains any high registers, or if the writeback
5510 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
5511 // instead if we're in Thumb2. Otherwise, this should have generated
5512 // an error in validateInstruction().
5513 unsigned Rn = Inst.getOperand(0).getReg();
5514 bool hasWritebackToken =
5515 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5516 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5517 bool listContainsBase;
5518 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
5519 (!listContainsBase && !hasWritebackToken) ||
5520 (listContainsBase && hasWritebackToken)) {
5521 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
5522 assert (isThumbTwo());
5523 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
5524 // If we're switching to the updating version, we need to insert
5525 // the writeback tied operand.
5526 if (hasWritebackToken)
5527 Inst.insert(Inst.begin(),
5528 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
5533 case ARM::tSTMIA_UPD: {
5534 // If the register list contains any high registers, we need to use
5535 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
5536 // should have generated an error in validateInstruction().
5537 unsigned Rn = Inst.getOperand(0).getReg();
5538 bool listContainsBase;
5539 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
5540 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
5541 assert (isThumbTwo());
5542 Inst.setOpcode(ARM::t2STMIA_UPD);
5548 bool listContainsBase;
5549 // If the register list contains any high registers, we need to use
5550 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
5551 // should have generated an error in validateInstruction().
5552 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
5554 assert (isThumbTwo());
5555 Inst.setOpcode(ARM::t2LDMIA_UPD);
5556 // Add the base register and writeback operands.
5557 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
5558 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
5562 bool listContainsBase;
5563 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
5565 assert (isThumbTwo());
5566 Inst.setOpcode(ARM::t2STMDB_UPD);
5567 // Add the base register and writeback operands.
5568 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
5569 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
5573 // If we can use the 16-bit encoding and the user didn't explicitly
5574 // request the 32-bit variant, transform it here.
5575 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
5576 Inst.getOperand(1).getImm() <= 255 &&
5577 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
5578 Inst.getOperand(4).getReg() == ARM::CPSR) ||
5579 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
5580 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
5581 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
5582 // The operands aren't in the same order for tMOVi8...
5584 TmpInst.setOpcode(ARM::tMOVi8);
5585 TmpInst.addOperand(Inst.getOperand(0));
5586 TmpInst.addOperand(Inst.getOperand(4));
5587 TmpInst.addOperand(Inst.getOperand(1));
5588 TmpInst.addOperand(Inst.getOperand(2));
5589 TmpInst.addOperand(Inst.getOperand(3));
5596 // If we can use the 16-bit encoding and the user didn't explicitly
5597 // request the 32-bit variant, transform it here.
5598 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
5599 isARMLowRegister(Inst.getOperand(1).getReg()) &&
5600 Inst.getOperand(2).getImm() == ARMCC::AL &&
5601 Inst.getOperand(4).getReg() == ARM::CPSR &&
5602 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
5603 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
5604 // The operands aren't the same for tMOV[S]r... (no cc_out)
5606 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
5607 TmpInst.addOperand(Inst.getOperand(0));
5608 TmpInst.addOperand(Inst.getOperand(1));
5609 TmpInst.addOperand(Inst.getOperand(2));
5610 TmpInst.addOperand(Inst.getOperand(3));
5620 // If we can use the 16-bit encoding and the user didn't explicitly
5621 // request the 32-bit variant, transform it here.
5622 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
5623 isARMLowRegister(Inst.getOperand(1).getReg()) &&
5624 Inst.getOperand(2).getImm() == 0 &&
5625 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
5626 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
5628 switch (Inst.getOpcode()) {
5629 default: llvm_unreachable("Illegal opcode!");
5630 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
5631 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
5632 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
5633 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
5635 // The operands aren't the same for thumb1 (no rotate operand).
5637 TmpInst.setOpcode(NewOpc);
5638 TmpInst.addOperand(Inst.getOperand(0));
5639 TmpInst.addOperand(Inst.getOperand(1));
5640 TmpInst.addOperand(Inst.getOperand(3));
5641 TmpInst.addOperand(Inst.getOperand(4));
5648 // The mask bits for all but the first condition are represented as
5649 // the low bit of the condition code value implies 't'. We currently
5650 // always have 1 implies 't', so XOR toggle the bits if the low bit
5651 // of the condition code is zero. The encoding also expects the low
5652 // bit of the condition to be encoded as bit 4 of the mask operand,
5653 // so mask that in if needed
5654 MCOperand &MO = Inst.getOperand(1);
5655 unsigned Mask = MO.getImm();
5656 unsigned OrigMask = Mask;
5657 unsigned TZ = CountTrailingZeros_32(Mask);
5658 if ((Inst.getOperand(0).getImm() & 1) == 0) {
5659 assert(Mask && TZ <= 3 && "illegal IT mask value!");
5660 for (unsigned i = 3; i != TZ; --i)
5666 // Set up the IT block state according to the IT instruction we just
5668 assert(!inITBlock() && "nested IT blocks?!");
5669 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
5670 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
5671 ITState.CurPosition = 0;
5672 ITState.FirstCond = true;
5679 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
5680 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
5681 // suffix depending on whether they're in an IT block or not.
5682 unsigned Opc = Inst.getOpcode();
5683 const MCInstrDesc &MCID = getInstDesc(Opc);
5684 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
5685 assert(MCID.hasOptionalDef() &&
5686 "optionally flag setting instruction missing optional def operand");
5687 assert(MCID.NumOperands == Inst.getNumOperands() &&
5688 "operand count mismatch!");
5689 // Find the optional-def operand (cc_out).
5692 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
5695 // If we're parsing Thumb1, reject it completely.
5696 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
5697 return Match_MnemonicFail;
5698 // If we're parsing Thumb2, which form is legal depends on whether we're
5700 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
5702 return Match_RequiresITBlock;
5703 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
5705 return Match_RequiresNotITBlock;
5707 // Some high-register supporting Thumb1 encodings only allow both registers
5708 // to be from r0-r7 when in Thumb2.
5709 else if (Opc == ARM::tADDhirr && isThumbOne() &&
5710 isARMLowRegister(Inst.getOperand(1).getReg()) &&
5711 isARMLowRegister(Inst.getOperand(2).getReg()))
5712 return Match_RequiresThumb2;
5713 // Others only require ARMv6 or later.
5714 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
5715 isARMLowRegister(Inst.getOperand(0).getReg()) &&
5716 isARMLowRegister(Inst.getOperand(1).getReg()))
5717 return Match_RequiresV6;
5718 return Match_Success;
5722 MatchAndEmitInstruction(SMLoc IDLoc,
5723 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
5727 unsigned MatchResult;
5728 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
5729 switch (MatchResult) {
5732 // Context sensitive operand constraints aren't handled by the matcher,
5733 // so check them here.
5734 if (validateInstruction(Inst, Operands)) {
5735 // Still progress the IT block, otherwise one wrong condition causes
5736 // nasty cascading errors.
5737 forwardITPosition();
5741 // Some instructions need post-processing to, for example, tweak which
5742 // encoding is selected. Loop on it while changes happen so the
5743 // individual transformations can chain off each other. E.g.,
5744 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
5745 while (processInstruction(Inst, Operands))
5748 // Only move forward at the very end so that everything in validate
5749 // and process gets a consistent answer about whether we're in an IT
5751 forwardITPosition();
5753 Out.EmitInstruction(Inst);
5755 case Match_MissingFeature:
5756 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
5758 case Match_InvalidOperand: {
5759 SMLoc ErrorLoc = IDLoc;
5760 if (ErrorInfo != ~0U) {
5761 if (ErrorInfo >= Operands.size())
5762 return Error(IDLoc, "too few operands for instruction");
5764 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
5765 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
5768 return Error(ErrorLoc, "invalid operand for instruction");
5770 case Match_MnemonicFail:
5771 return Error(IDLoc, "invalid instruction");
5772 case Match_ConversionFail:
5773 // The converter function will have already emited a diagnostic.
5775 case Match_RequiresNotITBlock:
5776 return Error(IDLoc, "flag setting instruction only valid outside IT block");
5777 case Match_RequiresITBlock:
5778 return Error(IDLoc, "instruction only valid inside IT block");
5779 case Match_RequiresV6:
5780 return Error(IDLoc, "instruction variant requires ARMv6 or later");
5781 case Match_RequiresThumb2:
5782 return Error(IDLoc, "instruction variant requires Thumb2");
5785 llvm_unreachable("Implement any new match types added!");
5789 /// parseDirective parses the arm specific directives
5790 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
5791 StringRef IDVal = DirectiveID.getIdentifier();
5792 if (IDVal == ".word")
5793 return parseDirectiveWord(4, DirectiveID.getLoc());
5794 else if (IDVal == ".thumb")
5795 return parseDirectiveThumb(DirectiveID.getLoc());
5796 else if (IDVal == ".arm")
5797 return parseDirectiveARM(DirectiveID.getLoc());
5798 else if (IDVal == ".thumb_func")
5799 return parseDirectiveThumbFunc(DirectiveID.getLoc());
5800 else if (IDVal == ".code")
5801 return parseDirectiveCode(DirectiveID.getLoc());
5802 else if (IDVal == ".syntax")
5803 return parseDirectiveSyntax(DirectiveID.getLoc());
5807 /// parseDirectiveWord
5808 /// ::= .word [ expression (, expression)* ]
5809 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
5810 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5812 const MCExpr *Value;
5813 if (getParser().ParseExpression(Value))
5816 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
5818 if (getLexer().is(AsmToken::EndOfStatement))
5821 // FIXME: Improve diagnostic.
5822 if (getLexer().isNot(AsmToken::Comma))
5823 return Error(L, "unexpected token in directive");
5832 /// parseDirectiveThumb
5834 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
5835 if (getLexer().isNot(AsmToken::EndOfStatement))
5836 return Error(L, "unexpected token in directive");
5841 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
5845 /// parseDirectiveARM
5847 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
5848 if (getLexer().isNot(AsmToken::EndOfStatement))
5849 return Error(L, "unexpected token in directive");
5854 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
5858 /// parseDirectiveThumbFunc
5859 /// ::= .thumbfunc symbol_name
5860 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
5861 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
5862 bool isMachO = MAI.hasSubsectionsViaSymbols();
5865 // Darwin asm has function name after .thumb_func direction
5868 const AsmToken &Tok = Parser.getTok();
5869 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
5870 return Error(L, "unexpected token in .thumb_func directive");
5871 Name = Tok.getIdentifier();
5872 Parser.Lex(); // Consume the identifier token.
5875 if (getLexer().isNot(AsmToken::EndOfStatement))
5876 return Error(L, "unexpected token in directive");
5879 // FIXME: assuming function name will be the line following .thumb_func
5881 Name = Parser.getTok().getIdentifier();
5884 // Mark symbol as a thumb symbol.
5885 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
5886 getParser().getStreamer().EmitThumbFunc(Func);
5890 /// parseDirectiveSyntax
5891 /// ::= .syntax unified | divided
5892 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
5893 const AsmToken &Tok = Parser.getTok();
5894 if (Tok.isNot(AsmToken::Identifier))
5895 return Error(L, "unexpected token in .syntax directive");
5896 StringRef Mode = Tok.getString();
5897 if (Mode == "unified" || Mode == "UNIFIED")
5899 else if (Mode == "divided" || Mode == "DIVIDED")
5900 return Error(L, "'.syntax divided' arm asssembly not supported");
5902 return Error(L, "unrecognized syntax mode in .syntax directive");
5904 if (getLexer().isNot(AsmToken::EndOfStatement))
5905 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
5908 // TODO tell the MC streamer the mode
5909 // getParser().getStreamer().Emit???();
5913 /// parseDirectiveCode
5914 /// ::= .code 16 | 32
5915 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
5916 const AsmToken &Tok = Parser.getTok();
5917 if (Tok.isNot(AsmToken::Integer))
5918 return Error(L, "unexpected token in .code directive");
5919 int64_t Val = Parser.getTok().getIntVal();
5925 return Error(L, "invalid operand to .code directive");
5927 if (getLexer().isNot(AsmToken::EndOfStatement))
5928 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
5934 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
5938 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
5944 extern "C" void LLVMInitializeARMAsmLexer();
5946 /// Force static initialization.
5947 extern "C" void LLVMInitializeARMAsmParser() {
5948 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
5949 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
5950 LLVMInitializeARMAsmLexer();
5953 #define GET_REGISTER_MATCHER
5954 #define GET_MATCHER_IMPLEMENTATION
5955 #include "ARMGenAsmMatcher.inc"