1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMAddressingModes.h"
12 #include "ARMSubtarget.h"
13 #include "llvm/MC/MCParser/MCAsmLexer.h"
14 #include "llvm/MC/MCParser/MCAsmParser.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/Target/TargetRegistry.h"
21 #include "llvm/Target/TargetAsmParser.h"
22 #include "llvm/Support/SourceMgr.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/ADT/StringSwitch.h"
26 #include "llvm/ADT/Twine.h"
29 // The shift types for register controlled shifts in arm memory addressing
42 class ARMAsmParser : public TargetAsmParser {
46 MCAsmParser &getParser() const { return Parser; }
47 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
49 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
50 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
52 int TryParseRegister();
53 ARMOperand *TryParseRegisterWithWriteBack();
54 ARMOperand *ParseRegisterList();
55 ARMOperand *ParseMemory();
56 ARMOperand *ParseOperand();
58 bool ParseMemoryOffsetReg(bool &Negative,
59 bool &OffsetRegShifted,
60 enum ShiftType &ShiftType,
61 const MCExpr *&ShiftAmount,
62 const MCExpr *&Offset,
66 bool ParseShift(enum ShiftType &St, const MCExpr *&ShiftAmount, SMLoc &E);
67 bool ParseDirectiveWord(unsigned Size, SMLoc L);
68 bool ParseDirectiveThumb(SMLoc L);
69 bool ParseDirectiveThumbFunc(SMLoc L);
70 bool ParseDirectiveCode(SMLoc L);
71 bool ParseDirectiveSyntax(SMLoc L);
73 bool MatchAndEmitInstruction(SMLoc IDLoc,
74 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
77 /// @name Auto-generated Match Functions
80 #define GET_ASSEMBLER_HEADER
81 #include "ARMGenAsmMatcher.inc"
86 ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
87 : TargetAsmParser(T), Parser(_Parser), TM(_TM) {
88 // Initialize the set of available features.
89 setAvailableFeatures(ComputeAvailableFeatures(
90 &TM.getSubtarget<ARMSubtarget>()));
93 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
94 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
95 virtual bool ParseDirective(AsmToken DirectiveID);
97 } // end anonymous namespace
101 /// ARMOperand - Instances of this class represent a parsed ARM machine
103 class ARMOperand : public MCParsedAsmOperand {
113 SMLoc StartLoc, EndLoc;
117 ARMCC::CondCodes Val;
139 // This is for all forms of ARM address expressions
142 unsigned OffsetRegNum; // used when OffsetIsReg is true
143 const MCExpr *Offset; // used when OffsetIsReg is false
144 const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
145 enum ShiftType ShiftType; // used when OffsetRegShifted is true
146 unsigned OffsetRegShifted : 1; // only used when OffsetIsReg is true
147 unsigned Preindexed : 1;
148 unsigned Postindexed : 1;
149 unsigned OffsetIsReg : 1;
150 unsigned Negative : 1; // only used when OffsetIsReg is true
151 unsigned Writeback : 1;
155 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
157 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
159 StartLoc = o.StartLoc;
183 /// getStartLoc - Get the location of the first token of this operand.
184 SMLoc getStartLoc() const { return StartLoc; }
185 /// getEndLoc - Get the location of the last token of this operand.
186 SMLoc getEndLoc() const { return EndLoc; }
188 ARMCC::CondCodes getCondCode() const {
189 assert(Kind == CondCode && "Invalid access!");
193 StringRef getToken() const {
194 assert(Kind == Token && "Invalid access!");
195 return StringRef(Tok.Data, Tok.Length);
198 unsigned getReg() const {
199 assert((Kind == Register || Kind == RegisterList) && "Invalid access!");
201 if (Kind == Register)
204 RegNum = RegList.RegStart;
208 std::pair<unsigned, unsigned> getRegList() const {
209 assert(Kind == RegisterList && "Invalid access!");
210 return std::make_pair(RegList.RegStart, RegList.Number);
213 const MCExpr *getImm() const {
214 assert(Kind == Immediate && "Invalid access!");
218 bool isCondCode() const { return Kind == CondCode; }
219 bool isImm() const { return Kind == Immediate; }
220 bool isReg() const { return Kind == Register; }
221 bool isRegList() const { return Kind == RegisterList; }
222 bool isToken() const { return Kind == Token; }
223 bool isMemory() const { return Kind == Memory; }
224 bool isMemMode5() const {
225 if (!isMemory() || Mem.OffsetIsReg || Mem.OffsetRegShifted ||
226 Mem.Writeback || Mem.Negative)
228 // If there is an offset expression, make sure it's valid.
231 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
234 // The offset must be a multiple of 4 in the range 0-1020.
235 int64_t Value = CE->getValue();
236 return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020);
239 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
240 // Add as immediates when possible. Null MCExpr = 0.
242 Inst.addOperand(MCOperand::CreateImm(0));
243 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
244 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
246 Inst.addOperand(MCOperand::CreateExpr(Expr));
249 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
250 assert(N == 2 && "Invalid number of operands!");
251 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
252 // FIXME: What belongs here?
253 Inst.addOperand(MCOperand::CreateReg(0));
256 void addRegOperands(MCInst &Inst, unsigned N) const {
257 assert(N == 1 && "Invalid number of operands!");
258 Inst.addOperand(MCOperand::CreateReg(getReg()));
261 void addRegListOperands(MCInst &Inst, unsigned N) const {
262 assert(N == 2 && "Invalid number of operands!");
263 std::pair<unsigned, unsigned> RegList = getRegList();
264 Inst.addOperand(MCOperand::CreateReg(RegList.first));
265 Inst.addOperand(MCOperand::CreateImm(RegList.second));
268 void addImmOperands(MCInst &Inst, unsigned N) const {
269 assert(N == 1 && "Invalid number of operands!");
270 addExpr(Inst, getImm());
273 void addMemMode5Operands(MCInst &Inst, unsigned N) const {
274 assert(N == 2 && isMemMode5() && "Invalid number of operands!");
276 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
277 assert(!Mem.OffsetIsReg && "Invalid mode 5 operand");
279 // FIXME: #-0 is encoded differently than #0. Does the parser preserve
282 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
283 assert(CE && "Non-constant mode 5 offset operand!");
285 // The MCInst offset operand doesn't include the low two bits (like
286 // the instruction encoding).
287 int64_t Offset = CE->getValue() / 4;
289 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add,
292 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub,
295 Inst.addOperand(MCOperand::CreateImm(0));
299 virtual void dump(raw_ostream &OS) const;
301 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
302 ARMOperand *Op = new ARMOperand(CondCode);
309 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
310 ARMOperand *Op = new ARMOperand(Token);
311 Op->Tok.Data = Str.data();
312 Op->Tok.Length = Str.size();
318 static ARMOperand *CreateReg(unsigned RegNum, bool Writeback, SMLoc S,
320 ARMOperand *Op = new ARMOperand(Register);
321 Op->Reg.RegNum = RegNum;
322 Op->Reg.Writeback = Writeback;
328 static ARMOperand *CreateRegList(unsigned RegStart, unsigned Number,
330 ARMOperand *Op = new ARMOperand(RegisterList);
331 Op->RegList.RegStart = RegStart;
332 Op->RegList.Number = Number;
338 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
339 ARMOperand *Op = new ARMOperand(Immediate);
346 static ARMOperand *CreateMem(unsigned BaseRegNum, bool OffsetIsReg,
347 const MCExpr *Offset, unsigned OffsetRegNum,
348 bool OffsetRegShifted, enum ShiftType ShiftType,
349 const MCExpr *ShiftAmount, bool Preindexed,
350 bool Postindexed, bool Negative, bool Writeback,
352 ARMOperand *Op = new ARMOperand(Memory);
353 Op->Mem.BaseRegNum = BaseRegNum;
354 Op->Mem.OffsetIsReg = OffsetIsReg;
355 Op->Mem.Offset = Offset;
356 Op->Mem.OffsetRegNum = OffsetRegNum;
357 Op->Mem.OffsetRegShifted = OffsetRegShifted;
358 Op->Mem.ShiftType = ShiftType;
359 Op->Mem.ShiftAmount = ShiftAmount;
360 Op->Mem.Preindexed = Preindexed;
361 Op->Mem.Postindexed = Postindexed;
362 Op->Mem.Negative = Negative;
363 Op->Mem.Writeback = Writeback;
371 } // end anonymous namespace.
373 void ARMOperand::dump(raw_ostream &OS) const {
376 OS << ARMCondCodeToString(getCondCode());
385 OS << "<register " << getReg() << ">";
388 OS << "<register_list ";
389 std::pair<unsigned, unsigned> List = getRegList();
390 unsigned RegEnd = List.first + List.second;
392 for (unsigned Idx = List.first; Idx < RegEnd; ) {
394 if (++Idx < RegEnd) OS << ", ";
401 OS << "'" << getToken() << "'";
406 /// @name Auto-generated Match Functions
409 static unsigned MatchRegisterName(StringRef Name);
413 /// Try to parse a register name. The token must be an Identifier when called,
414 /// and if it is a register name the token is eaten and the register number is
415 /// returned. Otherwise return -1.
417 int ARMAsmParser::TryParseRegister() {
418 const AsmToken &Tok = Parser.getTok();
419 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
421 // FIXME: Validate register for the current architecture; we have to do
422 // validation later, so maybe there is no need for this here.
423 unsigned RegNum = MatchRegisterName(Tok.getString());
426 Parser.Lex(); // Eat identifier token.
431 /// Try to parse a register name. The token must be an Identifier when called,
432 /// and if it is a register name the token is eaten and the register number is
433 /// returned. Otherwise return -1.
435 /// TODO this is likely to change to allow different register types and or to
436 /// parse for a specific register type.
437 ARMOperand *ARMAsmParser::TryParseRegisterWithWriteBack() {
438 SMLoc S = Parser.getTok().getLoc();
439 int RegNo = TryParseRegister();
443 SMLoc E = Parser.getTok().getLoc();
445 bool Writeback = false;
446 const AsmToken &ExclaimTok = Parser.getTok();
447 if (ExclaimTok.is(AsmToken::Exclaim)) {
448 E = ExclaimTok.getLoc();
450 Parser.Lex(); // Eat exclaim token
453 return ARMOperand::CreateReg(RegNo, Writeback, S, E);
456 /// Parse a register list, return it if successful else return null. The first
457 /// token must be a '{' when called.
458 ARMOperand *ARMAsmParser::ParseRegisterList() {
459 assert(Parser.getTok().is(AsmToken::LCurly) &&
460 "Token is not a Left Curly Brace");
461 SMLoc S = Parser.getTok().getLoc();
462 Parser.Lex(); // Eat left curly brace token.
464 const AsmToken &RegTok = Parser.getTok();
465 SMLoc RegLoc = RegTok.getLoc();
466 if (RegTok.isNot(AsmToken::Identifier)) {
467 Error(RegLoc, "register expected");
471 int RegNum = TryParseRegister();
473 Error(RegLoc, "register expected");
477 unsigned PrevRegNum = RegNum;
478 std::vector<std::pair<unsigned, SMLoc> > Registers;
479 Registers.reserve(32);
480 Registers.push_back(std::make_pair(RegNum, RegLoc));
482 while (Parser.getTok().is(AsmToken::Comma) ||
483 Parser.getTok().is(AsmToken::Minus)) {
484 bool IsRange = Parser.getTok().is(AsmToken::Minus);
485 Parser.Lex(); // Eat comma or minus token.
487 const AsmToken &RegTok = Parser.getTok();
488 SMLoc RegLoc = RegTok.getLoc();
489 if (RegTok.isNot(AsmToken::Identifier)) {
490 Error(RegLoc, "register expected");
494 int RegNum = TryParseRegister();
496 Error(RegLoc, "register expected");
501 int Reg = PrevRegNum;
504 Registers.push_back(std::make_pair(Reg, RegLoc));
505 } while (Reg != RegNum);
507 Registers.push_back(std::make_pair(RegNum, RegLoc));
513 // Process the right curly brace of the list.
514 const AsmToken &RCurlyTok = Parser.getTok();
515 if (RCurlyTok.isNot(AsmToken::RCurly)) {
516 Error(RCurlyTok.getLoc(), "'}' expected");
520 SMLoc E = RCurlyTok.getLoc();
521 Parser.Lex(); // Eat right curly brace token.
523 // Verify the register list.
524 std::vector<std::pair<unsigned, SMLoc> >::iterator
525 RI = Registers.begin(), RE = Registers.end();
527 unsigned Number = Registers.size();
528 unsigned HighRegNum = RI->first;
529 unsigned RegStart = RI->first;
531 DenseMap<unsigned, bool> RegMap;
532 RegMap[RI->first] = true;
534 for (++RI; RI != RE; ++RI) {
535 std::pair<unsigned, SMLoc> &RegInfo = *RI;
537 if (RegMap[RegInfo.first]) {
538 Error(RegInfo.second, "register duplicated in register list");
542 if (RegInfo.first < HighRegNum)
543 Warning(RegInfo.second,
544 "register not in ascending order in register list");
546 RegMap[RegInfo.first] = true;
547 HighRegNum = std::max(RegInfo.first, HighRegNum);
548 RegStart = std::min(RegInfo.first, RegStart);
551 if (RegStart + Number - 1 != HighRegNum) {
552 Error(RegLoc, "non-contiguous register range");
556 return ARMOperand::CreateRegList(RegStart, Number, S, E);
559 /// Parse an ARM memory expression, return false if successful else return true
560 /// or an error. The first token must be a '[' when called.
561 /// TODO Only preindexing and postindexing addressing are started, unindexed
562 /// with option, etc are still to do.
563 ARMOperand *ARMAsmParser::ParseMemory() {
565 assert(Parser.getTok().is(AsmToken::LBrac) &&
566 "Token is not a Left Bracket");
567 S = Parser.getTok().getLoc();
568 Parser.Lex(); // Eat left bracket token.
570 const AsmToken &BaseRegTok = Parser.getTok();
571 if (BaseRegTok.isNot(AsmToken::Identifier)) {
572 Error(BaseRegTok.getLoc(), "register expected");
575 int BaseRegNum = TryParseRegister();
576 if (BaseRegNum == -1) {
577 Error(BaseRegTok.getLoc(), "register expected");
581 bool Preindexed = false;
582 bool Postindexed = false;
583 bool OffsetIsReg = false;
584 bool Negative = false;
585 bool Writeback = false;
587 // First look for preindexed address forms, that is after the "[Rn" we now
588 // have to see if the next token is a comma.
589 const AsmToken &Tok = Parser.getTok();
590 if (Tok.is(AsmToken::Comma)) {
592 Parser.Lex(); // Eat comma token.
594 bool OffsetRegShifted;
595 enum ShiftType ShiftType;
596 const MCExpr *ShiftAmount;
597 const MCExpr *Offset;
598 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
599 Offset, OffsetIsReg, OffsetRegNum, E))
601 const AsmToken &RBracTok = Parser.getTok();
602 if (RBracTok.isNot(AsmToken::RBrac)) {
603 Error(RBracTok.getLoc(), "']' expected");
606 E = RBracTok.getLoc();
607 Parser.Lex(); // Eat right bracket token.
609 const AsmToken &ExclaimTok = Parser.getTok();
610 if (ExclaimTok.is(AsmToken::Exclaim)) {
611 E = ExclaimTok.getLoc();
613 Parser.Lex(); // Eat exclaim token
615 return ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
616 OffsetRegShifted, ShiftType, ShiftAmount,
617 Preindexed, Postindexed, Negative, Writeback,
620 // The "[Rn" we have so far was not followed by a comma.
621 else if (Tok.is(AsmToken::RBrac)) {
622 // If there's anything other than the right brace, this is a post indexing
625 Parser.Lex(); // Eat right bracket token.
627 int OffsetRegNum = 0;
628 bool OffsetRegShifted = false;
629 enum ShiftType ShiftType;
630 const MCExpr *ShiftAmount;
631 const MCExpr *Offset = 0;
633 const AsmToken &NextTok = Parser.getTok();
634 if (NextTok.isNot(AsmToken::EndOfStatement)) {
637 if (NextTok.isNot(AsmToken::Comma)) {
638 Error(NextTok.getLoc(), "',' expected");
641 Parser.Lex(); // Eat comma token.
642 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
643 ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
648 return ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
649 OffsetRegShifted, ShiftType, ShiftAmount,
650 Preindexed, Postindexed, Negative, Writeback,
657 /// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
658 /// we will parse the following (were +/- means that a plus or minus is
663 /// we return false on success or an error otherwise.
664 bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
665 bool &OffsetRegShifted,
666 enum ShiftType &ShiftType,
667 const MCExpr *&ShiftAmount,
668 const MCExpr *&Offset,
673 OffsetRegShifted = false;
676 const AsmToken &NextTok = Parser.getTok();
677 E = NextTok.getLoc();
678 if (NextTok.is(AsmToken::Plus))
679 Parser.Lex(); // Eat plus token.
680 else if (NextTok.is(AsmToken::Minus)) {
682 Parser.Lex(); // Eat minus token
684 // See if there is a register following the "[Rn," or "[Rn]," we have so far.
685 const AsmToken &OffsetRegTok = Parser.getTok();
686 if (OffsetRegTok.is(AsmToken::Identifier)) {
687 SMLoc CurLoc = OffsetRegTok.getLoc();
688 OffsetRegNum = TryParseRegister();
689 if (OffsetRegNum != -1) {
695 // If we parsed a register as the offset then there can be a shift after that.
696 if (OffsetRegNum != -1) {
697 // Look for a comma then a shift
698 const AsmToken &Tok = Parser.getTok();
699 if (Tok.is(AsmToken::Comma)) {
700 Parser.Lex(); // Eat comma token.
702 const AsmToken &Tok = Parser.getTok();
703 if (ParseShift(ShiftType, ShiftAmount, E))
704 return Error(Tok.getLoc(), "shift expected");
705 OffsetRegShifted = true;
708 else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
709 // Look for #offset following the "[Rn," or "[Rn],"
710 const AsmToken &HashTok = Parser.getTok();
711 if (HashTok.isNot(AsmToken::Hash))
712 return Error(HashTok.getLoc(), "'#' expected");
714 Parser.Lex(); // Eat hash token.
716 if (getParser().ParseExpression(Offset))
718 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
723 /// ParseShift as one of these two:
724 /// ( lsl | lsr | asr | ror ) , # shift_amount
726 /// and returns true if it parses a shift otherwise it returns false.
727 bool ARMAsmParser::ParseShift(ShiftType &St, const MCExpr *&ShiftAmount,
729 const AsmToken &Tok = Parser.getTok();
730 if (Tok.isNot(AsmToken::Identifier))
732 StringRef ShiftName = Tok.getString();
733 if (ShiftName == "lsl" || ShiftName == "LSL")
735 else if (ShiftName == "lsr" || ShiftName == "LSR")
737 else if (ShiftName == "asr" || ShiftName == "ASR")
739 else if (ShiftName == "ror" || ShiftName == "ROR")
741 else if (ShiftName == "rrx" || ShiftName == "RRX")
745 Parser.Lex(); // Eat shift type token.
751 // Otherwise, there must be a '#' and a shift amount.
752 const AsmToken &HashTok = Parser.getTok();
753 if (HashTok.isNot(AsmToken::Hash))
754 return Error(HashTok.getLoc(), "'#' expected");
755 Parser.Lex(); // Eat hash token.
757 if (getParser().ParseExpression(ShiftAmount))
763 /// Parse a arm instruction operand. For now this parses the operand regardless
765 ARMOperand *ARMAsmParser::ParseOperand() {
767 switch (getLexer().getKind()) {
769 Error(Parser.getTok().getLoc(), "unexpected token in operand");
771 case AsmToken::Identifier:
772 if (ARMOperand *Op = TryParseRegisterWithWriteBack())
775 // This was not a register so parse other operands that start with an
776 // identifier (like labels) as expressions and create them as immediates.
778 S = Parser.getTok().getLoc();
779 if (getParser().ParseExpression(IdVal))
781 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
782 return ARMOperand::CreateImm(IdVal, S, E);
783 case AsmToken::LBrac:
784 return ParseMemory();
785 case AsmToken::LCurly:
786 return ParseRegisterList();
789 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
790 S = Parser.getTok().getLoc();
792 const MCExpr *ImmVal;
793 if (getParser().ParseExpression(ImmVal))
795 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
796 return ARMOperand::CreateImm(ImmVal, S, E);
800 /// Parse an arm instruction mnemonic followed by its operands.
801 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
802 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
803 // Create the leading tokens for the mnemonic, split by '.' characters.
804 size_t Start = 0, Next = Name.find('.');
805 StringRef Head = Name.slice(Start, Next);
807 // Determine the predicate, if any.
809 // FIXME: We need a way to check whether a prefix supports predication,
810 // otherwise we will end up with an ambiguity for instructions that happen to
811 // end with a predicate name.
812 // FIXME: Likewise, some arithmetic instructions have an 's' prefix which
813 // indicates to update the condition codes. Those instructions have an
814 // additional immediate operand which encodes the prefix as reg0 or CPSR.
815 // Just checking for a suffix of 's' definitely creates ambiguities; e.g,
816 // the SMMLS instruction.
817 unsigned CC = StringSwitch<unsigned>(Head.substr(Head.size()-2))
818 .Case("eq", ARMCC::EQ)
819 .Case("ne", ARMCC::NE)
820 .Case("hs", ARMCC::HS)
821 .Case("lo", ARMCC::LO)
822 .Case("mi", ARMCC::MI)
823 .Case("pl", ARMCC::PL)
824 .Case("vs", ARMCC::VS)
825 .Case("vc", ARMCC::VC)
826 .Case("hi", ARMCC::HI)
827 .Case("ls", ARMCC::LS)
828 .Case("ge", ARMCC::GE)
829 .Case("lt", ARMCC::LT)
830 .Case("gt", ARMCC::GT)
831 .Case("le", ARMCC::LE)
832 .Case("al", ARMCC::AL)
836 (CC == ARMCC::LS && (Head == "vmls" || Head == "vnmls"))) {
839 Head = Head.slice(0, Head.size() - 2);
842 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
843 // FIXME: Should only add this operand for predicated instructions
844 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), NameLoc));
846 // Add the remaining tokens in the mnemonic.
847 while (Next != StringRef::npos) {
849 Next = Name.find('.', Start + 1);
850 Head = Name.slice(Start, Next);
852 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
855 // Read the remaining operands.
856 if (getLexer().isNot(AsmToken::EndOfStatement)) {
857 // Read the first operand.
858 if (ARMOperand *Op = ParseOperand())
859 Operands.push_back(Op);
861 Parser.EatToEndOfStatement();
865 while (getLexer().is(AsmToken::Comma)) {
866 Parser.Lex(); // Eat the comma.
868 // Parse and remember the operand.
869 if (ARMOperand *Op = ParseOperand())
870 Operands.push_back(Op);
872 Parser.EatToEndOfStatement();
878 if (getLexer().isNot(AsmToken::EndOfStatement)) {
879 Parser.EatToEndOfStatement();
880 return TokError("unexpected token in argument list");
883 Parser.Lex(); // Consume the EndOfStatement
888 MatchAndEmitInstruction(SMLoc IDLoc,
889 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
893 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo)) {
895 Out.EmitInstruction(Inst);
897 case Match_MissingFeature:
898 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
900 case Match_InvalidOperand: {
901 SMLoc ErrorLoc = IDLoc;
902 if (ErrorInfo != ~0U) {
903 if (ErrorInfo >= Operands.size())
904 return Error(IDLoc, "too few operands for instruction");
906 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
907 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
910 return Error(ErrorLoc, "invalid operand for instruction");
912 case Match_MnemonicFail:
913 return Error(IDLoc, "unrecognized instruction mnemonic");
916 llvm_unreachable("Implement any new match types added!");
920 /// ParseDirective parses the arm specific directives
921 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
922 StringRef IDVal = DirectiveID.getIdentifier();
923 if (IDVal == ".word")
924 return ParseDirectiveWord(4, DirectiveID.getLoc());
925 else if (IDVal == ".thumb")
926 return ParseDirectiveThumb(DirectiveID.getLoc());
927 else if (IDVal == ".thumb_func")
928 return ParseDirectiveThumbFunc(DirectiveID.getLoc());
929 else if (IDVal == ".code")
930 return ParseDirectiveCode(DirectiveID.getLoc());
931 else if (IDVal == ".syntax")
932 return ParseDirectiveSyntax(DirectiveID.getLoc());
936 /// ParseDirectiveWord
937 /// ::= .word [ expression (, expression)* ]
938 bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
939 if (getLexer().isNot(AsmToken::EndOfStatement)) {
942 if (getParser().ParseExpression(Value))
945 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
947 if (getLexer().is(AsmToken::EndOfStatement))
950 // FIXME: Improve diagnostic.
951 if (getLexer().isNot(AsmToken::Comma))
952 return Error(L, "unexpected token in directive");
961 /// ParseDirectiveThumb
963 bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
964 if (getLexer().isNot(AsmToken::EndOfStatement))
965 return Error(L, "unexpected token in directive");
968 // TODO: set thumb mode
969 // TODO: tell the MC streamer the mode
970 // getParser().getStreamer().Emit???();
974 /// ParseDirectiveThumbFunc
975 /// ::= .thumbfunc symbol_name
976 bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
977 const AsmToken &Tok = Parser.getTok();
978 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
979 return Error(L, "unexpected token in .thumb_func directive");
980 StringRef Name = Tok.getString();
981 Parser.Lex(); // Consume the identifier token.
982 if (getLexer().isNot(AsmToken::EndOfStatement))
983 return Error(L, "unexpected token in directive");
986 // Mark symbol as a thumb symbol.
987 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
988 getParser().getStreamer().EmitThumbFunc(Func);
992 /// ParseDirectiveSyntax
993 /// ::= .syntax unified | divided
994 bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
995 const AsmToken &Tok = Parser.getTok();
996 if (Tok.isNot(AsmToken::Identifier))
997 return Error(L, "unexpected token in .syntax directive");
998 StringRef Mode = Tok.getString();
999 if (Mode == "unified" || Mode == "UNIFIED")
1001 else if (Mode == "divided" || Mode == "DIVIDED")
1004 return Error(L, "unrecognized syntax mode in .syntax directive");
1006 if (getLexer().isNot(AsmToken::EndOfStatement))
1007 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
1010 // TODO tell the MC streamer the mode
1011 // getParser().getStreamer().Emit???();
1015 /// ParseDirectiveCode
1016 /// ::= .code 16 | 32
1017 bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
1018 const AsmToken &Tok = Parser.getTok();
1019 if (Tok.isNot(AsmToken::Integer))
1020 return Error(L, "unexpected token in .code directive");
1021 int64_t Val = Parser.getTok().getIntVal();
1027 return Error(L, "invalid operand to .code directive");
1029 if (getLexer().isNot(AsmToken::EndOfStatement))
1030 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
1034 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
1036 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
1041 extern "C" void LLVMInitializeARMAsmLexer();
1043 /// Force static initialization.
1044 extern "C" void LLVMInitializeARMAsmParser() {
1045 RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
1046 RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
1047 LLVMInitializeARMAsmLexer();
1050 #define GET_REGISTER_MATCHER
1051 #define GET_MATCHER_IMPLEMENTATION
1052 #include "ARMGenAsmMatcher.inc"