1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMBaseInfo.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMMCExpr.h"
13 #include "llvm/MC/MCParser/MCAsmLexer.h"
14 #include "llvm/MC/MCParser/MCAsmParser.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCAsmInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/MC/MCTargetAsmParser.h"
24 #include "llvm/Target/TargetRegistry.h"
25 #include "llvm/Support/SourceMgr.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include "llvm/ADT/OwningPtr.h"
28 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/ADT/StringExtras.h"
31 #include "llvm/ADT/StringSwitch.h"
32 #include "llvm/ADT/Twine.h"
40 class ARMAsmParser : public MCTargetAsmParser {
44 MCAsmParser &getParser() const { return Parser; }
45 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
47 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
48 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
50 int tryParseRegister();
51 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
52 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
53 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
54 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
55 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
56 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
57 const MCExpr *applyPrefixToExpr(const MCExpr *E,
58 MCSymbolRefExpr::VariantKind Variant);
61 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
62 unsigned &ShiftAmount);
63 bool parseDirectiveWord(unsigned Size, SMLoc L);
64 bool parseDirectiveThumb(SMLoc L);
65 bool parseDirectiveThumbFunc(SMLoc L);
66 bool parseDirectiveCode(SMLoc L);
67 bool parseDirectiveSyntax(SMLoc L);
69 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
70 bool &CarrySetting, unsigned &ProcessorIMod);
71 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
72 bool &CanAcceptPredicationCode);
74 bool isThumb() const {
75 // FIXME: Can tablegen auto-generate this?
76 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
78 bool isThumbOne() const {
79 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
81 bool isThumbTwo() const {
82 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
84 bool hasV6Ops() const {
85 return STI.getFeatureBits() & ARM::HasV6Ops;
88 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
89 setAvailableFeatures(FB);
92 /// @name Auto-generated Match Functions
95 #define GET_ASSEMBLER_HEADER
96 #include "ARMGenAsmMatcher.inc"
100 OperandMatchResultTy parseCoprocNumOperand(
101 SmallVectorImpl<MCParsedAsmOperand*>&);
102 OperandMatchResultTy parseCoprocRegOperand(
103 SmallVectorImpl<MCParsedAsmOperand*>&);
104 OperandMatchResultTy parseMemBarrierOptOperand(
105 SmallVectorImpl<MCParsedAsmOperand*>&);
106 OperandMatchResultTy parseProcIFlagsOperand(
107 SmallVectorImpl<MCParsedAsmOperand*>&);
108 OperandMatchResultTy parseMSRMaskOperand(
109 SmallVectorImpl<MCParsedAsmOperand*>&);
110 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
111 StringRef Op, int Low, int High);
112 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
113 return parsePKHImm(O, "lsl", 0, 31);
115 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
116 return parsePKHImm(O, "asr", 1, 32);
118 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
119 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
120 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
121 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
122 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
123 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
125 // Asm Match Converter Methods
126 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
127 const SmallVectorImpl<MCParsedAsmOperand*> &);
128 bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
129 const SmallVectorImpl<MCParsedAsmOperand*> &);
130 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
131 const SmallVectorImpl<MCParsedAsmOperand*> &);
132 bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
133 const SmallVectorImpl<MCParsedAsmOperand*> &);
134 bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
135 const SmallVectorImpl<MCParsedAsmOperand*> &);
136 bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
137 const SmallVectorImpl<MCParsedAsmOperand*> &);
138 bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
139 const SmallVectorImpl<MCParsedAsmOperand*> &);
140 bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
141 const SmallVectorImpl<MCParsedAsmOperand*> &);
142 bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
143 const SmallVectorImpl<MCParsedAsmOperand*> &);
144 bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
145 const SmallVectorImpl<MCParsedAsmOperand*> &);
146 bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
147 const SmallVectorImpl<MCParsedAsmOperand*> &);
149 bool validateInstruction(MCInst &Inst,
150 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
151 void processInstruction(MCInst &Inst,
152 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
153 bool shouldOmitCCOutOperand(StringRef Mnemonic,
154 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
157 enum ARMMatchResultTy {
158 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
163 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
164 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
165 MCAsmParserExtension::Initialize(_Parser);
167 // Initialize the set of available features.
168 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
171 // Implementation of the MCTargetAsmParser interface:
172 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
173 bool ParseInstruction(StringRef Name, SMLoc NameLoc,
174 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
175 bool ParseDirective(AsmToken DirectiveID);
177 unsigned checkTargetMatchPredicate(MCInst &Inst);
179 bool MatchAndEmitInstruction(SMLoc IDLoc,
180 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
183 } // end anonymous namespace
187 /// ARMOperand - Instances of this class represent a parsed ARM machine
189 class ARMOperand : public MCParsedAsmOperand {
213 SMLoc StartLoc, EndLoc;
214 SmallVector<unsigned, 8> Registers;
218 ARMCC::CondCodes Val;
230 ARM_PROC::IFlags Val;
250 /// Combined record for all forms of ARM address expressions.
253 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
255 const MCConstantExpr *OffsetImm; // Offset immediate value
256 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
257 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
258 unsigned ShiftImm; // shift for OffsetReg.
259 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
265 ARM_AM::ShiftOpc ShiftTy;
274 ARM_AM::ShiftOpc ShiftTy;
280 ARM_AM::ShiftOpc ShiftTy;
293 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
295 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
297 StartLoc = o.StartLoc;
311 case DPRRegisterList:
312 case SPRRegisterList:
313 Registers = o.Registers;
328 case PostIndexRegister:
329 PostIdxReg = o.PostIdxReg;
337 case ShifterImmediate:
338 ShifterImm = o.ShifterImm;
340 case ShiftedRegister:
341 RegShiftedReg = o.RegShiftedReg;
343 case ShiftedImmediate:
344 RegShiftedImm = o.RegShiftedImm;
346 case RotateImmediate:
349 case BitfieldDescriptor:
350 Bitfield = o.Bitfield;
355 /// getStartLoc - Get the location of the first token of this operand.
356 SMLoc getStartLoc() const { return StartLoc; }
357 /// getEndLoc - Get the location of the last token of this operand.
358 SMLoc getEndLoc() const { return EndLoc; }
360 ARMCC::CondCodes getCondCode() const {
361 assert(Kind == CondCode && "Invalid access!");
365 unsigned getCoproc() const {
366 assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
370 StringRef getToken() const {
371 assert(Kind == Token && "Invalid access!");
372 return StringRef(Tok.Data, Tok.Length);
375 unsigned getReg() const {
376 assert((Kind == Register || Kind == CCOut) && "Invalid access!");
380 const SmallVectorImpl<unsigned> &getRegList() const {
381 assert((Kind == RegisterList || Kind == DPRRegisterList ||
382 Kind == SPRRegisterList) && "Invalid access!");
386 const MCExpr *getImm() const {
387 assert(Kind == Immediate && "Invalid access!");
391 ARM_MB::MemBOpt getMemBarrierOpt() const {
392 assert(Kind == MemBarrierOpt && "Invalid access!");
396 ARM_PROC::IFlags getProcIFlags() const {
397 assert(Kind == ProcIFlags && "Invalid access!");
401 unsigned getMSRMask() const {
402 assert(Kind == MSRMask && "Invalid access!");
406 bool isCoprocNum() const { return Kind == CoprocNum; }
407 bool isCoprocReg() const { return Kind == CoprocReg; }
408 bool isCondCode() const { return Kind == CondCode; }
409 bool isCCOut() const { return Kind == CCOut; }
410 bool isImm() const { return Kind == Immediate; }
411 bool isImm0_255() const {
412 if (Kind != Immediate)
414 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
415 if (!CE) return false;
416 int64_t Value = CE->getValue();
417 return Value >= 0 && Value < 256;
419 bool isImm0_7() const {
420 if (Kind != Immediate)
422 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
423 if (!CE) return false;
424 int64_t Value = CE->getValue();
425 return Value >= 0 && Value < 8;
427 bool isImm0_15() const {
428 if (Kind != Immediate)
430 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
431 if (!CE) return false;
432 int64_t Value = CE->getValue();
433 return Value >= 0 && Value < 16;
435 bool isImm0_31() const {
436 if (Kind != Immediate)
438 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
439 if (!CE) return false;
440 int64_t Value = CE->getValue();
441 return Value >= 0 && Value < 32;
443 bool isImm1_16() const {
444 if (Kind != Immediate)
446 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
447 if (!CE) return false;
448 int64_t Value = CE->getValue();
449 return Value > 0 && Value < 17;
451 bool isImm1_32() const {
452 if (Kind != Immediate)
454 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
455 if (!CE) return false;
456 int64_t Value = CE->getValue();
457 return Value > 0 && Value < 33;
459 bool isImm0_65535() const {
460 if (Kind != Immediate)
462 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
463 if (!CE) return false;
464 int64_t Value = CE->getValue();
465 return Value >= 0 && Value < 65536;
467 bool isImm0_65535Expr() const {
468 if (Kind != Immediate)
470 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
471 // If it's not a constant expression, it'll generate a fixup and be
473 if (!CE) return true;
474 int64_t Value = CE->getValue();
475 return Value >= 0 && Value < 65536;
477 bool isImm24bit() const {
478 if (Kind != Immediate)
480 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
481 if (!CE) return false;
482 int64_t Value = CE->getValue();
483 return Value >= 0 && Value <= 0xffffff;
485 bool isPKHLSLImm() const {
486 if (Kind != Immediate)
488 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
489 if (!CE) return false;
490 int64_t Value = CE->getValue();
491 return Value >= 0 && Value < 32;
493 bool isPKHASRImm() const {
494 if (Kind != Immediate)
496 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
497 if (!CE) return false;
498 int64_t Value = CE->getValue();
499 return Value > 0 && Value <= 32;
501 bool isARMSOImm() const {
502 if (Kind != Immediate)
504 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
505 if (!CE) return false;
506 int64_t Value = CE->getValue();
507 return ARM_AM::getSOImmVal(Value) != -1;
509 bool isT2SOImm() const {
510 if (Kind != Immediate)
512 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
513 if (!CE) return false;
514 int64_t Value = CE->getValue();
515 return ARM_AM::getT2SOImmVal(Value) != -1;
517 bool isSetEndImm() const {
518 if (Kind != Immediate)
520 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
521 if (!CE) return false;
522 int64_t Value = CE->getValue();
523 return Value == 1 || Value == 0;
525 bool isReg() const { return Kind == Register; }
526 bool isRegList() const { return Kind == RegisterList; }
527 bool isDPRRegList() const { return Kind == DPRRegisterList; }
528 bool isSPRRegList() const { return Kind == SPRRegisterList; }
529 bool isToken() const { return Kind == Token; }
530 bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
531 bool isMemory() const { return Kind == Memory; }
532 bool isShifterImm() const { return Kind == ShifterImmediate; }
533 bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
534 bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
535 bool isRotImm() const { return Kind == RotateImmediate; }
536 bool isBitfield() const { return Kind == BitfieldDescriptor; }
537 bool isPostIdxRegShifted() const { return Kind == PostIndexRegister; }
538 bool isPostIdxReg() const {
539 return Kind == PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
541 bool isMemNoOffset() const {
544 // No offset of any kind.
545 return Mem.OffsetRegNum == 0 && Mem.OffsetImm == 0;
547 bool isAddrMode2() const {
550 // Check for register offset.
551 if (Mem.OffsetRegNum) return true;
552 // Immediate offset in range [-4095, 4095].
553 if (!Mem.OffsetImm) return true;
554 int64_t Val = Mem.OffsetImm->getValue();
555 return Val > -4096 && Val < 4096;
557 bool isAM2OffsetImm() const {
558 if (Kind != Immediate)
560 // Immediate offset in range [-4095, 4095].
561 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
562 if (!CE) return false;
563 int64_t Val = CE->getValue();
564 return Val > -4096 && Val < 4096;
566 bool isAddrMode3() const {
569 // No shifts are legal for AM3.
570 if (Mem.ShiftType != ARM_AM::no_shift) return false;
571 // Check for register offset.
572 if (Mem.OffsetRegNum) return true;
573 // Immediate offset in range [-255, 255].
574 if (!Mem.OffsetImm) return true;
575 int64_t Val = Mem.OffsetImm->getValue();
576 return Val > -256 && Val < 256;
578 bool isAM3Offset() const {
579 if (Kind != Immediate && Kind != PostIndexRegister)
581 if (Kind == PostIndexRegister)
582 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
583 // Immediate offset in range [-255, 255].
584 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
585 if (!CE) return false;
586 int64_t Val = CE->getValue();
587 // Special case, #-0 is INT32_MIN.
588 return (Val > -256 && Val < 256) || Val == INT32_MIN;
590 bool isAddrMode5() const {
593 // Check for register offset.
594 if (Mem.OffsetRegNum) return false;
595 // Immediate offset in range [-1020, 1020] and a multiple of 4.
596 if (!Mem.OffsetImm) return true;
597 int64_t Val = Mem.OffsetImm->getValue();
598 return Val >= -1020 && Val <= 1020 && ((Val & 3) == 0);
600 bool isMemRegOffset() const {
601 if (Kind != Memory || !Mem.OffsetRegNum)
605 bool isMemThumbRR() const {
606 // Thumb reg+reg addressing is simple. Just two registers, a base and
607 // an offset. No shifts, negations or any other complicating factors.
608 if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative ||
609 Mem.ShiftType != ARM_AM::no_shift)
613 bool isMemImm8Offset() const {
614 if (Kind != Memory || Mem.OffsetRegNum != 0)
616 // Immediate offset in range [-255, 255].
617 if (!Mem.OffsetImm) return true;
618 int64_t Val = Mem.OffsetImm->getValue();
619 return Val > -256 && Val < 256;
621 bool isMemImm12Offset() const {
622 // If we have an immediate that's not a constant, treat it as a label
623 // reference needing a fixup. If it is a constant, it's something else
625 if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
628 if (Kind != Memory || Mem.OffsetRegNum != 0)
630 // Immediate offset in range [-4095, 4095].
631 if (!Mem.OffsetImm) return true;
632 int64_t Val = Mem.OffsetImm->getValue();
633 return Val > -4096 && Val < 4096;
635 bool isPostIdxImm8() const {
636 if (Kind != Immediate)
638 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
639 if (!CE) return false;
640 int64_t Val = CE->getValue();
641 return Val > -256 && Val < 256;
644 bool isMSRMask() const { return Kind == MSRMask; }
645 bool isProcIFlags() const { return Kind == ProcIFlags; }
647 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
648 // Add as immediates when possible. Null MCExpr = 0.
650 Inst.addOperand(MCOperand::CreateImm(0));
651 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
652 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
654 Inst.addOperand(MCOperand::CreateExpr(Expr));
657 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
658 assert(N == 2 && "Invalid number of operands!");
659 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
660 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
661 Inst.addOperand(MCOperand::CreateReg(RegNum));
664 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
665 assert(N == 1 && "Invalid number of operands!");
666 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
669 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
670 assert(N == 1 && "Invalid number of operands!");
671 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
674 void addCCOutOperands(MCInst &Inst, unsigned N) const {
675 assert(N == 1 && "Invalid number of operands!");
676 Inst.addOperand(MCOperand::CreateReg(getReg()));
679 void addRegOperands(MCInst &Inst, unsigned N) const {
680 assert(N == 1 && "Invalid number of operands!");
681 Inst.addOperand(MCOperand::CreateReg(getReg()));
684 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
685 assert(N == 3 && "Invalid number of operands!");
686 assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
687 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
688 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
689 Inst.addOperand(MCOperand::CreateImm(
690 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
693 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
694 assert(N == 2 && "Invalid number of operands!");
695 assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
696 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
697 Inst.addOperand(MCOperand::CreateImm(
698 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
702 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
703 assert(N == 1 && "Invalid number of operands!");
704 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
708 void addRegListOperands(MCInst &Inst, unsigned N) const {
709 assert(N == 1 && "Invalid number of operands!");
710 const SmallVectorImpl<unsigned> &RegList = getRegList();
711 for (SmallVectorImpl<unsigned>::const_iterator
712 I = RegList.begin(), E = RegList.end(); I != E; ++I)
713 Inst.addOperand(MCOperand::CreateReg(*I));
716 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
717 addRegListOperands(Inst, N);
720 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
721 addRegListOperands(Inst, N);
724 void addRotImmOperands(MCInst &Inst, unsigned N) const {
725 assert(N == 1 && "Invalid number of operands!");
726 // Encoded as val>>3. The printer handles display as 8, 16, 24.
727 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
730 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
731 assert(N == 1 && "Invalid number of operands!");
732 // Munge the lsb/width into a bitfield mask.
733 unsigned lsb = Bitfield.LSB;
734 unsigned width = Bitfield.Width;
735 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
736 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
737 (32 - (lsb + width)));
738 Inst.addOperand(MCOperand::CreateImm(Mask));
741 void addImmOperands(MCInst &Inst, unsigned N) const {
742 assert(N == 1 && "Invalid number of operands!");
743 addExpr(Inst, getImm());
746 void addImm0_255Operands(MCInst &Inst, unsigned N) const {
747 assert(N == 1 && "Invalid number of operands!");
748 addExpr(Inst, getImm());
751 void addImm0_7Operands(MCInst &Inst, unsigned N) const {
752 assert(N == 1 && "Invalid number of operands!");
753 addExpr(Inst, getImm());
756 void addImm0_15Operands(MCInst &Inst, unsigned N) const {
757 assert(N == 1 && "Invalid number of operands!");
758 addExpr(Inst, getImm());
761 void addImm0_31Operands(MCInst &Inst, unsigned N) const {
762 assert(N == 1 && "Invalid number of operands!");
763 addExpr(Inst, getImm());
766 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
767 assert(N == 1 && "Invalid number of operands!");
768 // The constant encodes as the immediate-1, and we store in the instruction
769 // the bits as encoded, so subtract off one here.
770 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
771 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
774 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
775 assert(N == 1 && "Invalid number of operands!");
776 // The constant encodes as the immediate-1, and we store in the instruction
777 // the bits as encoded, so subtract off one here.
778 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
779 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
782 void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
783 assert(N == 1 && "Invalid number of operands!");
784 addExpr(Inst, getImm());
787 void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
788 assert(N == 1 && "Invalid number of operands!");
789 addExpr(Inst, getImm());
792 void addImm24bitOperands(MCInst &Inst, unsigned N) const {
793 assert(N == 1 && "Invalid number of operands!");
794 addExpr(Inst, getImm());
797 void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
798 assert(N == 1 && "Invalid number of operands!");
799 addExpr(Inst, getImm());
802 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
803 assert(N == 1 && "Invalid number of operands!");
804 // An ASR value of 32 encodes as 0, so that's how we want to add it to
805 // the instruction as well.
806 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
807 int Val = CE->getValue();
808 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
811 void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
812 assert(N == 1 && "Invalid number of operands!");
813 addExpr(Inst, getImm());
816 void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
817 assert(N == 1 && "Invalid number of operands!");
818 addExpr(Inst, getImm());
821 void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
822 assert(N == 1 && "Invalid number of operands!");
823 addExpr(Inst, getImm());
826 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
827 assert(N == 1 && "Invalid number of operands!");
828 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
831 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
832 assert(N == 1 && "Invalid number of operands!");
833 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
836 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
837 assert(N == 3 && "Invalid number of operands!");
838 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
839 if (!Mem.OffsetRegNum) {
840 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
841 // Special case for #-0
842 if (Val == INT32_MIN) Val = 0;
843 if (Val < 0) Val = -Val;
844 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
846 // For register offset, we encode the shift type and negation flag
848 Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
849 Mem.ShiftImm, Mem.ShiftType);
851 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
852 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
853 Inst.addOperand(MCOperand::CreateImm(Val));
856 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
857 assert(N == 2 && "Invalid number of operands!");
858 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
859 assert(CE && "non-constant AM2OffsetImm operand!");
860 int32_t Val = CE->getValue();
861 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
862 // Special case for #-0
863 if (Val == INT32_MIN) Val = 0;
864 if (Val < 0) Val = -Val;
865 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
866 Inst.addOperand(MCOperand::CreateReg(0));
867 Inst.addOperand(MCOperand::CreateImm(Val));
870 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
871 assert(N == 3 && "Invalid number of operands!");
872 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
873 if (!Mem.OffsetRegNum) {
874 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
875 // Special case for #-0
876 if (Val == INT32_MIN) Val = 0;
877 if (Val < 0) Val = -Val;
878 Val = ARM_AM::getAM3Opc(AddSub, Val);
880 // For register offset, we encode the shift type and negation flag
882 Val = ARM_AM::getAM3Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
884 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
885 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
886 Inst.addOperand(MCOperand::CreateImm(Val));
889 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
890 assert(N == 2 && "Invalid number of operands!");
891 if (Kind == PostIndexRegister) {
893 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
894 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
895 Inst.addOperand(MCOperand::CreateImm(Val));
900 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
901 int32_t Val = CE->getValue();
902 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
903 // Special case for #-0
904 if (Val == INT32_MIN) Val = 0;
905 if (Val < 0) Val = -Val;
906 Val = ARM_AM::getAM3Opc(AddSub, Val);
907 Inst.addOperand(MCOperand::CreateReg(0));
908 Inst.addOperand(MCOperand::CreateImm(Val));
911 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
912 assert(N == 2 && "Invalid number of operands!");
913 // The lower two bits are always zero and as such are not encoded.
914 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0;
915 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
916 // Special case for #-0
917 if (Val == INT32_MIN) Val = 0;
918 if (Val < 0) Val = -Val;
919 Val = ARM_AM::getAM5Opc(AddSub, Val);
920 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
921 Inst.addOperand(MCOperand::CreateImm(Val));
924 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
925 assert(N == 2 && "Invalid number of operands!");
926 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
927 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
928 Inst.addOperand(MCOperand::CreateImm(Val));
931 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
932 assert(N == 2 && "Invalid number of operands!");
933 // If this is an immediate, it's a label reference.
934 if (Kind == Immediate) {
935 addExpr(Inst, getImm());
936 Inst.addOperand(MCOperand::CreateImm(0));
940 // Otherwise, it's a normal memory reg+offset.
941 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
942 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
943 Inst.addOperand(MCOperand::CreateImm(Val));
946 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
947 assert(N == 3 && "Invalid number of operands!");
948 unsigned Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
949 Mem.ShiftImm, Mem.ShiftType);
950 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
951 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
952 Inst.addOperand(MCOperand::CreateImm(Val));
955 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
956 assert(N == 2 && "Invalid number of operands!");
957 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
958 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
961 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
962 assert(N == 1 && "Invalid number of operands!");
963 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
964 assert(CE && "non-constant post-idx-imm8 operand!");
965 int Imm = CE->getValue();
966 bool isAdd = Imm >= 0;
967 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
968 Inst.addOperand(MCOperand::CreateImm(Imm));
971 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
972 assert(N == 2 && "Invalid number of operands!");
973 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
974 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
977 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
978 assert(N == 2 && "Invalid number of operands!");
979 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
980 // The sign, shift type, and shift amount are encoded in a single operand
981 // using the AM2 encoding helpers.
982 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
983 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
985 Inst.addOperand(MCOperand::CreateImm(Imm));
988 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
989 assert(N == 1 && "Invalid number of operands!");
990 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
993 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
994 assert(N == 1 && "Invalid number of operands!");
995 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
998 virtual void print(raw_ostream &OS) const;
1000 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1001 ARMOperand *Op = new ARMOperand(CondCode);
1008 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1009 ARMOperand *Op = new ARMOperand(CoprocNum);
1010 Op->Cop.Val = CopVal;
1016 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1017 ARMOperand *Op = new ARMOperand(CoprocReg);
1018 Op->Cop.Val = CopVal;
1024 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1025 ARMOperand *Op = new ARMOperand(CCOut);
1026 Op->Reg.RegNum = RegNum;
1032 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1033 ARMOperand *Op = new ARMOperand(Token);
1034 Op->Tok.Data = Str.data();
1035 Op->Tok.Length = Str.size();
1041 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1042 ARMOperand *Op = new ARMOperand(Register);
1043 Op->Reg.RegNum = RegNum;
1049 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1054 ARMOperand *Op = new ARMOperand(ShiftedRegister);
1055 Op->RegShiftedReg.ShiftTy = ShTy;
1056 Op->RegShiftedReg.SrcReg = SrcReg;
1057 Op->RegShiftedReg.ShiftReg = ShiftReg;
1058 Op->RegShiftedReg.ShiftImm = ShiftImm;
1064 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1068 ARMOperand *Op = new ARMOperand(ShiftedImmediate);
1069 Op->RegShiftedImm.ShiftTy = ShTy;
1070 Op->RegShiftedImm.SrcReg = SrcReg;
1071 Op->RegShiftedImm.ShiftImm = ShiftImm;
1077 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1079 ARMOperand *Op = new ARMOperand(ShifterImmediate);
1080 Op->ShifterImm.isASR = isASR;
1081 Op->ShifterImm.Imm = Imm;
1087 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1088 ARMOperand *Op = new ARMOperand(RotateImmediate);
1089 Op->RotImm.Imm = Imm;
1095 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1097 ARMOperand *Op = new ARMOperand(BitfieldDescriptor);
1098 Op->Bitfield.LSB = LSB;
1099 Op->Bitfield.Width = Width;
1106 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1107 SMLoc StartLoc, SMLoc EndLoc) {
1108 KindTy Kind = RegisterList;
1110 if (llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].
1111 contains(Regs.front().first))
1112 Kind = DPRRegisterList;
1113 else if (llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].
1114 contains(Regs.front().first))
1115 Kind = SPRRegisterList;
1117 ARMOperand *Op = new ARMOperand(Kind);
1118 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1119 I = Regs.begin(), E = Regs.end(); I != E; ++I)
1120 Op->Registers.push_back(I->first);
1121 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1122 Op->StartLoc = StartLoc;
1123 Op->EndLoc = EndLoc;
1127 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1128 ARMOperand *Op = new ARMOperand(Immediate);
1135 static ARMOperand *CreateMem(unsigned BaseRegNum,
1136 const MCConstantExpr *OffsetImm,
1137 unsigned OffsetRegNum,
1138 ARM_AM::ShiftOpc ShiftType,
1142 ARMOperand *Op = new ARMOperand(Memory);
1143 Op->Mem.BaseRegNum = BaseRegNum;
1144 Op->Mem.OffsetImm = OffsetImm;
1145 Op->Mem.OffsetRegNum = OffsetRegNum;
1146 Op->Mem.ShiftType = ShiftType;
1147 Op->Mem.ShiftImm = ShiftImm;
1148 Op->Mem.isNegative = isNegative;
1154 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1155 ARM_AM::ShiftOpc ShiftTy,
1158 ARMOperand *Op = new ARMOperand(PostIndexRegister);
1159 Op->PostIdxReg.RegNum = RegNum;
1160 Op->PostIdxReg.isAdd = isAdd;
1161 Op->PostIdxReg.ShiftTy = ShiftTy;
1162 Op->PostIdxReg.ShiftImm = ShiftImm;
1168 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1169 ARMOperand *Op = new ARMOperand(MemBarrierOpt);
1170 Op->MBOpt.Val = Opt;
1176 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1177 ARMOperand *Op = new ARMOperand(ProcIFlags);
1178 Op->IFlags.Val = IFlags;
1184 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1185 ARMOperand *Op = new ARMOperand(MSRMask);
1186 Op->MMask.Val = MMask;
1193 } // end anonymous namespace.
1195 void ARMOperand::print(raw_ostream &OS) const {
1198 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1201 OS << "<ccout " << getReg() << ">";
1204 OS << "<coprocessor number: " << getCoproc() << ">";
1207 OS << "<coprocessor register: " << getCoproc() << ">";
1210 OS << "<mask: " << getMSRMask() << ">";
1213 getImm()->print(OS);
1216 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1220 << " base:" << Mem.BaseRegNum;
1223 case PostIndexRegister:
1224 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
1225 << PostIdxReg.RegNum;
1226 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1227 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1228 << PostIdxReg.ShiftImm;
1232 OS << "<ARM_PROC::";
1233 unsigned IFlags = getProcIFlags();
1234 for (int i=2; i >= 0; --i)
1235 if (IFlags & (1 << i))
1236 OS << ARM_PROC::IFlagsToString(1 << i);
1241 OS << "<register " << getReg() << ">";
1243 case ShifterImmediate:
1244 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1245 << " #" << ShifterImm.Imm << ">";
1247 case ShiftedRegister:
1248 OS << "<so_reg_reg "
1249 << RegShiftedReg.SrcReg
1250 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1251 << ", " << RegShiftedReg.ShiftReg << ", "
1252 << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1255 case ShiftedImmediate:
1256 OS << "<so_reg_imm "
1257 << RegShiftedImm.SrcReg
1258 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1259 << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
1262 case RotateImmediate:
1263 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
1265 case BitfieldDescriptor:
1266 OS << "<bitfield " << "lsb: " << Bitfield.LSB
1267 << ", width: " << Bitfield.Width << ">";
1270 case DPRRegisterList:
1271 case SPRRegisterList: {
1272 OS << "<register_list ";
1274 const SmallVectorImpl<unsigned> &RegList = getRegList();
1275 for (SmallVectorImpl<unsigned>::const_iterator
1276 I = RegList.begin(), E = RegList.end(); I != E; ) {
1278 if (++I < E) OS << ", ";
1285 OS << "'" << getToken() << "'";
1290 /// @name Auto-generated Match Functions
1293 static unsigned MatchRegisterName(StringRef Name);
1297 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
1298 SMLoc &StartLoc, SMLoc &EndLoc) {
1299 RegNo = tryParseRegister();
1301 return (RegNo == (unsigned)-1);
1304 /// Try to parse a register name. The token must be an Identifier when called,
1305 /// and if it is a register name the token is eaten and the register number is
1306 /// returned. Otherwise return -1.
1308 int ARMAsmParser::tryParseRegister() {
1309 const AsmToken &Tok = Parser.getTok();
1310 if (Tok.isNot(AsmToken::Identifier)) return -1;
1312 // FIXME: Validate register for the current architecture; we have to do
1313 // validation later, so maybe there is no need for this here.
1314 std::string upperCase = Tok.getString().str();
1315 std::string lowerCase = LowercaseString(upperCase);
1316 unsigned RegNum = MatchRegisterName(lowerCase);
1318 RegNum = StringSwitch<unsigned>(lowerCase)
1319 .Case("r13", ARM::SP)
1320 .Case("r14", ARM::LR)
1321 .Case("r15", ARM::PC)
1322 .Case("ip", ARM::R12)
1325 if (!RegNum) return -1;
1327 Parser.Lex(); // Eat identifier token.
1331 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
1332 // If a recoverable error occurs, return 1. If an irrecoverable error
1333 // occurs, return -1. An irrecoverable error is one where tokens have been
1334 // consumed in the process of trying to parse the shifter (i.e., when it is
1335 // indeed a shifter operand, but malformed).
1336 int ARMAsmParser::tryParseShiftRegister(
1337 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1338 SMLoc S = Parser.getTok().getLoc();
1339 const AsmToken &Tok = Parser.getTok();
1340 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1342 std::string upperCase = Tok.getString().str();
1343 std::string lowerCase = LowercaseString(upperCase);
1344 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
1345 .Case("lsl", ARM_AM::lsl)
1346 .Case("lsr", ARM_AM::lsr)
1347 .Case("asr", ARM_AM::asr)
1348 .Case("ror", ARM_AM::ror)
1349 .Case("rrx", ARM_AM::rrx)
1350 .Default(ARM_AM::no_shift);
1352 if (ShiftTy == ARM_AM::no_shift)
1355 Parser.Lex(); // Eat the operator.
1357 // The source register for the shift has already been added to the
1358 // operand list, so we need to pop it off and combine it into the shifted
1359 // register operand instead.
1360 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
1361 if (!PrevOp->isReg())
1362 return Error(PrevOp->getStartLoc(), "shift must be of a register");
1363 int SrcReg = PrevOp->getReg();
1366 if (ShiftTy == ARM_AM::rrx) {
1367 // RRX Doesn't have an explicit shift amount. The encoder expects
1368 // the shift register to be the same as the source register. Seems odd,
1372 // Figure out if this is shifted by a constant or a register (for non-RRX).
1373 if (Parser.getTok().is(AsmToken::Hash)) {
1374 Parser.Lex(); // Eat hash.
1375 SMLoc ImmLoc = Parser.getTok().getLoc();
1376 const MCExpr *ShiftExpr = 0;
1377 if (getParser().ParseExpression(ShiftExpr)) {
1378 Error(ImmLoc, "invalid immediate shift value");
1381 // The expression must be evaluatable as an immediate.
1382 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
1384 Error(ImmLoc, "invalid immediate shift value");
1387 // Range check the immediate.
1388 // lsl, ror: 0 <= imm <= 31
1389 // lsr, asr: 0 <= imm <= 32
1390 Imm = CE->getValue();
1392 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
1393 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
1394 Error(ImmLoc, "immediate shift value out of range");
1397 } else if (Parser.getTok().is(AsmToken::Identifier)) {
1398 ShiftReg = tryParseRegister();
1399 SMLoc L = Parser.getTok().getLoc();
1400 if (ShiftReg == -1) {
1401 Error (L, "expected immediate or register in shift operand");
1405 Error (Parser.getTok().getLoc(),
1406 "expected immediate or register in shift operand");
1411 if (ShiftReg && ShiftTy != ARM_AM::rrx)
1412 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
1414 S, Parser.getTok().getLoc()));
1416 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
1417 S, Parser.getTok().getLoc()));
1423 /// Try to parse a register name. The token must be an Identifier when called.
1424 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
1425 /// if there is a "writeback". 'true' if it's not a register.
1427 /// TODO this is likely to change to allow different register types and or to
1428 /// parse for a specific register type.
1430 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1431 SMLoc S = Parser.getTok().getLoc();
1432 int RegNo = tryParseRegister();
1436 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1438 const AsmToken &ExclaimTok = Parser.getTok();
1439 if (ExclaimTok.is(AsmToken::Exclaim)) {
1440 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
1441 ExclaimTok.getLoc()));
1442 Parser.Lex(); // Eat exclaim token
1448 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
1449 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
1451 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
1452 // Use the same layout as the tablegen'erated register name matcher. Ugly,
1454 switch (Name.size()) {
1457 if (Name[0] != CoprocOp)
1474 if (Name[0] != CoprocOp || Name[1] != '1')
1478 case '0': return 10;
1479 case '1': return 11;
1480 case '2': return 12;
1481 case '3': return 13;
1482 case '4': return 14;
1483 case '5': return 15;
1491 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
1492 /// token must be an Identifier when called, and if it is a coprocessor
1493 /// number, the token is eaten and the operand is added to the operand list.
1494 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1495 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1496 SMLoc S = Parser.getTok().getLoc();
1497 const AsmToken &Tok = Parser.getTok();
1498 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1500 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
1502 return MatchOperand_NoMatch;
1504 Parser.Lex(); // Eat identifier token.
1505 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
1506 return MatchOperand_Success;
1509 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
1510 /// token must be an Identifier when called, and if it is a coprocessor
1511 /// number, the token is eaten and the operand is added to the operand list.
1512 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1513 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1514 SMLoc S = Parser.getTok().getLoc();
1515 const AsmToken &Tok = Parser.getTok();
1516 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1518 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
1520 return MatchOperand_NoMatch;
1522 Parser.Lex(); // Eat identifier token.
1523 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
1524 return MatchOperand_Success;
1527 /// Parse a register list, return it if successful else return null. The first
1528 /// token must be a '{' when called.
1530 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1531 assert(Parser.getTok().is(AsmToken::LCurly) &&
1532 "Token is not a Left Curly Brace");
1533 SMLoc S = Parser.getTok().getLoc();
1535 // Read the rest of the registers in the list.
1536 unsigned PrevRegNum = 0;
1537 SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
1540 bool IsRange = Parser.getTok().is(AsmToken::Minus);
1541 Parser.Lex(); // Eat non-identifier token.
1543 const AsmToken &RegTok = Parser.getTok();
1544 SMLoc RegLoc = RegTok.getLoc();
1545 if (RegTok.isNot(AsmToken::Identifier)) {
1546 Error(RegLoc, "register expected");
1550 int RegNum = tryParseRegister();
1552 Error(RegLoc, "register expected");
1557 int Reg = PrevRegNum;
1560 Registers.push_back(std::make_pair(Reg, RegLoc));
1561 } while (Reg != RegNum);
1563 Registers.push_back(std::make_pair(RegNum, RegLoc));
1566 PrevRegNum = RegNum;
1567 } while (Parser.getTok().is(AsmToken::Comma) ||
1568 Parser.getTok().is(AsmToken::Minus));
1570 // Process the right curly brace of the list.
1571 const AsmToken &RCurlyTok = Parser.getTok();
1572 if (RCurlyTok.isNot(AsmToken::RCurly)) {
1573 Error(RCurlyTok.getLoc(), "'}' expected");
1577 SMLoc E = RCurlyTok.getLoc();
1578 Parser.Lex(); // Eat right curly brace token.
1580 // Verify the register list.
1581 SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1582 RI = Registers.begin(), RE = Registers.end();
1584 unsigned HighRegNum = getARMRegisterNumbering(RI->first);
1585 bool EmittedWarning = false;
1587 DenseMap<unsigned, bool> RegMap;
1588 RegMap[HighRegNum] = true;
1590 for (++RI; RI != RE; ++RI) {
1591 const std::pair<unsigned, SMLoc> &RegInfo = *RI;
1592 unsigned Reg = getARMRegisterNumbering(RegInfo.first);
1595 Error(RegInfo.second, "register duplicated in register list");
1599 if (!EmittedWarning && Reg < HighRegNum)
1600 Warning(RegInfo.second,
1601 "register not in ascending order in register list");
1604 HighRegNum = std::max(Reg, HighRegNum);
1607 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
1611 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
1612 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1613 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1614 SMLoc S = Parser.getTok().getLoc();
1615 const AsmToken &Tok = Parser.getTok();
1616 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1617 StringRef OptStr = Tok.getString();
1619 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
1620 .Case("sy", ARM_MB::SY)
1621 .Case("st", ARM_MB::ST)
1622 .Case("sh", ARM_MB::ISH)
1623 .Case("ish", ARM_MB::ISH)
1624 .Case("shst", ARM_MB::ISHST)
1625 .Case("ishst", ARM_MB::ISHST)
1626 .Case("nsh", ARM_MB::NSH)
1627 .Case("un", ARM_MB::NSH)
1628 .Case("nshst", ARM_MB::NSHST)
1629 .Case("unst", ARM_MB::NSHST)
1630 .Case("osh", ARM_MB::OSH)
1631 .Case("oshst", ARM_MB::OSHST)
1635 return MatchOperand_NoMatch;
1637 Parser.Lex(); // Eat identifier token.
1638 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
1639 return MatchOperand_Success;
1642 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
1643 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1644 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1645 SMLoc S = Parser.getTok().getLoc();
1646 const AsmToken &Tok = Parser.getTok();
1647 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1648 StringRef IFlagsStr = Tok.getString();
1650 unsigned IFlags = 0;
1651 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
1652 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
1653 .Case("a", ARM_PROC::A)
1654 .Case("i", ARM_PROC::I)
1655 .Case("f", ARM_PROC::F)
1658 // If some specific iflag is already set, it means that some letter is
1659 // present more than once, this is not acceptable.
1660 if (Flag == ~0U || (IFlags & Flag))
1661 return MatchOperand_NoMatch;
1666 Parser.Lex(); // Eat identifier token.
1667 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
1668 return MatchOperand_Success;
1671 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
1672 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1673 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1674 SMLoc S = Parser.getTok().getLoc();
1675 const AsmToken &Tok = Parser.getTok();
1676 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1677 StringRef Mask = Tok.getString();
1679 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
1680 size_t Start = 0, Next = Mask.find('_');
1681 StringRef Flags = "";
1682 std::string SpecReg = LowercaseString(Mask.slice(Start, Next));
1683 if (Next != StringRef::npos)
1684 Flags = Mask.slice(Next+1, Mask.size());
1686 // FlagsVal contains the complete mask:
1688 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1689 unsigned FlagsVal = 0;
1691 if (SpecReg == "apsr") {
1692 FlagsVal = StringSwitch<unsigned>(Flags)
1693 .Case("nzcvq", 0x8) // same as CPSR_f
1694 .Case("g", 0x4) // same as CPSR_s
1695 .Case("nzcvqg", 0xc) // same as CPSR_fs
1698 if (FlagsVal == ~0U) {
1700 return MatchOperand_NoMatch;
1702 FlagsVal = 0; // No flag
1704 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
1705 if (Flags == "all") // cpsr_all is an alias for cpsr_fc
1707 for (int i = 0, e = Flags.size(); i != e; ++i) {
1708 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
1715 // If some specific flag is already set, it means that some letter is
1716 // present more than once, this is not acceptable.
1717 if (FlagsVal == ~0U || (FlagsVal & Flag))
1718 return MatchOperand_NoMatch;
1721 } else // No match for special register.
1722 return MatchOperand_NoMatch;
1724 // Special register without flags are equivalent to "fc" flags.
1728 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1729 if (SpecReg == "spsr")
1732 Parser.Lex(); // Eat identifier token.
1733 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
1734 return MatchOperand_Success;
1737 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1738 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
1739 int Low, int High) {
1740 const AsmToken &Tok = Parser.getTok();
1741 if (Tok.isNot(AsmToken::Identifier)) {
1742 Error(Parser.getTok().getLoc(), Op + " operand expected.");
1743 return MatchOperand_ParseFail;
1745 StringRef ShiftName = Tok.getString();
1746 std::string LowerOp = LowercaseString(Op);
1747 std::string UpperOp = UppercaseString(Op);
1748 if (ShiftName != LowerOp && ShiftName != UpperOp) {
1749 Error(Parser.getTok().getLoc(), Op + " operand expected.");
1750 return MatchOperand_ParseFail;
1752 Parser.Lex(); // Eat shift type token.
1754 // There must be a '#' and a shift amount.
1755 if (Parser.getTok().isNot(AsmToken::Hash)) {
1756 Error(Parser.getTok().getLoc(), "'#' expected");
1757 return MatchOperand_ParseFail;
1759 Parser.Lex(); // Eat hash token.
1761 const MCExpr *ShiftAmount;
1762 SMLoc Loc = Parser.getTok().getLoc();
1763 if (getParser().ParseExpression(ShiftAmount)) {
1764 Error(Loc, "illegal expression");
1765 return MatchOperand_ParseFail;
1767 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1769 Error(Loc, "constant expression expected");
1770 return MatchOperand_ParseFail;
1772 int Val = CE->getValue();
1773 if (Val < Low || Val > High) {
1774 Error(Loc, "immediate value out of range");
1775 return MatchOperand_ParseFail;
1778 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
1780 return MatchOperand_Success;
1783 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1784 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1785 const AsmToken &Tok = Parser.getTok();
1786 SMLoc S = Tok.getLoc();
1787 if (Tok.isNot(AsmToken::Identifier)) {
1788 Error(Tok.getLoc(), "'be' or 'le' operand expected");
1789 return MatchOperand_ParseFail;
1791 int Val = StringSwitch<int>(Tok.getString())
1795 Parser.Lex(); // Eat the token.
1798 Error(Tok.getLoc(), "'be' or 'le' operand expected");
1799 return MatchOperand_ParseFail;
1801 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
1803 S, Parser.getTok().getLoc()));
1804 return MatchOperand_Success;
1807 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
1808 /// instructions. Legal values are:
1809 /// lsl #n 'n' in [0,31]
1810 /// asr #n 'n' in [1,32]
1811 /// n == 32 encoded as n == 0.
1812 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1813 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1814 const AsmToken &Tok = Parser.getTok();
1815 SMLoc S = Tok.getLoc();
1816 if (Tok.isNot(AsmToken::Identifier)) {
1817 Error(S, "shift operator 'asr' or 'lsl' expected");
1818 return MatchOperand_ParseFail;
1820 StringRef ShiftName = Tok.getString();
1822 if (ShiftName == "lsl" || ShiftName == "LSL")
1824 else if (ShiftName == "asr" || ShiftName == "ASR")
1827 Error(S, "shift operator 'asr' or 'lsl' expected");
1828 return MatchOperand_ParseFail;
1830 Parser.Lex(); // Eat the operator.
1832 // A '#' and a shift amount.
1833 if (Parser.getTok().isNot(AsmToken::Hash)) {
1834 Error(Parser.getTok().getLoc(), "'#' expected");
1835 return MatchOperand_ParseFail;
1837 Parser.Lex(); // Eat hash token.
1839 const MCExpr *ShiftAmount;
1840 SMLoc E = Parser.getTok().getLoc();
1841 if (getParser().ParseExpression(ShiftAmount)) {
1842 Error(E, "malformed shift expression");
1843 return MatchOperand_ParseFail;
1845 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1847 Error(E, "shift amount must be an immediate");
1848 return MatchOperand_ParseFail;
1851 int64_t Val = CE->getValue();
1853 // Shift amount must be in [1,32]
1854 if (Val < 1 || Val > 32) {
1855 Error(E, "'asr' shift amount must be in range [1,32]");
1856 return MatchOperand_ParseFail;
1858 // asr #32 encoded as asr #0.
1859 if (Val == 32) Val = 0;
1861 // Shift amount must be in [1,32]
1862 if (Val < 0 || Val > 31) {
1863 Error(E, "'lsr' shift amount must be in range [0,31]");
1864 return MatchOperand_ParseFail;
1868 E = Parser.getTok().getLoc();
1869 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
1871 return MatchOperand_Success;
1874 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
1875 /// of instructions. Legal values are:
1876 /// ror #n 'n' in {0, 8, 16, 24}
1877 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1878 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1879 const AsmToken &Tok = Parser.getTok();
1880 SMLoc S = Tok.getLoc();
1881 if (Tok.isNot(AsmToken::Identifier)) {
1882 Error(S, "rotate operator 'ror' expected");
1883 return MatchOperand_ParseFail;
1885 StringRef ShiftName = Tok.getString();
1886 if (ShiftName != "ror" && ShiftName != "ROR") {
1887 Error(S, "rotate operator 'ror' expected");
1888 return MatchOperand_ParseFail;
1890 Parser.Lex(); // Eat the operator.
1892 // A '#' and a rotate amount.
1893 if (Parser.getTok().isNot(AsmToken::Hash)) {
1894 Error(Parser.getTok().getLoc(), "'#' expected");
1895 return MatchOperand_ParseFail;
1897 Parser.Lex(); // Eat hash token.
1899 const MCExpr *ShiftAmount;
1900 SMLoc E = Parser.getTok().getLoc();
1901 if (getParser().ParseExpression(ShiftAmount)) {
1902 Error(E, "malformed rotate expression");
1903 return MatchOperand_ParseFail;
1905 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1907 Error(E, "rotate amount must be an immediate");
1908 return MatchOperand_ParseFail;
1911 int64_t Val = CE->getValue();
1912 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
1913 // normally, zero is represented in asm by omitting the rotate operand
1915 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
1916 Error(E, "'ror' rotate amount must be 8, 16, or 24");
1917 return MatchOperand_ParseFail;
1920 E = Parser.getTok().getLoc();
1921 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
1923 return MatchOperand_Success;
1926 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1927 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1928 SMLoc S = Parser.getTok().getLoc();
1929 // The bitfield descriptor is really two operands, the LSB and the width.
1930 if (Parser.getTok().isNot(AsmToken::Hash)) {
1931 Error(Parser.getTok().getLoc(), "'#' expected");
1932 return MatchOperand_ParseFail;
1934 Parser.Lex(); // Eat hash token.
1936 const MCExpr *LSBExpr;
1937 SMLoc E = Parser.getTok().getLoc();
1938 if (getParser().ParseExpression(LSBExpr)) {
1939 Error(E, "malformed immediate expression");
1940 return MatchOperand_ParseFail;
1942 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
1944 Error(E, "'lsb' operand must be an immediate");
1945 return MatchOperand_ParseFail;
1948 int64_t LSB = CE->getValue();
1949 // The LSB must be in the range [0,31]
1950 if (LSB < 0 || LSB > 31) {
1951 Error(E, "'lsb' operand must be in the range [0,31]");
1952 return MatchOperand_ParseFail;
1954 E = Parser.getTok().getLoc();
1956 // Expect another immediate operand.
1957 if (Parser.getTok().isNot(AsmToken::Comma)) {
1958 Error(Parser.getTok().getLoc(), "too few operands");
1959 return MatchOperand_ParseFail;
1961 Parser.Lex(); // Eat hash token.
1962 if (Parser.getTok().isNot(AsmToken::Hash)) {
1963 Error(Parser.getTok().getLoc(), "'#' expected");
1964 return MatchOperand_ParseFail;
1966 Parser.Lex(); // Eat hash token.
1968 const MCExpr *WidthExpr;
1969 if (getParser().ParseExpression(WidthExpr)) {
1970 Error(E, "malformed immediate expression");
1971 return MatchOperand_ParseFail;
1973 CE = dyn_cast<MCConstantExpr>(WidthExpr);
1975 Error(E, "'width' operand must be an immediate");
1976 return MatchOperand_ParseFail;
1979 int64_t Width = CE->getValue();
1980 // The LSB must be in the range [1,32-lsb]
1981 if (Width < 1 || Width > 32 - LSB) {
1982 Error(E, "'width' operand must be in the range [1,32-lsb]");
1983 return MatchOperand_ParseFail;
1985 E = Parser.getTok().getLoc();
1987 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
1989 return MatchOperand_Success;
1992 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1993 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1994 // Check for a post-index addressing register operand. Specifically:
1995 // postidx_reg := '+' register {, shift}
1996 // | '-' register {, shift}
1997 // | register {, shift}
1999 // This method must return MatchOperand_NoMatch without consuming any tokens
2000 // in the case where there is no match, as other alternatives take other
2002 AsmToken Tok = Parser.getTok();
2003 SMLoc S = Tok.getLoc();
2004 bool haveEaten = false;
2007 if (Tok.is(AsmToken::Plus)) {
2008 Parser.Lex(); // Eat the '+' token.
2010 } else if (Tok.is(AsmToken::Minus)) {
2011 Parser.Lex(); // Eat the '-' token.
2015 if (Parser.getTok().is(AsmToken::Identifier))
2016 Reg = tryParseRegister();
2019 return MatchOperand_NoMatch;
2020 Error(Parser.getTok().getLoc(), "register expected");
2021 return MatchOperand_ParseFail;
2023 SMLoc E = Parser.getTok().getLoc();
2025 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
2026 unsigned ShiftImm = 0;
2027 if (Parser.getTok().is(AsmToken::Comma)) {
2028 Parser.Lex(); // Eat the ','.
2029 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
2030 return MatchOperand_ParseFail;
2033 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
2036 return MatchOperand_Success;
2039 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2040 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2041 // Check for a post-index addressing register operand. Specifically:
2042 // am3offset := '+' register
2049 // This method must return MatchOperand_NoMatch without consuming any tokens
2050 // in the case where there is no match, as other alternatives take other
2052 AsmToken Tok = Parser.getTok();
2053 SMLoc S = Tok.getLoc();
2055 // Do immediates first, as we always parse those if we have a '#'.
2056 if (Parser.getTok().is(AsmToken::Hash)) {
2057 Parser.Lex(); // Eat the '#'.
2058 // Explicitly look for a '-', as we need to encode negative zero
2060 bool isNegative = Parser.getTok().is(AsmToken::Minus);
2061 const MCExpr *Offset;
2062 if (getParser().ParseExpression(Offset))
2063 return MatchOperand_ParseFail;
2064 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2066 Error(S, "constant expression expected");
2067 return MatchOperand_ParseFail;
2069 SMLoc E = Tok.getLoc();
2070 // Negative zero is encoded as the flag value INT32_MIN.
2071 int32_t Val = CE->getValue();
2072 if (isNegative && Val == 0)
2076 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
2078 return MatchOperand_Success;
2082 bool haveEaten = false;
2085 if (Tok.is(AsmToken::Plus)) {
2086 Parser.Lex(); // Eat the '+' token.
2088 } else if (Tok.is(AsmToken::Minus)) {
2089 Parser.Lex(); // Eat the '-' token.
2093 if (Parser.getTok().is(AsmToken::Identifier))
2094 Reg = tryParseRegister();
2097 return MatchOperand_NoMatch;
2098 Error(Parser.getTok().getLoc(), "register expected");
2099 return MatchOperand_ParseFail;
2101 SMLoc E = Parser.getTok().getLoc();
2103 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
2106 return MatchOperand_Success;
2109 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2110 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2111 /// when they refer multiple MIOperands inside a single one.
2113 cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2114 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2115 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2117 // Create a writeback register dummy placeholder.
2118 Inst.addOperand(MCOperand::CreateImm(0));
2120 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2121 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2125 /// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2126 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2127 /// when they refer multiple MIOperands inside a single one.
2129 cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2130 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2131 // Create a writeback register dummy placeholder.
2132 Inst.addOperand(MCOperand::CreateImm(0));
2133 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2134 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2135 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2139 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2140 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2141 /// when they refer multiple MIOperands inside a single one.
2143 cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2144 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2145 // Create a writeback register dummy placeholder.
2146 Inst.addOperand(MCOperand::CreateImm(0));
2147 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2148 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2149 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2153 /// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2154 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2155 /// when they refer multiple MIOperands inside a single one.
2157 cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2158 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2159 // Create a writeback register dummy placeholder.
2160 Inst.addOperand(MCOperand::CreateImm(0));
2161 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2162 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2163 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2167 /// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
2168 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2169 /// when they refer multiple MIOperands inside a single one.
2171 cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2172 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2174 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2175 // Create a writeback register dummy placeholder.
2176 Inst.addOperand(MCOperand::CreateImm(0));
2178 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2180 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2182 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2186 /// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
2187 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2188 /// when they refer multiple MIOperands inside a single one.
2190 cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2191 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2193 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2194 // Create a writeback register dummy placeholder.
2195 Inst.addOperand(MCOperand::CreateImm(0));
2197 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2199 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2201 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2205 /// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
2206 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2207 /// when they refer multiple MIOperands inside a single one.
2209 cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2210 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2211 // Create a writeback register dummy placeholder.
2212 Inst.addOperand(MCOperand::CreateImm(0));
2214 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2216 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2218 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2220 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2224 /// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
2225 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2226 /// when they refer multiple MIOperands inside a single one.
2228 cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2229 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2230 // Create a writeback register dummy placeholder.
2231 Inst.addOperand(MCOperand::CreateImm(0));
2233 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2235 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2237 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2239 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2243 /// cvtLdrdPre - Convert parsed operands to MCInst.
2244 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2245 /// when they refer multiple MIOperands inside a single one.
2247 cvtLdrdPre(MCInst &Inst, unsigned Opcode,
2248 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2250 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2251 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2252 // Create a writeback register dummy placeholder.
2253 Inst.addOperand(MCOperand::CreateImm(0));
2255 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2257 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2261 /// cvtStrdPre - Convert parsed operands to MCInst.
2262 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2263 /// when they refer multiple MIOperands inside a single one.
2265 cvtStrdPre(MCInst &Inst, unsigned Opcode,
2266 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2267 // Create a writeback register dummy placeholder.
2268 Inst.addOperand(MCOperand::CreateImm(0));
2270 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2271 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2273 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2275 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2279 /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2280 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2281 /// when they refer multiple MIOperands inside a single one.
2283 cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2284 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2285 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2286 // Create a writeback register dummy placeholder.
2287 Inst.addOperand(MCOperand::CreateImm(0));
2288 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2289 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2294 /// Parse an ARM memory expression, return false if successful else return true
2295 /// or an error. The first token must be a '[' when called.
2297 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2299 assert(Parser.getTok().is(AsmToken::LBrac) &&
2300 "Token is not a Left Bracket");
2301 S = Parser.getTok().getLoc();
2302 Parser.Lex(); // Eat left bracket token.
2304 const AsmToken &BaseRegTok = Parser.getTok();
2305 int BaseRegNum = tryParseRegister();
2306 if (BaseRegNum == -1)
2307 return Error(BaseRegTok.getLoc(), "register expected");
2309 // The next token must either be a comma or a closing bracket.
2310 const AsmToken &Tok = Parser.getTok();
2311 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
2312 return Error(Tok.getLoc(), "malformed memory operand");
2314 if (Tok.is(AsmToken::RBrac)) {
2316 Parser.Lex(); // Eat right bracket token.
2318 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
2324 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
2325 Parser.Lex(); // Eat the comma.
2327 // If we have a '#' it's an immediate offset, else assume it's a register
2329 if (Parser.getTok().is(AsmToken::Hash)) {
2330 Parser.Lex(); // Eat the '#'.
2331 E = Parser.getTok().getLoc();
2333 // FIXME: Special case #-0 so we can correctly set the U bit.
2335 const MCExpr *Offset;
2336 if (getParser().ParseExpression(Offset))
2339 // The expression has to be a constant. Memory references with relocations
2340 // don't come through here, as they use the <label> forms of the relevant
2342 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2344 return Error (E, "constant expression expected");
2346 // Now we should have the closing ']'
2347 E = Parser.getTok().getLoc();
2348 if (Parser.getTok().isNot(AsmToken::RBrac))
2349 return Error(E, "']' expected");
2350 Parser.Lex(); // Eat right bracket token.
2352 // Don't worry about range checking the value here. That's handled by
2353 // the is*() predicates.
2354 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
2355 ARM_AM::no_shift, 0, false, S,E));
2357 // If there's a pre-indexing writeback marker, '!', just add it as a token
2359 if (Parser.getTok().is(AsmToken::Exclaim)) {
2360 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2361 Parser.Lex(); // Eat the '!'.
2367 // The register offset is optionally preceded by a '+' or '-'
2368 bool isNegative = false;
2369 if (Parser.getTok().is(AsmToken::Minus)) {
2371 Parser.Lex(); // Eat the '-'.
2372 } else if (Parser.getTok().is(AsmToken::Plus)) {
2374 Parser.Lex(); // Eat the '+'.
2377 E = Parser.getTok().getLoc();
2378 int OffsetRegNum = tryParseRegister();
2379 if (OffsetRegNum == -1)
2380 return Error(E, "register expected");
2382 // If there's a shift operator, handle it.
2383 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
2384 unsigned ShiftImm = 0;
2385 if (Parser.getTok().is(AsmToken::Comma)) {
2386 Parser.Lex(); // Eat the ','.
2387 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
2391 // Now we should have the closing ']'
2392 E = Parser.getTok().getLoc();
2393 if (Parser.getTok().isNot(AsmToken::RBrac))
2394 return Error(E, "']' expected");
2395 Parser.Lex(); // Eat right bracket token.
2397 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
2398 ShiftType, ShiftImm, isNegative,
2401 // If there's a pre-indexing writeback marker, '!', just add it as a token
2403 if (Parser.getTok().is(AsmToken::Exclaim)) {
2404 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2405 Parser.Lex(); // Eat the '!'.
2411 /// parseMemRegOffsetShift - one of these two:
2412 /// ( lsl | lsr | asr | ror ) , # shift_amount
2414 /// return true if it parses a shift otherwise it returns false.
2415 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
2417 SMLoc Loc = Parser.getTok().getLoc();
2418 const AsmToken &Tok = Parser.getTok();
2419 if (Tok.isNot(AsmToken::Identifier))
2421 StringRef ShiftName = Tok.getString();
2422 if (ShiftName == "lsl" || ShiftName == "LSL")
2424 else if (ShiftName == "lsr" || ShiftName == "LSR")
2426 else if (ShiftName == "asr" || ShiftName == "ASR")
2428 else if (ShiftName == "ror" || ShiftName == "ROR")
2430 else if (ShiftName == "rrx" || ShiftName == "RRX")
2433 return Error(Loc, "illegal shift operator");
2434 Parser.Lex(); // Eat shift type token.
2436 // rrx stands alone.
2438 if (St != ARM_AM::rrx) {
2439 Loc = Parser.getTok().getLoc();
2440 // A '#' and a shift amount.
2441 const AsmToken &HashTok = Parser.getTok();
2442 if (HashTok.isNot(AsmToken::Hash))
2443 return Error(HashTok.getLoc(), "'#' expected");
2444 Parser.Lex(); // Eat hash token.
2447 if (getParser().ParseExpression(Expr))
2449 // Range check the immediate.
2450 // lsl, ror: 0 <= imm <= 31
2451 // lsr, asr: 0 <= imm <= 32
2452 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2454 return Error(Loc, "shift amount must be an immediate");
2455 int64_t Imm = CE->getValue();
2457 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
2458 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
2459 return Error(Loc, "immediate shift value out of range");
2466 /// Parse a arm instruction operand. For now this parses the operand regardless
2467 /// of the mnemonic.
2468 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2469 StringRef Mnemonic) {
2472 // Check if the current operand has a custom associated parser, if so, try to
2473 // custom parse the operand, or fallback to the general approach.
2474 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
2475 if (ResTy == MatchOperand_Success)
2477 // If there wasn't a custom match, try the generic matcher below. Otherwise,
2478 // there was a match, but an error occurred, in which case, just return that
2479 // the operand parsing failed.
2480 if (ResTy == MatchOperand_ParseFail)
2483 switch (getLexer().getKind()) {
2485 Error(Parser.getTok().getLoc(), "unexpected token in operand");
2487 case AsmToken::Identifier: {
2488 if (!tryParseRegisterWithWriteBack(Operands))
2490 int Res = tryParseShiftRegister(Operands);
2491 if (Res == 0) // success
2493 else if (Res == -1) // irrecoverable error
2496 // Fall though for the Identifier case that is not a register or a
2499 case AsmToken::Integer: // things like 1f and 2b as a branch targets
2500 case AsmToken::Dot: { // . as a branch target
2501 // This was not a register so parse other operands that start with an
2502 // identifier (like labels) as expressions and create them as immediates.
2503 const MCExpr *IdVal;
2504 S = Parser.getTok().getLoc();
2505 if (getParser().ParseExpression(IdVal))
2507 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2508 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
2511 case AsmToken::LBrac:
2512 return parseMemory(Operands);
2513 case AsmToken::LCurly:
2514 return parseRegisterList(Operands);
2515 case AsmToken::Hash:
2516 // #42 -> immediate.
2517 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
2518 S = Parser.getTok().getLoc();
2520 const MCExpr *ImmVal;
2521 if (getParser().ParseExpression(ImmVal))
2523 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2524 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
2526 case AsmToken::Colon: {
2527 // ":lower16:" and ":upper16:" expression prefixes
2528 // FIXME: Check it's an expression prefix,
2529 // e.g. (FOO - :lower16:BAR) isn't legal.
2530 ARMMCExpr::VariantKind RefKind;
2531 if (parsePrefix(RefKind))
2534 const MCExpr *SubExprVal;
2535 if (getParser().ParseExpression(SubExprVal))
2538 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
2540 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2541 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
2547 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
2548 // :lower16: and :upper16:.
2549 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
2550 RefKind = ARMMCExpr::VK_ARM_None;
2552 // :lower16: and :upper16: modifiers
2553 assert(getLexer().is(AsmToken::Colon) && "expected a :");
2554 Parser.Lex(); // Eat ':'
2556 if (getLexer().isNot(AsmToken::Identifier)) {
2557 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
2561 StringRef IDVal = Parser.getTok().getIdentifier();
2562 if (IDVal == "lower16") {
2563 RefKind = ARMMCExpr::VK_ARM_LO16;
2564 } else if (IDVal == "upper16") {
2565 RefKind = ARMMCExpr::VK_ARM_HI16;
2567 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
2572 if (getLexer().isNot(AsmToken::Colon)) {
2573 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
2576 Parser.Lex(); // Eat the last ':'
2581 ARMAsmParser::applyPrefixToExpr(const MCExpr *E,
2582 MCSymbolRefExpr::VariantKind Variant) {
2583 // Recurse over the given expression, rebuilding it to apply the given variant
2584 // to the leftmost symbol.
2585 if (Variant == MCSymbolRefExpr::VK_None)
2588 switch (E->getKind()) {
2589 case MCExpr::Target:
2590 llvm_unreachable("Can't handle target expr yet");
2591 case MCExpr::Constant:
2592 llvm_unreachable("Can't handle lower16/upper16 of constant yet");
2594 case MCExpr::SymbolRef: {
2595 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
2597 if (SRE->getKind() != MCSymbolRefExpr::VK_None)
2600 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext());
2604 llvm_unreachable("Can't handle unary expressions yet");
2606 case MCExpr::Binary: {
2607 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
2608 const MCExpr *LHS = applyPrefixToExpr(BE->getLHS(), Variant);
2609 const MCExpr *RHS = BE->getRHS();
2613 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext());
2617 assert(0 && "Invalid expression kind!");
2621 /// \brief Given a mnemonic, split out possible predication code and carry
2622 /// setting letters to form a canonical mnemonic and flags.
2624 // FIXME: Would be nice to autogen this.
2625 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
2626 unsigned &PredicationCode,
2628 unsigned &ProcessorIMod) {
2629 PredicationCode = ARMCC::AL;
2630 CarrySetting = false;
2633 // Ignore some mnemonics we know aren't predicated forms.
2635 // FIXME: Would be nice to autogen this.
2636 if ((Mnemonic == "movs" && isThumb()) ||
2637 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
2638 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
2639 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
2640 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
2641 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
2642 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
2643 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
2646 // First, split out any predication code. Ignore mnemonics we know aren't
2647 // predicated but do have a carry-set and so weren't caught above.
2648 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
2649 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
2650 Mnemonic != "umlals" && Mnemonic != "umulls") {
2651 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
2652 .Case("eq", ARMCC::EQ)
2653 .Case("ne", ARMCC::NE)
2654 .Case("hs", ARMCC::HS)
2655 .Case("cs", ARMCC::HS)
2656 .Case("lo", ARMCC::LO)
2657 .Case("cc", ARMCC::LO)
2658 .Case("mi", ARMCC::MI)
2659 .Case("pl", ARMCC::PL)
2660 .Case("vs", ARMCC::VS)
2661 .Case("vc", ARMCC::VC)
2662 .Case("hi", ARMCC::HI)
2663 .Case("ls", ARMCC::LS)
2664 .Case("ge", ARMCC::GE)
2665 .Case("lt", ARMCC::LT)
2666 .Case("gt", ARMCC::GT)
2667 .Case("le", ARMCC::LE)
2668 .Case("al", ARMCC::AL)
2671 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
2672 PredicationCode = CC;
2676 // Next, determine if we have a carry setting bit. We explicitly ignore all
2677 // the instructions we know end in 's'.
2678 if (Mnemonic.endswith("s") &&
2679 !(Mnemonic == "asrs" || Mnemonic == "cps" || Mnemonic == "mls" ||
2680 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
2681 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
2682 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
2683 Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
2684 (Mnemonic == "movs" && isThumb()))) {
2685 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
2686 CarrySetting = true;
2689 // The "cps" instruction can have a interrupt mode operand which is glued into
2690 // the mnemonic. Check if this is the case, split it and parse the imod op
2691 if (Mnemonic.startswith("cps")) {
2692 // Split out any imod code.
2694 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
2695 .Case("ie", ARM_PROC::IE)
2696 .Case("id", ARM_PROC::ID)
2699 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
2700 ProcessorIMod = IMod;
2707 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
2708 /// inclusion of carry set or predication code operands.
2710 // FIXME: It would be nice to autogen this.
2712 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
2713 bool &CanAcceptPredicationCode) {
2714 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
2715 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
2716 Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
2717 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
2718 Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" ||
2719 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
2720 Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
2721 Mnemonic == "eor" || Mnemonic == "smlal" ||
2722 // FIXME: We need a better way. This really confused Thumb2
2723 // parsing for 'mov'.
2724 (Mnemonic == "mov" && !isThumbOne())) {
2725 CanAcceptCarrySet = true;
2727 CanAcceptCarrySet = false;
2730 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
2731 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
2732 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
2733 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
2734 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "clrex" ||
2735 Mnemonic == "setend" ||
2736 ((Mnemonic == "pld" || Mnemonic == "pli") && !isThumb()) ||
2737 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs"))
2739 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumb())) {
2740 CanAcceptPredicationCode = false;
2742 CanAcceptPredicationCode = true;
2746 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
2747 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
2748 CanAcceptPredicationCode = false;
2751 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
2752 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2754 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
2755 // another does not. Specifically, the MOVW instruction does not. So we
2756 // special case it here and remove the defaulted (non-setting) cc_out
2757 // operand if that's the instruction we're trying to match.
2759 // We do this as post-processing of the explicit operands rather than just
2760 // conditionally adding the cc_out in the first place because we need
2761 // to check the type of the parsed immediate operand.
2762 if (Mnemonic == "mov" && Operands.size() > 4 &&
2763 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
2764 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
2765 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
2768 // Register-register 'add' for thumb does not have a cc_out operand
2769 // when there are only two register operands.
2770 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
2771 static_cast<ARMOperand*>(Operands[3])->isReg() &&
2772 static_cast<ARMOperand*>(Operands[4])->isReg() &&
2773 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
2779 /// Parse an arm instruction mnemonic followed by its operands.
2780 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
2781 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2782 // Create the leading tokens for the mnemonic, split by '.' characters.
2783 size_t Start = 0, Next = Name.find('.');
2784 StringRef Mnemonic = Name.slice(Start, Next);
2786 // Split out the predication code and carry setting flag from the mnemonic.
2787 unsigned PredicationCode;
2788 unsigned ProcessorIMod;
2790 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
2793 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
2795 // FIXME: This is all a pretty gross hack. We should automatically handle
2796 // optional operands like this via tblgen.
2798 // Next, add the CCOut and ConditionCode operands, if needed.
2800 // For mnemonics which can ever incorporate a carry setting bit or predication
2801 // code, our matching model involves us always generating CCOut and
2802 // ConditionCode operands to match the mnemonic "as written" and then we let
2803 // the matcher deal with finding the right instruction or generating an
2804 // appropriate error.
2805 bool CanAcceptCarrySet, CanAcceptPredicationCode;
2806 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
2808 // If we had a carry-set on an instruction that can't do that, issue an
2810 if (!CanAcceptCarrySet && CarrySetting) {
2811 Parser.EatToEndOfStatement();
2812 return Error(NameLoc, "instruction '" + Mnemonic +
2813 "' can not set flags, but 's' suffix specified");
2815 // If we had a predication code on an instruction that can't do that, issue an
2817 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
2818 Parser.EatToEndOfStatement();
2819 return Error(NameLoc, "instruction '" + Mnemonic +
2820 "' is not predicable, but condition code specified");
2823 // Add the carry setting operand, if necessary.
2825 // FIXME: It would be awesome if we could somehow invent a location such that
2826 // match errors on this operand would print a nice diagnostic about how the
2827 // 's' character in the mnemonic resulted in a CCOut operand.
2828 if (CanAcceptCarrySet)
2829 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
2832 // Add the predication code operand, if necessary.
2833 if (CanAcceptPredicationCode) {
2834 Operands.push_back(ARMOperand::CreateCondCode(
2835 ARMCC::CondCodes(PredicationCode), NameLoc));
2838 // Add the processor imod operand, if necessary.
2839 if (ProcessorIMod) {
2840 Operands.push_back(ARMOperand::CreateImm(
2841 MCConstantExpr::Create(ProcessorIMod, getContext()),
2844 // This mnemonic can't ever accept a imod, but the user wrote
2845 // one (or misspelled another mnemonic).
2847 // FIXME: Issue a nice error.
2850 // Add the remaining tokens in the mnemonic.
2851 while (Next != StringRef::npos) {
2853 Next = Name.find('.', Start + 1);
2854 StringRef ExtraToken = Name.slice(Start, Next);
2856 Operands.push_back(ARMOperand::CreateToken(ExtraToken, NameLoc));
2859 // Read the remaining operands.
2860 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2861 // Read the first operand.
2862 if (parseOperand(Operands, Mnemonic)) {
2863 Parser.EatToEndOfStatement();
2867 while (getLexer().is(AsmToken::Comma)) {
2868 Parser.Lex(); // Eat the comma.
2870 // Parse and remember the operand.
2871 if (parseOperand(Operands, Mnemonic)) {
2872 Parser.EatToEndOfStatement();
2878 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2879 Parser.EatToEndOfStatement();
2880 return TokError("unexpected token in argument list");
2883 Parser.Lex(); // Consume the EndOfStatement
2885 // Some instructions, mostly Thumb, have forms for the same mnemonic that
2886 // do and don't have a cc_out optional-def operand. With some spot-checks
2887 // of the operand list, we can figure out which variant we're trying to
2888 // parse and adjust accordingly before actually matching. Reason number
2889 // #317 the table driven matcher doesn't fit well with the ARM instruction
2891 if (shouldOmitCCOutOperand(Mnemonic, Operands)) {
2892 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
2893 Operands.erase(Operands.begin() + 1);
2897 // ARM mode 'blx' need special handling, as the register operand version
2898 // is predicable, but the label operand version is not. So, we can't rely
2899 // on the Mnemonic based checking to correctly figure out when to put
2900 // a CondCode operand in the list. If we're trying to match the label
2901 // version, remove the CondCode operand here.
2902 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
2903 static_cast<ARMOperand*>(Operands[2])->isImm()) {
2904 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
2905 Operands.erase(Operands.begin() + 1);
2909 // The vector-compare-to-zero instructions have a literal token "#0" at
2910 // the end that comes to here as an immediate operand. Convert it to a
2911 // token to play nicely with the matcher.
2912 if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
2913 Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
2914 static_cast<ARMOperand*>(Operands[5])->isImm()) {
2915 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
2916 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
2917 if (CE && CE->getValue() == 0) {
2918 Operands.erase(Operands.begin() + 5);
2919 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
2926 // Validate context-sensitive operand constraints.
2927 // FIXME: We would really like to be able to tablegen'erate this.
2929 validateInstruction(MCInst &Inst,
2930 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2931 switch (Inst.getOpcode()) {
2934 case ARM::LDRD_POST:
2936 // Rt2 must be Rt + 1.
2937 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
2938 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
2940 return Error(Operands[3]->getStartLoc(),
2941 "destination operands must be sequential");
2945 // Rt2 must be Rt + 1.
2946 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
2947 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
2949 return Error(Operands[3]->getStartLoc(),
2950 "source operands must be sequential");
2954 case ARM::STRD_POST:
2956 // Rt2 must be Rt + 1.
2957 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
2958 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
2960 return Error(Operands[3]->getStartLoc(),
2961 "source operands must be sequential");
2966 // width must be in range [1, 32-lsb]
2967 unsigned lsb = Inst.getOperand(2).getImm();
2968 unsigned widthm1 = Inst.getOperand(3).getImm();
2969 if (widthm1 >= 32 - lsb)
2970 return Error(Operands[5]->getStartLoc(),
2971 "bitfield width must be in range [1,32-lsb]");
2980 processInstruction(MCInst &Inst,
2981 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2982 switch (Inst.getOpcode()) {
2983 case ARM::LDMIA_UPD:
2984 // If this is a load of a single register via a 'pop', then we should use
2985 // a post-indexed LDR instruction instead, per the ARM ARM.
2986 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
2987 Inst.getNumOperands() == 5) {
2989 TmpInst.setOpcode(ARM::LDR_POST_IMM);
2990 TmpInst.addOperand(Inst.getOperand(4)); // Rt
2991 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
2992 TmpInst.addOperand(Inst.getOperand(1)); // Rn
2993 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
2994 TmpInst.addOperand(MCOperand::CreateImm(4));
2995 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
2996 TmpInst.addOperand(Inst.getOperand(3));
3000 case ARM::STMDB_UPD:
3001 // If this is a store of a single register via a 'push', then we should use
3002 // a pre-indexed STR instruction instead, per the ARM ARM.
3003 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
3004 Inst.getNumOperands() == 5) {
3006 TmpInst.setOpcode(ARM::STR_PRE_IMM);
3007 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3008 TmpInst.addOperand(Inst.getOperand(4)); // Rt
3009 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
3010 TmpInst.addOperand(MCOperand::CreateImm(-4));
3011 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3012 TmpInst.addOperand(Inst.getOperand(3));
3017 // If the immediate is in the range 0-7, we really wanted tADDi3.
3018 if (Inst.getOperand(3).getImm() < 8)
3019 Inst.setOpcode(ARM::tADDi3);
3024 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around
3025 // the ARMInsts array) instead. Getting that here requires awkward
3026 // API changes, though. Better way?
3028 extern MCInstrDesc ARMInsts[];
3030 static MCInstrDesc &getInstDesc(unsigned Opcode) {
3031 return ARMInsts[Opcode];
3034 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
3035 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
3036 // suffix depending on whether they're in an IT block or not.
3037 unsigned Opc = Inst.getOpcode();
3038 MCInstrDesc &MCID = getInstDesc(Opc);
3039 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
3040 assert(MCID.hasOptionalDef() &&
3041 "optionally flag setting instruction missing optional def operand");
3042 assert(MCID.NumOperands == Inst.getNumOperands() &&
3043 "operand count mismatch!");
3044 // Find the optional-def operand (cc_out).
3047 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
3050 // If we're parsing Thumb1, reject it completely.
3051 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3052 return Match_MnemonicFail;
3053 // If we're parsing Thumb2, which form is legal depends on whether we're
3055 // FIXME: We don't yet do IT blocks, so just always consider it to be
3056 // that we aren't in one until we do.
3057 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3058 return Match_RequiresITBlock;
3060 // Some high-register supporting Thumb1 encodings only allow both registers
3061 // to be from r0-r7 when in Thumb2.
3062 else if (Opc == ARM::tADDhirr && isThumbOne() &&
3063 isARMLowRegister(Inst.getOperand(1).getReg()) &&
3064 isARMLowRegister(Inst.getOperand(2).getReg()))
3065 return Match_RequiresThumb2;
3066 // Others only require ARMv6 or later.
3067 else if (Opc == ARM::tMOVr && isThumbOne() &&
3068 isARMLowRegister(Inst.getOperand(0).getReg()) &&
3069 isARMLowRegister(Inst.getOperand(1).getReg()))
3070 return Match_RequiresV6;
3071 return Match_Success;
3075 MatchAndEmitInstruction(SMLoc IDLoc,
3076 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
3080 unsigned MatchResult;
3081 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
3082 switch (MatchResult) {
3085 // Context sensitive operand constraints aren't handled by the matcher,
3086 // so check them here.
3087 if (validateInstruction(Inst, Operands))
3090 // Some instructions need post-processing to, for example, tweak which
3091 // encoding is selected.
3092 processInstruction(Inst, Operands);
3094 Out.EmitInstruction(Inst);
3096 case Match_MissingFeature:
3097 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
3099 case Match_InvalidOperand: {
3100 SMLoc ErrorLoc = IDLoc;
3101 if (ErrorInfo != ~0U) {
3102 if (ErrorInfo >= Operands.size())
3103 return Error(IDLoc, "too few operands for instruction");
3105 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
3106 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
3109 return Error(ErrorLoc, "invalid operand for instruction");
3111 case Match_MnemonicFail:
3112 return Error(IDLoc, "invalid instruction");
3113 case Match_ConversionFail:
3114 return Error(IDLoc, "unable to convert operands to instruction");
3115 case Match_RequiresITBlock:
3116 return Error(IDLoc, "instruction only valid inside IT block");
3117 case Match_RequiresV6:
3118 return Error(IDLoc, "instruction variant requires ARMv6 or later");
3119 case Match_RequiresThumb2:
3120 return Error(IDLoc, "instruction variant requires Thumb2");
3123 llvm_unreachable("Implement any new match types added!");
3127 /// parseDirective parses the arm specific directives
3128 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
3129 StringRef IDVal = DirectiveID.getIdentifier();
3130 if (IDVal == ".word")
3131 return parseDirectiveWord(4, DirectiveID.getLoc());
3132 else if (IDVal == ".thumb")
3133 return parseDirectiveThumb(DirectiveID.getLoc());
3134 else if (IDVal == ".thumb_func")
3135 return parseDirectiveThumbFunc(DirectiveID.getLoc());
3136 else if (IDVal == ".code")
3137 return parseDirectiveCode(DirectiveID.getLoc());
3138 else if (IDVal == ".syntax")
3139 return parseDirectiveSyntax(DirectiveID.getLoc());
3143 /// parseDirectiveWord
3144 /// ::= .word [ expression (, expression)* ]
3145 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
3146 if (getLexer().isNot(AsmToken::EndOfStatement)) {
3148 const MCExpr *Value;
3149 if (getParser().ParseExpression(Value))
3152 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
3154 if (getLexer().is(AsmToken::EndOfStatement))
3157 // FIXME: Improve diagnostic.
3158 if (getLexer().isNot(AsmToken::Comma))
3159 return Error(L, "unexpected token in directive");
3168 /// parseDirectiveThumb
3170 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
3171 if (getLexer().isNot(AsmToken::EndOfStatement))
3172 return Error(L, "unexpected token in directive");
3175 // TODO: set thumb mode
3176 // TODO: tell the MC streamer the mode
3177 // getParser().getStreamer().Emit???();
3181 /// parseDirectiveThumbFunc
3182 /// ::= .thumbfunc symbol_name
3183 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
3184 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
3185 bool isMachO = MAI.hasSubsectionsViaSymbols();
3188 // Darwin asm has function name after .thumb_func direction
3191 const AsmToken &Tok = Parser.getTok();
3192 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
3193 return Error(L, "unexpected token in .thumb_func directive");
3194 Name = Tok.getString();
3195 Parser.Lex(); // Consume the identifier token.
3198 if (getLexer().isNot(AsmToken::EndOfStatement))
3199 return Error(L, "unexpected token in directive");
3202 // FIXME: assuming function name will be the line following .thumb_func
3204 Name = Parser.getTok().getString();
3207 // Mark symbol as a thumb symbol.
3208 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
3209 getParser().getStreamer().EmitThumbFunc(Func);
3213 /// parseDirectiveSyntax
3214 /// ::= .syntax unified | divided
3215 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
3216 const AsmToken &Tok = Parser.getTok();
3217 if (Tok.isNot(AsmToken::Identifier))
3218 return Error(L, "unexpected token in .syntax directive");
3219 StringRef Mode = Tok.getString();
3220 if (Mode == "unified" || Mode == "UNIFIED")
3222 else if (Mode == "divided" || Mode == "DIVIDED")
3223 return Error(L, "'.syntax divided' arm asssembly not supported");
3225 return Error(L, "unrecognized syntax mode in .syntax directive");
3227 if (getLexer().isNot(AsmToken::EndOfStatement))
3228 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3231 // TODO tell the MC streamer the mode
3232 // getParser().getStreamer().Emit???();
3236 /// parseDirectiveCode
3237 /// ::= .code 16 | 32
3238 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
3239 const AsmToken &Tok = Parser.getTok();
3240 if (Tok.isNot(AsmToken::Integer))
3241 return Error(L, "unexpected token in .code directive");
3242 int64_t Val = Parser.getTok().getIntVal();
3248 return Error(L, "invalid operand to .code directive");
3250 if (getLexer().isNot(AsmToken::EndOfStatement))
3251 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3257 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
3262 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
3269 extern "C" void LLVMInitializeARMAsmLexer();
3271 /// Force static initialization.
3272 extern "C" void LLVMInitializeARMAsmParser() {
3273 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
3274 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
3275 LLVMInitializeARMAsmLexer();
3278 #define GET_REGISTER_MATCHER
3279 #define GET_MATCHER_IMPLEMENTATION
3280 #include "ARMGenAsmMatcher.inc"