1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMAddressingModes.h"
12 #include "ARMSubtarget.h"
13 #include "llvm/MC/MCParser/MCAsmLexer.h"
14 #include "llvm/MC/MCParser/MCAsmParser.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/Target/TargetRegistry.h"
21 #include "llvm/Target/TargetAsmParser.h"
22 #include "llvm/Support/SourceMgr.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/ADT/StringSwitch.h"
26 #include "llvm/ADT/Twine.h"
29 // The shift types for register controlled shifts in arm memory addressing
41 class ARMAsmParser : public TargetAsmParser {
45 MCAsmParser &getParser() const { return Parser; }
47 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
49 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
51 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
53 int TryParseRegister();
54 ARMOperand *TryParseRegisterWithWriteBack();
55 ARMOperand *ParseRegisterList();
56 ARMOperand *ParseMemory();
58 bool ParseMemoryOffsetReg(bool &Negative,
59 bool &OffsetRegShifted,
60 enum ShiftType &ShiftType,
61 const MCExpr *&ShiftAmount,
62 const MCExpr *&Offset,
67 bool ParseShift(enum ShiftType &St, const MCExpr *&ShiftAmount, SMLoc &E);
69 ARMOperand *ParseOperand();
71 bool ParseDirectiveWord(unsigned Size, SMLoc L);
73 bool ParseDirectiveThumb(SMLoc L);
75 bool ParseDirectiveThumbFunc(SMLoc L);
77 bool ParseDirectiveCode(SMLoc L);
79 bool ParseDirectiveSyntax(SMLoc L);
81 bool MatchAndEmitInstruction(SMLoc IDLoc,
82 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
85 /// @name Auto-generated Match Functions
88 #define GET_ASSEMBLER_HEADER
89 #include "ARMGenAsmMatcher.inc"
95 ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
96 : TargetAsmParser(T), Parser(_Parser), TM(_TM) {
97 // Initialize the set of available features.
98 setAvailableFeatures(ComputeAvailableFeatures(
99 &TM.getSubtarget<ARMSubtarget>()));
102 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
103 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
105 virtual bool ParseDirective(AsmToken DirectiveID);
107 } // end anonymous namespace
111 /// ARMOperand - Instances of this class represent a parsed ARM machine
113 struct ARMOperand : public MCParsedAsmOperand {
124 SMLoc StartLoc, EndLoc;
128 ARMCC::CondCodes Val;
150 // This is for all forms of ARM address expressions
153 unsigned OffsetRegNum; // used when OffsetIsReg is true
154 const MCExpr *Offset; // used when OffsetIsReg is false
155 const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
156 enum ShiftType ShiftType; // used when OffsetRegShifted is true
158 OffsetRegShifted : 1, // only used when OffsetIsReg is true
162 Negative : 1, // only used when OffsetIsReg is true
168 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
170 StartLoc = o.StartLoc;
194 /// getStartLoc - Get the location of the first token of this operand.
195 SMLoc getStartLoc() const { return StartLoc; }
196 /// getEndLoc - Get the location of the last token of this operand.
197 SMLoc getEndLoc() const { return EndLoc; }
199 ARMCC::CondCodes getCondCode() const {
200 assert(Kind == CondCode && "Invalid access!");
204 StringRef getToken() const {
205 assert(Kind == Token && "Invalid access!");
206 return StringRef(Tok.Data, Tok.Length);
209 unsigned getReg() const {
210 assert(Kind == Register && "Invalid access!");
214 std::pair<unsigned, unsigned> getRegList() const {
215 assert(Kind == RegisterList && "Invalid access!");
216 return std::make_pair(RegList.RegStart, RegList.Number);
219 const MCExpr *getImm() const {
220 assert(Kind == Immediate && "Invalid access!");
224 bool isCondCode() const { return Kind == CondCode; }
225 bool isImm() const { return Kind == Immediate; }
226 bool isReg() const { return Kind == Register; }
227 bool isRegList() const { return Kind == RegisterList; }
228 bool isToken() const { return Kind == Token; }
229 bool isMemory() const { return Kind == Memory; }
231 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
232 // Add as immediates when possible. Null MCExpr = 0.
234 Inst.addOperand(MCOperand::CreateImm(0));
235 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
236 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
238 Inst.addOperand(MCOperand::CreateExpr(Expr));
241 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
242 assert(N == 2 && "Invalid number of operands!");
243 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
244 // FIXME: What belongs here?
245 Inst.addOperand(MCOperand::CreateReg(0));
248 void addRegOperands(MCInst &Inst, unsigned N) const {
249 assert(N == 1 && "Invalid number of operands!");
250 Inst.addOperand(MCOperand::CreateReg(getReg()));
253 void addImmOperands(MCInst &Inst, unsigned N) const {
254 assert(N == 1 && "Invalid number of operands!");
255 addExpr(Inst, getImm());
259 bool isMemMode5() const {
260 if (!isMemory() || Mem.OffsetIsReg || Mem.OffsetRegShifted ||
261 Mem.Writeback || Mem.Negative)
263 // If there is an offset expression, make sure it's valid.
266 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
269 // The offset must be a multiple of 4 in the range 0-1020.
270 int64_t Value = CE->getValue();
271 return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020);
274 void addMemMode5Operands(MCInst &Inst, unsigned N) const {
275 assert(N == 2 && isMemMode5() && "Invalid number of operands!");
277 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
278 assert(!Mem.OffsetIsReg && "Invalid mode 5 operand");
280 // FIXME: #-0 is encoded differently than #0. Does the parser preserve
283 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Mem.Offset);
284 assert(CE && "Non-constant mode 5 offset operand!");
286 // The MCInst offset operand doesn't include the low two bits (like
287 // the instruction encoding).
288 int64_t Offset = CE->getValue() / 4;
290 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add,
293 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub,
296 Inst.addOperand(MCOperand::CreateImm(0));
300 virtual void dump(raw_ostream &OS) const;
302 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
303 ARMOperand *Op = new ARMOperand(CondCode);
310 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
311 ARMOperand *Op = new ARMOperand(Token);
312 Op->Tok.Data = Str.data();
313 Op->Tok.Length = Str.size();
319 static ARMOperand *CreateReg(unsigned RegNum, bool Writeback, SMLoc S,
321 ARMOperand *Op = new ARMOperand(Register);
322 Op->Reg.RegNum = RegNum;
323 Op->Reg.Writeback = Writeback;
329 static ARMOperand *CreateRegList(unsigned RegStart, unsigned Number,
331 ARMOperand *Op = new ARMOperand(RegisterList);
332 Op->RegList.RegStart = RegStart;
333 Op->RegList.Number = Number;
339 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
340 ARMOperand *Op = new ARMOperand(Immediate);
347 static ARMOperand *CreateMem(unsigned BaseRegNum, bool OffsetIsReg,
348 const MCExpr *Offset, unsigned OffsetRegNum,
349 bool OffsetRegShifted, enum ShiftType ShiftType,
350 const MCExpr *ShiftAmount, bool Preindexed,
351 bool Postindexed, bool Negative, bool Writeback,
353 ARMOperand *Op = new ARMOperand(Memory);
354 Op->Mem.BaseRegNum = BaseRegNum;
355 Op->Mem.OffsetIsReg = OffsetIsReg;
356 Op->Mem.Offset = Offset;
357 Op->Mem.OffsetRegNum = OffsetRegNum;
358 Op->Mem.OffsetRegShifted = OffsetRegShifted;
359 Op->Mem.ShiftType = ShiftType;
360 Op->Mem.ShiftAmount = ShiftAmount;
361 Op->Mem.Preindexed = Preindexed;
362 Op->Mem.Postindexed = Postindexed;
363 Op->Mem.Negative = Negative;
364 Op->Mem.Writeback = Writeback;
372 ARMOperand(KindTy K) : Kind(K) {}
375 } // end anonymous namespace.
377 void ARMOperand::dump(raw_ostream &OS) const {
380 OS << ARMCondCodeToString(getCondCode());
389 OS << "<register " << getReg() << ">";
392 OS << "<register_list ";
393 std::pair<unsigned, unsigned> List = getRegList();
394 unsigned RegEnd = List.first + List.second;
396 for (unsigned Idx = List.first; Idx < RegEnd; ) {
398 if (++Idx < RegEnd) OS << ", ";
405 OS << "'" << getToken() << "'";
410 /// @name Auto-generated Match Functions
413 static unsigned MatchRegisterName(StringRef Name);
417 /// Try to parse a register name. The token must be an Identifier when called,
418 /// and if it is a register name the token is eaten and the register number is
419 /// returned. Otherwise return -1.
421 int ARMAsmParser::TryParseRegister() {
422 const AsmToken &Tok = Parser.getTok();
423 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
425 // FIXME: Validate register for the current architecture; we have to do
426 // validation later, so maybe there is no need for this here.
427 unsigned RegNum = MatchRegisterName(Tok.getString());
430 Parser.Lex(); // Eat identifier token.
435 /// Try to parse a register name. The token must be an Identifier when called,
436 /// and if it is a register name the token is eaten and the register number is
437 /// returned. Otherwise return -1.
439 /// TODO this is likely to change to allow different register types and or to
440 /// parse for a specific register type.
441 ARMOperand *ARMAsmParser::TryParseRegisterWithWriteBack() {
442 SMLoc S = Parser.getTok().getLoc();
443 int RegNo = TryParseRegister();
444 if (RegNo == -1) return 0;
446 SMLoc E = Parser.getTok().getLoc();
448 bool Writeback = false;
449 const AsmToken &ExclaimTok = Parser.getTok();
450 if (ExclaimTok.is(AsmToken::Exclaim)) {
451 E = ExclaimTok.getLoc();
453 Parser.Lex(); // Eat exclaim token
456 return ARMOperand::CreateReg(RegNo, Writeback, S, E);
459 /// Parse a register list, return it if successful else return null. The first
460 /// token must be a '{' when called.
461 ARMOperand *ARMAsmParser::ParseRegisterList() {
463 assert(Parser.getTok().is(AsmToken::LCurly) &&
464 "Token is not a Left Curly Brace");
465 S = Parser.getTok().getLoc();
466 Parser.Lex(); // Eat left curly brace token.
468 const AsmToken &RegTok = Parser.getTok();
469 SMLoc RegLoc = RegTok.getLoc();
470 if (RegTok.isNot(AsmToken::Identifier)) {
471 Error(RegLoc, "register expected");
474 int RegNum = TryParseRegister();
476 Error(RegLoc, "register expected");
480 unsigned RegList = 1 << RegNum;
482 int HighRegNum = RegNum;
483 // TODO ranges like "{Rn-Rm}"
484 while (Parser.getTok().is(AsmToken::Comma)) {
485 Parser.Lex(); // Eat comma token.
487 const AsmToken &RegTok = Parser.getTok();
488 SMLoc RegLoc = RegTok.getLoc();
489 if (RegTok.isNot(AsmToken::Identifier)) {
490 Error(RegLoc, "register expected");
493 int RegNum = TryParseRegister();
495 Error(RegLoc, "register expected");
499 if (RegList & (1 << RegNum))
500 Warning(RegLoc, "register duplicated in register list");
501 else if (RegNum <= HighRegNum)
502 Warning(RegLoc, "register not in ascending order in register list");
503 RegList |= 1 << RegNum;
506 const AsmToken &RCurlyTok = Parser.getTok();
507 if (RCurlyTok.isNot(AsmToken::RCurly)) {
508 Error(RCurlyTok.getLoc(), "'}' expected");
511 E = RCurlyTok.getLoc();
512 Parser.Lex(); // Eat left curly brace token.
514 // FIXME: Need to return an operand!
515 Error(E, "FIXME: register list parsing not implemented");
519 /// Parse an arm memory expression, return false if successful else return true
520 /// or an error. The first token must be a '[' when called.
521 /// TODO Only preindexing and postindexing addressing are started, unindexed
522 /// with option, etc are still to do.
523 ARMOperand *ARMAsmParser::ParseMemory() {
525 assert(Parser.getTok().is(AsmToken::LBrac) &&
526 "Token is not a Left Bracket");
527 S = Parser.getTok().getLoc();
528 Parser.Lex(); // Eat left bracket token.
530 const AsmToken &BaseRegTok = Parser.getTok();
531 if (BaseRegTok.isNot(AsmToken::Identifier)) {
532 Error(BaseRegTok.getLoc(), "register expected");
535 int BaseRegNum = TryParseRegister();
536 if (BaseRegNum == -1) {
537 Error(BaseRegTok.getLoc(), "register expected");
541 bool Preindexed = false;
542 bool Postindexed = false;
543 bool OffsetIsReg = false;
544 bool Negative = false;
545 bool Writeback = false;
547 // First look for preindexed address forms, that is after the "[Rn" we now
548 // have to see if the next token is a comma.
549 const AsmToken &Tok = Parser.getTok();
550 if (Tok.is(AsmToken::Comma)) {
552 Parser.Lex(); // Eat comma token.
554 bool OffsetRegShifted;
555 enum ShiftType ShiftType;
556 const MCExpr *ShiftAmount;
557 const MCExpr *Offset;
558 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
559 Offset, OffsetIsReg, OffsetRegNum, E))
561 const AsmToken &RBracTok = Parser.getTok();
562 if (RBracTok.isNot(AsmToken::RBrac)) {
563 Error(RBracTok.getLoc(), "']' expected");
566 E = RBracTok.getLoc();
567 Parser.Lex(); // Eat right bracket token.
569 const AsmToken &ExclaimTok = Parser.getTok();
570 if (ExclaimTok.is(AsmToken::Exclaim)) {
571 E = ExclaimTok.getLoc();
573 Parser.Lex(); // Eat exclaim token
575 return ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
576 OffsetRegShifted, ShiftType, ShiftAmount,
577 Preindexed, Postindexed, Negative, Writeback,
580 // The "[Rn" we have so far was not followed by a comma.
581 else if (Tok.is(AsmToken::RBrac)) {
582 // If there's anything other than the right brace, this is a post indexing
585 Parser.Lex(); // Eat right bracket token.
587 int OffsetRegNum = 0;
588 bool OffsetRegShifted = false;
589 enum ShiftType ShiftType;
590 const MCExpr *ShiftAmount;
591 const MCExpr *Offset = 0;
593 const AsmToken &NextTok = Parser.getTok();
594 if (NextTok.isNot(AsmToken::EndOfStatement)) {
597 if (NextTok.isNot(AsmToken::Comma)) {
598 Error(NextTok.getLoc(), "',' expected");
601 Parser.Lex(); // Eat comma token.
602 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
603 ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
608 return ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
609 OffsetRegShifted, ShiftType, ShiftAmount,
610 Preindexed, Postindexed, Negative, Writeback,
617 /// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
618 /// we will parse the following (were +/- means that a plus or minus is
623 /// we return false on success or an error otherwise.
624 bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
625 bool &OffsetRegShifted,
626 enum ShiftType &ShiftType,
627 const MCExpr *&ShiftAmount,
628 const MCExpr *&Offset,
633 OffsetRegShifted = false;
636 const AsmToken &NextTok = Parser.getTok();
637 E = NextTok.getLoc();
638 if (NextTok.is(AsmToken::Plus))
639 Parser.Lex(); // Eat plus token.
640 else if (NextTok.is(AsmToken::Minus)) {
642 Parser.Lex(); // Eat minus token
644 // See if there is a register following the "[Rn," or "[Rn]," we have so far.
645 const AsmToken &OffsetRegTok = Parser.getTok();
646 if (OffsetRegTok.is(AsmToken::Identifier)) {
647 SMLoc CurLoc = OffsetRegTok.getLoc();
648 OffsetRegNum = TryParseRegister();
649 if (OffsetRegNum != -1) {
655 // If we parsed a register as the offset then there can be a shift after that.
656 if (OffsetRegNum != -1) {
657 // Look for a comma then a shift
658 const AsmToken &Tok = Parser.getTok();
659 if (Tok.is(AsmToken::Comma)) {
660 Parser.Lex(); // Eat comma token.
662 const AsmToken &Tok = Parser.getTok();
663 if (ParseShift(ShiftType, ShiftAmount, E))
664 return Error(Tok.getLoc(), "shift expected");
665 OffsetRegShifted = true;
668 else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
669 // Look for #offset following the "[Rn," or "[Rn],"
670 const AsmToken &HashTok = Parser.getTok();
671 if (HashTok.isNot(AsmToken::Hash))
672 return Error(HashTok.getLoc(), "'#' expected");
674 Parser.Lex(); // Eat hash token.
676 if (getParser().ParseExpression(Offset))
678 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
683 /// ParseShift as one of these two:
684 /// ( lsl | lsr | asr | ror ) , # shift_amount
686 /// and returns true if it parses a shift otherwise it returns false.
687 bool ARMAsmParser::ParseShift(ShiftType &St, const MCExpr *&ShiftAmount,
689 const AsmToken &Tok = Parser.getTok();
690 if (Tok.isNot(AsmToken::Identifier))
692 StringRef ShiftName = Tok.getString();
693 if (ShiftName == "lsl" || ShiftName == "LSL")
695 else if (ShiftName == "lsr" || ShiftName == "LSR")
697 else if (ShiftName == "asr" || ShiftName == "ASR")
699 else if (ShiftName == "ror" || ShiftName == "ROR")
701 else if (ShiftName == "rrx" || ShiftName == "RRX")
705 Parser.Lex(); // Eat shift type token.
711 // Otherwise, there must be a '#' and a shift amount.
712 const AsmToken &HashTok = Parser.getTok();
713 if (HashTok.isNot(AsmToken::Hash))
714 return Error(HashTok.getLoc(), "'#' expected");
715 Parser.Lex(); // Eat hash token.
717 if (getParser().ParseExpression(ShiftAmount))
723 /// Parse a arm instruction operand. For now this parses the operand regardless
725 ARMOperand *ARMAsmParser::ParseOperand() {
728 switch (getLexer().getKind()) {
729 case AsmToken::Identifier:
730 if (ARMOperand *Op = TryParseRegisterWithWriteBack())
733 // This was not a register so parse other operands that start with an
734 // identifier (like labels) as expressions and create them as immediates.
736 S = Parser.getTok().getLoc();
737 if (getParser().ParseExpression(IdVal))
739 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
740 return ARMOperand::CreateImm(IdVal, S, E);
741 case AsmToken::LBrac:
742 return ParseMemory();
743 case AsmToken::LCurly:
744 return ParseRegisterList();
747 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
748 S = Parser.getTok().getLoc();
750 const MCExpr *ImmVal;
751 if (getParser().ParseExpression(ImmVal))
753 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
754 return ARMOperand::CreateImm(ImmVal, S, E);
756 Error(Parser.getTok().getLoc(), "unexpected token in operand");
761 /// Parse an arm instruction mnemonic followed by its operands.
762 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
763 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
764 // Create the leading tokens for the mnemonic, split by '.' characters.
765 size_t Start = 0, Next = Name.find('.');
766 StringRef Head = Name.slice(Start, Next);
768 // Determine the predicate, if any.
770 // FIXME: We need a way to check whether a prefix supports predication,
771 // otherwise we will end up with an ambiguity for instructions that happen to
772 // end with a predicate name.
773 // FIXME: Likewise, some arithmetic instructions have an 's' prefix which
774 // indicates to update the condition codes. Those instructions have an
775 // additional immediate operand which encodes the prefix as reg0 or CPSR.
776 // Just checking for a suffix of 's' definitely creates ambiguities; e.g,
777 // the SMMLS instruction.
778 unsigned CC = StringSwitch<unsigned>(Head.substr(Head.size()-2))
779 .Case("eq", ARMCC::EQ)
780 .Case("ne", ARMCC::NE)
781 .Case("hs", ARMCC::HS)
782 .Case("lo", ARMCC::LO)
783 .Case("mi", ARMCC::MI)
784 .Case("pl", ARMCC::PL)
785 .Case("vs", ARMCC::VS)
786 .Case("vc", ARMCC::VC)
787 .Case("hi", ARMCC::HI)
788 .Case("ls", ARMCC::LS)
789 .Case("ge", ARMCC::GE)
790 .Case("lt", ARMCC::LT)
791 .Case("gt", ARMCC::GT)
792 .Case("le", ARMCC::LE)
793 .Case("al", ARMCC::AL)
797 (CC == ARMCC::LS && (Head == "vmls" || Head == "vnmls"))) {
800 Head = Head.slice(0, Head.size() - 2);
803 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
804 // FIXME: Should only add this operand for predicated instructions
805 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), NameLoc));
807 // Add the remaining tokens in the mnemonic.
808 while (Next != StringRef::npos) {
810 Next = Name.find('.', Start + 1);
811 Head = Name.slice(Start, Next);
813 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
816 // Read the remaining operands.
817 if (getLexer().isNot(AsmToken::EndOfStatement)) {
818 // Read the first operand.
819 if (ARMOperand *Op = ParseOperand())
820 Operands.push_back(Op);
822 Parser.EatToEndOfStatement();
826 while (getLexer().is(AsmToken::Comma)) {
827 Parser.Lex(); // Eat the comma.
829 // Parse and remember the operand.
830 if (ARMOperand *Op = ParseOperand())
831 Operands.push_back(Op);
833 Parser.EatToEndOfStatement();
839 if (getLexer().isNot(AsmToken::EndOfStatement)) {
840 Parser.EatToEndOfStatement();
841 return TokError("unexpected token in argument list");
843 Parser.Lex(); // Consume the EndOfStatement
848 MatchAndEmitInstruction(SMLoc IDLoc,
849 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
853 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo)) {
855 Out.EmitInstruction(Inst);
858 case Match_MissingFeature:
859 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
861 case Match_InvalidOperand: {
862 SMLoc ErrorLoc = IDLoc;
863 if (ErrorInfo != ~0U) {
864 if (ErrorInfo >= Operands.size())
865 return Error(IDLoc, "too few operands for instruction");
867 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
868 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
871 return Error(ErrorLoc, "invalid operand for instruction");
873 case Match_MnemonicFail:
874 return Error(IDLoc, "unrecognized instruction mnemonic");
877 llvm_unreachable("Implement any new match types added!");
882 /// ParseDirective parses the arm specific directives
883 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
884 StringRef IDVal = DirectiveID.getIdentifier();
885 if (IDVal == ".word")
886 return ParseDirectiveWord(4, DirectiveID.getLoc());
887 else if (IDVal == ".thumb")
888 return ParseDirectiveThumb(DirectiveID.getLoc());
889 else if (IDVal == ".thumb_func")
890 return ParseDirectiveThumbFunc(DirectiveID.getLoc());
891 else if (IDVal == ".code")
892 return ParseDirectiveCode(DirectiveID.getLoc());
893 else if (IDVal == ".syntax")
894 return ParseDirectiveSyntax(DirectiveID.getLoc());
898 /// ParseDirectiveWord
899 /// ::= .word [ expression (, expression)* ]
900 bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
901 if (getLexer().isNot(AsmToken::EndOfStatement)) {
904 if (getParser().ParseExpression(Value))
907 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
909 if (getLexer().is(AsmToken::EndOfStatement))
912 // FIXME: Improve diagnostic.
913 if (getLexer().isNot(AsmToken::Comma))
914 return Error(L, "unexpected token in directive");
923 /// ParseDirectiveThumb
925 bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
926 if (getLexer().isNot(AsmToken::EndOfStatement))
927 return Error(L, "unexpected token in directive");
930 // TODO: set thumb mode
931 // TODO: tell the MC streamer the mode
932 // getParser().getStreamer().Emit???();
936 /// ParseDirectiveThumbFunc
937 /// ::= .thumbfunc symbol_name
938 bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
939 const AsmToken &Tok = Parser.getTok();
940 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
941 return Error(L, "unexpected token in .thumb_func directive");
942 StringRef Name = Tok.getString();
943 Parser.Lex(); // Consume the identifier token.
944 if (getLexer().isNot(AsmToken::EndOfStatement))
945 return Error(L, "unexpected token in directive");
948 // Mark symbol as a thumb symbol.
949 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
950 getParser().getStreamer().EmitThumbFunc(Func);
954 /// ParseDirectiveSyntax
955 /// ::= .syntax unified | divided
956 bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
957 const AsmToken &Tok = Parser.getTok();
958 if (Tok.isNot(AsmToken::Identifier))
959 return Error(L, "unexpected token in .syntax directive");
960 StringRef Mode = Tok.getString();
961 if (Mode == "unified" || Mode == "UNIFIED")
963 else if (Mode == "divided" || Mode == "DIVIDED")
966 return Error(L, "unrecognized syntax mode in .syntax directive");
968 if (getLexer().isNot(AsmToken::EndOfStatement))
969 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
972 // TODO tell the MC streamer the mode
973 // getParser().getStreamer().Emit???();
977 /// ParseDirectiveCode
978 /// ::= .code 16 | 32
979 bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
980 const AsmToken &Tok = Parser.getTok();
981 if (Tok.isNot(AsmToken::Integer))
982 return Error(L, "unexpected token in .code directive");
983 int64_t Val = Parser.getTok().getIntVal();
989 return Error(L, "invalid operand to .code directive");
991 if (getLexer().isNot(AsmToken::EndOfStatement))
992 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
996 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
998 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
1003 extern "C" void LLVMInitializeARMAsmLexer();
1005 /// Force static initialization.
1006 extern "C" void LLVMInitializeARMAsmParser() {
1007 RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
1008 RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
1009 LLVMInitializeARMAsmLexer();
1012 #define GET_REGISTER_MATCHER
1013 #define GET_MATCHER_IMPLEMENTATION
1014 #include "ARMGenAsmMatcher.inc"