1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMBaseInfo.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMMCExpr.h"
13 #include "llvm/MC/MCParser/MCAsmLexer.h"
14 #include "llvm/MC/MCParser/MCAsmParser.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCAsmInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCTargetAsmParser.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/SourceMgr.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/ADT/BitVector.h"
30 #include "llvm/ADT/OwningPtr.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/StringSwitch.h"
34 #include "llvm/ADT/Twine.h"
42 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
44 class ARMAsmParser : public MCTargetAsmParser {
47 const MCRegisterInfo *MRI;
49 // Map of register aliases registers via the .req directive.
50 StringMap<unsigned> RegisterReqs;
53 ARMCC::CondCodes Cond; // Condition for IT block.
54 unsigned Mask:4; // Condition mask for instructions.
55 // Starting at first 1 (from lsb).
56 // '1' condition as indicated in IT.
57 // '0' inverse of condition (else).
58 // Count of instructions in IT block is
59 // 4 - trailingzeroes(mask)
61 bool FirstCond; // Explicit flag for when we're parsing the
62 // First instruction in the IT block. It's
63 // implied in the mask, so needs special
66 unsigned CurPosition; // Current position in parsing of IT
67 // block. In range [0,3]. Initialized
68 // according to count of instructions in block.
69 // ~0U if no active IT block.
71 bool inITBlock() { return ITState.CurPosition != ~0U;}
72 void forwardITPosition() {
73 if (!inITBlock()) return;
74 // Move to the next instruction in the IT block, if there is one. If not,
75 // mark the block as done.
76 unsigned TZ = CountTrailingZeros_32(ITState.Mask);
77 if (++ITState.CurPosition == 5 - TZ)
78 ITState.CurPosition = ~0U; // Done with the IT block after this.
82 MCAsmParser &getParser() const { return Parser; }
83 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
85 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
86 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
88 int tryParseRegister();
89 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
90 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
91 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
92 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
93 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
94 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
95 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
96 unsigned &ShiftAmount);
97 bool parseDirectiveWord(unsigned Size, SMLoc L);
98 bool parseDirectiveThumb(SMLoc L);
99 bool parseDirectiveARM(SMLoc L);
100 bool parseDirectiveThumbFunc(SMLoc L);
101 bool parseDirectiveCode(SMLoc L);
102 bool parseDirectiveSyntax(SMLoc L);
103 bool parseDirectiveReq(StringRef Name, SMLoc L);
104 bool parseDirectiveUnreq(SMLoc L);
105 bool parseDirectiveArch(SMLoc L);
106 bool parseDirectiveEabiAttr(SMLoc L);
108 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
109 bool &CarrySetting, unsigned &ProcessorIMod,
111 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
112 bool &CanAcceptPredicationCode);
114 bool isThumb() const {
115 // FIXME: Can tablegen auto-generate this?
116 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
118 bool isThumbOne() const {
119 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
121 bool isThumbTwo() const {
122 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
124 bool hasV6Ops() const {
125 return STI.getFeatureBits() & ARM::HasV6Ops;
127 bool hasV7Ops() const {
128 return STI.getFeatureBits() & ARM::HasV7Ops;
131 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
132 setAvailableFeatures(FB);
134 bool isMClass() const {
135 return STI.getFeatureBits() & ARM::FeatureMClass;
138 /// @name Auto-generated Match Functions
141 #define GET_ASSEMBLER_HEADER
142 #include "ARMGenAsmMatcher.inc"
146 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
147 OperandMatchResultTy parseCoprocNumOperand(
148 SmallVectorImpl<MCParsedAsmOperand*>&);
149 OperandMatchResultTy parseCoprocRegOperand(
150 SmallVectorImpl<MCParsedAsmOperand*>&);
151 OperandMatchResultTy parseCoprocOptionOperand(
152 SmallVectorImpl<MCParsedAsmOperand*>&);
153 OperandMatchResultTy parseMemBarrierOptOperand(
154 SmallVectorImpl<MCParsedAsmOperand*>&);
155 OperandMatchResultTy parseProcIFlagsOperand(
156 SmallVectorImpl<MCParsedAsmOperand*>&);
157 OperandMatchResultTy parseMSRMaskOperand(
158 SmallVectorImpl<MCParsedAsmOperand*>&);
159 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
160 StringRef Op, int Low, int High);
161 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
162 return parsePKHImm(O, "lsl", 0, 31);
164 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
165 return parsePKHImm(O, "asr", 1, 32);
167 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
168 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
169 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
170 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
171 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
172 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
173 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
174 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
175 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index);
177 // Asm Match Converter Methods
178 bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
179 const SmallVectorImpl<MCParsedAsmOperand*> &);
180 bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
181 const SmallVectorImpl<MCParsedAsmOperand*> &);
182 bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
183 const SmallVectorImpl<MCParsedAsmOperand*> &);
184 bool cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
185 const SmallVectorImpl<MCParsedAsmOperand*> &);
186 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
187 const SmallVectorImpl<MCParsedAsmOperand*> &);
188 bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
189 const SmallVectorImpl<MCParsedAsmOperand*> &);
190 bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
191 const SmallVectorImpl<MCParsedAsmOperand*> &);
192 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
193 const SmallVectorImpl<MCParsedAsmOperand*> &);
194 bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
195 const SmallVectorImpl<MCParsedAsmOperand*> &);
196 bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
197 const SmallVectorImpl<MCParsedAsmOperand*> &);
198 bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
199 const SmallVectorImpl<MCParsedAsmOperand*> &);
200 bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
201 const SmallVectorImpl<MCParsedAsmOperand*> &);
202 bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
203 const SmallVectorImpl<MCParsedAsmOperand*> &);
204 bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
205 const SmallVectorImpl<MCParsedAsmOperand*> &);
206 bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
207 const SmallVectorImpl<MCParsedAsmOperand*> &);
208 bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
209 const SmallVectorImpl<MCParsedAsmOperand*> &);
210 bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
211 const SmallVectorImpl<MCParsedAsmOperand*> &);
212 bool cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
213 const SmallVectorImpl<MCParsedAsmOperand*> &);
214 bool cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
215 const SmallVectorImpl<MCParsedAsmOperand*> &);
216 bool cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
217 const SmallVectorImpl<MCParsedAsmOperand*> &);
218 bool cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
219 const SmallVectorImpl<MCParsedAsmOperand*> &);
221 bool validateInstruction(MCInst &Inst,
222 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
223 bool processInstruction(MCInst &Inst,
224 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
225 bool shouldOmitCCOutOperand(StringRef Mnemonic,
226 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
229 enum ARMMatchResultTy {
230 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
231 Match_RequiresNotITBlock,
236 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
237 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
238 MCAsmParserExtension::Initialize(_Parser);
240 // Cache the MCRegisterInfo.
241 MRI = &getContext().getRegisterInfo();
243 // Initialize the set of available features.
244 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
246 // Not in an ITBlock to start with.
247 ITState.CurPosition = ~0U;
250 // Implementation of the MCTargetAsmParser interface:
251 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
252 bool ParseInstruction(StringRef Name, SMLoc NameLoc,
253 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
254 bool ParseDirective(AsmToken DirectiveID);
256 unsigned checkTargetMatchPredicate(MCInst &Inst);
258 bool MatchAndEmitInstruction(SMLoc IDLoc,
259 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
262 } // end anonymous namespace
266 /// ARMOperand - Instances of this class represent a parsed ARM machine
268 class ARMOperand : public MCParsedAsmOperand {
288 k_VectorListAllLanes,
294 k_BitfieldDescriptor,
298 SMLoc StartLoc, EndLoc;
299 SmallVector<unsigned, 8> Registers;
303 ARMCC::CondCodes Val;
323 ARM_PROC::IFlags Val;
339 // A vector register list is a sequential list of 1 to 4 registers.
355 /// Combined record for all forms of ARM address expressions.
358 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
360 const MCConstantExpr *OffsetImm; // Offset immediate value
361 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
362 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
363 unsigned ShiftImm; // shift for OffsetReg.
364 unsigned Alignment; // 0 = no alignment specified
365 // n = alignment in bytes (2, 4, 8, 16, or 32)
366 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
372 ARM_AM::ShiftOpc ShiftTy;
381 ARM_AM::ShiftOpc ShiftTy;
387 ARM_AM::ShiftOpc ShiftTy;
400 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
402 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
404 StartLoc = o.StartLoc;
421 case k_DPRRegisterList:
422 case k_SPRRegisterList:
423 Registers = o.Registers;
426 case k_VectorListAllLanes:
427 case k_VectorListIndexed:
428 VectorList = o.VectorList;
435 CoprocOption = o.CoprocOption;
440 case k_MemBarrierOpt:
446 case k_PostIndexRegister:
447 PostIdxReg = o.PostIdxReg;
455 case k_ShifterImmediate:
456 ShifterImm = o.ShifterImm;
458 case k_ShiftedRegister:
459 RegShiftedReg = o.RegShiftedReg;
461 case k_ShiftedImmediate:
462 RegShiftedImm = o.RegShiftedImm;
464 case k_RotateImmediate:
467 case k_BitfieldDescriptor:
468 Bitfield = o.Bitfield;
471 VectorIndex = o.VectorIndex;
476 /// getStartLoc - Get the location of the first token of this operand.
477 SMLoc getStartLoc() const { return StartLoc; }
478 /// getEndLoc - Get the location of the last token of this operand.
479 SMLoc getEndLoc() const { return EndLoc; }
481 ARMCC::CondCodes getCondCode() const {
482 assert(Kind == k_CondCode && "Invalid access!");
486 unsigned getCoproc() const {
487 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
491 StringRef getToken() const {
492 assert(Kind == k_Token && "Invalid access!");
493 return StringRef(Tok.Data, Tok.Length);
496 unsigned getReg() const {
497 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
501 const SmallVectorImpl<unsigned> &getRegList() const {
502 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
503 Kind == k_SPRRegisterList) && "Invalid access!");
507 const MCExpr *getImm() const {
508 assert(isImm() && "Invalid access!");
512 unsigned getVectorIndex() const {
513 assert(Kind == k_VectorIndex && "Invalid access!");
514 return VectorIndex.Val;
517 ARM_MB::MemBOpt getMemBarrierOpt() const {
518 assert(Kind == k_MemBarrierOpt && "Invalid access!");
522 ARM_PROC::IFlags getProcIFlags() const {
523 assert(Kind == k_ProcIFlags && "Invalid access!");
527 unsigned getMSRMask() const {
528 assert(Kind == k_MSRMask && "Invalid access!");
532 bool isCoprocNum() const { return Kind == k_CoprocNum; }
533 bool isCoprocReg() const { return Kind == k_CoprocReg; }
534 bool isCoprocOption() const { return Kind == k_CoprocOption; }
535 bool isCondCode() const { return Kind == k_CondCode; }
536 bool isCCOut() const { return Kind == k_CCOut; }
537 bool isITMask() const { return Kind == k_ITCondMask; }
538 bool isITCondCode() const { return Kind == k_CondCode; }
539 bool isImm() const { return Kind == k_Immediate; }
540 bool isFPImm() const {
541 if (!isImm()) return false;
542 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
543 if (!CE) return false;
544 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
547 bool isFBits16() const {
548 if (!isImm()) return false;
549 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
550 if (!CE) return false;
551 int64_t Value = CE->getValue();
552 return Value >= 0 && Value <= 16;
554 bool isFBits32() const {
555 if (!isImm()) return false;
556 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
557 if (!CE) return false;
558 int64_t Value = CE->getValue();
559 return Value >= 1 && Value <= 32;
561 bool isImm8s4() const {
562 if (!isImm()) return false;
563 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
564 if (!CE) return false;
565 int64_t Value = CE->getValue();
566 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
568 bool isImm0_1020s4() const {
569 if (!isImm()) return false;
570 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
571 if (!CE) return false;
572 int64_t Value = CE->getValue();
573 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
575 bool isImm0_508s4() const {
576 if (!isImm()) return false;
577 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
578 if (!CE) return false;
579 int64_t Value = CE->getValue();
580 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
582 bool isImm0_255() const {
583 if (!isImm()) return false;
584 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
585 if (!CE) return false;
586 int64_t Value = CE->getValue();
587 return Value >= 0 && Value < 256;
589 bool isImm0_1() const {
590 if (!isImm()) return false;
591 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
592 if (!CE) return false;
593 int64_t Value = CE->getValue();
594 return Value >= 0 && Value < 2;
596 bool isImm0_3() const {
597 if (!isImm()) return false;
598 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
599 if (!CE) return false;
600 int64_t Value = CE->getValue();
601 return Value >= 0 && Value < 4;
603 bool isImm0_7() const {
604 if (!isImm()) return false;
605 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
606 if (!CE) return false;
607 int64_t Value = CE->getValue();
608 return Value >= 0 && Value < 8;
610 bool isImm0_15() const {
611 if (!isImm()) return false;
612 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
613 if (!CE) return false;
614 int64_t Value = CE->getValue();
615 return Value >= 0 && Value < 16;
617 bool isImm0_31() const {
618 if (!isImm()) return false;
619 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
620 if (!CE) return false;
621 int64_t Value = CE->getValue();
622 return Value >= 0 && Value < 32;
624 bool isImm0_63() const {
625 if (!isImm()) return false;
626 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
627 if (!CE) return false;
628 int64_t Value = CE->getValue();
629 return Value >= 0 && Value < 64;
631 bool isImm8() const {
632 if (!isImm()) return false;
633 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
634 if (!CE) return false;
635 int64_t Value = CE->getValue();
638 bool isImm16() const {
639 if (!isImm()) return false;
640 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
641 if (!CE) return false;
642 int64_t Value = CE->getValue();
645 bool isImm32() const {
646 if (!isImm()) return false;
647 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
648 if (!CE) return false;
649 int64_t Value = CE->getValue();
652 bool isShrImm8() const {
653 if (!isImm()) return false;
654 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
655 if (!CE) return false;
656 int64_t Value = CE->getValue();
657 return Value > 0 && Value <= 8;
659 bool isShrImm16() const {
660 if (!isImm()) return false;
661 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
662 if (!CE) return false;
663 int64_t Value = CE->getValue();
664 return Value > 0 && Value <= 16;
666 bool isShrImm32() const {
667 if (!isImm()) return false;
668 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
669 if (!CE) return false;
670 int64_t Value = CE->getValue();
671 return Value > 0 && Value <= 32;
673 bool isShrImm64() const {
674 if (!isImm()) return false;
675 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
676 if (!CE) return false;
677 int64_t Value = CE->getValue();
678 return Value > 0 && Value <= 64;
680 bool isImm1_7() const {
681 if (!isImm()) return false;
682 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
683 if (!CE) return false;
684 int64_t Value = CE->getValue();
685 return Value > 0 && Value < 8;
687 bool isImm1_15() const {
688 if (!isImm()) return false;
689 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
690 if (!CE) return false;
691 int64_t Value = CE->getValue();
692 return Value > 0 && Value < 16;
694 bool isImm1_31() const {
695 if (!isImm()) return false;
696 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
697 if (!CE) return false;
698 int64_t Value = CE->getValue();
699 return Value > 0 && Value < 32;
701 bool isImm1_16() const {
702 if (!isImm()) return false;
703 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
704 if (!CE) return false;
705 int64_t Value = CE->getValue();
706 return Value > 0 && Value < 17;
708 bool isImm1_32() const {
709 if (!isImm()) return false;
710 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
711 if (!CE) return false;
712 int64_t Value = CE->getValue();
713 return Value > 0 && Value < 33;
715 bool isImm0_32() const {
716 if (!isImm()) return false;
717 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
718 if (!CE) return false;
719 int64_t Value = CE->getValue();
720 return Value >= 0 && Value < 33;
722 bool isImm0_65535() const {
723 if (!isImm()) return false;
724 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
725 if (!CE) return false;
726 int64_t Value = CE->getValue();
727 return Value >= 0 && Value < 65536;
729 bool isImm0_65535Expr() const {
730 if (!isImm()) return false;
731 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
732 // If it's not a constant expression, it'll generate a fixup and be
734 if (!CE) return true;
735 int64_t Value = CE->getValue();
736 return Value >= 0 && Value < 65536;
738 bool isImm24bit() const {
739 if (!isImm()) return false;
740 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
741 if (!CE) return false;
742 int64_t Value = CE->getValue();
743 return Value >= 0 && Value <= 0xffffff;
745 bool isImmThumbSR() const {
746 if (!isImm()) return false;
747 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
748 if (!CE) return false;
749 int64_t Value = CE->getValue();
750 return Value > 0 && Value < 33;
752 bool isPKHLSLImm() const {
753 if (!isImm()) return false;
754 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
755 if (!CE) return false;
756 int64_t Value = CE->getValue();
757 return Value >= 0 && Value < 32;
759 bool isPKHASRImm() const {
760 if (!isImm()) return false;
761 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
762 if (!CE) return false;
763 int64_t Value = CE->getValue();
764 return Value > 0 && Value <= 32;
766 bool isARMSOImm() const {
767 if (!isImm()) return false;
768 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
769 if (!CE) return false;
770 int64_t Value = CE->getValue();
771 return ARM_AM::getSOImmVal(Value) != -1;
773 bool isARMSOImmNot() const {
774 if (!isImm()) return false;
775 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
776 if (!CE) return false;
777 int64_t Value = CE->getValue();
778 return ARM_AM::getSOImmVal(~Value) != -1;
780 bool isARMSOImmNeg() const {
781 if (!isImm()) return false;
782 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
783 if (!CE) return false;
784 int64_t Value = CE->getValue();
785 // Negation must be representable as an so_imm and be non-zero.
786 return Value && ARM_AM::getSOImmVal(-Value) != -1;
788 bool isT2SOImm() const {
789 if (!isImm()) return false;
790 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
791 if (!CE) return false;
792 int64_t Value = CE->getValue();
793 return ARM_AM::getT2SOImmVal(Value) != -1;
795 bool isT2SOImmNot() const {
796 if (!isImm()) return false;
797 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
798 if (!CE) return false;
799 int64_t Value = CE->getValue();
800 return ARM_AM::getT2SOImmVal(~Value) != -1;
802 bool isT2SOImmNeg() const {
803 if (!isImm()) return false;
804 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
805 if (!CE) return false;
806 int64_t Value = CE->getValue();
807 // Negation must be representable as a t2_so_imm and be non-zero.
808 return Value && ARM_AM::getT2SOImmVal(-Value) != -1;
810 bool isSetEndImm() const {
811 if (!isImm()) return false;
812 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
813 if (!CE) return false;
814 int64_t Value = CE->getValue();
815 return Value == 1 || Value == 0;
817 bool isReg() const { return Kind == k_Register; }
818 bool isRegList() const { return Kind == k_RegisterList; }
819 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
820 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
821 bool isToken() const { return Kind == k_Token; }
822 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
823 bool isMemory() const { return Kind == k_Memory; }
824 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
825 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
826 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
827 bool isRotImm() const { return Kind == k_RotateImmediate; }
828 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
829 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
830 bool isPostIdxReg() const {
831 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
833 bool isMemNoOffset(bool alignOK = false) const {
836 // No offset of any kind.
837 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
838 (alignOK || Memory.Alignment == 0);
840 bool isMemPCRelImm12() const {
841 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
843 // Base register must be PC.
844 if (Memory.BaseRegNum != ARM::PC)
846 // Immediate offset in range [-4095, 4095].
847 if (!Memory.OffsetImm) return true;
848 int64_t Val = Memory.OffsetImm->getValue();
849 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
851 bool isAlignedMemory() const {
852 return isMemNoOffset(true);
854 bool isAddrMode2() const {
855 if (!isMemory() || Memory.Alignment != 0) return false;
856 // Check for register offset.
857 if (Memory.OffsetRegNum) return true;
858 // Immediate offset in range [-4095, 4095].
859 if (!Memory.OffsetImm) return true;
860 int64_t Val = Memory.OffsetImm->getValue();
861 return Val > -4096 && Val < 4096;
863 bool isAM2OffsetImm() const {
864 if (!isImm()) return false;
865 // Immediate offset in range [-4095, 4095].
866 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
867 if (!CE) return false;
868 int64_t Val = CE->getValue();
869 return Val > -4096 && Val < 4096;
871 bool isAddrMode3() const {
872 // If we have an immediate that's not a constant, treat it as a label
873 // reference needing a fixup. If it is a constant, it's something else
875 if (isImm() && !isa<MCConstantExpr>(getImm()))
877 if (!isMemory() || Memory.Alignment != 0) return false;
878 // No shifts are legal for AM3.
879 if (Memory.ShiftType != ARM_AM::no_shift) return false;
880 // Check for register offset.
881 if (Memory.OffsetRegNum) return true;
882 // Immediate offset in range [-255, 255].
883 if (!Memory.OffsetImm) return true;
884 int64_t Val = Memory.OffsetImm->getValue();
885 return Val > -256 && Val < 256;
887 bool isAM3Offset() const {
888 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
890 if (Kind == k_PostIndexRegister)
891 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
892 // Immediate offset in range [-255, 255].
893 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
894 if (!CE) return false;
895 int64_t Val = CE->getValue();
896 // Special case, #-0 is INT32_MIN.
897 return (Val > -256 && Val < 256) || Val == INT32_MIN;
899 bool isAddrMode5() const {
900 // If we have an immediate that's not a constant, treat it as a label
901 // reference needing a fixup. If it is a constant, it's something else
903 if (isImm() && !isa<MCConstantExpr>(getImm()))
905 if (!isMemory() || Memory.Alignment != 0) return false;
906 // Check for register offset.
907 if (Memory.OffsetRegNum) return false;
908 // Immediate offset in range [-1020, 1020] and a multiple of 4.
909 if (!Memory.OffsetImm) return true;
910 int64_t Val = Memory.OffsetImm->getValue();
911 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
914 bool isMemTBB() const {
915 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
916 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
920 bool isMemTBH() const {
921 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
922 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
923 Memory.Alignment != 0 )
927 bool isMemRegOffset() const {
928 if (!isMemory() || !Memory.OffsetRegNum || Memory.Alignment != 0)
932 bool isT2MemRegOffset() const {
933 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
934 Memory.Alignment != 0)
936 // Only lsl #{0, 1, 2, 3} allowed.
937 if (Memory.ShiftType == ARM_AM::no_shift)
939 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
943 bool isMemThumbRR() const {
944 // Thumb reg+reg addressing is simple. Just two registers, a base and
945 // an offset. No shifts, negations or any other complicating factors.
946 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
947 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
949 return isARMLowRegister(Memory.BaseRegNum) &&
950 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
952 bool isMemThumbRIs4() const {
953 if (!isMemory() || Memory.OffsetRegNum != 0 ||
954 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
956 // Immediate offset, multiple of 4 in range [0, 124].
957 if (!Memory.OffsetImm) return true;
958 int64_t Val = Memory.OffsetImm->getValue();
959 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
961 bool isMemThumbRIs2() const {
962 if (!isMemory() || Memory.OffsetRegNum != 0 ||
963 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
965 // Immediate offset, multiple of 4 in range [0, 62].
966 if (!Memory.OffsetImm) return true;
967 int64_t Val = Memory.OffsetImm->getValue();
968 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
970 bool isMemThumbRIs1() const {
971 if (!isMemory() || Memory.OffsetRegNum != 0 ||
972 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
974 // Immediate offset in range [0, 31].
975 if (!Memory.OffsetImm) return true;
976 int64_t Val = Memory.OffsetImm->getValue();
977 return Val >= 0 && Val <= 31;
979 bool isMemThumbSPI() const {
980 if (!isMemory() || Memory.OffsetRegNum != 0 ||
981 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
983 // Immediate offset, multiple of 4 in range [0, 1020].
984 if (!Memory.OffsetImm) return true;
985 int64_t Val = Memory.OffsetImm->getValue();
986 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
988 bool isMemImm8s4Offset() const {
989 // If we have an immediate that's not a constant, treat it as a label
990 // reference needing a fixup. If it is a constant, it's something else
992 if (isImm() && !isa<MCConstantExpr>(getImm()))
994 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
996 // Immediate offset a multiple of 4 in range [-1020, 1020].
997 if (!Memory.OffsetImm) return true;
998 int64_t Val = Memory.OffsetImm->getValue();
999 return Val >= -1020 && Val <= 1020 && (Val & 3) == 0;
1001 bool isMemImm0_1020s4Offset() const {
1002 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1004 // Immediate offset a multiple of 4 in range [0, 1020].
1005 if (!Memory.OffsetImm) return true;
1006 int64_t Val = Memory.OffsetImm->getValue();
1007 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1009 bool isMemImm8Offset() const {
1010 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1012 // Base reg of PC isn't allowed for these encodings.
1013 if (Memory.BaseRegNum == ARM::PC) return false;
1014 // Immediate offset in range [-255, 255].
1015 if (!Memory.OffsetImm) return true;
1016 int64_t Val = Memory.OffsetImm->getValue();
1017 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1019 bool isMemPosImm8Offset() const {
1020 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1022 // Immediate offset in range [0, 255].
1023 if (!Memory.OffsetImm) return true;
1024 int64_t Val = Memory.OffsetImm->getValue();
1025 return Val >= 0 && Val < 256;
1027 bool isMemNegImm8Offset() const {
1028 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1030 // Base reg of PC isn't allowed for these encodings.
1031 if (Memory.BaseRegNum == ARM::PC) return false;
1032 // Immediate offset in range [-255, -1].
1033 if (!Memory.OffsetImm) return false;
1034 int64_t Val = Memory.OffsetImm->getValue();
1035 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1037 bool isMemUImm12Offset() const {
1038 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1040 // Immediate offset in range [0, 4095].
1041 if (!Memory.OffsetImm) return true;
1042 int64_t Val = Memory.OffsetImm->getValue();
1043 return (Val >= 0 && Val < 4096);
1045 bool isMemImm12Offset() const {
1046 // If we have an immediate that's not a constant, treat it as a label
1047 // reference needing a fixup. If it is a constant, it's something else
1048 // and we reject it.
1049 if (isImm() && !isa<MCConstantExpr>(getImm()))
1052 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1054 // Immediate offset in range [-4095, 4095].
1055 if (!Memory.OffsetImm) return true;
1056 int64_t Val = Memory.OffsetImm->getValue();
1057 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1059 bool isPostIdxImm8() const {
1060 if (!isImm()) return false;
1061 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1062 if (!CE) return false;
1063 int64_t Val = CE->getValue();
1064 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1066 bool isPostIdxImm8s4() const {
1067 if (!isImm()) return false;
1068 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1069 if (!CE) return false;
1070 int64_t Val = CE->getValue();
1071 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1075 bool isMSRMask() const { return Kind == k_MSRMask; }
1076 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1079 bool isSingleSpacedVectorList() const {
1080 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1082 bool isDoubleSpacedVectorList() const {
1083 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1085 bool isVecListOneD() const {
1086 if (!isSingleSpacedVectorList()) return false;
1087 return VectorList.Count == 1;
1090 bool isVecListDPair() const {
1091 if (!isSingleSpacedVectorList()) return false;
1092 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1093 .contains(VectorList.RegNum));
1096 bool isVecListThreeD() const {
1097 if (!isSingleSpacedVectorList()) return false;
1098 return VectorList.Count == 3;
1101 bool isVecListFourD() const {
1102 if (!isSingleSpacedVectorList()) return false;
1103 return VectorList.Count == 4;
1106 bool isVecListDPairSpaced() const {
1107 if (isSingleSpacedVectorList()) return false;
1108 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1109 .contains(VectorList.RegNum));
1112 bool isVecListThreeQ() const {
1113 if (!isDoubleSpacedVectorList()) return false;
1114 return VectorList.Count == 3;
1117 bool isVecListFourQ() const {
1118 if (!isDoubleSpacedVectorList()) return false;
1119 return VectorList.Count == 4;
1122 bool isSingleSpacedVectorAllLanes() const {
1123 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1125 bool isDoubleSpacedVectorAllLanes() const {
1126 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1128 bool isVecListOneDAllLanes() const {
1129 if (!isSingleSpacedVectorAllLanes()) return false;
1130 return VectorList.Count == 1;
1133 bool isVecListDPairAllLanes() const {
1134 if (!isSingleSpacedVectorAllLanes()) return false;
1135 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1136 .contains(VectorList.RegNum));
1139 bool isVecListDPairSpacedAllLanes() const {
1140 if (!isDoubleSpacedVectorAllLanes()) return false;
1141 return VectorList.Count == 2;
1144 bool isVecListThreeDAllLanes() const {
1145 if (!isSingleSpacedVectorAllLanes()) return false;
1146 return VectorList.Count == 3;
1149 bool isVecListThreeQAllLanes() const {
1150 if (!isDoubleSpacedVectorAllLanes()) return false;
1151 return VectorList.Count == 3;
1154 bool isVecListFourDAllLanes() const {
1155 if (!isSingleSpacedVectorAllLanes()) return false;
1156 return VectorList.Count == 4;
1159 bool isVecListFourQAllLanes() const {
1160 if (!isDoubleSpacedVectorAllLanes()) return false;
1161 return VectorList.Count == 4;
1164 bool isSingleSpacedVectorIndexed() const {
1165 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1167 bool isDoubleSpacedVectorIndexed() const {
1168 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1170 bool isVecListOneDByteIndexed() const {
1171 if (!isSingleSpacedVectorIndexed()) return false;
1172 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1175 bool isVecListOneDHWordIndexed() const {
1176 if (!isSingleSpacedVectorIndexed()) return false;
1177 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1180 bool isVecListOneDWordIndexed() const {
1181 if (!isSingleSpacedVectorIndexed()) return false;
1182 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1185 bool isVecListTwoDByteIndexed() const {
1186 if (!isSingleSpacedVectorIndexed()) return false;
1187 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1190 bool isVecListTwoDHWordIndexed() const {
1191 if (!isSingleSpacedVectorIndexed()) return false;
1192 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1195 bool isVecListTwoQWordIndexed() const {
1196 if (!isDoubleSpacedVectorIndexed()) return false;
1197 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1200 bool isVecListTwoQHWordIndexed() const {
1201 if (!isDoubleSpacedVectorIndexed()) return false;
1202 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1205 bool isVecListTwoDWordIndexed() const {
1206 if (!isSingleSpacedVectorIndexed()) return false;
1207 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1210 bool isVecListThreeDByteIndexed() const {
1211 if (!isSingleSpacedVectorIndexed()) return false;
1212 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1215 bool isVecListThreeDHWordIndexed() const {
1216 if (!isSingleSpacedVectorIndexed()) return false;
1217 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1220 bool isVecListThreeQWordIndexed() const {
1221 if (!isDoubleSpacedVectorIndexed()) return false;
1222 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1225 bool isVecListThreeQHWordIndexed() const {
1226 if (!isDoubleSpacedVectorIndexed()) return false;
1227 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1230 bool isVecListThreeDWordIndexed() const {
1231 if (!isSingleSpacedVectorIndexed()) return false;
1232 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1235 bool isVecListFourDByteIndexed() const {
1236 if (!isSingleSpacedVectorIndexed()) return false;
1237 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1240 bool isVecListFourDHWordIndexed() const {
1241 if (!isSingleSpacedVectorIndexed()) return false;
1242 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1245 bool isVecListFourQWordIndexed() const {
1246 if (!isDoubleSpacedVectorIndexed()) return false;
1247 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1250 bool isVecListFourQHWordIndexed() const {
1251 if (!isDoubleSpacedVectorIndexed()) return false;
1252 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1255 bool isVecListFourDWordIndexed() const {
1256 if (!isSingleSpacedVectorIndexed()) return false;
1257 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1260 bool isVectorIndex8() const {
1261 if (Kind != k_VectorIndex) return false;
1262 return VectorIndex.Val < 8;
1264 bool isVectorIndex16() const {
1265 if (Kind != k_VectorIndex) return false;
1266 return VectorIndex.Val < 4;
1268 bool isVectorIndex32() const {
1269 if (Kind != k_VectorIndex) return false;
1270 return VectorIndex.Val < 2;
1273 bool isNEONi8splat() const {
1274 if (!isImm()) return false;
1275 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1276 // Must be a constant.
1277 if (!CE) return false;
1278 int64_t Value = CE->getValue();
1279 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1281 return Value >= 0 && Value < 256;
1284 bool isNEONi16splat() const {
1285 if (!isImm()) return false;
1286 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1287 // Must be a constant.
1288 if (!CE) return false;
1289 int64_t Value = CE->getValue();
1290 // i16 value in the range [0,255] or [0x0100, 0xff00]
1291 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1294 bool isNEONi32splat() const {
1295 if (!isImm()) return false;
1296 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1297 // Must be a constant.
1298 if (!CE) return false;
1299 int64_t Value = CE->getValue();
1300 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1301 return (Value >= 0 && Value < 256) ||
1302 (Value >= 0x0100 && Value <= 0xff00) ||
1303 (Value >= 0x010000 && Value <= 0xff0000) ||
1304 (Value >= 0x01000000 && Value <= 0xff000000);
1307 bool isNEONi32vmov() const {
1308 if (!isImm()) return false;
1309 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1310 // Must be a constant.
1311 if (!CE) return false;
1312 int64_t Value = CE->getValue();
1313 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1314 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1315 return (Value >= 0 && Value < 256) ||
1316 (Value >= 0x0100 && Value <= 0xff00) ||
1317 (Value >= 0x010000 && Value <= 0xff0000) ||
1318 (Value >= 0x01000000 && Value <= 0xff000000) ||
1319 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1320 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1322 bool isNEONi32vmovNeg() const {
1323 if (!isImm()) return false;
1324 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1325 // Must be a constant.
1326 if (!CE) return false;
1327 int64_t Value = ~CE->getValue();
1328 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1329 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1330 return (Value >= 0 && Value < 256) ||
1331 (Value >= 0x0100 && Value <= 0xff00) ||
1332 (Value >= 0x010000 && Value <= 0xff0000) ||
1333 (Value >= 0x01000000 && Value <= 0xff000000) ||
1334 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1335 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1338 bool isNEONi64splat() const {
1339 if (!isImm()) return false;
1340 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1341 // Must be a constant.
1342 if (!CE) return false;
1343 uint64_t Value = CE->getValue();
1344 // i64 value with each byte being either 0 or 0xff.
1345 for (unsigned i = 0; i < 8; ++i)
1346 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1350 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1351 // Add as immediates when possible. Null MCExpr = 0.
1353 Inst.addOperand(MCOperand::CreateImm(0));
1354 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1355 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1357 Inst.addOperand(MCOperand::CreateExpr(Expr));
1360 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1361 assert(N == 2 && "Invalid number of operands!");
1362 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1363 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1364 Inst.addOperand(MCOperand::CreateReg(RegNum));
1367 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1368 assert(N == 1 && "Invalid number of operands!");
1369 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1372 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1373 assert(N == 1 && "Invalid number of operands!");
1374 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1377 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1378 assert(N == 1 && "Invalid number of operands!");
1379 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1382 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1383 assert(N == 1 && "Invalid number of operands!");
1384 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1387 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1388 assert(N == 1 && "Invalid number of operands!");
1389 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1392 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1393 assert(N == 1 && "Invalid number of operands!");
1394 Inst.addOperand(MCOperand::CreateReg(getReg()));
1397 void addRegOperands(MCInst &Inst, unsigned N) const {
1398 assert(N == 1 && "Invalid number of operands!");
1399 Inst.addOperand(MCOperand::CreateReg(getReg()));
1402 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1403 assert(N == 3 && "Invalid number of operands!");
1404 assert(isRegShiftedReg() &&
1405 "addRegShiftedRegOperands() on non RegShiftedReg!");
1406 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1407 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1408 Inst.addOperand(MCOperand::CreateImm(
1409 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1412 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1413 assert(N == 2 && "Invalid number of operands!");
1414 assert(isRegShiftedImm() &&
1415 "addRegShiftedImmOperands() on non RegShiftedImm!");
1416 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1417 Inst.addOperand(MCOperand::CreateImm(
1418 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
1421 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1422 assert(N == 1 && "Invalid number of operands!");
1423 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1427 void addRegListOperands(MCInst &Inst, unsigned N) const {
1428 assert(N == 1 && "Invalid number of operands!");
1429 const SmallVectorImpl<unsigned> &RegList = getRegList();
1430 for (SmallVectorImpl<unsigned>::const_iterator
1431 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1432 Inst.addOperand(MCOperand::CreateReg(*I));
1435 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1436 addRegListOperands(Inst, N);
1439 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1440 addRegListOperands(Inst, N);
1443 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1444 assert(N == 1 && "Invalid number of operands!");
1445 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1446 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1449 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1450 assert(N == 1 && "Invalid number of operands!");
1451 // Munge the lsb/width into a bitfield mask.
1452 unsigned lsb = Bitfield.LSB;
1453 unsigned width = Bitfield.Width;
1454 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1455 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1456 (32 - (lsb + width)));
1457 Inst.addOperand(MCOperand::CreateImm(Mask));
1460 void addImmOperands(MCInst &Inst, unsigned N) const {
1461 assert(N == 1 && "Invalid number of operands!");
1462 addExpr(Inst, getImm());
1465 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1466 assert(N == 1 && "Invalid number of operands!");
1467 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1468 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1471 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1472 assert(N == 1 && "Invalid number of operands!");
1473 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1474 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1477 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1478 assert(N == 1 && "Invalid number of operands!");
1479 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1480 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1481 Inst.addOperand(MCOperand::CreateImm(Val));
1484 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1485 assert(N == 1 && "Invalid number of operands!");
1486 // FIXME: We really want to scale the value here, but the LDRD/STRD
1487 // instruction don't encode operands that way yet.
1488 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1489 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1492 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1493 assert(N == 1 && "Invalid number of operands!");
1494 // The immediate is scaled by four in the encoding and is stored
1495 // in the MCInst as such. Lop off the low two bits here.
1496 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1497 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1500 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1501 assert(N == 1 && "Invalid number of operands!");
1502 // The immediate is scaled by four in the encoding and is stored
1503 // in the MCInst as such. Lop off the low two bits here.
1504 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1505 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1508 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1509 assert(N == 1 && "Invalid number of operands!");
1510 // The constant encodes as the immediate-1, and we store in the instruction
1511 // the bits as encoded, so subtract off one here.
1512 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1513 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1516 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1517 assert(N == 1 && "Invalid number of operands!");
1518 // The constant encodes as the immediate-1, and we store in the instruction
1519 // the bits as encoded, so subtract off one here.
1520 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1521 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1524 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1525 assert(N == 1 && "Invalid number of operands!");
1526 // The constant encodes as the immediate, except for 32, which encodes as
1528 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1529 unsigned Imm = CE->getValue();
1530 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1533 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1534 assert(N == 1 && "Invalid number of operands!");
1535 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1536 // the instruction as well.
1537 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1538 int Val = CE->getValue();
1539 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1542 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1543 assert(N == 1 && "Invalid number of operands!");
1544 // The operand is actually a t2_so_imm, but we have its bitwise
1545 // negation in the assembly source, so twiddle it here.
1546 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1547 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1550 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1551 assert(N == 1 && "Invalid number of operands!");
1552 // The operand is actually a t2_so_imm, but we have its
1553 // negation in the assembly source, so twiddle it here.
1554 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1555 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1558 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1559 assert(N == 1 && "Invalid number of operands!");
1560 // The operand is actually a so_imm, but we have its bitwise
1561 // negation in the assembly source, so twiddle it here.
1562 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1563 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1566 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1567 assert(N == 1 && "Invalid number of operands!");
1568 // The operand is actually a so_imm, but we have its
1569 // negation in the assembly source, so twiddle it here.
1570 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1571 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1574 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1575 assert(N == 1 && "Invalid number of operands!");
1576 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1579 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1580 assert(N == 1 && "Invalid number of operands!");
1581 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1584 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1585 assert(N == 1 && "Invalid number of operands!");
1586 int32_t Imm = Memory.OffsetImm->getValue();
1587 // FIXME: Handle #-0
1588 if (Imm == INT32_MIN) Imm = 0;
1589 Inst.addOperand(MCOperand::CreateImm(Imm));
1592 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1593 assert(N == 2 && "Invalid number of operands!");
1594 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1595 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1598 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1599 assert(N == 3 && "Invalid number of operands!");
1600 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1601 if (!Memory.OffsetRegNum) {
1602 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1603 // Special case for #-0
1604 if (Val == INT32_MIN) Val = 0;
1605 if (Val < 0) Val = -Val;
1606 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1608 // For register offset, we encode the shift type and negation flag
1610 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1611 Memory.ShiftImm, Memory.ShiftType);
1613 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1614 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1615 Inst.addOperand(MCOperand::CreateImm(Val));
1618 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1619 assert(N == 2 && "Invalid number of operands!");
1620 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1621 assert(CE && "non-constant AM2OffsetImm operand!");
1622 int32_t Val = CE->getValue();
1623 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1624 // Special case for #-0
1625 if (Val == INT32_MIN) Val = 0;
1626 if (Val < 0) Val = -Val;
1627 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1628 Inst.addOperand(MCOperand::CreateReg(0));
1629 Inst.addOperand(MCOperand::CreateImm(Val));
1632 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1633 assert(N == 3 && "Invalid number of operands!");
1634 // If we have an immediate that's not a constant, treat it as a label
1635 // reference needing a fixup. If it is a constant, it's something else
1636 // and we reject it.
1638 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1639 Inst.addOperand(MCOperand::CreateReg(0));
1640 Inst.addOperand(MCOperand::CreateImm(0));
1644 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1645 if (!Memory.OffsetRegNum) {
1646 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1647 // Special case for #-0
1648 if (Val == INT32_MIN) Val = 0;
1649 if (Val < 0) Val = -Val;
1650 Val = ARM_AM::getAM3Opc(AddSub, Val);
1652 // For register offset, we encode the shift type and negation flag
1654 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1656 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1657 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1658 Inst.addOperand(MCOperand::CreateImm(Val));
1661 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1662 assert(N == 2 && "Invalid number of operands!");
1663 if (Kind == k_PostIndexRegister) {
1665 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1666 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1667 Inst.addOperand(MCOperand::CreateImm(Val));
1672 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1673 int32_t Val = CE->getValue();
1674 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1675 // Special case for #-0
1676 if (Val == INT32_MIN) Val = 0;
1677 if (Val < 0) Val = -Val;
1678 Val = ARM_AM::getAM3Opc(AddSub, Val);
1679 Inst.addOperand(MCOperand::CreateReg(0));
1680 Inst.addOperand(MCOperand::CreateImm(Val));
1683 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1684 assert(N == 2 && "Invalid number of operands!");
1685 // If we have an immediate that's not a constant, treat it as a label
1686 // reference needing a fixup. If it is a constant, it's something else
1687 // and we reject it.
1689 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1690 Inst.addOperand(MCOperand::CreateImm(0));
1694 // The lower two bits are always zero and as such are not encoded.
1695 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1696 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1697 // Special case for #-0
1698 if (Val == INT32_MIN) Val = 0;
1699 if (Val < 0) Val = -Val;
1700 Val = ARM_AM::getAM5Opc(AddSub, Val);
1701 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1702 Inst.addOperand(MCOperand::CreateImm(Val));
1705 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1706 assert(N == 2 && "Invalid number of operands!");
1707 // If we have an immediate that's not a constant, treat it as a label
1708 // reference needing a fixup. If it is a constant, it's something else
1709 // and we reject it.
1711 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1712 Inst.addOperand(MCOperand::CreateImm(0));
1716 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1717 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1718 Inst.addOperand(MCOperand::CreateImm(Val));
1721 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1722 assert(N == 2 && "Invalid number of operands!");
1723 // The lower two bits are always zero and as such are not encoded.
1724 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1725 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1726 Inst.addOperand(MCOperand::CreateImm(Val));
1729 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1730 assert(N == 2 && "Invalid number of operands!");
1731 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1732 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1733 Inst.addOperand(MCOperand::CreateImm(Val));
1736 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1737 addMemImm8OffsetOperands(Inst, N);
1740 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1741 addMemImm8OffsetOperands(Inst, N);
1744 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1745 assert(N == 2 && "Invalid number of operands!");
1746 // If this is an immediate, it's a label reference.
1748 addExpr(Inst, getImm());
1749 Inst.addOperand(MCOperand::CreateImm(0));
1753 // Otherwise, it's a normal memory reg+offset.
1754 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1755 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1756 Inst.addOperand(MCOperand::CreateImm(Val));
1759 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1760 assert(N == 2 && "Invalid number of operands!");
1761 // If this is an immediate, it's a label reference.
1763 addExpr(Inst, getImm());
1764 Inst.addOperand(MCOperand::CreateImm(0));
1768 // Otherwise, it's a normal memory reg+offset.
1769 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1770 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1771 Inst.addOperand(MCOperand::CreateImm(Val));
1774 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1775 assert(N == 2 && "Invalid number of operands!");
1776 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1777 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1780 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
1781 assert(N == 2 && "Invalid number of operands!");
1782 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1783 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1786 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1787 assert(N == 3 && "Invalid number of operands!");
1789 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1790 Memory.ShiftImm, Memory.ShiftType);
1791 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1792 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1793 Inst.addOperand(MCOperand::CreateImm(Val));
1796 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1797 assert(N == 3 && "Invalid number of operands!");
1798 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1799 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1800 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
1803 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1804 assert(N == 2 && "Invalid number of operands!");
1805 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1806 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1809 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1810 assert(N == 2 && "Invalid number of operands!");
1811 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1812 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1813 Inst.addOperand(MCOperand::CreateImm(Val));
1816 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1817 assert(N == 2 && "Invalid number of operands!");
1818 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
1819 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1820 Inst.addOperand(MCOperand::CreateImm(Val));
1823 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1824 assert(N == 2 && "Invalid number of operands!");
1825 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
1826 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1827 Inst.addOperand(MCOperand::CreateImm(Val));
1830 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1831 assert(N == 2 && "Invalid number of operands!");
1832 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1833 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1834 Inst.addOperand(MCOperand::CreateImm(Val));
1837 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1838 assert(N == 1 && "Invalid number of operands!");
1839 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1840 assert(CE && "non-constant post-idx-imm8 operand!");
1841 int Imm = CE->getValue();
1842 bool isAdd = Imm >= 0;
1843 if (Imm == INT32_MIN) Imm = 0;
1844 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1845 Inst.addOperand(MCOperand::CreateImm(Imm));
1848 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
1849 assert(N == 1 && "Invalid number of operands!");
1850 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1851 assert(CE && "non-constant post-idx-imm8s4 operand!");
1852 int Imm = CE->getValue();
1853 bool isAdd = Imm >= 0;
1854 if (Imm == INT32_MIN) Imm = 0;
1855 // Immediate is scaled by 4.
1856 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
1857 Inst.addOperand(MCOperand::CreateImm(Imm));
1860 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1861 assert(N == 2 && "Invalid number of operands!");
1862 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1863 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1866 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1867 assert(N == 2 && "Invalid number of operands!");
1868 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1869 // The sign, shift type, and shift amount are encoded in a single operand
1870 // using the AM2 encoding helpers.
1871 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1872 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1873 PostIdxReg.ShiftTy);
1874 Inst.addOperand(MCOperand::CreateImm(Imm));
1877 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1878 assert(N == 1 && "Invalid number of operands!");
1879 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1882 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1883 assert(N == 1 && "Invalid number of operands!");
1884 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1887 void addVecListOperands(MCInst &Inst, unsigned N) const {
1888 assert(N == 1 && "Invalid number of operands!");
1889 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1892 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
1893 assert(N == 2 && "Invalid number of operands!");
1894 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1895 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
1898 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
1899 assert(N == 1 && "Invalid number of operands!");
1900 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1903 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
1904 assert(N == 1 && "Invalid number of operands!");
1905 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1908 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
1909 assert(N == 1 && "Invalid number of operands!");
1910 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1913 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
1914 assert(N == 1 && "Invalid number of operands!");
1915 // The immediate encodes the type of constant as well as the value.
1916 // Mask in that this is an i8 splat.
1917 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1918 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
1921 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
1922 assert(N == 1 && "Invalid number of operands!");
1923 // The immediate encodes the type of constant as well as the value.
1924 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1925 unsigned Value = CE->getValue();
1927 Value = (Value >> 8) | 0xa00;
1930 Inst.addOperand(MCOperand::CreateImm(Value));
1933 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
1934 assert(N == 1 && "Invalid number of operands!");
1935 // The immediate encodes the type of constant as well as the value.
1936 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1937 unsigned Value = CE->getValue();
1938 if (Value >= 256 && Value <= 0xff00)
1939 Value = (Value >> 8) | 0x200;
1940 else if (Value > 0xffff && Value <= 0xff0000)
1941 Value = (Value >> 16) | 0x400;
1942 else if (Value > 0xffffff)
1943 Value = (Value >> 24) | 0x600;
1944 Inst.addOperand(MCOperand::CreateImm(Value));
1947 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
1948 assert(N == 1 && "Invalid number of operands!");
1949 // The immediate encodes the type of constant as well as the value.
1950 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1951 unsigned Value = CE->getValue();
1952 if (Value >= 256 && Value <= 0xffff)
1953 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
1954 else if (Value > 0xffff && Value <= 0xffffff)
1955 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
1956 else if (Value > 0xffffff)
1957 Value = (Value >> 24) | 0x600;
1958 Inst.addOperand(MCOperand::CreateImm(Value));
1961 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
1962 assert(N == 1 && "Invalid number of operands!");
1963 // The immediate encodes the type of constant as well as the value.
1964 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1965 unsigned Value = ~CE->getValue();
1966 if (Value >= 256 && Value <= 0xffff)
1967 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
1968 else if (Value > 0xffff && Value <= 0xffffff)
1969 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
1970 else if (Value > 0xffffff)
1971 Value = (Value >> 24) | 0x600;
1972 Inst.addOperand(MCOperand::CreateImm(Value));
1975 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
1976 assert(N == 1 && "Invalid number of operands!");
1977 // The immediate encodes the type of constant as well as the value.
1978 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1979 uint64_t Value = CE->getValue();
1981 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
1982 Imm |= (Value & 1) << i;
1984 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
1987 virtual void print(raw_ostream &OS) const;
1989 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
1990 ARMOperand *Op = new ARMOperand(k_ITCondMask);
1991 Op->ITMask.Mask = Mask;
1997 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1998 ARMOperand *Op = new ARMOperand(k_CondCode);
2005 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2006 ARMOperand *Op = new ARMOperand(k_CoprocNum);
2007 Op->Cop.Val = CopVal;
2013 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2014 ARMOperand *Op = new ARMOperand(k_CoprocReg);
2015 Op->Cop.Val = CopVal;
2021 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2022 ARMOperand *Op = new ARMOperand(k_CoprocOption);
2029 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2030 ARMOperand *Op = new ARMOperand(k_CCOut);
2031 Op->Reg.RegNum = RegNum;
2037 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2038 ARMOperand *Op = new ARMOperand(k_Token);
2039 Op->Tok.Data = Str.data();
2040 Op->Tok.Length = Str.size();
2046 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2047 ARMOperand *Op = new ARMOperand(k_Register);
2048 Op->Reg.RegNum = RegNum;
2054 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2059 ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2060 Op->RegShiftedReg.ShiftTy = ShTy;
2061 Op->RegShiftedReg.SrcReg = SrcReg;
2062 Op->RegShiftedReg.ShiftReg = ShiftReg;
2063 Op->RegShiftedReg.ShiftImm = ShiftImm;
2069 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2073 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2074 Op->RegShiftedImm.ShiftTy = ShTy;
2075 Op->RegShiftedImm.SrcReg = SrcReg;
2076 Op->RegShiftedImm.ShiftImm = ShiftImm;
2082 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2084 ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2085 Op->ShifterImm.isASR = isASR;
2086 Op->ShifterImm.Imm = Imm;
2092 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2093 ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2094 Op->RotImm.Imm = Imm;
2100 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2102 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2103 Op->Bitfield.LSB = LSB;
2104 Op->Bitfield.Width = Width;
2111 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
2112 SMLoc StartLoc, SMLoc EndLoc) {
2113 KindTy Kind = k_RegisterList;
2115 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
2116 Kind = k_DPRRegisterList;
2117 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2118 contains(Regs.front().first))
2119 Kind = k_SPRRegisterList;
2121 ARMOperand *Op = new ARMOperand(Kind);
2122 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
2123 I = Regs.begin(), E = Regs.end(); I != E; ++I)
2124 Op->Registers.push_back(I->first);
2125 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
2126 Op->StartLoc = StartLoc;
2127 Op->EndLoc = EndLoc;
2131 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2132 bool isDoubleSpaced, SMLoc S, SMLoc E) {
2133 ARMOperand *Op = new ARMOperand(k_VectorList);
2134 Op->VectorList.RegNum = RegNum;
2135 Op->VectorList.Count = Count;
2136 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2142 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2143 bool isDoubleSpaced,
2145 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2146 Op->VectorList.RegNum = RegNum;
2147 Op->VectorList.Count = Count;
2148 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2154 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2156 bool isDoubleSpaced,
2158 ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2159 Op->VectorList.RegNum = RegNum;
2160 Op->VectorList.Count = Count;
2161 Op->VectorList.LaneIndex = Index;
2162 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2168 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2170 ARMOperand *Op = new ARMOperand(k_VectorIndex);
2171 Op->VectorIndex.Val = Idx;
2177 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2178 ARMOperand *Op = new ARMOperand(k_Immediate);
2185 static ARMOperand *CreateMem(unsigned BaseRegNum,
2186 const MCConstantExpr *OffsetImm,
2187 unsigned OffsetRegNum,
2188 ARM_AM::ShiftOpc ShiftType,
2193 ARMOperand *Op = new ARMOperand(k_Memory);
2194 Op->Memory.BaseRegNum = BaseRegNum;
2195 Op->Memory.OffsetImm = OffsetImm;
2196 Op->Memory.OffsetRegNum = OffsetRegNum;
2197 Op->Memory.ShiftType = ShiftType;
2198 Op->Memory.ShiftImm = ShiftImm;
2199 Op->Memory.Alignment = Alignment;
2200 Op->Memory.isNegative = isNegative;
2206 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2207 ARM_AM::ShiftOpc ShiftTy,
2210 ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2211 Op->PostIdxReg.RegNum = RegNum;
2212 Op->PostIdxReg.isAdd = isAdd;
2213 Op->PostIdxReg.ShiftTy = ShiftTy;
2214 Op->PostIdxReg.ShiftImm = ShiftImm;
2220 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2221 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2222 Op->MBOpt.Val = Opt;
2228 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2229 ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2230 Op->IFlags.Val = IFlags;
2236 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2237 ARMOperand *Op = new ARMOperand(k_MSRMask);
2238 Op->MMask.Val = MMask;
2245 } // end anonymous namespace.
2247 void ARMOperand::print(raw_ostream &OS) const {
2250 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2253 OS << "<ccout " << getReg() << ">";
2255 case k_ITCondMask: {
2256 static const char *MaskStr[] = {
2257 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2258 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2260 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2261 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2265 OS << "<coprocessor number: " << getCoproc() << ">";
2268 OS << "<coprocessor register: " << getCoproc() << ">";
2270 case k_CoprocOption:
2271 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2274 OS << "<mask: " << getMSRMask() << ">";
2277 getImm()->print(OS);
2279 case k_MemBarrierOpt:
2280 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
2284 << " base:" << Memory.BaseRegNum;
2287 case k_PostIndexRegister:
2288 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2289 << PostIdxReg.RegNum;
2290 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2291 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2292 << PostIdxReg.ShiftImm;
2295 case k_ProcIFlags: {
2296 OS << "<ARM_PROC::";
2297 unsigned IFlags = getProcIFlags();
2298 for (int i=2; i >= 0; --i)
2299 if (IFlags & (1 << i))
2300 OS << ARM_PROC::IFlagsToString(1 << i);
2305 OS << "<register " << getReg() << ">";
2307 case k_ShifterImmediate:
2308 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2309 << " #" << ShifterImm.Imm << ">";
2311 case k_ShiftedRegister:
2312 OS << "<so_reg_reg "
2313 << RegShiftedReg.SrcReg << " "
2314 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2315 << " " << RegShiftedReg.ShiftReg << ">";
2317 case k_ShiftedImmediate:
2318 OS << "<so_reg_imm "
2319 << RegShiftedImm.SrcReg << " "
2320 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2321 << " #" << RegShiftedImm.ShiftImm << ">";
2323 case k_RotateImmediate:
2324 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2326 case k_BitfieldDescriptor:
2327 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2328 << ", width: " << Bitfield.Width << ">";
2330 case k_RegisterList:
2331 case k_DPRRegisterList:
2332 case k_SPRRegisterList: {
2333 OS << "<register_list ";
2335 const SmallVectorImpl<unsigned> &RegList = getRegList();
2336 for (SmallVectorImpl<unsigned>::const_iterator
2337 I = RegList.begin(), E = RegList.end(); I != E; ) {
2339 if (++I < E) OS << ", ";
2346 OS << "<vector_list " << VectorList.Count << " * "
2347 << VectorList.RegNum << ">";
2349 case k_VectorListAllLanes:
2350 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2351 << VectorList.RegNum << ">";
2353 case k_VectorListIndexed:
2354 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2355 << VectorList.Count << " * " << VectorList.RegNum << ">";
2358 OS << "'" << getToken() << "'";
2361 OS << "<vectorindex " << getVectorIndex() << ">";
2366 /// @name Auto-generated Match Functions
2369 static unsigned MatchRegisterName(StringRef Name);
2373 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2374 SMLoc &StartLoc, SMLoc &EndLoc) {
2375 StartLoc = Parser.getTok().getLoc();
2376 RegNo = tryParseRegister();
2377 EndLoc = Parser.getTok().getLoc();
2379 return (RegNo == (unsigned)-1);
2382 /// Try to parse a register name. The token must be an Identifier when called,
2383 /// and if it is a register name the token is eaten and the register number is
2384 /// returned. Otherwise return -1.
2386 int ARMAsmParser::tryParseRegister() {
2387 const AsmToken &Tok = Parser.getTok();
2388 if (Tok.isNot(AsmToken::Identifier)) return -1;
2390 std::string lowerCase = Tok.getString().lower();
2391 unsigned RegNum = MatchRegisterName(lowerCase);
2393 RegNum = StringSwitch<unsigned>(lowerCase)
2394 .Case("r13", ARM::SP)
2395 .Case("r14", ARM::LR)
2396 .Case("r15", ARM::PC)
2397 .Case("ip", ARM::R12)
2398 // Additional register name aliases for 'gas' compatibility.
2399 .Case("a1", ARM::R0)
2400 .Case("a2", ARM::R1)
2401 .Case("a3", ARM::R2)
2402 .Case("a4", ARM::R3)
2403 .Case("v1", ARM::R4)
2404 .Case("v2", ARM::R5)
2405 .Case("v3", ARM::R6)
2406 .Case("v4", ARM::R7)
2407 .Case("v5", ARM::R8)
2408 .Case("v6", ARM::R9)
2409 .Case("v7", ARM::R10)
2410 .Case("v8", ARM::R11)
2411 .Case("sb", ARM::R9)
2412 .Case("sl", ARM::R10)
2413 .Case("fp", ARM::R11)
2417 // Check for aliases registered via .req. Canonicalize to lower case.
2418 // That's more consistent since register names are case insensitive, and
2419 // it's how the original entry was passed in from MC/MCParser/AsmParser.
2420 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2421 // If no match, return failure.
2422 if (Entry == RegisterReqs.end())
2424 Parser.Lex(); // Eat identifier token.
2425 return Entry->getValue();
2428 Parser.Lex(); // Eat identifier token.
2433 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
2434 // If a recoverable error occurs, return 1. If an irrecoverable error
2435 // occurs, return -1. An irrecoverable error is one where tokens have been
2436 // consumed in the process of trying to parse the shifter (i.e., when it is
2437 // indeed a shifter operand, but malformed).
2438 int ARMAsmParser::tryParseShiftRegister(
2439 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2440 SMLoc S = Parser.getTok().getLoc();
2441 const AsmToken &Tok = Parser.getTok();
2442 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2444 std::string lowerCase = Tok.getString().lower();
2445 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2446 .Case("asl", ARM_AM::lsl)
2447 .Case("lsl", ARM_AM::lsl)
2448 .Case("lsr", ARM_AM::lsr)
2449 .Case("asr", ARM_AM::asr)
2450 .Case("ror", ARM_AM::ror)
2451 .Case("rrx", ARM_AM::rrx)
2452 .Default(ARM_AM::no_shift);
2454 if (ShiftTy == ARM_AM::no_shift)
2457 Parser.Lex(); // Eat the operator.
2459 // The source register for the shift has already been added to the
2460 // operand list, so we need to pop it off and combine it into the shifted
2461 // register operand instead.
2462 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2463 if (!PrevOp->isReg())
2464 return Error(PrevOp->getStartLoc(), "shift must be of a register");
2465 int SrcReg = PrevOp->getReg();
2468 if (ShiftTy == ARM_AM::rrx) {
2469 // RRX Doesn't have an explicit shift amount. The encoder expects
2470 // the shift register to be the same as the source register. Seems odd,
2474 // Figure out if this is shifted by a constant or a register (for non-RRX).
2475 if (Parser.getTok().is(AsmToken::Hash) ||
2476 Parser.getTok().is(AsmToken::Dollar)) {
2477 Parser.Lex(); // Eat hash.
2478 SMLoc ImmLoc = Parser.getTok().getLoc();
2479 const MCExpr *ShiftExpr = 0;
2480 if (getParser().ParseExpression(ShiftExpr)) {
2481 Error(ImmLoc, "invalid immediate shift value");
2484 // The expression must be evaluatable as an immediate.
2485 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2487 Error(ImmLoc, "invalid immediate shift value");
2490 // Range check the immediate.
2491 // lsl, ror: 0 <= imm <= 31
2492 // lsr, asr: 0 <= imm <= 32
2493 Imm = CE->getValue();
2495 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2496 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2497 Error(ImmLoc, "immediate shift value out of range");
2500 // shift by zero is a nop. Always send it through as lsl.
2501 // ('as' compatibility)
2503 ShiftTy = ARM_AM::lsl;
2504 } else if (Parser.getTok().is(AsmToken::Identifier)) {
2505 ShiftReg = tryParseRegister();
2506 SMLoc L = Parser.getTok().getLoc();
2507 if (ShiftReg == -1) {
2508 Error (L, "expected immediate or register in shift operand");
2512 Error (Parser.getTok().getLoc(),
2513 "expected immediate or register in shift operand");
2518 if (ShiftReg && ShiftTy != ARM_AM::rrx)
2519 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2521 S, Parser.getTok().getLoc()));
2523 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2524 S, Parser.getTok().getLoc()));
2530 /// Try to parse a register name. The token must be an Identifier when called.
2531 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
2532 /// if there is a "writeback". 'true' if it's not a register.
2534 /// TODO this is likely to change to allow different register types and or to
2535 /// parse for a specific register type.
2537 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2538 SMLoc S = Parser.getTok().getLoc();
2539 int RegNo = tryParseRegister();
2543 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
2545 const AsmToken &ExclaimTok = Parser.getTok();
2546 if (ExclaimTok.is(AsmToken::Exclaim)) {
2547 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2548 ExclaimTok.getLoc()));
2549 Parser.Lex(); // Eat exclaim token
2553 // Also check for an index operand. This is only legal for vector registers,
2554 // but that'll get caught OK in operand matching, so we don't need to
2555 // explicitly filter everything else out here.
2556 if (Parser.getTok().is(AsmToken::LBrac)) {
2557 SMLoc SIdx = Parser.getTok().getLoc();
2558 Parser.Lex(); // Eat left bracket token.
2560 const MCExpr *ImmVal;
2561 if (getParser().ParseExpression(ImmVal))
2563 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2565 return TokError("immediate value expected for vector index");
2567 SMLoc E = Parser.getTok().getLoc();
2568 if (Parser.getTok().isNot(AsmToken::RBrac))
2569 return Error(E, "']' expected");
2571 Parser.Lex(); // Eat right bracket token.
2573 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2581 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
2582 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2584 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2585 // Use the same layout as the tablegen'erated register name matcher. Ugly,
2587 switch (Name.size()) {
2590 if (Name[0] != CoprocOp)
2606 if (Name[0] != CoprocOp || Name[1] != '1')
2610 case '0': return 10;
2611 case '1': return 11;
2612 case '2': return 12;
2613 case '3': return 13;
2614 case '4': return 14;
2615 case '5': return 15;
2620 /// parseITCondCode - Try to parse a condition code for an IT instruction.
2621 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2622 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2623 SMLoc S = Parser.getTok().getLoc();
2624 const AsmToken &Tok = Parser.getTok();
2625 if (!Tok.is(AsmToken::Identifier))
2626 return MatchOperand_NoMatch;
2627 unsigned CC = StringSwitch<unsigned>(Tok.getString())
2628 .Case("eq", ARMCC::EQ)
2629 .Case("ne", ARMCC::NE)
2630 .Case("hs", ARMCC::HS)
2631 .Case("cs", ARMCC::HS)
2632 .Case("lo", ARMCC::LO)
2633 .Case("cc", ARMCC::LO)
2634 .Case("mi", ARMCC::MI)
2635 .Case("pl", ARMCC::PL)
2636 .Case("vs", ARMCC::VS)
2637 .Case("vc", ARMCC::VC)
2638 .Case("hi", ARMCC::HI)
2639 .Case("ls", ARMCC::LS)
2640 .Case("ge", ARMCC::GE)
2641 .Case("lt", ARMCC::LT)
2642 .Case("gt", ARMCC::GT)
2643 .Case("le", ARMCC::LE)
2644 .Case("al", ARMCC::AL)
2647 return MatchOperand_NoMatch;
2648 Parser.Lex(); // Eat the token.
2650 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2652 return MatchOperand_Success;
2655 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2656 /// token must be an Identifier when called, and if it is a coprocessor
2657 /// number, the token is eaten and the operand is added to the operand list.
2658 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2659 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2660 SMLoc S = Parser.getTok().getLoc();
2661 const AsmToken &Tok = Parser.getTok();
2662 if (Tok.isNot(AsmToken::Identifier))
2663 return MatchOperand_NoMatch;
2665 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2667 return MatchOperand_NoMatch;
2669 Parser.Lex(); // Eat identifier token.
2670 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2671 return MatchOperand_Success;
2674 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2675 /// token must be an Identifier when called, and if it is a coprocessor
2676 /// number, the token is eaten and the operand is added to the operand list.
2677 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2678 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2679 SMLoc S = Parser.getTok().getLoc();
2680 const AsmToken &Tok = Parser.getTok();
2681 if (Tok.isNot(AsmToken::Identifier))
2682 return MatchOperand_NoMatch;
2684 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2686 return MatchOperand_NoMatch;
2688 Parser.Lex(); // Eat identifier token.
2689 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2690 return MatchOperand_Success;
2693 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2694 /// coproc_option : '{' imm0_255 '}'
2695 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2696 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2697 SMLoc S = Parser.getTok().getLoc();
2699 // If this isn't a '{', this isn't a coprocessor immediate operand.
2700 if (Parser.getTok().isNot(AsmToken::LCurly))
2701 return MatchOperand_NoMatch;
2702 Parser.Lex(); // Eat the '{'
2705 SMLoc Loc = Parser.getTok().getLoc();
2706 if (getParser().ParseExpression(Expr)) {
2707 Error(Loc, "illegal expression");
2708 return MatchOperand_ParseFail;
2710 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2711 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2712 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2713 return MatchOperand_ParseFail;
2715 int Val = CE->getValue();
2717 // Check for and consume the closing '}'
2718 if (Parser.getTok().isNot(AsmToken::RCurly))
2719 return MatchOperand_ParseFail;
2720 SMLoc E = Parser.getTok().getLoc();
2721 Parser.Lex(); // Eat the '}'
2723 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2724 return MatchOperand_Success;
2727 // For register list parsing, we need to map from raw GPR register numbering
2728 // to the enumeration values. The enumeration values aren't sorted by
2729 // register number due to our using "sp", "lr" and "pc" as canonical names.
2730 static unsigned getNextRegister(unsigned Reg) {
2731 // If this is a GPR, we need to do it manually, otherwise we can rely
2732 // on the sort ordering of the enumeration since the other reg-classes
2734 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2737 default: llvm_unreachable("Invalid GPR number!");
2738 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
2739 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
2740 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
2741 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
2742 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
2743 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2744 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
2745 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
2749 // Return the low-subreg of a given Q register.
2750 static unsigned getDRegFromQReg(unsigned QReg) {
2752 default: llvm_unreachable("expected a Q register!");
2753 case ARM::Q0: return ARM::D0;
2754 case ARM::Q1: return ARM::D2;
2755 case ARM::Q2: return ARM::D4;
2756 case ARM::Q3: return ARM::D6;
2757 case ARM::Q4: return ARM::D8;
2758 case ARM::Q5: return ARM::D10;
2759 case ARM::Q6: return ARM::D12;
2760 case ARM::Q7: return ARM::D14;
2761 case ARM::Q8: return ARM::D16;
2762 case ARM::Q9: return ARM::D18;
2763 case ARM::Q10: return ARM::D20;
2764 case ARM::Q11: return ARM::D22;
2765 case ARM::Q12: return ARM::D24;
2766 case ARM::Q13: return ARM::D26;
2767 case ARM::Q14: return ARM::D28;
2768 case ARM::Q15: return ARM::D30;
2772 /// Parse a register list.
2774 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2775 assert(Parser.getTok().is(AsmToken::LCurly) &&
2776 "Token is not a Left Curly Brace");
2777 SMLoc S = Parser.getTok().getLoc();
2778 Parser.Lex(); // Eat '{' token.
2779 SMLoc RegLoc = Parser.getTok().getLoc();
2781 // Check the first register in the list to see what register class
2782 // this is a list of.
2783 int Reg = tryParseRegister();
2785 return Error(RegLoc, "register expected");
2787 // The reglist instructions have at most 16 registers, so reserve
2788 // space for that many.
2789 SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
2791 // Allow Q regs and just interpret them as the two D sub-registers.
2792 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2793 Reg = getDRegFromQReg(Reg);
2794 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2797 const MCRegisterClass *RC;
2798 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2799 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
2800 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
2801 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
2802 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
2803 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
2805 return Error(RegLoc, "invalid register in register list");
2807 // Store the register.
2808 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2810 // This starts immediately after the first register token in the list,
2811 // so we can see either a comma or a minus (range separator) as a legal
2813 while (Parser.getTok().is(AsmToken::Comma) ||
2814 Parser.getTok().is(AsmToken::Minus)) {
2815 if (Parser.getTok().is(AsmToken::Minus)) {
2816 Parser.Lex(); // Eat the minus.
2817 SMLoc EndLoc = Parser.getTok().getLoc();
2818 int EndReg = tryParseRegister();
2820 return Error(EndLoc, "register expected");
2821 // Allow Q regs and just interpret them as the two D sub-registers.
2822 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
2823 EndReg = getDRegFromQReg(EndReg) + 1;
2824 // If the register is the same as the start reg, there's nothing
2828 // The register must be in the same register class as the first.
2829 if (!RC->contains(EndReg))
2830 return Error(EndLoc, "invalid register in register list");
2831 // Ranges must go from low to high.
2832 if (getARMRegisterNumbering(Reg) > getARMRegisterNumbering(EndReg))
2833 return Error(EndLoc, "bad range in register list");
2835 // Add all the registers in the range to the register list.
2836 while (Reg != EndReg) {
2837 Reg = getNextRegister(Reg);
2838 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2842 Parser.Lex(); // Eat the comma.
2843 RegLoc = Parser.getTok().getLoc();
2845 const AsmToken RegTok = Parser.getTok();
2846 Reg = tryParseRegister();
2848 return Error(RegLoc, "register expected");
2849 // Allow Q regs and just interpret them as the two D sub-registers.
2850 bool isQReg = false;
2851 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2852 Reg = getDRegFromQReg(Reg);
2855 // The register must be in the same register class as the first.
2856 if (!RC->contains(Reg))
2857 return Error(RegLoc, "invalid register in register list");
2858 // List must be monotonically increasing.
2859 if (getARMRegisterNumbering(Reg) < getARMRegisterNumbering(OldReg)) {
2860 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2861 Warning(RegLoc, "register list not in ascending order");
2863 return Error(RegLoc, "register list not in ascending order");
2865 if (getARMRegisterNumbering(Reg) == getARMRegisterNumbering(OldReg)) {
2866 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
2867 ") in register list");
2870 // VFP register lists must also be contiguous.
2871 // It's OK to use the enumeration values directly here rather, as the
2872 // VFP register classes have the enum sorted properly.
2873 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
2875 return Error(RegLoc, "non-contiguous register range");
2876 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2878 Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc));
2881 SMLoc E = Parser.getTok().getLoc();
2882 if (Parser.getTok().isNot(AsmToken::RCurly))
2883 return Error(E, "'}' expected");
2884 Parser.Lex(); // Eat '}' token.
2886 // Push the register list operand.
2887 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
2889 // The ARM system instruction variants for LDM/STM have a '^' token here.
2890 if (Parser.getTok().is(AsmToken::Caret)) {
2891 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
2892 Parser.Lex(); // Eat '^' token.
2898 // Helper function to parse the lane index for vector lists.
2899 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2900 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index) {
2901 Index = 0; // Always return a defined index value.
2902 if (Parser.getTok().is(AsmToken::LBrac)) {
2903 Parser.Lex(); // Eat the '['.
2904 if (Parser.getTok().is(AsmToken::RBrac)) {
2905 // "Dn[]" is the 'all lanes' syntax.
2906 LaneKind = AllLanes;
2907 Parser.Lex(); // Eat the ']'.
2908 return MatchOperand_Success;
2911 // There's an optional '#' token here. Normally there wouldn't be, but
2912 // inline assemble puts one in, and it's friendly to accept that.
2913 if (Parser.getTok().is(AsmToken::Hash))
2914 Parser.Lex(); // Eat the '#'
2916 const MCExpr *LaneIndex;
2917 SMLoc Loc = Parser.getTok().getLoc();
2918 if (getParser().ParseExpression(LaneIndex)) {
2919 Error(Loc, "illegal expression");
2920 return MatchOperand_ParseFail;
2922 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
2924 Error(Loc, "lane index must be empty or an integer");
2925 return MatchOperand_ParseFail;
2927 if (Parser.getTok().isNot(AsmToken::RBrac)) {
2928 Error(Parser.getTok().getLoc(), "']' expected");
2929 return MatchOperand_ParseFail;
2931 Parser.Lex(); // Eat the ']'.
2932 int64_t Val = CE->getValue();
2934 // FIXME: Make this range check context sensitive for .8, .16, .32.
2935 if (Val < 0 || Val > 7) {
2936 Error(Parser.getTok().getLoc(), "lane index out of range");
2937 return MatchOperand_ParseFail;
2940 LaneKind = IndexedLane;
2941 return MatchOperand_Success;
2944 return MatchOperand_Success;
2947 // parse a vector register list
2948 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2949 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2950 VectorLaneTy LaneKind;
2952 SMLoc S = Parser.getTok().getLoc();
2953 // As an extension (to match gas), support a plain D register or Q register
2954 // (without encosing curly braces) as a single or double entry list,
2956 if (Parser.getTok().is(AsmToken::Identifier)) {
2957 int Reg = tryParseRegister();
2959 return MatchOperand_NoMatch;
2960 SMLoc E = Parser.getTok().getLoc();
2961 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
2962 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex);
2963 if (Res != MatchOperand_Success)
2967 E = Parser.getTok().getLoc();
2968 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
2971 E = Parser.getTok().getLoc();
2972 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
2976 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
2981 return MatchOperand_Success;
2983 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2984 Reg = getDRegFromQReg(Reg);
2985 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex);
2986 if (Res != MatchOperand_Success)
2990 E = Parser.getTok().getLoc();
2991 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
2992 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
2993 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
2996 E = Parser.getTok().getLoc();
2997 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
2998 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
2999 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3003 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3008 return MatchOperand_Success;
3010 Error(S, "vector register expected");
3011 return MatchOperand_ParseFail;
3014 if (Parser.getTok().isNot(AsmToken::LCurly))
3015 return MatchOperand_NoMatch;
3017 Parser.Lex(); // Eat '{' token.
3018 SMLoc RegLoc = Parser.getTok().getLoc();
3020 int Reg = tryParseRegister();
3022 Error(RegLoc, "register expected");
3023 return MatchOperand_ParseFail;
3027 unsigned FirstReg = Reg;
3028 // The list is of D registers, but we also allow Q regs and just interpret
3029 // them as the two D sub-registers.
3030 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3031 FirstReg = Reg = getDRegFromQReg(Reg);
3032 Spacing = 1; // double-spacing requires explicit D registers, otherwise
3033 // it's ambiguous with four-register single spaced.
3037 if (parseVectorLane(LaneKind, LaneIndex) != MatchOperand_Success)
3038 return MatchOperand_ParseFail;
3040 while (Parser.getTok().is(AsmToken::Comma) ||
3041 Parser.getTok().is(AsmToken::Minus)) {
3042 if (Parser.getTok().is(AsmToken::Minus)) {
3044 Spacing = 1; // Register range implies a single spaced list.
3045 else if (Spacing == 2) {
3046 Error(Parser.getTok().getLoc(),
3047 "sequential registers in double spaced list");
3048 return MatchOperand_ParseFail;
3050 Parser.Lex(); // Eat the minus.
3051 SMLoc EndLoc = Parser.getTok().getLoc();
3052 int EndReg = tryParseRegister();
3054 Error(EndLoc, "register expected");
3055 return MatchOperand_ParseFail;
3057 // Allow Q regs and just interpret them as the two D sub-registers.
3058 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3059 EndReg = getDRegFromQReg(EndReg) + 1;
3060 // If the register is the same as the start reg, there's nothing
3064 // The register must be in the same register class as the first.
3065 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3066 Error(EndLoc, "invalid register in register list");
3067 return MatchOperand_ParseFail;
3069 // Ranges must go from low to high.
3071 Error(EndLoc, "bad range in register list");
3072 return MatchOperand_ParseFail;
3074 // Parse the lane specifier if present.
3075 VectorLaneTy NextLaneKind;
3076 unsigned NextLaneIndex;
3077 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
3078 return MatchOperand_ParseFail;
3079 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3080 Error(EndLoc, "mismatched lane index in register list");
3081 return MatchOperand_ParseFail;
3083 EndLoc = Parser.getTok().getLoc();
3085 // Add all the registers in the range to the register list.
3086 Count += EndReg - Reg;
3090 Parser.Lex(); // Eat the comma.
3091 RegLoc = Parser.getTok().getLoc();
3093 Reg = tryParseRegister();
3095 Error(RegLoc, "register expected");
3096 return MatchOperand_ParseFail;
3098 // vector register lists must be contiguous.
3099 // It's OK to use the enumeration values directly here rather, as the
3100 // VFP register classes have the enum sorted properly.
3102 // The list is of D registers, but we also allow Q regs and just interpret
3103 // them as the two D sub-registers.
3104 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3106 Spacing = 1; // Register range implies a single spaced list.
3107 else if (Spacing == 2) {
3109 "invalid register in double-spaced list (must be 'D' register')");
3110 return MatchOperand_ParseFail;
3112 Reg = getDRegFromQReg(Reg);
3113 if (Reg != OldReg + 1) {
3114 Error(RegLoc, "non-contiguous register range");
3115 return MatchOperand_ParseFail;
3119 // Parse the lane specifier if present.
3120 VectorLaneTy NextLaneKind;
3121 unsigned NextLaneIndex;
3122 SMLoc EndLoc = Parser.getTok().getLoc();
3123 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
3124 return MatchOperand_ParseFail;
3125 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3126 Error(EndLoc, "mismatched lane index in register list");
3127 return MatchOperand_ParseFail;
3131 // Normal D register.
3132 // Figure out the register spacing (single or double) of the list if
3133 // we don't know it already.
3135 Spacing = 1 + (Reg == OldReg + 2);
3137 // Just check that it's contiguous and keep going.
3138 if (Reg != OldReg + Spacing) {
3139 Error(RegLoc, "non-contiguous register range");
3140 return MatchOperand_ParseFail;
3143 // Parse the lane specifier if present.
3144 VectorLaneTy NextLaneKind;
3145 unsigned NextLaneIndex;
3146 SMLoc EndLoc = Parser.getTok().getLoc();
3147 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
3148 return MatchOperand_ParseFail;
3149 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3150 Error(EndLoc, "mismatched lane index in register list");
3151 return MatchOperand_ParseFail;
3155 SMLoc E = Parser.getTok().getLoc();
3156 if (Parser.getTok().isNot(AsmToken::RCurly)) {
3157 Error(E, "'}' expected");
3158 return MatchOperand_ParseFail;
3160 Parser.Lex(); // Eat '}' token.
3164 // Two-register operands have been converted to the
3165 // composite register classes.
3167 const MCRegisterClass *RC = (Spacing == 1) ?
3168 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3169 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3170 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3173 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3174 (Spacing == 2), S, E));
3177 // Two-register operands have been converted to the
3178 // composite register classes.
3180 const MCRegisterClass *RC = (Spacing == 1) ?
3181 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3182 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3183 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3185 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3190 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3196 return MatchOperand_Success;
3199 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3200 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3201 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3202 SMLoc S = Parser.getTok().getLoc();
3203 const AsmToken &Tok = Parser.getTok();
3204 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
3205 StringRef OptStr = Tok.getString();
3207 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
3208 .Case("sy", ARM_MB::SY)
3209 .Case("st", ARM_MB::ST)
3210 .Case("sh", ARM_MB::ISH)
3211 .Case("ish", ARM_MB::ISH)
3212 .Case("shst", ARM_MB::ISHST)
3213 .Case("ishst", ARM_MB::ISHST)
3214 .Case("nsh", ARM_MB::NSH)
3215 .Case("un", ARM_MB::NSH)
3216 .Case("nshst", ARM_MB::NSHST)
3217 .Case("unst", ARM_MB::NSHST)
3218 .Case("osh", ARM_MB::OSH)
3219 .Case("oshst", ARM_MB::OSHST)
3223 return MatchOperand_NoMatch;
3225 Parser.Lex(); // Eat identifier token.
3226 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3227 return MatchOperand_Success;
3230 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3231 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3232 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3233 SMLoc S = Parser.getTok().getLoc();
3234 const AsmToken &Tok = Parser.getTok();
3235 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
3236 StringRef IFlagsStr = Tok.getString();
3238 // An iflags string of "none" is interpreted to mean that none of the AIF
3239 // bits are set. Not a terribly useful instruction, but a valid encoding.
3240 unsigned IFlags = 0;
3241 if (IFlagsStr != "none") {
3242 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3243 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3244 .Case("a", ARM_PROC::A)
3245 .Case("i", ARM_PROC::I)
3246 .Case("f", ARM_PROC::F)
3249 // If some specific iflag is already set, it means that some letter is
3250 // present more than once, this is not acceptable.
3251 if (Flag == ~0U || (IFlags & Flag))
3252 return MatchOperand_NoMatch;
3258 Parser.Lex(); // Eat identifier token.
3259 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3260 return MatchOperand_Success;
3263 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3264 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3265 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3266 SMLoc S = Parser.getTok().getLoc();
3267 const AsmToken &Tok = Parser.getTok();
3268 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
3269 StringRef Mask = Tok.getString();
3272 // See ARMv6-M 10.1.1
3273 std::string Name = Mask.lower();
3274 unsigned FlagsVal = StringSwitch<unsigned>(Name)
3284 .Case("primask", 16)
3285 .Case("basepri", 17)
3286 .Case("basepri_max", 18)
3287 .Case("faultmask", 19)
3288 .Case("control", 20)
3291 if (FlagsVal == ~0U)
3292 return MatchOperand_NoMatch;
3294 if (!hasV7Ops() && FlagsVal >= 17 && FlagsVal <= 19)
3295 // basepri, basepri_max and faultmask only valid for V7m.
3296 return MatchOperand_NoMatch;
3298 Parser.Lex(); // Eat identifier token.
3299 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3300 return MatchOperand_Success;
3303 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3304 size_t Start = 0, Next = Mask.find('_');
3305 StringRef Flags = "";
3306 std::string SpecReg = Mask.slice(Start, Next).lower();
3307 if (Next != StringRef::npos)
3308 Flags = Mask.slice(Next+1, Mask.size());
3310 // FlagsVal contains the complete mask:
3312 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3313 unsigned FlagsVal = 0;
3315 if (SpecReg == "apsr") {
3316 FlagsVal = StringSwitch<unsigned>(Flags)
3317 .Case("nzcvq", 0x8) // same as CPSR_f
3318 .Case("g", 0x4) // same as CPSR_s
3319 .Case("nzcvqg", 0xc) // same as CPSR_fs
3322 if (FlagsVal == ~0U) {
3324 return MatchOperand_NoMatch;
3326 FlagsVal = 8; // No flag
3328 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3329 if (Flags == "all") // cpsr_all is an alias for cpsr_fc
3331 for (int i = 0, e = Flags.size(); i != e; ++i) {
3332 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3339 // If some specific flag is already set, it means that some letter is
3340 // present more than once, this is not acceptable.
3341 if (FlagsVal == ~0U || (FlagsVal & Flag))
3342 return MatchOperand_NoMatch;
3345 } else // No match for special register.
3346 return MatchOperand_NoMatch;
3348 // Special register without flags is NOT equivalent to "fc" flags.
3349 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
3350 // two lines would enable gas compatibility at the expense of breaking
3356 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3357 if (SpecReg == "spsr")
3360 Parser.Lex(); // Eat identifier token.
3361 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3362 return MatchOperand_Success;
3365 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3366 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3367 int Low, int High) {
3368 const AsmToken &Tok = Parser.getTok();
3369 if (Tok.isNot(AsmToken::Identifier)) {
3370 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3371 return MatchOperand_ParseFail;
3373 StringRef ShiftName = Tok.getString();
3374 std::string LowerOp = Op.lower();
3375 std::string UpperOp = Op.upper();
3376 if (ShiftName != LowerOp && ShiftName != UpperOp) {
3377 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3378 return MatchOperand_ParseFail;
3380 Parser.Lex(); // Eat shift type token.
3382 // There must be a '#' and a shift amount.
3383 if (Parser.getTok().isNot(AsmToken::Hash) &&
3384 Parser.getTok().isNot(AsmToken::Dollar)) {
3385 Error(Parser.getTok().getLoc(), "'#' expected");
3386 return MatchOperand_ParseFail;
3388 Parser.Lex(); // Eat hash token.
3390 const MCExpr *ShiftAmount;
3391 SMLoc Loc = Parser.getTok().getLoc();
3392 if (getParser().ParseExpression(ShiftAmount)) {
3393 Error(Loc, "illegal expression");
3394 return MatchOperand_ParseFail;
3396 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3398 Error(Loc, "constant expression expected");
3399 return MatchOperand_ParseFail;
3401 int Val = CE->getValue();
3402 if (Val < Low || Val > High) {
3403 Error(Loc, "immediate value out of range");
3404 return MatchOperand_ParseFail;
3407 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
3409 return MatchOperand_Success;
3412 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3413 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3414 const AsmToken &Tok = Parser.getTok();
3415 SMLoc S = Tok.getLoc();
3416 if (Tok.isNot(AsmToken::Identifier)) {
3417 Error(Tok.getLoc(), "'be' or 'le' operand expected");
3418 return MatchOperand_ParseFail;
3420 int Val = StringSwitch<int>(Tok.getString())
3424 Parser.Lex(); // Eat the token.
3427 Error(Tok.getLoc(), "'be' or 'le' operand expected");
3428 return MatchOperand_ParseFail;
3430 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3432 S, Parser.getTok().getLoc()));
3433 return MatchOperand_Success;
3436 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3437 /// instructions. Legal values are:
3438 /// lsl #n 'n' in [0,31]
3439 /// asr #n 'n' in [1,32]
3440 /// n == 32 encoded as n == 0.
3441 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3442 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3443 const AsmToken &Tok = Parser.getTok();
3444 SMLoc S = Tok.getLoc();
3445 if (Tok.isNot(AsmToken::Identifier)) {
3446 Error(S, "shift operator 'asr' or 'lsl' expected");
3447 return MatchOperand_ParseFail;
3449 StringRef ShiftName = Tok.getString();
3451 if (ShiftName == "lsl" || ShiftName == "LSL")
3453 else if (ShiftName == "asr" || ShiftName == "ASR")
3456 Error(S, "shift operator 'asr' or 'lsl' expected");
3457 return MatchOperand_ParseFail;
3459 Parser.Lex(); // Eat the operator.
3461 // A '#' and a shift amount.
3462 if (Parser.getTok().isNot(AsmToken::Hash) &&
3463 Parser.getTok().isNot(AsmToken::Dollar)) {
3464 Error(Parser.getTok().getLoc(), "'#' expected");
3465 return MatchOperand_ParseFail;
3467 Parser.Lex(); // Eat hash token.
3469 const MCExpr *ShiftAmount;
3470 SMLoc E = Parser.getTok().getLoc();
3471 if (getParser().ParseExpression(ShiftAmount)) {
3472 Error(E, "malformed shift expression");
3473 return MatchOperand_ParseFail;
3475 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3477 Error(E, "shift amount must be an immediate");
3478 return MatchOperand_ParseFail;
3481 int64_t Val = CE->getValue();
3483 // Shift amount must be in [1,32]
3484 if (Val < 1 || Val > 32) {
3485 Error(E, "'asr' shift amount must be in range [1,32]");
3486 return MatchOperand_ParseFail;
3488 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3489 if (isThumb() && Val == 32) {
3490 Error(E, "'asr #32' shift amount not allowed in Thumb mode");
3491 return MatchOperand_ParseFail;
3493 if (Val == 32) Val = 0;
3495 // Shift amount must be in [1,32]
3496 if (Val < 0 || Val > 31) {
3497 Error(E, "'lsr' shift amount must be in range [0,31]");
3498 return MatchOperand_ParseFail;
3502 E = Parser.getTok().getLoc();
3503 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
3505 return MatchOperand_Success;
3508 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3509 /// of instructions. Legal values are:
3510 /// ror #n 'n' in {0, 8, 16, 24}
3511 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3512 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3513 const AsmToken &Tok = Parser.getTok();
3514 SMLoc S = Tok.getLoc();
3515 if (Tok.isNot(AsmToken::Identifier))
3516 return MatchOperand_NoMatch;
3517 StringRef ShiftName = Tok.getString();
3518 if (ShiftName != "ror" && ShiftName != "ROR")
3519 return MatchOperand_NoMatch;
3520 Parser.Lex(); // Eat the operator.
3522 // A '#' and a rotate amount.
3523 if (Parser.getTok().isNot(AsmToken::Hash) &&
3524 Parser.getTok().isNot(AsmToken::Dollar)) {
3525 Error(Parser.getTok().getLoc(), "'#' expected");
3526 return MatchOperand_ParseFail;
3528 Parser.Lex(); // Eat hash token.
3530 const MCExpr *ShiftAmount;
3531 SMLoc E = Parser.getTok().getLoc();
3532 if (getParser().ParseExpression(ShiftAmount)) {
3533 Error(E, "malformed rotate expression");
3534 return MatchOperand_ParseFail;
3536 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3538 Error(E, "rotate amount must be an immediate");
3539 return MatchOperand_ParseFail;
3542 int64_t Val = CE->getValue();
3543 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
3544 // normally, zero is represented in asm by omitting the rotate operand
3546 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
3547 Error(E, "'ror' rotate amount must be 8, 16, or 24");
3548 return MatchOperand_ParseFail;
3551 E = Parser.getTok().getLoc();
3552 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
3554 return MatchOperand_Success;
3557 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3558 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3559 SMLoc S = Parser.getTok().getLoc();
3560 // The bitfield descriptor is really two operands, the LSB and the width.
3561 if (Parser.getTok().isNot(AsmToken::Hash) &&
3562 Parser.getTok().isNot(AsmToken::Dollar)) {
3563 Error(Parser.getTok().getLoc(), "'#' expected");
3564 return MatchOperand_ParseFail;
3566 Parser.Lex(); // Eat hash token.
3568 const MCExpr *LSBExpr;
3569 SMLoc E = Parser.getTok().getLoc();
3570 if (getParser().ParseExpression(LSBExpr)) {
3571 Error(E, "malformed immediate expression");
3572 return MatchOperand_ParseFail;
3574 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
3576 Error(E, "'lsb' operand must be an immediate");
3577 return MatchOperand_ParseFail;
3580 int64_t LSB = CE->getValue();
3581 // The LSB must be in the range [0,31]
3582 if (LSB < 0 || LSB > 31) {
3583 Error(E, "'lsb' operand must be in the range [0,31]");
3584 return MatchOperand_ParseFail;
3586 E = Parser.getTok().getLoc();
3588 // Expect another immediate operand.
3589 if (Parser.getTok().isNot(AsmToken::Comma)) {
3590 Error(Parser.getTok().getLoc(), "too few operands");
3591 return MatchOperand_ParseFail;
3593 Parser.Lex(); // Eat hash token.
3594 if (Parser.getTok().isNot(AsmToken::Hash) &&
3595 Parser.getTok().isNot(AsmToken::Dollar)) {
3596 Error(Parser.getTok().getLoc(), "'#' expected");
3597 return MatchOperand_ParseFail;
3599 Parser.Lex(); // Eat hash token.
3601 const MCExpr *WidthExpr;
3602 if (getParser().ParseExpression(WidthExpr)) {
3603 Error(E, "malformed immediate expression");
3604 return MatchOperand_ParseFail;
3606 CE = dyn_cast<MCConstantExpr>(WidthExpr);
3608 Error(E, "'width' operand must be an immediate");
3609 return MatchOperand_ParseFail;
3612 int64_t Width = CE->getValue();
3613 // The LSB must be in the range [1,32-lsb]
3614 if (Width < 1 || Width > 32 - LSB) {
3615 Error(E, "'width' operand must be in the range [1,32-lsb]");
3616 return MatchOperand_ParseFail;
3618 E = Parser.getTok().getLoc();
3620 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
3622 return MatchOperand_Success;
3625 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3626 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3627 // Check for a post-index addressing register operand. Specifically:
3628 // postidx_reg := '+' register {, shift}
3629 // | '-' register {, shift}
3630 // | register {, shift}
3632 // This method must return MatchOperand_NoMatch without consuming any tokens
3633 // in the case where there is no match, as other alternatives take other
3635 AsmToken Tok = Parser.getTok();
3636 SMLoc S = Tok.getLoc();
3637 bool haveEaten = false;
3640 if (Tok.is(AsmToken::Plus)) {
3641 Parser.Lex(); // Eat the '+' token.
3643 } else if (Tok.is(AsmToken::Minus)) {
3644 Parser.Lex(); // Eat the '-' token.
3648 if (Parser.getTok().is(AsmToken::Identifier))
3649 Reg = tryParseRegister();
3652 return MatchOperand_NoMatch;
3653 Error(Parser.getTok().getLoc(), "register expected");
3654 return MatchOperand_ParseFail;
3656 SMLoc E = Parser.getTok().getLoc();
3658 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
3659 unsigned ShiftImm = 0;
3660 if (Parser.getTok().is(AsmToken::Comma)) {
3661 Parser.Lex(); // Eat the ','.
3662 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
3663 return MatchOperand_ParseFail;
3666 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
3669 return MatchOperand_Success;
3672 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3673 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3674 // Check for a post-index addressing register operand. Specifically:
3675 // am3offset := '+' register
3682 // This method must return MatchOperand_NoMatch without consuming any tokens
3683 // in the case where there is no match, as other alternatives take other
3685 AsmToken Tok = Parser.getTok();
3686 SMLoc S = Tok.getLoc();
3688 // Do immediates first, as we always parse those if we have a '#'.
3689 if (Parser.getTok().is(AsmToken::Hash) ||
3690 Parser.getTok().is(AsmToken::Dollar)) {
3691 Parser.Lex(); // Eat the '#'.
3692 // Explicitly look for a '-', as we need to encode negative zero
3694 bool isNegative = Parser.getTok().is(AsmToken::Minus);
3695 const MCExpr *Offset;
3696 if (getParser().ParseExpression(Offset))
3697 return MatchOperand_ParseFail;
3698 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
3700 Error(S, "constant expression expected");
3701 return MatchOperand_ParseFail;
3703 SMLoc E = Tok.getLoc();
3704 // Negative zero is encoded as the flag value INT32_MIN.
3705 int32_t Val = CE->getValue();
3706 if (isNegative && Val == 0)
3710 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
3712 return MatchOperand_Success;
3716 bool haveEaten = false;
3719 if (Tok.is(AsmToken::Plus)) {
3720 Parser.Lex(); // Eat the '+' token.
3722 } else if (Tok.is(AsmToken::Minus)) {
3723 Parser.Lex(); // Eat the '-' token.
3727 if (Parser.getTok().is(AsmToken::Identifier))
3728 Reg = tryParseRegister();
3731 return MatchOperand_NoMatch;
3732 Error(Parser.getTok().getLoc(), "register expected");
3733 return MatchOperand_ParseFail;
3735 SMLoc E = Parser.getTok().getLoc();
3737 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
3740 return MatchOperand_Success;
3743 /// cvtT2LdrdPre - Convert parsed operands to MCInst.
3744 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3745 /// when they refer multiple MIOperands inside a single one.
3747 cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
3748 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3750 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3751 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3752 // Create a writeback register dummy placeholder.
3753 Inst.addOperand(MCOperand::CreateReg(0));
3755 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3757 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3761 /// cvtT2StrdPre - Convert parsed operands to MCInst.
3762 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3763 /// when they refer multiple MIOperands inside a single one.
3765 cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
3766 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3767 // Create a writeback register dummy placeholder.
3768 Inst.addOperand(MCOperand::CreateReg(0));
3770 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3771 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3773 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3775 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3779 /// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3780 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3781 /// when they refer multiple MIOperands inside a single one.
3783 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3784 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3785 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3787 // Create a writeback register dummy placeholder.
3788 Inst.addOperand(MCOperand::CreateImm(0));
3790 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3791 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3795 /// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3796 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3797 /// when they refer multiple MIOperands inside a single one.
3799 cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3800 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3801 // Create a writeback register dummy placeholder.
3802 Inst.addOperand(MCOperand::CreateImm(0));
3803 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3804 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3805 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3809 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3810 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3811 /// when they refer multiple MIOperands inside a single one.
3813 cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3814 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3815 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3817 // Create a writeback register dummy placeholder.
3818 Inst.addOperand(MCOperand::CreateImm(0));
3820 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3821 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3825 /// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3826 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3827 /// when they refer multiple MIOperands inside a single one.
3829 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3830 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3831 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3833 // Create a writeback register dummy placeholder.
3834 Inst.addOperand(MCOperand::CreateImm(0));
3836 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3837 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3842 /// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3843 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3844 /// when they refer multiple MIOperands inside a single one.
3846 cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3847 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3848 // Create a writeback register dummy placeholder.
3849 Inst.addOperand(MCOperand::CreateImm(0));
3850 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3851 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3852 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3856 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3857 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3858 /// when they refer multiple MIOperands inside a single one.
3860 cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3861 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3862 // Create a writeback register dummy placeholder.
3863 Inst.addOperand(MCOperand::CreateImm(0));
3864 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3865 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3866 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3870 /// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
3871 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3872 /// when they refer multiple MIOperands inside a single one.
3874 cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
3875 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3876 // Create a writeback register dummy placeholder.
3877 Inst.addOperand(MCOperand::CreateImm(0));
3878 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3879 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
3880 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3884 /// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
3885 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3886 /// when they refer multiple MIOperands inside a single one.
3888 cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
3889 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3891 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3892 // Create a writeback register dummy placeholder.
3893 Inst.addOperand(MCOperand::CreateImm(0));
3895 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3897 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
3899 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3903 /// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
3904 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3905 /// when they refer multiple MIOperands inside a single one.
3907 cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
3908 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3910 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3911 // Create a writeback register dummy placeholder.
3912 Inst.addOperand(MCOperand::CreateImm(0));
3914 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3916 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
3918 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3922 /// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
3923 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3924 /// when they refer multiple MIOperands inside a single one.
3926 cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
3927 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3928 // Create a writeback register dummy placeholder.
3929 Inst.addOperand(MCOperand::CreateImm(0));
3931 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3933 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3935 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
3937 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3941 /// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
3942 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3943 /// when they refer multiple MIOperands inside a single one.
3945 cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
3946 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3947 // Create a writeback register dummy placeholder.
3948 Inst.addOperand(MCOperand::CreateImm(0));
3950 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3952 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3954 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
3956 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3960 /// cvtLdrdPre - Convert parsed operands to MCInst.
3961 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3962 /// when they refer multiple MIOperands inside a single one.
3964 cvtLdrdPre(MCInst &Inst, unsigned Opcode,
3965 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3967 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3968 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3969 // Create a writeback register dummy placeholder.
3970 Inst.addOperand(MCOperand::CreateImm(0));
3972 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
3974 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3978 /// cvtStrdPre - Convert parsed operands to MCInst.
3979 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3980 /// when they refer multiple MIOperands inside a single one.
3982 cvtStrdPre(MCInst &Inst, unsigned Opcode,
3983 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3984 // Create a writeback register dummy placeholder.
3985 Inst.addOperand(MCOperand::CreateImm(0));
3987 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3988 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3990 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
3992 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3996 /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
3997 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3998 /// when they refer multiple MIOperands inside a single one.
4000 cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
4001 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4002 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4003 // Create a writeback register dummy placeholder.
4004 Inst.addOperand(MCOperand::CreateImm(0));
4005 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4006 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4010 /// cvtThumbMultiple- Convert parsed operands to MCInst.
4011 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4012 /// when they refer multiple MIOperands inside a single one.
4014 cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
4015 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4016 // The second source operand must be the same register as the destination
4018 if (Operands.size() == 6 &&
4019 (((ARMOperand*)Operands[3])->getReg() !=
4020 ((ARMOperand*)Operands[5])->getReg()) &&
4021 (((ARMOperand*)Operands[3])->getReg() !=
4022 ((ARMOperand*)Operands[4])->getReg())) {
4023 Error(Operands[3]->getStartLoc(),
4024 "destination register must match source register");
4027 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4028 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4029 // If we have a three-operand form, make sure to set Rn to be the operand
4030 // that isn't the same as Rd.
4032 if (Operands.size() == 6 &&
4033 ((ARMOperand*)Operands[4])->getReg() ==
4034 ((ARMOperand*)Operands[3])->getReg())
4036 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4037 Inst.addOperand(Inst.getOperand(0));
4038 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4044 cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
4045 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4047 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4048 // Create a writeback register dummy placeholder.
4049 Inst.addOperand(MCOperand::CreateImm(0));
4051 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4053 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4058 cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
4059 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4061 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4062 // Create a writeback register dummy placeholder.
4063 Inst.addOperand(MCOperand::CreateImm(0));
4065 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4067 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4069 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4074 cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
4075 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4076 // Create a writeback register dummy placeholder.
4077 Inst.addOperand(MCOperand::CreateImm(0));
4079 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4081 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4083 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4088 cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
4089 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4090 // Create a writeback register dummy placeholder.
4091 Inst.addOperand(MCOperand::CreateImm(0));
4093 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4095 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4097 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4099 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4103 /// Parse an ARM memory expression, return false if successful else return true
4104 /// or an error. The first token must be a '[' when called.
4106 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4108 assert(Parser.getTok().is(AsmToken::LBrac) &&
4109 "Token is not a Left Bracket");
4110 S = Parser.getTok().getLoc();
4111 Parser.Lex(); // Eat left bracket token.
4113 const AsmToken &BaseRegTok = Parser.getTok();
4114 int BaseRegNum = tryParseRegister();
4115 if (BaseRegNum == -1)
4116 return Error(BaseRegTok.getLoc(), "register expected");
4118 // The next token must either be a comma or a closing bracket.
4119 const AsmToken &Tok = Parser.getTok();
4120 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
4121 return Error(Tok.getLoc(), "malformed memory operand");
4123 if (Tok.is(AsmToken::RBrac)) {
4125 Parser.Lex(); // Eat right bracket token.
4127 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4128 0, 0, false, S, E));
4130 // If there's a pre-indexing writeback marker, '!', just add it as a token
4131 // operand. It's rather odd, but syntactically valid.
4132 if (Parser.getTok().is(AsmToken::Exclaim)) {
4133 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4134 Parser.Lex(); // Eat the '!'.
4140 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
4141 Parser.Lex(); // Eat the comma.
4143 // If we have a ':', it's an alignment specifier.
4144 if (Parser.getTok().is(AsmToken::Colon)) {
4145 Parser.Lex(); // Eat the ':'.
4146 E = Parser.getTok().getLoc();
4149 if (getParser().ParseExpression(Expr))
4152 // The expression has to be a constant. Memory references with relocations
4153 // don't come through here, as they use the <label> forms of the relevant
4155 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4157 return Error (E, "constant expression expected");
4160 switch (CE->getValue()) {
4163 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4164 case 16: Align = 2; break;
4165 case 32: Align = 4; break;
4166 case 64: Align = 8; break;
4167 case 128: Align = 16; break;
4168 case 256: Align = 32; break;
4171 // Now we should have the closing ']'
4172 E = Parser.getTok().getLoc();
4173 if (Parser.getTok().isNot(AsmToken::RBrac))
4174 return Error(E, "']' expected");
4175 Parser.Lex(); // Eat right bracket token.
4177 // Don't worry about range checking the value here. That's handled by
4178 // the is*() predicates.
4179 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4180 ARM_AM::no_shift, 0, Align,
4183 // If there's a pre-indexing writeback marker, '!', just add it as a token
4185 if (Parser.getTok().is(AsmToken::Exclaim)) {
4186 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4187 Parser.Lex(); // Eat the '!'.
4193 // If we have a '#', it's an immediate offset, else assume it's a register
4194 // offset. Be friendly and also accept a plain integer (without a leading
4195 // hash) for gas compatibility.
4196 if (Parser.getTok().is(AsmToken::Hash) ||
4197 Parser.getTok().is(AsmToken::Dollar) ||
4198 Parser.getTok().is(AsmToken::Integer)) {
4199 if (Parser.getTok().isNot(AsmToken::Integer))
4200 Parser.Lex(); // Eat the '#'.
4201 E = Parser.getTok().getLoc();
4203 bool isNegative = getParser().getTok().is(AsmToken::Minus);
4204 const MCExpr *Offset;
4205 if (getParser().ParseExpression(Offset))
4208 // The expression has to be a constant. Memory references with relocations
4209 // don't come through here, as they use the <label> forms of the relevant
4211 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4213 return Error (E, "constant expression expected");
4215 // If the constant was #-0, represent it as INT32_MIN.
4216 int32_t Val = CE->getValue();
4217 if (isNegative && Val == 0)
4218 CE = MCConstantExpr::Create(INT32_MIN, getContext());
4220 // Now we should have the closing ']'
4221 E = Parser.getTok().getLoc();
4222 if (Parser.getTok().isNot(AsmToken::RBrac))
4223 return Error(E, "']' expected");
4224 Parser.Lex(); // Eat right bracket token.
4226 // Don't worry about range checking the value here. That's handled by
4227 // the is*() predicates.
4228 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4229 ARM_AM::no_shift, 0, 0,
4232 // If there's a pre-indexing writeback marker, '!', just add it as a token
4234 if (Parser.getTok().is(AsmToken::Exclaim)) {
4235 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4236 Parser.Lex(); // Eat the '!'.
4242 // The register offset is optionally preceded by a '+' or '-'
4243 bool isNegative = false;
4244 if (Parser.getTok().is(AsmToken::Minus)) {
4246 Parser.Lex(); // Eat the '-'.
4247 } else if (Parser.getTok().is(AsmToken::Plus)) {
4249 Parser.Lex(); // Eat the '+'.
4252 E = Parser.getTok().getLoc();
4253 int OffsetRegNum = tryParseRegister();
4254 if (OffsetRegNum == -1)
4255 return Error(E, "register expected");
4257 // If there's a shift operator, handle it.
4258 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4259 unsigned ShiftImm = 0;
4260 if (Parser.getTok().is(AsmToken::Comma)) {
4261 Parser.Lex(); // Eat the ','.
4262 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4266 // Now we should have the closing ']'
4267 E = Parser.getTok().getLoc();
4268 if (Parser.getTok().isNot(AsmToken::RBrac))
4269 return Error(E, "']' expected");
4270 Parser.Lex(); // Eat right bracket token.
4272 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4273 ShiftType, ShiftImm, 0, isNegative,
4276 // If there's a pre-indexing writeback marker, '!', just add it as a token
4278 if (Parser.getTok().is(AsmToken::Exclaim)) {
4279 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4280 Parser.Lex(); // Eat the '!'.
4286 /// parseMemRegOffsetShift - one of these two:
4287 /// ( lsl | lsr | asr | ror ) , # shift_amount
4289 /// return true if it parses a shift otherwise it returns false.
4290 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4292 SMLoc Loc = Parser.getTok().getLoc();
4293 const AsmToken &Tok = Parser.getTok();
4294 if (Tok.isNot(AsmToken::Identifier))
4296 StringRef ShiftName = Tok.getString();
4297 if (ShiftName == "lsl" || ShiftName == "LSL" ||
4298 ShiftName == "asl" || ShiftName == "ASL")
4300 else if (ShiftName == "lsr" || ShiftName == "LSR")
4302 else if (ShiftName == "asr" || ShiftName == "ASR")
4304 else if (ShiftName == "ror" || ShiftName == "ROR")
4306 else if (ShiftName == "rrx" || ShiftName == "RRX")
4309 return Error(Loc, "illegal shift operator");
4310 Parser.Lex(); // Eat shift type token.
4312 // rrx stands alone.
4314 if (St != ARM_AM::rrx) {
4315 Loc = Parser.getTok().getLoc();
4316 // A '#' and a shift amount.
4317 const AsmToken &HashTok = Parser.getTok();
4318 if (HashTok.isNot(AsmToken::Hash) &&
4319 HashTok.isNot(AsmToken::Dollar))
4320 return Error(HashTok.getLoc(), "'#' expected");
4321 Parser.Lex(); // Eat hash token.
4324 if (getParser().ParseExpression(Expr))
4326 // Range check the immediate.
4327 // lsl, ror: 0 <= imm <= 31
4328 // lsr, asr: 0 <= imm <= 32
4329 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4331 return Error(Loc, "shift amount must be an immediate");
4332 int64_t Imm = CE->getValue();
4334 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4335 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4336 return Error(Loc, "immediate shift value out of range");
4343 /// parseFPImm - A floating point immediate expression operand.
4344 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4345 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4346 // Anything that can accept a floating point constant as an operand
4347 // needs to go through here, as the regular ParseExpression is
4350 // This routine still creates a generic Immediate operand, containing
4351 // a bitcast of the 64-bit floating point value. The various operands
4352 // that accept floats can check whether the value is valid for them
4353 // via the standard is*() predicates.
4355 SMLoc S = Parser.getTok().getLoc();
4357 if (Parser.getTok().isNot(AsmToken::Hash) &&
4358 Parser.getTok().isNot(AsmToken::Dollar))
4359 return MatchOperand_NoMatch;
4361 // Disambiguate the VMOV forms that can accept an FP immediate.
4362 // vmov.f32 <sreg>, #imm
4363 // vmov.f64 <dreg>, #imm
4364 // vmov.f32 <dreg>, #imm @ vector f32x2
4365 // vmov.f32 <qreg>, #imm @ vector f32x4
4367 // There are also the NEON VMOV instructions which expect an
4368 // integer constant. Make sure we don't try to parse an FPImm
4370 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4371 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4372 if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
4373 TyOp->getToken() != ".f64"))
4374 return MatchOperand_NoMatch;
4376 Parser.Lex(); // Eat the '#'.
4378 // Handle negation, as that still comes through as a separate token.
4379 bool isNegative = false;
4380 if (Parser.getTok().is(AsmToken::Minus)) {
4384 const AsmToken &Tok = Parser.getTok();
4385 SMLoc Loc = Tok.getLoc();
4386 if (Tok.is(AsmToken::Real)) {
4387 APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4388 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4389 // If we had a '-' in front, toggle the sign bit.
4390 IntVal ^= (uint64_t)isNegative << 31;
4391 Parser.Lex(); // Eat the token.
4392 Operands.push_back(ARMOperand::CreateImm(
4393 MCConstantExpr::Create(IntVal, getContext()),
4394 S, Parser.getTok().getLoc()));
4395 return MatchOperand_Success;
4397 // Also handle plain integers. Instructions which allow floating point
4398 // immediates also allow a raw encoded 8-bit value.
4399 if (Tok.is(AsmToken::Integer)) {
4400 int64_t Val = Tok.getIntVal();
4401 Parser.Lex(); // Eat the token.
4402 if (Val > 255 || Val < 0) {
4403 Error(Loc, "encoded floating point value out of range");
4404 return MatchOperand_ParseFail;
4406 double RealVal = ARM_AM::getFPImmFloat(Val);
4407 Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue();
4408 Operands.push_back(ARMOperand::CreateImm(
4409 MCConstantExpr::Create(Val, getContext()), S,
4410 Parser.getTok().getLoc()));
4411 return MatchOperand_Success;
4414 Error(Loc, "invalid floating point immediate");
4415 return MatchOperand_ParseFail;
4418 /// Parse a arm instruction operand. For now this parses the operand regardless
4419 /// of the mnemonic.
4420 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4421 StringRef Mnemonic) {
4424 // Check if the current operand has a custom associated parser, if so, try to
4425 // custom parse the operand, or fallback to the general approach.
4426 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4427 if (ResTy == MatchOperand_Success)
4429 // If there wasn't a custom match, try the generic matcher below. Otherwise,
4430 // there was a match, but an error occurred, in which case, just return that
4431 // the operand parsing failed.
4432 if (ResTy == MatchOperand_ParseFail)
4435 switch (getLexer().getKind()) {
4437 Error(Parser.getTok().getLoc(), "unexpected token in operand");
4439 case AsmToken::Identifier: {
4440 if (!tryParseRegisterWithWriteBack(Operands))
4442 int Res = tryParseShiftRegister(Operands);
4443 if (Res == 0) // success
4445 else if (Res == -1) // irrecoverable error
4447 // If this is VMRS, check for the apsr_nzcv operand.
4448 if (Mnemonic == "vmrs" &&
4449 Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4450 S = Parser.getTok().getLoc();
4452 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4456 // Fall though for the Identifier case that is not a register or a
4459 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
4460 case AsmToken::Integer: // things like 1f and 2b as a branch targets
4461 case AsmToken::String: // quoted label names.
4462 case AsmToken::Dot: { // . as a branch target
4463 // This was not a register so parse other operands that start with an
4464 // identifier (like labels) as expressions and create them as immediates.
4465 const MCExpr *IdVal;
4466 S = Parser.getTok().getLoc();
4467 if (getParser().ParseExpression(IdVal))
4469 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4470 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4473 case AsmToken::LBrac:
4474 return parseMemory(Operands);
4475 case AsmToken::LCurly:
4476 return parseRegisterList(Operands);
4477 case AsmToken::Dollar:
4478 case AsmToken::Hash: {
4479 // #42 -> immediate.
4480 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
4481 S = Parser.getTok().getLoc();
4483 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4484 const MCExpr *ImmVal;
4485 if (getParser().ParseExpression(ImmVal))
4487 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4489 int32_t Val = CE->getValue();
4490 if (isNegative && Val == 0)
4491 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4493 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4494 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4497 case AsmToken::Colon: {
4498 // ":lower16:" and ":upper16:" expression prefixes
4499 // FIXME: Check it's an expression prefix,
4500 // e.g. (FOO - :lower16:BAR) isn't legal.
4501 ARMMCExpr::VariantKind RefKind;
4502 if (parsePrefix(RefKind))
4505 const MCExpr *SubExprVal;
4506 if (getParser().ParseExpression(SubExprVal))
4509 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4511 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4512 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4518 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4519 // :lower16: and :upper16:.
4520 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4521 RefKind = ARMMCExpr::VK_ARM_None;
4523 // :lower16: and :upper16: modifiers
4524 assert(getLexer().is(AsmToken::Colon) && "expected a :");
4525 Parser.Lex(); // Eat ':'
4527 if (getLexer().isNot(AsmToken::Identifier)) {
4528 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4532 StringRef IDVal = Parser.getTok().getIdentifier();
4533 if (IDVal == "lower16") {
4534 RefKind = ARMMCExpr::VK_ARM_LO16;
4535 } else if (IDVal == "upper16") {
4536 RefKind = ARMMCExpr::VK_ARM_HI16;
4538 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4543 if (getLexer().isNot(AsmToken::Colon)) {
4544 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4547 Parser.Lex(); // Eat the last ':'
4551 /// \brief Given a mnemonic, split out possible predication code and carry
4552 /// setting letters to form a canonical mnemonic and flags.
4554 // FIXME: Would be nice to autogen this.
4555 // FIXME: This is a bit of a maze of special cases.
4556 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4557 unsigned &PredicationCode,
4559 unsigned &ProcessorIMod,
4560 StringRef &ITMask) {
4561 PredicationCode = ARMCC::AL;
4562 CarrySetting = false;
4565 // Ignore some mnemonics we know aren't predicated forms.
4567 // FIXME: Would be nice to autogen this.
4568 if ((Mnemonic == "movs" && isThumb()) ||
4569 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
4570 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
4571 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
4572 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
4573 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
4574 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
4575 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4576 Mnemonic == "fmuls")
4579 // First, split out any predication code. Ignore mnemonics we know aren't
4580 // predicated but do have a carry-set and so weren't caught above.
4581 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4582 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4583 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4584 Mnemonic != "sbcs" && Mnemonic != "rscs") {
4585 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4586 .Case("eq", ARMCC::EQ)
4587 .Case("ne", ARMCC::NE)
4588 .Case("hs", ARMCC::HS)
4589 .Case("cs", ARMCC::HS)
4590 .Case("lo", ARMCC::LO)
4591 .Case("cc", ARMCC::LO)
4592 .Case("mi", ARMCC::MI)
4593 .Case("pl", ARMCC::PL)
4594 .Case("vs", ARMCC::VS)
4595 .Case("vc", ARMCC::VC)
4596 .Case("hi", ARMCC::HI)
4597 .Case("ls", ARMCC::LS)
4598 .Case("ge", ARMCC::GE)
4599 .Case("lt", ARMCC::LT)
4600 .Case("gt", ARMCC::GT)
4601 .Case("le", ARMCC::LE)
4602 .Case("al", ARMCC::AL)
4605 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4606 PredicationCode = CC;
4610 // Next, determine if we have a carry setting bit. We explicitly ignore all
4611 // the instructions we know end in 's'.
4612 if (Mnemonic.endswith("s") &&
4613 !(Mnemonic == "cps" || Mnemonic == "mls" ||
4614 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4615 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4616 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4617 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4618 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4619 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4620 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
4621 (Mnemonic == "movs" && isThumb()))) {
4622 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4623 CarrySetting = true;
4626 // The "cps" instruction can have a interrupt mode operand which is glued into
4627 // the mnemonic. Check if this is the case, split it and parse the imod op
4628 if (Mnemonic.startswith("cps")) {
4629 // Split out any imod code.
4631 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4632 .Case("ie", ARM_PROC::IE)
4633 .Case("id", ARM_PROC::ID)
4636 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4637 ProcessorIMod = IMod;
4641 // The "it" instruction has the condition mask on the end of the mnemonic.
4642 if (Mnemonic.startswith("it")) {
4643 ITMask = Mnemonic.slice(2, Mnemonic.size());
4644 Mnemonic = Mnemonic.slice(0, 2);
4650 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
4651 /// inclusion of carry set or predication code operands.
4653 // FIXME: It would be nice to autogen this.
4655 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
4656 bool &CanAcceptPredicationCode) {
4657 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4658 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4659 Mnemonic == "add" || Mnemonic == "adc" ||
4660 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4661 Mnemonic == "orr" || Mnemonic == "mvn" ||
4662 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4663 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4664 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4665 Mnemonic == "mla" || Mnemonic == "smlal" ||
4666 Mnemonic == "umlal" || Mnemonic == "umull"))) {
4667 CanAcceptCarrySet = true;
4669 CanAcceptCarrySet = false;
4671 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
4672 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
4673 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
4674 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
4675 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
4676 (Mnemonic == "clrex" && !isThumb()) ||
4677 (Mnemonic == "nop" && isThumbOne()) ||
4678 ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" ||
4679 Mnemonic == "ldc2" || Mnemonic == "ldc2l" ||
4680 Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) ||
4681 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
4683 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
4684 CanAcceptPredicationCode = false;
4686 CanAcceptPredicationCode = true;
4689 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
4690 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
4691 CanAcceptPredicationCode = false;
4695 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4696 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4697 // FIXME: This is all horribly hacky. We really need a better way to deal
4698 // with optional operands like this in the matcher table.
4700 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4701 // another does not. Specifically, the MOVW instruction does not. So we
4702 // special case it here and remove the defaulted (non-setting) cc_out
4703 // operand if that's the instruction we're trying to match.
4705 // We do this as post-processing of the explicit operands rather than just
4706 // conditionally adding the cc_out in the first place because we need
4707 // to check the type of the parsed immediate operand.
4708 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4709 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4710 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4711 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4714 // Register-register 'add' for thumb does not have a cc_out operand
4715 // when there are only two register operands.
4716 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4717 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4718 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4719 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4721 // Register-register 'add' for thumb does not have a cc_out operand
4722 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4723 // have to check the immediate range here since Thumb2 has a variant
4724 // that can handle a different range and has a cc_out operand.
4725 if (((isThumb() && Mnemonic == "add") ||
4726 (isThumbTwo() && Mnemonic == "sub")) &&
4727 Operands.size() == 6 &&
4728 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4729 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4730 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4731 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4732 (static_cast<ARMOperand*>(Operands[5])->isReg() ||
4733 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4735 // For Thumb2, add/sub immediate does not have a cc_out operand for the
4736 // imm0_4095 variant. That's the least-preferred variant when
4737 // selecting via the generic "add" mnemonic, so to know that we
4738 // should remove the cc_out operand, we have to explicitly check that
4739 // it's not one of the other variants. Ugh.
4740 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4741 Operands.size() == 6 &&
4742 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4743 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4744 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4745 // Nest conditions rather than one big 'if' statement for readability.
4747 // If either register is a high reg, it's either one of the SP
4748 // variants (handled above) or a 32-bit encoding, so we just
4749 // check against T3. If the second register is the PC, this is an
4750 // alternate form of ADR, which uses encoding T4, so check for that too.
4751 if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4752 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
4753 static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
4754 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
4756 // If both registers are low, we're in an IT block, and the immediate is
4757 // in range, we should use encoding T1 instead, which has a cc_out.
4759 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4760 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4761 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
4764 // Otherwise, we use encoding T4, which does not have a cc_out
4769 // The thumb2 multiply instruction doesn't have a CCOut register, so
4770 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
4771 // use the 16-bit encoding or not.
4772 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
4773 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4774 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4775 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4776 static_cast<ARMOperand*>(Operands[5])->isReg() &&
4777 // If the registers aren't low regs, the destination reg isn't the
4778 // same as one of the source regs, or the cc_out operand is zero
4779 // outside of an IT block, we have to use the 32-bit encoding, so
4780 // remove the cc_out operand.
4781 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4782 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4783 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
4785 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4786 static_cast<ARMOperand*>(Operands[5])->getReg() &&
4787 static_cast<ARMOperand*>(Operands[3])->getReg() !=
4788 static_cast<ARMOperand*>(Operands[4])->getReg())))
4791 // Also check the 'mul' syntax variant that doesn't specify an explicit
4792 // destination register.
4793 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
4794 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4795 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4796 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4797 // If the registers aren't low regs or the cc_out operand is zero
4798 // outside of an IT block, we have to use the 32-bit encoding, so
4799 // remove the cc_out operand.
4800 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4801 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4807 // Register-register 'add/sub' for thumb does not have a cc_out operand
4808 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
4809 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
4810 // right, this will result in better diagnostics (which operand is off)
4812 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
4813 (Operands.size() == 5 || Operands.size() == 6) &&
4814 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4815 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4816 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4822 static bool isDataTypeToken(StringRef Tok) {
4823 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
4824 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
4825 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
4826 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
4827 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
4828 Tok == ".f" || Tok == ".d";
4831 // FIXME: This bit should probably be handled via an explicit match class
4832 // in the .td files that matches the suffix instead of having it be
4833 // a literal string token the way it is now.
4834 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
4835 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
4838 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features);
4839 /// Parse an arm instruction mnemonic followed by its operands.
4840 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
4841 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4842 // Apply mnemonic aliases before doing anything else, as the destination
4843 // mnemnonic may include suffices and we want to handle them normally.
4844 // The generic tblgen'erated code does this later, at the start of
4845 // MatchInstructionImpl(), but that's too late for aliases that include
4846 // any sort of suffix.
4847 unsigned AvailableFeatures = getAvailableFeatures();
4848 applyMnemonicAliases(Name, AvailableFeatures);
4850 // First check for the ARM-specific .req directive.
4851 if (Parser.getTok().is(AsmToken::Identifier) &&
4852 Parser.getTok().getIdentifier() == ".req") {
4853 parseDirectiveReq(Name, NameLoc);
4854 // We always return 'error' for this, as we're done with this
4855 // statement and don't need to match the 'instruction."
4859 // Create the leading tokens for the mnemonic, split by '.' characters.
4860 size_t Start = 0, Next = Name.find('.');
4861 StringRef Mnemonic = Name.slice(Start, Next);
4863 // Split out the predication code and carry setting flag from the mnemonic.
4864 unsigned PredicationCode;
4865 unsigned ProcessorIMod;
4868 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
4869 ProcessorIMod, ITMask);
4871 // In Thumb1, only the branch (B) instruction can be predicated.
4872 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
4873 Parser.EatToEndOfStatement();
4874 return Error(NameLoc, "conditional execution not supported in Thumb1");
4877 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
4879 // Handle the IT instruction ITMask. Convert it to a bitmask. This
4880 // is the mask as it will be for the IT encoding if the conditional
4881 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
4882 // where the conditional bit0 is zero, the instruction post-processing
4883 // will adjust the mask accordingly.
4884 if (Mnemonic == "it") {
4885 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
4886 if (ITMask.size() > 3) {
4887 Parser.EatToEndOfStatement();
4888 return Error(Loc, "too many conditions on IT instruction");
4891 for (unsigned i = ITMask.size(); i != 0; --i) {
4892 char pos = ITMask[i - 1];
4893 if (pos != 't' && pos != 'e') {
4894 Parser.EatToEndOfStatement();
4895 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
4898 if (ITMask[i - 1] == 't')
4901 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
4904 // FIXME: This is all a pretty gross hack. We should automatically handle
4905 // optional operands like this via tblgen.
4907 // Next, add the CCOut and ConditionCode operands, if needed.
4909 // For mnemonics which can ever incorporate a carry setting bit or predication
4910 // code, our matching model involves us always generating CCOut and
4911 // ConditionCode operands to match the mnemonic "as written" and then we let
4912 // the matcher deal with finding the right instruction or generating an
4913 // appropriate error.
4914 bool CanAcceptCarrySet, CanAcceptPredicationCode;
4915 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
4917 // If we had a carry-set on an instruction that can't do that, issue an
4919 if (!CanAcceptCarrySet && CarrySetting) {
4920 Parser.EatToEndOfStatement();
4921 return Error(NameLoc, "instruction '" + Mnemonic +
4922 "' can not set flags, but 's' suffix specified");
4924 // If we had a predication code on an instruction that can't do that, issue an
4926 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
4927 Parser.EatToEndOfStatement();
4928 return Error(NameLoc, "instruction '" + Mnemonic +
4929 "' is not predicable, but condition code specified");
4932 // Add the carry setting operand, if necessary.
4933 if (CanAcceptCarrySet) {
4934 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
4935 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
4939 // Add the predication code operand, if necessary.
4940 if (CanAcceptPredicationCode) {
4941 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
4943 Operands.push_back(ARMOperand::CreateCondCode(
4944 ARMCC::CondCodes(PredicationCode), Loc));
4947 // Add the processor imod operand, if necessary.
4948 if (ProcessorIMod) {
4949 Operands.push_back(ARMOperand::CreateImm(
4950 MCConstantExpr::Create(ProcessorIMod, getContext()),
4954 // Add the remaining tokens in the mnemonic.
4955 while (Next != StringRef::npos) {
4957 Next = Name.find('.', Start + 1);
4958 StringRef ExtraToken = Name.slice(Start, Next);
4960 // Some NEON instructions have an optional datatype suffix that is
4961 // completely ignored. Check for that.
4962 if (isDataTypeToken(ExtraToken) &&
4963 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
4966 if (ExtraToken != ".n") {
4967 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
4968 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
4972 // Read the remaining operands.
4973 if (getLexer().isNot(AsmToken::EndOfStatement)) {
4974 // Read the first operand.
4975 if (parseOperand(Operands, Mnemonic)) {
4976 Parser.EatToEndOfStatement();
4980 while (getLexer().is(AsmToken::Comma)) {
4981 Parser.Lex(); // Eat the comma.
4983 // Parse and remember the operand.
4984 if (parseOperand(Operands, Mnemonic)) {
4985 Parser.EatToEndOfStatement();
4991 if (getLexer().isNot(AsmToken::EndOfStatement)) {
4992 SMLoc Loc = getLexer().getLoc();
4993 Parser.EatToEndOfStatement();
4994 return Error(Loc, "unexpected token in argument list");
4997 Parser.Lex(); // Consume the EndOfStatement
4999 // Some instructions, mostly Thumb, have forms for the same mnemonic that
5000 // do and don't have a cc_out optional-def operand. With some spot-checks
5001 // of the operand list, we can figure out which variant we're trying to
5002 // parse and adjust accordingly before actually matching. We shouldn't ever
5003 // try to remove a cc_out operand that was explicitly set on the the
5004 // mnemonic, of course (CarrySetting == true). Reason number #317 the
5005 // table driven matcher doesn't fit well with the ARM instruction set.
5006 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5007 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5008 Operands.erase(Operands.begin() + 1);
5012 // ARM mode 'blx' need special handling, as the register operand version
5013 // is predicable, but the label operand version is not. So, we can't rely
5014 // on the Mnemonic based checking to correctly figure out when to put
5015 // a k_CondCode operand in the list. If we're trying to match the label
5016 // version, remove the k_CondCode operand here.
5017 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5018 static_cast<ARMOperand*>(Operands[2])->isImm()) {
5019 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5020 Operands.erase(Operands.begin() + 1);
5024 // The vector-compare-to-zero instructions have a literal token "#0" at
5025 // the end that comes to here as an immediate operand. Convert it to a
5026 // token to play nicely with the matcher.
5027 if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
5028 Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
5029 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5030 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
5031 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5032 if (CE && CE->getValue() == 0) {
5033 Operands.erase(Operands.begin() + 5);
5034 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5038 // VCMP{E} does the same thing, but with a different operand count.
5039 if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 &&
5040 static_cast<ARMOperand*>(Operands[4])->isImm()) {
5041 ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]);
5042 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5043 if (CE && CE->getValue() == 0) {
5044 Operands.erase(Operands.begin() + 4);
5045 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5049 // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
5050 // end. Convert it to a token here. Take care not to convert those
5051 // that should hit the Thumb2 encoding.
5052 if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
5053 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5054 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5055 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5056 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
5057 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5058 if (CE && CE->getValue() == 0 &&
5060 // The cc_out operand matches the IT block.
5061 ((inITBlock() != CarrySetting) &&
5062 // Neither register operand is a high register.
5063 (isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
5064 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()))))){
5065 Operands.erase(Operands.begin() + 5);
5066 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5074 // Validate context-sensitive operand constraints.
5076 // return 'true' if register list contains non-low GPR registers,
5077 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5078 // 'containsReg' to true.
5079 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5080 unsigned HiReg, bool &containsReg) {
5081 containsReg = false;
5082 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5083 unsigned OpReg = Inst.getOperand(i).getReg();
5086 // Anything other than a low register isn't legal here.
5087 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5093 // Check if the specified regisgter is in the register list of the inst,
5094 // starting at the indicated operand number.
5095 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5096 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5097 unsigned OpReg = Inst.getOperand(i).getReg();
5104 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around
5105 // the ARMInsts array) instead. Getting that here requires awkward
5106 // API changes, though. Better way?
5108 extern const MCInstrDesc ARMInsts[];
5110 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
5111 return ARMInsts[Opcode];
5114 // FIXME: We would really like to be able to tablegen'erate this.
5116 validateInstruction(MCInst &Inst,
5117 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5118 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
5119 SMLoc Loc = Operands[0]->getStartLoc();
5120 // Check the IT block state first.
5121 // NOTE: BKPT instruction has the interesting property of being
5122 // allowed in IT blocks, but not being predicable. It just always
5124 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT &&
5125 Inst.getOpcode() != ARM::BKPT) {
5127 if (ITState.FirstCond)
5128 ITState.FirstCond = false;
5130 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5131 // The instruction must be predicable.
5132 if (!MCID.isPredicable())
5133 return Error(Loc, "instructions in IT block must be predicable");
5134 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5135 unsigned ITCond = bit ? ITState.Cond :
5136 ARMCC::getOppositeCondition(ITState.Cond);
5137 if (Cond != ITCond) {
5138 // Find the condition code Operand to get its SMLoc information.
5140 for (unsigned i = 1; i < Operands.size(); ++i)
5141 if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
5142 CondLoc = Operands[i]->getStartLoc();
5143 return Error(CondLoc, "incorrect condition in IT block; got '" +
5144 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5145 "', but expected '" +
5146 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5148 // Check for non-'al' condition codes outside of the IT block.
5149 } else if (isThumbTwo() && MCID.isPredicable() &&
5150 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5151 ARMCC::AL && Inst.getOpcode() != ARM::tB &&
5152 Inst.getOpcode() != ARM::t2B)
5153 return Error(Loc, "predicated instructions must be in IT block");
5155 switch (Inst.getOpcode()) {
5158 case ARM::LDRD_POST:
5160 // Rt2 must be Rt + 1.
5161 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
5162 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
5164 return Error(Operands[3]->getStartLoc(),
5165 "destination operands must be sequential");
5169 // Rt2 must be Rt + 1.
5170 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
5171 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
5173 return Error(Operands[3]->getStartLoc(),
5174 "source operands must be sequential");
5178 case ARM::STRD_POST:
5180 // Rt2 must be Rt + 1.
5181 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
5182 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
5184 return Error(Operands[3]->getStartLoc(),
5185 "source operands must be sequential");
5190 // width must be in range [1, 32-lsb]
5191 unsigned lsb = Inst.getOperand(2).getImm();
5192 unsigned widthm1 = Inst.getOperand(3).getImm();
5193 if (widthm1 >= 32 - lsb)
5194 return Error(Operands[5]->getStartLoc(),
5195 "bitfield width must be in range [1,32-lsb]");
5199 // If we're parsing Thumb2, the .w variant is available and handles
5200 // most cases that are normally illegal for a Thumb1 LDM
5201 // instruction. We'll make the transformation in processInstruction()
5204 // Thumb LDM instructions are writeback iff the base register is not
5205 // in the register list.
5206 unsigned Rn = Inst.getOperand(0).getReg();
5207 bool hasWritebackToken =
5208 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5209 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5210 bool listContainsBase;
5211 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
5212 return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
5213 "registers must be in range r0-r7");
5214 // If we should have writeback, then there should be a '!' token.
5215 if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
5216 return Error(Operands[2]->getStartLoc(),
5217 "writeback operator '!' expected");
5218 // If we should not have writeback, there must not be a '!'. This is
5219 // true even for the 32-bit wide encodings.
5220 if (listContainsBase && hasWritebackToken)
5221 return Error(Operands[3]->getStartLoc(),
5222 "writeback operator '!' not allowed when base register "
5223 "in register list");
5227 case ARM::t2LDMIA_UPD: {
5228 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5229 return Error(Operands[4]->getStartLoc(),
5230 "writeback operator '!' not allowed when base register "
5231 "in register list");
5234 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5235 // so only issue a diagnostic for thumb1. The instructions will be
5236 // switched to the t2 encodings in processInstruction() if necessary.
5238 bool listContainsBase;
5239 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
5241 return Error(Operands[2]->getStartLoc(),
5242 "registers must be in range r0-r7 or pc");
5246 bool listContainsBase;
5247 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
5249 return Error(Operands[2]->getStartLoc(),
5250 "registers must be in range r0-r7 or lr");
5253 case ARM::tSTMIA_UPD: {
5254 bool listContainsBase;
5255 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
5256 return Error(Operands[4]->getStartLoc(),
5257 "registers must be in range r0-r7");
5265 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5267 default: llvm_unreachable("unexpected opcode!");
5269 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5270 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5271 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5272 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5273 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5274 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5275 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
5276 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5277 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5280 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5281 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5282 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5283 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5284 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5286 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5287 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5288 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5289 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5290 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5292 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
5293 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5294 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5295 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5296 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5299 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5300 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5301 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5302 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5303 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5304 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5305 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5306 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5307 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5308 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5309 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
5310 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5311 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5312 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5313 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5316 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5317 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5318 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5319 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5320 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5321 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5322 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5323 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5324 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5325 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5326 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5327 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5328 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
5329 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5330 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5331 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
5332 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5333 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5336 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5337 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5338 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5339 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5340 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5341 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5342 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5343 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5344 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5345 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5346 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
5347 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5348 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5349 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5350 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5353 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5354 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5355 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5356 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5357 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5358 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5359 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5360 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5361 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5362 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5363 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5364 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5365 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
5366 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5367 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5368 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
5369 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5370 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5374 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
5376 default: llvm_unreachable("unexpected opcode!");
5378 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5379 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5380 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5381 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5382 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5383 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5384 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
5385 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5386 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5389 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5390 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5391 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5392 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5393 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5394 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5395 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5396 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5397 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5398 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5399 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
5400 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5401 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5402 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5403 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5406 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5407 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5408 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5409 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5410 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5411 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5412 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5413 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5414 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5415 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5416 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5417 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5418 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
5419 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5420 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5421 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5422 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5423 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5426 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5427 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5428 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5429 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5430 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5431 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5432 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5433 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5434 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5435 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5436 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
5437 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5438 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5439 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5440 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5443 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5444 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5445 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5446 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5447 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5448 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5449 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5450 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5451 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5452 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5453 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5454 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5455 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
5456 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5457 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5458 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
5459 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5460 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
5463 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5464 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5465 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5466 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
5467 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5468 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5469 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5470 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5471 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5472 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5473 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
5474 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5475 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5476 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5477 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5480 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5481 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5482 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5483 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5484 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5485 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5486 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5487 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5488 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5489 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
5490 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
5491 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5492 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
5493 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
5494 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
5495 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
5496 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
5497 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
5500 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5501 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5502 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5503 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5504 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5505 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5506 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5507 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5508 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5509 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5510 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5511 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5512 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
5513 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
5514 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
5515 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
5516 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
5517 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
5522 processInstruction(MCInst &Inst,
5523 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5524 switch (Inst.getOpcode()) {
5525 // Aliases for alternate PC+imm syntax of LDR instructions.
5526 case ARM::t2LDRpcrel:
5527 Inst.setOpcode(ARM::t2LDRpci);
5529 case ARM::t2LDRBpcrel:
5530 Inst.setOpcode(ARM::t2LDRBpci);
5532 case ARM::t2LDRHpcrel:
5533 Inst.setOpcode(ARM::t2LDRHpci);
5535 case ARM::t2LDRSBpcrel:
5536 Inst.setOpcode(ARM::t2LDRSBpci);
5538 case ARM::t2LDRSHpcrel:
5539 Inst.setOpcode(ARM::t2LDRSHpci);
5541 // Handle NEON VST complex aliases.
5542 case ARM::VST1LNdWB_register_Asm_8:
5543 case ARM::VST1LNdWB_register_Asm_16:
5544 case ARM::VST1LNdWB_register_Asm_32: {
5546 // Shuffle the operands around so the lane index operand is in the
5549 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5550 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5551 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5552 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5553 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5554 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5555 TmpInst.addOperand(Inst.getOperand(1)); // lane
5556 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5557 TmpInst.addOperand(Inst.getOperand(6));
5562 case ARM::VST2LNdWB_register_Asm_8:
5563 case ARM::VST2LNdWB_register_Asm_16:
5564 case ARM::VST2LNdWB_register_Asm_32:
5565 case ARM::VST2LNqWB_register_Asm_16:
5566 case ARM::VST2LNqWB_register_Asm_32: {
5568 // Shuffle the operands around so the lane index operand is in the
5571 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5572 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5573 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5574 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5575 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5576 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5577 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5579 TmpInst.addOperand(Inst.getOperand(1)); // lane
5580 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5581 TmpInst.addOperand(Inst.getOperand(6));
5586 case ARM::VST3LNdWB_register_Asm_8:
5587 case ARM::VST3LNdWB_register_Asm_16:
5588 case ARM::VST3LNdWB_register_Asm_32:
5589 case ARM::VST3LNqWB_register_Asm_16:
5590 case ARM::VST3LNqWB_register_Asm_32: {
5592 // Shuffle the operands around so the lane index operand is in the
5595 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5596 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5597 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5598 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5599 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5600 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5601 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5603 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5605 TmpInst.addOperand(Inst.getOperand(1)); // lane
5606 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5607 TmpInst.addOperand(Inst.getOperand(6));
5612 case ARM::VST4LNdWB_register_Asm_8:
5613 case ARM::VST4LNdWB_register_Asm_16:
5614 case ARM::VST4LNdWB_register_Asm_32:
5615 case ARM::VST4LNqWB_register_Asm_16:
5616 case ARM::VST4LNqWB_register_Asm_32: {
5618 // Shuffle the operands around so the lane index operand is in the
5621 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5622 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5623 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5624 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5625 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5626 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5627 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5629 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5631 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5633 TmpInst.addOperand(Inst.getOperand(1)); // lane
5634 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5635 TmpInst.addOperand(Inst.getOperand(6));
5640 case ARM::VST1LNdWB_fixed_Asm_8:
5641 case ARM::VST1LNdWB_fixed_Asm_16:
5642 case ARM::VST1LNdWB_fixed_Asm_32: {
5644 // Shuffle the operands around so the lane index operand is in the
5647 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5648 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5649 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5650 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5651 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5652 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5653 TmpInst.addOperand(Inst.getOperand(1)); // lane
5654 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5655 TmpInst.addOperand(Inst.getOperand(5));
5660 case ARM::VST2LNdWB_fixed_Asm_8:
5661 case ARM::VST2LNdWB_fixed_Asm_16:
5662 case ARM::VST2LNdWB_fixed_Asm_32:
5663 case ARM::VST2LNqWB_fixed_Asm_16:
5664 case ARM::VST2LNqWB_fixed_Asm_32: {
5666 // Shuffle the operands around so the lane index operand is in the
5669 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5670 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5671 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5672 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5673 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5674 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5675 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5677 TmpInst.addOperand(Inst.getOperand(1)); // lane
5678 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5679 TmpInst.addOperand(Inst.getOperand(5));
5684 case ARM::VST3LNdWB_fixed_Asm_8:
5685 case ARM::VST3LNdWB_fixed_Asm_16:
5686 case ARM::VST3LNdWB_fixed_Asm_32:
5687 case ARM::VST3LNqWB_fixed_Asm_16:
5688 case ARM::VST3LNqWB_fixed_Asm_32: {
5690 // Shuffle the operands around so the lane index operand is in the
5693 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5694 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5695 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5696 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5697 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5698 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5699 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5701 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5703 TmpInst.addOperand(Inst.getOperand(1)); // lane
5704 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5705 TmpInst.addOperand(Inst.getOperand(5));
5710 case ARM::VST4LNdWB_fixed_Asm_8:
5711 case ARM::VST4LNdWB_fixed_Asm_16:
5712 case ARM::VST4LNdWB_fixed_Asm_32:
5713 case ARM::VST4LNqWB_fixed_Asm_16:
5714 case ARM::VST4LNqWB_fixed_Asm_32: {
5716 // Shuffle the operands around so the lane index operand is in the
5719 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5720 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5721 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5722 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5723 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5724 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5725 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5727 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5729 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5731 TmpInst.addOperand(Inst.getOperand(1)); // lane
5732 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5733 TmpInst.addOperand(Inst.getOperand(5));
5738 case ARM::VST1LNdAsm_8:
5739 case ARM::VST1LNdAsm_16:
5740 case ARM::VST1LNdAsm_32: {
5742 // Shuffle the operands around so the lane index operand is in the
5745 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5746 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5747 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5748 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5749 TmpInst.addOperand(Inst.getOperand(1)); // lane
5750 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5751 TmpInst.addOperand(Inst.getOperand(5));
5756 case ARM::VST2LNdAsm_8:
5757 case ARM::VST2LNdAsm_16:
5758 case ARM::VST2LNdAsm_32:
5759 case ARM::VST2LNqAsm_16:
5760 case ARM::VST2LNqAsm_32: {
5762 // Shuffle the operands around so the lane index operand is in the
5765 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5766 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5767 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5768 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5769 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5771 TmpInst.addOperand(Inst.getOperand(1)); // lane
5772 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5773 TmpInst.addOperand(Inst.getOperand(5));
5778 case ARM::VST3LNdAsm_8:
5779 case ARM::VST3LNdAsm_16:
5780 case ARM::VST3LNdAsm_32:
5781 case ARM::VST3LNqAsm_16:
5782 case ARM::VST3LNqAsm_32: {
5784 // Shuffle the operands around so the lane index operand is in the
5787 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5788 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5789 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5790 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5791 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5793 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5795 TmpInst.addOperand(Inst.getOperand(1)); // lane
5796 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5797 TmpInst.addOperand(Inst.getOperand(5));
5802 case ARM::VST4LNdAsm_8:
5803 case ARM::VST4LNdAsm_16:
5804 case ARM::VST4LNdAsm_32:
5805 case ARM::VST4LNqAsm_16:
5806 case ARM::VST4LNqAsm_32: {
5808 // Shuffle the operands around so the lane index operand is in the
5811 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5812 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5813 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5814 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5815 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5817 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5819 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5821 TmpInst.addOperand(Inst.getOperand(1)); // lane
5822 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5823 TmpInst.addOperand(Inst.getOperand(5));
5828 // Handle NEON VLD complex aliases.
5829 case ARM::VLD1LNdWB_register_Asm_8:
5830 case ARM::VLD1LNdWB_register_Asm_16:
5831 case ARM::VLD1LNdWB_register_Asm_32: {
5833 // Shuffle the operands around so the lane index operand is in the
5836 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
5837 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5838 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5839 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5840 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5841 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5842 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5843 TmpInst.addOperand(Inst.getOperand(1)); // lane
5844 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5845 TmpInst.addOperand(Inst.getOperand(6));
5850 case ARM::VLD2LNdWB_register_Asm_8:
5851 case ARM::VLD2LNdWB_register_Asm_16:
5852 case ARM::VLD2LNdWB_register_Asm_32:
5853 case ARM::VLD2LNqWB_register_Asm_16:
5854 case ARM::VLD2LNqWB_register_Asm_32: {
5856 // Shuffle the operands around so the lane index operand is in the
5859 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
5860 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5861 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5863 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5864 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5865 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5866 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5867 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5868 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5870 TmpInst.addOperand(Inst.getOperand(1)); // lane
5871 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5872 TmpInst.addOperand(Inst.getOperand(6));
5877 case ARM::VLD3LNdWB_register_Asm_8:
5878 case ARM::VLD3LNdWB_register_Asm_16:
5879 case ARM::VLD3LNdWB_register_Asm_32:
5880 case ARM::VLD3LNqWB_register_Asm_16:
5881 case ARM::VLD3LNqWB_register_Asm_32: {
5883 // Shuffle the operands around so the lane index operand is in the
5886 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
5887 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5888 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5890 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5892 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5893 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5894 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5895 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5896 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5897 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5899 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5901 TmpInst.addOperand(Inst.getOperand(1)); // lane
5902 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5903 TmpInst.addOperand(Inst.getOperand(6));
5908 case ARM::VLD4LNdWB_register_Asm_8:
5909 case ARM::VLD4LNdWB_register_Asm_16:
5910 case ARM::VLD4LNdWB_register_Asm_32:
5911 case ARM::VLD4LNqWB_register_Asm_16:
5912 case ARM::VLD4LNqWB_register_Asm_32: {
5914 // Shuffle the operands around so the lane index operand is in the
5917 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
5918 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5919 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5921 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5923 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5925 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5926 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5927 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5928 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5929 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5930 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5932 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5934 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5936 TmpInst.addOperand(Inst.getOperand(1)); // lane
5937 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5938 TmpInst.addOperand(Inst.getOperand(6));
5943 case ARM::VLD1LNdWB_fixed_Asm_8:
5944 case ARM::VLD1LNdWB_fixed_Asm_16:
5945 case ARM::VLD1LNdWB_fixed_Asm_32: {
5947 // Shuffle the operands around so the lane index operand is in the
5950 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
5951 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5952 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5953 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5954 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5955 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5956 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5957 TmpInst.addOperand(Inst.getOperand(1)); // lane
5958 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5959 TmpInst.addOperand(Inst.getOperand(5));
5964 case ARM::VLD2LNdWB_fixed_Asm_8:
5965 case ARM::VLD2LNdWB_fixed_Asm_16:
5966 case ARM::VLD2LNdWB_fixed_Asm_32:
5967 case ARM::VLD2LNqWB_fixed_Asm_16:
5968 case ARM::VLD2LNqWB_fixed_Asm_32: {
5970 // Shuffle the operands around so the lane index operand is in the
5973 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
5974 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5975 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5977 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5978 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5979 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5980 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5981 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5982 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5984 TmpInst.addOperand(Inst.getOperand(1)); // lane
5985 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5986 TmpInst.addOperand(Inst.getOperand(5));
5991 case ARM::VLD3LNdWB_fixed_Asm_8:
5992 case ARM::VLD3LNdWB_fixed_Asm_16:
5993 case ARM::VLD3LNdWB_fixed_Asm_32:
5994 case ARM::VLD3LNqWB_fixed_Asm_16:
5995 case ARM::VLD3LNqWB_fixed_Asm_32: {
5997 // Shuffle the operands around so the lane index operand is in the
6000 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6001 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6002 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6004 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6006 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6007 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6008 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6009 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6010 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6011 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6013 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6015 TmpInst.addOperand(Inst.getOperand(1)); // lane
6016 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6017 TmpInst.addOperand(Inst.getOperand(5));
6022 case ARM::VLD4LNdWB_fixed_Asm_8:
6023 case ARM::VLD4LNdWB_fixed_Asm_16:
6024 case ARM::VLD4LNdWB_fixed_Asm_32:
6025 case ARM::VLD4LNqWB_fixed_Asm_16:
6026 case ARM::VLD4LNqWB_fixed_Asm_32: {
6028 // Shuffle the operands around so the lane index operand is in the
6031 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6032 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6033 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6035 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6037 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6039 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6040 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6041 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6042 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6043 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6044 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6046 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6048 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6050 TmpInst.addOperand(Inst.getOperand(1)); // lane
6051 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6052 TmpInst.addOperand(Inst.getOperand(5));
6057 case ARM::VLD1LNdAsm_8:
6058 case ARM::VLD1LNdAsm_16:
6059 case ARM::VLD1LNdAsm_32: {
6061 // Shuffle the operands around so the lane index operand is in the
6064 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6065 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6066 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6067 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6068 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6069 TmpInst.addOperand(Inst.getOperand(1)); // lane
6070 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6071 TmpInst.addOperand(Inst.getOperand(5));
6076 case ARM::VLD2LNdAsm_8:
6077 case ARM::VLD2LNdAsm_16:
6078 case ARM::VLD2LNdAsm_32:
6079 case ARM::VLD2LNqAsm_16:
6080 case ARM::VLD2LNqAsm_32: {
6082 // Shuffle the operands around so the lane index operand is in the
6085 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6086 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6087 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6089 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6090 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6091 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6092 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6094 TmpInst.addOperand(Inst.getOperand(1)); // lane
6095 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6096 TmpInst.addOperand(Inst.getOperand(5));
6101 case ARM::VLD3LNdAsm_8:
6102 case ARM::VLD3LNdAsm_16:
6103 case ARM::VLD3LNdAsm_32:
6104 case ARM::VLD3LNqAsm_16:
6105 case ARM::VLD3LNqAsm_32: {
6107 // Shuffle the operands around so the lane index operand is in the
6110 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6111 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6112 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6114 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6116 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6117 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6118 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6119 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6121 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6123 TmpInst.addOperand(Inst.getOperand(1)); // lane
6124 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6125 TmpInst.addOperand(Inst.getOperand(5));
6130 case ARM::VLD4LNdAsm_8:
6131 case ARM::VLD4LNdAsm_16:
6132 case ARM::VLD4LNdAsm_32:
6133 case ARM::VLD4LNqAsm_16:
6134 case ARM::VLD4LNqAsm_32: {
6136 // Shuffle the operands around so the lane index operand is in the
6139 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6140 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6141 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6143 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6145 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6147 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6148 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6149 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6150 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6152 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6154 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6156 TmpInst.addOperand(Inst.getOperand(1)); // lane
6157 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6158 TmpInst.addOperand(Inst.getOperand(5));
6163 // VLD3DUP single 3-element structure to all lanes instructions.
6164 case ARM::VLD3DUPdAsm_8:
6165 case ARM::VLD3DUPdAsm_16:
6166 case ARM::VLD3DUPdAsm_32:
6167 case ARM::VLD3DUPqAsm_8:
6168 case ARM::VLD3DUPqAsm_16:
6169 case ARM::VLD3DUPqAsm_32: {
6172 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6173 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6174 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6176 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6178 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6179 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6180 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6181 TmpInst.addOperand(Inst.getOperand(4));
6186 case ARM::VLD3DUPdWB_fixed_Asm_8:
6187 case ARM::VLD3DUPdWB_fixed_Asm_16:
6188 case ARM::VLD3DUPdWB_fixed_Asm_32:
6189 case ARM::VLD3DUPqWB_fixed_Asm_8:
6190 case ARM::VLD3DUPqWB_fixed_Asm_16:
6191 case ARM::VLD3DUPqWB_fixed_Asm_32: {
6194 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6195 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6196 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6198 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6200 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6201 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6202 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6203 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6204 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6205 TmpInst.addOperand(Inst.getOperand(4));
6210 case ARM::VLD3DUPdWB_register_Asm_8:
6211 case ARM::VLD3DUPdWB_register_Asm_16:
6212 case ARM::VLD3DUPdWB_register_Asm_32:
6213 case ARM::VLD3DUPqWB_register_Asm_8:
6214 case ARM::VLD3DUPqWB_register_Asm_16:
6215 case ARM::VLD3DUPqWB_register_Asm_32: {
6218 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6219 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6220 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6222 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6224 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6225 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6226 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6227 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6228 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6229 TmpInst.addOperand(Inst.getOperand(5));
6234 // VLD3 multiple 3-element structure instructions.
6235 case ARM::VLD3dAsm_8:
6236 case ARM::VLD3dAsm_16:
6237 case ARM::VLD3dAsm_32:
6238 case ARM::VLD3qAsm_8:
6239 case ARM::VLD3qAsm_16:
6240 case ARM::VLD3qAsm_32: {
6243 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6244 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6245 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6247 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6249 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6250 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6251 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6252 TmpInst.addOperand(Inst.getOperand(4));
6257 case ARM::VLD3dWB_fixed_Asm_8:
6258 case ARM::VLD3dWB_fixed_Asm_16:
6259 case ARM::VLD3dWB_fixed_Asm_32:
6260 case ARM::VLD3qWB_fixed_Asm_8:
6261 case ARM::VLD3qWB_fixed_Asm_16:
6262 case ARM::VLD3qWB_fixed_Asm_32: {
6265 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6266 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6267 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6269 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6271 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6272 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6273 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6274 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6275 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6276 TmpInst.addOperand(Inst.getOperand(4));
6281 case ARM::VLD3dWB_register_Asm_8:
6282 case ARM::VLD3dWB_register_Asm_16:
6283 case ARM::VLD3dWB_register_Asm_32:
6284 case ARM::VLD3qWB_register_Asm_8:
6285 case ARM::VLD3qWB_register_Asm_16:
6286 case ARM::VLD3qWB_register_Asm_32: {
6289 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6290 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6291 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6293 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6295 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6296 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6297 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6298 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6299 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6300 TmpInst.addOperand(Inst.getOperand(5));
6305 // VLD4DUP single 3-element structure to all lanes instructions.
6306 case ARM::VLD4DUPdAsm_8:
6307 case ARM::VLD4DUPdAsm_16:
6308 case ARM::VLD4DUPdAsm_32:
6309 case ARM::VLD4DUPqAsm_8:
6310 case ARM::VLD4DUPqAsm_16:
6311 case ARM::VLD4DUPqAsm_32: {
6314 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6315 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6316 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6318 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6320 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6322 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6323 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6324 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6325 TmpInst.addOperand(Inst.getOperand(4));
6330 case ARM::VLD4DUPdWB_fixed_Asm_8:
6331 case ARM::VLD4DUPdWB_fixed_Asm_16:
6332 case ARM::VLD4DUPdWB_fixed_Asm_32:
6333 case ARM::VLD4DUPqWB_fixed_Asm_8:
6334 case ARM::VLD4DUPqWB_fixed_Asm_16:
6335 case ARM::VLD4DUPqWB_fixed_Asm_32: {
6338 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6339 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6340 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6342 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6344 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6346 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6347 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6348 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6349 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6350 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6351 TmpInst.addOperand(Inst.getOperand(4));
6356 case ARM::VLD4DUPdWB_register_Asm_8:
6357 case ARM::VLD4DUPdWB_register_Asm_16:
6358 case ARM::VLD4DUPdWB_register_Asm_32:
6359 case ARM::VLD4DUPqWB_register_Asm_8:
6360 case ARM::VLD4DUPqWB_register_Asm_16:
6361 case ARM::VLD4DUPqWB_register_Asm_32: {
6364 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6365 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6366 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6368 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6370 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6372 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6373 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6374 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6375 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6376 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6377 TmpInst.addOperand(Inst.getOperand(5));
6382 // VLD4 multiple 4-element structure instructions.
6383 case ARM::VLD4dAsm_8:
6384 case ARM::VLD4dAsm_16:
6385 case ARM::VLD4dAsm_32:
6386 case ARM::VLD4qAsm_8:
6387 case ARM::VLD4qAsm_16:
6388 case ARM::VLD4qAsm_32: {
6391 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6392 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6393 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6395 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6397 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6399 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6400 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6401 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6402 TmpInst.addOperand(Inst.getOperand(4));
6407 case ARM::VLD4dWB_fixed_Asm_8:
6408 case ARM::VLD4dWB_fixed_Asm_16:
6409 case ARM::VLD4dWB_fixed_Asm_32:
6410 case ARM::VLD4qWB_fixed_Asm_8:
6411 case ARM::VLD4qWB_fixed_Asm_16:
6412 case ARM::VLD4qWB_fixed_Asm_32: {
6415 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6416 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6417 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6419 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6421 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6423 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6424 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6425 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6426 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6427 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6428 TmpInst.addOperand(Inst.getOperand(4));
6433 case ARM::VLD4dWB_register_Asm_8:
6434 case ARM::VLD4dWB_register_Asm_16:
6435 case ARM::VLD4dWB_register_Asm_32:
6436 case ARM::VLD4qWB_register_Asm_8:
6437 case ARM::VLD4qWB_register_Asm_16:
6438 case ARM::VLD4qWB_register_Asm_32: {
6441 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6442 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6443 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6445 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6447 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6449 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6450 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6451 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6452 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6453 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6454 TmpInst.addOperand(Inst.getOperand(5));
6459 // VST3 multiple 3-element structure instructions.
6460 case ARM::VST3dAsm_8:
6461 case ARM::VST3dAsm_16:
6462 case ARM::VST3dAsm_32:
6463 case ARM::VST3qAsm_8:
6464 case ARM::VST3qAsm_16:
6465 case ARM::VST3qAsm_32: {
6468 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6469 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6470 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6471 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6472 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6474 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6476 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6477 TmpInst.addOperand(Inst.getOperand(4));
6482 case ARM::VST3dWB_fixed_Asm_8:
6483 case ARM::VST3dWB_fixed_Asm_16:
6484 case ARM::VST3dWB_fixed_Asm_32:
6485 case ARM::VST3qWB_fixed_Asm_8:
6486 case ARM::VST3qWB_fixed_Asm_16:
6487 case ARM::VST3qWB_fixed_Asm_32: {
6490 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6491 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6492 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6493 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6494 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6495 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6496 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6498 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6500 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6501 TmpInst.addOperand(Inst.getOperand(4));
6506 case ARM::VST3dWB_register_Asm_8:
6507 case ARM::VST3dWB_register_Asm_16:
6508 case ARM::VST3dWB_register_Asm_32:
6509 case ARM::VST3qWB_register_Asm_8:
6510 case ARM::VST3qWB_register_Asm_16:
6511 case ARM::VST3qWB_register_Asm_32: {
6514 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6515 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6516 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6517 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6518 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6519 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6520 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6522 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6524 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6525 TmpInst.addOperand(Inst.getOperand(5));
6530 // VST4 multiple 3-element structure instructions.
6531 case ARM::VST4dAsm_8:
6532 case ARM::VST4dAsm_16:
6533 case ARM::VST4dAsm_32:
6534 case ARM::VST4qAsm_8:
6535 case ARM::VST4qAsm_16:
6536 case ARM::VST4qAsm_32: {
6539 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6540 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6541 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6542 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6543 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6545 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6547 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6549 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6550 TmpInst.addOperand(Inst.getOperand(4));
6555 case ARM::VST4dWB_fixed_Asm_8:
6556 case ARM::VST4dWB_fixed_Asm_16:
6557 case ARM::VST4dWB_fixed_Asm_32:
6558 case ARM::VST4qWB_fixed_Asm_8:
6559 case ARM::VST4qWB_fixed_Asm_16:
6560 case ARM::VST4qWB_fixed_Asm_32: {
6563 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6564 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6565 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6566 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6567 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6568 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6569 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6571 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6573 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6575 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6576 TmpInst.addOperand(Inst.getOperand(4));
6581 case ARM::VST4dWB_register_Asm_8:
6582 case ARM::VST4dWB_register_Asm_16:
6583 case ARM::VST4dWB_register_Asm_32:
6584 case ARM::VST4qWB_register_Asm_8:
6585 case ARM::VST4qWB_register_Asm_16:
6586 case ARM::VST4qWB_register_Asm_32: {
6589 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6590 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6591 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6592 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6593 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6594 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6595 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6597 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6599 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6601 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6602 TmpInst.addOperand(Inst.getOperand(5));
6607 // Handle the Thumb2 mode MOV complex aliases.
6609 case ARM::t2MOVSsr: {
6610 // Which instruction to expand to depends on the CCOut operand and
6611 // whether we're in an IT block if the register operands are low
6613 bool isNarrow = false;
6614 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6615 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6616 isARMLowRegister(Inst.getOperand(2).getReg()) &&
6617 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6618 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
6622 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
6623 default: llvm_unreachable("unexpected opcode!");
6624 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
6625 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
6626 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
6627 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
6629 TmpInst.setOpcode(newOpc);
6630 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6632 TmpInst.addOperand(MCOperand::CreateReg(
6633 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6634 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6635 TmpInst.addOperand(Inst.getOperand(2)); // Rm
6636 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6637 TmpInst.addOperand(Inst.getOperand(5));
6639 TmpInst.addOperand(MCOperand::CreateReg(
6640 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6645 case ARM::t2MOVSsi: {
6646 // Which instruction to expand to depends on the CCOut operand and
6647 // whether we're in an IT block if the register operands are low
6649 bool isNarrow = false;
6650 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6651 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6652 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
6656 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
6657 default: llvm_unreachable("unexpected opcode!");
6658 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
6659 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
6660 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
6661 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
6662 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
6664 unsigned Ammount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
6665 if (Ammount == 32) Ammount = 0;
6666 TmpInst.setOpcode(newOpc);
6667 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6669 TmpInst.addOperand(MCOperand::CreateReg(
6670 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6671 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6672 if (newOpc != ARM::t2RRX)
6673 TmpInst.addOperand(MCOperand::CreateImm(Ammount));
6674 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6675 TmpInst.addOperand(Inst.getOperand(4));
6677 TmpInst.addOperand(MCOperand::CreateReg(
6678 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6682 // Handle the ARM mode MOV complex aliases.
6687 ARM_AM::ShiftOpc ShiftTy;
6688 switch(Inst.getOpcode()) {
6689 default: llvm_unreachable("unexpected opcode!");
6690 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
6691 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
6692 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
6693 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
6695 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
6697 TmpInst.setOpcode(ARM::MOVsr);
6698 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6699 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6700 TmpInst.addOperand(Inst.getOperand(2)); // Rm
6701 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6702 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6703 TmpInst.addOperand(Inst.getOperand(4));
6704 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6712 ARM_AM::ShiftOpc ShiftTy;
6713 switch(Inst.getOpcode()) {
6714 default: llvm_unreachable("unexpected opcode!");
6715 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
6716 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
6717 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
6718 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
6720 // A shift by zero is a plain MOVr, not a MOVsi.
6721 unsigned Amt = Inst.getOperand(2).getImm();
6722 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
6723 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
6725 TmpInst.setOpcode(Opc);
6726 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6727 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6728 if (Opc == ARM::MOVsi)
6729 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6730 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6731 TmpInst.addOperand(Inst.getOperand(4));
6732 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6737 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
6739 TmpInst.setOpcode(ARM::MOVsi);
6740 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6741 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6742 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6743 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6744 TmpInst.addOperand(Inst.getOperand(3));
6745 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
6749 case ARM::t2LDMIA_UPD: {
6750 // If this is a load of a single register, then we should use
6751 // a post-indexed LDR instruction instead, per the ARM ARM.
6752 if (Inst.getNumOperands() != 5)
6755 TmpInst.setOpcode(ARM::t2LDR_POST);
6756 TmpInst.addOperand(Inst.getOperand(4)); // Rt
6757 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6758 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6759 TmpInst.addOperand(MCOperand::CreateImm(4));
6760 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6761 TmpInst.addOperand(Inst.getOperand(3));
6765 case ARM::t2STMDB_UPD: {
6766 // If this is a store of a single register, then we should use
6767 // a pre-indexed STR instruction instead, per the ARM ARM.
6768 if (Inst.getNumOperands() != 5)
6771 TmpInst.setOpcode(ARM::t2STR_PRE);
6772 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6773 TmpInst.addOperand(Inst.getOperand(4)); // Rt
6774 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6775 TmpInst.addOperand(MCOperand::CreateImm(-4));
6776 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6777 TmpInst.addOperand(Inst.getOperand(3));
6781 case ARM::LDMIA_UPD:
6782 // If this is a load of a single register via a 'pop', then we should use
6783 // a post-indexed LDR instruction instead, per the ARM ARM.
6784 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
6785 Inst.getNumOperands() == 5) {
6787 TmpInst.setOpcode(ARM::LDR_POST_IMM);
6788 TmpInst.addOperand(Inst.getOperand(4)); // Rt
6789 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6790 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6791 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
6792 TmpInst.addOperand(MCOperand::CreateImm(4));
6793 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6794 TmpInst.addOperand(Inst.getOperand(3));
6799 case ARM::STMDB_UPD:
6800 // If this is a store of a single register via a 'push', then we should use
6801 // a pre-indexed STR instruction instead, per the ARM ARM.
6802 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
6803 Inst.getNumOperands() == 5) {
6805 TmpInst.setOpcode(ARM::STR_PRE_IMM);
6806 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6807 TmpInst.addOperand(Inst.getOperand(4)); // Rt
6808 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
6809 TmpInst.addOperand(MCOperand::CreateImm(-4));
6810 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6811 TmpInst.addOperand(Inst.getOperand(3));
6815 case ARM::t2ADDri12:
6816 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
6817 // mnemonic was used (not "addw"), encoding T3 is preferred.
6818 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
6819 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
6821 Inst.setOpcode(ARM::t2ADDri);
6822 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
6824 case ARM::t2SUBri12:
6825 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
6826 // mnemonic was used (not "subw"), encoding T3 is preferred.
6827 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
6828 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
6830 Inst.setOpcode(ARM::t2SUBri);
6831 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
6834 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
6835 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
6836 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
6837 // to encoding T1 if <Rd> is omitted."
6838 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
6839 Inst.setOpcode(ARM::tADDi3);
6844 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
6845 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
6846 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
6847 // to encoding T1 if <Rd> is omitted."
6848 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
6849 Inst.setOpcode(ARM::tSUBi3);
6854 case ARM::t2SUBri: {
6855 // If the destination and first source operand are the same, and
6856 // the flags are compatible with the current IT status, use encoding T2
6857 // instead of T3. For compatibility with the system 'as'. Make sure the
6858 // wide encoding wasn't explicit.
6859 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
6860 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
6861 (unsigned)Inst.getOperand(2).getImm() > 255 ||
6862 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
6863 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
6864 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
6865 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
6868 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
6869 ARM::tADDi8 : ARM::tSUBi8);
6870 TmpInst.addOperand(Inst.getOperand(0));
6871 TmpInst.addOperand(Inst.getOperand(5));
6872 TmpInst.addOperand(Inst.getOperand(0));
6873 TmpInst.addOperand(Inst.getOperand(2));
6874 TmpInst.addOperand(Inst.getOperand(3));
6875 TmpInst.addOperand(Inst.getOperand(4));
6879 case ARM::t2ADDrr: {
6880 // If the destination and first source operand are the same, and
6881 // there's no setting of the flags, use encoding T2 instead of T3.
6882 // Note that this is only for ADD, not SUB. This mirrors the system
6883 // 'as' behaviour. Make sure the wide encoding wasn't explicit.
6884 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
6885 Inst.getOperand(5).getReg() != 0 ||
6886 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
6887 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
6890 TmpInst.setOpcode(ARM::tADDhirr);
6891 TmpInst.addOperand(Inst.getOperand(0));
6892 TmpInst.addOperand(Inst.getOperand(0));
6893 TmpInst.addOperand(Inst.getOperand(2));
6894 TmpInst.addOperand(Inst.getOperand(3));
6895 TmpInst.addOperand(Inst.getOperand(4));
6900 // A Thumb conditional branch outside of an IT block is a tBcc.
6901 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
6902 Inst.setOpcode(ARM::tBcc);
6907 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
6908 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
6909 Inst.setOpcode(ARM::t2Bcc);
6914 // If the conditional is AL or we're in an IT block, we really want t2B.
6915 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
6916 Inst.setOpcode(ARM::t2B);
6921 // If the conditional is AL, we really want tB.
6922 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
6923 Inst.setOpcode(ARM::tB);
6928 // If the register list contains any high registers, or if the writeback
6929 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
6930 // instead if we're in Thumb2. Otherwise, this should have generated
6931 // an error in validateInstruction().
6932 unsigned Rn = Inst.getOperand(0).getReg();
6933 bool hasWritebackToken =
6934 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
6935 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
6936 bool listContainsBase;
6937 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
6938 (!listContainsBase && !hasWritebackToken) ||
6939 (listContainsBase && hasWritebackToken)) {
6940 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
6941 assert (isThumbTwo());
6942 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
6943 // If we're switching to the updating version, we need to insert
6944 // the writeback tied operand.
6945 if (hasWritebackToken)
6946 Inst.insert(Inst.begin(),
6947 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
6952 case ARM::tSTMIA_UPD: {
6953 // If the register list contains any high registers, we need to use
6954 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
6955 // should have generated an error in validateInstruction().
6956 unsigned Rn = Inst.getOperand(0).getReg();
6957 bool listContainsBase;
6958 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
6959 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
6960 assert (isThumbTwo());
6961 Inst.setOpcode(ARM::t2STMIA_UPD);
6967 bool listContainsBase;
6968 // If the register list contains any high registers, we need to use
6969 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
6970 // should have generated an error in validateInstruction().
6971 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
6973 assert (isThumbTwo());
6974 Inst.setOpcode(ARM::t2LDMIA_UPD);
6975 // Add the base register and writeback operands.
6976 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
6977 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
6981 bool listContainsBase;
6982 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
6984 assert (isThumbTwo());
6985 Inst.setOpcode(ARM::t2STMDB_UPD);
6986 // Add the base register and writeback operands.
6987 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
6988 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
6992 // If we can use the 16-bit encoding and the user didn't explicitly
6993 // request the 32-bit variant, transform it here.
6994 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6995 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
6996 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
6997 Inst.getOperand(4).getReg() == ARM::CPSR) ||
6998 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
6999 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7000 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7001 // The operands aren't in the same order for tMOVi8...
7003 TmpInst.setOpcode(ARM::tMOVi8);
7004 TmpInst.addOperand(Inst.getOperand(0));
7005 TmpInst.addOperand(Inst.getOperand(4));
7006 TmpInst.addOperand(Inst.getOperand(1));
7007 TmpInst.addOperand(Inst.getOperand(2));
7008 TmpInst.addOperand(Inst.getOperand(3));
7015 // If we can use the 16-bit encoding and the user didn't explicitly
7016 // request the 32-bit variant, transform it here.
7017 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7018 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7019 Inst.getOperand(2).getImm() == ARMCC::AL &&
7020 Inst.getOperand(4).getReg() == ARM::CPSR &&
7021 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7022 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7023 // The operands aren't the same for tMOV[S]r... (no cc_out)
7025 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7026 TmpInst.addOperand(Inst.getOperand(0));
7027 TmpInst.addOperand(Inst.getOperand(1));
7028 TmpInst.addOperand(Inst.getOperand(2));
7029 TmpInst.addOperand(Inst.getOperand(3));
7039 // If we can use the 16-bit encoding and the user didn't explicitly
7040 // request the 32-bit variant, transform it here.
7041 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7042 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7043 Inst.getOperand(2).getImm() == 0 &&
7044 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7045 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7047 switch (Inst.getOpcode()) {
7048 default: llvm_unreachable("Illegal opcode!");
7049 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7050 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7051 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7052 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7054 // The operands aren't the same for thumb1 (no rotate operand).
7056 TmpInst.setOpcode(NewOpc);
7057 TmpInst.addOperand(Inst.getOperand(0));
7058 TmpInst.addOperand(Inst.getOperand(1));
7059 TmpInst.addOperand(Inst.getOperand(3));
7060 TmpInst.addOperand(Inst.getOperand(4));
7067 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7068 if (SOpc == ARM_AM::rrx) return false;
7069 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7070 // Shifting by zero is accepted as a vanilla 'MOVr'
7072 TmpInst.setOpcode(ARM::MOVr);
7073 TmpInst.addOperand(Inst.getOperand(0));
7074 TmpInst.addOperand(Inst.getOperand(1));
7075 TmpInst.addOperand(Inst.getOperand(3));
7076 TmpInst.addOperand(Inst.getOperand(4));
7077 TmpInst.addOperand(Inst.getOperand(5));
7090 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7091 if (SOpc == ARM_AM::rrx) return false;
7092 switch (Inst.getOpcode()) {
7093 default: llvm_unreachable("unexpected opcode!");
7094 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7095 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7096 case ARM::EORrsi: newOpc = ARM::EORrr; break;
7097 case ARM::BICrsi: newOpc = ARM::BICrr; break;
7098 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7099 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7101 // If the shift is by zero, use the non-shifted instruction definition.
7102 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0) {
7104 TmpInst.setOpcode(newOpc);
7105 TmpInst.addOperand(Inst.getOperand(0));
7106 TmpInst.addOperand(Inst.getOperand(1));
7107 TmpInst.addOperand(Inst.getOperand(2));
7108 TmpInst.addOperand(Inst.getOperand(4));
7109 TmpInst.addOperand(Inst.getOperand(5));
7110 TmpInst.addOperand(Inst.getOperand(6));
7118 // The mask bits for all but the first condition are represented as
7119 // the low bit of the condition code value implies 't'. We currently
7120 // always have 1 implies 't', so XOR toggle the bits if the low bit
7121 // of the condition code is zero. The encoding also expects the low
7122 // bit of the condition to be encoded as bit 4 of the mask operand,
7123 // so mask that in if needed
7124 MCOperand &MO = Inst.getOperand(1);
7125 unsigned Mask = MO.getImm();
7126 unsigned OrigMask = Mask;
7127 unsigned TZ = CountTrailingZeros_32(Mask);
7128 if ((Inst.getOperand(0).getImm() & 1) == 0) {
7129 assert(Mask && TZ <= 3 && "illegal IT mask value!");
7130 for (unsigned i = 3; i != TZ; --i)
7136 // Set up the IT block state according to the IT instruction we just
7138 assert(!inITBlock() && "nested IT blocks?!");
7139 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7140 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7141 ITState.CurPosition = 0;
7142 ITState.FirstCond = true;
7149 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7150 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7151 // suffix depending on whether they're in an IT block or not.
7152 unsigned Opc = Inst.getOpcode();
7153 const MCInstrDesc &MCID = getInstDesc(Opc);
7154 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7155 assert(MCID.hasOptionalDef() &&
7156 "optionally flag setting instruction missing optional def operand");
7157 assert(MCID.NumOperands == Inst.getNumOperands() &&
7158 "operand count mismatch!");
7159 // Find the optional-def operand (cc_out).
7162 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7165 // If we're parsing Thumb1, reject it completely.
7166 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7167 return Match_MnemonicFail;
7168 // If we're parsing Thumb2, which form is legal depends on whether we're
7170 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7172 return Match_RequiresITBlock;
7173 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7175 return Match_RequiresNotITBlock;
7177 // Some high-register supporting Thumb1 encodings only allow both registers
7178 // to be from r0-r7 when in Thumb2.
7179 else if (Opc == ARM::tADDhirr && isThumbOne() &&
7180 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7181 isARMLowRegister(Inst.getOperand(2).getReg()))
7182 return Match_RequiresThumb2;
7183 // Others only require ARMv6 or later.
7184 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7185 isARMLowRegister(Inst.getOperand(0).getReg()) &&
7186 isARMLowRegister(Inst.getOperand(1).getReg()))
7187 return Match_RequiresV6;
7188 return Match_Success;
7192 MatchAndEmitInstruction(SMLoc IDLoc,
7193 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
7197 unsigned MatchResult;
7198 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
7199 switch (MatchResult) {
7202 // Context sensitive operand constraints aren't handled by the matcher,
7203 // so check them here.
7204 if (validateInstruction(Inst, Operands)) {
7205 // Still progress the IT block, otherwise one wrong condition causes
7206 // nasty cascading errors.
7207 forwardITPosition();
7211 // Some instructions need post-processing to, for example, tweak which
7212 // encoding is selected. Loop on it while changes happen so the
7213 // individual transformations can chain off each other. E.g.,
7214 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
7215 while (processInstruction(Inst, Operands))
7218 // Only move forward at the very end so that everything in validate
7219 // and process gets a consistent answer about whether we're in an IT
7221 forwardITPosition();
7223 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7224 // doesn't actually encode.
7225 if (Inst.getOpcode() == ARM::ITasm)
7229 Out.EmitInstruction(Inst);
7231 case Match_MissingFeature:
7232 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
7234 case Match_InvalidOperand: {
7235 SMLoc ErrorLoc = IDLoc;
7236 if (ErrorInfo != ~0U) {
7237 if (ErrorInfo >= Operands.size())
7238 return Error(IDLoc, "too few operands for instruction");
7240 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7241 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7244 return Error(ErrorLoc, "invalid operand for instruction");
7246 case Match_MnemonicFail:
7247 return Error(IDLoc, "invalid instruction");
7248 case Match_ConversionFail:
7249 // The converter function will have already emited a diagnostic.
7251 case Match_RequiresNotITBlock:
7252 return Error(IDLoc, "flag setting instruction only valid outside IT block");
7253 case Match_RequiresITBlock:
7254 return Error(IDLoc, "instruction only valid inside IT block");
7255 case Match_RequiresV6:
7256 return Error(IDLoc, "instruction variant requires ARMv6 or later");
7257 case Match_RequiresThumb2:
7258 return Error(IDLoc, "instruction variant requires Thumb2");
7261 llvm_unreachable("Implement any new match types added!");
7264 /// parseDirective parses the arm specific directives
7265 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
7266 StringRef IDVal = DirectiveID.getIdentifier();
7267 if (IDVal == ".word")
7268 return parseDirectiveWord(4, DirectiveID.getLoc());
7269 else if (IDVal == ".thumb")
7270 return parseDirectiveThumb(DirectiveID.getLoc());
7271 else if (IDVal == ".arm")
7272 return parseDirectiveARM(DirectiveID.getLoc());
7273 else if (IDVal == ".thumb_func")
7274 return parseDirectiveThumbFunc(DirectiveID.getLoc());
7275 else if (IDVal == ".code")
7276 return parseDirectiveCode(DirectiveID.getLoc());
7277 else if (IDVal == ".syntax")
7278 return parseDirectiveSyntax(DirectiveID.getLoc());
7279 else if (IDVal == ".unreq")
7280 return parseDirectiveUnreq(DirectiveID.getLoc());
7281 else if (IDVal == ".arch")
7282 return parseDirectiveArch(DirectiveID.getLoc());
7283 else if (IDVal == ".eabi_attribute")
7284 return parseDirectiveEabiAttr(DirectiveID.getLoc());
7288 /// parseDirectiveWord
7289 /// ::= .word [ expression (, expression)* ]
7290 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
7291 if (getLexer().isNot(AsmToken::EndOfStatement)) {
7293 const MCExpr *Value;
7294 if (getParser().ParseExpression(Value))
7297 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
7299 if (getLexer().is(AsmToken::EndOfStatement))
7302 // FIXME: Improve diagnostic.
7303 if (getLexer().isNot(AsmToken::Comma))
7304 return Error(L, "unexpected token in directive");
7313 /// parseDirectiveThumb
7315 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
7316 if (getLexer().isNot(AsmToken::EndOfStatement))
7317 return Error(L, "unexpected token in directive");
7322 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7326 /// parseDirectiveARM
7328 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
7329 if (getLexer().isNot(AsmToken::EndOfStatement))
7330 return Error(L, "unexpected token in directive");
7335 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7339 /// parseDirectiveThumbFunc
7340 /// ::= .thumbfunc symbol_name
7341 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
7342 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
7343 bool isMachO = MAI.hasSubsectionsViaSymbols();
7345 bool needFuncName = true;
7347 // Darwin asm has (optionally) function name after .thumb_func direction
7350 const AsmToken &Tok = Parser.getTok();
7351 if (Tok.isNot(AsmToken::EndOfStatement)) {
7352 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
7353 return Error(L, "unexpected token in .thumb_func directive");
7354 Name = Tok.getIdentifier();
7355 Parser.Lex(); // Consume the identifier token.
7356 needFuncName = false;
7360 if (getLexer().isNot(AsmToken::EndOfStatement))
7361 return Error(L, "unexpected token in directive");
7363 // Eat the end of statement and any blank lines that follow.
7364 while (getLexer().is(AsmToken::EndOfStatement))
7367 // FIXME: assuming function name will be the line following .thumb_func
7368 // We really should be checking the next symbol definition even if there's
7369 // stuff in between.
7371 Name = Parser.getTok().getIdentifier();
7374 // Mark symbol as a thumb symbol.
7375 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
7376 getParser().getStreamer().EmitThumbFunc(Func);
7380 /// parseDirectiveSyntax
7381 /// ::= .syntax unified | divided
7382 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
7383 const AsmToken &Tok = Parser.getTok();
7384 if (Tok.isNot(AsmToken::Identifier))
7385 return Error(L, "unexpected token in .syntax directive");
7386 StringRef Mode = Tok.getString();
7387 if (Mode == "unified" || Mode == "UNIFIED")
7389 else if (Mode == "divided" || Mode == "DIVIDED")
7390 return Error(L, "'.syntax divided' arm asssembly not supported");
7392 return Error(L, "unrecognized syntax mode in .syntax directive");
7394 if (getLexer().isNot(AsmToken::EndOfStatement))
7395 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7398 // TODO tell the MC streamer the mode
7399 // getParser().getStreamer().Emit???();
7403 /// parseDirectiveCode
7404 /// ::= .code 16 | 32
7405 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
7406 const AsmToken &Tok = Parser.getTok();
7407 if (Tok.isNot(AsmToken::Integer))
7408 return Error(L, "unexpected token in .code directive");
7409 int64_t Val = Parser.getTok().getIntVal();
7415 return Error(L, "invalid operand to .code directive");
7417 if (getLexer().isNot(AsmToken::EndOfStatement))
7418 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7424 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7428 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7434 /// parseDirectiveReq
7435 /// ::= name .req registername
7436 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
7437 Parser.Lex(); // Eat the '.req' token.
7439 SMLoc SRegLoc, ERegLoc;
7440 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
7441 Parser.EatToEndOfStatement();
7442 return Error(SRegLoc, "register name expected");
7445 // Shouldn't be anything else.
7446 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
7447 Parser.EatToEndOfStatement();
7448 return Error(Parser.getTok().getLoc(),
7449 "unexpected input in .req directive.");
7452 Parser.Lex(); // Consume the EndOfStatement
7454 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg)
7455 return Error(SRegLoc, "redefinition of '" + Name +
7456 "' does not match original.");
7461 /// parseDirectiveUneq
7462 /// ::= .unreq registername
7463 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
7464 if (Parser.getTok().isNot(AsmToken::Identifier)) {
7465 Parser.EatToEndOfStatement();
7466 return Error(L, "unexpected input in .unreq directive.");
7468 RegisterReqs.erase(Parser.getTok().getIdentifier());
7469 Parser.Lex(); // Eat the identifier.
7473 /// parseDirectiveArch
7475 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
7479 /// parseDirectiveEabiAttr
7480 /// ::= .eabi_attribute int, int
7481 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
7485 extern "C" void LLVMInitializeARMAsmLexer();
7487 /// Force static initialization.
7488 extern "C" void LLVMInitializeARMAsmParser() {
7489 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
7490 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
7491 LLVMInitializeARMAsmLexer();
7494 #define GET_REGISTER_MATCHER
7495 #define GET_MATCHER_IMPLEMENTATION
7496 #include "ARMGenAsmMatcher.inc"