1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMBaseInfo.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMMCExpr.h"
13 #include "llvm/MC/MCParser/MCAsmLexer.h"
14 #include "llvm/MC/MCParser/MCAsmParser.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCAsmInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCTargetAsmParser.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/SourceMgr.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/ADT/BitVector.h"
30 #include "llvm/ADT/OwningPtr.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/StringSwitch.h"
34 #include "llvm/ADT/Twine.h"
42 class ARMAsmParser : public MCTargetAsmParser {
47 ARMCC::CondCodes Cond; // Condition for IT block.
48 unsigned Mask:4; // Condition mask for instructions.
49 // Starting at first 1 (from lsb).
50 // '1' condition as indicated in IT.
51 // '0' inverse of condition (else).
52 // Count of instructions in IT block is
53 // 4 - trailingzeroes(mask)
55 bool FirstCond; // Explicit flag for when we're parsing the
56 // First instruction in the IT block. It's
57 // implied in the mask, so needs special
60 unsigned CurPosition; // Current position in parsing of IT
61 // block. In range [0,3]. Initialized
62 // according to count of instructions in block.
63 // ~0U if no active IT block.
65 bool inITBlock() { return ITState.CurPosition != ~0U;}
66 void forwardITPosition() {
67 if (!inITBlock()) return;
68 // Move to the next instruction in the IT block, if there is one. If not,
69 // mark the block as done.
70 unsigned TZ = CountTrailingZeros_32(ITState.Mask);
71 if (++ITState.CurPosition == 5 - TZ)
72 ITState.CurPosition = ~0U; // Done with the IT block after this.
76 MCAsmParser &getParser() const { return Parser; }
77 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
79 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
80 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
82 int tryParseRegister();
83 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
84 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
85 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
86 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
87 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
88 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
89 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
90 unsigned &ShiftAmount);
91 bool parseDirectiveWord(unsigned Size, SMLoc L);
92 bool parseDirectiveThumb(SMLoc L);
93 bool parseDirectiveThumbFunc(SMLoc L);
94 bool parseDirectiveCode(SMLoc L);
95 bool parseDirectiveSyntax(SMLoc L);
97 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
98 bool &CarrySetting, unsigned &ProcessorIMod,
100 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
101 bool &CanAcceptPredicationCode);
103 bool isThumb() const {
104 // FIXME: Can tablegen auto-generate this?
105 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
107 bool isThumbOne() const {
108 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
110 bool isThumbTwo() const {
111 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
113 bool hasV6Ops() const {
114 return STI.getFeatureBits() & ARM::HasV6Ops;
116 bool hasV7Ops() const {
117 return STI.getFeatureBits() & ARM::HasV7Ops;
120 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
121 setAvailableFeatures(FB);
123 bool isMClass() const {
124 return STI.getFeatureBits() & ARM::FeatureMClass;
127 /// @name Auto-generated Match Functions
130 #define GET_ASSEMBLER_HEADER
131 #include "ARMGenAsmMatcher.inc"
135 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
136 OperandMatchResultTy parseCoprocNumOperand(
137 SmallVectorImpl<MCParsedAsmOperand*>&);
138 OperandMatchResultTy parseCoprocRegOperand(
139 SmallVectorImpl<MCParsedAsmOperand*>&);
140 OperandMatchResultTy parseCoprocOptionOperand(
141 SmallVectorImpl<MCParsedAsmOperand*>&);
142 OperandMatchResultTy parseMemBarrierOptOperand(
143 SmallVectorImpl<MCParsedAsmOperand*>&);
144 OperandMatchResultTy parseProcIFlagsOperand(
145 SmallVectorImpl<MCParsedAsmOperand*>&);
146 OperandMatchResultTy parseMSRMaskOperand(
147 SmallVectorImpl<MCParsedAsmOperand*>&);
148 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
149 StringRef Op, int Low, int High);
150 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
151 return parsePKHImm(O, "lsl", 0, 31);
153 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
154 return parsePKHImm(O, "asr", 1, 32);
156 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
157 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
158 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
159 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
160 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
161 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
162 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
163 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
165 // Asm Match Converter Methods
166 bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
167 const SmallVectorImpl<MCParsedAsmOperand*> &);
168 bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
169 const SmallVectorImpl<MCParsedAsmOperand*> &);
170 bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
171 const SmallVectorImpl<MCParsedAsmOperand*> &);
172 bool cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
173 const SmallVectorImpl<MCParsedAsmOperand*> &);
174 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
175 const SmallVectorImpl<MCParsedAsmOperand*> &);
176 bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
177 const SmallVectorImpl<MCParsedAsmOperand*> &);
178 bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
179 const SmallVectorImpl<MCParsedAsmOperand*> &);
180 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
181 const SmallVectorImpl<MCParsedAsmOperand*> &);
182 bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
183 const SmallVectorImpl<MCParsedAsmOperand*> &);
184 bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
185 const SmallVectorImpl<MCParsedAsmOperand*> &);
186 bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
187 const SmallVectorImpl<MCParsedAsmOperand*> &);
188 bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
189 const SmallVectorImpl<MCParsedAsmOperand*> &);
190 bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
191 const SmallVectorImpl<MCParsedAsmOperand*> &);
192 bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
193 const SmallVectorImpl<MCParsedAsmOperand*> &);
194 bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
195 const SmallVectorImpl<MCParsedAsmOperand*> &);
196 bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
197 const SmallVectorImpl<MCParsedAsmOperand*> &);
198 bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
199 const SmallVectorImpl<MCParsedAsmOperand*> &);
200 bool cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
201 const SmallVectorImpl<MCParsedAsmOperand*> &);
202 bool cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
203 const SmallVectorImpl<MCParsedAsmOperand*> &);
204 bool cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
205 const SmallVectorImpl<MCParsedAsmOperand*> &);
206 bool cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
207 const SmallVectorImpl<MCParsedAsmOperand*> &);
209 bool validateInstruction(MCInst &Inst,
210 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
211 bool processInstruction(MCInst &Inst,
212 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
213 bool shouldOmitCCOutOperand(StringRef Mnemonic,
214 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
217 enum ARMMatchResultTy {
218 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
219 Match_RequiresNotITBlock,
224 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
225 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
226 MCAsmParserExtension::Initialize(_Parser);
228 // Initialize the set of available features.
229 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
231 // Not in an ITBlock to start with.
232 ITState.CurPosition = ~0U;
235 // Implementation of the MCTargetAsmParser interface:
236 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
237 bool ParseInstruction(StringRef Name, SMLoc NameLoc,
238 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
239 bool ParseDirective(AsmToken DirectiveID);
241 unsigned checkTargetMatchPredicate(MCInst &Inst);
243 bool MatchAndEmitInstruction(SMLoc IDLoc,
244 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
247 } // end anonymous namespace
251 /// ARMOperand - Instances of this class represent a parsed ARM machine
253 class ARMOperand : public MCParsedAsmOperand {
278 k_BitfieldDescriptor,
282 SMLoc StartLoc, EndLoc;
283 SmallVector<unsigned, 8> Registers;
287 ARMCC::CondCodes Val;
307 ARM_PROC::IFlags Val;
323 // A vector register list is a sequential list of 1 to 4 registers.
338 unsigned Val; // encoded 8-bit representation
341 /// Combined record for all forms of ARM address expressions.
344 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
346 const MCConstantExpr *OffsetImm; // Offset immediate value
347 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
348 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
349 unsigned ShiftImm; // shift for OffsetReg.
350 unsigned Alignment; // 0 = no alignment specified
351 // n = alignment in bytes (8, 16, or 32)
352 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
358 ARM_AM::ShiftOpc ShiftTy;
367 ARM_AM::ShiftOpc ShiftTy;
373 ARM_AM::ShiftOpc ShiftTy;
386 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
388 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
390 StartLoc = o.StartLoc;
407 case k_DPRRegisterList:
408 case k_SPRRegisterList:
409 Registers = o.Registers;
412 VectorList = o.VectorList;
419 CoprocOption = o.CoprocOption;
427 case k_MemBarrierOpt:
433 case k_PostIndexRegister:
434 PostIdxReg = o.PostIdxReg;
442 case k_ShifterImmediate:
443 ShifterImm = o.ShifterImm;
445 case k_ShiftedRegister:
446 RegShiftedReg = o.RegShiftedReg;
448 case k_ShiftedImmediate:
449 RegShiftedImm = o.RegShiftedImm;
451 case k_RotateImmediate:
454 case k_BitfieldDescriptor:
455 Bitfield = o.Bitfield;
458 VectorIndex = o.VectorIndex;
463 /// getStartLoc - Get the location of the first token of this operand.
464 SMLoc getStartLoc() const { return StartLoc; }
465 /// getEndLoc - Get the location of the last token of this operand.
466 SMLoc getEndLoc() const { return EndLoc; }
468 ARMCC::CondCodes getCondCode() const {
469 assert(Kind == k_CondCode && "Invalid access!");
473 unsigned getCoproc() const {
474 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
478 StringRef getToken() const {
479 assert(Kind == k_Token && "Invalid access!");
480 return StringRef(Tok.Data, Tok.Length);
483 unsigned getReg() const {
484 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
488 const SmallVectorImpl<unsigned> &getRegList() const {
489 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
490 Kind == k_SPRRegisterList) && "Invalid access!");
494 const MCExpr *getImm() const {
495 assert(Kind == k_Immediate && "Invalid access!");
499 unsigned getFPImm() const {
500 assert(Kind == k_FPImmediate && "Invalid access!");
504 unsigned getVectorIndex() const {
505 assert(Kind == k_VectorIndex && "Invalid access!");
506 return VectorIndex.Val;
509 ARM_MB::MemBOpt getMemBarrierOpt() const {
510 assert(Kind == k_MemBarrierOpt && "Invalid access!");
514 ARM_PROC::IFlags getProcIFlags() const {
515 assert(Kind == k_ProcIFlags && "Invalid access!");
519 unsigned getMSRMask() const {
520 assert(Kind == k_MSRMask && "Invalid access!");
524 bool isCoprocNum() const { return Kind == k_CoprocNum; }
525 bool isCoprocReg() const { return Kind == k_CoprocReg; }
526 bool isCoprocOption() const { return Kind == k_CoprocOption; }
527 bool isCondCode() const { return Kind == k_CondCode; }
528 bool isCCOut() const { return Kind == k_CCOut; }
529 bool isITMask() const { return Kind == k_ITCondMask; }
530 bool isITCondCode() const { return Kind == k_CondCode; }
531 bool isImm() const { return Kind == k_Immediate; }
532 bool isFPImm() const { return Kind == k_FPImmediate; }
533 bool isImm8s4() const {
534 if (Kind != k_Immediate)
536 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
537 if (!CE) return false;
538 int64_t Value = CE->getValue();
539 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
541 bool isImm0_1020s4() const {
542 if (Kind != k_Immediate)
544 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
545 if (!CE) return false;
546 int64_t Value = CE->getValue();
547 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
549 bool isImm0_508s4() const {
550 if (Kind != k_Immediate)
552 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
553 if (!CE) return false;
554 int64_t Value = CE->getValue();
555 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
557 bool isImm0_255() const {
558 if (Kind != k_Immediate)
560 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
561 if (!CE) return false;
562 int64_t Value = CE->getValue();
563 return Value >= 0 && Value < 256;
565 bool isImm0_7() const {
566 if (Kind != k_Immediate)
568 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
569 if (!CE) return false;
570 int64_t Value = CE->getValue();
571 return Value >= 0 && Value < 8;
573 bool isImm0_15() const {
574 if (Kind != k_Immediate)
576 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
577 if (!CE) return false;
578 int64_t Value = CE->getValue();
579 return Value >= 0 && Value < 16;
581 bool isImm0_31() const {
582 if (Kind != k_Immediate)
584 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
585 if (!CE) return false;
586 int64_t Value = CE->getValue();
587 return Value >= 0 && Value < 32;
589 bool isImm1_16() const {
590 if (Kind != k_Immediate)
592 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
593 if (!CE) return false;
594 int64_t Value = CE->getValue();
595 return Value > 0 && Value < 17;
597 bool isImm1_32() const {
598 if (Kind != k_Immediate)
600 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
601 if (!CE) return false;
602 int64_t Value = CE->getValue();
603 return Value > 0 && Value < 33;
605 bool isImm0_32() const {
606 if (Kind != k_Immediate)
608 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
609 if (!CE) return false;
610 int64_t Value = CE->getValue();
611 return Value >= 0 && Value < 33;
613 bool isImm0_65535() const {
614 if (Kind != k_Immediate)
616 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
617 if (!CE) return false;
618 int64_t Value = CE->getValue();
619 return Value >= 0 && Value < 65536;
621 bool isImm0_65535Expr() const {
622 if (Kind != k_Immediate)
624 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
625 // If it's not a constant expression, it'll generate a fixup and be
627 if (!CE) return true;
628 int64_t Value = CE->getValue();
629 return Value >= 0 && Value < 65536;
631 bool isImm24bit() const {
632 if (Kind != k_Immediate)
634 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
635 if (!CE) return false;
636 int64_t Value = CE->getValue();
637 return Value >= 0 && Value <= 0xffffff;
639 bool isImmThumbSR() const {
640 if (Kind != k_Immediate)
642 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
643 if (!CE) return false;
644 int64_t Value = CE->getValue();
645 return Value > 0 && Value < 33;
647 bool isPKHLSLImm() const {
648 if (Kind != k_Immediate)
650 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
651 if (!CE) return false;
652 int64_t Value = CE->getValue();
653 return Value >= 0 && Value < 32;
655 bool isPKHASRImm() const {
656 if (Kind != k_Immediate)
658 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
659 if (!CE) return false;
660 int64_t Value = CE->getValue();
661 return Value > 0 && Value <= 32;
663 bool isARMSOImm() const {
664 if (Kind != k_Immediate)
666 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
667 if (!CE) return false;
668 int64_t Value = CE->getValue();
669 return ARM_AM::getSOImmVal(Value) != -1;
671 bool isARMSOImmNot() const {
672 if (Kind != k_Immediate)
674 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
675 if (!CE) return false;
676 int64_t Value = CE->getValue();
677 return ARM_AM::getSOImmVal(~Value) != -1;
679 bool isT2SOImm() const {
680 if (Kind != k_Immediate)
682 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
683 if (!CE) return false;
684 int64_t Value = CE->getValue();
685 return ARM_AM::getT2SOImmVal(Value) != -1;
687 bool isT2SOImmNot() const {
688 if (Kind != k_Immediate)
690 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
691 if (!CE) return false;
692 int64_t Value = CE->getValue();
693 return ARM_AM::getT2SOImmVal(~Value) != -1;
695 bool isSetEndImm() const {
696 if (Kind != k_Immediate)
698 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
699 if (!CE) return false;
700 int64_t Value = CE->getValue();
701 return Value == 1 || Value == 0;
703 bool isReg() const { return Kind == k_Register; }
704 bool isRegList() const { return Kind == k_RegisterList; }
705 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
706 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
707 bool isToken() const { return Kind == k_Token; }
708 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
709 bool isMemory() const { return Kind == k_Memory; }
710 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
711 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
712 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
713 bool isRotImm() const { return Kind == k_RotateImmediate; }
714 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
715 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
716 bool isPostIdxReg() const {
717 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
719 bool isMemNoOffset(bool alignOK = false) const {
722 // No offset of any kind.
723 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
724 (alignOK || Memory.Alignment == 0);
726 bool isAlignedMemory() const {
727 return isMemNoOffset(true);
729 bool isAddrMode2() const {
730 if (!isMemory() || Memory.Alignment != 0) return false;
731 // Check for register offset.
732 if (Memory.OffsetRegNum) return true;
733 // Immediate offset in range [-4095, 4095].
734 if (!Memory.OffsetImm) return true;
735 int64_t Val = Memory.OffsetImm->getValue();
736 return Val > -4096 && Val < 4096;
738 bool isAM2OffsetImm() const {
739 if (Kind != k_Immediate)
741 // Immediate offset in range [-4095, 4095].
742 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
743 if (!CE) return false;
744 int64_t Val = CE->getValue();
745 return Val > -4096 && Val < 4096;
747 bool isAddrMode3() const {
748 if (!isMemory() || Memory.Alignment != 0) return false;
749 // No shifts are legal for AM3.
750 if (Memory.ShiftType != ARM_AM::no_shift) return false;
751 // Check for register offset.
752 if (Memory.OffsetRegNum) return true;
753 // Immediate offset in range [-255, 255].
754 if (!Memory.OffsetImm) return true;
755 int64_t Val = Memory.OffsetImm->getValue();
756 return Val > -256 && Val < 256;
758 bool isAM3Offset() const {
759 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
761 if (Kind == k_PostIndexRegister)
762 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
763 // Immediate offset in range [-255, 255].
764 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
765 if (!CE) return false;
766 int64_t Val = CE->getValue();
767 // Special case, #-0 is INT32_MIN.
768 return (Val > -256 && Val < 256) || Val == INT32_MIN;
770 bool isAddrMode5() const {
771 // If we have an immediate that's not a constant, treat it as a label
772 // reference needing a fixup. If it is a constant, it's something else
774 if (Kind == k_Immediate && !isa<MCConstantExpr>(getImm()))
776 if (!isMemory() || Memory.Alignment != 0) return false;
777 // Check for register offset.
778 if (Memory.OffsetRegNum) return false;
779 // Immediate offset in range [-1020, 1020] and a multiple of 4.
780 if (!Memory.OffsetImm) return true;
781 int64_t Val = Memory.OffsetImm->getValue();
782 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
785 bool isMemTBB() const {
786 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
787 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
791 bool isMemTBH() const {
792 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
793 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
794 Memory.Alignment != 0 )
798 bool isMemRegOffset() const {
799 if (!isMemory() || !Memory.OffsetRegNum || Memory.Alignment != 0)
803 bool isT2MemRegOffset() const {
804 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
805 Memory.Alignment != 0)
807 // Only lsl #{0, 1, 2, 3} allowed.
808 if (Memory.ShiftType == ARM_AM::no_shift)
810 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
814 bool isMemThumbRR() const {
815 // Thumb reg+reg addressing is simple. Just two registers, a base and
816 // an offset. No shifts, negations or any other complicating factors.
817 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
818 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
820 return isARMLowRegister(Memory.BaseRegNum) &&
821 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
823 bool isMemThumbRIs4() const {
824 if (!isMemory() || Memory.OffsetRegNum != 0 ||
825 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
827 // Immediate offset, multiple of 4 in range [0, 124].
828 if (!Memory.OffsetImm) return true;
829 int64_t Val = Memory.OffsetImm->getValue();
830 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
832 bool isMemThumbRIs2() const {
833 if (!isMemory() || Memory.OffsetRegNum != 0 ||
834 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
836 // Immediate offset, multiple of 4 in range [0, 62].
837 if (!Memory.OffsetImm) return true;
838 int64_t Val = Memory.OffsetImm->getValue();
839 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
841 bool isMemThumbRIs1() const {
842 if (!isMemory() || Memory.OffsetRegNum != 0 ||
843 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
845 // Immediate offset in range [0, 31].
846 if (!Memory.OffsetImm) return true;
847 int64_t Val = Memory.OffsetImm->getValue();
848 return Val >= 0 && Val <= 31;
850 bool isMemThumbSPI() const {
851 if (!isMemory() || Memory.OffsetRegNum != 0 ||
852 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
854 // Immediate offset, multiple of 4 in range [0, 1020].
855 if (!Memory.OffsetImm) return true;
856 int64_t Val = Memory.OffsetImm->getValue();
857 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
859 bool isMemImm8s4Offset() const {
860 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
862 // Immediate offset a multiple of 4 in range [-1020, 1020].
863 if (!Memory.OffsetImm) return true;
864 int64_t Val = Memory.OffsetImm->getValue();
865 return Val >= -1020 && Val <= 1020 && (Val & 3) == 0;
867 bool isMemImm0_1020s4Offset() const {
868 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
870 // Immediate offset a multiple of 4 in range [0, 1020].
871 if (!Memory.OffsetImm) return true;
872 int64_t Val = Memory.OffsetImm->getValue();
873 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
875 bool isMemImm8Offset() const {
876 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
878 // Immediate offset in range [-255, 255].
879 if (!Memory.OffsetImm) return true;
880 int64_t Val = Memory.OffsetImm->getValue();
881 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
883 bool isMemPosImm8Offset() const {
884 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
886 // Immediate offset in range [0, 255].
887 if (!Memory.OffsetImm) return true;
888 int64_t Val = Memory.OffsetImm->getValue();
889 return Val >= 0 && Val < 256;
891 bool isMemNegImm8Offset() const {
892 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
894 // Immediate offset in range [-255, -1].
895 if (!Memory.OffsetImm) return true;
896 int64_t Val = Memory.OffsetImm->getValue();
897 return Val > -256 && Val < 0;
899 bool isMemUImm12Offset() const {
900 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
902 // Immediate offset in range [0, 4095].
903 if (!Memory.OffsetImm) return true;
904 int64_t Val = Memory.OffsetImm->getValue();
905 return (Val >= 0 && Val < 4096);
907 bool isMemImm12Offset() const {
908 // If we have an immediate that's not a constant, treat it as a label
909 // reference needing a fixup. If it is a constant, it's something else
911 if (Kind == k_Immediate && !isa<MCConstantExpr>(getImm()))
914 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
916 // Immediate offset in range [-4095, 4095].
917 if (!Memory.OffsetImm) return true;
918 int64_t Val = Memory.OffsetImm->getValue();
919 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
921 bool isPostIdxImm8() const {
922 if (Kind != k_Immediate)
924 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
925 if (!CE) return false;
926 int64_t Val = CE->getValue();
927 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
929 bool isPostIdxImm8s4() const {
930 if (Kind != k_Immediate)
932 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
933 if (!CE) return false;
934 int64_t Val = CE->getValue();
935 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
939 bool isMSRMask() const { return Kind == k_MSRMask; }
940 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
943 bool isVecListOneD() const {
944 if (Kind != k_VectorList) return false;
945 return VectorList.Count == 1;
948 bool isVecListTwoD() const {
949 if (Kind != k_VectorList) return false;
950 return VectorList.Count == 2;
953 bool isVecListThreeD() const {
954 if (Kind != k_VectorList) return false;
955 return VectorList.Count == 3;
958 bool isVecListFourD() const {
959 if (Kind != k_VectorList) return false;
960 return VectorList.Count == 4;
963 bool isVecListTwoQ() const {
964 if (Kind != k_VectorList) return false;
965 //FIXME: We haven't taught the parser to handle by-two register lists
966 // yet, so don't pretend to know one.
967 return VectorList.Count == 2 && false;
970 bool isVectorIndex8() const {
971 if (Kind != k_VectorIndex) return false;
972 return VectorIndex.Val < 8;
974 bool isVectorIndex16() const {
975 if (Kind != k_VectorIndex) return false;
976 return VectorIndex.Val < 4;
978 bool isVectorIndex32() const {
979 if (Kind != k_VectorIndex) return false;
980 return VectorIndex.Val < 2;
983 bool isNEONi8splat() const {
984 if (Kind != k_Immediate)
986 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
987 // Must be a constant.
988 if (!CE) return false;
989 int64_t Value = CE->getValue();
990 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
992 return Value >= 0 && Value < 256;
995 bool isNEONi16splat() const {
996 if (Kind != k_Immediate)
998 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
999 // Must be a constant.
1000 if (!CE) return false;
1001 int64_t Value = CE->getValue();
1002 // i16 value in the range [0,255] or [0x0100, 0xff00]
1003 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1006 bool isNEONi32splat() const {
1007 if (Kind != k_Immediate)
1009 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1010 // Must be a constant.
1011 if (!CE) return false;
1012 int64_t Value = CE->getValue();
1013 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1014 return (Value >= 0 && Value < 256) ||
1015 (Value >= 0x0100 && Value <= 0xff00) ||
1016 (Value >= 0x010000 && Value <= 0xff0000) ||
1017 (Value >= 0x01000000 && Value <= 0xff000000);
1020 bool isNEONi32vmov() const {
1021 if (Kind != k_Immediate)
1023 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1024 // Must be a constant.
1025 if (!CE) return false;
1026 int64_t Value = CE->getValue();
1027 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1028 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1029 return (Value >= 0 && Value < 256) ||
1030 (Value >= 0x0100 && Value <= 0xff00) ||
1031 (Value >= 0x010000 && Value <= 0xff0000) ||
1032 (Value >= 0x01000000 && Value <= 0xff000000) ||
1033 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1034 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1037 bool isNEONi64splat() const {
1038 if (Kind != k_Immediate)
1040 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1041 // Must be a constant.
1042 if (!CE) return false;
1043 uint64_t Value = CE->getValue();
1044 // i64 value with each byte being either 0 or 0xff.
1045 for (unsigned i = 0; i < 8; ++i)
1046 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1050 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1051 // Add as immediates when possible. Null MCExpr = 0.
1053 Inst.addOperand(MCOperand::CreateImm(0));
1054 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1055 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1057 Inst.addOperand(MCOperand::CreateExpr(Expr));
1060 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1061 assert(N == 2 && "Invalid number of operands!");
1062 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1063 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1064 Inst.addOperand(MCOperand::CreateReg(RegNum));
1067 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1068 assert(N == 1 && "Invalid number of operands!");
1069 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1072 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1073 assert(N == 1 && "Invalid number of operands!");
1074 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1077 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1078 assert(N == 1 && "Invalid number of operands!");
1079 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1082 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1083 assert(N == 1 && "Invalid number of operands!");
1084 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1087 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1088 assert(N == 1 && "Invalid number of operands!");
1089 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1092 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1093 assert(N == 1 && "Invalid number of operands!");
1094 Inst.addOperand(MCOperand::CreateReg(getReg()));
1097 void addRegOperands(MCInst &Inst, unsigned N) const {
1098 assert(N == 1 && "Invalid number of operands!");
1099 Inst.addOperand(MCOperand::CreateReg(getReg()));
1102 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1103 assert(N == 3 && "Invalid number of operands!");
1104 assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
1105 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1106 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1107 Inst.addOperand(MCOperand::CreateImm(
1108 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1111 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1112 assert(N == 2 && "Invalid number of operands!");
1113 assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
1114 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1115 Inst.addOperand(MCOperand::CreateImm(
1116 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
1119 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1120 assert(N == 1 && "Invalid number of operands!");
1121 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1125 void addRegListOperands(MCInst &Inst, unsigned N) const {
1126 assert(N == 1 && "Invalid number of operands!");
1127 const SmallVectorImpl<unsigned> &RegList = getRegList();
1128 for (SmallVectorImpl<unsigned>::const_iterator
1129 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1130 Inst.addOperand(MCOperand::CreateReg(*I));
1133 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1134 addRegListOperands(Inst, N);
1137 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1138 addRegListOperands(Inst, N);
1141 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1142 assert(N == 1 && "Invalid number of operands!");
1143 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1144 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1147 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1148 assert(N == 1 && "Invalid number of operands!");
1149 // Munge the lsb/width into a bitfield mask.
1150 unsigned lsb = Bitfield.LSB;
1151 unsigned width = Bitfield.Width;
1152 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1153 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1154 (32 - (lsb + width)));
1155 Inst.addOperand(MCOperand::CreateImm(Mask));
1158 void addImmOperands(MCInst &Inst, unsigned N) const {
1159 assert(N == 1 && "Invalid number of operands!");
1160 addExpr(Inst, getImm());
1163 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1164 assert(N == 1 && "Invalid number of operands!");
1165 Inst.addOperand(MCOperand::CreateImm(getFPImm()));
1168 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1169 assert(N == 1 && "Invalid number of operands!");
1170 // FIXME: We really want to scale the value here, but the LDRD/STRD
1171 // instruction don't encode operands that way yet.
1172 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1173 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1176 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1177 assert(N == 1 && "Invalid number of operands!");
1178 // The immediate is scaled by four in the encoding and is stored
1179 // in the MCInst as such. Lop off the low two bits here.
1180 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1181 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1184 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1185 assert(N == 1 && "Invalid number of operands!");
1186 // The immediate is scaled by four in the encoding and is stored
1187 // in the MCInst as such. Lop off the low two bits here.
1188 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1189 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1192 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1193 assert(N == 1 && "Invalid number of operands!");
1194 // The constant encodes as the immediate-1, and we store in the instruction
1195 // the bits as encoded, so subtract off one here.
1196 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1197 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1200 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1201 assert(N == 1 && "Invalid number of operands!");
1202 // The constant encodes as the immediate-1, and we store in the instruction
1203 // the bits as encoded, so subtract off one here.
1204 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1205 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1208 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1209 assert(N == 1 && "Invalid number of operands!");
1210 // The constant encodes as the immediate, except for 32, which encodes as
1212 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1213 unsigned Imm = CE->getValue();
1214 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1217 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1218 assert(N == 1 && "Invalid number of operands!");
1219 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1220 // the instruction as well.
1221 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1222 int Val = CE->getValue();
1223 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1226 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1227 assert(N == 1 && "Invalid number of operands!");
1228 // The operand is actually a t2_so_imm, but we have its bitwise
1229 // negation in the assembly source, so twiddle it here.
1230 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1231 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1234 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1235 assert(N == 1 && "Invalid number of operands!");
1236 // The operand is actually a so_imm, but we have its bitwise
1237 // negation in the assembly source, so twiddle it here.
1238 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1239 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1242 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1243 assert(N == 1 && "Invalid number of operands!");
1244 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1247 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1248 assert(N == 1 && "Invalid number of operands!");
1249 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1252 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1253 assert(N == 2 && "Invalid number of operands!");
1254 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1255 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1258 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1259 assert(N == 3 && "Invalid number of operands!");
1260 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1261 if (!Memory.OffsetRegNum) {
1262 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1263 // Special case for #-0
1264 if (Val == INT32_MIN) Val = 0;
1265 if (Val < 0) Val = -Val;
1266 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1268 // For register offset, we encode the shift type and negation flag
1270 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1271 Memory.ShiftImm, Memory.ShiftType);
1273 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1274 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1275 Inst.addOperand(MCOperand::CreateImm(Val));
1278 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1279 assert(N == 2 && "Invalid number of operands!");
1280 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1281 assert(CE && "non-constant AM2OffsetImm operand!");
1282 int32_t Val = CE->getValue();
1283 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1284 // Special case for #-0
1285 if (Val == INT32_MIN) Val = 0;
1286 if (Val < 0) Val = -Val;
1287 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1288 Inst.addOperand(MCOperand::CreateReg(0));
1289 Inst.addOperand(MCOperand::CreateImm(Val));
1292 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1293 assert(N == 3 && "Invalid number of operands!");
1294 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1295 if (!Memory.OffsetRegNum) {
1296 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1297 // Special case for #-0
1298 if (Val == INT32_MIN) Val = 0;
1299 if (Val < 0) Val = -Val;
1300 Val = ARM_AM::getAM3Opc(AddSub, Val);
1302 // For register offset, we encode the shift type and negation flag
1304 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1306 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1307 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1308 Inst.addOperand(MCOperand::CreateImm(Val));
1311 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1312 assert(N == 2 && "Invalid number of operands!");
1313 if (Kind == k_PostIndexRegister) {
1315 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1316 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1317 Inst.addOperand(MCOperand::CreateImm(Val));
1322 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1323 int32_t Val = CE->getValue();
1324 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1325 // Special case for #-0
1326 if (Val == INT32_MIN) Val = 0;
1327 if (Val < 0) Val = -Val;
1328 Val = ARM_AM::getAM3Opc(AddSub, Val);
1329 Inst.addOperand(MCOperand::CreateReg(0));
1330 Inst.addOperand(MCOperand::CreateImm(Val));
1333 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1334 assert(N == 2 && "Invalid number of operands!");
1335 // If we have an immediate that's not a constant, treat it as a label
1336 // reference needing a fixup. If it is a constant, it's something else
1337 // and we reject it.
1339 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1340 Inst.addOperand(MCOperand::CreateImm(0));
1344 // The lower two bits are always zero and as such are not encoded.
1345 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1346 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1347 // Special case for #-0
1348 if (Val == INT32_MIN) Val = 0;
1349 if (Val < 0) Val = -Val;
1350 Val = ARM_AM::getAM5Opc(AddSub, Val);
1351 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1352 Inst.addOperand(MCOperand::CreateImm(Val));
1355 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1356 assert(N == 2 && "Invalid number of operands!");
1357 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1358 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1359 Inst.addOperand(MCOperand::CreateImm(Val));
1362 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1363 assert(N == 2 && "Invalid number of operands!");
1364 // The lower two bits are always zero and as such are not encoded.
1365 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1366 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1367 Inst.addOperand(MCOperand::CreateImm(Val));
1370 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1371 assert(N == 2 && "Invalid number of operands!");
1372 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1373 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1374 Inst.addOperand(MCOperand::CreateImm(Val));
1377 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1378 addMemImm8OffsetOperands(Inst, N);
1381 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1382 addMemImm8OffsetOperands(Inst, N);
1385 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1386 assert(N == 2 && "Invalid number of operands!");
1387 // If this is an immediate, it's a label reference.
1388 if (Kind == k_Immediate) {
1389 addExpr(Inst, getImm());
1390 Inst.addOperand(MCOperand::CreateImm(0));
1394 // Otherwise, it's a normal memory reg+offset.
1395 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1396 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1397 Inst.addOperand(MCOperand::CreateImm(Val));
1400 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1401 assert(N == 2 && "Invalid number of operands!");
1402 // If this is an immediate, it's a label reference.
1403 if (Kind == k_Immediate) {
1404 addExpr(Inst, getImm());
1405 Inst.addOperand(MCOperand::CreateImm(0));
1409 // Otherwise, it's a normal memory reg+offset.
1410 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1411 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1412 Inst.addOperand(MCOperand::CreateImm(Val));
1415 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1416 assert(N == 2 && "Invalid number of operands!");
1417 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1418 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1421 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
1422 assert(N == 2 && "Invalid number of operands!");
1423 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1424 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1427 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1428 assert(N == 3 && "Invalid number of operands!");
1429 unsigned Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1430 Memory.ShiftImm, Memory.ShiftType);
1431 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1432 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1433 Inst.addOperand(MCOperand::CreateImm(Val));
1436 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1437 assert(N == 3 && "Invalid number of operands!");
1438 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1439 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1440 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
1443 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1444 assert(N == 2 && "Invalid number of operands!");
1445 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1446 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1449 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1450 assert(N == 2 && "Invalid number of operands!");
1451 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1452 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1453 Inst.addOperand(MCOperand::CreateImm(Val));
1456 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1457 assert(N == 2 && "Invalid number of operands!");
1458 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
1459 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1460 Inst.addOperand(MCOperand::CreateImm(Val));
1463 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1464 assert(N == 2 && "Invalid number of operands!");
1465 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
1466 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1467 Inst.addOperand(MCOperand::CreateImm(Val));
1470 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1471 assert(N == 2 && "Invalid number of operands!");
1472 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1473 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1474 Inst.addOperand(MCOperand::CreateImm(Val));
1477 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1478 assert(N == 1 && "Invalid number of operands!");
1479 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1480 assert(CE && "non-constant post-idx-imm8 operand!");
1481 int Imm = CE->getValue();
1482 bool isAdd = Imm >= 0;
1483 if (Imm == INT32_MIN) Imm = 0;
1484 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1485 Inst.addOperand(MCOperand::CreateImm(Imm));
1488 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
1489 assert(N == 1 && "Invalid number of operands!");
1490 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1491 assert(CE && "non-constant post-idx-imm8s4 operand!");
1492 int Imm = CE->getValue();
1493 bool isAdd = Imm >= 0;
1494 if (Imm == INT32_MIN) Imm = 0;
1495 // Immediate is scaled by 4.
1496 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
1497 Inst.addOperand(MCOperand::CreateImm(Imm));
1500 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1501 assert(N == 2 && "Invalid number of operands!");
1502 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1503 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1506 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1507 assert(N == 2 && "Invalid number of operands!");
1508 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1509 // The sign, shift type, and shift amount are encoded in a single operand
1510 // using the AM2 encoding helpers.
1511 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1512 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1513 PostIdxReg.ShiftTy);
1514 Inst.addOperand(MCOperand::CreateImm(Imm));
1517 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1518 assert(N == 1 && "Invalid number of operands!");
1519 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1522 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1523 assert(N == 1 && "Invalid number of operands!");
1524 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1527 void addVecListOneDOperands(MCInst &Inst, unsigned N) const {
1528 assert(N == 1 && "Invalid number of operands!");
1529 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1532 void addVecListTwoDOperands(MCInst &Inst, unsigned N) const {
1533 assert(N == 1 && "Invalid number of operands!");
1534 // Only the first register actually goes on the instruction. The rest
1535 // are implied by the opcode.
1536 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1539 void addVecListThreeDOperands(MCInst &Inst, unsigned N) const {
1540 assert(N == 1 && "Invalid number of operands!");
1541 // Only the first register actually goes on the instruction. The rest
1542 // are implied by the opcode.
1543 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1546 void addVecListFourDOperands(MCInst &Inst, unsigned N) const {
1547 assert(N == 1 && "Invalid number of operands!");
1548 // Only the first register actually goes on the instruction. The rest
1549 // are implied by the opcode.
1550 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1553 void addVecListTwoQOperands(MCInst &Inst, unsigned N) const {
1554 assert(N == 1 && "Invalid number of operands!");
1555 // Only the first register actually goes on the instruction. The rest
1556 // are implied by the opcode.
1557 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1560 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
1561 assert(N == 1 && "Invalid number of operands!");
1562 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1565 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
1566 assert(N == 1 && "Invalid number of operands!");
1567 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1570 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
1571 assert(N == 1 && "Invalid number of operands!");
1572 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1575 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
1576 assert(N == 1 && "Invalid number of operands!");
1577 // The immediate encodes the type of constant as well as the value.
1578 // Mask in that this is an i8 splat.
1579 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1580 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
1583 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
1584 assert(N == 1 && "Invalid number of operands!");
1585 // The immediate encodes the type of constant as well as the value.
1586 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1587 unsigned Value = CE->getValue();
1589 Value = (Value >> 8) | 0xa00;
1592 Inst.addOperand(MCOperand::CreateImm(Value));
1595 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
1596 assert(N == 1 && "Invalid number of operands!");
1597 // The immediate encodes the type of constant as well as the value.
1598 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1599 unsigned Value = CE->getValue();
1600 if (Value >= 256 && Value <= 0xff00)
1601 Value = (Value >> 8) | 0x200;
1602 else if (Value > 0xffff && Value <= 0xff0000)
1603 Value = (Value >> 16) | 0x400;
1604 else if (Value > 0xffffff)
1605 Value = (Value >> 24) | 0x600;
1606 Inst.addOperand(MCOperand::CreateImm(Value));
1609 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
1610 assert(N == 1 && "Invalid number of operands!");
1611 // The immediate encodes the type of constant as well as the value.
1612 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1613 unsigned Value = CE->getValue();
1614 if (Value >= 256 && Value <= 0xffff)
1615 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
1616 else if (Value > 0xffff && Value <= 0xffffff)
1617 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
1618 else if (Value > 0xffffff)
1619 Value = (Value >> 24) | 0x600;
1620 Inst.addOperand(MCOperand::CreateImm(Value));
1623 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
1624 assert(N == 1 && "Invalid number of operands!");
1625 // The immediate encodes the type of constant as well as the value.
1626 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1627 uint64_t Value = CE->getValue();
1629 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
1630 Imm |= (Value & 1) << i;
1632 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
1635 virtual void print(raw_ostream &OS) const;
1637 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
1638 ARMOperand *Op = new ARMOperand(k_ITCondMask);
1639 Op->ITMask.Mask = Mask;
1645 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1646 ARMOperand *Op = new ARMOperand(k_CondCode);
1653 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1654 ARMOperand *Op = new ARMOperand(k_CoprocNum);
1655 Op->Cop.Val = CopVal;
1661 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1662 ARMOperand *Op = new ARMOperand(k_CoprocReg);
1663 Op->Cop.Val = CopVal;
1669 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
1670 ARMOperand *Op = new ARMOperand(k_CoprocOption);
1677 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1678 ARMOperand *Op = new ARMOperand(k_CCOut);
1679 Op->Reg.RegNum = RegNum;
1685 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1686 ARMOperand *Op = new ARMOperand(k_Token);
1687 Op->Tok.Data = Str.data();
1688 Op->Tok.Length = Str.size();
1694 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1695 ARMOperand *Op = new ARMOperand(k_Register);
1696 Op->Reg.RegNum = RegNum;
1702 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1707 ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
1708 Op->RegShiftedReg.ShiftTy = ShTy;
1709 Op->RegShiftedReg.SrcReg = SrcReg;
1710 Op->RegShiftedReg.ShiftReg = ShiftReg;
1711 Op->RegShiftedReg.ShiftImm = ShiftImm;
1717 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1721 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
1722 Op->RegShiftedImm.ShiftTy = ShTy;
1723 Op->RegShiftedImm.SrcReg = SrcReg;
1724 Op->RegShiftedImm.ShiftImm = ShiftImm;
1730 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1732 ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
1733 Op->ShifterImm.isASR = isASR;
1734 Op->ShifterImm.Imm = Imm;
1740 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1741 ARMOperand *Op = new ARMOperand(k_RotateImmediate);
1742 Op->RotImm.Imm = Imm;
1748 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1750 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
1751 Op->Bitfield.LSB = LSB;
1752 Op->Bitfield.Width = Width;
1759 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1760 SMLoc StartLoc, SMLoc EndLoc) {
1761 KindTy Kind = k_RegisterList;
1763 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
1764 Kind = k_DPRRegisterList;
1765 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
1766 contains(Regs.front().first))
1767 Kind = k_SPRRegisterList;
1769 ARMOperand *Op = new ARMOperand(Kind);
1770 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1771 I = Regs.begin(), E = Regs.end(); I != E; ++I)
1772 Op->Registers.push_back(I->first);
1773 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1774 Op->StartLoc = StartLoc;
1775 Op->EndLoc = EndLoc;
1779 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
1781 ARMOperand *Op = new ARMOperand(k_VectorList);
1782 Op->VectorList.RegNum = RegNum;
1783 Op->VectorList.Count = Count;
1789 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
1791 ARMOperand *Op = new ARMOperand(k_VectorIndex);
1792 Op->VectorIndex.Val = Idx;
1798 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1799 ARMOperand *Op = new ARMOperand(k_Immediate);
1806 static ARMOperand *CreateFPImm(unsigned Val, SMLoc S, MCContext &Ctx) {
1807 ARMOperand *Op = new ARMOperand(k_FPImmediate);
1808 Op->FPImm.Val = Val;
1814 static ARMOperand *CreateMem(unsigned BaseRegNum,
1815 const MCConstantExpr *OffsetImm,
1816 unsigned OffsetRegNum,
1817 ARM_AM::ShiftOpc ShiftType,
1822 ARMOperand *Op = new ARMOperand(k_Memory);
1823 Op->Memory.BaseRegNum = BaseRegNum;
1824 Op->Memory.OffsetImm = OffsetImm;
1825 Op->Memory.OffsetRegNum = OffsetRegNum;
1826 Op->Memory.ShiftType = ShiftType;
1827 Op->Memory.ShiftImm = ShiftImm;
1828 Op->Memory.Alignment = Alignment;
1829 Op->Memory.isNegative = isNegative;
1835 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1836 ARM_AM::ShiftOpc ShiftTy,
1839 ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
1840 Op->PostIdxReg.RegNum = RegNum;
1841 Op->PostIdxReg.isAdd = isAdd;
1842 Op->PostIdxReg.ShiftTy = ShiftTy;
1843 Op->PostIdxReg.ShiftImm = ShiftImm;
1849 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1850 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
1851 Op->MBOpt.Val = Opt;
1857 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1858 ARMOperand *Op = new ARMOperand(k_ProcIFlags);
1859 Op->IFlags.Val = IFlags;
1865 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1866 ARMOperand *Op = new ARMOperand(k_MSRMask);
1867 Op->MMask.Val = MMask;
1874 } // end anonymous namespace.
1876 void ARMOperand::print(raw_ostream &OS) const {
1879 OS << "<fpimm " << getFPImm() << "(" << ARM_AM::getFPImmFloat(getFPImm())
1883 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1886 OS << "<ccout " << getReg() << ">";
1888 case k_ITCondMask: {
1889 static const char *MaskStr[] = {
1890 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
1891 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
1893 assert((ITMask.Mask & 0xf) == ITMask.Mask);
1894 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
1898 OS << "<coprocessor number: " << getCoproc() << ">";
1901 OS << "<coprocessor register: " << getCoproc() << ">";
1903 case k_CoprocOption:
1904 OS << "<coprocessor option: " << CoprocOption.Val << ">";
1907 OS << "<mask: " << getMSRMask() << ">";
1910 getImm()->print(OS);
1912 case k_MemBarrierOpt:
1913 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1917 << " base:" << Memory.BaseRegNum;
1920 case k_PostIndexRegister:
1921 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
1922 << PostIdxReg.RegNum;
1923 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1924 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1925 << PostIdxReg.ShiftImm;
1928 case k_ProcIFlags: {
1929 OS << "<ARM_PROC::";
1930 unsigned IFlags = getProcIFlags();
1931 for (int i=2; i >= 0; --i)
1932 if (IFlags & (1 << i))
1933 OS << ARM_PROC::IFlagsToString(1 << i);
1938 OS << "<register " << getReg() << ">";
1940 case k_ShifterImmediate:
1941 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1942 << " #" << ShifterImm.Imm << ">";
1944 case k_ShiftedRegister:
1945 OS << "<so_reg_reg "
1946 << RegShiftedReg.SrcReg
1947 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1948 << ", " << RegShiftedReg.ShiftReg << ", "
1949 << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1952 case k_ShiftedImmediate:
1953 OS << "<so_reg_imm "
1954 << RegShiftedImm.SrcReg
1955 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1956 << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
1959 case k_RotateImmediate:
1960 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
1962 case k_BitfieldDescriptor:
1963 OS << "<bitfield " << "lsb: " << Bitfield.LSB
1964 << ", width: " << Bitfield.Width << ">";
1966 case k_RegisterList:
1967 case k_DPRRegisterList:
1968 case k_SPRRegisterList: {
1969 OS << "<register_list ";
1971 const SmallVectorImpl<unsigned> &RegList = getRegList();
1972 for (SmallVectorImpl<unsigned>::const_iterator
1973 I = RegList.begin(), E = RegList.end(); I != E; ) {
1975 if (++I < E) OS << ", ";
1982 OS << "<vector_list " << VectorList.Count << " * "
1983 << VectorList.RegNum << ">";
1986 OS << "'" << getToken() << "'";
1989 OS << "<vectorindex " << getVectorIndex() << ">";
1994 /// @name Auto-generated Match Functions
1997 static unsigned MatchRegisterName(StringRef Name);
2001 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2002 SMLoc &StartLoc, SMLoc &EndLoc) {
2003 RegNo = tryParseRegister();
2005 return (RegNo == (unsigned)-1);
2008 /// Try to parse a register name. The token must be an Identifier when called,
2009 /// and if it is a register name the token is eaten and the register number is
2010 /// returned. Otherwise return -1.
2012 int ARMAsmParser::tryParseRegister() {
2013 const AsmToken &Tok = Parser.getTok();
2014 if (Tok.isNot(AsmToken::Identifier)) return -1;
2016 // FIXME: Validate register for the current architecture; we have to do
2017 // validation later, so maybe there is no need for this here.
2018 std::string lowerCase = Tok.getString().lower();
2019 unsigned RegNum = MatchRegisterName(lowerCase);
2021 RegNum = StringSwitch<unsigned>(lowerCase)
2022 .Case("r13", ARM::SP)
2023 .Case("r14", ARM::LR)
2024 .Case("r15", ARM::PC)
2025 .Case("ip", ARM::R12)
2028 if (!RegNum) return -1;
2030 Parser.Lex(); // Eat identifier token.
2035 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
2036 // If a recoverable error occurs, return 1. If an irrecoverable error
2037 // occurs, return -1. An irrecoverable error is one where tokens have been
2038 // consumed in the process of trying to parse the shifter (i.e., when it is
2039 // indeed a shifter operand, but malformed).
2040 int ARMAsmParser::tryParseShiftRegister(
2041 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2042 SMLoc S = Parser.getTok().getLoc();
2043 const AsmToken &Tok = Parser.getTok();
2044 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2046 std::string lowerCase = Tok.getString().lower();
2047 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2048 .Case("lsl", ARM_AM::lsl)
2049 .Case("lsr", ARM_AM::lsr)
2050 .Case("asr", ARM_AM::asr)
2051 .Case("ror", ARM_AM::ror)
2052 .Case("rrx", ARM_AM::rrx)
2053 .Default(ARM_AM::no_shift);
2055 if (ShiftTy == ARM_AM::no_shift)
2058 Parser.Lex(); // Eat the operator.
2060 // The source register for the shift has already been added to the
2061 // operand list, so we need to pop it off and combine it into the shifted
2062 // register operand instead.
2063 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2064 if (!PrevOp->isReg())
2065 return Error(PrevOp->getStartLoc(), "shift must be of a register");
2066 int SrcReg = PrevOp->getReg();
2069 if (ShiftTy == ARM_AM::rrx) {
2070 // RRX Doesn't have an explicit shift amount. The encoder expects
2071 // the shift register to be the same as the source register. Seems odd,
2075 // Figure out if this is shifted by a constant or a register (for non-RRX).
2076 if (Parser.getTok().is(AsmToken::Hash)) {
2077 Parser.Lex(); // Eat hash.
2078 SMLoc ImmLoc = Parser.getTok().getLoc();
2079 const MCExpr *ShiftExpr = 0;
2080 if (getParser().ParseExpression(ShiftExpr)) {
2081 Error(ImmLoc, "invalid immediate shift value");
2084 // The expression must be evaluatable as an immediate.
2085 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2087 Error(ImmLoc, "invalid immediate shift value");
2090 // Range check the immediate.
2091 // lsl, ror: 0 <= imm <= 31
2092 // lsr, asr: 0 <= imm <= 32
2093 Imm = CE->getValue();
2095 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2096 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2097 Error(ImmLoc, "immediate shift value out of range");
2100 } else if (Parser.getTok().is(AsmToken::Identifier)) {
2101 ShiftReg = tryParseRegister();
2102 SMLoc L = Parser.getTok().getLoc();
2103 if (ShiftReg == -1) {
2104 Error (L, "expected immediate or register in shift operand");
2108 Error (Parser.getTok().getLoc(),
2109 "expected immediate or register in shift operand");
2114 if (ShiftReg && ShiftTy != ARM_AM::rrx)
2115 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2117 S, Parser.getTok().getLoc()));
2119 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2120 S, Parser.getTok().getLoc()));
2126 /// Try to parse a register name. The token must be an Identifier when called.
2127 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
2128 /// if there is a "writeback". 'true' if it's not a register.
2130 /// TODO this is likely to change to allow different register types and or to
2131 /// parse for a specific register type.
2133 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2134 SMLoc S = Parser.getTok().getLoc();
2135 int RegNo = tryParseRegister();
2139 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
2141 const AsmToken &ExclaimTok = Parser.getTok();
2142 if (ExclaimTok.is(AsmToken::Exclaim)) {
2143 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2144 ExclaimTok.getLoc()));
2145 Parser.Lex(); // Eat exclaim token
2149 // Also check for an index operand. This is only legal for vector registers,
2150 // but that'll get caught OK in operand matching, so we don't need to
2151 // explicitly filter everything else out here.
2152 if (Parser.getTok().is(AsmToken::LBrac)) {
2153 SMLoc SIdx = Parser.getTok().getLoc();
2154 Parser.Lex(); // Eat left bracket token.
2156 const MCExpr *ImmVal;
2157 if (getParser().ParseExpression(ImmVal))
2158 return MatchOperand_ParseFail;
2159 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2161 TokError("immediate value expected for vector index");
2162 return MatchOperand_ParseFail;
2165 SMLoc E = Parser.getTok().getLoc();
2166 if (Parser.getTok().isNot(AsmToken::RBrac)) {
2167 Error(E, "']' expected");
2168 return MatchOperand_ParseFail;
2171 Parser.Lex(); // Eat right bracket token.
2173 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2181 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
2182 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2184 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2185 // Use the same layout as the tablegen'erated register name matcher. Ugly,
2187 switch (Name.size()) {
2190 if (Name[0] != CoprocOp)
2207 if (Name[0] != CoprocOp || Name[1] != '1')
2211 case '0': return 10;
2212 case '1': return 11;
2213 case '2': return 12;
2214 case '3': return 13;
2215 case '4': return 14;
2216 case '5': return 15;
2224 /// parseITCondCode - Try to parse a condition code for an IT instruction.
2225 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2226 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2227 SMLoc S = Parser.getTok().getLoc();
2228 const AsmToken &Tok = Parser.getTok();
2229 if (!Tok.is(AsmToken::Identifier))
2230 return MatchOperand_NoMatch;
2231 unsigned CC = StringSwitch<unsigned>(Tok.getString())
2232 .Case("eq", ARMCC::EQ)
2233 .Case("ne", ARMCC::NE)
2234 .Case("hs", ARMCC::HS)
2235 .Case("cs", ARMCC::HS)
2236 .Case("lo", ARMCC::LO)
2237 .Case("cc", ARMCC::LO)
2238 .Case("mi", ARMCC::MI)
2239 .Case("pl", ARMCC::PL)
2240 .Case("vs", ARMCC::VS)
2241 .Case("vc", ARMCC::VC)
2242 .Case("hi", ARMCC::HI)
2243 .Case("ls", ARMCC::LS)
2244 .Case("ge", ARMCC::GE)
2245 .Case("lt", ARMCC::LT)
2246 .Case("gt", ARMCC::GT)
2247 .Case("le", ARMCC::LE)
2248 .Case("al", ARMCC::AL)
2251 return MatchOperand_NoMatch;
2252 Parser.Lex(); // Eat the token.
2254 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2256 return MatchOperand_Success;
2259 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2260 /// token must be an Identifier when called, and if it is a coprocessor
2261 /// number, the token is eaten and the operand is added to the operand list.
2262 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2263 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2264 SMLoc S = Parser.getTok().getLoc();
2265 const AsmToken &Tok = Parser.getTok();
2266 if (Tok.isNot(AsmToken::Identifier))
2267 return MatchOperand_NoMatch;
2269 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2271 return MatchOperand_NoMatch;
2273 Parser.Lex(); // Eat identifier token.
2274 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2275 return MatchOperand_Success;
2278 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2279 /// token must be an Identifier when called, and if it is a coprocessor
2280 /// number, the token is eaten and the operand is added to the operand list.
2281 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2282 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2283 SMLoc S = Parser.getTok().getLoc();
2284 const AsmToken &Tok = Parser.getTok();
2285 if (Tok.isNot(AsmToken::Identifier))
2286 return MatchOperand_NoMatch;
2288 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2290 return MatchOperand_NoMatch;
2292 Parser.Lex(); // Eat identifier token.
2293 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2294 return MatchOperand_Success;
2297 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2298 /// coproc_option : '{' imm0_255 '}'
2299 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2300 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2301 SMLoc S = Parser.getTok().getLoc();
2303 // If this isn't a '{', this isn't a coprocessor immediate operand.
2304 if (Parser.getTok().isNot(AsmToken::LCurly))
2305 return MatchOperand_NoMatch;
2306 Parser.Lex(); // Eat the '{'
2309 SMLoc Loc = Parser.getTok().getLoc();
2310 if (getParser().ParseExpression(Expr)) {
2311 Error(Loc, "illegal expression");
2312 return MatchOperand_ParseFail;
2314 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2315 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2316 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2317 return MatchOperand_ParseFail;
2319 int Val = CE->getValue();
2321 // Check for and consume the closing '}'
2322 if (Parser.getTok().isNot(AsmToken::RCurly))
2323 return MatchOperand_ParseFail;
2324 SMLoc E = Parser.getTok().getLoc();
2325 Parser.Lex(); // Eat the '}'
2327 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2328 return MatchOperand_Success;
2331 // For register list parsing, we need to map from raw GPR register numbering
2332 // to the enumeration values. The enumeration values aren't sorted by
2333 // register number due to our using "sp", "lr" and "pc" as canonical names.
2334 static unsigned getNextRegister(unsigned Reg) {
2335 // If this is a GPR, we need to do it manually, otherwise we can rely
2336 // on the sort ordering of the enumeration since the other reg-classes
2338 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2341 default: assert(0 && "Invalid GPR number!");
2342 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
2343 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
2344 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
2345 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
2346 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
2347 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2348 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
2349 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
2353 // Return the low-subreg of a given Q register.
2354 static unsigned getDRegFromQReg(unsigned QReg) {
2356 default: llvm_unreachable("expected a Q register!");
2357 case ARM::Q0: return ARM::D0;
2358 case ARM::Q1: return ARM::D2;
2359 case ARM::Q2: return ARM::D4;
2360 case ARM::Q3: return ARM::D6;
2361 case ARM::Q4: return ARM::D8;
2362 case ARM::Q5: return ARM::D10;
2363 case ARM::Q6: return ARM::D12;
2364 case ARM::Q7: return ARM::D14;
2365 case ARM::Q8: return ARM::D16;
2366 case ARM::Q9: return ARM::D19;
2367 case ARM::Q10: return ARM::D20;
2368 case ARM::Q11: return ARM::D22;
2369 case ARM::Q12: return ARM::D24;
2370 case ARM::Q13: return ARM::D26;
2371 case ARM::Q14: return ARM::D28;
2372 case ARM::Q15: return ARM::D30;
2376 /// Parse a register list.
2378 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2379 assert(Parser.getTok().is(AsmToken::LCurly) &&
2380 "Token is not a Left Curly Brace");
2381 SMLoc S = Parser.getTok().getLoc();
2382 Parser.Lex(); // Eat '{' token.
2383 SMLoc RegLoc = Parser.getTok().getLoc();
2385 // Check the first register in the list to see what register class
2386 // this is a list of.
2387 int Reg = tryParseRegister();
2389 return Error(RegLoc, "register expected");
2391 // The reglist instructions have at most 16 registers, so reserve
2392 // space for that many.
2393 SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
2395 // Allow Q regs and just interpret them as the two D sub-registers.
2396 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2397 Reg = getDRegFromQReg(Reg);
2398 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2401 const MCRegisterClass *RC;
2402 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2403 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
2404 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
2405 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
2406 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
2407 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
2409 return Error(RegLoc, "invalid register in register list");
2411 // Store the register.
2412 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2414 // This starts immediately after the first register token in the list,
2415 // so we can see either a comma or a minus (range separator) as a legal
2417 while (Parser.getTok().is(AsmToken::Comma) ||
2418 Parser.getTok().is(AsmToken::Minus)) {
2419 if (Parser.getTok().is(AsmToken::Minus)) {
2420 Parser.Lex(); // Eat the comma.
2421 SMLoc EndLoc = Parser.getTok().getLoc();
2422 int EndReg = tryParseRegister();
2424 return Error(EndLoc, "register expected");
2425 // Allow Q regs and just interpret them as the two D sub-registers.
2426 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
2427 EndReg = getDRegFromQReg(EndReg) + 1;
2428 // If the register is the same as the start reg, there's nothing
2432 // The register must be in the same register class as the first.
2433 if (!RC->contains(EndReg))
2434 return Error(EndLoc, "invalid register in register list");
2435 // Ranges must go from low to high.
2436 if (getARMRegisterNumbering(Reg) > getARMRegisterNumbering(EndReg))
2437 return Error(EndLoc, "bad range in register list");
2439 // Add all the registers in the range to the register list.
2440 while (Reg != EndReg) {
2441 Reg = getNextRegister(Reg);
2442 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2446 Parser.Lex(); // Eat the comma.
2447 RegLoc = Parser.getTok().getLoc();
2449 Reg = tryParseRegister();
2451 return Error(RegLoc, "register expected");
2452 // Allow Q regs and just interpret them as the two D sub-registers.
2453 bool isQReg = false;
2454 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2455 Reg = getDRegFromQReg(Reg);
2458 // The register must be in the same register class as the first.
2459 if (!RC->contains(Reg))
2460 return Error(RegLoc, "invalid register in register list");
2461 // List must be monotonically increasing.
2462 if (getARMRegisterNumbering(Reg) <= getARMRegisterNumbering(OldReg))
2463 return Error(RegLoc, "register list not in ascending order");
2464 // VFP register lists must also be contiguous.
2465 // It's OK to use the enumeration values directly here rather, as the
2466 // VFP register classes have the enum sorted properly.
2467 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
2469 return Error(RegLoc, "non-contiguous register range");
2470 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2472 Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc));
2475 SMLoc E = Parser.getTok().getLoc();
2476 if (Parser.getTok().isNot(AsmToken::RCurly))
2477 return Error(E, "'}' expected");
2478 Parser.Lex(); // Eat '}' token.
2480 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
2484 // parse a vector register list
2485 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2486 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2487 if(Parser.getTok().isNot(AsmToken::LCurly))
2488 return MatchOperand_NoMatch;
2490 SMLoc S = Parser.getTok().getLoc();
2491 Parser.Lex(); // Eat '{' token.
2492 SMLoc RegLoc = Parser.getTok().getLoc();
2494 int Reg = tryParseRegister();
2496 Error(RegLoc, "register expected");
2497 return MatchOperand_ParseFail;
2500 unsigned FirstReg = Reg;
2501 // The list is of D registers, but we also allow Q regs and just interpret
2502 // them as the two D sub-registers.
2503 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2504 FirstReg = Reg = getDRegFromQReg(Reg);
2509 while (Parser.getTok().is(AsmToken::Comma)) {
2510 Parser.Lex(); // Eat the comma.
2511 RegLoc = Parser.getTok().getLoc();
2513 Reg = tryParseRegister();
2515 Error(RegLoc, "register expected");
2516 return MatchOperand_ParseFail;
2518 // vector register lists must be contiguous.
2519 // It's OK to use the enumeration values directly here rather, as the
2520 // VFP register classes have the enum sorted properly.
2522 // The list is of D registers, but we also allow Q regs and just interpret
2523 // them as the two D sub-registers.
2524 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2525 Reg = getDRegFromQReg(Reg);
2526 if (Reg != OldReg + 1) {
2527 Error(RegLoc, "non-contiguous register range");
2528 return MatchOperand_ParseFail;
2534 // Normal D register. Just check that it's contiguous and keep going.
2535 if (Reg != OldReg + 1) {
2536 Error(RegLoc, "non-contiguous register range");
2537 return MatchOperand_ParseFail;
2542 SMLoc E = Parser.getTok().getLoc();
2543 if (Parser.getTok().isNot(AsmToken::RCurly)) {
2544 Error(E, "'}' expected");
2545 return MatchOperand_ParseFail;
2547 Parser.Lex(); // Eat '}' token.
2549 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, S, E));
2550 return MatchOperand_Success;
2553 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
2554 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2555 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2556 SMLoc S = Parser.getTok().getLoc();
2557 const AsmToken &Tok = Parser.getTok();
2558 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2559 StringRef OptStr = Tok.getString();
2561 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
2562 .Case("sy", ARM_MB::SY)
2563 .Case("st", ARM_MB::ST)
2564 .Case("sh", ARM_MB::ISH)
2565 .Case("ish", ARM_MB::ISH)
2566 .Case("shst", ARM_MB::ISHST)
2567 .Case("ishst", ARM_MB::ISHST)
2568 .Case("nsh", ARM_MB::NSH)
2569 .Case("un", ARM_MB::NSH)
2570 .Case("nshst", ARM_MB::NSHST)
2571 .Case("unst", ARM_MB::NSHST)
2572 .Case("osh", ARM_MB::OSH)
2573 .Case("oshst", ARM_MB::OSHST)
2577 return MatchOperand_NoMatch;
2579 Parser.Lex(); // Eat identifier token.
2580 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
2581 return MatchOperand_Success;
2584 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
2585 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2586 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2587 SMLoc S = Parser.getTok().getLoc();
2588 const AsmToken &Tok = Parser.getTok();
2589 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2590 StringRef IFlagsStr = Tok.getString();
2592 // An iflags string of "none" is interpreted to mean that none of the AIF
2593 // bits are set. Not a terribly useful instruction, but a valid encoding.
2594 unsigned IFlags = 0;
2595 if (IFlagsStr != "none") {
2596 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
2597 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
2598 .Case("a", ARM_PROC::A)
2599 .Case("i", ARM_PROC::I)
2600 .Case("f", ARM_PROC::F)
2603 // If some specific iflag is already set, it means that some letter is
2604 // present more than once, this is not acceptable.
2605 if (Flag == ~0U || (IFlags & Flag))
2606 return MatchOperand_NoMatch;
2612 Parser.Lex(); // Eat identifier token.
2613 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
2614 return MatchOperand_Success;
2617 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
2618 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2619 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2620 SMLoc S = Parser.getTok().getLoc();
2621 const AsmToken &Tok = Parser.getTok();
2622 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2623 StringRef Mask = Tok.getString();
2626 // See ARMv6-M 10.1.1
2627 unsigned FlagsVal = StringSwitch<unsigned>(Mask)
2637 .Case("primask", 16)
2638 .Case("basepri", 17)
2639 .Case("basepri_max", 18)
2640 .Case("faultmask", 19)
2641 .Case("control", 20)
2644 if (FlagsVal == ~0U)
2645 return MatchOperand_NoMatch;
2647 if (!hasV7Ops() && FlagsVal >= 17 && FlagsVal <= 19)
2648 // basepri, basepri_max and faultmask only valid for V7m.
2649 return MatchOperand_NoMatch;
2651 Parser.Lex(); // Eat identifier token.
2652 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
2653 return MatchOperand_Success;
2656 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
2657 size_t Start = 0, Next = Mask.find('_');
2658 StringRef Flags = "";
2659 std::string SpecReg = Mask.slice(Start, Next).lower();
2660 if (Next != StringRef::npos)
2661 Flags = Mask.slice(Next+1, Mask.size());
2663 // FlagsVal contains the complete mask:
2665 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
2666 unsigned FlagsVal = 0;
2668 if (SpecReg == "apsr") {
2669 FlagsVal = StringSwitch<unsigned>(Flags)
2670 .Case("nzcvq", 0x8) // same as CPSR_f
2671 .Case("g", 0x4) // same as CPSR_s
2672 .Case("nzcvqg", 0xc) // same as CPSR_fs
2675 if (FlagsVal == ~0U) {
2677 return MatchOperand_NoMatch;
2679 FlagsVal = 8; // No flag
2681 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
2682 if (Flags == "all") // cpsr_all is an alias for cpsr_fc
2684 for (int i = 0, e = Flags.size(); i != e; ++i) {
2685 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
2692 // If some specific flag is already set, it means that some letter is
2693 // present more than once, this is not acceptable.
2694 if (FlagsVal == ~0U || (FlagsVal & Flag))
2695 return MatchOperand_NoMatch;
2698 } else // No match for special register.
2699 return MatchOperand_NoMatch;
2701 // Special register without flags is NOT equivalent to "fc" flags.
2702 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
2703 // two lines would enable gas compatibility at the expense of breaking
2709 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
2710 if (SpecReg == "spsr")
2713 Parser.Lex(); // Eat identifier token.
2714 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
2715 return MatchOperand_Success;
2718 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2719 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
2720 int Low, int High) {
2721 const AsmToken &Tok = Parser.getTok();
2722 if (Tok.isNot(AsmToken::Identifier)) {
2723 Error(Parser.getTok().getLoc(), Op + " operand expected.");
2724 return MatchOperand_ParseFail;
2726 StringRef ShiftName = Tok.getString();
2727 std::string LowerOp = Op.lower();
2728 std::string UpperOp = Op.upper();
2729 if (ShiftName != LowerOp && ShiftName != UpperOp) {
2730 Error(Parser.getTok().getLoc(), Op + " operand expected.");
2731 return MatchOperand_ParseFail;
2733 Parser.Lex(); // Eat shift type token.
2735 // There must be a '#' and a shift amount.
2736 if (Parser.getTok().isNot(AsmToken::Hash)) {
2737 Error(Parser.getTok().getLoc(), "'#' expected");
2738 return MatchOperand_ParseFail;
2740 Parser.Lex(); // Eat hash token.
2742 const MCExpr *ShiftAmount;
2743 SMLoc Loc = Parser.getTok().getLoc();
2744 if (getParser().ParseExpression(ShiftAmount)) {
2745 Error(Loc, "illegal expression");
2746 return MatchOperand_ParseFail;
2748 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2750 Error(Loc, "constant expression expected");
2751 return MatchOperand_ParseFail;
2753 int Val = CE->getValue();
2754 if (Val < Low || Val > High) {
2755 Error(Loc, "immediate value out of range");
2756 return MatchOperand_ParseFail;
2759 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
2761 return MatchOperand_Success;
2764 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2765 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2766 const AsmToken &Tok = Parser.getTok();
2767 SMLoc S = Tok.getLoc();
2768 if (Tok.isNot(AsmToken::Identifier)) {
2769 Error(Tok.getLoc(), "'be' or 'le' operand expected");
2770 return MatchOperand_ParseFail;
2772 int Val = StringSwitch<int>(Tok.getString())
2776 Parser.Lex(); // Eat the token.
2779 Error(Tok.getLoc(), "'be' or 'le' operand expected");
2780 return MatchOperand_ParseFail;
2782 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
2784 S, Parser.getTok().getLoc()));
2785 return MatchOperand_Success;
2788 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
2789 /// instructions. Legal values are:
2790 /// lsl #n 'n' in [0,31]
2791 /// asr #n 'n' in [1,32]
2792 /// n == 32 encoded as n == 0.
2793 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2794 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2795 const AsmToken &Tok = Parser.getTok();
2796 SMLoc S = Tok.getLoc();
2797 if (Tok.isNot(AsmToken::Identifier)) {
2798 Error(S, "shift operator 'asr' or 'lsl' expected");
2799 return MatchOperand_ParseFail;
2801 StringRef ShiftName = Tok.getString();
2803 if (ShiftName == "lsl" || ShiftName == "LSL")
2805 else if (ShiftName == "asr" || ShiftName == "ASR")
2808 Error(S, "shift operator 'asr' or 'lsl' expected");
2809 return MatchOperand_ParseFail;
2811 Parser.Lex(); // Eat the operator.
2813 // A '#' and a shift amount.
2814 if (Parser.getTok().isNot(AsmToken::Hash)) {
2815 Error(Parser.getTok().getLoc(), "'#' expected");
2816 return MatchOperand_ParseFail;
2818 Parser.Lex(); // Eat hash token.
2820 const MCExpr *ShiftAmount;
2821 SMLoc E = Parser.getTok().getLoc();
2822 if (getParser().ParseExpression(ShiftAmount)) {
2823 Error(E, "malformed shift expression");
2824 return MatchOperand_ParseFail;
2826 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2828 Error(E, "shift amount must be an immediate");
2829 return MatchOperand_ParseFail;
2832 int64_t Val = CE->getValue();
2834 // Shift amount must be in [1,32]
2835 if (Val < 1 || Val > 32) {
2836 Error(E, "'asr' shift amount must be in range [1,32]");
2837 return MatchOperand_ParseFail;
2839 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
2840 if (isThumb() && Val == 32) {
2841 Error(E, "'asr #32' shift amount not allowed in Thumb mode");
2842 return MatchOperand_ParseFail;
2844 if (Val == 32) Val = 0;
2846 // Shift amount must be in [1,32]
2847 if (Val < 0 || Val > 31) {
2848 Error(E, "'lsr' shift amount must be in range [0,31]");
2849 return MatchOperand_ParseFail;
2853 E = Parser.getTok().getLoc();
2854 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
2856 return MatchOperand_Success;
2859 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
2860 /// of instructions. Legal values are:
2861 /// ror #n 'n' in {0, 8, 16, 24}
2862 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2863 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2864 const AsmToken &Tok = Parser.getTok();
2865 SMLoc S = Tok.getLoc();
2866 if (Tok.isNot(AsmToken::Identifier))
2867 return MatchOperand_NoMatch;
2868 StringRef ShiftName = Tok.getString();
2869 if (ShiftName != "ror" && ShiftName != "ROR")
2870 return MatchOperand_NoMatch;
2871 Parser.Lex(); // Eat the operator.
2873 // A '#' and a rotate amount.
2874 if (Parser.getTok().isNot(AsmToken::Hash)) {
2875 Error(Parser.getTok().getLoc(), "'#' expected");
2876 return MatchOperand_ParseFail;
2878 Parser.Lex(); // Eat hash token.
2880 const MCExpr *ShiftAmount;
2881 SMLoc E = Parser.getTok().getLoc();
2882 if (getParser().ParseExpression(ShiftAmount)) {
2883 Error(E, "malformed rotate expression");
2884 return MatchOperand_ParseFail;
2886 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2888 Error(E, "rotate amount must be an immediate");
2889 return MatchOperand_ParseFail;
2892 int64_t Val = CE->getValue();
2893 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
2894 // normally, zero is represented in asm by omitting the rotate operand
2896 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
2897 Error(E, "'ror' rotate amount must be 8, 16, or 24");
2898 return MatchOperand_ParseFail;
2901 E = Parser.getTok().getLoc();
2902 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
2904 return MatchOperand_Success;
2907 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2908 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2909 SMLoc S = Parser.getTok().getLoc();
2910 // The bitfield descriptor is really two operands, the LSB and the width.
2911 if (Parser.getTok().isNot(AsmToken::Hash)) {
2912 Error(Parser.getTok().getLoc(), "'#' expected");
2913 return MatchOperand_ParseFail;
2915 Parser.Lex(); // Eat hash token.
2917 const MCExpr *LSBExpr;
2918 SMLoc E = Parser.getTok().getLoc();
2919 if (getParser().ParseExpression(LSBExpr)) {
2920 Error(E, "malformed immediate expression");
2921 return MatchOperand_ParseFail;
2923 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
2925 Error(E, "'lsb' operand must be an immediate");
2926 return MatchOperand_ParseFail;
2929 int64_t LSB = CE->getValue();
2930 // The LSB must be in the range [0,31]
2931 if (LSB < 0 || LSB > 31) {
2932 Error(E, "'lsb' operand must be in the range [0,31]");
2933 return MatchOperand_ParseFail;
2935 E = Parser.getTok().getLoc();
2937 // Expect another immediate operand.
2938 if (Parser.getTok().isNot(AsmToken::Comma)) {
2939 Error(Parser.getTok().getLoc(), "too few operands");
2940 return MatchOperand_ParseFail;
2942 Parser.Lex(); // Eat hash token.
2943 if (Parser.getTok().isNot(AsmToken::Hash)) {
2944 Error(Parser.getTok().getLoc(), "'#' expected");
2945 return MatchOperand_ParseFail;
2947 Parser.Lex(); // Eat hash token.
2949 const MCExpr *WidthExpr;
2950 if (getParser().ParseExpression(WidthExpr)) {
2951 Error(E, "malformed immediate expression");
2952 return MatchOperand_ParseFail;
2954 CE = dyn_cast<MCConstantExpr>(WidthExpr);
2956 Error(E, "'width' operand must be an immediate");
2957 return MatchOperand_ParseFail;
2960 int64_t Width = CE->getValue();
2961 // The LSB must be in the range [1,32-lsb]
2962 if (Width < 1 || Width > 32 - LSB) {
2963 Error(E, "'width' operand must be in the range [1,32-lsb]");
2964 return MatchOperand_ParseFail;
2966 E = Parser.getTok().getLoc();
2968 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
2970 return MatchOperand_Success;
2973 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2974 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2975 // Check for a post-index addressing register operand. Specifically:
2976 // postidx_reg := '+' register {, shift}
2977 // | '-' register {, shift}
2978 // | register {, shift}
2980 // This method must return MatchOperand_NoMatch without consuming any tokens
2981 // in the case where there is no match, as other alternatives take other
2983 AsmToken Tok = Parser.getTok();
2984 SMLoc S = Tok.getLoc();
2985 bool haveEaten = false;
2988 if (Tok.is(AsmToken::Plus)) {
2989 Parser.Lex(); // Eat the '+' token.
2991 } else if (Tok.is(AsmToken::Minus)) {
2992 Parser.Lex(); // Eat the '-' token.
2996 if (Parser.getTok().is(AsmToken::Identifier))
2997 Reg = tryParseRegister();
3000 return MatchOperand_NoMatch;
3001 Error(Parser.getTok().getLoc(), "register expected");
3002 return MatchOperand_ParseFail;
3004 SMLoc E = Parser.getTok().getLoc();
3006 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
3007 unsigned ShiftImm = 0;
3008 if (Parser.getTok().is(AsmToken::Comma)) {
3009 Parser.Lex(); // Eat the ','.
3010 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
3011 return MatchOperand_ParseFail;
3014 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
3017 return MatchOperand_Success;
3020 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3021 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3022 // Check for a post-index addressing register operand. Specifically:
3023 // am3offset := '+' register
3030 // This method must return MatchOperand_NoMatch without consuming any tokens
3031 // in the case where there is no match, as other alternatives take other
3033 AsmToken Tok = Parser.getTok();
3034 SMLoc S = Tok.getLoc();
3036 // Do immediates first, as we always parse those if we have a '#'.
3037 if (Parser.getTok().is(AsmToken::Hash)) {
3038 Parser.Lex(); // Eat the '#'.
3039 // Explicitly look for a '-', as we need to encode negative zero
3041 bool isNegative = Parser.getTok().is(AsmToken::Minus);
3042 const MCExpr *Offset;
3043 if (getParser().ParseExpression(Offset))
3044 return MatchOperand_ParseFail;
3045 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
3047 Error(S, "constant expression expected");
3048 return MatchOperand_ParseFail;
3050 SMLoc E = Tok.getLoc();
3051 // Negative zero is encoded as the flag value INT32_MIN.
3052 int32_t Val = CE->getValue();
3053 if (isNegative && Val == 0)
3057 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
3059 return MatchOperand_Success;
3063 bool haveEaten = false;
3066 if (Tok.is(AsmToken::Plus)) {
3067 Parser.Lex(); // Eat the '+' token.
3069 } else if (Tok.is(AsmToken::Minus)) {
3070 Parser.Lex(); // Eat the '-' token.
3074 if (Parser.getTok().is(AsmToken::Identifier))
3075 Reg = tryParseRegister();
3078 return MatchOperand_NoMatch;
3079 Error(Parser.getTok().getLoc(), "register expected");
3080 return MatchOperand_ParseFail;
3082 SMLoc E = Parser.getTok().getLoc();
3084 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
3087 return MatchOperand_Success;
3090 /// cvtT2LdrdPre - Convert parsed operands to MCInst.
3091 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3092 /// when they refer multiple MIOperands inside a single one.
3094 cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
3095 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3097 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3098 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3099 // Create a writeback register dummy placeholder.
3100 Inst.addOperand(MCOperand::CreateReg(0));
3102 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3104 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3108 /// cvtT2StrdPre - Convert parsed operands to MCInst.
3109 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3110 /// when they refer multiple MIOperands inside a single one.
3112 cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
3113 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3114 // Create a writeback register dummy placeholder.
3115 Inst.addOperand(MCOperand::CreateReg(0));
3117 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3118 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3120 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3122 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3126 /// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3127 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3128 /// when they refer multiple MIOperands inside a single one.
3130 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3131 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3132 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3134 // Create a writeback register dummy placeholder.
3135 Inst.addOperand(MCOperand::CreateImm(0));
3137 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3138 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3142 /// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3143 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3144 /// when they refer multiple MIOperands inside a single one.
3146 cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3147 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3148 // Create a writeback register dummy placeholder.
3149 Inst.addOperand(MCOperand::CreateImm(0));
3150 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3151 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3152 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3156 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3157 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3158 /// when they refer multiple MIOperands inside a single one.
3160 cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3161 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3162 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3164 // Create a writeback register dummy placeholder.
3165 Inst.addOperand(MCOperand::CreateImm(0));
3167 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3168 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3172 /// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3173 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3174 /// when they refer multiple MIOperands inside a single one.
3176 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3177 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3178 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3180 // Create a writeback register dummy placeholder.
3181 Inst.addOperand(MCOperand::CreateImm(0));
3183 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3184 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3189 /// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3190 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3191 /// when they refer multiple MIOperands inside a single one.
3193 cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3194 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3195 // Create a writeback register dummy placeholder.
3196 Inst.addOperand(MCOperand::CreateImm(0));
3197 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3198 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3199 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3203 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3204 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3205 /// when they refer multiple MIOperands inside a single one.
3207 cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3208 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3209 // Create a writeback register dummy placeholder.
3210 Inst.addOperand(MCOperand::CreateImm(0));
3211 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3212 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3213 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3217 /// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
3218 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3219 /// when they refer multiple MIOperands inside a single one.
3221 cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
3222 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3223 // Create a writeback register dummy placeholder.
3224 Inst.addOperand(MCOperand::CreateImm(0));
3225 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3226 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
3227 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3231 /// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
3232 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3233 /// when they refer multiple MIOperands inside a single one.
3235 cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
3236 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3238 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3239 // Create a writeback register dummy placeholder.
3240 Inst.addOperand(MCOperand::CreateImm(0));
3242 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3244 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
3246 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3250 /// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
3251 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3252 /// when they refer multiple MIOperands inside a single one.
3254 cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
3255 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3257 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3258 // Create a writeback register dummy placeholder.
3259 Inst.addOperand(MCOperand::CreateImm(0));
3261 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3263 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
3265 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3269 /// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
3270 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3271 /// when they refer multiple MIOperands inside a single one.
3273 cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
3274 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3275 // Create a writeback register dummy placeholder.
3276 Inst.addOperand(MCOperand::CreateImm(0));
3278 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3280 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3282 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
3284 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3288 /// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
3289 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3290 /// when they refer multiple MIOperands inside a single one.
3292 cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
3293 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3294 // Create a writeback register dummy placeholder.
3295 Inst.addOperand(MCOperand::CreateImm(0));
3297 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3299 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3301 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
3303 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3307 /// cvtLdrdPre - Convert parsed operands to MCInst.
3308 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3309 /// when they refer multiple MIOperands inside a single one.
3311 cvtLdrdPre(MCInst &Inst, unsigned Opcode,
3312 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3314 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3315 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3316 // Create a writeback register dummy placeholder.
3317 Inst.addOperand(MCOperand::CreateImm(0));
3319 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
3321 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3325 /// cvtStrdPre - Convert parsed operands to MCInst.
3326 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3327 /// when they refer multiple MIOperands inside a single one.
3329 cvtStrdPre(MCInst &Inst, unsigned Opcode,
3330 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3331 // Create a writeback register dummy placeholder.
3332 Inst.addOperand(MCOperand::CreateImm(0));
3334 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3335 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3337 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
3339 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3343 /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
3344 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3345 /// when they refer multiple MIOperands inside a single one.
3347 cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
3348 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3349 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3350 // Create a writeback register dummy placeholder.
3351 Inst.addOperand(MCOperand::CreateImm(0));
3352 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
3353 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3357 /// cvtThumbMultiple- Convert parsed operands to MCInst.
3358 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3359 /// when they refer multiple MIOperands inside a single one.
3361 cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
3362 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3363 // The second source operand must be the same register as the destination
3365 if (Operands.size() == 6 &&
3366 (((ARMOperand*)Operands[3])->getReg() !=
3367 ((ARMOperand*)Operands[5])->getReg()) &&
3368 (((ARMOperand*)Operands[3])->getReg() !=
3369 ((ARMOperand*)Operands[4])->getReg())) {
3370 Error(Operands[3]->getStartLoc(),
3371 "destination register must match source register");
3374 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3375 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
3376 // If we have a three-operand form, make sure to set Rn to be the operand
3377 // that isn't the same as Rd.
3379 if (Operands.size() == 6 &&
3380 ((ARMOperand*)Operands[4])->getReg() ==
3381 ((ARMOperand*)Operands[3])->getReg())
3383 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
3384 Inst.addOperand(Inst.getOperand(0));
3385 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
3391 cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
3392 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3394 ((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1);
3395 // Create a writeback register dummy placeholder.
3396 Inst.addOperand(MCOperand::CreateImm(0));
3398 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3400 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3405 cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
3406 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3408 ((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1);
3409 // Create a writeback register dummy placeholder.
3410 Inst.addOperand(MCOperand::CreateImm(0));
3412 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3414 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
3416 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3421 cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
3422 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3423 // Create a writeback register dummy placeholder.
3424 Inst.addOperand(MCOperand::CreateImm(0));
3426 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3428 ((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1);
3430 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3435 cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
3436 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3437 // Create a writeback register dummy placeholder.
3438 Inst.addOperand(MCOperand::CreateImm(0));
3440 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3442 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
3444 ((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1);
3446 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3450 /// Parse an ARM memory expression, return false if successful else return true
3451 /// or an error. The first token must be a '[' when called.
3453 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3455 assert(Parser.getTok().is(AsmToken::LBrac) &&
3456 "Token is not a Left Bracket");
3457 S = Parser.getTok().getLoc();
3458 Parser.Lex(); // Eat left bracket token.
3460 const AsmToken &BaseRegTok = Parser.getTok();
3461 int BaseRegNum = tryParseRegister();
3462 if (BaseRegNum == -1)
3463 return Error(BaseRegTok.getLoc(), "register expected");
3465 // The next token must either be a comma or a closing bracket.
3466 const AsmToken &Tok = Parser.getTok();
3467 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
3468 return Error(Tok.getLoc(), "malformed memory operand");
3470 if (Tok.is(AsmToken::RBrac)) {
3472 Parser.Lex(); // Eat right bracket token.
3474 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
3475 0, 0, false, S, E));
3477 // If there's a pre-indexing writeback marker, '!', just add it as a token
3478 // operand. It's rather odd, but syntactically valid.
3479 if (Parser.getTok().is(AsmToken::Exclaim)) {
3480 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3481 Parser.Lex(); // Eat the '!'.
3487 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
3488 Parser.Lex(); // Eat the comma.
3490 // If we have a ':', it's an alignment specifier.
3491 if (Parser.getTok().is(AsmToken::Colon)) {
3492 Parser.Lex(); // Eat the ':'.
3493 E = Parser.getTok().getLoc();
3496 if (getParser().ParseExpression(Expr))
3499 // The expression has to be a constant. Memory references with relocations
3500 // don't come through here, as they use the <label> forms of the relevant
3502 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3504 return Error (E, "constant expression expected");
3507 switch (CE->getValue()) {
3509 return Error(E, "alignment specifier must be 64, 128, or 256 bits");
3510 case 64: Align = 8; break;
3511 case 128: Align = 16; break;
3512 case 256: Align = 32; break;
3515 // Now we should have the closing ']'
3516 E = Parser.getTok().getLoc();
3517 if (Parser.getTok().isNot(AsmToken::RBrac))
3518 return Error(E, "']' expected");
3519 Parser.Lex(); // Eat right bracket token.
3521 // Don't worry about range checking the value here. That's handled by
3522 // the is*() predicates.
3523 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
3524 ARM_AM::no_shift, 0, Align,
3527 // If there's a pre-indexing writeback marker, '!', just add it as a token
3529 if (Parser.getTok().is(AsmToken::Exclaim)) {
3530 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3531 Parser.Lex(); // Eat the '!'.
3537 // If we have a '#', it's an immediate offset, else assume it's a register
3539 if (Parser.getTok().is(AsmToken::Hash)) {
3540 Parser.Lex(); // Eat the '#'.
3541 E = Parser.getTok().getLoc();
3543 bool isNegative = getParser().getTok().is(AsmToken::Minus);
3544 const MCExpr *Offset;
3545 if (getParser().ParseExpression(Offset))
3548 // The expression has to be a constant. Memory references with relocations
3549 // don't come through here, as they use the <label> forms of the relevant
3551 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
3553 return Error (E, "constant expression expected");
3555 // If the constant was #-0, represent it as INT32_MIN.
3556 int32_t Val = CE->getValue();
3557 if (isNegative && Val == 0)
3558 CE = MCConstantExpr::Create(INT32_MIN, getContext());
3560 // Now we should have the closing ']'
3561 E = Parser.getTok().getLoc();
3562 if (Parser.getTok().isNot(AsmToken::RBrac))
3563 return Error(E, "']' expected");
3564 Parser.Lex(); // Eat right bracket token.
3566 // Don't worry about range checking the value here. That's handled by
3567 // the is*() predicates.
3568 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
3569 ARM_AM::no_shift, 0, 0,
3572 // If there's a pre-indexing writeback marker, '!', just add it as a token
3574 if (Parser.getTok().is(AsmToken::Exclaim)) {
3575 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3576 Parser.Lex(); // Eat the '!'.
3582 // The register offset is optionally preceded by a '+' or '-'
3583 bool isNegative = false;
3584 if (Parser.getTok().is(AsmToken::Minus)) {
3586 Parser.Lex(); // Eat the '-'.
3587 } else if (Parser.getTok().is(AsmToken::Plus)) {
3589 Parser.Lex(); // Eat the '+'.
3592 E = Parser.getTok().getLoc();
3593 int OffsetRegNum = tryParseRegister();
3594 if (OffsetRegNum == -1)
3595 return Error(E, "register expected");
3597 // If there's a shift operator, handle it.
3598 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
3599 unsigned ShiftImm = 0;
3600 if (Parser.getTok().is(AsmToken::Comma)) {
3601 Parser.Lex(); // Eat the ','.
3602 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
3606 // Now we should have the closing ']'
3607 E = Parser.getTok().getLoc();
3608 if (Parser.getTok().isNot(AsmToken::RBrac))
3609 return Error(E, "']' expected");
3610 Parser.Lex(); // Eat right bracket token.
3612 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
3613 ShiftType, ShiftImm, 0, isNegative,
3616 // If there's a pre-indexing writeback marker, '!', just add it as a token
3618 if (Parser.getTok().is(AsmToken::Exclaim)) {
3619 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3620 Parser.Lex(); // Eat the '!'.
3626 /// parseMemRegOffsetShift - one of these two:
3627 /// ( lsl | lsr | asr | ror ) , # shift_amount
3629 /// return true if it parses a shift otherwise it returns false.
3630 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
3632 SMLoc Loc = Parser.getTok().getLoc();
3633 const AsmToken &Tok = Parser.getTok();
3634 if (Tok.isNot(AsmToken::Identifier))
3636 StringRef ShiftName = Tok.getString();
3637 if (ShiftName == "lsl" || ShiftName == "LSL")
3639 else if (ShiftName == "lsr" || ShiftName == "LSR")
3641 else if (ShiftName == "asr" || ShiftName == "ASR")
3643 else if (ShiftName == "ror" || ShiftName == "ROR")
3645 else if (ShiftName == "rrx" || ShiftName == "RRX")
3648 return Error(Loc, "illegal shift operator");
3649 Parser.Lex(); // Eat shift type token.
3651 // rrx stands alone.
3653 if (St != ARM_AM::rrx) {
3654 Loc = Parser.getTok().getLoc();
3655 // A '#' and a shift amount.
3656 const AsmToken &HashTok = Parser.getTok();
3657 if (HashTok.isNot(AsmToken::Hash))
3658 return Error(HashTok.getLoc(), "'#' expected");
3659 Parser.Lex(); // Eat hash token.
3662 if (getParser().ParseExpression(Expr))
3664 // Range check the immediate.
3665 // lsl, ror: 0 <= imm <= 31
3666 // lsr, asr: 0 <= imm <= 32
3667 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3669 return Error(Loc, "shift amount must be an immediate");
3670 int64_t Imm = CE->getValue();
3672 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
3673 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
3674 return Error(Loc, "immediate shift value out of range");
3681 /// parseFPImm - A floating point immediate expression operand.
3682 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3683 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3684 SMLoc S = Parser.getTok().getLoc();
3686 if (Parser.getTok().isNot(AsmToken::Hash))
3687 return MatchOperand_NoMatch;
3689 // Disambiguate the VMOV forms that can accept an FP immediate.
3690 // vmov.f32 <sreg>, #imm
3691 // vmov.f64 <dreg>, #imm
3692 // vmov.f32 <dreg>, #imm @ vector f32x2
3693 // vmov.f32 <qreg>, #imm @ vector f32x4
3695 // There are also the NEON VMOV instructions which expect an
3696 // integer constant. Make sure we don't try to parse an FPImm
3698 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
3699 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
3700 if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
3701 TyOp->getToken() != ".f64"))
3702 return MatchOperand_NoMatch;
3704 Parser.Lex(); // Eat the '#'.
3706 // Handle negation, as that still comes through as a separate token.
3707 bool isNegative = false;
3708 if (Parser.getTok().is(AsmToken::Minus)) {
3712 const AsmToken &Tok = Parser.getTok();
3713 if (Tok.is(AsmToken::Real)) {
3714 APFloat RealVal(APFloat::IEEEdouble, Tok.getString());
3715 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
3716 // If we had a '-' in front, toggle the sign bit.
3717 IntVal ^= (uint64_t)isNegative << 63;
3718 int Val = ARM_AM::getFP64Imm(APInt(64, IntVal));
3719 Parser.Lex(); // Eat the token.
3721 TokError("floating point value out of range");
3722 return MatchOperand_ParseFail;
3724 Operands.push_back(ARMOperand::CreateFPImm(Val, S, getContext()));
3725 return MatchOperand_Success;
3727 if (Tok.is(AsmToken::Integer)) {
3728 int64_t Val = Tok.getIntVal();
3729 Parser.Lex(); // Eat the token.
3730 if (Val > 255 || Val < 0) {
3731 TokError("encoded floating point value out of range");
3732 return MatchOperand_ParseFail;
3734 Operands.push_back(ARMOperand::CreateFPImm(Val, S, getContext()));
3735 return MatchOperand_Success;
3738 TokError("invalid floating point immediate");
3739 return MatchOperand_ParseFail;
3741 /// Parse a arm instruction operand. For now this parses the operand regardless
3742 /// of the mnemonic.
3743 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
3744 StringRef Mnemonic) {
3747 // Check if the current operand has a custom associated parser, if so, try to
3748 // custom parse the operand, or fallback to the general approach.
3749 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
3750 if (ResTy == MatchOperand_Success)
3752 // If there wasn't a custom match, try the generic matcher below. Otherwise,
3753 // there was a match, but an error occurred, in which case, just return that
3754 // the operand parsing failed.
3755 if (ResTy == MatchOperand_ParseFail)
3758 switch (getLexer().getKind()) {
3760 Error(Parser.getTok().getLoc(), "unexpected token in operand");
3762 case AsmToken::Identifier: {
3763 // If this is VMRS, check for the apsr_nzcv operand.
3764 if (!tryParseRegisterWithWriteBack(Operands))
3766 int Res = tryParseShiftRegister(Operands);
3767 if (Res == 0) // success
3769 else if (Res == -1) // irrecoverable error
3771 if (Mnemonic == "vmrs" && Parser.getTok().getString() == "apsr_nzcv") {
3772 S = Parser.getTok().getLoc();
3774 Operands.push_back(ARMOperand::CreateToken("apsr_nzcv", S));
3778 // Fall though for the Identifier case that is not a register or a
3781 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
3782 case AsmToken::Integer: // things like 1f and 2b as a branch targets
3783 case AsmToken::String: // quoted label names.
3784 case AsmToken::Dot: { // . as a branch target
3785 // This was not a register so parse other operands that start with an
3786 // identifier (like labels) as expressions and create them as immediates.
3787 const MCExpr *IdVal;
3788 S = Parser.getTok().getLoc();
3789 if (getParser().ParseExpression(IdVal))
3791 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3792 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
3795 case AsmToken::LBrac:
3796 return parseMemory(Operands);
3797 case AsmToken::LCurly:
3798 return parseRegisterList(Operands);
3799 case AsmToken::Hash: {
3800 // #42 -> immediate.
3801 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
3802 S = Parser.getTok().getLoc();
3804 bool isNegative = Parser.getTok().is(AsmToken::Minus);
3805 const MCExpr *ImmVal;
3806 if (getParser().ParseExpression(ImmVal))
3808 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
3810 int32_t Val = CE->getValue();
3811 if (isNegative && Val == 0)
3812 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
3814 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3815 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
3818 case AsmToken::Colon: {
3819 // ":lower16:" and ":upper16:" expression prefixes
3820 // FIXME: Check it's an expression prefix,
3821 // e.g. (FOO - :lower16:BAR) isn't legal.
3822 ARMMCExpr::VariantKind RefKind;
3823 if (parsePrefix(RefKind))
3826 const MCExpr *SubExprVal;
3827 if (getParser().ParseExpression(SubExprVal))
3830 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
3832 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3833 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
3839 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
3840 // :lower16: and :upper16:.
3841 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
3842 RefKind = ARMMCExpr::VK_ARM_None;
3844 // :lower16: and :upper16: modifiers
3845 assert(getLexer().is(AsmToken::Colon) && "expected a :");
3846 Parser.Lex(); // Eat ':'
3848 if (getLexer().isNot(AsmToken::Identifier)) {
3849 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
3853 StringRef IDVal = Parser.getTok().getIdentifier();
3854 if (IDVal == "lower16") {
3855 RefKind = ARMMCExpr::VK_ARM_LO16;
3856 } else if (IDVal == "upper16") {
3857 RefKind = ARMMCExpr::VK_ARM_HI16;
3859 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
3864 if (getLexer().isNot(AsmToken::Colon)) {
3865 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
3868 Parser.Lex(); // Eat the last ':'
3872 /// \brief Given a mnemonic, split out possible predication code and carry
3873 /// setting letters to form a canonical mnemonic and flags.
3875 // FIXME: Would be nice to autogen this.
3876 // FIXME: This is a bit of a maze of special cases.
3877 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
3878 unsigned &PredicationCode,
3880 unsigned &ProcessorIMod,
3881 StringRef &ITMask) {
3882 PredicationCode = ARMCC::AL;
3883 CarrySetting = false;
3886 // Ignore some mnemonics we know aren't predicated forms.
3888 // FIXME: Would be nice to autogen this.
3889 if ((Mnemonic == "movs" && isThumb()) ||
3890 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
3891 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
3892 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
3893 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
3894 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
3895 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
3896 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
3899 // First, split out any predication code. Ignore mnemonics we know aren't
3900 // predicated but do have a carry-set and so weren't caught above.
3901 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
3902 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
3903 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
3904 Mnemonic != "sbcs" && Mnemonic != "rscs") {
3905 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
3906 .Case("eq", ARMCC::EQ)
3907 .Case("ne", ARMCC::NE)
3908 .Case("hs", ARMCC::HS)
3909 .Case("cs", ARMCC::HS)
3910 .Case("lo", ARMCC::LO)
3911 .Case("cc", ARMCC::LO)
3912 .Case("mi", ARMCC::MI)
3913 .Case("pl", ARMCC::PL)
3914 .Case("vs", ARMCC::VS)
3915 .Case("vc", ARMCC::VC)
3916 .Case("hi", ARMCC::HI)
3917 .Case("ls", ARMCC::LS)
3918 .Case("ge", ARMCC::GE)
3919 .Case("lt", ARMCC::LT)
3920 .Case("gt", ARMCC::GT)
3921 .Case("le", ARMCC::LE)
3922 .Case("al", ARMCC::AL)
3925 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
3926 PredicationCode = CC;
3930 // Next, determine if we have a carry setting bit. We explicitly ignore all
3931 // the instructions we know end in 's'.
3932 if (Mnemonic.endswith("s") &&
3933 !(Mnemonic == "cps" || Mnemonic == "mls" ||
3934 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
3935 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
3936 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
3937 Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
3938 (Mnemonic == "movs" && isThumb()))) {
3939 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
3940 CarrySetting = true;
3943 // The "cps" instruction can have a interrupt mode operand which is glued into
3944 // the mnemonic. Check if this is the case, split it and parse the imod op
3945 if (Mnemonic.startswith("cps")) {
3946 // Split out any imod code.
3948 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
3949 .Case("ie", ARM_PROC::IE)
3950 .Case("id", ARM_PROC::ID)
3953 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
3954 ProcessorIMod = IMod;
3958 // The "it" instruction has the condition mask on the end of the mnemonic.
3959 if (Mnemonic.startswith("it")) {
3960 ITMask = Mnemonic.slice(2, Mnemonic.size());
3961 Mnemonic = Mnemonic.slice(0, 2);
3967 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
3968 /// inclusion of carry set or predication code operands.
3970 // FIXME: It would be nice to autogen this.
3972 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
3973 bool &CanAcceptPredicationCode) {
3974 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
3975 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
3976 Mnemonic == "add" || Mnemonic == "adc" ||
3977 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
3978 Mnemonic == "orr" || Mnemonic == "mvn" ||
3979 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
3980 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
3981 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
3982 Mnemonic == "mla" || Mnemonic == "smlal" ||
3983 Mnemonic == "umlal" || Mnemonic == "umull"))) {
3984 CanAcceptCarrySet = true;
3986 CanAcceptCarrySet = false;
3988 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
3989 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
3990 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
3991 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
3992 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
3993 (Mnemonic == "clrex" && !isThumb()) ||
3994 (Mnemonic == "nop" && isThumbOne()) ||
3995 ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" ||
3996 Mnemonic == "ldc2" || Mnemonic == "ldc2l" ||
3997 Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) ||
3998 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
4000 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
4001 CanAcceptPredicationCode = false;
4003 CanAcceptPredicationCode = true;
4006 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
4007 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
4008 CanAcceptPredicationCode = false;
4012 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4013 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4014 // FIXME: This is all horribly hacky. We really need a better way to deal
4015 // with optional operands like this in the matcher table.
4017 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4018 // another does not. Specifically, the MOVW instruction does not. So we
4019 // special case it here and remove the defaulted (non-setting) cc_out
4020 // operand if that's the instruction we're trying to match.
4022 // We do this as post-processing of the explicit operands rather than just
4023 // conditionally adding the cc_out in the first place because we need
4024 // to check the type of the parsed immediate operand.
4025 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4026 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4027 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4028 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4031 // Register-register 'add' for thumb does not have a cc_out operand
4032 // when there are only two register operands.
4033 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4034 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4035 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4036 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4038 // Register-register 'add' for thumb does not have a cc_out operand
4039 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4040 // have to check the immediate range here since Thumb2 has a variant
4041 // that can handle a different range and has a cc_out operand.
4042 if (((isThumb() && Mnemonic == "add") ||
4043 (isThumbTwo() && Mnemonic == "sub")) &&
4044 Operands.size() == 6 &&
4045 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4046 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4047 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4048 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4049 (static_cast<ARMOperand*>(Operands[5])->isReg() ||
4050 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4052 // For Thumb2, add/sub immediate does not have a cc_out operand for the
4053 // imm0_4095 variant. That's the least-preferred variant when
4054 // selecting via the generic "add" mnemonic, so to know that we
4055 // should remove the cc_out operand, we have to explicitly check that
4056 // it's not one of the other variants. Ugh.
4057 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4058 Operands.size() == 6 &&
4059 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4060 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4061 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4062 // Nest conditions rather than one big 'if' statement for readability.
4064 // If either register is a high reg, it's either one of the SP
4065 // variants (handled above) or a 32-bit encoding, so we just
4066 // check against T3.
4067 if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4068 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
4069 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
4071 // If both registers are low, we're in an IT block, and the immediate is
4072 // in range, we should use encoding T1 instead, which has a cc_out.
4074 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4075 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4076 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
4079 // Otherwise, we use encoding T4, which does not have a cc_out
4084 // The thumb2 multiply instruction doesn't have a CCOut register, so
4085 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
4086 // use the 16-bit encoding or not.
4087 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
4088 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4089 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4090 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4091 static_cast<ARMOperand*>(Operands[5])->isReg() &&
4092 // If the registers aren't low regs, the destination reg isn't the
4093 // same as one of the source regs, or the cc_out operand is zero
4094 // outside of an IT block, we have to use the 32-bit encoding, so
4095 // remove the cc_out operand.
4096 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4097 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4099 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4100 static_cast<ARMOperand*>(Operands[5])->getReg() &&
4101 static_cast<ARMOperand*>(Operands[3])->getReg() !=
4102 static_cast<ARMOperand*>(Operands[4])->getReg())))
4107 // Register-register 'add/sub' for thumb does not have a cc_out operand
4108 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
4109 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
4110 // right, this will result in better diagnostics (which operand is off)
4112 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
4113 (Operands.size() == 5 || Operands.size() == 6) &&
4114 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4115 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4116 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4122 static bool isDataTypeToken(StringRef Tok) {
4123 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
4124 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
4125 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
4126 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
4127 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
4128 Tok == ".f" || Tok == ".d";
4131 // FIXME: This bit should probably be handled via an explicit match class
4132 // in the .td files that matches the suffix instead of having it be
4133 // a literal string token the way it is now.
4134 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
4135 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
4138 /// Parse an arm instruction mnemonic followed by its operands.
4139 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
4140 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4141 // Create the leading tokens for the mnemonic, split by '.' characters.
4142 size_t Start = 0, Next = Name.find('.');
4143 StringRef Mnemonic = Name.slice(Start, Next);
4145 // Split out the predication code and carry setting flag from the mnemonic.
4146 unsigned PredicationCode;
4147 unsigned ProcessorIMod;
4150 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
4151 ProcessorIMod, ITMask);
4153 // In Thumb1, only the branch (B) instruction can be predicated.
4154 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
4155 Parser.EatToEndOfStatement();
4156 return Error(NameLoc, "conditional execution not supported in Thumb1");
4159 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
4161 // Handle the IT instruction ITMask. Convert it to a bitmask. This
4162 // is the mask as it will be for the IT encoding if the conditional
4163 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
4164 // where the conditional bit0 is zero, the instruction post-processing
4165 // will adjust the mask accordingly.
4166 if (Mnemonic == "it") {
4167 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
4168 if (ITMask.size() > 3) {
4169 Parser.EatToEndOfStatement();
4170 return Error(Loc, "too many conditions on IT instruction");
4173 for (unsigned i = ITMask.size(); i != 0; --i) {
4174 char pos = ITMask[i - 1];
4175 if (pos != 't' && pos != 'e') {
4176 Parser.EatToEndOfStatement();
4177 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
4180 if (ITMask[i - 1] == 't')
4183 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
4186 // FIXME: This is all a pretty gross hack. We should automatically handle
4187 // optional operands like this via tblgen.
4189 // Next, add the CCOut and ConditionCode operands, if needed.
4191 // For mnemonics which can ever incorporate a carry setting bit or predication
4192 // code, our matching model involves us always generating CCOut and
4193 // ConditionCode operands to match the mnemonic "as written" and then we let
4194 // the matcher deal with finding the right instruction or generating an
4195 // appropriate error.
4196 bool CanAcceptCarrySet, CanAcceptPredicationCode;
4197 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
4199 // If we had a carry-set on an instruction that can't do that, issue an
4201 if (!CanAcceptCarrySet && CarrySetting) {
4202 Parser.EatToEndOfStatement();
4203 return Error(NameLoc, "instruction '" + Mnemonic +
4204 "' can not set flags, but 's' suffix specified");
4206 // If we had a predication code on an instruction that can't do that, issue an
4208 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
4209 Parser.EatToEndOfStatement();
4210 return Error(NameLoc, "instruction '" + Mnemonic +
4211 "' is not predicable, but condition code specified");
4214 // Add the carry setting operand, if necessary.
4215 if (CanAcceptCarrySet) {
4216 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
4217 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
4221 // Add the predication code operand, if necessary.
4222 if (CanAcceptPredicationCode) {
4223 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
4225 Operands.push_back(ARMOperand::CreateCondCode(
4226 ARMCC::CondCodes(PredicationCode), Loc));
4229 // Add the processor imod operand, if necessary.
4230 if (ProcessorIMod) {
4231 Operands.push_back(ARMOperand::CreateImm(
4232 MCConstantExpr::Create(ProcessorIMod, getContext()),
4236 // Add the remaining tokens in the mnemonic.
4237 while (Next != StringRef::npos) {
4239 Next = Name.find('.', Start + 1);
4240 StringRef ExtraToken = Name.slice(Start, Next);
4242 // Some NEON instructions have an optional datatype suffix that is
4243 // completely ignored. Check for that.
4244 if (isDataTypeToken(ExtraToken) &&
4245 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
4248 if (ExtraToken != ".n") {
4249 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
4250 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
4254 // Read the remaining operands.
4255 if (getLexer().isNot(AsmToken::EndOfStatement)) {
4256 // Read the first operand.
4257 if (parseOperand(Operands, Mnemonic)) {
4258 Parser.EatToEndOfStatement();
4262 while (getLexer().is(AsmToken::Comma)) {
4263 Parser.Lex(); // Eat the comma.
4265 // Parse and remember the operand.
4266 if (parseOperand(Operands, Mnemonic)) {
4267 Parser.EatToEndOfStatement();
4273 if (getLexer().isNot(AsmToken::EndOfStatement)) {
4274 SMLoc Loc = getLexer().getLoc();
4275 Parser.EatToEndOfStatement();
4276 return Error(Loc, "unexpected token in argument list");
4279 Parser.Lex(); // Consume the EndOfStatement
4281 // Some instructions, mostly Thumb, have forms for the same mnemonic that
4282 // do and don't have a cc_out optional-def operand. With some spot-checks
4283 // of the operand list, we can figure out which variant we're trying to
4284 // parse and adjust accordingly before actually matching. We shouldn't ever
4285 // try to remove a cc_out operand that was explicitly set on the the
4286 // mnemonic, of course (CarrySetting == true). Reason number #317 the
4287 // table driven matcher doesn't fit well with the ARM instruction set.
4288 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
4289 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
4290 Operands.erase(Operands.begin() + 1);
4294 // ARM mode 'blx' need special handling, as the register operand version
4295 // is predicable, but the label operand version is not. So, we can't rely
4296 // on the Mnemonic based checking to correctly figure out when to put
4297 // a k_CondCode operand in the list. If we're trying to match the label
4298 // version, remove the k_CondCode operand here.
4299 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
4300 static_cast<ARMOperand*>(Operands[2])->isImm()) {
4301 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
4302 Operands.erase(Operands.begin() + 1);
4306 // The vector-compare-to-zero instructions have a literal token "#0" at
4307 // the end that comes to here as an immediate operand. Convert it to a
4308 // token to play nicely with the matcher.
4309 if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
4310 Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
4311 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4312 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
4313 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4314 if (CE && CE->getValue() == 0) {
4315 Operands.erase(Operands.begin() + 5);
4316 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4320 // VCMP{E} does the same thing, but with a different operand count.
4321 if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 &&
4322 static_cast<ARMOperand*>(Operands[4])->isImm()) {
4323 ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]);
4324 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4325 if (CE && CE->getValue() == 0) {
4326 Operands.erase(Operands.begin() + 4);
4327 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4331 // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
4332 // end. Convert it to a token here.
4333 if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
4334 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4335 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
4336 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4337 if (CE && CE->getValue() == 0) {
4338 Operands.erase(Operands.begin() + 5);
4339 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4347 // Validate context-sensitive operand constraints.
4349 // return 'true' if register list contains non-low GPR registers,
4350 // 'false' otherwise. If Reg is in the register list or is HiReg, set
4351 // 'containsReg' to true.
4352 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
4353 unsigned HiReg, bool &containsReg) {
4354 containsReg = false;
4355 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
4356 unsigned OpReg = Inst.getOperand(i).getReg();
4359 // Anything other than a low register isn't legal here.
4360 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
4366 // Check if the specified regisgter is in the register list of the inst,
4367 // starting at the indicated operand number.
4368 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
4369 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
4370 unsigned OpReg = Inst.getOperand(i).getReg();
4377 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around
4378 // the ARMInsts array) instead. Getting that here requires awkward
4379 // API changes, though. Better way?
4381 extern const MCInstrDesc ARMInsts[];
4383 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
4384 return ARMInsts[Opcode];
4387 // FIXME: We would really like to be able to tablegen'erate this.
4389 validateInstruction(MCInst &Inst,
4390 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4391 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
4392 SMLoc Loc = Operands[0]->getStartLoc();
4393 // Check the IT block state first.
4394 // NOTE: In Thumb mode, the BKPT instruction has the interesting property of
4395 // being allowed in IT blocks, but not being predicable. It just always
4397 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT) {
4399 if (ITState.FirstCond)
4400 ITState.FirstCond = false;
4402 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
4403 // The instruction must be predicable.
4404 if (!MCID.isPredicable())
4405 return Error(Loc, "instructions in IT block must be predicable");
4406 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
4407 unsigned ITCond = bit ? ITState.Cond :
4408 ARMCC::getOppositeCondition(ITState.Cond);
4409 if (Cond != ITCond) {
4410 // Find the condition code Operand to get its SMLoc information.
4412 for (unsigned i = 1; i < Operands.size(); ++i)
4413 if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
4414 CondLoc = Operands[i]->getStartLoc();
4415 return Error(CondLoc, "incorrect condition in IT block; got '" +
4416 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
4417 "', but expected '" +
4418 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
4420 // Check for non-'al' condition codes outside of the IT block.
4421 } else if (isThumbTwo() && MCID.isPredicable() &&
4422 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
4423 ARMCC::AL && Inst.getOpcode() != ARM::tB &&
4424 Inst.getOpcode() != ARM::t2B)
4425 return Error(Loc, "predicated instructions must be in IT block");
4427 switch (Inst.getOpcode()) {
4430 case ARM::LDRD_POST:
4432 // Rt2 must be Rt + 1.
4433 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
4434 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
4436 return Error(Operands[3]->getStartLoc(),
4437 "destination operands must be sequential");
4441 // Rt2 must be Rt + 1.
4442 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
4443 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
4445 return Error(Operands[3]->getStartLoc(),
4446 "source operands must be sequential");
4450 case ARM::STRD_POST:
4452 // Rt2 must be Rt + 1.
4453 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
4454 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
4456 return Error(Operands[3]->getStartLoc(),
4457 "source operands must be sequential");
4462 // width must be in range [1, 32-lsb]
4463 unsigned lsb = Inst.getOperand(2).getImm();
4464 unsigned widthm1 = Inst.getOperand(3).getImm();
4465 if (widthm1 >= 32 - lsb)
4466 return Error(Operands[5]->getStartLoc(),
4467 "bitfield width must be in range [1,32-lsb]");
4471 // If we're parsing Thumb2, the .w variant is available and handles
4472 // most cases that are normally illegal for a Thumb1 LDM
4473 // instruction. We'll make the transformation in processInstruction()
4476 // Thumb LDM instructions are writeback iff the base register is not
4477 // in the register list.
4478 unsigned Rn = Inst.getOperand(0).getReg();
4479 bool hasWritebackToken =
4480 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
4481 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
4482 bool listContainsBase;
4483 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
4484 return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
4485 "registers must be in range r0-r7");
4486 // If we should have writeback, then there should be a '!' token.
4487 if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
4488 return Error(Operands[2]->getStartLoc(),
4489 "writeback operator '!' expected");
4490 // If we should not have writeback, there must not be a '!'. This is
4491 // true even for the 32-bit wide encodings.
4492 if (listContainsBase && hasWritebackToken)
4493 return Error(Operands[3]->getStartLoc(),
4494 "writeback operator '!' not allowed when base register "
4495 "in register list");
4499 case ARM::t2LDMIA_UPD: {
4500 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
4501 return Error(Operands[4]->getStartLoc(),
4502 "writeback operator '!' not allowed when base register "
4503 "in register list");
4506 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
4507 // so only issue a diagnostic for thumb1. The instructions will be
4508 // switched to the t2 encodings in processInstruction() if necessary.
4510 bool listContainsBase;
4511 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
4513 return Error(Operands[2]->getStartLoc(),
4514 "registers must be in range r0-r7 or pc");
4518 bool listContainsBase;
4519 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
4521 return Error(Operands[2]->getStartLoc(),
4522 "registers must be in range r0-r7 or lr");
4525 case ARM::tSTMIA_UPD: {
4526 bool listContainsBase;
4527 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
4528 return Error(Operands[4]->getStartLoc(),
4529 "registers must be in range r0-r7");
4538 processInstruction(MCInst &Inst,
4539 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4540 switch (Inst.getOpcode()) {
4541 // Handle the MOV complex aliases.
4546 ARM_AM::ShiftOpc ShiftTy;
4547 unsigned Amt = Inst.getOperand(2).getImm();
4548 switch(Inst.getOpcode()) {
4549 default: llvm_unreachable("unexpected opcode!");
4550 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
4551 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
4552 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
4553 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
4555 // A shift by zero is a plain MOVr, not a MOVsi.
4556 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
4557 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
4559 TmpInst.setOpcode(Opc);
4560 TmpInst.addOperand(Inst.getOperand(0)); // Rd
4561 TmpInst.addOperand(Inst.getOperand(1)); // Rn
4562 if (Opc == ARM::MOVsi)
4563 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
4564 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
4565 TmpInst.addOperand(Inst.getOperand(4));
4566 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
4570 case ARM::t2LDMIA_UPD: {
4571 // If this is a load of a single register, then we should use
4572 // a post-indexed LDR instruction instead, per the ARM ARM.
4573 if (Inst.getNumOperands() != 5)
4576 TmpInst.setOpcode(ARM::t2LDR_POST);
4577 TmpInst.addOperand(Inst.getOperand(4)); // Rt
4578 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
4579 TmpInst.addOperand(Inst.getOperand(1)); // Rn
4580 TmpInst.addOperand(MCOperand::CreateImm(4));
4581 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
4582 TmpInst.addOperand(Inst.getOperand(3));
4586 case ARM::t2STMDB_UPD: {
4587 // If this is a store of a single register, then we should use
4588 // a pre-indexed STR instruction instead, per the ARM ARM.
4589 if (Inst.getNumOperands() != 5)
4592 TmpInst.setOpcode(ARM::t2STR_PRE);
4593 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
4594 TmpInst.addOperand(Inst.getOperand(4)); // Rt
4595 TmpInst.addOperand(Inst.getOperand(1)); // Rn
4596 TmpInst.addOperand(MCOperand::CreateImm(-4));
4597 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
4598 TmpInst.addOperand(Inst.getOperand(3));
4602 case ARM::LDMIA_UPD:
4603 // If this is a load of a single register via a 'pop', then we should use
4604 // a post-indexed LDR instruction instead, per the ARM ARM.
4605 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
4606 Inst.getNumOperands() == 5) {
4608 TmpInst.setOpcode(ARM::LDR_POST_IMM);
4609 TmpInst.addOperand(Inst.getOperand(4)); // Rt
4610 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
4611 TmpInst.addOperand(Inst.getOperand(1)); // Rn
4612 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
4613 TmpInst.addOperand(MCOperand::CreateImm(4));
4614 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
4615 TmpInst.addOperand(Inst.getOperand(3));
4620 case ARM::STMDB_UPD:
4621 // If this is a store of a single register via a 'push', then we should use
4622 // a pre-indexed STR instruction instead, per the ARM ARM.
4623 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
4624 Inst.getNumOperands() == 5) {
4626 TmpInst.setOpcode(ARM::STR_PRE_IMM);
4627 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
4628 TmpInst.addOperand(Inst.getOperand(4)); // Rt
4629 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
4630 TmpInst.addOperand(MCOperand::CreateImm(-4));
4631 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
4632 TmpInst.addOperand(Inst.getOperand(3));
4637 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
4638 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
4639 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
4640 // to encoding T1 if <Rd> is omitted."
4641 if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
4642 Inst.setOpcode(ARM::tADDi3);
4647 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
4648 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
4649 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
4650 // to encoding T1 if <Rd> is omitted."
4651 if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
4652 Inst.setOpcode(ARM::tSUBi3);
4657 // A Thumb conditional branch outside of an IT block is a tBcc.
4658 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
4659 Inst.setOpcode(ARM::tBcc);
4664 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
4665 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
4666 Inst.setOpcode(ARM::t2Bcc);
4671 // If the conditional is AL or we're in an IT block, we really want t2B.
4672 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
4673 Inst.setOpcode(ARM::t2B);
4678 // If the conditional is AL, we really want tB.
4679 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
4680 Inst.setOpcode(ARM::tB);
4685 // If the register list contains any high registers, or if the writeback
4686 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
4687 // instead if we're in Thumb2. Otherwise, this should have generated
4688 // an error in validateInstruction().
4689 unsigned Rn = Inst.getOperand(0).getReg();
4690 bool hasWritebackToken =
4691 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
4692 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
4693 bool listContainsBase;
4694 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
4695 (!listContainsBase && !hasWritebackToken) ||
4696 (listContainsBase && hasWritebackToken)) {
4697 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
4698 assert (isThumbTwo());
4699 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
4700 // If we're switching to the updating version, we need to insert
4701 // the writeback tied operand.
4702 if (hasWritebackToken)
4703 Inst.insert(Inst.begin(),
4704 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
4709 case ARM::tSTMIA_UPD: {
4710 // If the register list contains any high registers, we need to use
4711 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
4712 // should have generated an error in validateInstruction().
4713 unsigned Rn = Inst.getOperand(0).getReg();
4714 bool listContainsBase;
4715 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
4716 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
4717 assert (isThumbTwo());
4718 Inst.setOpcode(ARM::t2STMIA_UPD);
4724 bool listContainsBase;
4725 // If the register list contains any high registers, we need to use
4726 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
4727 // should have generated an error in validateInstruction().
4728 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
4730 assert (isThumbTwo());
4731 Inst.setOpcode(ARM::t2LDMIA_UPD);
4732 // Add the base register and writeback operands.
4733 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
4734 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
4738 bool listContainsBase;
4739 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
4741 assert (isThumbTwo());
4742 Inst.setOpcode(ARM::t2STMDB_UPD);
4743 // Add the base register and writeback operands.
4744 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
4745 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
4749 // If we can use the 16-bit encoding and the user didn't explicitly
4750 // request the 32-bit variant, transform it here.
4751 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
4752 Inst.getOperand(1).getImm() <= 255 &&
4753 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
4754 Inst.getOperand(4).getReg() == ARM::CPSR) ||
4755 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
4756 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
4757 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
4758 // The operands aren't in the same order for tMOVi8...
4760 TmpInst.setOpcode(ARM::tMOVi8);
4761 TmpInst.addOperand(Inst.getOperand(0));
4762 TmpInst.addOperand(Inst.getOperand(4));
4763 TmpInst.addOperand(Inst.getOperand(1));
4764 TmpInst.addOperand(Inst.getOperand(2));
4765 TmpInst.addOperand(Inst.getOperand(3));
4772 // If we can use the 16-bit encoding and the user didn't explicitly
4773 // request the 32-bit variant, transform it here.
4774 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
4775 isARMLowRegister(Inst.getOperand(1).getReg()) &&
4776 Inst.getOperand(2).getImm() == ARMCC::AL &&
4777 Inst.getOperand(4).getReg() == ARM::CPSR &&
4778 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
4779 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
4780 // The operands aren't the same for tMOV[S]r... (no cc_out)
4782 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
4783 TmpInst.addOperand(Inst.getOperand(0));
4784 TmpInst.addOperand(Inst.getOperand(1));
4785 TmpInst.addOperand(Inst.getOperand(2));
4786 TmpInst.addOperand(Inst.getOperand(3));
4796 // If we can use the 16-bit encoding and the user didn't explicitly
4797 // request the 32-bit variant, transform it here.
4798 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
4799 isARMLowRegister(Inst.getOperand(1).getReg()) &&
4800 Inst.getOperand(2).getImm() == 0 &&
4801 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
4802 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
4804 switch (Inst.getOpcode()) {
4805 default: llvm_unreachable("Illegal opcode!");
4806 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
4807 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
4808 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
4809 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
4811 // The operands aren't the same for thumb1 (no rotate operand).
4813 TmpInst.setOpcode(NewOpc);
4814 TmpInst.addOperand(Inst.getOperand(0));
4815 TmpInst.addOperand(Inst.getOperand(1));
4816 TmpInst.addOperand(Inst.getOperand(3));
4817 TmpInst.addOperand(Inst.getOperand(4));
4824 // The mask bits for all but the first condition are represented as
4825 // the low bit of the condition code value implies 't'. We currently
4826 // always have 1 implies 't', so XOR toggle the bits if the low bit
4827 // of the condition code is zero. The encoding also expects the low
4828 // bit of the condition to be encoded as bit 4 of the mask operand,
4829 // so mask that in if needed
4830 MCOperand &MO = Inst.getOperand(1);
4831 unsigned Mask = MO.getImm();
4832 unsigned OrigMask = Mask;
4833 unsigned TZ = CountTrailingZeros_32(Mask);
4834 if ((Inst.getOperand(0).getImm() & 1) == 0) {
4835 assert(Mask && TZ <= 3 && "illegal IT mask value!");
4836 for (unsigned i = 3; i != TZ; --i)
4842 // Set up the IT block state according to the IT instruction we just
4844 assert(!inITBlock() && "nested IT blocks?!");
4845 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
4846 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
4847 ITState.CurPosition = 0;
4848 ITState.FirstCond = true;
4855 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
4856 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
4857 // suffix depending on whether they're in an IT block or not.
4858 unsigned Opc = Inst.getOpcode();
4859 const MCInstrDesc &MCID = getInstDesc(Opc);
4860 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
4861 assert(MCID.hasOptionalDef() &&
4862 "optionally flag setting instruction missing optional def operand");
4863 assert(MCID.NumOperands == Inst.getNumOperands() &&
4864 "operand count mismatch!");
4865 // Find the optional-def operand (cc_out).
4868 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
4871 // If we're parsing Thumb1, reject it completely.
4872 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
4873 return Match_MnemonicFail;
4874 // If we're parsing Thumb2, which form is legal depends on whether we're
4876 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
4878 return Match_RequiresITBlock;
4879 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
4881 return Match_RequiresNotITBlock;
4883 // Some high-register supporting Thumb1 encodings only allow both registers
4884 // to be from r0-r7 when in Thumb2.
4885 else if (Opc == ARM::tADDhirr && isThumbOne() &&
4886 isARMLowRegister(Inst.getOperand(1).getReg()) &&
4887 isARMLowRegister(Inst.getOperand(2).getReg()))
4888 return Match_RequiresThumb2;
4889 // Others only require ARMv6 or later.
4890 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
4891 isARMLowRegister(Inst.getOperand(0).getReg()) &&
4892 isARMLowRegister(Inst.getOperand(1).getReg()))
4893 return Match_RequiresV6;
4894 return Match_Success;
4898 MatchAndEmitInstruction(SMLoc IDLoc,
4899 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4903 unsigned MatchResult;
4904 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
4905 switch (MatchResult) {
4908 // Context sensitive operand constraints aren't handled by the matcher,
4909 // so check them here.
4910 if (validateInstruction(Inst, Operands)) {
4911 // Still progress the IT block, otherwise one wrong condition causes
4912 // nasty cascading errors.
4913 forwardITPosition();
4917 // Some instructions need post-processing to, for example, tweak which
4918 // encoding is selected. Loop on it while changes happen so the
4919 // individual transformations can chain off each other. E.g.,
4920 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
4921 while (processInstruction(Inst, Operands))
4924 // Only move forward at the very end so that everything in validate
4925 // and process gets a consistent answer about whether we're in an IT
4927 forwardITPosition();
4929 Out.EmitInstruction(Inst);
4931 case Match_MissingFeature:
4932 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
4934 case Match_InvalidOperand: {
4935 SMLoc ErrorLoc = IDLoc;
4936 if (ErrorInfo != ~0U) {
4937 if (ErrorInfo >= Operands.size())
4938 return Error(IDLoc, "too few operands for instruction");
4940 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
4941 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
4944 return Error(ErrorLoc, "invalid operand for instruction");
4946 case Match_MnemonicFail:
4947 return Error(IDLoc, "invalid instruction");
4948 case Match_ConversionFail:
4949 // The converter function will have already emited a diagnostic.
4951 case Match_RequiresNotITBlock:
4952 return Error(IDLoc, "flag setting instruction only valid outside IT block");
4953 case Match_RequiresITBlock:
4954 return Error(IDLoc, "instruction only valid inside IT block");
4955 case Match_RequiresV6:
4956 return Error(IDLoc, "instruction variant requires ARMv6 or later");
4957 case Match_RequiresThumb2:
4958 return Error(IDLoc, "instruction variant requires Thumb2");
4961 llvm_unreachable("Implement any new match types added!");
4965 /// parseDirective parses the arm specific directives
4966 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
4967 StringRef IDVal = DirectiveID.getIdentifier();
4968 if (IDVal == ".word")
4969 return parseDirectiveWord(4, DirectiveID.getLoc());
4970 else if (IDVal == ".thumb")
4971 return parseDirectiveThumb(DirectiveID.getLoc());
4972 else if (IDVal == ".thumb_func")
4973 return parseDirectiveThumbFunc(DirectiveID.getLoc());
4974 else if (IDVal == ".code")
4975 return parseDirectiveCode(DirectiveID.getLoc());
4976 else if (IDVal == ".syntax")
4977 return parseDirectiveSyntax(DirectiveID.getLoc());
4981 /// parseDirectiveWord
4982 /// ::= .word [ expression (, expression)* ]
4983 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
4984 if (getLexer().isNot(AsmToken::EndOfStatement)) {
4986 const MCExpr *Value;
4987 if (getParser().ParseExpression(Value))
4990 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
4992 if (getLexer().is(AsmToken::EndOfStatement))
4995 // FIXME: Improve diagnostic.
4996 if (getLexer().isNot(AsmToken::Comma))
4997 return Error(L, "unexpected token in directive");
5006 /// parseDirectiveThumb
5008 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
5009 if (getLexer().isNot(AsmToken::EndOfStatement))
5010 return Error(L, "unexpected token in directive");
5013 // TODO: set thumb mode
5014 // TODO: tell the MC streamer the mode
5015 // getParser().getStreamer().Emit???();
5019 /// parseDirectiveThumbFunc
5020 /// ::= .thumbfunc symbol_name
5021 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
5022 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
5023 bool isMachO = MAI.hasSubsectionsViaSymbols();
5026 // Darwin asm has function name after .thumb_func direction
5029 const AsmToken &Tok = Parser.getTok();
5030 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
5031 return Error(L, "unexpected token in .thumb_func directive");
5032 Name = Tok.getIdentifier();
5033 Parser.Lex(); // Consume the identifier token.
5036 if (getLexer().isNot(AsmToken::EndOfStatement))
5037 return Error(L, "unexpected token in directive");
5040 // FIXME: assuming function name will be the line following .thumb_func
5042 Name = Parser.getTok().getIdentifier();
5045 // Mark symbol as a thumb symbol.
5046 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
5047 getParser().getStreamer().EmitThumbFunc(Func);
5051 /// parseDirectiveSyntax
5052 /// ::= .syntax unified | divided
5053 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
5054 const AsmToken &Tok = Parser.getTok();
5055 if (Tok.isNot(AsmToken::Identifier))
5056 return Error(L, "unexpected token in .syntax directive");
5057 StringRef Mode = Tok.getString();
5058 if (Mode == "unified" || Mode == "UNIFIED")
5060 else if (Mode == "divided" || Mode == "DIVIDED")
5061 return Error(L, "'.syntax divided' arm asssembly not supported");
5063 return Error(L, "unrecognized syntax mode in .syntax directive");
5065 if (getLexer().isNot(AsmToken::EndOfStatement))
5066 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
5069 // TODO tell the MC streamer the mode
5070 // getParser().getStreamer().Emit???();
5074 /// parseDirectiveCode
5075 /// ::= .code 16 | 32
5076 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
5077 const AsmToken &Tok = Parser.getTok();
5078 if (Tok.isNot(AsmToken::Integer))
5079 return Error(L, "unexpected token in .code directive");
5080 int64_t Val = Parser.getTok().getIntVal();
5086 return Error(L, "invalid operand to .code directive");
5088 if (getLexer().isNot(AsmToken::EndOfStatement))
5089 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
5095 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
5099 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
5105 extern "C" void LLVMInitializeARMAsmLexer();
5107 /// Force static initialization.
5108 extern "C" void LLVMInitializeARMAsmParser() {
5109 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
5110 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
5111 LLVMInitializeARMAsmLexer();
5114 #define GET_REGISTER_MATCHER
5115 #define GET_MATCHER_IMPLEMENTATION
5116 #include "ARMGenAsmMatcher.inc"