1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMBaseInfo.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMMCExpr.h"
13 #include "llvm/MC/MCParser/MCAsmLexer.h"
14 #include "llvm/MC/MCParser/MCAsmParser.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCAsmInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCTargetAsmParser.h"
25 #include "llvm/Support/SourceMgr.h"
26 #include "llvm/Support/TargetRegistry.h"
27 #include "llvm/Support/raw_ostream.h"
28 #include "llvm/ADT/BitVector.h"
29 #include "llvm/ADT/OwningPtr.h"
30 #include "llvm/ADT/STLExtras.h"
31 #include "llvm/ADT/SmallVector.h"
32 #include "llvm/ADT/StringExtras.h"
33 #include "llvm/ADT/StringSwitch.h"
34 #include "llvm/ADT/Twine.h"
42 class ARMAsmParser : public MCTargetAsmParser {
46 MCAsmParser &getParser() const { return Parser; }
47 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
49 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
50 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
52 int tryParseRegister();
53 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
54 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
55 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
56 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
57 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
58 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
59 const MCExpr *applyPrefixToExpr(const MCExpr *E,
60 MCSymbolRefExpr::VariantKind Variant);
63 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
64 unsigned &ShiftAmount);
65 bool parseDirectiveWord(unsigned Size, SMLoc L);
66 bool parseDirectiveThumb(SMLoc L);
67 bool parseDirectiveThumbFunc(SMLoc L);
68 bool parseDirectiveCode(SMLoc L);
69 bool parseDirectiveSyntax(SMLoc L);
71 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
72 bool &CarrySetting, unsigned &ProcessorIMod);
73 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
74 bool &CanAcceptPredicationCode);
76 bool isThumb() const {
77 // FIXME: Can tablegen auto-generate this?
78 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
80 bool isThumbOne() const {
81 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
83 bool isThumbTwo() const {
84 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
86 bool hasV6Ops() const {
87 return STI.getFeatureBits() & ARM::HasV6Ops;
90 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
91 setAvailableFeatures(FB);
94 /// @name Auto-generated Match Functions
97 #define GET_ASSEMBLER_HEADER
98 #include "ARMGenAsmMatcher.inc"
102 OperandMatchResultTy parseCoprocNumOperand(
103 SmallVectorImpl<MCParsedAsmOperand*>&);
104 OperandMatchResultTy parseCoprocRegOperand(
105 SmallVectorImpl<MCParsedAsmOperand*>&);
106 OperandMatchResultTy parseMemBarrierOptOperand(
107 SmallVectorImpl<MCParsedAsmOperand*>&);
108 OperandMatchResultTy parseProcIFlagsOperand(
109 SmallVectorImpl<MCParsedAsmOperand*>&);
110 OperandMatchResultTy parseMSRMaskOperand(
111 SmallVectorImpl<MCParsedAsmOperand*>&);
112 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
113 StringRef Op, int Low, int High);
114 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
115 return parsePKHImm(O, "lsl", 0, 31);
117 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
118 return parsePKHImm(O, "asr", 1, 32);
120 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
121 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
122 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
123 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
124 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
125 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
127 // Asm Match Converter Methods
128 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
129 const SmallVectorImpl<MCParsedAsmOperand*> &);
130 bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
131 const SmallVectorImpl<MCParsedAsmOperand*> &);
132 bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
133 const SmallVectorImpl<MCParsedAsmOperand*> &);
134 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
135 const SmallVectorImpl<MCParsedAsmOperand*> &);
136 bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
137 const SmallVectorImpl<MCParsedAsmOperand*> &);
138 bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
139 const SmallVectorImpl<MCParsedAsmOperand*> &);
140 bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
141 const SmallVectorImpl<MCParsedAsmOperand*> &);
142 bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
143 const SmallVectorImpl<MCParsedAsmOperand*> &);
144 bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
145 const SmallVectorImpl<MCParsedAsmOperand*> &);
146 bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
147 const SmallVectorImpl<MCParsedAsmOperand*> &);
148 bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
149 const SmallVectorImpl<MCParsedAsmOperand*> &);
150 bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
151 const SmallVectorImpl<MCParsedAsmOperand*> &);
152 bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
153 const SmallVectorImpl<MCParsedAsmOperand*> &);
155 bool validateInstruction(MCInst &Inst,
156 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
157 void processInstruction(MCInst &Inst,
158 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
159 bool shouldOmitCCOutOperand(StringRef Mnemonic,
160 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
163 enum ARMMatchResultTy {
164 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
169 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
170 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
171 MCAsmParserExtension::Initialize(_Parser);
173 // Initialize the set of available features.
174 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
177 // Implementation of the MCTargetAsmParser interface:
178 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
179 bool ParseInstruction(StringRef Name, SMLoc NameLoc,
180 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
181 bool ParseDirective(AsmToken DirectiveID);
183 unsigned checkTargetMatchPredicate(MCInst &Inst);
185 bool MatchAndEmitInstruction(SMLoc IDLoc,
186 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
189 } // end anonymous namespace
193 /// ARMOperand - Instances of this class represent a parsed ARM machine
195 class ARMOperand : public MCParsedAsmOperand {
219 SMLoc StartLoc, EndLoc;
220 SmallVector<unsigned, 8> Registers;
224 ARMCC::CondCodes Val;
236 ARM_PROC::IFlags Val;
256 /// Combined record for all forms of ARM address expressions.
259 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
261 const MCConstantExpr *OffsetImm; // Offset immediate value
262 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
263 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
264 unsigned ShiftImm; // shift for OffsetReg.
265 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
271 ARM_AM::ShiftOpc ShiftTy;
280 ARM_AM::ShiftOpc ShiftTy;
286 ARM_AM::ShiftOpc ShiftTy;
299 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
301 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
303 StartLoc = o.StartLoc;
317 case DPRRegisterList:
318 case SPRRegisterList:
319 Registers = o.Registers;
334 case PostIndexRegister:
335 PostIdxReg = o.PostIdxReg;
343 case ShifterImmediate:
344 ShifterImm = o.ShifterImm;
346 case ShiftedRegister:
347 RegShiftedReg = o.RegShiftedReg;
349 case ShiftedImmediate:
350 RegShiftedImm = o.RegShiftedImm;
352 case RotateImmediate:
355 case BitfieldDescriptor:
356 Bitfield = o.Bitfield;
361 /// getStartLoc - Get the location of the first token of this operand.
362 SMLoc getStartLoc() const { return StartLoc; }
363 /// getEndLoc - Get the location of the last token of this operand.
364 SMLoc getEndLoc() const { return EndLoc; }
366 ARMCC::CondCodes getCondCode() const {
367 assert(Kind == CondCode && "Invalid access!");
371 unsigned getCoproc() const {
372 assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
376 StringRef getToken() const {
377 assert(Kind == Token && "Invalid access!");
378 return StringRef(Tok.Data, Tok.Length);
381 unsigned getReg() const {
382 assert((Kind == Register || Kind == CCOut) && "Invalid access!");
386 const SmallVectorImpl<unsigned> &getRegList() const {
387 assert((Kind == RegisterList || Kind == DPRRegisterList ||
388 Kind == SPRRegisterList) && "Invalid access!");
392 const MCExpr *getImm() const {
393 assert(Kind == Immediate && "Invalid access!");
397 ARM_MB::MemBOpt getMemBarrierOpt() const {
398 assert(Kind == MemBarrierOpt && "Invalid access!");
402 ARM_PROC::IFlags getProcIFlags() const {
403 assert(Kind == ProcIFlags && "Invalid access!");
407 unsigned getMSRMask() const {
408 assert(Kind == MSRMask && "Invalid access!");
412 bool isCoprocNum() const { return Kind == CoprocNum; }
413 bool isCoprocReg() const { return Kind == CoprocReg; }
414 bool isCondCode() const { return Kind == CondCode; }
415 bool isCCOut() const { return Kind == CCOut; }
416 bool isImm() const { return Kind == Immediate; }
417 bool isImm0_1020s4() const {
418 if (Kind != Immediate)
420 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
421 if (!CE) return false;
422 int64_t Value = CE->getValue();
423 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
425 bool isImm0_508s4() const {
426 if (Kind != Immediate)
428 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
429 if (!CE) return false;
430 int64_t Value = CE->getValue();
431 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
433 bool isImm0_255() const {
434 if (Kind != Immediate)
436 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
437 if (!CE) return false;
438 int64_t Value = CE->getValue();
439 return Value >= 0 && Value < 256;
441 bool isImm0_7() const {
442 if (Kind != Immediate)
444 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
445 if (!CE) return false;
446 int64_t Value = CE->getValue();
447 return Value >= 0 && Value < 8;
449 bool isImm0_15() const {
450 if (Kind != Immediate)
452 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
453 if (!CE) return false;
454 int64_t Value = CE->getValue();
455 return Value >= 0 && Value < 16;
457 bool isImm0_31() const {
458 if (Kind != Immediate)
460 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
461 if (!CE) return false;
462 int64_t Value = CE->getValue();
463 return Value >= 0 && Value < 32;
465 bool isImm1_16() const {
466 if (Kind != Immediate)
468 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
469 if (!CE) return false;
470 int64_t Value = CE->getValue();
471 return Value > 0 && Value < 17;
473 bool isImm1_32() const {
474 if (Kind != Immediate)
476 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
477 if (!CE) return false;
478 int64_t Value = CE->getValue();
479 return Value > 0 && Value < 33;
481 bool isImm0_65535() const {
482 if (Kind != Immediate)
484 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
485 if (!CE) return false;
486 int64_t Value = CE->getValue();
487 return Value >= 0 && Value < 65536;
489 bool isImm0_65535Expr() const {
490 if (Kind != Immediate)
492 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
493 // If it's not a constant expression, it'll generate a fixup and be
495 if (!CE) return true;
496 int64_t Value = CE->getValue();
497 return Value >= 0 && Value < 65536;
499 bool isImm24bit() const {
500 if (Kind != Immediate)
502 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
503 if (!CE) return false;
504 int64_t Value = CE->getValue();
505 return Value >= 0 && Value <= 0xffffff;
507 bool isImmThumbSR() const {
508 if (Kind != Immediate)
510 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
511 if (!CE) return false;
512 int64_t Value = CE->getValue();
513 return Value > 0 && Value < 33;
515 bool isPKHLSLImm() const {
516 if (Kind != Immediate)
518 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
519 if (!CE) return false;
520 int64_t Value = CE->getValue();
521 return Value >= 0 && Value < 32;
523 bool isPKHASRImm() const {
524 if (Kind != Immediate)
526 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
527 if (!CE) return false;
528 int64_t Value = CE->getValue();
529 return Value > 0 && Value <= 32;
531 bool isARMSOImm() const {
532 if (Kind != Immediate)
534 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
535 if (!CE) return false;
536 int64_t Value = CE->getValue();
537 return ARM_AM::getSOImmVal(Value) != -1;
539 bool isT2SOImm() const {
540 if (Kind != Immediate)
542 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
543 if (!CE) return false;
544 int64_t Value = CE->getValue();
545 return ARM_AM::getT2SOImmVal(Value) != -1;
547 bool isSetEndImm() const {
548 if (Kind != Immediate)
550 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
551 if (!CE) return false;
552 int64_t Value = CE->getValue();
553 return Value == 1 || Value == 0;
555 bool isReg() const { return Kind == Register; }
556 bool isRegList() const { return Kind == RegisterList; }
557 bool isDPRRegList() const { return Kind == DPRRegisterList; }
558 bool isSPRRegList() const { return Kind == SPRRegisterList; }
559 bool isToken() const { return Kind == Token; }
560 bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
561 bool isMemory() const { return Kind == Memory; }
562 bool isShifterImm() const { return Kind == ShifterImmediate; }
563 bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
564 bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
565 bool isRotImm() const { return Kind == RotateImmediate; }
566 bool isBitfield() const { return Kind == BitfieldDescriptor; }
567 bool isPostIdxRegShifted() const { return Kind == PostIndexRegister; }
568 bool isPostIdxReg() const {
569 return Kind == PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
571 bool isMemNoOffset() const {
574 // No offset of any kind.
575 return Mem.OffsetRegNum == 0 && Mem.OffsetImm == 0;
577 bool isAddrMode2() const {
580 // Check for register offset.
581 if (Mem.OffsetRegNum) return true;
582 // Immediate offset in range [-4095, 4095].
583 if (!Mem.OffsetImm) return true;
584 int64_t Val = Mem.OffsetImm->getValue();
585 return Val > -4096 && Val < 4096;
587 bool isAM2OffsetImm() const {
588 if (Kind != Immediate)
590 // Immediate offset in range [-4095, 4095].
591 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
592 if (!CE) return false;
593 int64_t Val = CE->getValue();
594 return Val > -4096 && Val < 4096;
596 bool isAddrMode3() const {
599 // No shifts are legal for AM3.
600 if (Mem.ShiftType != ARM_AM::no_shift) return false;
601 // Check for register offset.
602 if (Mem.OffsetRegNum) return true;
603 // Immediate offset in range [-255, 255].
604 if (!Mem.OffsetImm) return true;
605 int64_t Val = Mem.OffsetImm->getValue();
606 return Val > -256 && Val < 256;
608 bool isAM3Offset() const {
609 if (Kind != Immediate && Kind != PostIndexRegister)
611 if (Kind == PostIndexRegister)
612 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
613 // Immediate offset in range [-255, 255].
614 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
615 if (!CE) return false;
616 int64_t Val = CE->getValue();
617 // Special case, #-0 is INT32_MIN.
618 return (Val > -256 && Val < 256) || Val == INT32_MIN;
620 bool isAddrMode5() const {
623 // Check for register offset.
624 if (Mem.OffsetRegNum) return false;
625 // Immediate offset in range [-1020, 1020] and a multiple of 4.
626 if (!Mem.OffsetImm) return true;
627 int64_t Val = Mem.OffsetImm->getValue();
628 return Val >= -1020 && Val <= 1020 && ((Val & 3) == 0);
630 bool isMemRegOffset() const {
631 if (Kind != Memory || !Mem.OffsetRegNum)
635 bool isMemThumbRR() const {
636 // Thumb reg+reg addressing is simple. Just two registers, a base and
637 // an offset. No shifts, negations or any other complicating factors.
638 if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative ||
639 Mem.ShiftType != ARM_AM::no_shift)
641 return isARMLowRegister(Mem.BaseRegNum) &&
642 (!Mem.OffsetRegNum || isARMLowRegister(Mem.OffsetRegNum));
644 bool isMemThumbRIs4() const {
645 if (Kind != Memory || Mem.OffsetRegNum != 0 ||
646 !isARMLowRegister(Mem.BaseRegNum))
648 // Immediate offset, multiple of 4 in range [0, 124].
649 if (!Mem.OffsetImm) return true;
650 int64_t Val = Mem.OffsetImm->getValue();
651 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
653 bool isMemThumbRIs2() const {
654 if (Kind != Memory || Mem.OffsetRegNum != 0 ||
655 !isARMLowRegister(Mem.BaseRegNum))
657 // Immediate offset, multiple of 4 in range [0, 62].
658 if (!Mem.OffsetImm) return true;
659 int64_t Val = Mem.OffsetImm->getValue();
660 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
662 bool isMemThumbRIs1() const {
663 if (Kind != Memory || Mem.OffsetRegNum != 0 ||
664 !isARMLowRegister(Mem.BaseRegNum))
666 // Immediate offset in range [0, 31].
667 if (!Mem.OffsetImm) return true;
668 int64_t Val = Mem.OffsetImm->getValue();
669 return Val >= 0 && Val <= 31;
671 bool isMemThumbSPI() const {
672 if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP)
674 // Immediate offset, multiple of 4 in range [0, 1020].
675 if (!Mem.OffsetImm) return true;
676 int64_t Val = Mem.OffsetImm->getValue();
677 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
679 bool isMemImm8Offset() const {
680 if (Kind != Memory || Mem.OffsetRegNum != 0)
682 // Immediate offset in range [-255, 255].
683 if (!Mem.OffsetImm) return true;
684 int64_t Val = Mem.OffsetImm->getValue();
685 return Val > -256 && Val < 256;
687 bool isMemImm12Offset() const {
688 // If we have an immediate that's not a constant, treat it as a label
689 // reference needing a fixup. If it is a constant, it's something else
691 if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
694 if (Kind != Memory || Mem.OffsetRegNum != 0)
696 // Immediate offset in range [-4095, 4095].
697 if (!Mem.OffsetImm) return true;
698 int64_t Val = Mem.OffsetImm->getValue();
699 return Val > -4096 && Val < 4096;
701 bool isPostIdxImm8() const {
702 if (Kind != Immediate)
704 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
705 if (!CE) return false;
706 int64_t Val = CE->getValue();
707 return Val > -256 && Val < 256;
710 bool isMSRMask() const { return Kind == MSRMask; }
711 bool isProcIFlags() const { return Kind == ProcIFlags; }
713 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
714 // Add as immediates when possible. Null MCExpr = 0.
716 Inst.addOperand(MCOperand::CreateImm(0));
717 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
718 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
720 Inst.addOperand(MCOperand::CreateExpr(Expr));
723 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
724 assert(N == 2 && "Invalid number of operands!");
725 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
726 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
727 Inst.addOperand(MCOperand::CreateReg(RegNum));
730 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
731 assert(N == 1 && "Invalid number of operands!");
732 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
735 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
736 assert(N == 1 && "Invalid number of operands!");
737 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
740 void addCCOutOperands(MCInst &Inst, unsigned N) const {
741 assert(N == 1 && "Invalid number of operands!");
742 Inst.addOperand(MCOperand::CreateReg(getReg()));
745 void addRegOperands(MCInst &Inst, unsigned N) const {
746 assert(N == 1 && "Invalid number of operands!");
747 Inst.addOperand(MCOperand::CreateReg(getReg()));
750 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
751 assert(N == 3 && "Invalid number of operands!");
752 assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
753 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
754 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
755 Inst.addOperand(MCOperand::CreateImm(
756 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
759 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
760 assert(N == 2 && "Invalid number of operands!");
761 assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
762 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
763 Inst.addOperand(MCOperand::CreateImm(
764 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
768 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
769 assert(N == 1 && "Invalid number of operands!");
770 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
774 void addRegListOperands(MCInst &Inst, unsigned N) const {
775 assert(N == 1 && "Invalid number of operands!");
776 const SmallVectorImpl<unsigned> &RegList = getRegList();
777 for (SmallVectorImpl<unsigned>::const_iterator
778 I = RegList.begin(), E = RegList.end(); I != E; ++I)
779 Inst.addOperand(MCOperand::CreateReg(*I));
782 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
783 addRegListOperands(Inst, N);
786 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
787 addRegListOperands(Inst, N);
790 void addRotImmOperands(MCInst &Inst, unsigned N) const {
791 assert(N == 1 && "Invalid number of operands!");
792 // Encoded as val>>3. The printer handles display as 8, 16, 24.
793 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
796 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
797 assert(N == 1 && "Invalid number of operands!");
798 // Munge the lsb/width into a bitfield mask.
799 unsigned lsb = Bitfield.LSB;
800 unsigned width = Bitfield.Width;
801 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
802 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
803 (32 - (lsb + width)));
804 Inst.addOperand(MCOperand::CreateImm(Mask));
807 void addImmOperands(MCInst &Inst, unsigned N) const {
808 assert(N == 1 && "Invalid number of operands!");
809 addExpr(Inst, getImm());
812 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
813 assert(N == 1 && "Invalid number of operands!");
814 // The immediate is scaled by four in the encoding and is stored
815 // in the MCInst as such. Lop off the low two bits here.
816 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
817 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
820 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
821 assert(N == 1 && "Invalid number of operands!");
822 // The immediate is scaled by four in the encoding and is stored
823 // in the MCInst as such. Lop off the low two bits here.
824 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
825 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
828 void addImm0_255Operands(MCInst &Inst, unsigned N) const {
829 assert(N == 1 && "Invalid number of operands!");
830 addExpr(Inst, getImm());
833 void addImm0_7Operands(MCInst &Inst, unsigned N) const {
834 assert(N == 1 && "Invalid number of operands!");
835 addExpr(Inst, getImm());
838 void addImm0_15Operands(MCInst &Inst, unsigned N) const {
839 assert(N == 1 && "Invalid number of operands!");
840 addExpr(Inst, getImm());
843 void addImm0_31Operands(MCInst &Inst, unsigned N) const {
844 assert(N == 1 && "Invalid number of operands!");
845 addExpr(Inst, getImm());
848 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
849 assert(N == 1 && "Invalid number of operands!");
850 // The constant encodes as the immediate-1, and we store in the instruction
851 // the bits as encoded, so subtract off one here.
852 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
853 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
856 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
857 assert(N == 1 && "Invalid number of operands!");
858 // The constant encodes as the immediate-1, and we store in the instruction
859 // the bits as encoded, so subtract off one here.
860 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
861 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
864 void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
865 assert(N == 1 && "Invalid number of operands!");
866 addExpr(Inst, getImm());
869 void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
870 assert(N == 1 && "Invalid number of operands!");
871 addExpr(Inst, getImm());
874 void addImm24bitOperands(MCInst &Inst, unsigned N) const {
875 assert(N == 1 && "Invalid number of operands!");
876 addExpr(Inst, getImm());
879 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
880 assert(N == 1 && "Invalid number of operands!");
881 // The constant encodes as the immediate, except for 32, which encodes as
883 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
884 unsigned Imm = CE->getValue();
885 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
888 void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
889 assert(N == 1 && "Invalid number of operands!");
890 addExpr(Inst, getImm());
893 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
894 assert(N == 1 && "Invalid number of operands!");
895 // An ASR value of 32 encodes as 0, so that's how we want to add it to
896 // the instruction as well.
897 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
898 int Val = CE->getValue();
899 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
902 void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
903 assert(N == 1 && "Invalid number of operands!");
904 addExpr(Inst, getImm());
907 void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
908 assert(N == 1 && "Invalid number of operands!");
909 addExpr(Inst, getImm());
912 void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
913 assert(N == 1 && "Invalid number of operands!");
914 addExpr(Inst, getImm());
917 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
918 assert(N == 1 && "Invalid number of operands!");
919 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
922 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
923 assert(N == 1 && "Invalid number of operands!");
924 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
927 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
928 assert(N == 3 && "Invalid number of operands!");
929 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
930 if (!Mem.OffsetRegNum) {
931 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
932 // Special case for #-0
933 if (Val == INT32_MIN) Val = 0;
934 if (Val < 0) Val = -Val;
935 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
937 // For register offset, we encode the shift type and negation flag
939 Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
940 Mem.ShiftImm, Mem.ShiftType);
942 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
943 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
944 Inst.addOperand(MCOperand::CreateImm(Val));
947 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
948 assert(N == 2 && "Invalid number of operands!");
949 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
950 assert(CE && "non-constant AM2OffsetImm operand!");
951 int32_t Val = CE->getValue();
952 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
953 // Special case for #-0
954 if (Val == INT32_MIN) Val = 0;
955 if (Val < 0) Val = -Val;
956 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
957 Inst.addOperand(MCOperand::CreateReg(0));
958 Inst.addOperand(MCOperand::CreateImm(Val));
961 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
962 assert(N == 3 && "Invalid number of operands!");
963 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
964 if (!Mem.OffsetRegNum) {
965 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
966 // Special case for #-0
967 if (Val == INT32_MIN) Val = 0;
968 if (Val < 0) Val = -Val;
969 Val = ARM_AM::getAM3Opc(AddSub, Val);
971 // For register offset, we encode the shift type and negation flag
973 Val = ARM_AM::getAM3Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
975 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
976 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
977 Inst.addOperand(MCOperand::CreateImm(Val));
980 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
981 assert(N == 2 && "Invalid number of operands!");
982 if (Kind == PostIndexRegister) {
984 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
985 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
986 Inst.addOperand(MCOperand::CreateImm(Val));
991 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
992 int32_t Val = CE->getValue();
993 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
994 // Special case for #-0
995 if (Val == INT32_MIN) Val = 0;
996 if (Val < 0) Val = -Val;
997 Val = ARM_AM::getAM3Opc(AddSub, Val);
998 Inst.addOperand(MCOperand::CreateReg(0));
999 Inst.addOperand(MCOperand::CreateImm(Val));
1002 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1003 assert(N == 2 && "Invalid number of operands!");
1004 // The lower two bits are always zero and as such are not encoded.
1005 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0;
1006 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1007 // Special case for #-0
1008 if (Val == INT32_MIN) Val = 0;
1009 if (Val < 0) Val = -Val;
1010 Val = ARM_AM::getAM5Opc(AddSub, Val);
1011 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1012 Inst.addOperand(MCOperand::CreateImm(Val));
1015 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1016 assert(N == 2 && "Invalid number of operands!");
1017 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1018 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1019 Inst.addOperand(MCOperand::CreateImm(Val));
1022 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1023 assert(N == 2 && "Invalid number of operands!");
1024 // If this is an immediate, it's a label reference.
1025 if (Kind == Immediate) {
1026 addExpr(Inst, getImm());
1027 Inst.addOperand(MCOperand::CreateImm(0));
1031 // Otherwise, it's a normal memory reg+offset.
1032 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1033 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1034 Inst.addOperand(MCOperand::CreateImm(Val));
1037 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1038 assert(N == 3 && "Invalid number of operands!");
1039 unsigned Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
1040 Mem.ShiftImm, Mem.ShiftType);
1041 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1042 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1043 Inst.addOperand(MCOperand::CreateImm(Val));
1046 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1047 assert(N == 2 && "Invalid number of operands!");
1048 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1049 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1052 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1053 assert(N == 2 && "Invalid number of operands!");
1054 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1055 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1056 Inst.addOperand(MCOperand::CreateImm(Val));
1059 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1060 assert(N == 2 && "Invalid number of operands!");
1061 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 2) : 0;
1062 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1063 Inst.addOperand(MCOperand::CreateImm(Val));
1066 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1067 assert(N == 2 && "Invalid number of operands!");
1068 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue()) : 0;
1069 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1070 Inst.addOperand(MCOperand::CreateImm(Val));
1073 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1074 assert(N == 2 && "Invalid number of operands!");
1075 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1076 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1077 Inst.addOperand(MCOperand::CreateImm(Val));
1080 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1081 assert(N == 1 && "Invalid number of operands!");
1082 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1083 assert(CE && "non-constant post-idx-imm8 operand!");
1084 int Imm = CE->getValue();
1085 bool isAdd = Imm >= 0;
1086 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1087 Inst.addOperand(MCOperand::CreateImm(Imm));
1090 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1091 assert(N == 2 && "Invalid number of operands!");
1092 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1093 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1096 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1097 assert(N == 2 && "Invalid number of operands!");
1098 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1099 // The sign, shift type, and shift amount are encoded in a single operand
1100 // using the AM2 encoding helpers.
1101 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1102 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1103 PostIdxReg.ShiftTy);
1104 Inst.addOperand(MCOperand::CreateImm(Imm));
1107 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1108 assert(N == 1 && "Invalid number of operands!");
1109 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1112 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1113 assert(N == 1 && "Invalid number of operands!");
1114 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1117 virtual void print(raw_ostream &OS) const;
1119 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1120 ARMOperand *Op = new ARMOperand(CondCode);
1127 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1128 ARMOperand *Op = new ARMOperand(CoprocNum);
1129 Op->Cop.Val = CopVal;
1135 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1136 ARMOperand *Op = new ARMOperand(CoprocReg);
1137 Op->Cop.Val = CopVal;
1143 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1144 ARMOperand *Op = new ARMOperand(CCOut);
1145 Op->Reg.RegNum = RegNum;
1151 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1152 ARMOperand *Op = new ARMOperand(Token);
1153 Op->Tok.Data = Str.data();
1154 Op->Tok.Length = Str.size();
1160 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1161 ARMOperand *Op = new ARMOperand(Register);
1162 Op->Reg.RegNum = RegNum;
1168 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1173 ARMOperand *Op = new ARMOperand(ShiftedRegister);
1174 Op->RegShiftedReg.ShiftTy = ShTy;
1175 Op->RegShiftedReg.SrcReg = SrcReg;
1176 Op->RegShiftedReg.ShiftReg = ShiftReg;
1177 Op->RegShiftedReg.ShiftImm = ShiftImm;
1183 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1187 ARMOperand *Op = new ARMOperand(ShiftedImmediate);
1188 Op->RegShiftedImm.ShiftTy = ShTy;
1189 Op->RegShiftedImm.SrcReg = SrcReg;
1190 Op->RegShiftedImm.ShiftImm = ShiftImm;
1196 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1198 ARMOperand *Op = new ARMOperand(ShifterImmediate);
1199 Op->ShifterImm.isASR = isASR;
1200 Op->ShifterImm.Imm = Imm;
1206 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1207 ARMOperand *Op = new ARMOperand(RotateImmediate);
1208 Op->RotImm.Imm = Imm;
1214 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1216 ARMOperand *Op = new ARMOperand(BitfieldDescriptor);
1217 Op->Bitfield.LSB = LSB;
1218 Op->Bitfield.Width = Width;
1225 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1226 SMLoc StartLoc, SMLoc EndLoc) {
1227 KindTy Kind = RegisterList;
1229 if (llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].
1230 contains(Regs.front().first))
1231 Kind = DPRRegisterList;
1232 else if (llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].
1233 contains(Regs.front().first))
1234 Kind = SPRRegisterList;
1236 ARMOperand *Op = new ARMOperand(Kind);
1237 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1238 I = Regs.begin(), E = Regs.end(); I != E; ++I)
1239 Op->Registers.push_back(I->first);
1240 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1241 Op->StartLoc = StartLoc;
1242 Op->EndLoc = EndLoc;
1246 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1247 ARMOperand *Op = new ARMOperand(Immediate);
1254 static ARMOperand *CreateMem(unsigned BaseRegNum,
1255 const MCConstantExpr *OffsetImm,
1256 unsigned OffsetRegNum,
1257 ARM_AM::ShiftOpc ShiftType,
1261 ARMOperand *Op = new ARMOperand(Memory);
1262 Op->Mem.BaseRegNum = BaseRegNum;
1263 Op->Mem.OffsetImm = OffsetImm;
1264 Op->Mem.OffsetRegNum = OffsetRegNum;
1265 Op->Mem.ShiftType = ShiftType;
1266 Op->Mem.ShiftImm = ShiftImm;
1267 Op->Mem.isNegative = isNegative;
1273 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1274 ARM_AM::ShiftOpc ShiftTy,
1277 ARMOperand *Op = new ARMOperand(PostIndexRegister);
1278 Op->PostIdxReg.RegNum = RegNum;
1279 Op->PostIdxReg.isAdd = isAdd;
1280 Op->PostIdxReg.ShiftTy = ShiftTy;
1281 Op->PostIdxReg.ShiftImm = ShiftImm;
1287 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1288 ARMOperand *Op = new ARMOperand(MemBarrierOpt);
1289 Op->MBOpt.Val = Opt;
1295 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1296 ARMOperand *Op = new ARMOperand(ProcIFlags);
1297 Op->IFlags.Val = IFlags;
1303 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1304 ARMOperand *Op = new ARMOperand(MSRMask);
1305 Op->MMask.Val = MMask;
1312 } // end anonymous namespace.
1314 void ARMOperand::print(raw_ostream &OS) const {
1317 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1320 OS << "<ccout " << getReg() << ">";
1323 OS << "<coprocessor number: " << getCoproc() << ">";
1326 OS << "<coprocessor register: " << getCoproc() << ">";
1329 OS << "<mask: " << getMSRMask() << ">";
1332 getImm()->print(OS);
1335 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1339 << " base:" << Mem.BaseRegNum;
1342 case PostIndexRegister:
1343 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
1344 << PostIdxReg.RegNum;
1345 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1346 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1347 << PostIdxReg.ShiftImm;
1351 OS << "<ARM_PROC::";
1352 unsigned IFlags = getProcIFlags();
1353 for (int i=2; i >= 0; --i)
1354 if (IFlags & (1 << i))
1355 OS << ARM_PROC::IFlagsToString(1 << i);
1360 OS << "<register " << getReg() << ">";
1362 case ShifterImmediate:
1363 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1364 << " #" << ShifterImm.Imm << ">";
1366 case ShiftedRegister:
1367 OS << "<so_reg_reg "
1368 << RegShiftedReg.SrcReg
1369 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1370 << ", " << RegShiftedReg.ShiftReg << ", "
1371 << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1374 case ShiftedImmediate:
1375 OS << "<so_reg_imm "
1376 << RegShiftedImm.SrcReg
1377 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1378 << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
1381 case RotateImmediate:
1382 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
1384 case BitfieldDescriptor:
1385 OS << "<bitfield " << "lsb: " << Bitfield.LSB
1386 << ", width: " << Bitfield.Width << ">";
1389 case DPRRegisterList:
1390 case SPRRegisterList: {
1391 OS << "<register_list ";
1393 const SmallVectorImpl<unsigned> &RegList = getRegList();
1394 for (SmallVectorImpl<unsigned>::const_iterator
1395 I = RegList.begin(), E = RegList.end(); I != E; ) {
1397 if (++I < E) OS << ", ";
1404 OS << "'" << getToken() << "'";
1409 /// @name Auto-generated Match Functions
1412 static unsigned MatchRegisterName(StringRef Name);
1416 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
1417 SMLoc &StartLoc, SMLoc &EndLoc) {
1418 RegNo = tryParseRegister();
1420 return (RegNo == (unsigned)-1);
1423 /// Try to parse a register name. The token must be an Identifier when called,
1424 /// and if it is a register name the token is eaten and the register number is
1425 /// returned. Otherwise return -1.
1427 int ARMAsmParser::tryParseRegister() {
1428 const AsmToken &Tok = Parser.getTok();
1429 if (Tok.isNot(AsmToken::Identifier)) return -1;
1431 // FIXME: Validate register for the current architecture; we have to do
1432 // validation later, so maybe there is no need for this here.
1433 std::string upperCase = Tok.getString().str();
1434 std::string lowerCase = LowercaseString(upperCase);
1435 unsigned RegNum = MatchRegisterName(lowerCase);
1437 RegNum = StringSwitch<unsigned>(lowerCase)
1438 .Case("r13", ARM::SP)
1439 .Case("r14", ARM::LR)
1440 .Case("r15", ARM::PC)
1441 .Case("ip", ARM::R12)
1444 if (!RegNum) return -1;
1446 Parser.Lex(); // Eat identifier token.
1450 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
1451 // If a recoverable error occurs, return 1. If an irrecoverable error
1452 // occurs, return -1. An irrecoverable error is one where tokens have been
1453 // consumed in the process of trying to parse the shifter (i.e., when it is
1454 // indeed a shifter operand, but malformed).
1455 int ARMAsmParser::tryParseShiftRegister(
1456 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1457 SMLoc S = Parser.getTok().getLoc();
1458 const AsmToken &Tok = Parser.getTok();
1459 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1461 std::string upperCase = Tok.getString().str();
1462 std::string lowerCase = LowercaseString(upperCase);
1463 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
1464 .Case("lsl", ARM_AM::lsl)
1465 .Case("lsr", ARM_AM::lsr)
1466 .Case("asr", ARM_AM::asr)
1467 .Case("ror", ARM_AM::ror)
1468 .Case("rrx", ARM_AM::rrx)
1469 .Default(ARM_AM::no_shift);
1471 if (ShiftTy == ARM_AM::no_shift)
1474 Parser.Lex(); // Eat the operator.
1476 // The source register for the shift has already been added to the
1477 // operand list, so we need to pop it off and combine it into the shifted
1478 // register operand instead.
1479 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
1480 if (!PrevOp->isReg())
1481 return Error(PrevOp->getStartLoc(), "shift must be of a register");
1482 int SrcReg = PrevOp->getReg();
1485 if (ShiftTy == ARM_AM::rrx) {
1486 // RRX Doesn't have an explicit shift amount. The encoder expects
1487 // the shift register to be the same as the source register. Seems odd,
1491 // Figure out if this is shifted by a constant or a register (for non-RRX).
1492 if (Parser.getTok().is(AsmToken::Hash)) {
1493 Parser.Lex(); // Eat hash.
1494 SMLoc ImmLoc = Parser.getTok().getLoc();
1495 const MCExpr *ShiftExpr = 0;
1496 if (getParser().ParseExpression(ShiftExpr)) {
1497 Error(ImmLoc, "invalid immediate shift value");
1500 // The expression must be evaluatable as an immediate.
1501 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
1503 Error(ImmLoc, "invalid immediate shift value");
1506 // Range check the immediate.
1507 // lsl, ror: 0 <= imm <= 31
1508 // lsr, asr: 0 <= imm <= 32
1509 Imm = CE->getValue();
1511 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
1512 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
1513 Error(ImmLoc, "immediate shift value out of range");
1516 } else if (Parser.getTok().is(AsmToken::Identifier)) {
1517 ShiftReg = tryParseRegister();
1518 SMLoc L = Parser.getTok().getLoc();
1519 if (ShiftReg == -1) {
1520 Error (L, "expected immediate or register in shift operand");
1524 Error (Parser.getTok().getLoc(),
1525 "expected immediate or register in shift operand");
1530 if (ShiftReg && ShiftTy != ARM_AM::rrx)
1531 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
1533 S, Parser.getTok().getLoc()));
1535 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
1536 S, Parser.getTok().getLoc()));
1542 /// Try to parse a register name. The token must be an Identifier when called.
1543 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
1544 /// if there is a "writeback". 'true' if it's not a register.
1546 /// TODO this is likely to change to allow different register types and or to
1547 /// parse for a specific register type.
1549 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1550 SMLoc S = Parser.getTok().getLoc();
1551 int RegNo = tryParseRegister();
1555 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1557 const AsmToken &ExclaimTok = Parser.getTok();
1558 if (ExclaimTok.is(AsmToken::Exclaim)) {
1559 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
1560 ExclaimTok.getLoc()));
1561 Parser.Lex(); // Eat exclaim token
1567 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
1568 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
1570 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
1571 // Use the same layout as the tablegen'erated register name matcher. Ugly,
1573 switch (Name.size()) {
1576 if (Name[0] != CoprocOp)
1593 if (Name[0] != CoprocOp || Name[1] != '1')
1597 case '0': return 10;
1598 case '1': return 11;
1599 case '2': return 12;
1600 case '3': return 13;
1601 case '4': return 14;
1602 case '5': return 15;
1610 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
1611 /// token must be an Identifier when called, and if it is a coprocessor
1612 /// number, the token is eaten and the operand is added to the operand list.
1613 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1614 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1615 SMLoc S = Parser.getTok().getLoc();
1616 const AsmToken &Tok = Parser.getTok();
1617 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1619 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
1621 return MatchOperand_NoMatch;
1623 Parser.Lex(); // Eat identifier token.
1624 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
1625 return MatchOperand_Success;
1628 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
1629 /// token must be an Identifier when called, and if it is a coprocessor
1630 /// number, the token is eaten and the operand is added to the operand list.
1631 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1632 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1633 SMLoc S = Parser.getTok().getLoc();
1634 const AsmToken &Tok = Parser.getTok();
1635 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1637 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
1639 return MatchOperand_NoMatch;
1641 Parser.Lex(); // Eat identifier token.
1642 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
1643 return MatchOperand_Success;
1646 /// Parse a register list, return it if successful else return null. The first
1647 /// token must be a '{' when called.
1649 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1650 assert(Parser.getTok().is(AsmToken::LCurly) &&
1651 "Token is not a Left Curly Brace");
1652 SMLoc S = Parser.getTok().getLoc();
1654 // Read the rest of the registers in the list.
1655 unsigned PrevRegNum = 0;
1656 SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
1659 bool IsRange = Parser.getTok().is(AsmToken::Minus);
1660 Parser.Lex(); // Eat non-identifier token.
1662 const AsmToken &RegTok = Parser.getTok();
1663 SMLoc RegLoc = RegTok.getLoc();
1664 if (RegTok.isNot(AsmToken::Identifier)) {
1665 Error(RegLoc, "register expected");
1669 int RegNum = tryParseRegister();
1671 Error(RegLoc, "register expected");
1676 int Reg = PrevRegNum;
1679 Registers.push_back(std::make_pair(Reg, RegLoc));
1680 } while (Reg != RegNum);
1682 Registers.push_back(std::make_pair(RegNum, RegLoc));
1685 PrevRegNum = RegNum;
1686 } while (Parser.getTok().is(AsmToken::Comma) ||
1687 Parser.getTok().is(AsmToken::Minus));
1689 // Process the right curly brace of the list.
1690 const AsmToken &RCurlyTok = Parser.getTok();
1691 if (RCurlyTok.isNot(AsmToken::RCurly)) {
1692 Error(RCurlyTok.getLoc(), "'}' expected");
1696 SMLoc E = RCurlyTok.getLoc();
1697 Parser.Lex(); // Eat right curly brace token.
1699 // Verify the register list.
1700 bool EmittedWarning = false;
1701 unsigned HighRegNum = 0;
1702 BitVector RegMap(32);
1703 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
1704 const std::pair<unsigned, SMLoc> &RegInfo = Registers[i];
1705 unsigned Reg = getARMRegisterNumbering(RegInfo.first);
1708 Error(RegInfo.second, "register duplicated in register list");
1712 if (!EmittedWarning && Reg < HighRegNum)
1713 Warning(RegInfo.second,
1714 "register not in ascending order in register list");
1717 HighRegNum = std::max(Reg, HighRegNum);
1720 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
1724 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
1725 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1726 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1727 SMLoc S = Parser.getTok().getLoc();
1728 const AsmToken &Tok = Parser.getTok();
1729 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1730 StringRef OptStr = Tok.getString();
1732 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
1733 .Case("sy", ARM_MB::SY)
1734 .Case("st", ARM_MB::ST)
1735 .Case("sh", ARM_MB::ISH)
1736 .Case("ish", ARM_MB::ISH)
1737 .Case("shst", ARM_MB::ISHST)
1738 .Case("ishst", ARM_MB::ISHST)
1739 .Case("nsh", ARM_MB::NSH)
1740 .Case("un", ARM_MB::NSH)
1741 .Case("nshst", ARM_MB::NSHST)
1742 .Case("unst", ARM_MB::NSHST)
1743 .Case("osh", ARM_MB::OSH)
1744 .Case("oshst", ARM_MB::OSHST)
1748 return MatchOperand_NoMatch;
1750 Parser.Lex(); // Eat identifier token.
1751 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
1752 return MatchOperand_Success;
1755 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
1756 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1757 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1758 SMLoc S = Parser.getTok().getLoc();
1759 const AsmToken &Tok = Parser.getTok();
1760 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1761 StringRef IFlagsStr = Tok.getString();
1763 unsigned IFlags = 0;
1764 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
1765 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
1766 .Case("a", ARM_PROC::A)
1767 .Case("i", ARM_PROC::I)
1768 .Case("f", ARM_PROC::F)
1771 // If some specific iflag is already set, it means that some letter is
1772 // present more than once, this is not acceptable.
1773 if (Flag == ~0U || (IFlags & Flag))
1774 return MatchOperand_NoMatch;
1779 Parser.Lex(); // Eat identifier token.
1780 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
1781 return MatchOperand_Success;
1784 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
1785 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1786 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1787 SMLoc S = Parser.getTok().getLoc();
1788 const AsmToken &Tok = Parser.getTok();
1789 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1790 StringRef Mask = Tok.getString();
1792 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
1793 size_t Start = 0, Next = Mask.find('_');
1794 StringRef Flags = "";
1795 std::string SpecReg = LowercaseString(Mask.slice(Start, Next));
1796 if (Next != StringRef::npos)
1797 Flags = Mask.slice(Next+1, Mask.size());
1799 // FlagsVal contains the complete mask:
1801 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1802 unsigned FlagsVal = 0;
1804 if (SpecReg == "apsr") {
1805 FlagsVal = StringSwitch<unsigned>(Flags)
1806 .Case("nzcvq", 0x8) // same as CPSR_f
1807 .Case("g", 0x4) // same as CPSR_s
1808 .Case("nzcvqg", 0xc) // same as CPSR_fs
1811 if (FlagsVal == ~0U) {
1813 return MatchOperand_NoMatch;
1815 FlagsVal = 0; // No flag
1817 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
1818 if (Flags == "all") // cpsr_all is an alias for cpsr_fc
1820 for (int i = 0, e = Flags.size(); i != e; ++i) {
1821 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
1828 // If some specific flag is already set, it means that some letter is
1829 // present more than once, this is not acceptable.
1830 if (FlagsVal == ~0U || (FlagsVal & Flag))
1831 return MatchOperand_NoMatch;
1834 } else // No match for special register.
1835 return MatchOperand_NoMatch;
1837 // Special register without flags are equivalent to "fc" flags.
1841 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1842 if (SpecReg == "spsr")
1845 Parser.Lex(); // Eat identifier token.
1846 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
1847 return MatchOperand_Success;
1850 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1851 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
1852 int Low, int High) {
1853 const AsmToken &Tok = Parser.getTok();
1854 if (Tok.isNot(AsmToken::Identifier)) {
1855 Error(Parser.getTok().getLoc(), Op + " operand expected.");
1856 return MatchOperand_ParseFail;
1858 StringRef ShiftName = Tok.getString();
1859 std::string LowerOp = LowercaseString(Op);
1860 std::string UpperOp = UppercaseString(Op);
1861 if (ShiftName != LowerOp && ShiftName != UpperOp) {
1862 Error(Parser.getTok().getLoc(), Op + " operand expected.");
1863 return MatchOperand_ParseFail;
1865 Parser.Lex(); // Eat shift type token.
1867 // There must be a '#' and a shift amount.
1868 if (Parser.getTok().isNot(AsmToken::Hash)) {
1869 Error(Parser.getTok().getLoc(), "'#' expected");
1870 return MatchOperand_ParseFail;
1872 Parser.Lex(); // Eat hash token.
1874 const MCExpr *ShiftAmount;
1875 SMLoc Loc = Parser.getTok().getLoc();
1876 if (getParser().ParseExpression(ShiftAmount)) {
1877 Error(Loc, "illegal expression");
1878 return MatchOperand_ParseFail;
1880 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1882 Error(Loc, "constant expression expected");
1883 return MatchOperand_ParseFail;
1885 int Val = CE->getValue();
1886 if (Val < Low || Val > High) {
1887 Error(Loc, "immediate value out of range");
1888 return MatchOperand_ParseFail;
1891 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
1893 return MatchOperand_Success;
1896 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1897 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1898 const AsmToken &Tok = Parser.getTok();
1899 SMLoc S = Tok.getLoc();
1900 if (Tok.isNot(AsmToken::Identifier)) {
1901 Error(Tok.getLoc(), "'be' or 'le' operand expected");
1902 return MatchOperand_ParseFail;
1904 int Val = StringSwitch<int>(Tok.getString())
1908 Parser.Lex(); // Eat the token.
1911 Error(Tok.getLoc(), "'be' or 'le' operand expected");
1912 return MatchOperand_ParseFail;
1914 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
1916 S, Parser.getTok().getLoc()));
1917 return MatchOperand_Success;
1920 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
1921 /// instructions. Legal values are:
1922 /// lsl #n 'n' in [0,31]
1923 /// asr #n 'n' in [1,32]
1924 /// n == 32 encoded as n == 0.
1925 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1926 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1927 const AsmToken &Tok = Parser.getTok();
1928 SMLoc S = Tok.getLoc();
1929 if (Tok.isNot(AsmToken::Identifier)) {
1930 Error(S, "shift operator 'asr' or 'lsl' expected");
1931 return MatchOperand_ParseFail;
1933 StringRef ShiftName = Tok.getString();
1935 if (ShiftName == "lsl" || ShiftName == "LSL")
1937 else if (ShiftName == "asr" || ShiftName == "ASR")
1940 Error(S, "shift operator 'asr' or 'lsl' expected");
1941 return MatchOperand_ParseFail;
1943 Parser.Lex(); // Eat the operator.
1945 // A '#' and a shift amount.
1946 if (Parser.getTok().isNot(AsmToken::Hash)) {
1947 Error(Parser.getTok().getLoc(), "'#' expected");
1948 return MatchOperand_ParseFail;
1950 Parser.Lex(); // Eat hash token.
1952 const MCExpr *ShiftAmount;
1953 SMLoc E = Parser.getTok().getLoc();
1954 if (getParser().ParseExpression(ShiftAmount)) {
1955 Error(E, "malformed shift expression");
1956 return MatchOperand_ParseFail;
1958 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1960 Error(E, "shift amount must be an immediate");
1961 return MatchOperand_ParseFail;
1964 int64_t Val = CE->getValue();
1966 // Shift amount must be in [1,32]
1967 if (Val < 1 || Val > 32) {
1968 Error(E, "'asr' shift amount must be in range [1,32]");
1969 return MatchOperand_ParseFail;
1971 // asr #32 encoded as asr #0.
1972 if (Val == 32) Val = 0;
1974 // Shift amount must be in [1,32]
1975 if (Val < 0 || Val > 31) {
1976 Error(E, "'lsr' shift amount must be in range [0,31]");
1977 return MatchOperand_ParseFail;
1981 E = Parser.getTok().getLoc();
1982 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
1984 return MatchOperand_Success;
1987 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
1988 /// of instructions. Legal values are:
1989 /// ror #n 'n' in {0, 8, 16, 24}
1990 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1991 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1992 const AsmToken &Tok = Parser.getTok();
1993 SMLoc S = Tok.getLoc();
1994 if (Tok.isNot(AsmToken::Identifier)) {
1995 Error(S, "rotate operator 'ror' expected");
1996 return MatchOperand_ParseFail;
1998 StringRef ShiftName = Tok.getString();
1999 if (ShiftName != "ror" && ShiftName != "ROR") {
2000 Error(S, "rotate operator 'ror' expected");
2001 return MatchOperand_ParseFail;
2003 Parser.Lex(); // Eat the operator.
2005 // A '#' and a rotate amount.
2006 if (Parser.getTok().isNot(AsmToken::Hash)) {
2007 Error(Parser.getTok().getLoc(), "'#' expected");
2008 return MatchOperand_ParseFail;
2010 Parser.Lex(); // Eat hash token.
2012 const MCExpr *ShiftAmount;
2013 SMLoc E = Parser.getTok().getLoc();
2014 if (getParser().ParseExpression(ShiftAmount)) {
2015 Error(E, "malformed rotate expression");
2016 return MatchOperand_ParseFail;
2018 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2020 Error(E, "rotate amount must be an immediate");
2021 return MatchOperand_ParseFail;
2024 int64_t Val = CE->getValue();
2025 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
2026 // normally, zero is represented in asm by omitting the rotate operand
2028 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
2029 Error(E, "'ror' rotate amount must be 8, 16, or 24");
2030 return MatchOperand_ParseFail;
2033 E = Parser.getTok().getLoc();
2034 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
2036 return MatchOperand_Success;
2039 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2040 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2041 SMLoc S = Parser.getTok().getLoc();
2042 // The bitfield descriptor is really two operands, the LSB and the width.
2043 if (Parser.getTok().isNot(AsmToken::Hash)) {
2044 Error(Parser.getTok().getLoc(), "'#' expected");
2045 return MatchOperand_ParseFail;
2047 Parser.Lex(); // Eat hash token.
2049 const MCExpr *LSBExpr;
2050 SMLoc E = Parser.getTok().getLoc();
2051 if (getParser().ParseExpression(LSBExpr)) {
2052 Error(E, "malformed immediate expression");
2053 return MatchOperand_ParseFail;
2055 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
2057 Error(E, "'lsb' operand must be an immediate");
2058 return MatchOperand_ParseFail;
2061 int64_t LSB = CE->getValue();
2062 // The LSB must be in the range [0,31]
2063 if (LSB < 0 || LSB > 31) {
2064 Error(E, "'lsb' operand must be in the range [0,31]");
2065 return MatchOperand_ParseFail;
2067 E = Parser.getTok().getLoc();
2069 // Expect another immediate operand.
2070 if (Parser.getTok().isNot(AsmToken::Comma)) {
2071 Error(Parser.getTok().getLoc(), "too few operands");
2072 return MatchOperand_ParseFail;
2074 Parser.Lex(); // Eat hash token.
2075 if (Parser.getTok().isNot(AsmToken::Hash)) {
2076 Error(Parser.getTok().getLoc(), "'#' expected");
2077 return MatchOperand_ParseFail;
2079 Parser.Lex(); // Eat hash token.
2081 const MCExpr *WidthExpr;
2082 if (getParser().ParseExpression(WidthExpr)) {
2083 Error(E, "malformed immediate expression");
2084 return MatchOperand_ParseFail;
2086 CE = dyn_cast<MCConstantExpr>(WidthExpr);
2088 Error(E, "'width' operand must be an immediate");
2089 return MatchOperand_ParseFail;
2092 int64_t Width = CE->getValue();
2093 // The LSB must be in the range [1,32-lsb]
2094 if (Width < 1 || Width > 32 - LSB) {
2095 Error(E, "'width' operand must be in the range [1,32-lsb]");
2096 return MatchOperand_ParseFail;
2098 E = Parser.getTok().getLoc();
2100 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
2102 return MatchOperand_Success;
2105 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2106 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2107 // Check for a post-index addressing register operand. Specifically:
2108 // postidx_reg := '+' register {, shift}
2109 // | '-' register {, shift}
2110 // | register {, shift}
2112 // This method must return MatchOperand_NoMatch without consuming any tokens
2113 // in the case where there is no match, as other alternatives take other
2115 AsmToken Tok = Parser.getTok();
2116 SMLoc S = Tok.getLoc();
2117 bool haveEaten = false;
2120 if (Tok.is(AsmToken::Plus)) {
2121 Parser.Lex(); // Eat the '+' token.
2123 } else if (Tok.is(AsmToken::Minus)) {
2124 Parser.Lex(); // Eat the '-' token.
2128 if (Parser.getTok().is(AsmToken::Identifier))
2129 Reg = tryParseRegister();
2132 return MatchOperand_NoMatch;
2133 Error(Parser.getTok().getLoc(), "register expected");
2134 return MatchOperand_ParseFail;
2136 SMLoc E = Parser.getTok().getLoc();
2138 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
2139 unsigned ShiftImm = 0;
2140 if (Parser.getTok().is(AsmToken::Comma)) {
2141 Parser.Lex(); // Eat the ','.
2142 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
2143 return MatchOperand_ParseFail;
2146 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
2149 return MatchOperand_Success;
2152 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2153 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2154 // Check for a post-index addressing register operand. Specifically:
2155 // am3offset := '+' register
2162 // This method must return MatchOperand_NoMatch without consuming any tokens
2163 // in the case where there is no match, as other alternatives take other
2165 AsmToken Tok = Parser.getTok();
2166 SMLoc S = Tok.getLoc();
2168 // Do immediates first, as we always parse those if we have a '#'.
2169 if (Parser.getTok().is(AsmToken::Hash)) {
2170 Parser.Lex(); // Eat the '#'.
2171 // Explicitly look for a '-', as we need to encode negative zero
2173 bool isNegative = Parser.getTok().is(AsmToken::Minus);
2174 const MCExpr *Offset;
2175 if (getParser().ParseExpression(Offset))
2176 return MatchOperand_ParseFail;
2177 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2179 Error(S, "constant expression expected");
2180 return MatchOperand_ParseFail;
2182 SMLoc E = Tok.getLoc();
2183 // Negative zero is encoded as the flag value INT32_MIN.
2184 int32_t Val = CE->getValue();
2185 if (isNegative && Val == 0)
2189 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
2191 return MatchOperand_Success;
2195 bool haveEaten = false;
2198 if (Tok.is(AsmToken::Plus)) {
2199 Parser.Lex(); // Eat the '+' token.
2201 } else if (Tok.is(AsmToken::Minus)) {
2202 Parser.Lex(); // Eat the '-' token.
2206 if (Parser.getTok().is(AsmToken::Identifier))
2207 Reg = tryParseRegister();
2210 return MatchOperand_NoMatch;
2211 Error(Parser.getTok().getLoc(), "register expected");
2212 return MatchOperand_ParseFail;
2214 SMLoc E = Parser.getTok().getLoc();
2216 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
2219 return MatchOperand_Success;
2222 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2223 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2224 /// when they refer multiple MIOperands inside a single one.
2226 cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2227 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2228 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2230 // Create a writeback register dummy placeholder.
2231 Inst.addOperand(MCOperand::CreateImm(0));
2233 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2234 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2238 /// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2239 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2240 /// when they refer multiple MIOperands inside a single one.
2242 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2243 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2244 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2246 // Create a writeback register dummy placeholder.
2247 Inst.addOperand(MCOperand::CreateImm(0));
2249 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2250 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2255 /// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2256 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2257 /// when they refer multiple MIOperands inside a single one.
2259 cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2260 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2261 // Create a writeback register dummy placeholder.
2262 Inst.addOperand(MCOperand::CreateImm(0));
2263 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2264 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2265 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2269 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2270 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2271 /// when they refer multiple MIOperands inside a single one.
2273 cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2274 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2275 // Create a writeback register dummy placeholder.
2276 Inst.addOperand(MCOperand::CreateImm(0));
2277 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2278 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2279 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2283 /// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2284 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2285 /// when they refer multiple MIOperands inside a single one.
2287 cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2288 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2289 // Create a writeback register dummy placeholder.
2290 Inst.addOperand(MCOperand::CreateImm(0));
2291 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2292 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2293 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2297 /// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
2298 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2299 /// when they refer multiple MIOperands inside a single one.
2301 cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2302 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2304 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2305 // Create a writeback register dummy placeholder.
2306 Inst.addOperand(MCOperand::CreateImm(0));
2308 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2310 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2312 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2316 /// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
2317 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2318 /// when they refer multiple MIOperands inside a single one.
2320 cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2321 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2323 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2324 // Create a writeback register dummy placeholder.
2325 Inst.addOperand(MCOperand::CreateImm(0));
2327 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2329 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2331 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2335 /// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
2336 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2337 /// when they refer multiple MIOperands inside a single one.
2339 cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2340 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2341 // Create a writeback register dummy placeholder.
2342 Inst.addOperand(MCOperand::CreateImm(0));
2344 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2346 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2348 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2350 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2354 /// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
2355 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2356 /// when they refer multiple MIOperands inside a single one.
2358 cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2359 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2360 // Create a writeback register dummy placeholder.
2361 Inst.addOperand(MCOperand::CreateImm(0));
2363 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2365 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2367 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2369 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2373 /// cvtLdrdPre - Convert parsed operands to MCInst.
2374 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2375 /// when they refer multiple MIOperands inside a single one.
2377 cvtLdrdPre(MCInst &Inst, unsigned Opcode,
2378 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2380 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2381 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2382 // Create a writeback register dummy placeholder.
2383 Inst.addOperand(MCOperand::CreateImm(0));
2385 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2387 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2391 /// cvtStrdPre - Convert parsed operands to MCInst.
2392 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2393 /// when they refer multiple MIOperands inside a single one.
2395 cvtStrdPre(MCInst &Inst, unsigned Opcode,
2396 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2397 // Create a writeback register dummy placeholder.
2398 Inst.addOperand(MCOperand::CreateImm(0));
2400 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2401 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2403 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2405 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2409 /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2410 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2411 /// when they refer multiple MIOperands inside a single one.
2413 cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2414 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2415 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2416 // Create a writeback register dummy placeholder.
2417 Inst.addOperand(MCOperand::CreateImm(0));
2418 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2419 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2423 /// cvtThumbMultiple- Convert parsed operands to MCInst.
2424 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2425 /// when they refer multiple MIOperands inside a single one.
2427 cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
2428 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2429 // The second source operand must be the same register as the destination
2431 if (Operands.size() == 6 &&
2432 (((ARMOperand*)Operands[3])->getReg() !=
2433 ((ARMOperand*)Operands[5])->getReg()) &&
2434 (((ARMOperand*)Operands[3])->getReg() !=
2435 ((ARMOperand*)Operands[4])->getReg())) {
2436 Error(Operands[3]->getStartLoc(),
2437 "destination register must match source register");
2440 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2441 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
2442 ((ARMOperand*)Operands[4])->addRegOperands(Inst, 1);
2443 // If we have a three-operand form, use that, else the second source operand
2444 // is just the destination operand again.
2445 if (Operands.size() == 6)
2446 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
2448 Inst.addOperand(Inst.getOperand(0));
2449 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
2454 /// Parse an ARM memory expression, return false if successful else return true
2455 /// or an error. The first token must be a '[' when called.
2457 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2459 assert(Parser.getTok().is(AsmToken::LBrac) &&
2460 "Token is not a Left Bracket");
2461 S = Parser.getTok().getLoc();
2462 Parser.Lex(); // Eat left bracket token.
2464 const AsmToken &BaseRegTok = Parser.getTok();
2465 int BaseRegNum = tryParseRegister();
2466 if (BaseRegNum == -1)
2467 return Error(BaseRegTok.getLoc(), "register expected");
2469 // The next token must either be a comma or a closing bracket.
2470 const AsmToken &Tok = Parser.getTok();
2471 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
2472 return Error(Tok.getLoc(), "malformed memory operand");
2474 if (Tok.is(AsmToken::RBrac)) {
2476 Parser.Lex(); // Eat right bracket token.
2478 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
2484 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
2485 Parser.Lex(); // Eat the comma.
2487 // If we have a '#' it's an immediate offset, else assume it's a register
2489 if (Parser.getTok().is(AsmToken::Hash)) {
2490 Parser.Lex(); // Eat the '#'.
2491 E = Parser.getTok().getLoc();
2493 // FIXME: Special case #-0 so we can correctly set the U bit.
2495 const MCExpr *Offset;
2496 if (getParser().ParseExpression(Offset))
2499 // The expression has to be a constant. Memory references with relocations
2500 // don't come through here, as they use the <label> forms of the relevant
2502 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2504 return Error (E, "constant expression expected");
2506 // Now we should have the closing ']'
2507 E = Parser.getTok().getLoc();
2508 if (Parser.getTok().isNot(AsmToken::RBrac))
2509 return Error(E, "']' expected");
2510 Parser.Lex(); // Eat right bracket token.
2512 // Don't worry about range checking the value here. That's handled by
2513 // the is*() predicates.
2514 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
2515 ARM_AM::no_shift, 0, false, S,E));
2517 // If there's a pre-indexing writeback marker, '!', just add it as a token
2519 if (Parser.getTok().is(AsmToken::Exclaim)) {
2520 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2521 Parser.Lex(); // Eat the '!'.
2527 // The register offset is optionally preceded by a '+' or '-'
2528 bool isNegative = false;
2529 if (Parser.getTok().is(AsmToken::Minus)) {
2531 Parser.Lex(); // Eat the '-'.
2532 } else if (Parser.getTok().is(AsmToken::Plus)) {
2534 Parser.Lex(); // Eat the '+'.
2537 E = Parser.getTok().getLoc();
2538 int OffsetRegNum = tryParseRegister();
2539 if (OffsetRegNum == -1)
2540 return Error(E, "register expected");
2542 // If there's a shift operator, handle it.
2543 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
2544 unsigned ShiftImm = 0;
2545 if (Parser.getTok().is(AsmToken::Comma)) {
2546 Parser.Lex(); // Eat the ','.
2547 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
2551 // Now we should have the closing ']'
2552 E = Parser.getTok().getLoc();
2553 if (Parser.getTok().isNot(AsmToken::RBrac))
2554 return Error(E, "']' expected");
2555 Parser.Lex(); // Eat right bracket token.
2557 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
2558 ShiftType, ShiftImm, isNegative,
2561 // If there's a pre-indexing writeback marker, '!', just add it as a token
2563 if (Parser.getTok().is(AsmToken::Exclaim)) {
2564 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2565 Parser.Lex(); // Eat the '!'.
2571 /// parseMemRegOffsetShift - one of these two:
2572 /// ( lsl | lsr | asr | ror ) , # shift_amount
2574 /// return true if it parses a shift otherwise it returns false.
2575 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
2577 SMLoc Loc = Parser.getTok().getLoc();
2578 const AsmToken &Tok = Parser.getTok();
2579 if (Tok.isNot(AsmToken::Identifier))
2581 StringRef ShiftName = Tok.getString();
2582 if (ShiftName == "lsl" || ShiftName == "LSL")
2584 else if (ShiftName == "lsr" || ShiftName == "LSR")
2586 else if (ShiftName == "asr" || ShiftName == "ASR")
2588 else if (ShiftName == "ror" || ShiftName == "ROR")
2590 else if (ShiftName == "rrx" || ShiftName == "RRX")
2593 return Error(Loc, "illegal shift operator");
2594 Parser.Lex(); // Eat shift type token.
2596 // rrx stands alone.
2598 if (St != ARM_AM::rrx) {
2599 Loc = Parser.getTok().getLoc();
2600 // A '#' and a shift amount.
2601 const AsmToken &HashTok = Parser.getTok();
2602 if (HashTok.isNot(AsmToken::Hash))
2603 return Error(HashTok.getLoc(), "'#' expected");
2604 Parser.Lex(); // Eat hash token.
2607 if (getParser().ParseExpression(Expr))
2609 // Range check the immediate.
2610 // lsl, ror: 0 <= imm <= 31
2611 // lsr, asr: 0 <= imm <= 32
2612 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2614 return Error(Loc, "shift amount must be an immediate");
2615 int64_t Imm = CE->getValue();
2617 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
2618 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
2619 return Error(Loc, "immediate shift value out of range");
2626 /// Parse a arm instruction operand. For now this parses the operand regardless
2627 /// of the mnemonic.
2628 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2629 StringRef Mnemonic) {
2632 // Check if the current operand has a custom associated parser, if so, try to
2633 // custom parse the operand, or fallback to the general approach.
2634 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
2635 if (ResTy == MatchOperand_Success)
2637 // If there wasn't a custom match, try the generic matcher below. Otherwise,
2638 // there was a match, but an error occurred, in which case, just return that
2639 // the operand parsing failed.
2640 if (ResTy == MatchOperand_ParseFail)
2643 switch (getLexer().getKind()) {
2645 Error(Parser.getTok().getLoc(), "unexpected token in operand");
2647 case AsmToken::Identifier: {
2648 if (!tryParseRegisterWithWriteBack(Operands))
2650 int Res = tryParseShiftRegister(Operands);
2651 if (Res == 0) // success
2653 else if (Res == -1) // irrecoverable error
2656 // Fall though for the Identifier case that is not a register or a
2659 case AsmToken::Integer: // things like 1f and 2b as a branch targets
2660 case AsmToken::Dot: { // . as a branch target
2661 // This was not a register so parse other operands that start with an
2662 // identifier (like labels) as expressions and create them as immediates.
2663 const MCExpr *IdVal;
2664 S = Parser.getTok().getLoc();
2665 if (getParser().ParseExpression(IdVal))
2667 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2668 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
2671 case AsmToken::LBrac:
2672 return parseMemory(Operands);
2673 case AsmToken::LCurly:
2674 return parseRegisterList(Operands);
2675 case AsmToken::Hash:
2676 // #42 -> immediate.
2677 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
2678 S = Parser.getTok().getLoc();
2680 const MCExpr *ImmVal;
2681 if (getParser().ParseExpression(ImmVal))
2683 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2684 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
2686 case AsmToken::Colon: {
2687 // ":lower16:" and ":upper16:" expression prefixes
2688 // FIXME: Check it's an expression prefix,
2689 // e.g. (FOO - :lower16:BAR) isn't legal.
2690 ARMMCExpr::VariantKind RefKind;
2691 if (parsePrefix(RefKind))
2694 const MCExpr *SubExprVal;
2695 if (getParser().ParseExpression(SubExprVal))
2698 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
2700 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2701 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
2707 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
2708 // :lower16: and :upper16:.
2709 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
2710 RefKind = ARMMCExpr::VK_ARM_None;
2712 // :lower16: and :upper16: modifiers
2713 assert(getLexer().is(AsmToken::Colon) && "expected a :");
2714 Parser.Lex(); // Eat ':'
2716 if (getLexer().isNot(AsmToken::Identifier)) {
2717 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
2721 StringRef IDVal = Parser.getTok().getIdentifier();
2722 if (IDVal == "lower16") {
2723 RefKind = ARMMCExpr::VK_ARM_LO16;
2724 } else if (IDVal == "upper16") {
2725 RefKind = ARMMCExpr::VK_ARM_HI16;
2727 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
2732 if (getLexer().isNot(AsmToken::Colon)) {
2733 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
2736 Parser.Lex(); // Eat the last ':'
2741 ARMAsmParser::applyPrefixToExpr(const MCExpr *E,
2742 MCSymbolRefExpr::VariantKind Variant) {
2743 // Recurse over the given expression, rebuilding it to apply the given variant
2744 // to the leftmost symbol.
2745 if (Variant == MCSymbolRefExpr::VK_None)
2748 switch (E->getKind()) {
2749 case MCExpr::Target:
2750 llvm_unreachable("Can't handle target expr yet");
2751 case MCExpr::Constant:
2752 llvm_unreachable("Can't handle lower16/upper16 of constant yet");
2754 case MCExpr::SymbolRef: {
2755 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
2757 if (SRE->getKind() != MCSymbolRefExpr::VK_None)
2760 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext());
2764 llvm_unreachable("Can't handle unary expressions yet");
2766 case MCExpr::Binary: {
2767 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
2768 const MCExpr *LHS = applyPrefixToExpr(BE->getLHS(), Variant);
2769 const MCExpr *RHS = BE->getRHS();
2773 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext());
2777 assert(0 && "Invalid expression kind!");
2781 /// \brief Given a mnemonic, split out possible predication code and carry
2782 /// setting letters to form a canonical mnemonic and flags.
2784 // FIXME: Would be nice to autogen this.
2785 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
2786 unsigned &PredicationCode,
2788 unsigned &ProcessorIMod) {
2789 PredicationCode = ARMCC::AL;
2790 CarrySetting = false;
2793 // Ignore some mnemonics we know aren't predicated forms.
2795 // FIXME: Would be nice to autogen this.
2796 if ((Mnemonic == "movs" && isThumb()) ||
2797 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
2798 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
2799 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
2800 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
2801 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
2802 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
2803 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
2806 // First, split out any predication code. Ignore mnemonics we know aren't
2807 // predicated but do have a carry-set and so weren't caught above.
2808 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
2809 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
2810 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
2811 Mnemonic != "sbcs") {
2812 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
2813 .Case("eq", ARMCC::EQ)
2814 .Case("ne", ARMCC::NE)
2815 .Case("hs", ARMCC::HS)
2816 .Case("cs", ARMCC::HS)
2817 .Case("lo", ARMCC::LO)
2818 .Case("cc", ARMCC::LO)
2819 .Case("mi", ARMCC::MI)
2820 .Case("pl", ARMCC::PL)
2821 .Case("vs", ARMCC::VS)
2822 .Case("vc", ARMCC::VC)
2823 .Case("hi", ARMCC::HI)
2824 .Case("ls", ARMCC::LS)
2825 .Case("ge", ARMCC::GE)
2826 .Case("lt", ARMCC::LT)
2827 .Case("gt", ARMCC::GT)
2828 .Case("le", ARMCC::LE)
2829 .Case("al", ARMCC::AL)
2832 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
2833 PredicationCode = CC;
2837 // Next, determine if we have a carry setting bit. We explicitly ignore all
2838 // the instructions we know end in 's'.
2839 if (Mnemonic.endswith("s") &&
2840 !(Mnemonic == "cps" || Mnemonic == "mls" ||
2841 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
2842 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
2843 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
2844 Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
2845 (Mnemonic == "movs" && isThumb()))) {
2846 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
2847 CarrySetting = true;
2850 // The "cps" instruction can have a interrupt mode operand which is glued into
2851 // the mnemonic. Check if this is the case, split it and parse the imod op
2852 if (Mnemonic.startswith("cps")) {
2853 // Split out any imod code.
2855 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
2856 .Case("ie", ARM_PROC::IE)
2857 .Case("id", ARM_PROC::ID)
2860 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
2861 ProcessorIMod = IMod;
2868 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
2869 /// inclusion of carry set or predication code operands.
2871 // FIXME: It would be nice to autogen this.
2873 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
2874 bool &CanAcceptPredicationCode) {
2875 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
2876 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
2877 Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
2878 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
2879 Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" ||
2880 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
2881 Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
2882 Mnemonic == "eor" || Mnemonic == "smlal" || Mnemonic == "neg" ||
2883 // FIXME: We need a better way. This really confused Thumb2
2884 // parsing for 'mov'.
2885 (Mnemonic == "mov" && !isThumbOne())) {
2886 CanAcceptCarrySet = true;
2888 CanAcceptCarrySet = false;
2891 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
2892 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
2893 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
2894 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
2895 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "clrex" ||
2896 Mnemonic == "setend" ||
2897 (Mnemonic == "nop" && isThumbOne()) ||
2898 ((Mnemonic == "pld" || Mnemonic == "pli") && !isThumb()) ||
2899 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs"))
2901 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumb())) {
2902 CanAcceptPredicationCode = false;
2904 CanAcceptPredicationCode = true;
2908 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
2909 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
2910 CanAcceptPredicationCode = false;
2913 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
2914 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2916 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
2917 // another does not. Specifically, the MOVW instruction does not. So we
2918 // special case it here and remove the defaulted (non-setting) cc_out
2919 // operand if that's the instruction we're trying to match.
2921 // We do this as post-processing of the explicit operands rather than just
2922 // conditionally adding the cc_out in the first place because we need
2923 // to check the type of the parsed immediate operand.
2924 if (Mnemonic == "mov" && Operands.size() > 4 &&
2925 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
2926 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
2927 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
2930 // Register-register 'add' for thumb does not have a cc_out operand
2931 // when there are only two register operands.
2932 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
2933 static_cast<ARMOperand*>(Operands[3])->isReg() &&
2934 static_cast<ARMOperand*>(Operands[4])->isReg() &&
2935 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
2937 // Register-register 'add' for thumb does not have a cc_out operand
2938 // when it's an ADD Rdm, SP, {Rdm|#imm} instruction.
2939 if (isThumb() && Mnemonic == "add" && Operands.size() == 6 &&
2940 static_cast<ARMOperand*>(Operands[3])->isReg() &&
2941 static_cast<ARMOperand*>(Operands[4])->isReg() &&
2942 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
2943 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
2945 // Register-register 'add/sub' for thumb does not have a cc_out operand
2946 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
2947 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
2948 // right, this will result in better diagnostics (which operand is off)
2950 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
2951 (Operands.size() == 5 || Operands.size() == 6) &&
2952 static_cast<ARMOperand*>(Operands[3])->isReg() &&
2953 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
2954 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
2960 /// Parse an arm instruction mnemonic followed by its operands.
2961 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
2962 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2963 // Create the leading tokens for the mnemonic, split by '.' characters.
2964 size_t Start = 0, Next = Name.find('.');
2965 StringRef Mnemonic = Name.slice(Start, Next);
2967 // Split out the predication code and carry setting flag from the mnemonic.
2968 unsigned PredicationCode;
2969 unsigned ProcessorIMod;
2971 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
2974 // In Thumb1, only the branch (B) instruction can be predicated.
2975 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
2976 Parser.EatToEndOfStatement();
2977 return Error(NameLoc, "conditional execution not supported in Thumb1");
2980 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
2982 // FIXME: This is all a pretty gross hack. We should automatically handle
2983 // optional operands like this via tblgen.
2985 // Next, add the CCOut and ConditionCode operands, if needed.
2987 // For mnemonics which can ever incorporate a carry setting bit or predication
2988 // code, our matching model involves us always generating CCOut and
2989 // ConditionCode operands to match the mnemonic "as written" and then we let
2990 // the matcher deal with finding the right instruction or generating an
2991 // appropriate error.
2992 bool CanAcceptCarrySet, CanAcceptPredicationCode;
2993 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
2995 // If we had a carry-set on an instruction that can't do that, issue an
2997 if (!CanAcceptCarrySet && CarrySetting) {
2998 Parser.EatToEndOfStatement();
2999 return Error(NameLoc, "instruction '" + Mnemonic +
3000 "' can not set flags, but 's' suffix specified");
3002 // If we had a predication code on an instruction that can't do that, issue an
3004 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
3005 Parser.EatToEndOfStatement();
3006 return Error(NameLoc, "instruction '" + Mnemonic +
3007 "' is not predicable, but condition code specified");
3010 // Add the carry setting operand, if necessary.
3012 // FIXME: It would be awesome if we could somehow invent a location such that
3013 // match errors on this operand would print a nice diagnostic about how the
3014 // 's' character in the mnemonic resulted in a CCOut operand.
3015 if (CanAcceptCarrySet)
3016 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
3019 // Add the predication code operand, if necessary.
3020 if (CanAcceptPredicationCode) {
3021 Operands.push_back(ARMOperand::CreateCondCode(
3022 ARMCC::CondCodes(PredicationCode), NameLoc));
3025 // Add the processor imod operand, if necessary.
3026 if (ProcessorIMod) {
3027 Operands.push_back(ARMOperand::CreateImm(
3028 MCConstantExpr::Create(ProcessorIMod, getContext()),
3031 // This mnemonic can't ever accept a imod, but the user wrote
3032 // one (or misspelled another mnemonic).
3034 // FIXME: Issue a nice error.
3037 // Add the remaining tokens in the mnemonic.
3038 while (Next != StringRef::npos) {
3040 Next = Name.find('.', Start + 1);
3041 StringRef ExtraToken = Name.slice(Start, Next);
3043 // For now, we're only parsing Thumb1 (for the most part), so
3044 // just ignore ".n" qualifiers. We'll use them to restrict
3045 // matching when we do Thumb2.
3046 if (ExtraToken != ".n")
3047 Operands.push_back(ARMOperand::CreateToken(ExtraToken, NameLoc));
3050 // Read the remaining operands.
3051 if (getLexer().isNot(AsmToken::EndOfStatement)) {
3052 // Read the first operand.
3053 if (parseOperand(Operands, Mnemonic)) {
3054 Parser.EatToEndOfStatement();
3058 while (getLexer().is(AsmToken::Comma)) {
3059 Parser.Lex(); // Eat the comma.
3061 // Parse and remember the operand.
3062 if (parseOperand(Operands, Mnemonic)) {
3063 Parser.EatToEndOfStatement();
3069 if (getLexer().isNot(AsmToken::EndOfStatement)) {
3070 Parser.EatToEndOfStatement();
3071 return TokError("unexpected token in argument list");
3074 Parser.Lex(); // Consume the EndOfStatement
3076 // Some instructions, mostly Thumb, have forms for the same mnemonic that
3077 // do and don't have a cc_out optional-def operand. With some spot-checks
3078 // of the operand list, we can figure out which variant we're trying to
3079 // parse and adjust accordingly before actually matching. Reason number
3080 // #317 the table driven matcher doesn't fit well with the ARM instruction
3082 if (shouldOmitCCOutOperand(Mnemonic, Operands)) {
3083 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3084 Operands.erase(Operands.begin() + 1);
3088 // ARM mode 'blx' need special handling, as the register operand version
3089 // is predicable, but the label operand version is not. So, we can't rely
3090 // on the Mnemonic based checking to correctly figure out when to put
3091 // a CondCode operand in the list. If we're trying to match the label
3092 // version, remove the CondCode operand here.
3093 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
3094 static_cast<ARMOperand*>(Operands[2])->isImm()) {
3095 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3096 Operands.erase(Operands.begin() + 1);
3100 // The vector-compare-to-zero instructions have a literal token "#0" at
3101 // the end that comes to here as an immediate operand. Convert it to a
3102 // token to play nicely with the matcher.
3103 if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
3104 Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
3105 static_cast<ARMOperand*>(Operands[5])->isImm()) {
3106 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
3107 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
3108 if (CE && CE->getValue() == 0) {
3109 Operands.erase(Operands.begin() + 5);
3110 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3114 // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
3115 // end. Convert it to a token here.
3116 if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
3117 static_cast<ARMOperand*>(Operands[5])->isImm()) {
3118 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
3119 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
3120 if (CE && CE->getValue() == 0) {
3121 Operands.erase(Operands.begin() + 5);
3122 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3130 // Validate context-sensitive operand constraints.
3132 // return 'true' if register list contains non-low GPR registers,
3133 // 'false' otherwise. If Reg is in the register list or is HiReg, set
3134 // 'containsReg' to true.
3135 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
3136 unsigned HiReg, bool &containsReg) {
3137 containsReg = false;
3138 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
3139 unsigned OpReg = Inst.getOperand(i).getReg();
3142 // Anything other than a low register isn't legal here.
3143 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
3149 // FIXME: We would really like to be able to tablegen'erate this.
3151 validateInstruction(MCInst &Inst,
3152 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3153 switch (Inst.getOpcode()) {
3156 case ARM::LDRD_POST:
3158 // Rt2 must be Rt + 1.
3159 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3160 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3162 return Error(Operands[3]->getStartLoc(),
3163 "destination operands must be sequential");
3167 // Rt2 must be Rt + 1.
3168 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3169 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3171 return Error(Operands[3]->getStartLoc(),
3172 "source operands must be sequential");
3176 case ARM::STRD_POST:
3178 // Rt2 must be Rt + 1.
3179 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3180 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
3182 return Error(Operands[3]->getStartLoc(),
3183 "source operands must be sequential");
3188 // width must be in range [1, 32-lsb]
3189 unsigned lsb = Inst.getOperand(2).getImm();
3190 unsigned widthm1 = Inst.getOperand(3).getImm();
3191 if (widthm1 >= 32 - lsb)
3192 return Error(Operands[5]->getStartLoc(),
3193 "bitfield width must be in range [1,32-lsb]");
3197 // Thumb LDM instructions are writeback iff the base register is not
3198 // in the register list.
3199 unsigned Rn = Inst.getOperand(0).getReg();
3200 bool hasWritebackToken =
3201 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
3202 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
3203 bool listContainsBase;
3204 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase))
3205 return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
3206 "registers must be in range r0-r7");
3207 // If we should have writeback, then there should be a '!' token.
3208 if (!listContainsBase && !hasWritebackToken)
3209 return Error(Operands[2]->getStartLoc(),
3210 "writeback operator '!' expected");
3211 // Likewise, if we should not have writeback, there must not be a '!'
3212 if (listContainsBase && hasWritebackToken)
3213 return Error(Operands[3]->getStartLoc(),
3214 "writeback operator '!' not allowed when base register "
3215 "in register list");
3220 bool listContainsBase;
3221 if (checkLowRegisterList(Inst, 3, 0, ARM::PC, listContainsBase))
3222 return Error(Operands[2]->getStartLoc(),
3223 "registers must be in range r0-r7 or pc");
3227 bool listContainsBase;
3228 if (checkLowRegisterList(Inst, 3, 0, ARM::LR, listContainsBase))
3229 return Error(Operands[2]->getStartLoc(),
3230 "registers must be in range r0-r7 or lr");
3233 case ARM::tSTMIA_UPD: {
3234 bool listContainsBase;
3235 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase))
3236 return Error(Operands[4]->getStartLoc(),
3237 "registers must be in range r0-r7");
3246 processInstruction(MCInst &Inst,
3247 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3248 switch (Inst.getOpcode()) {
3249 case ARM::LDMIA_UPD:
3250 // If this is a load of a single register via a 'pop', then we should use
3251 // a post-indexed LDR instruction instead, per the ARM ARM.
3252 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
3253 Inst.getNumOperands() == 5) {
3255 TmpInst.setOpcode(ARM::LDR_POST_IMM);
3256 TmpInst.addOperand(Inst.getOperand(4)); // Rt
3257 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3258 TmpInst.addOperand(Inst.getOperand(1)); // Rn
3259 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
3260 TmpInst.addOperand(MCOperand::CreateImm(4));
3261 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3262 TmpInst.addOperand(Inst.getOperand(3));
3266 case ARM::STMDB_UPD:
3267 // If this is a store of a single register via a 'push', then we should use
3268 // a pre-indexed STR instruction instead, per the ARM ARM.
3269 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
3270 Inst.getNumOperands() == 5) {
3272 TmpInst.setOpcode(ARM::STR_PRE_IMM);
3273 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3274 TmpInst.addOperand(Inst.getOperand(4)); // Rt
3275 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
3276 TmpInst.addOperand(MCOperand::CreateImm(-4));
3277 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3278 TmpInst.addOperand(Inst.getOperand(3));
3283 // If the immediate is in the range 0-7, we really wanted tADDi3.
3284 if (Inst.getOperand(3).getImm() < 8)
3285 Inst.setOpcode(ARM::tADDi3);
3288 // If the conditional is AL, we really want tB.
3289 if (Inst.getOperand(1).getImm() == ARMCC::AL)
3290 Inst.setOpcode(ARM::tB);
3295 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around
3296 // the ARMInsts array) instead. Getting that here requires awkward
3297 // API changes, though. Better way?
3299 extern MCInstrDesc ARMInsts[];
3301 static MCInstrDesc &getInstDesc(unsigned Opcode) {
3302 return ARMInsts[Opcode];
3305 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
3306 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
3307 // suffix depending on whether they're in an IT block or not.
3308 unsigned Opc = Inst.getOpcode();
3309 MCInstrDesc &MCID = getInstDesc(Opc);
3310 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
3311 assert(MCID.hasOptionalDef() &&
3312 "optionally flag setting instruction missing optional def operand");
3313 assert(MCID.NumOperands == Inst.getNumOperands() &&
3314 "operand count mismatch!");
3315 // Find the optional-def operand (cc_out).
3318 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
3321 // If we're parsing Thumb1, reject it completely.
3322 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3323 return Match_MnemonicFail;
3324 // If we're parsing Thumb2, which form is legal depends on whether we're
3326 // FIXME: We don't yet do IT blocks, so just always consider it to be
3327 // that we aren't in one until we do.
3328 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3329 return Match_RequiresITBlock;
3331 // Some high-register supporting Thumb1 encodings only allow both registers
3332 // to be from r0-r7 when in Thumb2.
3333 else if (Opc == ARM::tADDhirr && isThumbOne() &&
3334 isARMLowRegister(Inst.getOperand(1).getReg()) &&
3335 isARMLowRegister(Inst.getOperand(2).getReg()))
3336 return Match_RequiresThumb2;
3337 // Others only require ARMv6 or later.
3338 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
3339 isARMLowRegister(Inst.getOperand(0).getReg()) &&
3340 isARMLowRegister(Inst.getOperand(1).getReg()))
3341 return Match_RequiresV6;
3342 return Match_Success;
3346 MatchAndEmitInstruction(SMLoc IDLoc,
3347 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
3351 unsigned MatchResult;
3352 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
3353 switch (MatchResult) {
3356 // Context sensitive operand constraints aren't handled by the matcher,
3357 // so check them here.
3358 if (validateInstruction(Inst, Operands))
3361 // Some instructions need post-processing to, for example, tweak which
3362 // encoding is selected.
3363 processInstruction(Inst, Operands);
3365 Out.EmitInstruction(Inst);
3367 case Match_MissingFeature:
3368 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
3370 case Match_InvalidOperand: {
3371 SMLoc ErrorLoc = IDLoc;
3372 if (ErrorInfo != ~0U) {
3373 if (ErrorInfo >= Operands.size())
3374 return Error(IDLoc, "too few operands for instruction");
3376 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
3377 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
3380 return Error(ErrorLoc, "invalid operand for instruction");
3382 case Match_MnemonicFail:
3383 return Error(IDLoc, "invalid instruction");
3384 case Match_ConversionFail:
3385 // The converter function will have already emited a diagnostic.
3387 case Match_RequiresITBlock:
3388 return Error(IDLoc, "instruction only valid inside IT block");
3389 case Match_RequiresV6:
3390 return Error(IDLoc, "instruction variant requires ARMv6 or later");
3391 case Match_RequiresThumb2:
3392 return Error(IDLoc, "instruction variant requires Thumb2");
3395 llvm_unreachable("Implement any new match types added!");
3399 /// parseDirective parses the arm specific directives
3400 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
3401 StringRef IDVal = DirectiveID.getIdentifier();
3402 if (IDVal == ".word")
3403 return parseDirectiveWord(4, DirectiveID.getLoc());
3404 else if (IDVal == ".thumb")
3405 return parseDirectiveThumb(DirectiveID.getLoc());
3406 else if (IDVal == ".thumb_func")
3407 return parseDirectiveThumbFunc(DirectiveID.getLoc());
3408 else if (IDVal == ".code")
3409 return parseDirectiveCode(DirectiveID.getLoc());
3410 else if (IDVal == ".syntax")
3411 return parseDirectiveSyntax(DirectiveID.getLoc());
3415 /// parseDirectiveWord
3416 /// ::= .word [ expression (, expression)* ]
3417 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
3418 if (getLexer().isNot(AsmToken::EndOfStatement)) {
3420 const MCExpr *Value;
3421 if (getParser().ParseExpression(Value))
3424 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
3426 if (getLexer().is(AsmToken::EndOfStatement))
3429 // FIXME: Improve diagnostic.
3430 if (getLexer().isNot(AsmToken::Comma))
3431 return Error(L, "unexpected token in directive");
3440 /// parseDirectiveThumb
3442 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
3443 if (getLexer().isNot(AsmToken::EndOfStatement))
3444 return Error(L, "unexpected token in directive");
3447 // TODO: set thumb mode
3448 // TODO: tell the MC streamer the mode
3449 // getParser().getStreamer().Emit???();
3453 /// parseDirectiveThumbFunc
3454 /// ::= .thumbfunc symbol_name
3455 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
3456 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
3457 bool isMachO = MAI.hasSubsectionsViaSymbols();
3460 // Darwin asm has function name after .thumb_func direction
3463 const AsmToken &Tok = Parser.getTok();
3464 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
3465 return Error(L, "unexpected token in .thumb_func directive");
3466 Name = Tok.getString();
3467 Parser.Lex(); // Consume the identifier token.
3470 if (getLexer().isNot(AsmToken::EndOfStatement))
3471 return Error(L, "unexpected token in directive");
3474 // FIXME: assuming function name will be the line following .thumb_func
3476 Name = Parser.getTok().getString();
3479 // Mark symbol as a thumb symbol.
3480 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
3481 getParser().getStreamer().EmitThumbFunc(Func);
3485 /// parseDirectiveSyntax
3486 /// ::= .syntax unified | divided
3487 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
3488 const AsmToken &Tok = Parser.getTok();
3489 if (Tok.isNot(AsmToken::Identifier))
3490 return Error(L, "unexpected token in .syntax directive");
3491 StringRef Mode = Tok.getString();
3492 if (Mode == "unified" || Mode == "UNIFIED")
3494 else if (Mode == "divided" || Mode == "DIVIDED")
3495 return Error(L, "'.syntax divided' arm asssembly not supported");
3497 return Error(L, "unrecognized syntax mode in .syntax directive");
3499 if (getLexer().isNot(AsmToken::EndOfStatement))
3500 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3503 // TODO tell the MC streamer the mode
3504 // getParser().getStreamer().Emit???();
3508 /// parseDirectiveCode
3509 /// ::= .code 16 | 32
3510 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
3511 const AsmToken &Tok = Parser.getTok();
3512 if (Tok.isNot(AsmToken::Integer))
3513 return Error(L, "unexpected token in .code directive");
3514 int64_t Val = Parser.getTok().getIntVal();
3520 return Error(L, "invalid operand to .code directive");
3522 if (getLexer().isNot(AsmToken::EndOfStatement))
3523 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3529 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
3534 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
3541 extern "C" void LLVMInitializeARMAsmLexer();
3543 /// Force static initialization.
3544 extern "C" void LLVMInitializeARMAsmParser() {
3545 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
3546 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
3547 LLVMInitializeARMAsmLexer();
3550 #define GET_REGISTER_MATCHER
3551 #define GET_MATCHER_IMPLEMENTATION
3552 #include "ARMGenAsmMatcher.inc"