1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMBaseRegisterInfo.h"
12 #include "ARMSubtarget.h"
13 #include "MCTargetDesc/ARMAddressingModes.h"
14 #include "MCTargetDesc/ARMMCExpr.h"
15 #include "llvm/MC/MCParser/MCAsmLexer.h"
16 #include "llvm/MC/MCParser/MCAsmParser.h"
17 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
18 #include "llvm/MC/MCAsmInfo.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCStreamer.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/TargetAsmParser.h"
25 #include "llvm/Target/TargetRegistry.h"
26 #include "llvm/Support/SourceMgr.h"
27 #include "llvm/Support/raw_ostream.h"
28 #include "llvm/ADT/OwningPtr.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/ADT/StringExtras.h"
31 #include "llvm/ADT/StringSwitch.h"
32 #include "llvm/ADT/Twine.h"
40 class ARMAsmParser : public TargetAsmParser {
44 MCAsmParser &getParser() const { return Parser; }
45 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
47 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
48 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
50 int TryParseRegister();
51 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
52 bool TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
53 int TryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
54 bool ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
55 bool ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &,
56 ARMII::AddrMode AddrMode);
57 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
58 bool ParsePrefix(ARMMCExpr::VariantKind &RefKind);
59 const MCExpr *ApplyPrefixToExpr(const MCExpr *E,
60 MCSymbolRefExpr::VariantKind Variant);
63 bool ParseMemoryOffsetReg(bool &Negative,
64 bool &OffsetRegShifted,
65 enum ARM_AM::ShiftOpc &ShiftType,
66 const MCExpr *&ShiftAmount,
67 const MCExpr *&Offset,
71 bool ParseShift(enum ARM_AM::ShiftOpc &St,
72 const MCExpr *&ShiftAmount, SMLoc &E);
73 bool ParseDirectiveWord(unsigned Size, SMLoc L);
74 bool ParseDirectiveThumb(SMLoc L);
75 bool ParseDirectiveThumbFunc(SMLoc L);
76 bool ParseDirectiveCode(SMLoc L);
77 bool ParseDirectiveSyntax(SMLoc L);
79 bool MatchAndEmitInstruction(SMLoc IDLoc,
80 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
82 StringRef SplitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
83 bool &CarrySetting, unsigned &ProcessorIMod);
84 void GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
85 bool &CanAcceptPredicationCode);
87 bool isThumb() const {
88 // FIXME: Can tablegen auto-generate this?
89 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
91 bool isThumbOne() const {
92 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
95 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
96 setAvailableFeatures(FB);
99 /// @name Auto-generated Match Functions
102 #define GET_ASSEMBLER_HEADER
103 #include "ARMGenAsmMatcher.inc"
107 OperandMatchResultTy parseCoprocNumOperand(
108 SmallVectorImpl<MCParsedAsmOperand*>&);
109 OperandMatchResultTy parseCoprocRegOperand(
110 SmallVectorImpl<MCParsedAsmOperand*>&);
111 OperandMatchResultTy parseMemBarrierOptOperand(
112 SmallVectorImpl<MCParsedAsmOperand*>&);
113 OperandMatchResultTy parseProcIFlagsOperand(
114 SmallVectorImpl<MCParsedAsmOperand*>&);
115 OperandMatchResultTy parseMSRMaskOperand(
116 SmallVectorImpl<MCParsedAsmOperand*>&);
117 OperandMatchResultTy parseMemMode2Operand(
118 SmallVectorImpl<MCParsedAsmOperand*>&);
119 OperandMatchResultTy parseMemMode3Operand(
120 SmallVectorImpl<MCParsedAsmOperand*>&);
121 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
122 StringRef Op, int Low, int High);
123 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
124 return parsePKHImm(O, "lsl", 0, 31);
126 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
127 return parsePKHImm(O, "asr", 1, 32);
129 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
131 // Asm Match Converter Methods
132 bool CvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
133 const SmallVectorImpl<MCParsedAsmOperand*> &);
134 bool CvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
135 const SmallVectorImpl<MCParsedAsmOperand*> &);
136 bool CvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
137 const SmallVectorImpl<MCParsedAsmOperand*> &);
138 bool CvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
139 const SmallVectorImpl<MCParsedAsmOperand*> &);
142 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
143 : TargetAsmParser(), STI(_STI), Parser(_Parser) {
144 MCAsmParserExtension::Initialize(_Parser);
146 // Initialize the set of available features.
147 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
150 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
151 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
152 virtual bool ParseDirective(AsmToken DirectiveID);
154 } // end anonymous namespace
158 /// ARMOperand - Instances of this class represent a parsed ARM machine
160 class ARMOperand : public MCParsedAsmOperand {
181 SMLoc StartLoc, EndLoc;
182 SmallVector<unsigned, 8> Registers;
186 ARMCC::CondCodes Val;
198 ARM_PROC::IFlags Val;
218 /// Combined record for all forms of ARM address expressions.
220 ARMII::AddrMode AddrMode;
223 unsigned RegNum; ///< Offset register num, when OffsetIsReg.
224 const MCExpr *Value; ///< Offset value, when !OffsetIsReg.
226 const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
227 enum ARM_AM::ShiftOpc ShiftType; // used when OffsetRegShifted is true
228 unsigned OffsetRegShifted : 1; // only used when OffsetIsReg is true
229 unsigned Preindexed : 1;
230 unsigned Postindexed : 1;
231 unsigned OffsetIsReg : 1;
232 unsigned Negative : 1; // only used when OffsetIsReg is true
233 unsigned Writeback : 1;
237 ARM_AM::ShiftOpc ShiftTy;
241 ARM_AM::ShiftOpc ShiftTy;
247 ARM_AM::ShiftOpc ShiftTy;
253 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
255 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
257 StartLoc = o.StartLoc;
271 case DPRRegisterList:
272 case SPRRegisterList:
273 Registers = o.Registers;
297 case ShiftedRegister:
298 RegShiftedReg = o.RegShiftedReg;
300 case ShiftedImmediate:
301 RegShiftedImm = o.RegShiftedImm;
306 /// getStartLoc - Get the location of the first token of this operand.
307 SMLoc getStartLoc() const { return StartLoc; }
308 /// getEndLoc - Get the location of the last token of this operand.
309 SMLoc getEndLoc() const { return EndLoc; }
311 ARMCC::CondCodes getCondCode() const {
312 assert(Kind == CondCode && "Invalid access!");
316 unsigned getCoproc() const {
317 assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
321 StringRef getToken() const {
322 assert(Kind == Token && "Invalid access!");
323 return StringRef(Tok.Data, Tok.Length);
326 unsigned getReg() const {
327 assert((Kind == Register || Kind == CCOut) && "Invalid access!");
331 const SmallVectorImpl<unsigned> &getRegList() const {
332 assert((Kind == RegisterList || Kind == DPRRegisterList ||
333 Kind == SPRRegisterList) && "Invalid access!");
337 const MCExpr *getImm() const {
338 assert(Kind == Immediate && "Invalid access!");
342 ARM_MB::MemBOpt getMemBarrierOpt() const {
343 assert(Kind == MemBarrierOpt && "Invalid access!");
347 ARM_PROC::IFlags getProcIFlags() const {
348 assert(Kind == ProcIFlags && "Invalid access!");
352 unsigned getMSRMask() const {
353 assert(Kind == MSRMask && "Invalid access!");
357 /// @name Memory Operand Accessors
359 ARMII::AddrMode getMemAddrMode() const {
362 unsigned getMemBaseRegNum() const {
363 return Mem.BaseRegNum;
365 unsigned getMemOffsetRegNum() const {
366 assert(Mem.OffsetIsReg && "Invalid access!");
367 return Mem.Offset.RegNum;
369 const MCExpr *getMemOffset() const {
370 assert(!Mem.OffsetIsReg && "Invalid access!");
371 return Mem.Offset.Value;
373 unsigned getMemOffsetRegShifted() const {
374 assert(Mem.OffsetIsReg && "Invalid access!");
375 return Mem.OffsetRegShifted;
377 const MCExpr *getMemShiftAmount() const {
378 assert(Mem.OffsetIsReg && Mem.OffsetRegShifted && "Invalid access!");
379 return Mem.ShiftAmount;
381 enum ARM_AM::ShiftOpc getMemShiftType() const {
382 assert(Mem.OffsetIsReg && Mem.OffsetRegShifted && "Invalid access!");
383 return Mem.ShiftType;
385 bool getMemPreindexed() const { return Mem.Preindexed; }
386 bool getMemPostindexed() const { return Mem.Postindexed; }
387 bool getMemOffsetIsReg() const { return Mem.OffsetIsReg; }
388 bool getMemNegative() const { return Mem.Negative; }
389 bool getMemWriteback() const { return Mem.Writeback; }
393 bool isCoprocNum() const { return Kind == CoprocNum; }
394 bool isCoprocReg() const { return Kind == CoprocReg; }
395 bool isCondCode() const { return Kind == CondCode; }
396 bool isCCOut() const { return Kind == CCOut; }
397 bool isImm() const { return Kind == Immediate; }
398 bool isImm0_255() const {
399 if (Kind != Immediate)
401 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
402 if (!CE) return false;
403 int64_t Value = CE->getValue();
404 return Value >= 0 && Value < 256;
406 bool isImm0_7() const {
407 if (Kind != Immediate)
409 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
410 if (!CE) return false;
411 int64_t Value = CE->getValue();
412 return Value >= 0 && Value < 8;
414 bool isImm0_15() const {
415 if (Kind != Immediate)
417 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
418 if (!CE) return false;
419 int64_t Value = CE->getValue();
420 return Value >= 0 && Value < 16;
422 bool isImm0_31() const {
423 if (Kind != Immediate)
425 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
426 if (!CE) return false;
427 int64_t Value = CE->getValue();
428 return Value >= 0 && Value < 32;
430 bool isImm1_32() const {
431 if (Kind != Immediate)
433 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
434 if (!CE) return false;
435 int64_t Value = CE->getValue();
436 return Value > 0 && Value < 33;
438 bool isImm0_65535() const {
439 if (Kind != Immediate)
441 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
442 if (!CE) return false;
443 int64_t Value = CE->getValue();
444 return Value >= 0 && Value < 65536;
446 bool isImm0_65535Expr() const {
447 if (Kind != Immediate)
449 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
450 // If it's not a constant expression, it'll generate a fixup and be
452 if (!CE) return true;
453 int64_t Value = CE->getValue();
454 return Value >= 0 && Value < 65536;
456 bool isPKHLSLImm() const {
457 if (Kind != Immediate)
459 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
460 if (!CE) return false;
461 int64_t Value = CE->getValue();
462 return Value >= 0 && Value < 32;
464 bool isPKHASRImm() const {
465 if (Kind != Immediate)
467 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
468 if (!CE) return false;
469 int64_t Value = CE->getValue();
470 return Value > 0 && Value <= 32;
472 bool isARMSOImm() const {
473 if (Kind != Immediate)
475 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
476 if (!CE) return false;
477 int64_t Value = CE->getValue();
478 return ARM_AM::getSOImmVal(Value) != -1;
480 bool isT2SOImm() const {
481 if (Kind != Immediate)
483 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
484 if (!CE) return false;
485 int64_t Value = CE->getValue();
486 return ARM_AM::getT2SOImmVal(Value) != -1;
488 bool isSetEndImm() const {
489 if (Kind != Immediate)
491 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
492 if (!CE) return false;
493 int64_t Value = CE->getValue();
494 return Value == 1 || Value == 0;
496 bool isReg() const { return Kind == Register; }
497 bool isRegList() const { return Kind == RegisterList; }
498 bool isDPRRegList() const { return Kind == DPRRegisterList; }
499 bool isSPRRegList() const { return Kind == SPRRegisterList; }
500 bool isToken() const { return Kind == Token; }
501 bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
502 bool isMemory() const { return Kind == Memory; }
503 bool isShifter() const { return Kind == Shifter; }
504 bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
505 bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
506 bool isMemMode2() const {
507 if (getMemAddrMode() != ARMII::AddrMode2)
510 if (getMemOffsetIsReg())
513 if (getMemNegative() &&
514 !(getMemPostindexed() || getMemPreindexed()))
517 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
518 if (!CE) return false;
519 int64_t Value = CE->getValue();
521 // The offset must be in the range 0-4095 (imm12).
522 if (Value > 4095 || Value < -4095)
527 bool isMemMode3() const {
528 if (getMemAddrMode() != ARMII::AddrMode3)
531 if (getMemOffsetIsReg()) {
532 if (getMemOffsetRegShifted())
533 return false; // No shift with offset reg allowed
537 if (getMemNegative() &&
538 !(getMemPostindexed() || getMemPreindexed()))
541 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
542 if (!CE) return false;
543 int64_t Value = CE->getValue();
545 // The offset must be in the range 0-255 (imm8).
546 if (Value > 255 || Value < -255)
551 bool isMemMode5() const {
552 if (!isMemory() || getMemOffsetIsReg() || getMemWriteback() ||
556 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
557 if (!CE) return false;
559 // The offset must be a multiple of 4 in the range 0-1020.
560 int64_t Value = CE->getValue();
561 return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020);
563 bool isMemMode7() const {
565 getMemPreindexed() ||
566 getMemPostindexed() ||
567 getMemOffsetIsReg() ||
572 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
573 if (!CE) return false;
580 bool isMemModeRegThumb() const {
581 if (!isMemory() || !getMemOffsetIsReg() || getMemWriteback())
585 bool isMemModeImmThumb() const {
586 if (!isMemory() || getMemOffsetIsReg() || getMemWriteback())
589 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
590 if (!CE) return false;
592 // The offset must be a multiple of 4 in the range 0-124.
593 uint64_t Value = CE->getValue();
594 return ((Value & 0x3) == 0 && Value <= 124);
596 bool isMSRMask() const { return Kind == MSRMask; }
597 bool isProcIFlags() const { return Kind == ProcIFlags; }
599 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
600 // Add as immediates when possible. Null MCExpr = 0.
602 Inst.addOperand(MCOperand::CreateImm(0));
603 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
604 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
606 Inst.addOperand(MCOperand::CreateExpr(Expr));
609 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
610 assert(N == 2 && "Invalid number of operands!");
611 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
612 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
613 Inst.addOperand(MCOperand::CreateReg(RegNum));
616 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
617 assert(N == 1 && "Invalid number of operands!");
618 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
621 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
622 assert(N == 1 && "Invalid number of operands!");
623 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
626 void addCCOutOperands(MCInst &Inst, unsigned N) const {
627 assert(N == 1 && "Invalid number of operands!");
628 Inst.addOperand(MCOperand::CreateReg(getReg()));
631 void addRegOperands(MCInst &Inst, unsigned N) const {
632 assert(N == 1 && "Invalid number of operands!");
633 Inst.addOperand(MCOperand::CreateReg(getReg()));
636 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
637 assert(N == 3 && "Invalid number of operands!");
638 assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
639 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
640 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
641 Inst.addOperand(MCOperand::CreateImm(
642 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
645 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
646 assert(N == 2 && "Invalid number of operands!");
647 assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
648 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
649 Inst.addOperand(MCOperand::CreateImm(
650 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
654 void addShifterOperands(MCInst &Inst, unsigned N) const {
655 assert(N == 1 && "Invalid number of operands!");
656 Inst.addOperand(MCOperand::CreateImm(
657 ARM_AM::getSORegOpc(Shift.ShiftTy, 0)));
660 void addRegListOperands(MCInst &Inst, unsigned N) const {
661 assert(N == 1 && "Invalid number of operands!");
662 const SmallVectorImpl<unsigned> &RegList = getRegList();
663 for (SmallVectorImpl<unsigned>::const_iterator
664 I = RegList.begin(), E = RegList.end(); I != E; ++I)
665 Inst.addOperand(MCOperand::CreateReg(*I));
668 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
669 addRegListOperands(Inst, N);
672 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
673 addRegListOperands(Inst, N);
676 void addImmOperands(MCInst &Inst, unsigned N) const {
677 assert(N == 1 && "Invalid number of operands!");
678 addExpr(Inst, getImm());
681 void addImm0_255Operands(MCInst &Inst, unsigned N) const {
682 assert(N == 1 && "Invalid number of operands!");
683 addExpr(Inst, getImm());
686 void addImm0_7Operands(MCInst &Inst, unsigned N) const {
687 assert(N == 1 && "Invalid number of operands!");
688 addExpr(Inst, getImm());
691 void addImm0_15Operands(MCInst &Inst, unsigned N) const {
692 assert(N == 1 && "Invalid number of operands!");
693 addExpr(Inst, getImm());
696 void addImm0_31Operands(MCInst &Inst, unsigned N) const {
697 assert(N == 1 && "Invalid number of operands!");
698 addExpr(Inst, getImm());
701 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
702 assert(N == 1 && "Invalid number of operands!");
703 // The constant encodes as the immediate-1, and we store in the instruction
704 // the bits as encoded, so subtract off one here.
705 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
706 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
709 void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
710 assert(N == 1 && "Invalid number of operands!");
711 addExpr(Inst, getImm());
714 void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
715 assert(N == 1 && "Invalid number of operands!");
716 addExpr(Inst, getImm());
719 void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
720 assert(N == 1 && "Invalid number of operands!");
721 addExpr(Inst, getImm());
724 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
725 assert(N == 1 && "Invalid number of operands!");
726 // An ASR value of 32 encodes as 0, so that's how we want to add it to
727 // the instruction as well.
728 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
729 int Val = CE->getValue();
730 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
733 void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
734 assert(N == 1 && "Invalid number of operands!");
735 addExpr(Inst, getImm());
738 void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
739 assert(N == 1 && "Invalid number of operands!");
740 addExpr(Inst, getImm());
743 void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
744 assert(N == 1 && "Invalid number of operands!");
745 addExpr(Inst, getImm());
748 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
749 assert(N == 1 && "Invalid number of operands!");
750 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
753 void addMemMode7Operands(MCInst &Inst, unsigned N) const {
754 assert(N == 1 && isMemMode7() && "Invalid number of operands!");
755 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
757 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
759 assert((CE || CE->getValue() == 0) &&
760 "No offset operand support in mode 7");
763 void addMemMode2Operands(MCInst &Inst, unsigned N) const {
764 assert(isMemMode2() && "Invalid mode or number of operands!");
765 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
766 unsigned IdxMode = (getMemPreindexed() | getMemPostindexed() << 1);
768 if (getMemOffsetIsReg()) {
769 Inst.addOperand(MCOperand::CreateReg(getMemOffsetRegNum()));
771 ARM_AM::AddrOpc AMOpc = getMemNegative() ? ARM_AM::sub : ARM_AM::add;
772 ARM_AM::ShiftOpc ShOpc = ARM_AM::no_shift;
773 int64_t ShiftAmount = 0;
775 if (getMemOffsetRegShifted()) {
776 ShOpc = getMemShiftType();
777 const MCConstantExpr *CE =
778 dyn_cast<MCConstantExpr>(getMemShiftAmount());
779 ShiftAmount = CE->getValue();
782 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(AMOpc, ShiftAmount,
787 // Create a operand placeholder to always yield the same number of operands.
788 Inst.addOperand(MCOperand::CreateReg(0));
790 // FIXME: #-0 is encoded differently than #0. Does the parser preserve
792 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
793 assert(CE && "Non-constant mode 2 offset operand!");
794 int64_t Offset = CE->getValue();
797 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(ARM_AM::add,
798 Offset, ARM_AM::no_shift, IdxMode)));
800 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(ARM_AM::sub,
801 -Offset, ARM_AM::no_shift, IdxMode)));
804 void addMemMode3Operands(MCInst &Inst, unsigned N) const {
805 assert(isMemMode3() && "Invalid mode or number of operands!");
806 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
807 unsigned IdxMode = (getMemPreindexed() | getMemPostindexed() << 1);
809 if (getMemOffsetIsReg()) {
810 Inst.addOperand(MCOperand::CreateReg(getMemOffsetRegNum()));
812 ARM_AM::AddrOpc AMOpc = getMemNegative() ? ARM_AM::sub : ARM_AM::add;
813 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM3Opc(AMOpc, 0,
818 // Create a operand placeholder to always yield the same number of operands.
819 Inst.addOperand(MCOperand::CreateReg(0));
821 // FIXME: #-0 is encoded differently than #0. Does the parser preserve
823 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
824 assert(CE && "Non-constant mode 3 offset operand!");
825 int64_t Offset = CE->getValue();
828 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM3Opc(ARM_AM::add,
831 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM3Opc(ARM_AM::sub,
835 void addMemMode5Operands(MCInst &Inst, unsigned N) const {
836 assert(N == 2 && isMemMode5() && "Invalid number of operands!");
838 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
839 assert(!getMemOffsetIsReg() && "Invalid mode 5 operand");
841 // FIXME: #-0 is encoded differently than #0. Does the parser preserve
843 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
844 assert(CE && "Non-constant mode 5 offset operand!");
846 // The MCInst offset operand doesn't include the low two bits (like
847 // the instruction encoding).
848 int64_t Offset = CE->getValue() / 4;
850 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add,
853 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub,
857 void addMemModeRegThumbOperands(MCInst &Inst, unsigned N) const {
858 assert(N == 2 && isMemModeRegThumb() && "Invalid number of operands!");
859 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
860 Inst.addOperand(MCOperand::CreateReg(getMemOffsetRegNum()));
863 void addMemModeImmThumbOperands(MCInst &Inst, unsigned N) const {
864 assert(N == 2 && isMemModeImmThumb() && "Invalid number of operands!");
865 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
866 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
867 assert(CE && "Non-constant mode offset operand!");
868 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
871 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
872 assert(N == 1 && "Invalid number of operands!");
873 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
876 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
877 assert(N == 1 && "Invalid number of operands!");
878 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
881 virtual void print(raw_ostream &OS) const;
883 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
884 ARMOperand *Op = new ARMOperand(CondCode);
891 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
892 ARMOperand *Op = new ARMOperand(CoprocNum);
893 Op->Cop.Val = CopVal;
899 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
900 ARMOperand *Op = new ARMOperand(CoprocReg);
901 Op->Cop.Val = CopVal;
907 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
908 ARMOperand *Op = new ARMOperand(CCOut);
909 Op->Reg.RegNum = RegNum;
915 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
916 ARMOperand *Op = new ARMOperand(Token);
917 Op->Tok.Data = Str.data();
918 Op->Tok.Length = Str.size();
924 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
925 ARMOperand *Op = new ARMOperand(Register);
926 Op->Reg.RegNum = RegNum;
932 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
937 ARMOperand *Op = new ARMOperand(ShiftedRegister);
938 Op->RegShiftedReg.ShiftTy = ShTy;
939 Op->RegShiftedReg.SrcReg = SrcReg;
940 Op->RegShiftedReg.ShiftReg = ShiftReg;
941 Op->RegShiftedReg.ShiftImm = ShiftImm;
947 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
951 ARMOperand *Op = new ARMOperand(ShiftedImmediate);
952 Op->RegShiftedImm.ShiftTy = ShTy;
953 Op->RegShiftedImm.SrcReg = SrcReg;
954 Op->RegShiftedImm.ShiftImm = ShiftImm;
960 static ARMOperand *CreateShifter(ARM_AM::ShiftOpc ShTy,
962 ARMOperand *Op = new ARMOperand(Shifter);
963 Op->Shift.ShiftTy = ShTy;
970 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
971 SMLoc StartLoc, SMLoc EndLoc) {
972 KindTy Kind = RegisterList;
974 if (ARM::DPRRegClass.contains(Regs.front().first))
975 Kind = DPRRegisterList;
976 else if (ARM::SPRRegClass.contains(Regs.front().first))
977 Kind = SPRRegisterList;
979 ARMOperand *Op = new ARMOperand(Kind);
980 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
981 I = Regs.begin(), E = Regs.end(); I != E; ++I)
982 Op->Registers.push_back(I->first);
983 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
984 Op->StartLoc = StartLoc;
989 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
990 ARMOperand *Op = new ARMOperand(Immediate);
997 static ARMOperand *CreateMem(ARMII::AddrMode AddrMode, unsigned BaseRegNum,
998 bool OffsetIsReg, const MCExpr *Offset,
999 int OffsetRegNum, bool OffsetRegShifted,
1000 enum ARM_AM::ShiftOpc ShiftType,
1001 const MCExpr *ShiftAmount, bool Preindexed,
1002 bool Postindexed, bool Negative, bool Writeback,
1004 assert((OffsetRegNum == -1 || OffsetIsReg) &&
1005 "OffsetRegNum must imply OffsetIsReg!");
1006 assert((!OffsetRegShifted || OffsetIsReg) &&
1007 "OffsetRegShifted must imply OffsetIsReg!");
1008 assert((Offset || OffsetIsReg) &&
1009 "Offset must exists unless register offset is used!");
1010 assert((!ShiftAmount || (OffsetIsReg && OffsetRegShifted)) &&
1011 "Cannot have shift amount without shifted register offset!");
1012 assert((!Offset || !OffsetIsReg) &&
1013 "Cannot have expression offset and register offset!");
1015 ARMOperand *Op = new ARMOperand(Memory);
1016 Op->Mem.AddrMode = AddrMode;
1017 Op->Mem.BaseRegNum = BaseRegNum;
1018 Op->Mem.OffsetIsReg = OffsetIsReg;
1020 Op->Mem.Offset.RegNum = OffsetRegNum;
1022 Op->Mem.Offset.Value = Offset;
1023 Op->Mem.OffsetRegShifted = OffsetRegShifted;
1024 Op->Mem.ShiftType = ShiftType;
1025 Op->Mem.ShiftAmount = ShiftAmount;
1026 Op->Mem.Preindexed = Preindexed;
1027 Op->Mem.Postindexed = Postindexed;
1028 Op->Mem.Negative = Negative;
1029 Op->Mem.Writeback = Writeback;
1036 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1037 ARMOperand *Op = new ARMOperand(MemBarrierOpt);
1038 Op->MBOpt.Val = Opt;
1044 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1045 ARMOperand *Op = new ARMOperand(ProcIFlags);
1046 Op->IFlags.Val = IFlags;
1052 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1053 ARMOperand *Op = new ARMOperand(MSRMask);
1054 Op->MMask.Val = MMask;
1061 } // end anonymous namespace.
1063 void ARMOperand::print(raw_ostream &OS) const {
1066 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1069 OS << "<ccout " << getReg() << ">";
1072 OS << "<coprocessor number: " << getCoproc() << ">";
1075 OS << "<coprocessor register: " << getCoproc() << ">";
1078 OS << "<mask: " << getMSRMask() << ">";
1081 getImm()->print(OS);
1084 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1088 << "am:" << ARMII::AddrModeToString(getMemAddrMode())
1089 << " base:" << getMemBaseRegNum();
1090 if (getMemOffsetIsReg()) {
1091 OS << " offset:<register " << getMemOffsetRegNum();
1092 if (getMemOffsetRegShifted()) {
1093 OS << " offset-shift-type:" << getMemShiftType();
1094 OS << " offset-shift-amount:" << *getMemShiftAmount();
1097 OS << " offset:" << *getMemOffset();
1099 if (getMemOffsetIsReg())
1100 OS << " (offset-is-reg)";
1101 if (getMemPreindexed())
1102 OS << " (pre-indexed)";
1103 if (getMemPostindexed())
1104 OS << " (post-indexed)";
1105 if (getMemNegative())
1106 OS << " (negative)";
1107 if (getMemWriteback())
1108 OS << " (writeback)";
1112 OS << "<ARM_PROC::";
1113 unsigned IFlags = getProcIFlags();
1114 for (int i=2; i >= 0; --i)
1115 if (IFlags & (1 << i))
1116 OS << ARM_PROC::IFlagsToString(1 << i);
1121 OS << "<register " << getReg() << ">";
1124 OS << "<shifter " << ARM_AM::getShiftOpcStr(Shift.ShiftTy) << ">";
1126 case ShiftedRegister:
1127 OS << "<so_reg_reg "
1128 << RegShiftedReg.SrcReg
1129 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1130 << ", " << RegShiftedReg.ShiftReg << ", "
1131 << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1134 case ShiftedImmediate:
1135 OS << "<so_reg_imm "
1136 << RegShiftedImm.SrcReg
1137 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1138 << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
1142 case DPRRegisterList:
1143 case SPRRegisterList: {
1144 OS << "<register_list ";
1146 const SmallVectorImpl<unsigned> &RegList = getRegList();
1147 for (SmallVectorImpl<unsigned>::const_iterator
1148 I = RegList.begin(), E = RegList.end(); I != E; ) {
1150 if (++I < E) OS << ", ";
1157 OS << "'" << getToken() << "'";
1162 /// @name Auto-generated Match Functions
1165 static unsigned MatchRegisterName(StringRef Name);
1169 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
1170 SMLoc &StartLoc, SMLoc &EndLoc) {
1171 RegNo = TryParseRegister();
1173 return (RegNo == (unsigned)-1);
1176 /// Try to parse a register name. The token must be an Identifier when called,
1177 /// and if it is a register name the token is eaten and the register number is
1178 /// returned. Otherwise return -1.
1180 int ARMAsmParser::TryParseRegister() {
1181 const AsmToken &Tok = Parser.getTok();
1182 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1184 // FIXME: Validate register for the current architecture; we have to do
1185 // validation later, so maybe there is no need for this here.
1186 std::string upperCase = Tok.getString().str();
1187 std::string lowerCase = LowercaseString(upperCase);
1188 unsigned RegNum = MatchRegisterName(lowerCase);
1190 RegNum = StringSwitch<unsigned>(lowerCase)
1191 .Case("r13", ARM::SP)
1192 .Case("r14", ARM::LR)
1193 .Case("r15", ARM::PC)
1194 .Case("ip", ARM::R12)
1197 if (!RegNum) return -1;
1199 Parser.Lex(); // Eat identifier token.
1203 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
1204 // If a recoverable error occurs, return 1. If an irrecoverable error
1205 // occurs, return -1. An irrecoverable error is one where tokens have been
1206 // consumed in the process of trying to parse the shifter (i.e., when it is
1207 // indeed a shifter operand, but malformed).
1208 int ARMAsmParser::TryParseShiftRegister(
1209 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1210 SMLoc S = Parser.getTok().getLoc();
1211 const AsmToken &Tok = Parser.getTok();
1212 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1214 std::string upperCase = Tok.getString().str();
1215 std::string lowerCase = LowercaseString(upperCase);
1216 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
1217 .Case("lsl", ARM_AM::lsl)
1218 .Case("lsr", ARM_AM::lsr)
1219 .Case("asr", ARM_AM::asr)
1220 .Case("ror", ARM_AM::ror)
1221 .Case("rrx", ARM_AM::rrx)
1222 .Default(ARM_AM::no_shift);
1224 if (ShiftTy == ARM_AM::no_shift)
1227 Parser.Lex(); // Eat the operator.
1229 // The source register for the shift has already been added to the
1230 // operand list, so we need to pop it off and combine it into the shifted
1231 // register operand instead.
1232 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
1233 if (!PrevOp->isReg())
1234 return Error(PrevOp->getStartLoc(), "shift must be of a register");
1235 int SrcReg = PrevOp->getReg();
1238 if (ShiftTy == ARM_AM::rrx) {
1239 // RRX Doesn't have an explicit shift amount. The encoder expects
1240 // the shift register to be the same as the source register. Seems odd,
1244 // Figure out if this is shifted by a constant or a register (for non-RRX).
1245 if (Parser.getTok().is(AsmToken::Hash)) {
1246 Parser.Lex(); // Eat hash.
1247 SMLoc ImmLoc = Parser.getTok().getLoc();
1248 const MCExpr *ShiftExpr = 0;
1249 if (getParser().ParseExpression(ShiftExpr)) {
1250 Error(ImmLoc, "invalid immediate shift value");
1253 // The expression must be evaluatable as an immediate.
1254 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
1256 Error(ImmLoc, "invalid immediate shift value");
1259 // Range check the immediate.
1260 // lsl, ror: 0 <= imm <= 31
1261 // lsr, asr: 0 <= imm <= 32
1262 Imm = CE->getValue();
1264 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
1265 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
1266 Error(ImmLoc, "immediate shift value out of range");
1269 } else if (Parser.getTok().is(AsmToken::Identifier)) {
1270 ShiftReg = TryParseRegister();
1271 SMLoc L = Parser.getTok().getLoc();
1272 if (ShiftReg == -1) {
1273 Error (L, "expected immediate or register in shift operand");
1277 Error (Parser.getTok().getLoc(),
1278 "expected immediate or register in shift operand");
1283 if (ShiftReg && ShiftTy != ARM_AM::rrx)
1284 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
1286 S, Parser.getTok().getLoc()));
1288 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
1289 S, Parser.getTok().getLoc()));
1295 /// Try to parse a register name. The token must be an Identifier when called.
1296 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
1297 /// if there is a "writeback". 'true' if it's not a register.
1299 /// TODO this is likely to change to allow different register types and or to
1300 /// parse for a specific register type.
1302 TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1303 SMLoc S = Parser.getTok().getLoc();
1304 int RegNo = TryParseRegister();
1308 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1310 const AsmToken &ExclaimTok = Parser.getTok();
1311 if (ExclaimTok.is(AsmToken::Exclaim)) {
1312 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
1313 ExclaimTok.getLoc()));
1314 Parser.Lex(); // Eat exclaim token
1320 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
1321 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
1323 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
1324 // Use the same layout as the tablegen'erated register name matcher. Ugly,
1326 switch (Name.size()) {
1329 if (Name[0] != CoprocOp)
1346 if (Name[0] != CoprocOp || Name[1] != '1')
1350 case '0': return 10;
1351 case '1': return 11;
1352 case '2': return 12;
1353 case '3': return 13;
1354 case '4': return 14;
1355 case '5': return 15;
1363 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
1364 /// token must be an Identifier when called, and if it is a coprocessor
1365 /// number, the token is eaten and the operand is added to the operand list.
1366 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1367 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1368 SMLoc S = Parser.getTok().getLoc();
1369 const AsmToken &Tok = Parser.getTok();
1370 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1372 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
1374 return MatchOperand_NoMatch;
1376 Parser.Lex(); // Eat identifier token.
1377 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
1378 return MatchOperand_Success;
1381 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
1382 /// token must be an Identifier when called, and if it is a coprocessor
1383 /// number, the token is eaten and the operand is added to the operand list.
1384 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1385 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1386 SMLoc S = Parser.getTok().getLoc();
1387 const AsmToken &Tok = Parser.getTok();
1388 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1390 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
1392 return MatchOperand_NoMatch;
1394 Parser.Lex(); // Eat identifier token.
1395 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
1396 return MatchOperand_Success;
1399 /// Parse a register list, return it if successful else return null. The first
1400 /// token must be a '{' when called.
1402 ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1403 assert(Parser.getTok().is(AsmToken::LCurly) &&
1404 "Token is not a Left Curly Brace");
1405 SMLoc S = Parser.getTok().getLoc();
1407 // Read the rest of the registers in the list.
1408 unsigned PrevRegNum = 0;
1409 SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
1412 bool IsRange = Parser.getTok().is(AsmToken::Minus);
1413 Parser.Lex(); // Eat non-identifier token.
1415 const AsmToken &RegTok = Parser.getTok();
1416 SMLoc RegLoc = RegTok.getLoc();
1417 if (RegTok.isNot(AsmToken::Identifier)) {
1418 Error(RegLoc, "register expected");
1422 int RegNum = TryParseRegister();
1424 Error(RegLoc, "register expected");
1429 int Reg = PrevRegNum;
1432 Registers.push_back(std::make_pair(Reg, RegLoc));
1433 } while (Reg != RegNum);
1435 Registers.push_back(std::make_pair(RegNum, RegLoc));
1438 PrevRegNum = RegNum;
1439 } while (Parser.getTok().is(AsmToken::Comma) ||
1440 Parser.getTok().is(AsmToken::Minus));
1442 // Process the right curly brace of the list.
1443 const AsmToken &RCurlyTok = Parser.getTok();
1444 if (RCurlyTok.isNot(AsmToken::RCurly)) {
1445 Error(RCurlyTok.getLoc(), "'}' expected");
1449 SMLoc E = RCurlyTok.getLoc();
1450 Parser.Lex(); // Eat right curly brace token.
1452 // Verify the register list.
1453 SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1454 RI = Registers.begin(), RE = Registers.end();
1456 unsigned HighRegNum = getARMRegisterNumbering(RI->first);
1457 bool EmittedWarning = false;
1459 DenseMap<unsigned, bool> RegMap;
1460 RegMap[HighRegNum] = true;
1462 for (++RI; RI != RE; ++RI) {
1463 const std::pair<unsigned, SMLoc> &RegInfo = *RI;
1464 unsigned Reg = getARMRegisterNumbering(RegInfo.first);
1467 Error(RegInfo.second, "register duplicated in register list");
1471 if (!EmittedWarning && Reg < HighRegNum)
1472 Warning(RegInfo.second,
1473 "register not in ascending order in register list");
1476 HighRegNum = std::max(Reg, HighRegNum);
1479 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
1483 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
1484 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1485 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1486 SMLoc S = Parser.getTok().getLoc();
1487 const AsmToken &Tok = Parser.getTok();
1488 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1489 StringRef OptStr = Tok.getString();
1491 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
1492 .Case("sy", ARM_MB::SY)
1493 .Case("st", ARM_MB::ST)
1494 .Case("sh", ARM_MB::ISH)
1495 .Case("ish", ARM_MB::ISH)
1496 .Case("shst", ARM_MB::ISHST)
1497 .Case("ishst", ARM_MB::ISHST)
1498 .Case("nsh", ARM_MB::NSH)
1499 .Case("un", ARM_MB::NSH)
1500 .Case("nshst", ARM_MB::NSHST)
1501 .Case("unst", ARM_MB::NSHST)
1502 .Case("osh", ARM_MB::OSH)
1503 .Case("oshst", ARM_MB::OSHST)
1507 return MatchOperand_NoMatch;
1509 Parser.Lex(); // Eat identifier token.
1510 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
1511 return MatchOperand_Success;
1514 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
1515 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1516 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1517 SMLoc S = Parser.getTok().getLoc();
1518 const AsmToken &Tok = Parser.getTok();
1519 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1520 StringRef IFlagsStr = Tok.getString();
1522 unsigned IFlags = 0;
1523 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
1524 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
1525 .Case("a", ARM_PROC::A)
1526 .Case("i", ARM_PROC::I)
1527 .Case("f", ARM_PROC::F)
1530 // If some specific iflag is already set, it means that some letter is
1531 // present more than once, this is not acceptable.
1532 if (Flag == ~0U || (IFlags & Flag))
1533 return MatchOperand_NoMatch;
1538 Parser.Lex(); // Eat identifier token.
1539 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
1540 return MatchOperand_Success;
1543 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
1544 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1545 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1546 SMLoc S = Parser.getTok().getLoc();
1547 const AsmToken &Tok = Parser.getTok();
1548 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1549 StringRef Mask = Tok.getString();
1551 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
1552 size_t Start = 0, Next = Mask.find('_');
1553 StringRef Flags = "";
1554 std::string SpecReg = LowercaseString(Mask.slice(Start, Next));
1555 if (Next != StringRef::npos)
1556 Flags = Mask.slice(Next+1, Mask.size());
1558 // FlagsVal contains the complete mask:
1560 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1561 unsigned FlagsVal = 0;
1563 if (SpecReg == "apsr") {
1564 FlagsVal = StringSwitch<unsigned>(Flags)
1565 .Case("nzcvq", 0x8) // same as CPSR_f
1566 .Case("g", 0x4) // same as CPSR_s
1567 .Case("nzcvqg", 0xc) // same as CPSR_fs
1570 if (FlagsVal == ~0U) {
1572 return MatchOperand_NoMatch;
1574 FlagsVal = 0; // No flag
1576 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
1577 if (Flags == "all") // cpsr_all is an alias for cpsr_fc
1579 for (int i = 0, e = Flags.size(); i != e; ++i) {
1580 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
1587 // If some specific flag is already set, it means that some letter is
1588 // present more than once, this is not acceptable.
1589 if (FlagsVal == ~0U || (FlagsVal & Flag))
1590 return MatchOperand_NoMatch;
1593 } else // No match for special register.
1594 return MatchOperand_NoMatch;
1596 // Special register without flags are equivalent to "fc" flags.
1600 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1601 if (SpecReg == "spsr")
1604 Parser.Lex(); // Eat identifier token.
1605 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
1606 return MatchOperand_Success;
1609 /// parseMemMode2Operand - Try to parse memory addressing mode 2 operand.
1610 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1611 parseMemMode2Operand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1612 assert(Parser.getTok().is(AsmToken::LBrac) && "Token is not a \"[\"");
1614 if (ParseMemory(Operands, ARMII::AddrMode2))
1615 return MatchOperand_NoMatch;
1617 return MatchOperand_Success;
1620 /// parseMemMode3Operand - Try to parse memory addressing mode 3 operand.
1621 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1622 parseMemMode3Operand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1623 assert(Parser.getTok().is(AsmToken::LBrac) && "Token is not a \"[\"");
1625 if (ParseMemory(Operands, ARMII::AddrMode3))
1626 return MatchOperand_NoMatch;
1628 return MatchOperand_Success;
1631 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1632 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
1633 int Low, int High) {
1634 const AsmToken &Tok = Parser.getTok();
1635 if (Tok.isNot(AsmToken::Identifier)) {
1636 Error(Parser.getTok().getLoc(), Op + " operand expected.");
1637 return MatchOperand_ParseFail;
1639 StringRef ShiftName = Tok.getString();
1640 std::string LowerOp = LowercaseString(Op);
1641 std::string UpperOp = UppercaseString(Op);
1642 if (ShiftName != LowerOp && ShiftName != UpperOp) {
1643 Error(Parser.getTok().getLoc(), Op + " operand expected.");
1644 return MatchOperand_ParseFail;
1646 Parser.Lex(); // Eat shift type token.
1648 // There must be a '#' and a shift amount.
1649 if (Parser.getTok().isNot(AsmToken::Hash)) {
1650 Error(Parser.getTok().getLoc(), "'#' expected");
1651 return MatchOperand_ParseFail;
1653 Parser.Lex(); // Eat hash token.
1655 const MCExpr *ShiftAmount;
1656 SMLoc Loc = Parser.getTok().getLoc();
1657 if (getParser().ParseExpression(ShiftAmount)) {
1658 Error(Loc, "illegal expression");
1659 return MatchOperand_ParseFail;
1661 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1663 Error(Loc, "constant expression expected");
1664 return MatchOperand_ParseFail;
1666 int Val = CE->getValue();
1667 if (Val < Low || Val > High) {
1668 Error(Loc, "immediate value out of range");
1669 return MatchOperand_ParseFail;
1672 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
1674 return MatchOperand_Success;
1677 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1678 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1679 const AsmToken &Tok = Parser.getTok();
1680 SMLoc S = Tok.getLoc();
1681 if (Tok.isNot(AsmToken::Identifier)) {
1682 Error(Tok.getLoc(), "'be' or 'le' operand expected");
1683 return MatchOperand_ParseFail;
1685 int Val = StringSwitch<int>(Tok.getString())
1689 Parser.Lex(); // Eat the token.
1692 Error(Tok.getLoc(), "'be' or 'le' operand expected");
1693 return MatchOperand_ParseFail;
1695 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
1697 S, Parser.getTok().getLoc()));
1698 return MatchOperand_Success;
1701 /// CvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
1702 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
1703 /// when they refer multiple MIOperands inside a single one.
1705 CvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
1706 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1707 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
1709 // Create a writeback register dummy placeholder.
1710 Inst.addOperand(MCOperand::CreateImm(0));
1712 ((ARMOperand*)Operands[3])->addMemMode2Operands(Inst, 3);
1713 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
1717 /// CvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
1718 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
1719 /// when they refer multiple MIOperands inside a single one.
1721 CvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
1722 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1723 // Create a writeback register dummy placeholder.
1724 Inst.addOperand(MCOperand::CreateImm(0));
1725 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
1726 ((ARMOperand*)Operands[3])->addMemMode2Operands(Inst, 3);
1727 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
1731 /// CvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
1732 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
1733 /// when they refer multiple MIOperands inside a single one.
1735 CvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
1736 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1737 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
1739 // Create a writeback register dummy placeholder.
1740 Inst.addOperand(MCOperand::CreateImm(0));
1742 ((ARMOperand*)Operands[3])->addMemMode3Operands(Inst, 3);
1743 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
1747 /// CvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
1748 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
1749 /// when they refer multiple MIOperands inside a single one.
1751 CvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
1752 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1753 // Create a writeback register dummy placeholder.
1754 Inst.addOperand(MCOperand::CreateImm(0));
1755 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
1756 ((ARMOperand*)Operands[3])->addMemMode3Operands(Inst, 3);
1757 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
1761 /// Parse an ARM memory expression, return false if successful else return true
1762 /// or an error. The first token must be a '[' when called.
1764 /// TODO Only preindexing and postindexing addressing are started, unindexed
1765 /// with option, etc are still to do.
1767 ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1768 ARMII::AddrMode AddrMode = ARMII::AddrModeNone) {
1770 assert(Parser.getTok().is(AsmToken::LBrac) &&
1771 "Token is not a Left Bracket");
1772 S = Parser.getTok().getLoc();
1773 Parser.Lex(); // Eat left bracket token.
1775 const AsmToken &BaseRegTok = Parser.getTok();
1776 if (BaseRegTok.isNot(AsmToken::Identifier)) {
1777 Error(BaseRegTok.getLoc(), "register expected");
1780 int BaseRegNum = TryParseRegister();
1781 if (BaseRegNum == -1) {
1782 Error(BaseRegTok.getLoc(), "register expected");
1786 // The next token must either be a comma or a closing bracket.
1787 const AsmToken &Tok = Parser.getTok();
1788 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
1791 bool Preindexed = false;
1792 bool Postindexed = false;
1793 bool OffsetIsReg = false;
1794 bool Negative = false;
1795 bool Writeback = false;
1796 ARMOperand *WBOp = 0;
1797 int OffsetRegNum = -1;
1798 bool OffsetRegShifted = false;
1799 enum ARM_AM::ShiftOpc ShiftType = ARM_AM::lsl;
1800 const MCExpr *ShiftAmount = 0;
1801 const MCExpr *Offset = 0;
1803 // First look for preindexed address forms, that is after the "[Rn" we now
1804 // have to see if the next token is a comma.
1805 if (Tok.is(AsmToken::Comma)) {
1807 Parser.Lex(); // Eat comma token.
1809 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
1810 Offset, OffsetIsReg, OffsetRegNum, E))
1812 const AsmToken &RBracTok = Parser.getTok();
1813 if (RBracTok.isNot(AsmToken::RBrac)) {
1814 Error(RBracTok.getLoc(), "']' expected");
1817 E = RBracTok.getLoc();
1818 Parser.Lex(); // Eat right bracket token.
1820 const AsmToken &ExclaimTok = Parser.getTok();
1821 if (ExclaimTok.is(AsmToken::Exclaim)) {
1822 // None of addrmode3 instruction uses "!"
1823 if (AddrMode == ARMII::AddrMode3)
1826 WBOp = ARMOperand::CreateToken(ExclaimTok.getString(),
1827 ExclaimTok.getLoc());
1829 Parser.Lex(); // Eat exclaim token
1830 } else { // In addressing mode 2, pre-indexed mode always end with "!"
1831 if (AddrMode == ARMII::AddrMode2)
1835 // The "[Rn" we have so far was not followed by a comma.
1837 // If there's anything other than the right brace, this is a post indexing
1840 Parser.Lex(); // Eat right bracket token.
1842 const AsmToken &NextTok = Parser.getTok();
1844 if (NextTok.isNot(AsmToken::EndOfStatement)) {
1848 if (NextTok.isNot(AsmToken::Comma)) {
1849 Error(NextTok.getLoc(), "',' expected");
1853 Parser.Lex(); // Eat comma token.
1855 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
1856 ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
1862 // Force Offset to exist if used.
1865 Offset = MCConstantExpr::Create(0, getContext());
1867 if (AddrMode == ARMII::AddrMode3 && OffsetRegShifted) {
1868 Error(E, "shift amount not supported");
1873 Operands.push_back(ARMOperand::CreateMem(AddrMode, BaseRegNum, OffsetIsReg,
1874 Offset, OffsetRegNum, OffsetRegShifted,
1875 ShiftType, ShiftAmount, Preindexed,
1876 Postindexed, Negative, Writeback, S, E));
1878 Operands.push_back(WBOp);
1883 /// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
1884 /// we will parse the following (were +/- means that a plus or minus is
1889 /// we return false on success or an error otherwise.
1890 bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
1891 bool &OffsetRegShifted,
1892 enum ARM_AM::ShiftOpc &ShiftType,
1893 const MCExpr *&ShiftAmount,
1894 const MCExpr *&Offset,
1899 OffsetRegShifted = false;
1900 OffsetIsReg = false;
1902 const AsmToken &NextTok = Parser.getTok();
1903 E = NextTok.getLoc();
1904 if (NextTok.is(AsmToken::Plus))
1905 Parser.Lex(); // Eat plus token.
1906 else if (NextTok.is(AsmToken::Minus)) {
1908 Parser.Lex(); // Eat minus token
1910 // See if there is a register following the "[Rn," or "[Rn]," we have so far.
1911 const AsmToken &OffsetRegTok = Parser.getTok();
1912 if (OffsetRegTok.is(AsmToken::Identifier)) {
1913 SMLoc CurLoc = OffsetRegTok.getLoc();
1914 OffsetRegNum = TryParseRegister();
1915 if (OffsetRegNum != -1) {
1921 // If we parsed a register as the offset then there can be a shift after that.
1922 if (OffsetRegNum != -1) {
1923 // Look for a comma then a shift
1924 const AsmToken &Tok = Parser.getTok();
1925 if (Tok.is(AsmToken::Comma)) {
1926 Parser.Lex(); // Eat comma token.
1928 const AsmToken &Tok = Parser.getTok();
1929 if (ParseShift(ShiftType, ShiftAmount, E))
1930 return Error(Tok.getLoc(), "shift expected");
1931 OffsetRegShifted = true;
1934 else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
1935 // Look for #offset following the "[Rn," or "[Rn],"
1936 const AsmToken &HashTok = Parser.getTok();
1937 if (HashTok.isNot(AsmToken::Hash))
1938 return Error(HashTok.getLoc(), "'#' expected");
1940 Parser.Lex(); // Eat hash token.
1942 if (getParser().ParseExpression(Offset))
1944 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1949 /// ParseShift as one of these two:
1950 /// ( lsl | lsr | asr | ror ) , # shift_amount
1952 /// and returns true if it parses a shift otherwise it returns false.
1953 bool ARMAsmParser::ParseShift(ARM_AM::ShiftOpc &St,
1954 const MCExpr *&ShiftAmount, SMLoc &E) {
1955 const AsmToken &Tok = Parser.getTok();
1956 if (Tok.isNot(AsmToken::Identifier))
1958 StringRef ShiftName = Tok.getString();
1959 if (ShiftName == "lsl" || ShiftName == "LSL")
1961 else if (ShiftName == "lsr" || ShiftName == "LSR")
1963 else if (ShiftName == "asr" || ShiftName == "ASR")
1965 else if (ShiftName == "ror" || ShiftName == "ROR")
1967 else if (ShiftName == "rrx" || ShiftName == "RRX")
1971 Parser.Lex(); // Eat shift type token.
1973 // Rrx stands alone.
1974 if (St == ARM_AM::rrx)
1977 // Otherwise, there must be a '#' and a shift amount.
1978 const AsmToken &HashTok = Parser.getTok();
1979 if (HashTok.isNot(AsmToken::Hash))
1980 return Error(HashTok.getLoc(), "'#' expected");
1981 Parser.Lex(); // Eat hash token.
1983 if (getParser().ParseExpression(ShiftAmount))
1989 /// Parse a arm instruction operand. For now this parses the operand regardless
1990 /// of the mnemonic.
1991 bool ARMAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1992 StringRef Mnemonic) {
1995 // Check if the current operand has a custom associated parser, if so, try to
1996 // custom parse the operand, or fallback to the general approach.
1997 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1998 if (ResTy == MatchOperand_Success)
2000 // If there wasn't a custom match, try the generic matcher below. Otherwise,
2001 // there was a match, but an error occurred, in which case, just return that
2002 // the operand parsing failed.
2003 if (ResTy == MatchOperand_ParseFail)
2006 switch (getLexer().getKind()) {
2008 Error(Parser.getTok().getLoc(), "unexpected token in operand");
2010 case AsmToken::Identifier: {
2011 if (!TryParseRegisterWithWriteBack(Operands))
2013 int Res = TryParseShiftRegister(Operands);
2014 if (Res == 0) // success
2016 else if (Res == -1) // irrecoverable error
2019 // Fall though for the Identifier case that is not a register or a
2022 case AsmToken::Integer: // things like 1f and 2b as a branch targets
2023 case AsmToken::Dot: { // . as a branch target
2024 // This was not a register so parse other operands that start with an
2025 // identifier (like labels) as expressions and create them as immediates.
2026 const MCExpr *IdVal;
2027 S = Parser.getTok().getLoc();
2028 if (getParser().ParseExpression(IdVal))
2030 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2031 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
2034 case AsmToken::LBrac:
2035 return ParseMemory(Operands);
2036 case AsmToken::LCurly:
2037 return ParseRegisterList(Operands);
2038 case AsmToken::Hash:
2039 // #42 -> immediate.
2040 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
2041 S = Parser.getTok().getLoc();
2043 const MCExpr *ImmVal;
2044 if (getParser().ParseExpression(ImmVal))
2046 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2047 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
2049 case AsmToken::Colon: {
2050 // ":lower16:" and ":upper16:" expression prefixes
2051 // FIXME: Check it's an expression prefix,
2052 // e.g. (FOO - :lower16:BAR) isn't legal.
2053 ARMMCExpr::VariantKind RefKind;
2054 if (ParsePrefix(RefKind))
2057 const MCExpr *SubExprVal;
2058 if (getParser().ParseExpression(SubExprVal))
2061 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
2063 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2064 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
2070 // ParsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
2071 // :lower16: and :upper16:.
2072 bool ARMAsmParser::ParsePrefix(ARMMCExpr::VariantKind &RefKind) {
2073 RefKind = ARMMCExpr::VK_ARM_None;
2075 // :lower16: and :upper16: modifiers
2076 assert(getLexer().is(AsmToken::Colon) && "expected a :");
2077 Parser.Lex(); // Eat ':'
2079 if (getLexer().isNot(AsmToken::Identifier)) {
2080 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
2084 StringRef IDVal = Parser.getTok().getIdentifier();
2085 if (IDVal == "lower16") {
2086 RefKind = ARMMCExpr::VK_ARM_LO16;
2087 } else if (IDVal == "upper16") {
2088 RefKind = ARMMCExpr::VK_ARM_HI16;
2090 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
2095 if (getLexer().isNot(AsmToken::Colon)) {
2096 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
2099 Parser.Lex(); // Eat the last ':'
2104 ARMAsmParser::ApplyPrefixToExpr(const MCExpr *E,
2105 MCSymbolRefExpr::VariantKind Variant) {
2106 // Recurse over the given expression, rebuilding it to apply the given variant
2107 // to the leftmost symbol.
2108 if (Variant == MCSymbolRefExpr::VK_None)
2111 switch (E->getKind()) {
2112 case MCExpr::Target:
2113 llvm_unreachable("Can't handle target expr yet");
2114 case MCExpr::Constant:
2115 llvm_unreachable("Can't handle lower16/upper16 of constant yet");
2117 case MCExpr::SymbolRef: {
2118 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
2120 if (SRE->getKind() != MCSymbolRefExpr::VK_None)
2123 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext());
2127 llvm_unreachable("Can't handle unary expressions yet");
2129 case MCExpr::Binary: {
2130 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
2131 const MCExpr *LHS = ApplyPrefixToExpr(BE->getLHS(), Variant);
2132 const MCExpr *RHS = BE->getRHS();
2136 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext());
2140 assert(0 && "Invalid expression kind!");
2144 /// \brief Given a mnemonic, split out possible predication code and carry
2145 /// setting letters to form a canonical mnemonic and flags.
2147 // FIXME: Would be nice to autogen this.
2148 StringRef ARMAsmParser::SplitMnemonic(StringRef Mnemonic,
2149 unsigned &PredicationCode,
2151 unsigned &ProcessorIMod) {
2152 PredicationCode = ARMCC::AL;
2153 CarrySetting = false;
2156 // Ignore some mnemonics we know aren't predicated forms.
2158 // FIXME: Would be nice to autogen this.
2159 if ((Mnemonic == "movs" && isThumb()) ||
2160 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
2161 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
2162 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
2163 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
2164 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
2165 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
2166 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
2169 // First, split out any predication code. Ignore mnemonics we know aren't
2170 // predicated but do have a carry-set and so weren't caught above.
2171 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
2172 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls") {
2173 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
2174 .Case("eq", ARMCC::EQ)
2175 .Case("ne", ARMCC::NE)
2176 .Case("hs", ARMCC::HS)
2177 .Case("cs", ARMCC::HS)
2178 .Case("lo", ARMCC::LO)
2179 .Case("cc", ARMCC::LO)
2180 .Case("mi", ARMCC::MI)
2181 .Case("pl", ARMCC::PL)
2182 .Case("vs", ARMCC::VS)
2183 .Case("vc", ARMCC::VC)
2184 .Case("hi", ARMCC::HI)
2185 .Case("ls", ARMCC::LS)
2186 .Case("ge", ARMCC::GE)
2187 .Case("lt", ARMCC::LT)
2188 .Case("gt", ARMCC::GT)
2189 .Case("le", ARMCC::LE)
2190 .Case("al", ARMCC::AL)
2193 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
2194 PredicationCode = CC;
2198 // Next, determine if we have a carry setting bit. We explicitly ignore all
2199 // the instructions we know end in 's'.
2200 if (Mnemonic.endswith("s") &&
2201 !(Mnemonic == "asrs" || Mnemonic == "cps" || Mnemonic == "mls" ||
2202 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
2203 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
2204 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
2205 Mnemonic == "vrsqrts" || (Mnemonic == "movs" && isThumb()))) {
2206 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
2207 CarrySetting = true;
2210 // The "cps" instruction can have a interrupt mode operand which is glued into
2211 // the mnemonic. Check if this is the case, split it and parse the imod op
2212 if (Mnemonic.startswith("cps")) {
2213 // Split out any imod code.
2215 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
2216 .Case("ie", ARM_PROC::IE)
2217 .Case("id", ARM_PROC::ID)
2220 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
2221 ProcessorIMod = IMod;
2228 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
2229 /// inclusion of carry set or predication code operands.
2231 // FIXME: It would be nice to autogen this.
2233 GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
2234 bool &CanAcceptPredicationCode) {
2235 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
2236 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
2237 Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
2238 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
2239 Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" ||
2240 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
2241 Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
2242 Mnemonic == "eor" || Mnemonic == "smlal" ||
2243 (Mnemonic == "mov" && !isThumbOne())) {
2244 CanAcceptCarrySet = true;
2246 CanAcceptCarrySet = false;
2249 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
2250 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
2251 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
2252 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
2253 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "clrex" ||
2254 Mnemonic == "setend" ||
2255 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumb())) {
2256 CanAcceptPredicationCode = false;
2258 CanAcceptPredicationCode = true;
2262 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
2263 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
2264 CanAcceptPredicationCode = false;
2267 /// Parse an arm instruction mnemonic followed by its operands.
2268 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
2269 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2270 // Create the leading tokens for the mnemonic, split by '.' characters.
2271 size_t Start = 0, Next = Name.find('.');
2272 StringRef Mnemonic = Name.slice(Start, Next);
2274 // Split out the predication code and carry setting flag from the mnemonic.
2275 unsigned PredicationCode;
2276 unsigned ProcessorIMod;
2278 Mnemonic = SplitMnemonic(Mnemonic, PredicationCode, CarrySetting,
2281 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
2283 // FIXME: This is all a pretty gross hack. We should automatically handle
2284 // optional operands like this via tblgen.
2286 // Next, add the CCOut and ConditionCode operands, if needed.
2288 // For mnemonics which can ever incorporate a carry setting bit or predication
2289 // code, our matching model involves us always generating CCOut and
2290 // ConditionCode operands to match the mnemonic "as written" and then we let
2291 // the matcher deal with finding the right instruction or generating an
2292 // appropriate error.
2293 bool CanAcceptCarrySet, CanAcceptPredicationCode;
2294 GetMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
2296 // If we had a carry-set on an instruction that can't do that, issue an
2298 if (!CanAcceptCarrySet && CarrySetting) {
2299 Parser.EatToEndOfStatement();
2300 return Error(NameLoc, "instruction '" + Mnemonic +
2301 "' can not set flags, but 's' suffix specified");
2303 // If we had a predication code on an instruction that can't do that, issue an
2305 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
2306 Parser.EatToEndOfStatement();
2307 return Error(NameLoc, "instruction '" + Mnemonic +
2308 "' is not predicable, but condition code specified");
2311 // Add the carry setting operand, if necessary.
2313 // FIXME: It would be awesome if we could somehow invent a location such that
2314 // match errors on this operand would print a nice diagnostic about how the
2315 // 's' character in the mnemonic resulted in a CCOut operand.
2316 if (CanAcceptCarrySet)
2317 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
2320 // Add the predication code operand, if necessary.
2321 if (CanAcceptPredicationCode) {
2322 Operands.push_back(ARMOperand::CreateCondCode(
2323 ARMCC::CondCodes(PredicationCode), NameLoc));
2326 // Add the processor imod operand, if necessary.
2327 if (ProcessorIMod) {
2328 Operands.push_back(ARMOperand::CreateImm(
2329 MCConstantExpr::Create(ProcessorIMod, getContext()),
2332 // This mnemonic can't ever accept a imod, but the user wrote
2333 // one (or misspelled another mnemonic).
2335 // FIXME: Issue a nice error.
2338 // Add the remaining tokens in the mnemonic.
2339 while (Next != StringRef::npos) {
2341 Next = Name.find('.', Start + 1);
2342 StringRef ExtraToken = Name.slice(Start, Next);
2344 Operands.push_back(ARMOperand::CreateToken(ExtraToken, NameLoc));
2347 // Read the remaining operands.
2348 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2349 // Read the first operand.
2350 if (ParseOperand(Operands, Mnemonic)) {
2351 Parser.EatToEndOfStatement();
2355 while (getLexer().is(AsmToken::Comma)) {
2356 Parser.Lex(); // Eat the comma.
2358 // Parse and remember the operand.
2359 if (ParseOperand(Operands, Mnemonic)) {
2360 Parser.EatToEndOfStatement();
2366 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2367 Parser.EatToEndOfStatement();
2368 return TokError("unexpected token in argument list");
2371 Parser.Lex(); // Consume the EndOfStatement
2374 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
2375 // another does not. Specifically, the MOVW instruction does not. So we
2376 // special case it here and remove the defaulted (non-setting) cc_out
2377 // operand if that's the instruction we're trying to match.
2379 // We do this post-processing of the explicit operands rather than just
2380 // conditionally adding the cc_out in the first place because we need
2381 // to check the type of the parsed immediate operand.
2382 if (Mnemonic == "mov" && Operands.size() > 4 &&
2383 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
2384 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
2385 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) {
2386 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
2387 Operands.erase(Operands.begin() + 1);
2395 MatchAndEmitInstruction(SMLoc IDLoc,
2396 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2400 MatchResultTy MatchResult;
2401 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
2402 switch (MatchResult) {
2404 Out.EmitInstruction(Inst);
2406 case Match_MissingFeature:
2407 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
2409 case Match_InvalidOperand: {
2410 SMLoc ErrorLoc = IDLoc;
2411 if (ErrorInfo != ~0U) {
2412 if (ErrorInfo >= Operands.size())
2413 return Error(IDLoc, "too few operands for instruction");
2415 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
2416 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
2419 return Error(ErrorLoc, "invalid operand for instruction");
2421 case Match_MnemonicFail:
2422 return Error(IDLoc, "unrecognized instruction mnemonic");
2423 case Match_ConversionFail:
2424 return Error(IDLoc, "unable to convert operands to instruction");
2427 llvm_unreachable("Implement any new match types added!");
2431 /// ParseDirective parses the arm specific directives
2432 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
2433 StringRef IDVal = DirectiveID.getIdentifier();
2434 if (IDVal == ".word")
2435 return ParseDirectiveWord(4, DirectiveID.getLoc());
2436 else if (IDVal == ".thumb")
2437 return ParseDirectiveThumb(DirectiveID.getLoc());
2438 else if (IDVal == ".thumb_func")
2439 return ParseDirectiveThumbFunc(DirectiveID.getLoc());
2440 else if (IDVal == ".code")
2441 return ParseDirectiveCode(DirectiveID.getLoc());
2442 else if (IDVal == ".syntax")
2443 return ParseDirectiveSyntax(DirectiveID.getLoc());
2447 /// ParseDirectiveWord
2448 /// ::= .word [ expression (, expression)* ]
2449 bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
2450 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2452 const MCExpr *Value;
2453 if (getParser().ParseExpression(Value))
2456 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
2458 if (getLexer().is(AsmToken::EndOfStatement))
2461 // FIXME: Improve diagnostic.
2462 if (getLexer().isNot(AsmToken::Comma))
2463 return Error(L, "unexpected token in directive");
2472 /// ParseDirectiveThumb
2474 bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
2475 if (getLexer().isNot(AsmToken::EndOfStatement))
2476 return Error(L, "unexpected token in directive");
2479 // TODO: set thumb mode
2480 // TODO: tell the MC streamer the mode
2481 // getParser().getStreamer().Emit???();
2485 /// ParseDirectiveThumbFunc
2486 /// ::= .thumbfunc symbol_name
2487 bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
2488 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
2489 bool isMachO = MAI.hasSubsectionsViaSymbols();
2492 // Darwin asm has function name after .thumb_func direction
2495 const AsmToken &Tok = Parser.getTok();
2496 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
2497 return Error(L, "unexpected token in .thumb_func directive");
2498 Name = Tok.getString();
2499 Parser.Lex(); // Consume the identifier token.
2502 if (getLexer().isNot(AsmToken::EndOfStatement))
2503 return Error(L, "unexpected token in directive");
2506 // FIXME: assuming function name will be the line following .thumb_func
2508 Name = Parser.getTok().getString();
2511 // Mark symbol as a thumb symbol.
2512 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
2513 getParser().getStreamer().EmitThumbFunc(Func);
2517 /// ParseDirectiveSyntax
2518 /// ::= .syntax unified | divided
2519 bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
2520 const AsmToken &Tok = Parser.getTok();
2521 if (Tok.isNot(AsmToken::Identifier))
2522 return Error(L, "unexpected token in .syntax directive");
2523 StringRef Mode = Tok.getString();
2524 if (Mode == "unified" || Mode == "UNIFIED")
2526 else if (Mode == "divided" || Mode == "DIVIDED")
2527 return Error(L, "'.syntax divided' arm asssembly not supported");
2529 return Error(L, "unrecognized syntax mode in .syntax directive");
2531 if (getLexer().isNot(AsmToken::EndOfStatement))
2532 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
2535 // TODO tell the MC streamer the mode
2536 // getParser().getStreamer().Emit???();
2540 /// ParseDirectiveCode
2541 /// ::= .code 16 | 32
2542 bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
2543 const AsmToken &Tok = Parser.getTok();
2544 if (Tok.isNot(AsmToken::Integer))
2545 return Error(L, "unexpected token in .code directive");
2546 int64_t Val = Parser.getTok().getIntVal();
2552 return Error(L, "invalid operand to .code directive");
2554 if (getLexer().isNot(AsmToken::EndOfStatement))
2555 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
2561 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
2565 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
2571 extern "C" void LLVMInitializeARMAsmLexer();
2573 /// Force static initialization.
2574 extern "C" void LLVMInitializeARMAsmParser() {
2575 RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
2576 RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
2577 LLVMInitializeARMAsmLexer();
2580 #define GET_REGISTER_MATCHER
2581 #define GET_MATCHER_IMPLEMENTATION
2582 #include "ARMGenAsmMatcher.inc"