1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMBaseInfo.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMMCExpr.h"
13 #include "llvm/MC/MCParser/MCAsmLexer.h"
14 #include "llvm/MC/MCParser/MCAsmParser.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCAsmInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCTargetAsmParser.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/SourceMgr.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/ADT/BitVector.h"
30 #include "llvm/ADT/OwningPtr.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/StringExtras.h"
34 #include "llvm/ADT/StringSwitch.h"
35 #include "llvm/ADT/Twine.h"
43 class ARMAsmParser : public MCTargetAsmParser {
48 ARMCC::CondCodes Cond; // Condition for IT block.
49 unsigned Mask:4; // Condition mask for instructions.
50 // Starting at first 1 (from lsb).
51 // '1' condition as indicated in IT.
52 // '0' inverse of condition (else).
53 // Count of instructions in IT block is
54 // 4 - trailingzeroes(mask)
56 bool FirstCond; // Explicit flag for when we're parsing the
57 // First instruction in the IT block. It's
58 // implied in the mask, so needs special
61 unsigned CurPosition; // Current position in parsing of IT
62 // block. In range [0,3]. Initialized
63 // according to count of instructions in block.
64 // ~0U if no active IT block.
66 bool inITBlock() { return ITState.CurPosition != ~0U;}
67 void forwardITPosition() {
68 if (!inITBlock()) return;
69 // Move to the next instruction in the IT block, if there is one. If not,
70 // mark the block as done.
71 unsigned TZ = CountTrailingZeros_32(ITState.Mask);
72 if (++ITState.CurPosition == 5 - TZ)
73 ITState.CurPosition = ~0U; // Done with the IT block after this.
77 MCAsmParser &getParser() const { return Parser; }
78 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
80 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
81 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
83 int tryParseRegister();
84 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
85 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
86 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
87 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
88 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
89 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
90 const MCExpr *applyPrefixToExpr(const MCExpr *E,
91 MCSymbolRefExpr::VariantKind Variant);
94 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
95 unsigned &ShiftAmount);
96 bool parseDirectiveWord(unsigned Size, SMLoc L);
97 bool parseDirectiveThumb(SMLoc L);
98 bool parseDirectiveThumbFunc(SMLoc L);
99 bool parseDirectiveCode(SMLoc L);
100 bool parseDirectiveSyntax(SMLoc L);
102 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
103 bool &CarrySetting, unsigned &ProcessorIMod,
105 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
106 bool &CanAcceptPredicationCode);
108 bool isThumb() const {
109 // FIXME: Can tablegen auto-generate this?
110 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
112 bool isThumbOne() const {
113 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
115 bool isThumbTwo() const {
116 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
118 bool hasV6Ops() const {
119 return STI.getFeatureBits() & ARM::HasV6Ops;
122 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
123 setAvailableFeatures(FB);
126 /// @name Auto-generated Match Functions
129 #define GET_ASSEMBLER_HEADER
130 #include "ARMGenAsmMatcher.inc"
134 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
135 OperandMatchResultTy parseCoprocNumOperand(
136 SmallVectorImpl<MCParsedAsmOperand*>&);
137 OperandMatchResultTy parseCoprocRegOperand(
138 SmallVectorImpl<MCParsedAsmOperand*>&);
139 OperandMatchResultTy parseMemBarrierOptOperand(
140 SmallVectorImpl<MCParsedAsmOperand*>&);
141 OperandMatchResultTy parseProcIFlagsOperand(
142 SmallVectorImpl<MCParsedAsmOperand*>&);
143 OperandMatchResultTy parseMSRMaskOperand(
144 SmallVectorImpl<MCParsedAsmOperand*>&);
145 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
146 StringRef Op, int Low, int High);
147 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
148 return parsePKHImm(O, "lsl", 0, 31);
150 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
151 return parsePKHImm(O, "asr", 1, 32);
153 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
154 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
155 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
156 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
157 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
158 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
160 // Asm Match Converter Methods
161 bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
162 const SmallVectorImpl<MCParsedAsmOperand*> &);
163 bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
164 const SmallVectorImpl<MCParsedAsmOperand*> &);
165 bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
166 const SmallVectorImpl<MCParsedAsmOperand*> &);
167 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
168 const SmallVectorImpl<MCParsedAsmOperand*> &);
169 bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
170 const SmallVectorImpl<MCParsedAsmOperand*> &);
171 bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
172 const SmallVectorImpl<MCParsedAsmOperand*> &);
173 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
174 const SmallVectorImpl<MCParsedAsmOperand*> &);
175 bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
176 const SmallVectorImpl<MCParsedAsmOperand*> &);
177 bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
178 const SmallVectorImpl<MCParsedAsmOperand*> &);
179 bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
180 const SmallVectorImpl<MCParsedAsmOperand*> &);
181 bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
182 const SmallVectorImpl<MCParsedAsmOperand*> &);
183 bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
184 const SmallVectorImpl<MCParsedAsmOperand*> &);
185 bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
186 const SmallVectorImpl<MCParsedAsmOperand*> &);
187 bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
188 const SmallVectorImpl<MCParsedAsmOperand*> &);
189 bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
190 const SmallVectorImpl<MCParsedAsmOperand*> &);
191 bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
192 const SmallVectorImpl<MCParsedAsmOperand*> &);
194 bool validateInstruction(MCInst &Inst,
195 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
196 void processInstruction(MCInst &Inst,
197 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
198 bool shouldOmitCCOutOperand(StringRef Mnemonic,
199 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
202 enum ARMMatchResultTy {
203 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
204 Match_RequiresNotITBlock,
209 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
210 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
211 MCAsmParserExtension::Initialize(_Parser);
213 // Initialize the set of available features.
214 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
216 // Not in an ITBlock to start with.
217 ITState.CurPosition = ~0U;
220 // Implementation of the MCTargetAsmParser interface:
221 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
222 bool ParseInstruction(StringRef Name, SMLoc NameLoc,
223 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
224 bool ParseDirective(AsmToken DirectiveID);
226 unsigned checkTargetMatchPredicate(MCInst &Inst);
228 bool MatchAndEmitInstruction(SMLoc IDLoc,
229 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
232 } // end anonymous namespace
236 /// ARMOperand - Instances of this class represent a parsed ARM machine
238 class ARMOperand : public MCParsedAsmOperand {
263 SMLoc StartLoc, EndLoc;
264 SmallVector<unsigned, 8> Registers;
268 ARMCC::CondCodes Val;
284 ARM_PROC::IFlags Val;
304 /// Combined record for all forms of ARM address expressions.
307 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
309 const MCConstantExpr *OffsetImm; // Offset immediate value
310 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
311 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
312 unsigned ShiftImm; // shift for OffsetReg.
313 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
319 ARM_AM::ShiftOpc ShiftTy;
328 ARM_AM::ShiftOpc ShiftTy;
334 ARM_AM::ShiftOpc ShiftTy;
347 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
349 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
351 StartLoc = o.StartLoc;
368 case DPRRegisterList:
369 case SPRRegisterList:
370 Registers = o.Registers;
385 case PostIndexRegister:
386 PostIdxReg = o.PostIdxReg;
394 case ShifterImmediate:
395 ShifterImm = o.ShifterImm;
397 case ShiftedRegister:
398 RegShiftedReg = o.RegShiftedReg;
400 case ShiftedImmediate:
401 RegShiftedImm = o.RegShiftedImm;
403 case RotateImmediate:
406 case BitfieldDescriptor:
407 Bitfield = o.Bitfield;
412 /// getStartLoc - Get the location of the first token of this operand.
413 SMLoc getStartLoc() const { return StartLoc; }
414 /// getEndLoc - Get the location of the last token of this operand.
415 SMLoc getEndLoc() const { return EndLoc; }
417 ARMCC::CondCodes getCondCode() const {
418 assert(Kind == CondCode && "Invalid access!");
422 unsigned getCoproc() const {
423 assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
427 StringRef getToken() const {
428 assert(Kind == Token && "Invalid access!");
429 return StringRef(Tok.Data, Tok.Length);
432 unsigned getReg() const {
433 assert((Kind == Register || Kind == CCOut) && "Invalid access!");
437 const SmallVectorImpl<unsigned> &getRegList() const {
438 assert((Kind == RegisterList || Kind == DPRRegisterList ||
439 Kind == SPRRegisterList) && "Invalid access!");
443 const MCExpr *getImm() const {
444 assert(Kind == Immediate && "Invalid access!");
448 ARM_MB::MemBOpt getMemBarrierOpt() const {
449 assert(Kind == MemBarrierOpt && "Invalid access!");
453 ARM_PROC::IFlags getProcIFlags() const {
454 assert(Kind == ProcIFlags && "Invalid access!");
458 unsigned getMSRMask() const {
459 assert(Kind == MSRMask && "Invalid access!");
463 bool isCoprocNum() const { return Kind == CoprocNum; }
464 bool isCoprocReg() const { return Kind == CoprocReg; }
465 bool isCondCode() const { return Kind == CondCode; }
466 bool isCCOut() const { return Kind == CCOut; }
467 bool isITMask() const { return Kind == ITCondMask; }
468 bool isITCondCode() const { return Kind == CondCode; }
469 bool isImm() const { return Kind == Immediate; }
470 bool isImm8s4() const {
471 if (Kind != Immediate)
473 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
474 if (!CE) return false;
475 int64_t Value = CE->getValue();
476 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
478 bool isImm0_1020s4() const {
479 if (Kind != Immediate)
481 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
482 if (!CE) return false;
483 int64_t Value = CE->getValue();
484 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
486 bool isImm0_508s4() const {
487 if (Kind != Immediate)
489 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
490 if (!CE) return false;
491 int64_t Value = CE->getValue();
492 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
494 bool isImm0_255() const {
495 if (Kind != Immediate)
497 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
498 if (!CE) return false;
499 int64_t Value = CE->getValue();
500 return Value >= 0 && Value < 256;
502 bool isImm0_7() const {
503 if (Kind != Immediate)
505 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
506 if (!CE) return false;
507 int64_t Value = CE->getValue();
508 return Value >= 0 && Value < 8;
510 bool isImm0_15() const {
511 if (Kind != Immediate)
513 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
514 if (!CE) return false;
515 int64_t Value = CE->getValue();
516 return Value >= 0 && Value < 16;
518 bool isImm0_31() const {
519 if (Kind != Immediate)
521 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
522 if (!CE) return false;
523 int64_t Value = CE->getValue();
524 return Value >= 0 && Value < 32;
526 bool isImm1_16() const {
527 if (Kind != Immediate)
529 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
530 if (!CE) return false;
531 int64_t Value = CE->getValue();
532 return Value > 0 && Value < 17;
534 bool isImm1_32() const {
535 if (Kind != Immediate)
537 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
538 if (!CE) return false;
539 int64_t Value = CE->getValue();
540 return Value > 0 && Value < 33;
542 bool isImm0_65535() const {
543 if (Kind != Immediate)
545 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
546 if (!CE) return false;
547 int64_t Value = CE->getValue();
548 return Value >= 0 && Value < 65536;
550 bool isImm0_65535Expr() const {
551 if (Kind != Immediate)
553 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
554 // If it's not a constant expression, it'll generate a fixup and be
556 if (!CE) return true;
557 int64_t Value = CE->getValue();
558 return Value >= 0 && Value < 65536;
560 bool isImm24bit() const {
561 if (Kind != Immediate)
563 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
564 if (!CE) return false;
565 int64_t Value = CE->getValue();
566 return Value >= 0 && Value <= 0xffffff;
568 bool isImmThumbSR() const {
569 if (Kind != Immediate)
571 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
572 if (!CE) return false;
573 int64_t Value = CE->getValue();
574 return Value > 0 && Value < 33;
576 bool isPKHLSLImm() const {
577 if (Kind != Immediate)
579 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
580 if (!CE) return false;
581 int64_t Value = CE->getValue();
582 return Value >= 0 && Value < 32;
584 bool isPKHASRImm() const {
585 if (Kind != Immediate)
587 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
588 if (!CE) return false;
589 int64_t Value = CE->getValue();
590 return Value > 0 && Value <= 32;
592 bool isARMSOImm() const {
593 if (Kind != Immediate)
595 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
596 if (!CE) return false;
597 int64_t Value = CE->getValue();
598 return ARM_AM::getSOImmVal(Value) != -1;
600 bool isT2SOImm() const {
601 if (Kind != Immediate)
603 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
604 if (!CE) return false;
605 int64_t Value = CE->getValue();
606 return ARM_AM::getT2SOImmVal(Value) != -1;
608 bool isSetEndImm() const {
609 if (Kind != Immediate)
611 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
612 if (!CE) return false;
613 int64_t Value = CE->getValue();
614 return Value == 1 || Value == 0;
616 bool isReg() const { return Kind == Register; }
617 bool isRegList() const { return Kind == RegisterList; }
618 bool isDPRRegList() const { return Kind == DPRRegisterList; }
619 bool isSPRRegList() const { return Kind == SPRRegisterList; }
620 bool isToken() const { return Kind == Token; }
621 bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
622 bool isMemory() const { return Kind == Memory; }
623 bool isShifterImm() const { return Kind == ShifterImmediate; }
624 bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
625 bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
626 bool isRotImm() const { return Kind == RotateImmediate; }
627 bool isBitfield() const { return Kind == BitfieldDescriptor; }
628 bool isPostIdxRegShifted() const { return Kind == PostIndexRegister; }
629 bool isPostIdxReg() const {
630 return Kind == PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
632 bool isMemNoOffset() const {
635 // No offset of any kind.
636 return Mem.OffsetRegNum == 0 && Mem.OffsetImm == 0;
638 bool isAddrMode2() const {
641 // Check for register offset.
642 if (Mem.OffsetRegNum) return true;
643 // Immediate offset in range [-4095, 4095].
644 if (!Mem.OffsetImm) return true;
645 int64_t Val = Mem.OffsetImm->getValue();
646 return Val > -4096 && Val < 4096;
648 bool isAM2OffsetImm() const {
649 if (Kind != Immediate)
651 // Immediate offset in range [-4095, 4095].
652 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
653 if (!CE) return false;
654 int64_t Val = CE->getValue();
655 return Val > -4096 && Val < 4096;
657 bool isAddrMode3() const {
660 // No shifts are legal for AM3.
661 if (Mem.ShiftType != ARM_AM::no_shift) return false;
662 // Check for register offset.
663 if (Mem.OffsetRegNum) return true;
664 // Immediate offset in range [-255, 255].
665 if (!Mem.OffsetImm) return true;
666 int64_t Val = Mem.OffsetImm->getValue();
667 return Val > -256 && Val < 256;
669 bool isAM3Offset() const {
670 if (Kind != Immediate && Kind != PostIndexRegister)
672 if (Kind == PostIndexRegister)
673 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
674 // Immediate offset in range [-255, 255].
675 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
676 if (!CE) return false;
677 int64_t Val = CE->getValue();
678 // Special case, #-0 is INT32_MIN.
679 return (Val > -256 && Val < 256) || Val == INT32_MIN;
681 bool isAddrMode5() const {
684 // Check for register offset.
685 if (Mem.OffsetRegNum) return false;
686 // Immediate offset in range [-1020, 1020] and a multiple of 4.
687 if (!Mem.OffsetImm) return true;
688 int64_t Val = Mem.OffsetImm->getValue();
689 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
692 bool isMemRegOffset() const {
693 if (Kind != Memory || !Mem.OffsetRegNum)
697 bool isT2MemRegOffset() const {
698 if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative)
700 // Only lsl #{0, 1, 2, 3} allowed.
701 if (Mem.ShiftType == ARM_AM::no_shift)
703 if (Mem.ShiftType != ARM_AM::lsl || Mem.ShiftImm > 3)
707 bool isMemThumbRR() const {
708 // Thumb reg+reg addressing is simple. Just two registers, a base and
709 // an offset. No shifts, negations or any other complicating factors.
710 if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative ||
711 Mem.ShiftType != ARM_AM::no_shift)
713 return isARMLowRegister(Mem.BaseRegNum) &&
714 (!Mem.OffsetRegNum || isARMLowRegister(Mem.OffsetRegNum));
716 bool isMemThumbRIs4() const {
717 if (Kind != Memory || Mem.OffsetRegNum != 0 ||
718 !isARMLowRegister(Mem.BaseRegNum))
720 // Immediate offset, multiple of 4 in range [0, 124].
721 if (!Mem.OffsetImm) return true;
722 int64_t Val = Mem.OffsetImm->getValue();
723 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
725 bool isMemThumbRIs2() const {
726 if (Kind != Memory || Mem.OffsetRegNum != 0 ||
727 !isARMLowRegister(Mem.BaseRegNum))
729 // Immediate offset, multiple of 4 in range [0, 62].
730 if (!Mem.OffsetImm) return true;
731 int64_t Val = Mem.OffsetImm->getValue();
732 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
734 bool isMemThumbRIs1() const {
735 if (Kind != Memory || Mem.OffsetRegNum != 0 ||
736 !isARMLowRegister(Mem.BaseRegNum))
738 // Immediate offset in range [0, 31].
739 if (!Mem.OffsetImm) return true;
740 int64_t Val = Mem.OffsetImm->getValue();
741 return Val >= 0 && Val <= 31;
743 bool isMemThumbSPI() const {
744 if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP)
746 // Immediate offset, multiple of 4 in range [0, 1020].
747 if (!Mem.OffsetImm) return true;
748 int64_t Val = Mem.OffsetImm->getValue();
749 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
751 bool isMemImm8s4Offset() const {
752 if (Kind != Memory || Mem.OffsetRegNum != 0)
754 // Immediate offset a multiple of 4 in range [-1020, 1020].
755 if (!Mem.OffsetImm) return true;
756 int64_t Val = Mem.OffsetImm->getValue();
757 return Val >= -1020 && Val <= 1020 && (Val & 3) == 0;
759 bool isMemImm0_1020s4Offset() const {
760 if (Kind != Memory || Mem.OffsetRegNum != 0)
762 // Immediate offset a multiple of 4 in range [0, 1020].
763 if (!Mem.OffsetImm) return true;
764 int64_t Val = Mem.OffsetImm->getValue();
765 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
767 bool isMemImm8Offset() const {
768 if (Kind != Memory || Mem.OffsetRegNum != 0)
770 // Immediate offset in range [-255, 255].
771 if (!Mem.OffsetImm) return true;
772 int64_t Val = Mem.OffsetImm->getValue();
773 return Val > -256 && Val < 256;
775 bool isMemPosImm8Offset() const {
776 if (Kind != Memory || Mem.OffsetRegNum != 0)
778 // Immediate offset in range [0, 255].
779 if (!Mem.OffsetImm) return true;
780 int64_t Val = Mem.OffsetImm->getValue();
781 return Val >= 0 && Val < 256;
783 bool isMemNegImm8Offset() const {
784 if (Kind != Memory || Mem.OffsetRegNum != 0)
786 // Immediate offset in range [-255, -1].
787 if (!Mem.OffsetImm) return true;
788 int64_t Val = Mem.OffsetImm->getValue();
789 return Val > -256 && Val < 0;
791 bool isMemUImm12Offset() const {
792 // If we have an immediate that's not a constant, treat it as a label
793 // reference needing a fixup. If it is a constant, it's something else
795 if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
798 if (Kind != Memory || Mem.OffsetRegNum != 0)
800 // Immediate offset in range [0, 4095].
801 if (!Mem.OffsetImm) return true;
802 int64_t Val = Mem.OffsetImm->getValue();
803 return (Val >= 0 && Val < 4096);
805 bool isMemImm12Offset() const {
806 // If we have an immediate that's not a constant, treat it as a label
807 // reference needing a fixup. If it is a constant, it's something else
809 if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
812 if (Kind != Memory || Mem.OffsetRegNum != 0)
814 // Immediate offset in range [-4095, 4095].
815 if (!Mem.OffsetImm) return true;
816 int64_t Val = Mem.OffsetImm->getValue();
817 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
819 bool isPostIdxImm8() const {
820 if (Kind != Immediate)
822 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
823 if (!CE) return false;
824 int64_t Val = CE->getValue();
825 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
828 bool isMSRMask() const { return Kind == MSRMask; }
829 bool isProcIFlags() const { return Kind == ProcIFlags; }
831 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
832 // Add as immediates when possible. Null MCExpr = 0.
834 Inst.addOperand(MCOperand::CreateImm(0));
835 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
836 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
838 Inst.addOperand(MCOperand::CreateExpr(Expr));
841 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
842 assert(N == 2 && "Invalid number of operands!");
843 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
844 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
845 Inst.addOperand(MCOperand::CreateReg(RegNum));
848 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
849 assert(N == 1 && "Invalid number of operands!");
850 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
853 void addITMaskOperands(MCInst &Inst, unsigned N) const {
854 assert(N == 1 && "Invalid number of operands!");
855 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
858 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
859 assert(N == 1 && "Invalid number of operands!");
860 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
863 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
864 assert(N == 1 && "Invalid number of operands!");
865 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
868 void addCCOutOperands(MCInst &Inst, unsigned N) const {
869 assert(N == 1 && "Invalid number of operands!");
870 Inst.addOperand(MCOperand::CreateReg(getReg()));
873 void addRegOperands(MCInst &Inst, unsigned N) const {
874 assert(N == 1 && "Invalid number of operands!");
875 Inst.addOperand(MCOperand::CreateReg(getReg()));
878 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
879 assert(N == 3 && "Invalid number of operands!");
880 assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
881 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
882 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
883 Inst.addOperand(MCOperand::CreateImm(
884 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
887 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
888 assert(N == 2 && "Invalid number of operands!");
889 assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
890 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
891 Inst.addOperand(MCOperand::CreateImm(
892 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
895 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
896 assert(N == 1 && "Invalid number of operands!");
897 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
901 void addRegListOperands(MCInst &Inst, unsigned N) const {
902 assert(N == 1 && "Invalid number of operands!");
903 const SmallVectorImpl<unsigned> &RegList = getRegList();
904 for (SmallVectorImpl<unsigned>::const_iterator
905 I = RegList.begin(), E = RegList.end(); I != E; ++I)
906 Inst.addOperand(MCOperand::CreateReg(*I));
909 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
910 addRegListOperands(Inst, N);
913 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
914 addRegListOperands(Inst, N);
917 void addRotImmOperands(MCInst &Inst, unsigned N) const {
918 assert(N == 1 && "Invalid number of operands!");
919 // Encoded as val>>3. The printer handles display as 8, 16, 24.
920 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
923 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
924 assert(N == 1 && "Invalid number of operands!");
925 // Munge the lsb/width into a bitfield mask.
926 unsigned lsb = Bitfield.LSB;
927 unsigned width = Bitfield.Width;
928 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
929 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
930 (32 - (lsb + width)));
931 Inst.addOperand(MCOperand::CreateImm(Mask));
934 void addImmOperands(MCInst &Inst, unsigned N) const {
935 assert(N == 1 && "Invalid number of operands!");
936 addExpr(Inst, getImm());
939 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
940 assert(N == 1 && "Invalid number of operands!");
941 // FIXME: We really want to scale the value here, but the LDRD/STRD
942 // instruction don't encode operands that way yet.
943 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
944 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
947 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
948 assert(N == 1 && "Invalid number of operands!");
949 // The immediate is scaled by four in the encoding and is stored
950 // in the MCInst as such. Lop off the low two bits here.
951 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
952 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
955 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
956 assert(N == 1 && "Invalid number of operands!");
957 // The immediate is scaled by four in the encoding and is stored
958 // in the MCInst as such. Lop off the low two bits here.
959 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
960 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
963 void addImm0_255Operands(MCInst &Inst, unsigned N) const {
964 assert(N == 1 && "Invalid number of operands!");
965 addExpr(Inst, getImm());
968 void addImm0_7Operands(MCInst &Inst, unsigned N) const {
969 assert(N == 1 && "Invalid number of operands!");
970 addExpr(Inst, getImm());
973 void addImm0_15Operands(MCInst &Inst, unsigned N) const {
974 assert(N == 1 && "Invalid number of operands!");
975 addExpr(Inst, getImm());
978 void addImm0_31Operands(MCInst &Inst, unsigned N) const {
979 assert(N == 1 && "Invalid number of operands!");
980 addExpr(Inst, getImm());
983 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
984 assert(N == 1 && "Invalid number of operands!");
985 // The constant encodes as the immediate-1, and we store in the instruction
986 // the bits as encoded, so subtract off one here.
987 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
988 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
991 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
992 assert(N == 1 && "Invalid number of operands!");
993 // The constant encodes as the immediate-1, and we store in the instruction
994 // the bits as encoded, so subtract off one here.
995 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
996 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
999 void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
1000 assert(N == 1 && "Invalid number of operands!");
1001 addExpr(Inst, getImm());
1004 void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
1005 assert(N == 1 && "Invalid number of operands!");
1006 addExpr(Inst, getImm());
1009 void addImm24bitOperands(MCInst &Inst, unsigned N) const {
1010 assert(N == 1 && "Invalid number of operands!");
1011 addExpr(Inst, getImm());
1014 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1015 assert(N == 1 && "Invalid number of operands!");
1016 // The constant encodes as the immediate, except for 32, which encodes as
1018 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1019 unsigned Imm = CE->getValue();
1020 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1023 void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
1024 assert(N == 1 && "Invalid number of operands!");
1025 addExpr(Inst, getImm());
1028 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1029 assert(N == 1 && "Invalid number of operands!");
1030 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1031 // the instruction as well.
1032 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1033 int Val = CE->getValue();
1034 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1037 void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
1038 assert(N == 1 && "Invalid number of operands!");
1039 addExpr(Inst, getImm());
1042 void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
1043 assert(N == 1 && "Invalid number of operands!");
1044 addExpr(Inst, getImm());
1047 void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
1048 assert(N == 1 && "Invalid number of operands!");
1049 addExpr(Inst, getImm());
1052 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1053 assert(N == 1 && "Invalid number of operands!");
1054 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1057 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1058 assert(N == 1 && "Invalid number of operands!");
1059 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1062 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1063 assert(N == 3 && "Invalid number of operands!");
1064 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1065 if (!Mem.OffsetRegNum) {
1066 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1067 // Special case for #-0
1068 if (Val == INT32_MIN) Val = 0;
1069 if (Val < 0) Val = -Val;
1070 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1072 // For register offset, we encode the shift type and negation flag
1074 Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
1075 Mem.ShiftImm, Mem.ShiftType);
1077 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1078 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1079 Inst.addOperand(MCOperand::CreateImm(Val));
1082 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1083 assert(N == 2 && "Invalid number of operands!");
1084 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1085 assert(CE && "non-constant AM2OffsetImm operand!");
1086 int32_t Val = CE->getValue();
1087 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1088 // Special case for #-0
1089 if (Val == INT32_MIN) Val = 0;
1090 if (Val < 0) Val = -Val;
1091 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1092 Inst.addOperand(MCOperand::CreateReg(0));
1093 Inst.addOperand(MCOperand::CreateImm(Val));
1096 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1097 assert(N == 3 && "Invalid number of operands!");
1098 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1099 if (!Mem.OffsetRegNum) {
1100 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1101 // Special case for #-0
1102 if (Val == INT32_MIN) Val = 0;
1103 if (Val < 0) Val = -Val;
1104 Val = ARM_AM::getAM3Opc(AddSub, Val);
1106 // For register offset, we encode the shift type and negation flag
1108 Val = ARM_AM::getAM3Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1110 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1111 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1112 Inst.addOperand(MCOperand::CreateImm(Val));
1115 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1116 assert(N == 2 && "Invalid number of operands!");
1117 if (Kind == PostIndexRegister) {
1119 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1120 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1121 Inst.addOperand(MCOperand::CreateImm(Val));
1126 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1127 int32_t Val = CE->getValue();
1128 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1129 // Special case for #-0
1130 if (Val == INT32_MIN) Val = 0;
1131 if (Val < 0) Val = -Val;
1132 Val = ARM_AM::getAM3Opc(AddSub, Val);
1133 Inst.addOperand(MCOperand::CreateReg(0));
1134 Inst.addOperand(MCOperand::CreateImm(Val));
1137 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1138 assert(N == 2 && "Invalid number of operands!");
1139 // The lower two bits are always zero and as such are not encoded.
1140 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0;
1141 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1142 // Special case for #-0
1143 if (Val == INT32_MIN) Val = 0;
1144 if (Val < 0) Val = -Val;
1145 Val = ARM_AM::getAM5Opc(AddSub, Val);
1146 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1147 Inst.addOperand(MCOperand::CreateImm(Val));
1150 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1151 assert(N == 2 && "Invalid number of operands!");
1152 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1153 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1154 Inst.addOperand(MCOperand::CreateImm(Val));
1157 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1158 assert(N == 2 && "Invalid number of operands!");
1159 // The lower two bits are always zero and as such are not encoded.
1160 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0;
1161 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1162 Inst.addOperand(MCOperand::CreateImm(Val));
1165 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1166 assert(N == 2 && "Invalid number of operands!");
1167 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1168 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1169 Inst.addOperand(MCOperand::CreateImm(Val));
1172 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1173 addMemImm8OffsetOperands(Inst, N);
1176 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1177 addMemImm8OffsetOperands(Inst, N);
1180 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1181 assert(N == 2 && "Invalid number of operands!");
1182 // If this is an immediate, it's a label reference.
1183 if (Kind == Immediate) {
1184 addExpr(Inst, getImm());
1185 Inst.addOperand(MCOperand::CreateImm(0));
1189 // Otherwise, it's a normal memory reg+offset.
1190 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1191 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1192 Inst.addOperand(MCOperand::CreateImm(Val));
1195 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1196 assert(N == 2 && "Invalid number of operands!");
1197 // If this is an immediate, it's a label reference.
1198 if (Kind == Immediate) {
1199 addExpr(Inst, getImm());
1200 Inst.addOperand(MCOperand::CreateImm(0));
1204 // Otherwise, it's a normal memory reg+offset.
1205 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1206 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1207 Inst.addOperand(MCOperand::CreateImm(Val));
1210 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1211 assert(N == 3 && "Invalid number of operands!");
1212 unsigned Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
1213 Mem.ShiftImm, Mem.ShiftType);
1214 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1215 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1216 Inst.addOperand(MCOperand::CreateImm(Val));
1219 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1220 assert(N == 3 && "Invalid number of operands!");
1221 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1222 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1223 Inst.addOperand(MCOperand::CreateImm(Mem.ShiftImm));
1226 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1227 assert(N == 2 && "Invalid number of operands!");
1228 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1229 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1232 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1233 assert(N == 2 && "Invalid number of operands!");
1234 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1235 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1236 Inst.addOperand(MCOperand::CreateImm(Val));
1239 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1240 assert(N == 2 && "Invalid number of operands!");
1241 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 2) : 0;
1242 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1243 Inst.addOperand(MCOperand::CreateImm(Val));
1246 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1247 assert(N == 2 && "Invalid number of operands!");
1248 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue()) : 0;
1249 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1250 Inst.addOperand(MCOperand::CreateImm(Val));
1253 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1254 assert(N == 2 && "Invalid number of operands!");
1255 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1256 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1257 Inst.addOperand(MCOperand::CreateImm(Val));
1260 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1261 assert(N == 1 && "Invalid number of operands!");
1262 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1263 assert(CE && "non-constant post-idx-imm8 operand!");
1264 int Imm = CE->getValue();
1265 bool isAdd = Imm >= 0;
1266 if (Imm == INT32_MIN) Imm = 0;
1267 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1268 Inst.addOperand(MCOperand::CreateImm(Imm));
1271 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1272 assert(N == 2 && "Invalid number of operands!");
1273 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1274 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1277 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1278 assert(N == 2 && "Invalid number of operands!");
1279 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1280 // The sign, shift type, and shift amount are encoded in a single operand
1281 // using the AM2 encoding helpers.
1282 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1283 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1284 PostIdxReg.ShiftTy);
1285 Inst.addOperand(MCOperand::CreateImm(Imm));
1288 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1289 assert(N == 1 && "Invalid number of operands!");
1290 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1293 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1294 assert(N == 1 && "Invalid number of operands!");
1295 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1298 virtual void print(raw_ostream &OS) const;
1300 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
1301 ARMOperand *Op = new ARMOperand(ITCondMask);
1302 Op->ITMask.Mask = Mask;
1308 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1309 ARMOperand *Op = new ARMOperand(CondCode);
1316 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1317 ARMOperand *Op = new ARMOperand(CoprocNum);
1318 Op->Cop.Val = CopVal;
1324 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1325 ARMOperand *Op = new ARMOperand(CoprocReg);
1326 Op->Cop.Val = CopVal;
1332 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1333 ARMOperand *Op = new ARMOperand(CCOut);
1334 Op->Reg.RegNum = RegNum;
1340 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1341 ARMOperand *Op = new ARMOperand(Token);
1342 Op->Tok.Data = Str.data();
1343 Op->Tok.Length = Str.size();
1349 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1350 ARMOperand *Op = new ARMOperand(Register);
1351 Op->Reg.RegNum = RegNum;
1357 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1362 ARMOperand *Op = new ARMOperand(ShiftedRegister);
1363 Op->RegShiftedReg.ShiftTy = ShTy;
1364 Op->RegShiftedReg.SrcReg = SrcReg;
1365 Op->RegShiftedReg.ShiftReg = ShiftReg;
1366 Op->RegShiftedReg.ShiftImm = ShiftImm;
1372 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1376 ARMOperand *Op = new ARMOperand(ShiftedImmediate);
1377 Op->RegShiftedImm.ShiftTy = ShTy;
1378 Op->RegShiftedImm.SrcReg = SrcReg;
1379 Op->RegShiftedImm.ShiftImm = ShiftImm;
1385 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1387 ARMOperand *Op = new ARMOperand(ShifterImmediate);
1388 Op->ShifterImm.isASR = isASR;
1389 Op->ShifterImm.Imm = Imm;
1395 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1396 ARMOperand *Op = new ARMOperand(RotateImmediate);
1397 Op->RotImm.Imm = Imm;
1403 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1405 ARMOperand *Op = new ARMOperand(BitfieldDescriptor);
1406 Op->Bitfield.LSB = LSB;
1407 Op->Bitfield.Width = Width;
1414 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1415 SMLoc StartLoc, SMLoc EndLoc) {
1416 KindTy Kind = RegisterList;
1418 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
1419 Kind = DPRRegisterList;
1420 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
1421 contains(Regs.front().first))
1422 Kind = SPRRegisterList;
1424 ARMOperand *Op = new ARMOperand(Kind);
1425 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1426 I = Regs.begin(), E = Regs.end(); I != E; ++I)
1427 Op->Registers.push_back(I->first);
1428 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1429 Op->StartLoc = StartLoc;
1430 Op->EndLoc = EndLoc;
1434 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1435 ARMOperand *Op = new ARMOperand(Immediate);
1442 static ARMOperand *CreateMem(unsigned BaseRegNum,
1443 const MCConstantExpr *OffsetImm,
1444 unsigned OffsetRegNum,
1445 ARM_AM::ShiftOpc ShiftType,
1449 ARMOperand *Op = new ARMOperand(Memory);
1450 Op->Mem.BaseRegNum = BaseRegNum;
1451 Op->Mem.OffsetImm = OffsetImm;
1452 Op->Mem.OffsetRegNum = OffsetRegNum;
1453 Op->Mem.ShiftType = ShiftType;
1454 Op->Mem.ShiftImm = ShiftImm;
1455 Op->Mem.isNegative = isNegative;
1461 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1462 ARM_AM::ShiftOpc ShiftTy,
1465 ARMOperand *Op = new ARMOperand(PostIndexRegister);
1466 Op->PostIdxReg.RegNum = RegNum;
1467 Op->PostIdxReg.isAdd = isAdd;
1468 Op->PostIdxReg.ShiftTy = ShiftTy;
1469 Op->PostIdxReg.ShiftImm = ShiftImm;
1475 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1476 ARMOperand *Op = new ARMOperand(MemBarrierOpt);
1477 Op->MBOpt.Val = Opt;
1483 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1484 ARMOperand *Op = new ARMOperand(ProcIFlags);
1485 Op->IFlags.Val = IFlags;
1491 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1492 ARMOperand *Op = new ARMOperand(MSRMask);
1493 Op->MMask.Val = MMask;
1500 } // end anonymous namespace.
1502 void ARMOperand::print(raw_ostream &OS) const {
1505 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1508 OS << "<ccout " << getReg() << ">";
1511 static char MaskStr[][6] = { "()", "(t)", "(e)", "(tt)", "(et)", "(te)",
1512 "(ee)", "(ttt)", "(ett)", "(tet)", "(eet)", "(tte)", "(ete)",
1514 assert((ITMask.Mask & 0xf) == ITMask.Mask);
1515 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
1519 OS << "<coprocessor number: " << getCoproc() << ">";
1522 OS << "<coprocessor register: " << getCoproc() << ">";
1525 OS << "<mask: " << getMSRMask() << ">";
1528 getImm()->print(OS);
1531 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1535 << " base:" << Mem.BaseRegNum;
1538 case PostIndexRegister:
1539 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
1540 << PostIdxReg.RegNum;
1541 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1542 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1543 << PostIdxReg.ShiftImm;
1547 OS << "<ARM_PROC::";
1548 unsigned IFlags = getProcIFlags();
1549 for (int i=2; i >= 0; --i)
1550 if (IFlags & (1 << i))
1551 OS << ARM_PROC::IFlagsToString(1 << i);
1556 OS << "<register " << getReg() << ">";
1558 case ShifterImmediate:
1559 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1560 << " #" << ShifterImm.Imm << ">";
1562 case ShiftedRegister:
1563 OS << "<so_reg_reg "
1564 << RegShiftedReg.SrcReg
1565 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1566 << ", " << RegShiftedReg.ShiftReg << ", "
1567 << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1570 case ShiftedImmediate:
1571 OS << "<so_reg_imm "
1572 << RegShiftedImm.SrcReg
1573 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1574 << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
1577 case RotateImmediate:
1578 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
1580 case BitfieldDescriptor:
1581 OS << "<bitfield " << "lsb: " << Bitfield.LSB
1582 << ", width: " << Bitfield.Width << ">";
1585 case DPRRegisterList:
1586 case SPRRegisterList: {
1587 OS << "<register_list ";
1589 const SmallVectorImpl<unsigned> &RegList = getRegList();
1590 for (SmallVectorImpl<unsigned>::const_iterator
1591 I = RegList.begin(), E = RegList.end(); I != E; ) {
1593 if (++I < E) OS << ", ";
1600 OS << "'" << getToken() << "'";
1605 /// @name Auto-generated Match Functions
1608 static unsigned MatchRegisterName(StringRef Name);
1612 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
1613 SMLoc &StartLoc, SMLoc &EndLoc) {
1614 RegNo = tryParseRegister();
1616 return (RegNo == (unsigned)-1);
1619 /// Try to parse a register name. The token must be an Identifier when called,
1620 /// and if it is a register name the token is eaten and the register number is
1621 /// returned. Otherwise return -1.
1623 int ARMAsmParser::tryParseRegister() {
1624 const AsmToken &Tok = Parser.getTok();
1625 if (Tok.isNot(AsmToken::Identifier)) return -1;
1627 // FIXME: Validate register for the current architecture; we have to do
1628 // validation later, so maybe there is no need for this here.
1629 std::string upperCase = Tok.getString().str();
1630 std::string lowerCase = LowercaseString(upperCase);
1631 unsigned RegNum = MatchRegisterName(lowerCase);
1633 RegNum = StringSwitch<unsigned>(lowerCase)
1634 .Case("r13", ARM::SP)
1635 .Case("r14", ARM::LR)
1636 .Case("r15", ARM::PC)
1637 .Case("ip", ARM::R12)
1640 if (!RegNum) return -1;
1642 Parser.Lex(); // Eat identifier token.
1646 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
1647 // If a recoverable error occurs, return 1. If an irrecoverable error
1648 // occurs, return -1. An irrecoverable error is one where tokens have been
1649 // consumed in the process of trying to parse the shifter (i.e., when it is
1650 // indeed a shifter operand, but malformed).
1651 int ARMAsmParser::tryParseShiftRegister(
1652 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1653 SMLoc S = Parser.getTok().getLoc();
1654 const AsmToken &Tok = Parser.getTok();
1655 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1657 std::string upperCase = Tok.getString().str();
1658 std::string lowerCase = LowercaseString(upperCase);
1659 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
1660 .Case("lsl", ARM_AM::lsl)
1661 .Case("lsr", ARM_AM::lsr)
1662 .Case("asr", ARM_AM::asr)
1663 .Case("ror", ARM_AM::ror)
1664 .Case("rrx", ARM_AM::rrx)
1665 .Default(ARM_AM::no_shift);
1667 if (ShiftTy == ARM_AM::no_shift)
1670 Parser.Lex(); // Eat the operator.
1672 // The source register for the shift has already been added to the
1673 // operand list, so we need to pop it off and combine it into the shifted
1674 // register operand instead.
1675 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
1676 if (!PrevOp->isReg())
1677 return Error(PrevOp->getStartLoc(), "shift must be of a register");
1678 int SrcReg = PrevOp->getReg();
1681 if (ShiftTy == ARM_AM::rrx) {
1682 // RRX Doesn't have an explicit shift amount. The encoder expects
1683 // the shift register to be the same as the source register. Seems odd,
1687 // Figure out if this is shifted by a constant or a register (for non-RRX).
1688 if (Parser.getTok().is(AsmToken::Hash)) {
1689 Parser.Lex(); // Eat hash.
1690 SMLoc ImmLoc = Parser.getTok().getLoc();
1691 const MCExpr *ShiftExpr = 0;
1692 if (getParser().ParseExpression(ShiftExpr)) {
1693 Error(ImmLoc, "invalid immediate shift value");
1696 // The expression must be evaluatable as an immediate.
1697 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
1699 Error(ImmLoc, "invalid immediate shift value");
1702 // Range check the immediate.
1703 // lsl, ror: 0 <= imm <= 31
1704 // lsr, asr: 0 <= imm <= 32
1705 Imm = CE->getValue();
1707 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
1708 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
1709 Error(ImmLoc, "immediate shift value out of range");
1712 } else if (Parser.getTok().is(AsmToken::Identifier)) {
1713 ShiftReg = tryParseRegister();
1714 SMLoc L = Parser.getTok().getLoc();
1715 if (ShiftReg == -1) {
1716 Error (L, "expected immediate or register in shift operand");
1720 Error (Parser.getTok().getLoc(),
1721 "expected immediate or register in shift operand");
1726 if (ShiftReg && ShiftTy != ARM_AM::rrx)
1727 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
1729 S, Parser.getTok().getLoc()));
1731 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
1732 S, Parser.getTok().getLoc()));
1738 /// Try to parse a register name. The token must be an Identifier when called.
1739 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
1740 /// if there is a "writeback". 'true' if it's not a register.
1742 /// TODO this is likely to change to allow different register types and or to
1743 /// parse for a specific register type.
1745 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1746 SMLoc S = Parser.getTok().getLoc();
1747 int RegNo = tryParseRegister();
1751 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1753 const AsmToken &ExclaimTok = Parser.getTok();
1754 if (ExclaimTok.is(AsmToken::Exclaim)) {
1755 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
1756 ExclaimTok.getLoc()));
1757 Parser.Lex(); // Eat exclaim token
1763 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
1764 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
1766 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
1767 // Use the same layout as the tablegen'erated register name matcher. Ugly,
1769 switch (Name.size()) {
1772 if (Name[0] != CoprocOp)
1789 if (Name[0] != CoprocOp || Name[1] != '1')
1793 case '0': return 10;
1794 case '1': return 11;
1795 case '2': return 12;
1796 case '3': return 13;
1797 case '4': return 14;
1798 case '5': return 15;
1806 /// parseITCondCode - Try to parse a condition code for an IT instruction.
1807 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1808 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1809 SMLoc S = Parser.getTok().getLoc();
1810 const AsmToken &Tok = Parser.getTok();
1811 if (!Tok.is(AsmToken::Identifier))
1812 return MatchOperand_NoMatch;
1813 unsigned CC = StringSwitch<unsigned>(Tok.getString())
1814 .Case("eq", ARMCC::EQ)
1815 .Case("ne", ARMCC::NE)
1816 .Case("hs", ARMCC::HS)
1817 .Case("cs", ARMCC::HS)
1818 .Case("lo", ARMCC::LO)
1819 .Case("cc", ARMCC::LO)
1820 .Case("mi", ARMCC::MI)
1821 .Case("pl", ARMCC::PL)
1822 .Case("vs", ARMCC::VS)
1823 .Case("vc", ARMCC::VC)
1824 .Case("hi", ARMCC::HI)
1825 .Case("ls", ARMCC::LS)
1826 .Case("ge", ARMCC::GE)
1827 .Case("lt", ARMCC::LT)
1828 .Case("gt", ARMCC::GT)
1829 .Case("le", ARMCC::LE)
1830 .Case("al", ARMCC::AL)
1833 return MatchOperand_NoMatch;
1834 Parser.Lex(); // Eat the token.
1836 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
1838 return MatchOperand_Success;
1841 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
1842 /// token must be an Identifier when called, and if it is a coprocessor
1843 /// number, the token is eaten and the operand is added to the operand list.
1844 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1845 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1846 SMLoc S = Parser.getTok().getLoc();
1847 const AsmToken &Tok = Parser.getTok();
1848 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1850 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
1852 return MatchOperand_NoMatch;
1854 Parser.Lex(); // Eat identifier token.
1855 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
1856 return MatchOperand_Success;
1859 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
1860 /// token must be an Identifier when called, and if it is a coprocessor
1861 /// number, the token is eaten and the operand is added to the operand list.
1862 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1863 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1864 SMLoc S = Parser.getTok().getLoc();
1865 const AsmToken &Tok = Parser.getTok();
1866 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1868 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
1870 return MatchOperand_NoMatch;
1872 Parser.Lex(); // Eat identifier token.
1873 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
1874 return MatchOperand_Success;
1877 // For register list parsing, we need to map from raw GPR register numbering
1878 // to the enumeration values. The enumeration values aren't sorted by
1879 // register number due to our using "sp", "lr" and "pc" as canonical names.
1880 static unsigned getNextRegister(unsigned Reg) {
1881 // If this is a GPR, we need to do it manually, otherwise we can rely
1882 // on the sort ordering of the enumeration since the other reg-classes
1884 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
1887 default: assert(0 && "Invalid GPR number!");
1888 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
1889 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
1890 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
1891 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
1892 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
1893 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
1894 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
1895 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
1899 /// Parse a register list.
1901 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1902 assert(Parser.getTok().is(AsmToken::LCurly) &&
1903 "Token is not a Left Curly Brace");
1904 SMLoc S = Parser.getTok().getLoc();
1905 Parser.Lex(); // Eat '{' token.
1906 SMLoc RegLoc = Parser.getTok().getLoc();
1908 // Check the first register in the list to see what register class
1909 // this is a list of.
1910 int Reg = tryParseRegister();
1912 return Error(RegLoc, "register expected");
1914 MCRegisterClass *RC;
1915 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
1916 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
1917 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
1918 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
1919 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
1920 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
1922 return Error(RegLoc, "invalid register in register list");
1924 // The reglist instructions have at most 16 registers, so reserve
1925 // space for that many.
1926 SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
1927 // Store the first register.
1928 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
1930 // This starts immediately after the first register token in the list,
1931 // so we can see either a comma or a minus (range separator) as a legal
1933 while (Parser.getTok().is(AsmToken::Comma) ||
1934 Parser.getTok().is(AsmToken::Minus)) {
1935 if (Parser.getTok().is(AsmToken::Minus)) {
1936 Parser.Lex(); // Eat the comma.
1937 SMLoc EndLoc = Parser.getTok().getLoc();
1938 int EndReg = tryParseRegister();
1940 return Error(EndLoc, "register expected");
1941 // If the register is the same as the start reg, there's nothing
1945 // The register must be in the same register class as the first.
1946 if (!RC->contains(EndReg))
1947 return Error(EndLoc, "invalid register in register list");
1948 // Ranges must go from low to high.
1949 if (getARMRegisterNumbering(Reg) > getARMRegisterNumbering(EndReg))
1950 return Error(EndLoc, "bad range in register list");
1952 // Add all the registers in the range to the register list.
1953 while (Reg != EndReg) {
1954 Reg = getNextRegister(Reg);
1955 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
1959 Parser.Lex(); // Eat the comma.
1960 RegLoc = Parser.getTok().getLoc();
1962 Reg = tryParseRegister();
1964 return Error(RegLoc, "register expected");
1965 // The register must be in the same register class as the first.
1966 if (!RC->contains(Reg))
1967 return Error(RegLoc, "invalid register in register list");
1968 // List must be monotonically increasing.
1969 if (getARMRegisterNumbering(Reg) <= getARMRegisterNumbering(OldReg))
1970 return Error(RegLoc, "register list not in ascending order");
1971 // VFP register lists must also be contiguous.
1972 // It's OK to use the enumeration values directly here rather, as the
1973 // VFP register classes have the enum sorted properly.
1974 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
1976 return Error(RegLoc, "non-contiguous register range");
1977 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
1980 SMLoc E = Parser.getTok().getLoc();
1981 if (Parser.getTok().isNot(AsmToken::RCurly))
1982 return Error(E, "'}' expected");
1983 Parser.Lex(); // Eat '}' token.
1985 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
1989 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
1990 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1991 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1992 SMLoc S = Parser.getTok().getLoc();
1993 const AsmToken &Tok = Parser.getTok();
1994 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1995 StringRef OptStr = Tok.getString();
1997 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
1998 .Case("sy", ARM_MB::SY)
1999 .Case("st", ARM_MB::ST)
2000 .Case("sh", ARM_MB::ISH)
2001 .Case("ish", ARM_MB::ISH)
2002 .Case("shst", ARM_MB::ISHST)
2003 .Case("ishst", ARM_MB::ISHST)
2004 .Case("nsh", ARM_MB::NSH)
2005 .Case("un", ARM_MB::NSH)
2006 .Case("nshst", ARM_MB::NSHST)
2007 .Case("unst", ARM_MB::NSHST)
2008 .Case("osh", ARM_MB::OSH)
2009 .Case("oshst", ARM_MB::OSHST)
2013 return MatchOperand_NoMatch;
2015 Parser.Lex(); // Eat identifier token.
2016 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
2017 return MatchOperand_Success;
2020 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
2021 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2022 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2023 SMLoc S = Parser.getTok().getLoc();
2024 const AsmToken &Tok = Parser.getTok();
2025 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2026 StringRef IFlagsStr = Tok.getString();
2028 unsigned IFlags = 0;
2029 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
2030 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
2031 .Case("a", ARM_PROC::A)
2032 .Case("i", ARM_PROC::I)
2033 .Case("f", ARM_PROC::F)
2036 // If some specific iflag is already set, it means that some letter is
2037 // present more than once, this is not acceptable.
2038 if (Flag == ~0U || (IFlags & Flag))
2039 return MatchOperand_NoMatch;
2044 Parser.Lex(); // Eat identifier token.
2045 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
2046 return MatchOperand_Success;
2049 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
2050 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2051 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2052 SMLoc S = Parser.getTok().getLoc();
2053 const AsmToken &Tok = Parser.getTok();
2054 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2055 StringRef Mask = Tok.getString();
2057 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
2058 size_t Start = 0, Next = Mask.find('_');
2059 StringRef Flags = "";
2060 std::string SpecReg = LowercaseString(Mask.slice(Start, Next));
2061 if (Next != StringRef::npos)
2062 Flags = Mask.slice(Next+1, Mask.size());
2064 // FlagsVal contains the complete mask:
2066 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
2067 unsigned FlagsVal = 0;
2069 if (SpecReg == "apsr") {
2070 FlagsVal = StringSwitch<unsigned>(Flags)
2071 .Case("nzcvq", 0x8) // same as CPSR_f
2072 .Case("g", 0x4) // same as CPSR_s
2073 .Case("nzcvqg", 0xc) // same as CPSR_fs
2076 if (FlagsVal == ~0U) {
2078 return MatchOperand_NoMatch;
2080 FlagsVal = 8; // No flag
2082 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
2083 if (Flags == "all") // cpsr_all is an alias for cpsr_fc
2085 for (int i = 0, e = Flags.size(); i != e; ++i) {
2086 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
2093 // If some specific flag is already set, it means that some letter is
2094 // present more than once, this is not acceptable.
2095 if (FlagsVal == ~0U || (FlagsVal & Flag))
2096 return MatchOperand_NoMatch;
2099 } else // No match for special register.
2100 return MatchOperand_NoMatch;
2102 // Special register without flags are equivalent to "fc" flags.
2106 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
2107 if (SpecReg == "spsr")
2110 Parser.Lex(); // Eat identifier token.
2111 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
2112 return MatchOperand_Success;
2115 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2116 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
2117 int Low, int High) {
2118 const AsmToken &Tok = Parser.getTok();
2119 if (Tok.isNot(AsmToken::Identifier)) {
2120 Error(Parser.getTok().getLoc(), Op + " operand expected.");
2121 return MatchOperand_ParseFail;
2123 StringRef ShiftName = Tok.getString();
2124 std::string LowerOp = LowercaseString(Op);
2125 std::string UpperOp = UppercaseString(Op);
2126 if (ShiftName != LowerOp && ShiftName != UpperOp) {
2127 Error(Parser.getTok().getLoc(), Op + " operand expected.");
2128 return MatchOperand_ParseFail;
2130 Parser.Lex(); // Eat shift type token.
2132 // There must be a '#' and a shift amount.
2133 if (Parser.getTok().isNot(AsmToken::Hash)) {
2134 Error(Parser.getTok().getLoc(), "'#' expected");
2135 return MatchOperand_ParseFail;
2137 Parser.Lex(); // Eat hash token.
2139 const MCExpr *ShiftAmount;
2140 SMLoc Loc = Parser.getTok().getLoc();
2141 if (getParser().ParseExpression(ShiftAmount)) {
2142 Error(Loc, "illegal expression");
2143 return MatchOperand_ParseFail;
2145 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2147 Error(Loc, "constant expression expected");
2148 return MatchOperand_ParseFail;
2150 int Val = CE->getValue();
2151 if (Val < Low || Val > High) {
2152 Error(Loc, "immediate value out of range");
2153 return MatchOperand_ParseFail;
2156 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
2158 return MatchOperand_Success;
2161 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2162 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2163 const AsmToken &Tok = Parser.getTok();
2164 SMLoc S = Tok.getLoc();
2165 if (Tok.isNot(AsmToken::Identifier)) {
2166 Error(Tok.getLoc(), "'be' or 'le' operand expected");
2167 return MatchOperand_ParseFail;
2169 int Val = StringSwitch<int>(Tok.getString())
2173 Parser.Lex(); // Eat the token.
2176 Error(Tok.getLoc(), "'be' or 'le' operand expected");
2177 return MatchOperand_ParseFail;
2179 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
2181 S, Parser.getTok().getLoc()));
2182 return MatchOperand_Success;
2185 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
2186 /// instructions. Legal values are:
2187 /// lsl #n 'n' in [0,31]
2188 /// asr #n 'n' in [1,32]
2189 /// n == 32 encoded as n == 0.
2190 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2191 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2192 const AsmToken &Tok = Parser.getTok();
2193 SMLoc S = Tok.getLoc();
2194 if (Tok.isNot(AsmToken::Identifier)) {
2195 Error(S, "shift operator 'asr' or 'lsl' expected");
2196 return MatchOperand_ParseFail;
2198 StringRef ShiftName = Tok.getString();
2200 if (ShiftName == "lsl" || ShiftName == "LSL")
2202 else if (ShiftName == "asr" || ShiftName == "ASR")
2205 Error(S, "shift operator 'asr' or 'lsl' expected");
2206 return MatchOperand_ParseFail;
2208 Parser.Lex(); // Eat the operator.
2210 // A '#' and a shift amount.
2211 if (Parser.getTok().isNot(AsmToken::Hash)) {
2212 Error(Parser.getTok().getLoc(), "'#' expected");
2213 return MatchOperand_ParseFail;
2215 Parser.Lex(); // Eat hash token.
2217 const MCExpr *ShiftAmount;
2218 SMLoc E = Parser.getTok().getLoc();
2219 if (getParser().ParseExpression(ShiftAmount)) {
2220 Error(E, "malformed shift expression");
2221 return MatchOperand_ParseFail;
2223 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2225 Error(E, "shift amount must be an immediate");
2226 return MatchOperand_ParseFail;
2229 int64_t Val = CE->getValue();
2231 // Shift amount must be in [1,32]
2232 if (Val < 1 || Val > 32) {
2233 Error(E, "'asr' shift amount must be in range [1,32]");
2234 return MatchOperand_ParseFail;
2236 // asr #32 encoded as asr #0.
2237 if (Val == 32) Val = 0;
2239 // Shift amount must be in [1,32]
2240 if (Val < 0 || Val > 31) {
2241 Error(E, "'lsr' shift amount must be in range [0,31]");
2242 return MatchOperand_ParseFail;
2246 E = Parser.getTok().getLoc();
2247 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
2249 return MatchOperand_Success;
2252 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
2253 /// of instructions. Legal values are:
2254 /// ror #n 'n' in {0, 8, 16, 24}
2255 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2256 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2257 const AsmToken &Tok = Parser.getTok();
2258 SMLoc S = Tok.getLoc();
2259 if (Tok.isNot(AsmToken::Identifier)) {
2260 Error(S, "rotate operator 'ror' expected");
2261 return MatchOperand_ParseFail;
2263 StringRef ShiftName = Tok.getString();
2264 if (ShiftName != "ror" && ShiftName != "ROR") {
2265 Error(S, "rotate operator 'ror' expected");
2266 return MatchOperand_ParseFail;
2268 Parser.Lex(); // Eat the operator.
2270 // A '#' and a rotate amount.
2271 if (Parser.getTok().isNot(AsmToken::Hash)) {
2272 Error(Parser.getTok().getLoc(), "'#' expected");
2273 return MatchOperand_ParseFail;
2275 Parser.Lex(); // Eat hash token.
2277 const MCExpr *ShiftAmount;
2278 SMLoc E = Parser.getTok().getLoc();
2279 if (getParser().ParseExpression(ShiftAmount)) {
2280 Error(E, "malformed rotate expression");
2281 return MatchOperand_ParseFail;
2283 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2285 Error(E, "rotate amount must be an immediate");
2286 return MatchOperand_ParseFail;
2289 int64_t Val = CE->getValue();
2290 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
2291 // normally, zero is represented in asm by omitting the rotate operand
2293 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
2294 Error(E, "'ror' rotate amount must be 8, 16, or 24");
2295 return MatchOperand_ParseFail;
2298 E = Parser.getTok().getLoc();
2299 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
2301 return MatchOperand_Success;
2304 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2305 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2306 SMLoc S = Parser.getTok().getLoc();
2307 // The bitfield descriptor is really two operands, the LSB and the width.
2308 if (Parser.getTok().isNot(AsmToken::Hash)) {
2309 Error(Parser.getTok().getLoc(), "'#' expected");
2310 return MatchOperand_ParseFail;
2312 Parser.Lex(); // Eat hash token.
2314 const MCExpr *LSBExpr;
2315 SMLoc E = Parser.getTok().getLoc();
2316 if (getParser().ParseExpression(LSBExpr)) {
2317 Error(E, "malformed immediate expression");
2318 return MatchOperand_ParseFail;
2320 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
2322 Error(E, "'lsb' operand must be an immediate");
2323 return MatchOperand_ParseFail;
2326 int64_t LSB = CE->getValue();
2327 // The LSB must be in the range [0,31]
2328 if (LSB < 0 || LSB > 31) {
2329 Error(E, "'lsb' operand must be in the range [0,31]");
2330 return MatchOperand_ParseFail;
2332 E = Parser.getTok().getLoc();
2334 // Expect another immediate operand.
2335 if (Parser.getTok().isNot(AsmToken::Comma)) {
2336 Error(Parser.getTok().getLoc(), "too few operands");
2337 return MatchOperand_ParseFail;
2339 Parser.Lex(); // Eat hash token.
2340 if (Parser.getTok().isNot(AsmToken::Hash)) {
2341 Error(Parser.getTok().getLoc(), "'#' expected");
2342 return MatchOperand_ParseFail;
2344 Parser.Lex(); // Eat hash token.
2346 const MCExpr *WidthExpr;
2347 if (getParser().ParseExpression(WidthExpr)) {
2348 Error(E, "malformed immediate expression");
2349 return MatchOperand_ParseFail;
2351 CE = dyn_cast<MCConstantExpr>(WidthExpr);
2353 Error(E, "'width' operand must be an immediate");
2354 return MatchOperand_ParseFail;
2357 int64_t Width = CE->getValue();
2358 // The LSB must be in the range [1,32-lsb]
2359 if (Width < 1 || Width > 32 - LSB) {
2360 Error(E, "'width' operand must be in the range [1,32-lsb]");
2361 return MatchOperand_ParseFail;
2363 E = Parser.getTok().getLoc();
2365 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
2367 return MatchOperand_Success;
2370 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2371 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2372 // Check for a post-index addressing register operand. Specifically:
2373 // postidx_reg := '+' register {, shift}
2374 // | '-' register {, shift}
2375 // | register {, shift}
2377 // This method must return MatchOperand_NoMatch without consuming any tokens
2378 // in the case where there is no match, as other alternatives take other
2380 AsmToken Tok = Parser.getTok();
2381 SMLoc S = Tok.getLoc();
2382 bool haveEaten = false;
2385 if (Tok.is(AsmToken::Plus)) {
2386 Parser.Lex(); // Eat the '+' token.
2388 } else if (Tok.is(AsmToken::Minus)) {
2389 Parser.Lex(); // Eat the '-' token.
2393 if (Parser.getTok().is(AsmToken::Identifier))
2394 Reg = tryParseRegister();
2397 return MatchOperand_NoMatch;
2398 Error(Parser.getTok().getLoc(), "register expected");
2399 return MatchOperand_ParseFail;
2401 SMLoc E = Parser.getTok().getLoc();
2403 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
2404 unsigned ShiftImm = 0;
2405 if (Parser.getTok().is(AsmToken::Comma)) {
2406 Parser.Lex(); // Eat the ','.
2407 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
2408 return MatchOperand_ParseFail;
2411 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
2414 return MatchOperand_Success;
2417 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2418 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2419 // Check for a post-index addressing register operand. Specifically:
2420 // am3offset := '+' register
2427 // This method must return MatchOperand_NoMatch without consuming any tokens
2428 // in the case where there is no match, as other alternatives take other
2430 AsmToken Tok = Parser.getTok();
2431 SMLoc S = Tok.getLoc();
2433 // Do immediates first, as we always parse those if we have a '#'.
2434 if (Parser.getTok().is(AsmToken::Hash)) {
2435 Parser.Lex(); // Eat the '#'.
2436 // Explicitly look for a '-', as we need to encode negative zero
2438 bool isNegative = Parser.getTok().is(AsmToken::Minus);
2439 const MCExpr *Offset;
2440 if (getParser().ParseExpression(Offset))
2441 return MatchOperand_ParseFail;
2442 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2444 Error(S, "constant expression expected");
2445 return MatchOperand_ParseFail;
2447 SMLoc E = Tok.getLoc();
2448 // Negative zero is encoded as the flag value INT32_MIN.
2449 int32_t Val = CE->getValue();
2450 if (isNegative && Val == 0)
2454 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
2456 return MatchOperand_Success;
2460 bool haveEaten = false;
2463 if (Tok.is(AsmToken::Plus)) {
2464 Parser.Lex(); // Eat the '+' token.
2466 } else if (Tok.is(AsmToken::Minus)) {
2467 Parser.Lex(); // Eat the '-' token.
2471 if (Parser.getTok().is(AsmToken::Identifier))
2472 Reg = tryParseRegister();
2475 return MatchOperand_NoMatch;
2476 Error(Parser.getTok().getLoc(), "register expected");
2477 return MatchOperand_ParseFail;
2479 SMLoc E = Parser.getTok().getLoc();
2481 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
2484 return MatchOperand_Success;
2487 /// cvtT2LdrdPre - Convert parsed operands to MCInst.
2488 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2489 /// when they refer multiple MIOperands inside a single one.
2491 cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
2492 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2494 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2495 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2496 // Create a writeback register dummy placeholder.
2497 Inst.addOperand(MCOperand::CreateReg(0));
2499 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
2501 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2505 /// cvtT2StrdPre - Convert parsed operands to MCInst.
2506 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2507 /// when they refer multiple MIOperands inside a single one.
2509 cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
2510 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2511 // Create a writeback register dummy placeholder.
2512 Inst.addOperand(MCOperand::CreateReg(0));
2514 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2515 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2517 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
2519 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2523 /// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
2524 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2525 /// when they refer multiple MIOperands inside a single one.
2527 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
2528 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2529 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2531 // Create a writeback register dummy placeholder.
2532 Inst.addOperand(MCOperand::CreateImm(0));
2534 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
2535 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2539 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2540 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2541 /// when they refer multiple MIOperands inside a single one.
2543 cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2544 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2545 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2547 // Create a writeback register dummy placeholder.
2548 Inst.addOperand(MCOperand::CreateImm(0));
2550 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2551 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2555 /// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2556 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2557 /// when they refer multiple MIOperands inside a single one.
2559 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2560 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2561 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2563 // Create a writeback register dummy placeholder.
2564 Inst.addOperand(MCOperand::CreateImm(0));
2566 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2567 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2572 /// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2573 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2574 /// when they refer multiple MIOperands inside a single one.
2576 cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2577 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2578 // Create a writeback register dummy placeholder.
2579 Inst.addOperand(MCOperand::CreateImm(0));
2580 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2581 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2582 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2586 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2587 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2588 /// when they refer multiple MIOperands inside a single one.
2590 cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2591 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2592 // Create a writeback register dummy placeholder.
2593 Inst.addOperand(MCOperand::CreateImm(0));
2594 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2595 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2596 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2600 /// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2601 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2602 /// when they refer multiple MIOperands inside a single one.
2604 cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2605 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2606 // Create a writeback register dummy placeholder.
2607 Inst.addOperand(MCOperand::CreateImm(0));
2608 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2609 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2610 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2614 /// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
2615 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2616 /// when they refer multiple MIOperands inside a single one.
2618 cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2619 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2621 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2622 // Create a writeback register dummy placeholder.
2623 Inst.addOperand(MCOperand::CreateImm(0));
2625 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2627 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2629 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2633 /// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
2634 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2635 /// when they refer multiple MIOperands inside a single one.
2637 cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2638 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2640 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2641 // Create a writeback register dummy placeholder.
2642 Inst.addOperand(MCOperand::CreateImm(0));
2644 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2646 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2648 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2652 /// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
2653 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2654 /// when they refer multiple MIOperands inside a single one.
2656 cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2657 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2658 // Create a writeback register dummy placeholder.
2659 Inst.addOperand(MCOperand::CreateImm(0));
2661 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2663 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2665 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2667 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2671 /// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
2672 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2673 /// when they refer multiple MIOperands inside a single one.
2675 cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2676 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2677 // Create a writeback register dummy placeholder.
2678 Inst.addOperand(MCOperand::CreateImm(0));
2680 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2682 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2684 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2686 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2690 /// cvtLdrdPre - Convert parsed operands to MCInst.
2691 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2692 /// when they refer multiple MIOperands inside a single one.
2694 cvtLdrdPre(MCInst &Inst, unsigned Opcode,
2695 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2697 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2698 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2699 // Create a writeback register dummy placeholder.
2700 Inst.addOperand(MCOperand::CreateImm(0));
2702 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2704 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2708 /// cvtStrdPre - Convert parsed operands to MCInst.
2709 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2710 /// when they refer multiple MIOperands inside a single one.
2712 cvtStrdPre(MCInst &Inst, unsigned Opcode,
2713 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2714 // Create a writeback register dummy placeholder.
2715 Inst.addOperand(MCOperand::CreateImm(0));
2717 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2718 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2720 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2722 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2726 /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2727 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2728 /// when they refer multiple MIOperands inside a single one.
2730 cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2731 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2732 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2733 // Create a writeback register dummy placeholder.
2734 Inst.addOperand(MCOperand::CreateImm(0));
2735 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2736 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2740 /// cvtThumbMultiple- Convert parsed operands to MCInst.
2741 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2742 /// when they refer multiple MIOperands inside a single one.
2744 cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
2745 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2746 // The second source operand must be the same register as the destination
2748 if (Operands.size() == 6 &&
2749 (((ARMOperand*)Operands[3])->getReg() !=
2750 ((ARMOperand*)Operands[5])->getReg()) &&
2751 (((ARMOperand*)Operands[3])->getReg() !=
2752 ((ARMOperand*)Operands[4])->getReg())) {
2753 Error(Operands[3]->getStartLoc(),
2754 "destination register must match source register");
2757 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2758 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
2759 ((ARMOperand*)Operands[4])->addRegOperands(Inst, 1);
2760 // If we have a three-operand form, use that, else the second source operand
2761 // is just the destination operand again.
2762 if (Operands.size() == 6)
2763 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
2765 Inst.addOperand(Inst.getOperand(0));
2766 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
2771 /// Parse an ARM memory expression, return false if successful else return true
2772 /// or an error. The first token must be a '[' when called.
2774 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2776 assert(Parser.getTok().is(AsmToken::LBrac) &&
2777 "Token is not a Left Bracket");
2778 S = Parser.getTok().getLoc();
2779 Parser.Lex(); // Eat left bracket token.
2781 const AsmToken &BaseRegTok = Parser.getTok();
2782 int BaseRegNum = tryParseRegister();
2783 if (BaseRegNum == -1)
2784 return Error(BaseRegTok.getLoc(), "register expected");
2786 // The next token must either be a comma or a closing bracket.
2787 const AsmToken &Tok = Parser.getTok();
2788 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
2789 return Error(Tok.getLoc(), "malformed memory operand");
2791 if (Tok.is(AsmToken::RBrac)) {
2793 Parser.Lex(); // Eat right bracket token.
2795 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
2801 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
2802 Parser.Lex(); // Eat the comma.
2804 // If we have a '#' it's an immediate offset, else assume it's a register
2806 if (Parser.getTok().is(AsmToken::Hash)) {
2807 Parser.Lex(); // Eat the '#'.
2808 E = Parser.getTok().getLoc();
2810 bool isNegative = getParser().getTok().is(AsmToken::Minus);
2811 const MCExpr *Offset;
2812 if (getParser().ParseExpression(Offset))
2815 // The expression has to be a constant. Memory references with relocations
2816 // don't come through here, as they use the <label> forms of the relevant
2818 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2820 return Error (E, "constant expression expected");
2822 // If the constant was #-0, represent it as INT32_MIN.
2823 int32_t Val = CE->getValue();
2824 if (isNegative && Val == 0)
2825 CE = MCConstantExpr::Create(INT32_MIN, getContext());
2827 // Now we should have the closing ']'
2828 E = Parser.getTok().getLoc();
2829 if (Parser.getTok().isNot(AsmToken::RBrac))
2830 return Error(E, "']' expected");
2831 Parser.Lex(); // Eat right bracket token.
2833 // Don't worry about range checking the value here. That's handled by
2834 // the is*() predicates.
2835 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
2836 ARM_AM::no_shift, 0, false, S,E));
2838 // If there's a pre-indexing writeback marker, '!', just add it as a token
2840 if (Parser.getTok().is(AsmToken::Exclaim)) {
2841 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2842 Parser.Lex(); // Eat the '!'.
2848 // The register offset is optionally preceded by a '+' or '-'
2849 bool isNegative = false;
2850 if (Parser.getTok().is(AsmToken::Minus)) {
2852 Parser.Lex(); // Eat the '-'.
2853 } else if (Parser.getTok().is(AsmToken::Plus)) {
2855 Parser.Lex(); // Eat the '+'.
2858 E = Parser.getTok().getLoc();
2859 int OffsetRegNum = tryParseRegister();
2860 if (OffsetRegNum == -1)
2861 return Error(E, "register expected");
2863 // If there's a shift operator, handle it.
2864 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
2865 unsigned ShiftImm = 0;
2866 if (Parser.getTok().is(AsmToken::Comma)) {
2867 Parser.Lex(); // Eat the ','.
2868 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
2872 // Now we should have the closing ']'
2873 E = Parser.getTok().getLoc();
2874 if (Parser.getTok().isNot(AsmToken::RBrac))
2875 return Error(E, "']' expected");
2876 Parser.Lex(); // Eat right bracket token.
2878 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
2879 ShiftType, ShiftImm, isNegative,
2882 // If there's a pre-indexing writeback marker, '!', just add it as a token
2884 if (Parser.getTok().is(AsmToken::Exclaim)) {
2885 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2886 Parser.Lex(); // Eat the '!'.
2892 /// parseMemRegOffsetShift - one of these two:
2893 /// ( lsl | lsr | asr | ror ) , # shift_amount
2895 /// return true if it parses a shift otherwise it returns false.
2896 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
2898 SMLoc Loc = Parser.getTok().getLoc();
2899 const AsmToken &Tok = Parser.getTok();
2900 if (Tok.isNot(AsmToken::Identifier))
2902 StringRef ShiftName = Tok.getString();
2903 if (ShiftName == "lsl" || ShiftName == "LSL")
2905 else if (ShiftName == "lsr" || ShiftName == "LSR")
2907 else if (ShiftName == "asr" || ShiftName == "ASR")
2909 else if (ShiftName == "ror" || ShiftName == "ROR")
2911 else if (ShiftName == "rrx" || ShiftName == "RRX")
2914 return Error(Loc, "illegal shift operator");
2915 Parser.Lex(); // Eat shift type token.
2917 // rrx stands alone.
2919 if (St != ARM_AM::rrx) {
2920 Loc = Parser.getTok().getLoc();
2921 // A '#' and a shift amount.
2922 const AsmToken &HashTok = Parser.getTok();
2923 if (HashTok.isNot(AsmToken::Hash))
2924 return Error(HashTok.getLoc(), "'#' expected");
2925 Parser.Lex(); // Eat hash token.
2928 if (getParser().ParseExpression(Expr))
2930 // Range check the immediate.
2931 // lsl, ror: 0 <= imm <= 31
2932 // lsr, asr: 0 <= imm <= 32
2933 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2935 return Error(Loc, "shift amount must be an immediate");
2936 int64_t Imm = CE->getValue();
2938 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
2939 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
2940 return Error(Loc, "immediate shift value out of range");
2947 /// Parse a arm instruction operand. For now this parses the operand regardless
2948 /// of the mnemonic.
2949 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2950 StringRef Mnemonic) {
2953 // Check if the current operand has a custom associated parser, if so, try to
2954 // custom parse the operand, or fallback to the general approach.
2955 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
2956 if (ResTy == MatchOperand_Success)
2958 // If there wasn't a custom match, try the generic matcher below. Otherwise,
2959 // there was a match, but an error occurred, in which case, just return that
2960 // the operand parsing failed.
2961 if (ResTy == MatchOperand_ParseFail)
2964 switch (getLexer().getKind()) {
2966 Error(Parser.getTok().getLoc(), "unexpected token in operand");
2968 case AsmToken::Identifier: {
2969 if (!tryParseRegisterWithWriteBack(Operands))
2971 int Res = tryParseShiftRegister(Operands);
2972 if (Res == 0) // success
2974 else if (Res == -1) // irrecoverable error
2977 // Fall though for the Identifier case that is not a register or a
2980 case AsmToken::Integer: // things like 1f and 2b as a branch targets
2981 case AsmToken::Dot: { // . as a branch target
2982 // This was not a register so parse other operands that start with an
2983 // identifier (like labels) as expressions and create them as immediates.
2984 const MCExpr *IdVal;
2985 S = Parser.getTok().getLoc();
2986 if (getParser().ParseExpression(IdVal))
2988 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2989 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
2992 case AsmToken::LBrac:
2993 return parseMemory(Operands);
2994 case AsmToken::LCurly:
2995 return parseRegisterList(Operands);
2996 case AsmToken::Hash: {
2997 // #42 -> immediate.
2998 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
2999 S = Parser.getTok().getLoc();
3001 bool isNegative = Parser.getTok().is(AsmToken::Minus);
3002 const MCExpr *ImmVal;
3003 if (getParser().ParseExpression(ImmVal))
3005 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
3007 Error(S, "constant expression expected");
3008 return MatchOperand_ParseFail;
3010 int32_t Val = CE->getValue();
3011 if (isNegative && Val == 0)
3012 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
3013 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3014 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
3017 case AsmToken::Colon: {
3018 // ":lower16:" and ":upper16:" expression prefixes
3019 // FIXME: Check it's an expression prefix,
3020 // e.g. (FOO - :lower16:BAR) isn't legal.
3021 ARMMCExpr::VariantKind RefKind;
3022 if (parsePrefix(RefKind))
3025 const MCExpr *SubExprVal;
3026 if (getParser().ParseExpression(SubExprVal))
3029 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
3031 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3032 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
3038 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
3039 // :lower16: and :upper16:.
3040 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
3041 RefKind = ARMMCExpr::VK_ARM_None;
3043 // :lower16: and :upper16: modifiers
3044 assert(getLexer().is(AsmToken::Colon) && "expected a :");
3045 Parser.Lex(); // Eat ':'
3047 if (getLexer().isNot(AsmToken::Identifier)) {
3048 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
3052 StringRef IDVal = Parser.getTok().getIdentifier();
3053 if (IDVal == "lower16") {
3054 RefKind = ARMMCExpr::VK_ARM_LO16;
3055 } else if (IDVal == "upper16") {
3056 RefKind = ARMMCExpr::VK_ARM_HI16;
3058 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
3063 if (getLexer().isNot(AsmToken::Colon)) {
3064 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
3067 Parser.Lex(); // Eat the last ':'
3072 ARMAsmParser::applyPrefixToExpr(const MCExpr *E,
3073 MCSymbolRefExpr::VariantKind Variant) {
3074 // Recurse over the given expression, rebuilding it to apply the given variant
3075 // to the leftmost symbol.
3076 if (Variant == MCSymbolRefExpr::VK_None)
3079 switch (E->getKind()) {
3080 case MCExpr::Target:
3081 llvm_unreachable("Can't handle target expr yet");
3082 case MCExpr::Constant:
3083 llvm_unreachable("Can't handle lower16/upper16 of constant yet");
3085 case MCExpr::SymbolRef: {
3086 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
3088 if (SRE->getKind() != MCSymbolRefExpr::VK_None)
3091 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext());
3095 llvm_unreachable("Can't handle unary expressions yet");
3097 case MCExpr::Binary: {
3098 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
3099 const MCExpr *LHS = applyPrefixToExpr(BE->getLHS(), Variant);
3100 const MCExpr *RHS = BE->getRHS();
3104 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext());
3108 assert(0 && "Invalid expression kind!");
3112 /// \brief Given a mnemonic, split out possible predication code and carry
3113 /// setting letters to form a canonical mnemonic and flags.
3115 // FIXME: Would be nice to autogen this.
3116 // FIXME: This is a bit of a maze of special cases.
3117 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
3118 unsigned &PredicationCode,
3120 unsigned &ProcessorIMod,
3121 StringRef &ITMask) {
3122 PredicationCode = ARMCC::AL;
3123 CarrySetting = false;
3126 // Ignore some mnemonics we know aren't predicated forms.
3128 // FIXME: Would be nice to autogen this.
3129 if ((Mnemonic == "movs" && isThumb()) ||
3130 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
3131 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
3132 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
3133 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
3134 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
3135 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
3136 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
3139 // First, split out any predication code. Ignore mnemonics we know aren't
3140 // predicated but do have a carry-set and so weren't caught above.
3141 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
3142 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
3143 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
3144 Mnemonic != "sbcs" && Mnemonic != "rscs") {
3145 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
3146 .Case("eq", ARMCC::EQ)
3147 .Case("ne", ARMCC::NE)
3148 .Case("hs", ARMCC::HS)
3149 .Case("cs", ARMCC::HS)
3150 .Case("lo", ARMCC::LO)
3151 .Case("cc", ARMCC::LO)
3152 .Case("mi", ARMCC::MI)
3153 .Case("pl", ARMCC::PL)
3154 .Case("vs", ARMCC::VS)
3155 .Case("vc", ARMCC::VC)
3156 .Case("hi", ARMCC::HI)
3157 .Case("ls", ARMCC::LS)
3158 .Case("ge", ARMCC::GE)
3159 .Case("lt", ARMCC::LT)
3160 .Case("gt", ARMCC::GT)
3161 .Case("le", ARMCC::LE)
3162 .Case("al", ARMCC::AL)
3165 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
3166 PredicationCode = CC;
3170 // Next, determine if we have a carry setting bit. We explicitly ignore all
3171 // the instructions we know end in 's'.
3172 if (Mnemonic.endswith("s") &&
3173 !(Mnemonic == "cps" || Mnemonic == "mls" ||
3174 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
3175 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
3176 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
3177 Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
3178 (Mnemonic == "movs" && isThumb()))) {
3179 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
3180 CarrySetting = true;
3183 // The "cps" instruction can have a interrupt mode operand which is glued into
3184 // the mnemonic. Check if this is the case, split it and parse the imod op
3185 if (Mnemonic.startswith("cps")) {
3186 // Split out any imod code.
3188 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
3189 .Case("ie", ARM_PROC::IE)
3190 .Case("id", ARM_PROC::ID)
3193 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
3194 ProcessorIMod = IMod;
3198 // The "it" instruction has the condition mask on the end of the mnemonic.
3199 if (Mnemonic.startswith("it")) {
3200 ITMask = Mnemonic.slice(2, Mnemonic.size());
3201 Mnemonic = Mnemonic.slice(0, 2);
3207 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
3208 /// inclusion of carry set or predication code operands.
3210 // FIXME: It would be nice to autogen this.
3212 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
3213 bool &CanAcceptPredicationCode) {
3214 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
3215 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
3216 Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
3217 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
3218 Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" ||
3219 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
3220 Mnemonic == "sbc" || Mnemonic == "umull" ||
3221 Mnemonic == "eor" || Mnemonic == "smlal" || Mnemonic == "neg" ||
3222 ((Mnemonic == "mov" || Mnemonic == "mla") && !isThumb())) {
3223 CanAcceptCarrySet = true;
3225 CanAcceptCarrySet = false;
3228 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
3229 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
3230 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
3231 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
3232 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
3233 (Mnemonic == "clrex" && !isThumb()) ||
3234 (Mnemonic == "nop" && isThumbOne()) ||
3235 ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw") &&
3237 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
3239 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
3240 CanAcceptPredicationCode = false;
3242 CanAcceptPredicationCode = true;
3246 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
3247 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
3248 CanAcceptPredicationCode = false;
3251 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
3252 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3253 // FIXME: This is all horribly hacky. We really need a better way to deal
3254 // with optional operands like this in the matcher table.
3256 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
3257 // another does not. Specifically, the MOVW instruction does not. So we
3258 // special case it here and remove the defaulted (non-setting) cc_out
3259 // operand if that's the instruction we're trying to match.
3261 // We do this as post-processing of the explicit operands rather than just
3262 // conditionally adding the cc_out in the first place because we need
3263 // to check the type of the parsed immediate operand.
3264 if (Mnemonic == "mov" && Operands.size() > 4 &&
3265 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
3266 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
3267 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3270 // Register-register 'add' for thumb does not have a cc_out operand
3271 // when there are only two register operands.
3272 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
3273 static_cast<ARMOperand*>(Operands[3])->isReg() &&
3274 static_cast<ARMOperand*>(Operands[4])->isReg() &&
3275 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3277 // Register-register 'add' for thumb does not have a cc_out operand
3278 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
3279 // have to check the immediate range here since Thumb2 has a variant
3280 // that can handle a different range and has a cc_out operand.
3281 if (isThumb() && Mnemonic == "add" && Operands.size() == 6 &&
3282 static_cast<ARMOperand*>(Operands[3])->isReg() &&
3283 static_cast<ARMOperand*>(Operands[4])->isReg() &&
3284 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
3285 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
3286 (static_cast<ARMOperand*>(Operands[5])->isReg() ||
3287 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
3289 // For Thumb2, add immediate does not have a cc_out operand for the
3290 // imm0_4096 variant. That's the least-preferred variant when
3291 // selecting via the generic "add" mnemonic, so to know that we
3292 // should remove the cc_out operand, we have to explicitly check that
3293 // it's not one of the other variants. Ugh.
3294 if (isThumbTwo() && Mnemonic == "add" && Operands.size() == 6 &&
3295 static_cast<ARMOperand*>(Operands[3])->isReg() &&
3296 static_cast<ARMOperand*>(Operands[4])->isReg() &&
3297 static_cast<ARMOperand*>(Operands[5])->isImm()) {
3298 // Nest conditions rather than one big 'if' statement for readability.
3300 // If either register is a high reg, it's either one of the SP
3301 // variants (handled above) or a 32-bit encoding, so we just
3302 // check against T3.
3303 if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
3304 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
3305 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
3307 // If both registers are low, we're in an IT block, and the immediate is
3308 // in range, we should use encoding T1 instead, which has a cc_out.
3310 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
3311 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
3312 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
3315 // Otherwise, we use encoding T4, which does not have a cc_out
3321 // Register-register 'add/sub' for thumb does not have a cc_out operand
3322 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
3323 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
3324 // right, this will result in better diagnostics (which operand is off)
3326 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
3327 (Operands.size() == 5 || Operands.size() == 6) &&
3328 static_cast<ARMOperand*>(Operands[3])->isReg() &&
3329 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
3330 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3336 /// Parse an arm instruction mnemonic followed by its operands.
3337 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
3338 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3339 // Create the leading tokens for the mnemonic, split by '.' characters.
3340 size_t Start = 0, Next = Name.find('.');
3341 StringRef Mnemonic = Name.slice(Start, Next);
3343 // Split out the predication code and carry setting flag from the mnemonic.
3344 unsigned PredicationCode;
3345 unsigned ProcessorIMod;
3348 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
3349 ProcessorIMod, ITMask);
3351 // In Thumb1, only the branch (B) instruction can be predicated.
3352 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
3353 Parser.EatToEndOfStatement();
3354 return Error(NameLoc, "conditional execution not supported in Thumb1");
3357 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
3359 // Handle the IT instruction ITMask. Convert it to a bitmask. This
3360 // is the mask as it will be for the IT encoding if the conditional
3361 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
3362 // where the conditional bit0 is zero, the instruction post-processing
3363 // will adjust the mask accordingly.
3364 if (Mnemonic == "it") {
3365 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
3366 if (ITMask.size() > 3) {
3367 Parser.EatToEndOfStatement();
3368 return Error(Loc, "too many conditions on IT instruction");
3371 for (unsigned i = ITMask.size(); i != 0; --i) {
3372 char pos = ITMask[i - 1];
3373 if (pos != 't' && pos != 'e') {
3374 Parser.EatToEndOfStatement();
3375 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
3378 if (ITMask[i - 1] == 't')
3381 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
3384 // FIXME: This is all a pretty gross hack. We should automatically handle
3385 // optional operands like this via tblgen.
3387 // Next, add the CCOut and ConditionCode operands, if needed.
3389 // For mnemonics which can ever incorporate a carry setting bit or predication
3390 // code, our matching model involves us always generating CCOut and
3391 // ConditionCode operands to match the mnemonic "as written" and then we let
3392 // the matcher deal with finding the right instruction or generating an
3393 // appropriate error.
3394 bool CanAcceptCarrySet, CanAcceptPredicationCode;
3395 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
3397 // If we had a carry-set on an instruction that can't do that, issue an
3399 if (!CanAcceptCarrySet && CarrySetting) {
3400 Parser.EatToEndOfStatement();
3401 return Error(NameLoc, "instruction '" + Mnemonic +
3402 "' can not set flags, but 's' suffix specified");
3404 // If we had a predication code on an instruction that can't do that, issue an
3406 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
3407 Parser.EatToEndOfStatement();
3408 return Error(NameLoc, "instruction '" + Mnemonic +
3409 "' is not predicable, but condition code specified");
3412 // Add the carry setting operand, if necessary.
3413 if (CanAcceptCarrySet) {
3414 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
3415 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
3419 // Add the predication code operand, if necessary.
3420 if (CanAcceptPredicationCode) {
3421 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
3423 Operands.push_back(ARMOperand::CreateCondCode(
3424 ARMCC::CondCodes(PredicationCode), Loc));
3427 // Add the processor imod operand, if necessary.
3428 if (ProcessorIMod) {
3429 Operands.push_back(ARMOperand::CreateImm(
3430 MCConstantExpr::Create(ProcessorIMod, getContext()),
3434 // Add the remaining tokens in the mnemonic.
3435 while (Next != StringRef::npos) {
3437 Next = Name.find('.', Start + 1);
3438 StringRef ExtraToken = Name.slice(Start, Next);
3440 // For now, we're only parsing Thumb1 (for the most part), so
3441 // just ignore ".n" qualifiers. We'll use them to restrict
3442 // matching when we do Thumb2.
3443 if (ExtraToken != ".n") {
3444 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
3445 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
3449 // Read the remaining operands.
3450 if (getLexer().isNot(AsmToken::EndOfStatement)) {
3451 // Read the first operand.
3452 if (parseOperand(Operands, Mnemonic)) {
3453 Parser.EatToEndOfStatement();
3457 while (getLexer().is(AsmToken::Comma)) {
3458 Parser.Lex(); // Eat the comma.
3460 // Parse and remember the operand.
3461 if (parseOperand(Operands, Mnemonic)) {
3462 Parser.EatToEndOfStatement();
3468 if (getLexer().isNot(AsmToken::EndOfStatement)) {
3469 Parser.EatToEndOfStatement();
3470 return TokError("unexpected token in argument list");
3473 Parser.Lex(); // Consume the EndOfStatement
3475 // Some instructions, mostly Thumb, have forms for the same mnemonic that
3476 // do and don't have a cc_out optional-def operand. With some spot-checks
3477 // of the operand list, we can figure out which variant we're trying to
3478 // parse and adjust accordingly before actually matching. We shouldn't ever
3479 // try to remove a cc_out operand that was explicitly set on the the
3480 // mnemonic, of course (CarrySetting == true). Reason number #317 the
3481 // table driven matcher doesn't fit well with the ARM instruction set.
3482 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
3483 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3484 Operands.erase(Operands.begin() + 1);
3488 // ARM mode 'blx' need special handling, as the register operand version
3489 // is predicable, but the label operand version is not. So, we can't rely
3490 // on the Mnemonic based checking to correctly figure out when to put
3491 // a CondCode operand in the list. If we're trying to match the label
3492 // version, remove the CondCode operand here.
3493 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
3494 static_cast<ARMOperand*>(Operands[2])->isImm()) {
3495 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3496 Operands.erase(Operands.begin() + 1);
3500 // The vector-compare-to-zero instructions have a literal token "#0" at
3501 // the end that comes to here as an immediate operand. Convert it to a
3502 // token to play nicely with the matcher.
3503 if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
3504 Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
3505 static_cast<ARMOperand*>(Operands[5])->isImm()) {
3506 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
3507 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
3508 if (CE && CE->getValue() == 0) {
3509 Operands.erase(Operands.begin() + 5);
3510 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3514 // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
3515 // end. Convert it to a token here.
3516 if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
3517 static_cast<ARMOperand*>(Operands[5])->isImm()) {
3518 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
3519 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
3520 if (CE && CE->getValue() == 0) {
3521 Operands.erase(Operands.begin() + 5);
3522 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3530 // Validate context-sensitive operand constraints.
3532 // return 'true' if register list contains non-low GPR registers,
3533 // 'false' otherwise. If Reg is in the register list or is HiReg, set
3534 // 'containsReg' to true.
3535 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
3536 unsigned HiReg, bool &containsReg) {
3537 containsReg = false;
3538 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
3539 unsigned OpReg = Inst.getOperand(i).getReg();
3542 // Anything other than a low register isn't legal here.
3543 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
3549 // Check if the specified regisgter is in the register list of the inst,
3550 // starting at the indicated operand number.
3551 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
3552 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
3553 unsigned OpReg = Inst.getOperand(i).getReg();
3560 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around
3561 // the ARMInsts array) instead. Getting that here requires awkward
3562 // API changes, though. Better way?
3564 extern MCInstrDesc ARMInsts[];
3566 static MCInstrDesc &getInstDesc(unsigned Opcode) {
3567 return ARMInsts[Opcode];
3570 // FIXME: We would really like to be able to tablegen'erate this.
3572 validateInstruction(MCInst &Inst,
3573 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3574 MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
3575 SMLoc Loc = Operands[0]->getStartLoc();
3576 // Check the IT block state first.
3577 // NOTE: In Thumb mode, the BKPT instruction has the interesting property of
3578 // being allowed in IT blocks, but not being predicable. It just always
3580 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT) {
3582 if (ITState.FirstCond)
3583 ITState.FirstCond = false;
3585 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
3586 // The instruction must be predicable.
3587 if (!MCID.isPredicable())
3588 return Error(Loc, "instructions in IT block must be predicable");
3589 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
3590 unsigned ITCond = bit ? ITState.Cond :
3591 ARMCC::getOppositeCondition(ITState.Cond);
3592 if (Cond != ITCond) {
3593 // Find the condition code Operand to get its SMLoc information.
3595 for (unsigned i = 1; i < Operands.size(); ++i)
3596 if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
3597 CondLoc = Operands[i]->getStartLoc();
3598 return Error(CondLoc, "incorrect condition in IT block; got '" +
3599 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
3600 "', but expected '" +
3601 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
3603 // Check for non-'al' condition codes outside of the IT block.
3604 } else if (isThumbTwo() && MCID.isPredicable() &&
3605 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
3606 ARMCC::AL && Inst.getOpcode() != ARM::tB &&
3607 Inst.getOpcode() != ARM::t2B)
3608 return Error(Loc, "predicated instructions must be in IT block");
3610 switch (Inst.getOpcode()) {
3613 case ARM::LDRD_POST:
3615 // Rt2 must be Rt + 1.
3616 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3617 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3619 return Error(Operands[3]->getStartLoc(),
3620 "destination operands must be sequential");
3624 // Rt2 must be Rt + 1.
3625 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3626 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3628 return Error(Operands[3]->getStartLoc(),
3629 "source operands must be sequential");
3633 case ARM::STRD_POST:
3635 // Rt2 must be Rt + 1.
3636 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3637 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
3639 return Error(Operands[3]->getStartLoc(),
3640 "source operands must be sequential");
3645 // width must be in range [1, 32-lsb]
3646 unsigned lsb = Inst.getOperand(2).getImm();
3647 unsigned widthm1 = Inst.getOperand(3).getImm();
3648 if (widthm1 >= 32 - lsb)
3649 return Error(Operands[5]->getStartLoc(),
3650 "bitfield width must be in range [1,32-lsb]");
3654 // If we're parsing Thumb2, the .w variant is available and handles
3655 // most cases that are normally illegal for a Thumb1 LDM
3656 // instruction. We'll make the transformation in processInstruction()
3659 // Thumb LDM instructions are writeback iff the base register is not
3660 // in the register list.
3661 unsigned Rn = Inst.getOperand(0).getReg();
3662 bool hasWritebackToken =
3663 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
3664 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
3665 bool listContainsBase;
3666 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
3667 return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
3668 "registers must be in range r0-r7");
3669 // If we should have writeback, then there should be a '!' token.
3670 if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
3671 return Error(Operands[2]->getStartLoc(),
3672 "writeback operator '!' expected");
3673 // If we should not have writeback, there must not be a '!'. This is
3674 // true even for the 32-bit wide encodings.
3675 if (listContainsBase && hasWritebackToken)
3676 return Error(Operands[3]->getStartLoc(),
3677 "writeback operator '!' not allowed when base register "
3678 "in register list");
3682 case ARM::t2LDMIA_UPD: {
3683 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
3684 return Error(Operands[4]->getStartLoc(),
3685 "writeback operator '!' not allowed when base register "
3686 "in register list");
3690 bool listContainsBase;
3691 if (checkLowRegisterList(Inst, 3, 0, ARM::PC, listContainsBase))
3692 return Error(Operands[2]->getStartLoc(),
3693 "registers must be in range r0-r7 or pc");
3697 bool listContainsBase;
3698 if (checkLowRegisterList(Inst, 3, 0, ARM::LR, listContainsBase))
3699 return Error(Operands[2]->getStartLoc(),
3700 "registers must be in range r0-r7 or lr");
3703 case ARM::tSTMIA_UPD: {
3704 bool listContainsBase;
3705 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase))
3706 return Error(Operands[4]->getStartLoc(),
3707 "registers must be in range r0-r7");
3716 processInstruction(MCInst &Inst,
3717 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3718 switch (Inst.getOpcode()) {
3719 case ARM::LDMIA_UPD:
3720 // If this is a load of a single register via a 'pop', then we should use
3721 // a post-indexed LDR instruction instead, per the ARM ARM.
3722 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
3723 Inst.getNumOperands() == 5) {
3725 TmpInst.setOpcode(ARM::LDR_POST_IMM);
3726 TmpInst.addOperand(Inst.getOperand(4)); // Rt
3727 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3728 TmpInst.addOperand(Inst.getOperand(1)); // Rn
3729 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
3730 TmpInst.addOperand(MCOperand::CreateImm(4));
3731 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3732 TmpInst.addOperand(Inst.getOperand(3));
3736 case ARM::STMDB_UPD:
3737 // If this is a store of a single register via a 'push', then we should use
3738 // a pre-indexed STR instruction instead, per the ARM ARM.
3739 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
3740 Inst.getNumOperands() == 5) {
3742 TmpInst.setOpcode(ARM::STR_PRE_IMM);
3743 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3744 TmpInst.addOperand(Inst.getOperand(4)); // Rt
3745 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
3746 TmpInst.addOperand(MCOperand::CreateImm(-4));
3747 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3748 TmpInst.addOperand(Inst.getOperand(3));
3753 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
3754 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
3755 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
3756 // to encoding T1 if <Rd> is omitted."
3757 if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6)
3758 Inst.setOpcode(ARM::tADDi3);
3761 // A Thumb conditional branch outside of an IT block is a tBcc.
3762 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock())
3763 Inst.setOpcode(ARM::tBcc);
3766 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
3767 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock())
3768 Inst.setOpcode(ARM::t2Bcc);
3771 // If the conditional is AL or we're in an IT block, we really want t2B.
3772 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock())
3773 Inst.setOpcode(ARM::t2B);
3776 // If the conditional is AL, we really want tB.
3777 if (Inst.getOperand(1).getImm() == ARMCC::AL)
3778 Inst.setOpcode(ARM::tB);
3781 // If the register list contains any high registers, or if the writeback
3782 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
3783 // instead if we're in Thumb2. Otherwise, this should have generated
3784 // an error in validateInstruction().
3785 unsigned Rn = Inst.getOperand(0).getReg();
3786 bool hasWritebackToken =
3787 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
3788 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
3789 bool listContainsBase;
3790 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
3791 (!listContainsBase && !hasWritebackToken) ||
3792 (listContainsBase && hasWritebackToken)) {
3793 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
3794 assert (isThumbTwo());
3795 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
3796 // If we're switching to the updating version, we need to insert
3797 // the writeback tied operand.
3798 if (hasWritebackToken)
3799 Inst.insert(Inst.begin(),
3800 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
3805 // If we can use the 16-bit encoding and the user didn't explicitly
3806 // request the 32-bit variant, transform it here.
3807 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
3808 Inst.getOperand(1).getImm() <= 255 &&
3809 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
3810 Inst.getOperand(4).getReg() == ARM::CPSR) ||
3811 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
3812 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
3813 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
3814 // The operands aren't in the same order for tMOVi8...
3816 TmpInst.setOpcode(ARM::tMOVi8);
3817 TmpInst.addOperand(Inst.getOperand(0));
3818 TmpInst.addOperand(Inst.getOperand(4));
3819 TmpInst.addOperand(Inst.getOperand(1));
3820 TmpInst.addOperand(Inst.getOperand(2));
3821 TmpInst.addOperand(Inst.getOperand(3));
3827 // If we can use the 16-bit encoding and the user didn't explicitly
3828 // request the 32-bit variant, transform it here.
3829 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
3830 isARMLowRegister(Inst.getOperand(1).getReg()) &&
3831 Inst.getOperand(2).getImm() == ARMCC::AL &&
3832 Inst.getOperand(4).getReg() == ARM::CPSR &&
3833 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
3834 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
3835 // The operands aren't the same for tMOV[S]r... (no cc_out)
3837 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
3838 TmpInst.addOperand(Inst.getOperand(0));
3839 TmpInst.addOperand(Inst.getOperand(1));
3840 TmpInst.addOperand(Inst.getOperand(2));
3841 TmpInst.addOperand(Inst.getOperand(3));
3847 // The mask bits for all but the first condition are represented as
3848 // the low bit of the condition code value implies 't'. We currently
3849 // always have 1 implies 't', so XOR toggle the bits if the low bit
3850 // of the condition code is zero. The encoding also expects the low
3851 // bit of the condition to be encoded as bit 4 of the mask operand,
3852 // so mask that in if needed
3853 MCOperand &MO = Inst.getOperand(1);
3854 unsigned Mask = MO.getImm();
3855 unsigned OrigMask = Mask;
3856 unsigned TZ = CountTrailingZeros_32(Mask);
3857 if ((Inst.getOperand(0).getImm() & 1) == 0) {
3858 assert(Mask && TZ <= 3 && "illegal IT mask value!");
3859 for (unsigned i = 3; i != TZ; --i)
3865 // Set up the IT block state according to the IT instruction we just
3867 assert(!inITBlock() && "nested IT blocks?!");
3868 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
3869 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
3870 ITState.CurPosition = 0;
3871 ITState.FirstCond = true;
3877 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
3878 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
3879 // suffix depending on whether they're in an IT block or not.
3880 unsigned Opc = Inst.getOpcode();
3881 MCInstrDesc &MCID = getInstDesc(Opc);
3882 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
3883 assert(MCID.hasOptionalDef() &&
3884 "optionally flag setting instruction missing optional def operand");
3885 assert(MCID.NumOperands == Inst.getNumOperands() &&
3886 "operand count mismatch!");
3887 // Find the optional-def operand (cc_out).
3890 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
3893 // If we're parsing Thumb1, reject it completely.
3894 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3895 return Match_MnemonicFail;
3896 // If we're parsing Thumb2, which form is legal depends on whether we're
3898 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
3900 return Match_RequiresITBlock;
3901 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
3903 return Match_RequiresNotITBlock;
3905 // Some high-register supporting Thumb1 encodings only allow both registers
3906 // to be from r0-r7 when in Thumb2.
3907 else if (Opc == ARM::tADDhirr && isThumbOne() &&
3908 isARMLowRegister(Inst.getOperand(1).getReg()) &&
3909 isARMLowRegister(Inst.getOperand(2).getReg()))
3910 return Match_RequiresThumb2;
3911 // Others only require ARMv6 or later.
3912 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
3913 isARMLowRegister(Inst.getOperand(0).getReg()) &&
3914 isARMLowRegister(Inst.getOperand(1).getReg()))
3915 return Match_RequiresV6;
3916 return Match_Success;
3920 MatchAndEmitInstruction(SMLoc IDLoc,
3921 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
3925 unsigned MatchResult;
3926 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
3927 switch (MatchResult) {
3930 // Context sensitive operand constraints aren't handled by the matcher,
3931 // so check them here.
3932 if (validateInstruction(Inst, Operands)) {
3933 // Still progress the IT block, otherwise one wrong condition causes
3934 // nasty cascading errors.
3935 forwardITPosition();
3939 // Some instructions need post-processing to, for example, tweak which
3940 // encoding is selected.
3941 processInstruction(Inst, Operands);
3943 // Only move forward at the very end so that everything in validate
3944 // and process gets a consistent answer about whether we're in an IT
3946 forwardITPosition();
3948 Out.EmitInstruction(Inst);
3950 case Match_MissingFeature:
3951 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
3953 case Match_InvalidOperand: {
3954 SMLoc ErrorLoc = IDLoc;
3955 if (ErrorInfo != ~0U) {
3956 if (ErrorInfo >= Operands.size())
3957 return Error(IDLoc, "too few operands for instruction");
3959 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
3960 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
3963 return Error(ErrorLoc, "invalid operand for instruction");
3965 case Match_MnemonicFail:
3966 return Error(IDLoc, "invalid instruction");
3967 case Match_ConversionFail:
3968 // The converter function will have already emited a diagnostic.
3970 case Match_RequiresNotITBlock:
3971 return Error(IDLoc, "flag setting instruction only valid outside IT block");
3972 case Match_RequiresITBlock:
3973 return Error(IDLoc, "instruction only valid inside IT block");
3974 case Match_RequiresV6:
3975 return Error(IDLoc, "instruction variant requires ARMv6 or later");
3976 case Match_RequiresThumb2:
3977 return Error(IDLoc, "instruction variant requires Thumb2");
3980 llvm_unreachable("Implement any new match types added!");
3984 /// parseDirective parses the arm specific directives
3985 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
3986 StringRef IDVal = DirectiveID.getIdentifier();
3987 if (IDVal == ".word")
3988 return parseDirectiveWord(4, DirectiveID.getLoc());
3989 else if (IDVal == ".thumb")
3990 return parseDirectiveThumb(DirectiveID.getLoc());
3991 else if (IDVal == ".thumb_func")
3992 return parseDirectiveThumbFunc(DirectiveID.getLoc());
3993 else if (IDVal == ".code")
3994 return parseDirectiveCode(DirectiveID.getLoc());
3995 else if (IDVal == ".syntax")
3996 return parseDirectiveSyntax(DirectiveID.getLoc());
4000 /// parseDirectiveWord
4001 /// ::= .word [ expression (, expression)* ]
4002 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
4003 if (getLexer().isNot(AsmToken::EndOfStatement)) {
4005 const MCExpr *Value;
4006 if (getParser().ParseExpression(Value))
4009 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
4011 if (getLexer().is(AsmToken::EndOfStatement))
4014 // FIXME: Improve diagnostic.
4015 if (getLexer().isNot(AsmToken::Comma))
4016 return Error(L, "unexpected token in directive");
4025 /// parseDirectiveThumb
4027 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
4028 if (getLexer().isNot(AsmToken::EndOfStatement))
4029 return Error(L, "unexpected token in directive");
4032 // TODO: set thumb mode
4033 // TODO: tell the MC streamer the mode
4034 // getParser().getStreamer().Emit???();
4038 /// parseDirectiveThumbFunc
4039 /// ::= .thumbfunc symbol_name
4040 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
4041 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
4042 bool isMachO = MAI.hasSubsectionsViaSymbols();
4045 // Darwin asm has function name after .thumb_func direction
4048 const AsmToken &Tok = Parser.getTok();
4049 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
4050 return Error(L, "unexpected token in .thumb_func directive");
4051 Name = Tok.getString();
4052 Parser.Lex(); // Consume the identifier token.
4055 if (getLexer().isNot(AsmToken::EndOfStatement))
4056 return Error(L, "unexpected token in directive");
4059 // FIXME: assuming function name will be the line following .thumb_func
4061 Name = Parser.getTok().getString();
4064 // Mark symbol as a thumb symbol.
4065 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
4066 getParser().getStreamer().EmitThumbFunc(Func);
4070 /// parseDirectiveSyntax
4071 /// ::= .syntax unified | divided
4072 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
4073 const AsmToken &Tok = Parser.getTok();
4074 if (Tok.isNot(AsmToken::Identifier))
4075 return Error(L, "unexpected token in .syntax directive");
4076 StringRef Mode = Tok.getString();
4077 if (Mode == "unified" || Mode == "UNIFIED")
4079 else if (Mode == "divided" || Mode == "DIVIDED")
4080 return Error(L, "'.syntax divided' arm asssembly not supported");
4082 return Error(L, "unrecognized syntax mode in .syntax directive");
4084 if (getLexer().isNot(AsmToken::EndOfStatement))
4085 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
4088 // TODO tell the MC streamer the mode
4089 // getParser().getStreamer().Emit???();
4093 /// parseDirectiveCode
4094 /// ::= .code 16 | 32
4095 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
4096 const AsmToken &Tok = Parser.getTok();
4097 if (Tok.isNot(AsmToken::Integer))
4098 return Error(L, "unexpected token in .code directive");
4099 int64_t Val = Parser.getTok().getIntVal();
4105 return Error(L, "invalid operand to .code directive");
4107 if (getLexer().isNot(AsmToken::EndOfStatement))
4108 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
4114 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
4118 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
4124 extern "C" void LLVMInitializeARMAsmLexer();
4126 /// Force static initialization.
4127 extern "C" void LLVMInitializeARMAsmParser() {
4128 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
4129 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
4130 LLVMInitializeARMAsmLexer();
4133 #define GET_REGISTER_MATCHER
4134 #define GET_MATCHER_IMPLEMENTATION
4135 #include "ARMGenAsmMatcher.inc"