1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMBaseInfo.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMMCExpr.h"
13 #include "llvm/MC/MCParser/MCAsmLexer.h"
14 #include "llvm/MC/MCParser/MCAsmParser.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCAsmInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCTargetAsmParser.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/SourceMgr.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/ADT/BitVector.h"
30 #include "llvm/ADT/OwningPtr.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/StringSwitch.h"
34 #include "llvm/ADT/Twine.h"
42 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
44 class ARMAsmParser : public MCTargetAsmParser {
47 const MCRegisterInfo *MRI;
49 // Map of register aliases registers via the .req directive.
50 StringMap<unsigned> RegisterReqs;
53 ARMCC::CondCodes Cond; // Condition for IT block.
54 unsigned Mask:4; // Condition mask for instructions.
55 // Starting at first 1 (from lsb).
56 // '1' condition as indicated in IT.
57 // '0' inverse of condition (else).
58 // Count of instructions in IT block is
59 // 4 - trailingzeroes(mask)
61 bool FirstCond; // Explicit flag for when we're parsing the
62 // First instruction in the IT block. It's
63 // implied in the mask, so needs special
66 unsigned CurPosition; // Current position in parsing of IT
67 // block. In range [0,3]. Initialized
68 // according to count of instructions in block.
69 // ~0U if no active IT block.
71 bool inITBlock() { return ITState.CurPosition != ~0U;}
72 void forwardITPosition() {
73 if (!inITBlock()) return;
74 // Move to the next instruction in the IT block, if there is one. If not,
75 // mark the block as done.
76 unsigned TZ = CountTrailingZeros_32(ITState.Mask);
77 if (++ITState.CurPosition == 5 - TZ)
78 ITState.CurPosition = ~0U; // Done with the IT block after this.
82 MCAsmParser &getParser() const { return Parser; }
83 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
85 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
86 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
88 int tryParseRegister();
89 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
90 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
91 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
92 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
93 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
94 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
95 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
96 unsigned &ShiftAmount);
97 bool parseDirectiveWord(unsigned Size, SMLoc L);
98 bool parseDirectiveThumb(SMLoc L);
99 bool parseDirectiveARM(SMLoc L);
100 bool parseDirectiveThumbFunc(SMLoc L);
101 bool parseDirectiveCode(SMLoc L);
102 bool parseDirectiveSyntax(SMLoc L);
103 bool parseDirectiveReq(StringRef Name, SMLoc L);
104 bool parseDirectiveUnreq(SMLoc L);
105 bool parseDirectiveArch(SMLoc L);
106 bool parseDirectiveEabiAttr(SMLoc L);
108 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
109 bool &CarrySetting, unsigned &ProcessorIMod,
111 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
112 bool &CanAcceptPredicationCode);
114 bool isThumb() const {
115 // FIXME: Can tablegen auto-generate this?
116 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
118 bool isThumbOne() const {
119 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
121 bool isThumbTwo() const {
122 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
124 bool hasV6Ops() const {
125 return STI.getFeatureBits() & ARM::HasV6Ops;
127 bool hasV7Ops() const {
128 return STI.getFeatureBits() & ARM::HasV7Ops;
131 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
132 setAvailableFeatures(FB);
134 bool isMClass() const {
135 return STI.getFeatureBits() & ARM::FeatureMClass;
138 /// @name Auto-generated Match Functions
141 #define GET_ASSEMBLER_HEADER
142 #include "ARMGenAsmMatcher.inc"
146 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
147 OperandMatchResultTy parseCoprocNumOperand(
148 SmallVectorImpl<MCParsedAsmOperand*>&);
149 OperandMatchResultTy parseCoprocRegOperand(
150 SmallVectorImpl<MCParsedAsmOperand*>&);
151 OperandMatchResultTy parseCoprocOptionOperand(
152 SmallVectorImpl<MCParsedAsmOperand*>&);
153 OperandMatchResultTy parseMemBarrierOptOperand(
154 SmallVectorImpl<MCParsedAsmOperand*>&);
155 OperandMatchResultTy parseProcIFlagsOperand(
156 SmallVectorImpl<MCParsedAsmOperand*>&);
157 OperandMatchResultTy parseMSRMaskOperand(
158 SmallVectorImpl<MCParsedAsmOperand*>&);
159 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
160 StringRef Op, int Low, int High);
161 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
162 return parsePKHImm(O, "lsl", 0, 31);
164 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
165 return parsePKHImm(O, "asr", 1, 32);
167 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
168 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
169 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
170 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
171 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
172 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
173 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
174 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
175 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index);
177 // Asm Match Converter Methods
178 bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
179 const SmallVectorImpl<MCParsedAsmOperand*> &);
180 bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
181 const SmallVectorImpl<MCParsedAsmOperand*> &);
182 bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
183 const SmallVectorImpl<MCParsedAsmOperand*> &);
184 bool cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
185 const SmallVectorImpl<MCParsedAsmOperand*> &);
186 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
187 const SmallVectorImpl<MCParsedAsmOperand*> &);
188 bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
189 const SmallVectorImpl<MCParsedAsmOperand*> &);
190 bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
191 const SmallVectorImpl<MCParsedAsmOperand*> &);
192 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
193 const SmallVectorImpl<MCParsedAsmOperand*> &);
194 bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
195 const SmallVectorImpl<MCParsedAsmOperand*> &);
196 bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
197 const SmallVectorImpl<MCParsedAsmOperand*> &);
198 bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
199 const SmallVectorImpl<MCParsedAsmOperand*> &);
200 bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
201 const SmallVectorImpl<MCParsedAsmOperand*> &);
202 bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
203 const SmallVectorImpl<MCParsedAsmOperand*> &);
204 bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
205 const SmallVectorImpl<MCParsedAsmOperand*> &);
206 bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
207 const SmallVectorImpl<MCParsedAsmOperand*> &);
208 bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
209 const SmallVectorImpl<MCParsedAsmOperand*> &);
210 bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
211 const SmallVectorImpl<MCParsedAsmOperand*> &);
212 bool cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
213 const SmallVectorImpl<MCParsedAsmOperand*> &);
214 bool cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
215 const SmallVectorImpl<MCParsedAsmOperand*> &);
216 bool cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
217 const SmallVectorImpl<MCParsedAsmOperand*> &);
218 bool cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
219 const SmallVectorImpl<MCParsedAsmOperand*> &);
221 bool validateInstruction(MCInst &Inst,
222 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
223 bool processInstruction(MCInst &Inst,
224 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
225 bool shouldOmitCCOutOperand(StringRef Mnemonic,
226 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
229 enum ARMMatchResultTy {
230 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
231 Match_RequiresNotITBlock,
236 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
237 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
238 MCAsmParserExtension::Initialize(_Parser);
240 // Cache the MCRegisterInfo.
241 MRI = &getContext().getRegisterInfo();
243 // Initialize the set of available features.
244 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
246 // Not in an ITBlock to start with.
247 ITState.CurPosition = ~0U;
250 // Implementation of the MCTargetAsmParser interface:
251 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
252 bool ParseInstruction(StringRef Name, SMLoc NameLoc,
253 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
254 bool ParseDirective(AsmToken DirectiveID);
256 unsigned checkTargetMatchPredicate(MCInst &Inst);
258 bool MatchAndEmitInstruction(SMLoc IDLoc,
259 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
262 } // end anonymous namespace
266 /// ARMOperand - Instances of this class represent a parsed ARM machine
268 class ARMOperand : public MCParsedAsmOperand {
288 k_VectorListAllLanes,
294 k_BitfieldDescriptor,
298 SMLoc StartLoc, EndLoc;
299 SmallVector<unsigned, 8> Registers;
303 ARMCC::CondCodes Val;
323 ARM_PROC::IFlags Val;
339 // A vector register list is a sequential list of 1 to 4 registers.
355 /// Combined record for all forms of ARM address expressions.
358 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
360 const MCConstantExpr *OffsetImm; // Offset immediate value
361 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
362 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
363 unsigned ShiftImm; // shift for OffsetReg.
364 unsigned Alignment; // 0 = no alignment specified
365 // n = alignment in bytes (2, 4, 8, 16, or 32)
366 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
372 ARM_AM::ShiftOpc ShiftTy;
381 ARM_AM::ShiftOpc ShiftTy;
387 ARM_AM::ShiftOpc ShiftTy;
400 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
402 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
404 StartLoc = o.StartLoc;
421 case k_DPRRegisterList:
422 case k_SPRRegisterList:
423 Registers = o.Registers;
426 case k_VectorListAllLanes:
427 case k_VectorListIndexed:
428 VectorList = o.VectorList;
435 CoprocOption = o.CoprocOption;
440 case k_MemBarrierOpt:
446 case k_PostIndexRegister:
447 PostIdxReg = o.PostIdxReg;
455 case k_ShifterImmediate:
456 ShifterImm = o.ShifterImm;
458 case k_ShiftedRegister:
459 RegShiftedReg = o.RegShiftedReg;
461 case k_ShiftedImmediate:
462 RegShiftedImm = o.RegShiftedImm;
464 case k_RotateImmediate:
467 case k_BitfieldDescriptor:
468 Bitfield = o.Bitfield;
471 VectorIndex = o.VectorIndex;
476 /// getStartLoc - Get the location of the first token of this operand.
477 SMLoc getStartLoc() const { return StartLoc; }
478 /// getEndLoc - Get the location of the last token of this operand.
479 SMLoc getEndLoc() const { return EndLoc; }
481 ARMCC::CondCodes getCondCode() const {
482 assert(Kind == k_CondCode && "Invalid access!");
486 unsigned getCoproc() const {
487 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
491 StringRef getToken() const {
492 assert(Kind == k_Token && "Invalid access!");
493 return StringRef(Tok.Data, Tok.Length);
496 unsigned getReg() const {
497 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
501 const SmallVectorImpl<unsigned> &getRegList() const {
502 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
503 Kind == k_SPRRegisterList) && "Invalid access!");
507 const MCExpr *getImm() const {
508 assert(isImm() && "Invalid access!");
512 unsigned getVectorIndex() const {
513 assert(Kind == k_VectorIndex && "Invalid access!");
514 return VectorIndex.Val;
517 ARM_MB::MemBOpt getMemBarrierOpt() const {
518 assert(Kind == k_MemBarrierOpt && "Invalid access!");
522 ARM_PROC::IFlags getProcIFlags() const {
523 assert(Kind == k_ProcIFlags && "Invalid access!");
527 unsigned getMSRMask() const {
528 assert(Kind == k_MSRMask && "Invalid access!");
532 bool isCoprocNum() const { return Kind == k_CoprocNum; }
533 bool isCoprocReg() const { return Kind == k_CoprocReg; }
534 bool isCoprocOption() const { return Kind == k_CoprocOption; }
535 bool isCondCode() const { return Kind == k_CondCode; }
536 bool isCCOut() const { return Kind == k_CCOut; }
537 bool isITMask() const { return Kind == k_ITCondMask; }
538 bool isITCondCode() const { return Kind == k_CondCode; }
539 bool isImm() const { return Kind == k_Immediate; }
540 bool isFPImm() const {
541 if (!isImm()) return false;
542 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
543 if (!CE) return false;
544 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
547 bool isFBits16() const {
548 if (!isImm()) return false;
549 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
550 if (!CE) return false;
551 int64_t Value = CE->getValue();
552 return Value >= 0 && Value <= 16;
554 bool isFBits32() const {
555 if (!isImm()) return false;
556 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
557 if (!CE) return false;
558 int64_t Value = CE->getValue();
559 return Value >= 1 && Value <= 32;
561 bool isImm8s4() const {
562 if (!isImm()) return false;
563 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
564 if (!CE) return false;
565 int64_t Value = CE->getValue();
566 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
568 bool isImm0_1020s4() const {
569 if (!isImm()) return false;
570 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
571 if (!CE) return false;
572 int64_t Value = CE->getValue();
573 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
575 bool isImm0_508s4() const {
576 if (!isImm()) return false;
577 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
578 if (!CE) return false;
579 int64_t Value = CE->getValue();
580 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
582 bool isImm0_255() const {
583 if (!isImm()) return false;
584 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
585 if (!CE) return false;
586 int64_t Value = CE->getValue();
587 return Value >= 0 && Value < 256;
589 bool isImm0_1() const {
590 if (!isImm()) return false;
591 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
592 if (!CE) return false;
593 int64_t Value = CE->getValue();
594 return Value >= 0 && Value < 2;
596 bool isImm0_3() const {
597 if (!isImm()) return false;
598 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
599 if (!CE) return false;
600 int64_t Value = CE->getValue();
601 return Value >= 0 && Value < 4;
603 bool isImm0_7() const {
604 if (!isImm()) return false;
605 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
606 if (!CE) return false;
607 int64_t Value = CE->getValue();
608 return Value >= 0 && Value < 8;
610 bool isImm0_15() const {
611 if (!isImm()) return false;
612 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
613 if (!CE) return false;
614 int64_t Value = CE->getValue();
615 return Value >= 0 && Value < 16;
617 bool isImm0_31() const {
618 if (!isImm()) return false;
619 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
620 if (!CE) return false;
621 int64_t Value = CE->getValue();
622 return Value >= 0 && Value < 32;
624 bool isImm0_63() const {
625 if (!isImm()) return false;
626 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
627 if (!CE) return false;
628 int64_t Value = CE->getValue();
629 return Value >= 0 && Value < 64;
631 bool isImm8() const {
632 if (!isImm()) return false;
633 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
634 if (!CE) return false;
635 int64_t Value = CE->getValue();
638 bool isImm16() const {
639 if (!isImm()) return false;
640 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
641 if (!CE) return false;
642 int64_t Value = CE->getValue();
645 bool isImm32() const {
646 if (!isImm()) return false;
647 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
648 if (!CE) return false;
649 int64_t Value = CE->getValue();
652 bool isShrImm8() const {
653 if (!isImm()) return false;
654 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
655 if (!CE) return false;
656 int64_t Value = CE->getValue();
657 return Value > 0 && Value <= 8;
659 bool isShrImm16() const {
660 if (!isImm()) return false;
661 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
662 if (!CE) return false;
663 int64_t Value = CE->getValue();
664 return Value > 0 && Value <= 16;
666 bool isShrImm32() const {
667 if (!isImm()) return false;
668 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
669 if (!CE) return false;
670 int64_t Value = CE->getValue();
671 return Value > 0 && Value <= 32;
673 bool isShrImm64() const {
674 if (!isImm()) return false;
675 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
676 if (!CE) return false;
677 int64_t Value = CE->getValue();
678 return Value > 0 && Value <= 64;
680 bool isImm1_7() const {
681 if (!isImm()) return false;
682 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
683 if (!CE) return false;
684 int64_t Value = CE->getValue();
685 return Value > 0 && Value < 8;
687 bool isImm1_15() const {
688 if (!isImm()) return false;
689 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
690 if (!CE) return false;
691 int64_t Value = CE->getValue();
692 return Value > 0 && Value < 16;
694 bool isImm1_31() const {
695 if (!isImm()) return false;
696 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
697 if (!CE) return false;
698 int64_t Value = CE->getValue();
699 return Value > 0 && Value < 32;
701 bool isImm1_16() const {
702 if (!isImm()) return false;
703 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
704 if (!CE) return false;
705 int64_t Value = CE->getValue();
706 return Value > 0 && Value < 17;
708 bool isImm1_32() const {
709 if (!isImm()) return false;
710 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
711 if (!CE) return false;
712 int64_t Value = CE->getValue();
713 return Value > 0 && Value < 33;
715 bool isImm0_32() const {
716 if (!isImm()) return false;
717 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
718 if (!CE) return false;
719 int64_t Value = CE->getValue();
720 return Value >= 0 && Value < 33;
722 bool isImm0_65535() const {
723 if (!isImm()) return false;
724 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
725 if (!CE) return false;
726 int64_t Value = CE->getValue();
727 return Value >= 0 && Value < 65536;
729 bool isImm0_65535Expr() const {
730 if (!isImm()) return false;
731 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
732 // If it's not a constant expression, it'll generate a fixup and be
734 if (!CE) return true;
735 int64_t Value = CE->getValue();
736 return Value >= 0 && Value < 65536;
738 bool isImm24bit() const {
739 if (!isImm()) return false;
740 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
741 if (!CE) return false;
742 int64_t Value = CE->getValue();
743 return Value >= 0 && Value <= 0xffffff;
745 bool isImmThumbSR() const {
746 if (!isImm()) return false;
747 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
748 if (!CE) return false;
749 int64_t Value = CE->getValue();
750 return Value > 0 && Value < 33;
752 bool isPKHLSLImm() const {
753 if (!isImm()) return false;
754 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
755 if (!CE) return false;
756 int64_t Value = CE->getValue();
757 return Value >= 0 && Value < 32;
759 bool isPKHASRImm() const {
760 if (!isImm()) return false;
761 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
762 if (!CE) return false;
763 int64_t Value = CE->getValue();
764 return Value > 0 && Value <= 32;
766 bool isARMSOImm() const {
767 if (!isImm()) return false;
768 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
769 if (!CE) return false;
770 int64_t Value = CE->getValue();
771 return ARM_AM::getSOImmVal(Value) != -1;
773 bool isARMSOImmNot() const {
774 if (!isImm()) return false;
775 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
776 if (!CE) return false;
777 int64_t Value = CE->getValue();
778 return ARM_AM::getSOImmVal(~Value) != -1;
780 bool isARMSOImmNeg() const {
781 if (!isImm()) return false;
782 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
783 if (!CE) return false;
784 int64_t Value = CE->getValue();
785 return ARM_AM::getSOImmVal(-Value) != -1;
787 bool isT2SOImm() const {
788 if (!isImm()) return false;
789 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
790 if (!CE) return false;
791 int64_t Value = CE->getValue();
792 return ARM_AM::getT2SOImmVal(Value) != -1;
794 bool isT2SOImmNot() const {
795 if (!isImm()) return false;
796 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
797 if (!CE) return false;
798 int64_t Value = CE->getValue();
799 return ARM_AM::getT2SOImmVal(~Value) != -1;
801 bool isT2SOImmNeg() const {
802 if (!isImm()) return false;
803 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
804 if (!CE) return false;
805 int64_t Value = CE->getValue();
806 return ARM_AM::getT2SOImmVal(-Value) != -1;
808 bool isSetEndImm() const {
809 if (!isImm()) return false;
810 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
811 if (!CE) return false;
812 int64_t Value = CE->getValue();
813 return Value == 1 || Value == 0;
815 bool isReg() const { return Kind == k_Register; }
816 bool isRegList() const { return Kind == k_RegisterList; }
817 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
818 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
819 bool isToken() const { return Kind == k_Token; }
820 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
821 bool isMemory() const { return Kind == k_Memory; }
822 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
823 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
824 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
825 bool isRotImm() const { return Kind == k_RotateImmediate; }
826 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
827 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
828 bool isPostIdxReg() const {
829 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
831 bool isMemNoOffset(bool alignOK = false) const {
834 // No offset of any kind.
835 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
836 (alignOK || Memory.Alignment == 0);
838 bool isMemPCRelImm12() const {
839 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
841 // Base register must be PC.
842 if (Memory.BaseRegNum != ARM::PC)
844 // Immediate offset in range [-4095, 4095].
845 if (!Memory.OffsetImm) return true;
846 int64_t Val = Memory.OffsetImm->getValue();
847 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
849 bool isAlignedMemory() const {
850 return isMemNoOffset(true);
852 bool isAddrMode2() const {
853 if (!isMemory() || Memory.Alignment != 0) return false;
854 // Check for register offset.
855 if (Memory.OffsetRegNum) return true;
856 // Immediate offset in range [-4095, 4095].
857 if (!Memory.OffsetImm) return true;
858 int64_t Val = Memory.OffsetImm->getValue();
859 return Val > -4096 && Val < 4096;
861 bool isAM2OffsetImm() const {
862 if (!isImm()) return false;
863 // Immediate offset in range [-4095, 4095].
864 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
865 if (!CE) return false;
866 int64_t Val = CE->getValue();
867 return Val > -4096 && Val < 4096;
869 bool isAddrMode3() const {
870 // If we have an immediate that's not a constant, treat it as a label
871 // reference needing a fixup. If it is a constant, it's something else
873 if (isImm() && !isa<MCConstantExpr>(getImm()))
875 if (!isMemory() || Memory.Alignment != 0) return false;
876 // No shifts are legal for AM3.
877 if (Memory.ShiftType != ARM_AM::no_shift) return false;
878 // Check for register offset.
879 if (Memory.OffsetRegNum) return true;
880 // Immediate offset in range [-255, 255].
881 if (!Memory.OffsetImm) return true;
882 int64_t Val = Memory.OffsetImm->getValue();
883 return Val > -256 && Val < 256;
885 bool isAM3Offset() const {
886 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
888 if (Kind == k_PostIndexRegister)
889 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
890 // Immediate offset in range [-255, 255].
891 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
892 if (!CE) return false;
893 int64_t Val = CE->getValue();
894 // Special case, #-0 is INT32_MIN.
895 return (Val > -256 && Val < 256) || Val == INT32_MIN;
897 bool isAddrMode5() const {
898 // If we have an immediate that's not a constant, treat it as a label
899 // reference needing a fixup. If it is a constant, it's something else
901 if (isImm() && !isa<MCConstantExpr>(getImm()))
903 if (!isMemory() || Memory.Alignment != 0) return false;
904 // Check for register offset.
905 if (Memory.OffsetRegNum) return false;
906 // Immediate offset in range [-1020, 1020] and a multiple of 4.
907 if (!Memory.OffsetImm) return true;
908 int64_t Val = Memory.OffsetImm->getValue();
909 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
912 bool isMemTBB() const {
913 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
914 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
918 bool isMemTBH() const {
919 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
920 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
921 Memory.Alignment != 0 )
925 bool isMemRegOffset() const {
926 if (!isMemory() || !Memory.OffsetRegNum || Memory.Alignment != 0)
930 bool isT2MemRegOffset() const {
931 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
932 Memory.Alignment != 0)
934 // Only lsl #{0, 1, 2, 3} allowed.
935 if (Memory.ShiftType == ARM_AM::no_shift)
937 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
941 bool isMemThumbRR() const {
942 // Thumb reg+reg addressing is simple. Just two registers, a base and
943 // an offset. No shifts, negations or any other complicating factors.
944 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
945 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
947 return isARMLowRegister(Memory.BaseRegNum) &&
948 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
950 bool isMemThumbRIs4() const {
951 if (!isMemory() || Memory.OffsetRegNum != 0 ||
952 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
954 // Immediate offset, multiple of 4 in range [0, 124].
955 if (!Memory.OffsetImm) return true;
956 int64_t Val = Memory.OffsetImm->getValue();
957 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
959 bool isMemThumbRIs2() const {
960 if (!isMemory() || Memory.OffsetRegNum != 0 ||
961 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
963 // Immediate offset, multiple of 4 in range [0, 62].
964 if (!Memory.OffsetImm) return true;
965 int64_t Val = Memory.OffsetImm->getValue();
966 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
968 bool isMemThumbRIs1() const {
969 if (!isMemory() || Memory.OffsetRegNum != 0 ||
970 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
972 // Immediate offset in range [0, 31].
973 if (!Memory.OffsetImm) return true;
974 int64_t Val = Memory.OffsetImm->getValue();
975 return Val >= 0 && Val <= 31;
977 bool isMemThumbSPI() const {
978 if (!isMemory() || Memory.OffsetRegNum != 0 ||
979 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
981 // Immediate offset, multiple of 4 in range [0, 1020].
982 if (!Memory.OffsetImm) return true;
983 int64_t Val = Memory.OffsetImm->getValue();
984 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
986 bool isMemImm8s4Offset() const {
987 // If we have an immediate that's not a constant, treat it as a label
988 // reference needing a fixup. If it is a constant, it's something else
990 if (isImm() && !isa<MCConstantExpr>(getImm()))
992 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
994 // Immediate offset a multiple of 4 in range [-1020, 1020].
995 if (!Memory.OffsetImm) return true;
996 int64_t Val = Memory.OffsetImm->getValue();
997 return Val >= -1020 && Val <= 1020 && (Val & 3) == 0;
999 bool isMemImm0_1020s4Offset() const {
1000 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1002 // Immediate offset a multiple of 4 in range [0, 1020].
1003 if (!Memory.OffsetImm) return true;
1004 int64_t Val = Memory.OffsetImm->getValue();
1005 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1007 bool isMemImm8Offset() const {
1008 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1010 // Base reg of PC isn't allowed for these encodings.
1011 if (Memory.BaseRegNum == ARM::PC) return false;
1012 // Immediate offset in range [-255, 255].
1013 if (!Memory.OffsetImm) return true;
1014 int64_t Val = Memory.OffsetImm->getValue();
1015 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1017 bool isMemPosImm8Offset() const {
1018 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1020 // Immediate offset in range [0, 255].
1021 if (!Memory.OffsetImm) return true;
1022 int64_t Val = Memory.OffsetImm->getValue();
1023 return Val >= 0 && Val < 256;
1025 bool isMemNegImm8Offset() const {
1026 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1028 // Base reg of PC isn't allowed for these encodings.
1029 if (Memory.BaseRegNum == ARM::PC) return false;
1030 // Immediate offset in range [-255, -1].
1031 if (!Memory.OffsetImm) return false;
1032 int64_t Val = Memory.OffsetImm->getValue();
1033 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1035 bool isMemUImm12Offset() const {
1036 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1038 // Immediate offset in range [0, 4095].
1039 if (!Memory.OffsetImm) return true;
1040 int64_t Val = Memory.OffsetImm->getValue();
1041 return (Val >= 0 && Val < 4096);
1043 bool isMemImm12Offset() const {
1044 // If we have an immediate that's not a constant, treat it as a label
1045 // reference needing a fixup. If it is a constant, it's something else
1046 // and we reject it.
1047 if (isImm() && !isa<MCConstantExpr>(getImm()))
1050 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1052 // Immediate offset in range [-4095, 4095].
1053 if (!Memory.OffsetImm) return true;
1054 int64_t Val = Memory.OffsetImm->getValue();
1055 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1057 bool isPostIdxImm8() const {
1058 if (!isImm()) return false;
1059 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1060 if (!CE) return false;
1061 int64_t Val = CE->getValue();
1062 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1064 bool isPostIdxImm8s4() const {
1065 if (!isImm()) return false;
1066 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1067 if (!CE) return false;
1068 int64_t Val = CE->getValue();
1069 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1073 bool isMSRMask() const { return Kind == k_MSRMask; }
1074 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1077 bool isSingleSpacedVectorList() const {
1078 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1080 bool isDoubleSpacedVectorList() const {
1081 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1083 bool isVecListOneD() const {
1084 if (!isSingleSpacedVectorList()) return false;
1085 return VectorList.Count == 1;
1088 bool isVecListDPair() const {
1089 if (!isSingleSpacedVectorList()) return false;
1090 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1091 .contains(VectorList.RegNum));
1094 bool isVecListThreeD() const {
1095 if (!isSingleSpacedVectorList()) return false;
1096 return VectorList.Count == 3;
1099 bool isVecListFourD() const {
1100 if (!isSingleSpacedVectorList()) return false;
1101 return VectorList.Count == 4;
1104 bool isVecListTwoQ() const {
1105 if (!isDoubleSpacedVectorList()) return false;
1106 return VectorList.Count == 2;
1109 bool isVecListDPairSpaced() const {
1110 if (!isSingleSpacedVectorList()) return false;
1111 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1112 .contains(VectorList.RegNum));
1115 bool isVecListThreeQ() const {
1116 if (!isDoubleSpacedVectorList()) return false;
1117 return VectorList.Count == 3;
1120 bool isVecListFourQ() const {
1121 if (!isDoubleSpacedVectorList()) return false;
1122 return VectorList.Count == 4;
1125 bool isSingleSpacedVectorAllLanes() const {
1126 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1128 bool isDoubleSpacedVectorAllLanes() const {
1129 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1131 bool isVecListOneDAllLanes() const {
1132 if (!isSingleSpacedVectorAllLanes()) return false;
1133 return VectorList.Count == 1;
1136 bool isVecListDPairAllLanes() const {
1137 if (!isSingleSpacedVectorAllLanes()) return false;
1138 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1139 .contains(VectorList.RegNum));
1142 bool isVecListTwoQAllLanes() const {
1143 if (!isDoubleSpacedVectorAllLanes()) return false;
1144 return VectorList.Count == 2;
1147 bool isVecListThreeDAllLanes() const {
1148 if (!isSingleSpacedVectorAllLanes()) return false;
1149 return VectorList.Count == 3;
1152 bool isVecListThreeQAllLanes() const {
1153 if (!isDoubleSpacedVectorAllLanes()) return false;
1154 return VectorList.Count == 3;
1157 bool isVecListFourDAllLanes() const {
1158 if (!isSingleSpacedVectorAllLanes()) return false;
1159 return VectorList.Count == 4;
1162 bool isVecListFourQAllLanes() const {
1163 if (!isDoubleSpacedVectorAllLanes()) return false;
1164 return VectorList.Count == 4;
1167 bool isSingleSpacedVectorIndexed() const {
1168 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1170 bool isDoubleSpacedVectorIndexed() const {
1171 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1173 bool isVecListOneDByteIndexed() const {
1174 if (!isSingleSpacedVectorIndexed()) return false;
1175 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1178 bool isVecListOneDHWordIndexed() const {
1179 if (!isSingleSpacedVectorIndexed()) return false;
1180 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1183 bool isVecListOneDWordIndexed() const {
1184 if (!isSingleSpacedVectorIndexed()) return false;
1185 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1188 bool isVecListTwoDByteIndexed() const {
1189 if (!isSingleSpacedVectorIndexed()) return false;
1190 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1193 bool isVecListTwoDHWordIndexed() const {
1194 if (!isSingleSpacedVectorIndexed()) return false;
1195 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1198 bool isVecListTwoQWordIndexed() const {
1199 if (!isDoubleSpacedVectorIndexed()) return false;
1200 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1203 bool isVecListTwoQHWordIndexed() const {
1204 if (!isDoubleSpacedVectorIndexed()) return false;
1205 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1208 bool isVecListTwoDWordIndexed() const {
1209 if (!isSingleSpacedVectorIndexed()) return false;
1210 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1213 bool isVecListThreeDByteIndexed() const {
1214 if (!isSingleSpacedVectorIndexed()) return false;
1215 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1218 bool isVecListThreeDHWordIndexed() const {
1219 if (!isSingleSpacedVectorIndexed()) return false;
1220 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1223 bool isVecListThreeQWordIndexed() const {
1224 if (!isDoubleSpacedVectorIndexed()) return false;
1225 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1228 bool isVecListThreeQHWordIndexed() const {
1229 if (!isDoubleSpacedVectorIndexed()) return false;
1230 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1233 bool isVecListThreeDWordIndexed() const {
1234 if (!isSingleSpacedVectorIndexed()) return false;
1235 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1238 bool isVecListFourDByteIndexed() const {
1239 if (!isSingleSpacedVectorIndexed()) return false;
1240 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1243 bool isVecListFourDHWordIndexed() const {
1244 if (!isSingleSpacedVectorIndexed()) return false;
1245 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1248 bool isVecListFourQWordIndexed() const {
1249 if (!isDoubleSpacedVectorIndexed()) return false;
1250 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1253 bool isVecListFourQHWordIndexed() const {
1254 if (!isDoubleSpacedVectorIndexed()) return false;
1255 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1258 bool isVecListFourDWordIndexed() const {
1259 if (!isSingleSpacedVectorIndexed()) return false;
1260 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1263 bool isVectorIndex8() const {
1264 if (Kind != k_VectorIndex) return false;
1265 return VectorIndex.Val < 8;
1267 bool isVectorIndex16() const {
1268 if (Kind != k_VectorIndex) return false;
1269 return VectorIndex.Val < 4;
1271 bool isVectorIndex32() const {
1272 if (Kind != k_VectorIndex) return false;
1273 return VectorIndex.Val < 2;
1276 bool isNEONi8splat() const {
1277 if (!isImm()) return false;
1278 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1279 // Must be a constant.
1280 if (!CE) return false;
1281 int64_t Value = CE->getValue();
1282 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1284 return Value >= 0 && Value < 256;
1287 bool isNEONi16splat() const {
1288 if (!isImm()) return false;
1289 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1290 // Must be a constant.
1291 if (!CE) return false;
1292 int64_t Value = CE->getValue();
1293 // i16 value in the range [0,255] or [0x0100, 0xff00]
1294 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1297 bool isNEONi32splat() const {
1298 if (!isImm()) return false;
1299 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1300 // Must be a constant.
1301 if (!CE) return false;
1302 int64_t Value = CE->getValue();
1303 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1304 return (Value >= 0 && Value < 256) ||
1305 (Value >= 0x0100 && Value <= 0xff00) ||
1306 (Value >= 0x010000 && Value <= 0xff0000) ||
1307 (Value >= 0x01000000 && Value <= 0xff000000);
1310 bool isNEONi32vmov() const {
1311 if (!isImm()) return false;
1312 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1313 // Must be a constant.
1314 if (!CE) return false;
1315 int64_t Value = CE->getValue();
1316 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1317 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1318 return (Value >= 0 && Value < 256) ||
1319 (Value >= 0x0100 && Value <= 0xff00) ||
1320 (Value >= 0x010000 && Value <= 0xff0000) ||
1321 (Value >= 0x01000000 && Value <= 0xff000000) ||
1322 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1323 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1325 bool isNEONi32vmovNeg() const {
1326 if (!isImm()) return false;
1327 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1328 // Must be a constant.
1329 if (!CE) return false;
1330 int64_t Value = ~CE->getValue();
1331 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1332 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1333 return (Value >= 0 && Value < 256) ||
1334 (Value >= 0x0100 && Value <= 0xff00) ||
1335 (Value >= 0x010000 && Value <= 0xff0000) ||
1336 (Value >= 0x01000000 && Value <= 0xff000000) ||
1337 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1338 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1341 bool isNEONi64splat() const {
1342 if (!isImm()) return false;
1343 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1344 // Must be a constant.
1345 if (!CE) return false;
1346 uint64_t Value = CE->getValue();
1347 // i64 value with each byte being either 0 or 0xff.
1348 for (unsigned i = 0; i < 8; ++i)
1349 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1353 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1354 // Add as immediates when possible. Null MCExpr = 0.
1356 Inst.addOperand(MCOperand::CreateImm(0));
1357 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1358 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1360 Inst.addOperand(MCOperand::CreateExpr(Expr));
1363 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1364 assert(N == 2 && "Invalid number of operands!");
1365 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1366 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1367 Inst.addOperand(MCOperand::CreateReg(RegNum));
1370 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1371 assert(N == 1 && "Invalid number of operands!");
1372 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1375 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1376 assert(N == 1 && "Invalid number of operands!");
1377 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1380 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1381 assert(N == 1 && "Invalid number of operands!");
1382 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1385 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1386 assert(N == 1 && "Invalid number of operands!");
1387 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1390 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1391 assert(N == 1 && "Invalid number of operands!");
1392 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1395 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1396 assert(N == 1 && "Invalid number of operands!");
1397 Inst.addOperand(MCOperand::CreateReg(getReg()));
1400 void addRegOperands(MCInst &Inst, unsigned N) const {
1401 assert(N == 1 && "Invalid number of operands!");
1402 Inst.addOperand(MCOperand::CreateReg(getReg()));
1405 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1406 assert(N == 3 && "Invalid number of operands!");
1407 assert(isRegShiftedReg() &&
1408 "addRegShiftedRegOperands() on non RegShiftedReg!");
1409 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1410 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1411 Inst.addOperand(MCOperand::CreateImm(
1412 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1415 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1416 assert(N == 2 && "Invalid number of operands!");
1417 assert(isRegShiftedImm() &&
1418 "addRegShiftedImmOperands() on non RegShiftedImm!");
1419 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1420 Inst.addOperand(MCOperand::CreateImm(
1421 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
1424 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1425 assert(N == 1 && "Invalid number of operands!");
1426 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1430 void addRegListOperands(MCInst &Inst, unsigned N) const {
1431 assert(N == 1 && "Invalid number of operands!");
1432 const SmallVectorImpl<unsigned> &RegList = getRegList();
1433 for (SmallVectorImpl<unsigned>::const_iterator
1434 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1435 Inst.addOperand(MCOperand::CreateReg(*I));
1438 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1439 addRegListOperands(Inst, N);
1442 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1443 addRegListOperands(Inst, N);
1446 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1447 assert(N == 1 && "Invalid number of operands!");
1448 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1449 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1452 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1453 assert(N == 1 && "Invalid number of operands!");
1454 // Munge the lsb/width into a bitfield mask.
1455 unsigned lsb = Bitfield.LSB;
1456 unsigned width = Bitfield.Width;
1457 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1458 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1459 (32 - (lsb + width)));
1460 Inst.addOperand(MCOperand::CreateImm(Mask));
1463 void addImmOperands(MCInst &Inst, unsigned N) const {
1464 assert(N == 1 && "Invalid number of operands!");
1465 addExpr(Inst, getImm());
1468 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1469 assert(N == 1 && "Invalid number of operands!");
1470 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1471 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1474 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1475 assert(N == 1 && "Invalid number of operands!");
1476 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1477 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1480 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1481 assert(N == 1 && "Invalid number of operands!");
1482 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1483 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1484 Inst.addOperand(MCOperand::CreateImm(Val));
1487 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1488 assert(N == 1 && "Invalid number of operands!");
1489 // FIXME: We really want to scale the value here, but the LDRD/STRD
1490 // instruction don't encode operands that way yet.
1491 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1492 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1495 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1496 assert(N == 1 && "Invalid number of operands!");
1497 // The immediate is scaled by four in the encoding and is stored
1498 // in the MCInst as such. Lop off the low two bits here.
1499 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1500 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1503 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1504 assert(N == 1 && "Invalid number of operands!");
1505 // The immediate is scaled by four in the encoding and is stored
1506 // in the MCInst as such. Lop off the low two bits here.
1507 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1508 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1511 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1512 assert(N == 1 && "Invalid number of operands!");
1513 // The constant encodes as the immediate-1, and we store in the instruction
1514 // the bits as encoded, so subtract off one here.
1515 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1516 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1519 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1520 assert(N == 1 && "Invalid number of operands!");
1521 // The constant encodes as the immediate-1, and we store in the instruction
1522 // the bits as encoded, so subtract off one here.
1523 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1524 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1527 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1528 assert(N == 1 && "Invalid number of operands!");
1529 // The constant encodes as the immediate, except for 32, which encodes as
1531 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1532 unsigned Imm = CE->getValue();
1533 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1536 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1537 assert(N == 1 && "Invalid number of operands!");
1538 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1539 // the instruction as well.
1540 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1541 int Val = CE->getValue();
1542 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1545 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1546 assert(N == 1 && "Invalid number of operands!");
1547 // The operand is actually a t2_so_imm, but we have its bitwise
1548 // negation in the assembly source, so twiddle it here.
1549 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1550 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1553 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1554 assert(N == 1 && "Invalid number of operands!");
1555 // The operand is actually a t2_so_imm, but we have its
1556 // negation in the assembly source, so twiddle it here.
1557 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1558 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1561 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1562 assert(N == 1 && "Invalid number of operands!");
1563 // The operand is actually a so_imm, but we have its bitwise
1564 // negation in the assembly source, so twiddle it here.
1565 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1566 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1569 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1570 assert(N == 1 && "Invalid number of operands!");
1571 // The operand is actually a so_imm, but we have its
1572 // negation in the assembly source, so twiddle it here.
1573 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1574 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1577 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1578 assert(N == 1 && "Invalid number of operands!");
1579 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1582 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1583 assert(N == 1 && "Invalid number of operands!");
1584 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1587 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1588 assert(N == 1 && "Invalid number of operands!");
1589 int32_t Imm = Memory.OffsetImm->getValue();
1590 // FIXME: Handle #-0
1591 if (Imm == INT32_MIN) Imm = 0;
1592 Inst.addOperand(MCOperand::CreateImm(Imm));
1595 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1596 assert(N == 2 && "Invalid number of operands!");
1597 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1598 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1601 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1602 assert(N == 3 && "Invalid number of operands!");
1603 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1604 if (!Memory.OffsetRegNum) {
1605 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1606 // Special case for #-0
1607 if (Val == INT32_MIN) Val = 0;
1608 if (Val < 0) Val = -Val;
1609 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1611 // For register offset, we encode the shift type and negation flag
1613 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1614 Memory.ShiftImm, Memory.ShiftType);
1616 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1617 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1618 Inst.addOperand(MCOperand::CreateImm(Val));
1621 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1622 assert(N == 2 && "Invalid number of operands!");
1623 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1624 assert(CE && "non-constant AM2OffsetImm operand!");
1625 int32_t Val = CE->getValue();
1626 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1627 // Special case for #-0
1628 if (Val == INT32_MIN) Val = 0;
1629 if (Val < 0) Val = -Val;
1630 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1631 Inst.addOperand(MCOperand::CreateReg(0));
1632 Inst.addOperand(MCOperand::CreateImm(Val));
1635 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1636 assert(N == 3 && "Invalid number of operands!");
1637 // If we have an immediate that's not a constant, treat it as a label
1638 // reference needing a fixup. If it is a constant, it's something else
1639 // and we reject it.
1641 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1642 Inst.addOperand(MCOperand::CreateReg(0));
1643 Inst.addOperand(MCOperand::CreateImm(0));
1647 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1648 if (!Memory.OffsetRegNum) {
1649 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1650 // Special case for #-0
1651 if (Val == INT32_MIN) Val = 0;
1652 if (Val < 0) Val = -Val;
1653 Val = ARM_AM::getAM3Opc(AddSub, Val);
1655 // For register offset, we encode the shift type and negation flag
1657 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1659 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1660 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1661 Inst.addOperand(MCOperand::CreateImm(Val));
1664 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1665 assert(N == 2 && "Invalid number of operands!");
1666 if (Kind == k_PostIndexRegister) {
1668 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1669 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1670 Inst.addOperand(MCOperand::CreateImm(Val));
1675 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1676 int32_t Val = CE->getValue();
1677 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1678 // Special case for #-0
1679 if (Val == INT32_MIN) Val = 0;
1680 if (Val < 0) Val = -Val;
1681 Val = ARM_AM::getAM3Opc(AddSub, Val);
1682 Inst.addOperand(MCOperand::CreateReg(0));
1683 Inst.addOperand(MCOperand::CreateImm(Val));
1686 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1687 assert(N == 2 && "Invalid number of operands!");
1688 // If we have an immediate that's not a constant, treat it as a label
1689 // reference needing a fixup. If it is a constant, it's something else
1690 // and we reject it.
1692 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1693 Inst.addOperand(MCOperand::CreateImm(0));
1697 // The lower two bits are always zero and as such are not encoded.
1698 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1699 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1700 // Special case for #-0
1701 if (Val == INT32_MIN) Val = 0;
1702 if (Val < 0) Val = -Val;
1703 Val = ARM_AM::getAM5Opc(AddSub, Val);
1704 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1705 Inst.addOperand(MCOperand::CreateImm(Val));
1708 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1709 assert(N == 2 && "Invalid number of operands!");
1710 // If we have an immediate that's not a constant, treat it as a label
1711 // reference needing a fixup. If it is a constant, it's something else
1712 // and we reject it.
1714 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1715 Inst.addOperand(MCOperand::CreateImm(0));
1719 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1720 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1721 Inst.addOperand(MCOperand::CreateImm(Val));
1724 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1725 assert(N == 2 && "Invalid number of operands!");
1726 // The lower two bits are always zero and as such are not encoded.
1727 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1728 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1729 Inst.addOperand(MCOperand::CreateImm(Val));
1732 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1733 assert(N == 2 && "Invalid number of operands!");
1734 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1735 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1736 Inst.addOperand(MCOperand::CreateImm(Val));
1739 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1740 addMemImm8OffsetOperands(Inst, N);
1743 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1744 addMemImm8OffsetOperands(Inst, N);
1747 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1748 assert(N == 2 && "Invalid number of operands!");
1749 // If this is an immediate, it's a label reference.
1751 addExpr(Inst, getImm());
1752 Inst.addOperand(MCOperand::CreateImm(0));
1756 // Otherwise, it's a normal memory reg+offset.
1757 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1758 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1759 Inst.addOperand(MCOperand::CreateImm(Val));
1762 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1763 assert(N == 2 && "Invalid number of operands!");
1764 // If this is an immediate, it's a label reference.
1766 addExpr(Inst, getImm());
1767 Inst.addOperand(MCOperand::CreateImm(0));
1771 // Otherwise, it's a normal memory reg+offset.
1772 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1773 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1774 Inst.addOperand(MCOperand::CreateImm(Val));
1777 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1778 assert(N == 2 && "Invalid number of operands!");
1779 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1780 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1783 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
1784 assert(N == 2 && "Invalid number of operands!");
1785 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1786 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1789 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1790 assert(N == 3 && "Invalid number of operands!");
1792 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1793 Memory.ShiftImm, Memory.ShiftType);
1794 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1795 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1796 Inst.addOperand(MCOperand::CreateImm(Val));
1799 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1800 assert(N == 3 && "Invalid number of operands!");
1801 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1802 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1803 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
1806 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1807 assert(N == 2 && "Invalid number of operands!");
1808 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1809 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1812 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1813 assert(N == 2 && "Invalid number of operands!");
1814 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1815 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1816 Inst.addOperand(MCOperand::CreateImm(Val));
1819 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1820 assert(N == 2 && "Invalid number of operands!");
1821 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
1822 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1823 Inst.addOperand(MCOperand::CreateImm(Val));
1826 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1827 assert(N == 2 && "Invalid number of operands!");
1828 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
1829 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1830 Inst.addOperand(MCOperand::CreateImm(Val));
1833 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1834 assert(N == 2 && "Invalid number of operands!");
1835 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1836 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1837 Inst.addOperand(MCOperand::CreateImm(Val));
1840 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1841 assert(N == 1 && "Invalid number of operands!");
1842 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1843 assert(CE && "non-constant post-idx-imm8 operand!");
1844 int Imm = CE->getValue();
1845 bool isAdd = Imm >= 0;
1846 if (Imm == INT32_MIN) Imm = 0;
1847 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1848 Inst.addOperand(MCOperand::CreateImm(Imm));
1851 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
1852 assert(N == 1 && "Invalid number of operands!");
1853 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1854 assert(CE && "non-constant post-idx-imm8s4 operand!");
1855 int Imm = CE->getValue();
1856 bool isAdd = Imm >= 0;
1857 if (Imm == INT32_MIN) Imm = 0;
1858 // Immediate is scaled by 4.
1859 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
1860 Inst.addOperand(MCOperand::CreateImm(Imm));
1863 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1864 assert(N == 2 && "Invalid number of operands!");
1865 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1866 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1869 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1870 assert(N == 2 && "Invalid number of operands!");
1871 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1872 // The sign, shift type, and shift amount are encoded in a single operand
1873 // using the AM2 encoding helpers.
1874 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1875 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1876 PostIdxReg.ShiftTy);
1877 Inst.addOperand(MCOperand::CreateImm(Imm));
1880 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1881 assert(N == 1 && "Invalid number of operands!");
1882 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1885 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1886 assert(N == 1 && "Invalid number of operands!");
1887 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1890 void addVecListOperands(MCInst &Inst, unsigned N) const {
1891 assert(N == 1 && "Invalid number of operands!");
1892 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1895 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
1896 assert(N == 2 && "Invalid number of operands!");
1897 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1898 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
1901 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
1902 assert(N == 1 && "Invalid number of operands!");
1903 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1906 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
1907 assert(N == 1 && "Invalid number of operands!");
1908 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1911 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
1912 assert(N == 1 && "Invalid number of operands!");
1913 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1916 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
1917 assert(N == 1 && "Invalid number of operands!");
1918 // The immediate encodes the type of constant as well as the value.
1919 // Mask in that this is an i8 splat.
1920 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1921 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
1924 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
1925 assert(N == 1 && "Invalid number of operands!");
1926 // The immediate encodes the type of constant as well as the value.
1927 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1928 unsigned Value = CE->getValue();
1930 Value = (Value >> 8) | 0xa00;
1933 Inst.addOperand(MCOperand::CreateImm(Value));
1936 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
1937 assert(N == 1 && "Invalid number of operands!");
1938 // The immediate encodes the type of constant as well as the value.
1939 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1940 unsigned Value = CE->getValue();
1941 if (Value >= 256 && Value <= 0xff00)
1942 Value = (Value >> 8) | 0x200;
1943 else if (Value > 0xffff && Value <= 0xff0000)
1944 Value = (Value >> 16) | 0x400;
1945 else if (Value > 0xffffff)
1946 Value = (Value >> 24) | 0x600;
1947 Inst.addOperand(MCOperand::CreateImm(Value));
1950 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
1951 assert(N == 1 && "Invalid number of operands!");
1952 // The immediate encodes the type of constant as well as the value.
1953 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1954 unsigned Value = CE->getValue();
1955 if (Value >= 256 && Value <= 0xffff)
1956 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
1957 else if (Value > 0xffff && Value <= 0xffffff)
1958 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
1959 else if (Value > 0xffffff)
1960 Value = (Value >> 24) | 0x600;
1961 Inst.addOperand(MCOperand::CreateImm(Value));
1964 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
1965 assert(N == 1 && "Invalid number of operands!");
1966 // The immediate encodes the type of constant as well as the value.
1967 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1968 unsigned Value = ~CE->getValue();
1969 if (Value >= 256 && Value <= 0xffff)
1970 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
1971 else if (Value > 0xffff && Value <= 0xffffff)
1972 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
1973 else if (Value > 0xffffff)
1974 Value = (Value >> 24) | 0x600;
1975 Inst.addOperand(MCOperand::CreateImm(Value));
1978 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
1979 assert(N == 1 && "Invalid number of operands!");
1980 // The immediate encodes the type of constant as well as the value.
1981 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1982 uint64_t Value = CE->getValue();
1984 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
1985 Imm |= (Value & 1) << i;
1987 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
1990 virtual void print(raw_ostream &OS) const;
1992 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
1993 ARMOperand *Op = new ARMOperand(k_ITCondMask);
1994 Op->ITMask.Mask = Mask;
2000 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2001 ARMOperand *Op = new ARMOperand(k_CondCode);
2008 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2009 ARMOperand *Op = new ARMOperand(k_CoprocNum);
2010 Op->Cop.Val = CopVal;
2016 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2017 ARMOperand *Op = new ARMOperand(k_CoprocReg);
2018 Op->Cop.Val = CopVal;
2024 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2025 ARMOperand *Op = new ARMOperand(k_CoprocOption);
2032 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2033 ARMOperand *Op = new ARMOperand(k_CCOut);
2034 Op->Reg.RegNum = RegNum;
2040 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2041 ARMOperand *Op = new ARMOperand(k_Token);
2042 Op->Tok.Data = Str.data();
2043 Op->Tok.Length = Str.size();
2049 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2050 ARMOperand *Op = new ARMOperand(k_Register);
2051 Op->Reg.RegNum = RegNum;
2057 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2062 ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2063 Op->RegShiftedReg.ShiftTy = ShTy;
2064 Op->RegShiftedReg.SrcReg = SrcReg;
2065 Op->RegShiftedReg.ShiftReg = ShiftReg;
2066 Op->RegShiftedReg.ShiftImm = ShiftImm;
2072 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2076 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2077 Op->RegShiftedImm.ShiftTy = ShTy;
2078 Op->RegShiftedImm.SrcReg = SrcReg;
2079 Op->RegShiftedImm.ShiftImm = ShiftImm;
2085 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2087 ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2088 Op->ShifterImm.isASR = isASR;
2089 Op->ShifterImm.Imm = Imm;
2095 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2096 ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2097 Op->RotImm.Imm = Imm;
2103 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2105 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2106 Op->Bitfield.LSB = LSB;
2107 Op->Bitfield.Width = Width;
2114 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
2115 SMLoc StartLoc, SMLoc EndLoc) {
2116 KindTy Kind = k_RegisterList;
2118 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
2119 Kind = k_DPRRegisterList;
2120 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2121 contains(Regs.front().first))
2122 Kind = k_SPRRegisterList;
2124 ARMOperand *Op = new ARMOperand(Kind);
2125 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
2126 I = Regs.begin(), E = Regs.end(); I != E; ++I)
2127 Op->Registers.push_back(I->first);
2128 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
2129 Op->StartLoc = StartLoc;
2130 Op->EndLoc = EndLoc;
2134 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2135 bool isDoubleSpaced, SMLoc S, SMLoc E) {
2136 ARMOperand *Op = new ARMOperand(k_VectorList);
2137 Op->VectorList.RegNum = RegNum;
2138 Op->VectorList.Count = Count;
2139 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2145 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2146 bool isDoubleSpaced,
2148 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2149 Op->VectorList.RegNum = RegNum;
2150 Op->VectorList.Count = Count;
2151 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2157 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2159 bool isDoubleSpaced,
2161 ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2162 Op->VectorList.RegNum = RegNum;
2163 Op->VectorList.Count = Count;
2164 Op->VectorList.LaneIndex = Index;
2165 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2171 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2173 ARMOperand *Op = new ARMOperand(k_VectorIndex);
2174 Op->VectorIndex.Val = Idx;
2180 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2181 ARMOperand *Op = new ARMOperand(k_Immediate);
2188 static ARMOperand *CreateMem(unsigned BaseRegNum,
2189 const MCConstantExpr *OffsetImm,
2190 unsigned OffsetRegNum,
2191 ARM_AM::ShiftOpc ShiftType,
2196 ARMOperand *Op = new ARMOperand(k_Memory);
2197 Op->Memory.BaseRegNum = BaseRegNum;
2198 Op->Memory.OffsetImm = OffsetImm;
2199 Op->Memory.OffsetRegNum = OffsetRegNum;
2200 Op->Memory.ShiftType = ShiftType;
2201 Op->Memory.ShiftImm = ShiftImm;
2202 Op->Memory.Alignment = Alignment;
2203 Op->Memory.isNegative = isNegative;
2209 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2210 ARM_AM::ShiftOpc ShiftTy,
2213 ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2214 Op->PostIdxReg.RegNum = RegNum;
2215 Op->PostIdxReg.isAdd = isAdd;
2216 Op->PostIdxReg.ShiftTy = ShiftTy;
2217 Op->PostIdxReg.ShiftImm = ShiftImm;
2223 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2224 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2225 Op->MBOpt.Val = Opt;
2231 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2232 ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2233 Op->IFlags.Val = IFlags;
2239 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2240 ARMOperand *Op = new ARMOperand(k_MSRMask);
2241 Op->MMask.Val = MMask;
2248 } // end anonymous namespace.
2250 void ARMOperand::print(raw_ostream &OS) const {
2253 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2256 OS << "<ccout " << getReg() << ">";
2258 case k_ITCondMask: {
2259 static const char *MaskStr[] = {
2260 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2261 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2263 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2264 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2268 OS << "<coprocessor number: " << getCoproc() << ">";
2271 OS << "<coprocessor register: " << getCoproc() << ">";
2273 case k_CoprocOption:
2274 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2277 OS << "<mask: " << getMSRMask() << ">";
2280 getImm()->print(OS);
2282 case k_MemBarrierOpt:
2283 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
2287 << " base:" << Memory.BaseRegNum;
2290 case k_PostIndexRegister:
2291 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2292 << PostIdxReg.RegNum;
2293 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2294 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2295 << PostIdxReg.ShiftImm;
2298 case k_ProcIFlags: {
2299 OS << "<ARM_PROC::";
2300 unsigned IFlags = getProcIFlags();
2301 for (int i=2; i >= 0; --i)
2302 if (IFlags & (1 << i))
2303 OS << ARM_PROC::IFlagsToString(1 << i);
2308 OS << "<register " << getReg() << ">";
2310 case k_ShifterImmediate:
2311 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2312 << " #" << ShifterImm.Imm << ">";
2314 case k_ShiftedRegister:
2315 OS << "<so_reg_reg "
2316 << RegShiftedReg.SrcReg << " "
2317 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2318 << " " << RegShiftedReg.ShiftReg << ">";
2320 case k_ShiftedImmediate:
2321 OS << "<so_reg_imm "
2322 << RegShiftedImm.SrcReg << " "
2323 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2324 << " #" << RegShiftedImm.ShiftImm << ">";
2326 case k_RotateImmediate:
2327 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2329 case k_BitfieldDescriptor:
2330 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2331 << ", width: " << Bitfield.Width << ">";
2333 case k_RegisterList:
2334 case k_DPRRegisterList:
2335 case k_SPRRegisterList: {
2336 OS << "<register_list ";
2338 const SmallVectorImpl<unsigned> &RegList = getRegList();
2339 for (SmallVectorImpl<unsigned>::const_iterator
2340 I = RegList.begin(), E = RegList.end(); I != E; ) {
2342 if (++I < E) OS << ", ";
2349 OS << "<vector_list " << VectorList.Count << " * "
2350 << VectorList.RegNum << ">";
2352 case k_VectorListAllLanes:
2353 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2354 << VectorList.RegNum << ">";
2356 case k_VectorListIndexed:
2357 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2358 << VectorList.Count << " * " << VectorList.RegNum << ">";
2361 OS << "'" << getToken() << "'";
2364 OS << "<vectorindex " << getVectorIndex() << ">";
2369 /// @name Auto-generated Match Functions
2372 static unsigned MatchRegisterName(StringRef Name);
2376 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2377 SMLoc &StartLoc, SMLoc &EndLoc) {
2378 StartLoc = Parser.getTok().getLoc();
2379 RegNo = tryParseRegister();
2380 EndLoc = Parser.getTok().getLoc();
2382 return (RegNo == (unsigned)-1);
2385 /// Try to parse a register name. The token must be an Identifier when called,
2386 /// and if it is a register name the token is eaten and the register number is
2387 /// returned. Otherwise return -1.
2389 int ARMAsmParser::tryParseRegister() {
2390 const AsmToken &Tok = Parser.getTok();
2391 if (Tok.isNot(AsmToken::Identifier)) return -1;
2393 std::string lowerCase = Tok.getString().lower();
2394 unsigned RegNum = MatchRegisterName(lowerCase);
2396 RegNum = StringSwitch<unsigned>(lowerCase)
2397 .Case("r13", ARM::SP)
2398 .Case("r14", ARM::LR)
2399 .Case("r15", ARM::PC)
2400 .Case("ip", ARM::R12)
2401 // Additional register name aliases for 'gas' compatibility.
2402 .Case("a1", ARM::R0)
2403 .Case("a2", ARM::R1)
2404 .Case("a3", ARM::R2)
2405 .Case("a4", ARM::R3)
2406 .Case("v1", ARM::R4)
2407 .Case("v2", ARM::R5)
2408 .Case("v3", ARM::R6)
2409 .Case("v4", ARM::R7)
2410 .Case("v5", ARM::R8)
2411 .Case("v6", ARM::R9)
2412 .Case("v7", ARM::R10)
2413 .Case("v8", ARM::R11)
2414 .Case("sb", ARM::R9)
2415 .Case("sl", ARM::R10)
2416 .Case("fp", ARM::R11)
2420 // Check for aliases registered via .req. Canonicalize to lower case.
2421 // That's more consistent since register names are case insensitive, and
2422 // it's how the original entry was passed in from MC/MCParser/AsmParser.
2423 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2424 // If no match, return failure.
2425 if (Entry == RegisterReqs.end())
2427 Parser.Lex(); // Eat identifier token.
2428 return Entry->getValue();
2431 Parser.Lex(); // Eat identifier token.
2436 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
2437 // If a recoverable error occurs, return 1. If an irrecoverable error
2438 // occurs, return -1. An irrecoverable error is one where tokens have been
2439 // consumed in the process of trying to parse the shifter (i.e., when it is
2440 // indeed a shifter operand, but malformed).
2441 int ARMAsmParser::tryParseShiftRegister(
2442 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2443 SMLoc S = Parser.getTok().getLoc();
2444 const AsmToken &Tok = Parser.getTok();
2445 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2447 std::string lowerCase = Tok.getString().lower();
2448 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2449 .Case("asl", ARM_AM::lsl)
2450 .Case("lsl", ARM_AM::lsl)
2451 .Case("lsr", ARM_AM::lsr)
2452 .Case("asr", ARM_AM::asr)
2453 .Case("ror", ARM_AM::ror)
2454 .Case("rrx", ARM_AM::rrx)
2455 .Default(ARM_AM::no_shift);
2457 if (ShiftTy == ARM_AM::no_shift)
2460 Parser.Lex(); // Eat the operator.
2462 // The source register for the shift has already been added to the
2463 // operand list, so we need to pop it off and combine it into the shifted
2464 // register operand instead.
2465 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2466 if (!PrevOp->isReg())
2467 return Error(PrevOp->getStartLoc(), "shift must be of a register");
2468 int SrcReg = PrevOp->getReg();
2471 if (ShiftTy == ARM_AM::rrx) {
2472 // RRX Doesn't have an explicit shift amount. The encoder expects
2473 // the shift register to be the same as the source register. Seems odd,
2477 // Figure out if this is shifted by a constant or a register (for non-RRX).
2478 if (Parser.getTok().is(AsmToken::Hash) ||
2479 Parser.getTok().is(AsmToken::Dollar)) {
2480 Parser.Lex(); // Eat hash.
2481 SMLoc ImmLoc = Parser.getTok().getLoc();
2482 const MCExpr *ShiftExpr = 0;
2483 if (getParser().ParseExpression(ShiftExpr)) {
2484 Error(ImmLoc, "invalid immediate shift value");
2487 // The expression must be evaluatable as an immediate.
2488 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2490 Error(ImmLoc, "invalid immediate shift value");
2493 // Range check the immediate.
2494 // lsl, ror: 0 <= imm <= 31
2495 // lsr, asr: 0 <= imm <= 32
2496 Imm = CE->getValue();
2498 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2499 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2500 Error(ImmLoc, "immediate shift value out of range");
2503 // shift by zero is a nop. Always send it through as lsl.
2504 // ('as' compatibility)
2506 ShiftTy = ARM_AM::lsl;
2507 } else if (Parser.getTok().is(AsmToken::Identifier)) {
2508 ShiftReg = tryParseRegister();
2509 SMLoc L = Parser.getTok().getLoc();
2510 if (ShiftReg == -1) {
2511 Error (L, "expected immediate or register in shift operand");
2515 Error (Parser.getTok().getLoc(),
2516 "expected immediate or register in shift operand");
2521 if (ShiftReg && ShiftTy != ARM_AM::rrx)
2522 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2524 S, Parser.getTok().getLoc()));
2526 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2527 S, Parser.getTok().getLoc()));
2533 /// Try to parse a register name. The token must be an Identifier when called.
2534 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
2535 /// if there is a "writeback". 'true' if it's not a register.
2537 /// TODO this is likely to change to allow different register types and or to
2538 /// parse for a specific register type.
2540 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2541 SMLoc S = Parser.getTok().getLoc();
2542 int RegNo = tryParseRegister();
2546 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
2548 const AsmToken &ExclaimTok = Parser.getTok();
2549 if (ExclaimTok.is(AsmToken::Exclaim)) {
2550 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2551 ExclaimTok.getLoc()));
2552 Parser.Lex(); // Eat exclaim token
2556 // Also check for an index operand. This is only legal for vector registers,
2557 // but that'll get caught OK in operand matching, so we don't need to
2558 // explicitly filter everything else out here.
2559 if (Parser.getTok().is(AsmToken::LBrac)) {
2560 SMLoc SIdx = Parser.getTok().getLoc();
2561 Parser.Lex(); // Eat left bracket token.
2563 const MCExpr *ImmVal;
2564 if (getParser().ParseExpression(ImmVal))
2566 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2568 return TokError("immediate value expected for vector index");
2570 SMLoc E = Parser.getTok().getLoc();
2571 if (Parser.getTok().isNot(AsmToken::RBrac))
2572 return Error(E, "']' expected");
2574 Parser.Lex(); // Eat right bracket token.
2576 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2584 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
2585 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2587 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2588 // Use the same layout as the tablegen'erated register name matcher. Ugly,
2590 switch (Name.size()) {
2593 if (Name[0] != CoprocOp)
2609 if (Name[0] != CoprocOp || Name[1] != '1')
2613 case '0': return 10;
2614 case '1': return 11;
2615 case '2': return 12;
2616 case '3': return 13;
2617 case '4': return 14;
2618 case '5': return 15;
2623 /// parseITCondCode - Try to parse a condition code for an IT instruction.
2624 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2625 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2626 SMLoc S = Parser.getTok().getLoc();
2627 const AsmToken &Tok = Parser.getTok();
2628 if (!Tok.is(AsmToken::Identifier))
2629 return MatchOperand_NoMatch;
2630 unsigned CC = StringSwitch<unsigned>(Tok.getString())
2631 .Case("eq", ARMCC::EQ)
2632 .Case("ne", ARMCC::NE)
2633 .Case("hs", ARMCC::HS)
2634 .Case("cs", ARMCC::HS)
2635 .Case("lo", ARMCC::LO)
2636 .Case("cc", ARMCC::LO)
2637 .Case("mi", ARMCC::MI)
2638 .Case("pl", ARMCC::PL)
2639 .Case("vs", ARMCC::VS)
2640 .Case("vc", ARMCC::VC)
2641 .Case("hi", ARMCC::HI)
2642 .Case("ls", ARMCC::LS)
2643 .Case("ge", ARMCC::GE)
2644 .Case("lt", ARMCC::LT)
2645 .Case("gt", ARMCC::GT)
2646 .Case("le", ARMCC::LE)
2647 .Case("al", ARMCC::AL)
2650 return MatchOperand_NoMatch;
2651 Parser.Lex(); // Eat the token.
2653 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2655 return MatchOperand_Success;
2658 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2659 /// token must be an Identifier when called, and if it is a coprocessor
2660 /// number, the token is eaten and the operand is added to the operand list.
2661 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2662 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2663 SMLoc S = Parser.getTok().getLoc();
2664 const AsmToken &Tok = Parser.getTok();
2665 if (Tok.isNot(AsmToken::Identifier))
2666 return MatchOperand_NoMatch;
2668 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2670 return MatchOperand_NoMatch;
2672 Parser.Lex(); // Eat identifier token.
2673 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2674 return MatchOperand_Success;
2677 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2678 /// token must be an Identifier when called, and if it is a coprocessor
2679 /// number, the token is eaten and the operand is added to the operand list.
2680 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2681 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2682 SMLoc S = Parser.getTok().getLoc();
2683 const AsmToken &Tok = Parser.getTok();
2684 if (Tok.isNot(AsmToken::Identifier))
2685 return MatchOperand_NoMatch;
2687 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2689 return MatchOperand_NoMatch;
2691 Parser.Lex(); // Eat identifier token.
2692 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2693 return MatchOperand_Success;
2696 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2697 /// coproc_option : '{' imm0_255 '}'
2698 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2699 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2700 SMLoc S = Parser.getTok().getLoc();
2702 // If this isn't a '{', this isn't a coprocessor immediate operand.
2703 if (Parser.getTok().isNot(AsmToken::LCurly))
2704 return MatchOperand_NoMatch;
2705 Parser.Lex(); // Eat the '{'
2708 SMLoc Loc = Parser.getTok().getLoc();
2709 if (getParser().ParseExpression(Expr)) {
2710 Error(Loc, "illegal expression");
2711 return MatchOperand_ParseFail;
2713 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2714 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2715 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2716 return MatchOperand_ParseFail;
2718 int Val = CE->getValue();
2720 // Check for and consume the closing '}'
2721 if (Parser.getTok().isNot(AsmToken::RCurly))
2722 return MatchOperand_ParseFail;
2723 SMLoc E = Parser.getTok().getLoc();
2724 Parser.Lex(); // Eat the '}'
2726 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2727 return MatchOperand_Success;
2730 // For register list parsing, we need to map from raw GPR register numbering
2731 // to the enumeration values. The enumeration values aren't sorted by
2732 // register number due to our using "sp", "lr" and "pc" as canonical names.
2733 static unsigned getNextRegister(unsigned Reg) {
2734 // If this is a GPR, we need to do it manually, otherwise we can rely
2735 // on the sort ordering of the enumeration since the other reg-classes
2737 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2740 default: llvm_unreachable("Invalid GPR number!");
2741 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
2742 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
2743 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
2744 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
2745 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
2746 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2747 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
2748 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
2752 // Return the low-subreg of a given Q register.
2753 static unsigned getDRegFromQReg(unsigned QReg) {
2755 default: llvm_unreachable("expected a Q register!");
2756 case ARM::Q0: return ARM::D0;
2757 case ARM::Q1: return ARM::D2;
2758 case ARM::Q2: return ARM::D4;
2759 case ARM::Q3: return ARM::D6;
2760 case ARM::Q4: return ARM::D8;
2761 case ARM::Q5: return ARM::D10;
2762 case ARM::Q6: return ARM::D12;
2763 case ARM::Q7: return ARM::D14;
2764 case ARM::Q8: return ARM::D16;
2765 case ARM::Q9: return ARM::D18;
2766 case ARM::Q10: return ARM::D20;
2767 case ARM::Q11: return ARM::D22;
2768 case ARM::Q12: return ARM::D24;
2769 case ARM::Q13: return ARM::D26;
2770 case ARM::Q14: return ARM::D28;
2771 case ARM::Q15: return ARM::D30;
2775 /// Parse a register list.
2777 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2778 assert(Parser.getTok().is(AsmToken::LCurly) &&
2779 "Token is not a Left Curly Brace");
2780 SMLoc S = Parser.getTok().getLoc();
2781 Parser.Lex(); // Eat '{' token.
2782 SMLoc RegLoc = Parser.getTok().getLoc();
2784 // Check the first register in the list to see what register class
2785 // this is a list of.
2786 int Reg = tryParseRegister();
2788 return Error(RegLoc, "register expected");
2790 // The reglist instructions have at most 16 registers, so reserve
2791 // space for that many.
2792 SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
2794 // Allow Q regs and just interpret them as the two D sub-registers.
2795 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2796 Reg = getDRegFromQReg(Reg);
2797 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2800 const MCRegisterClass *RC;
2801 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2802 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
2803 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
2804 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
2805 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
2806 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
2808 return Error(RegLoc, "invalid register in register list");
2810 // Store the register.
2811 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2813 // This starts immediately after the first register token in the list,
2814 // so we can see either a comma or a minus (range separator) as a legal
2816 while (Parser.getTok().is(AsmToken::Comma) ||
2817 Parser.getTok().is(AsmToken::Minus)) {
2818 if (Parser.getTok().is(AsmToken::Minus)) {
2819 Parser.Lex(); // Eat the minus.
2820 SMLoc EndLoc = Parser.getTok().getLoc();
2821 int EndReg = tryParseRegister();
2823 return Error(EndLoc, "register expected");
2824 // Allow Q regs and just interpret them as the two D sub-registers.
2825 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
2826 EndReg = getDRegFromQReg(EndReg) + 1;
2827 // If the register is the same as the start reg, there's nothing
2831 // The register must be in the same register class as the first.
2832 if (!RC->contains(EndReg))
2833 return Error(EndLoc, "invalid register in register list");
2834 // Ranges must go from low to high.
2835 if (getARMRegisterNumbering(Reg) > getARMRegisterNumbering(EndReg))
2836 return Error(EndLoc, "bad range in register list");
2838 // Add all the registers in the range to the register list.
2839 while (Reg != EndReg) {
2840 Reg = getNextRegister(Reg);
2841 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2845 Parser.Lex(); // Eat the comma.
2846 RegLoc = Parser.getTok().getLoc();
2848 const AsmToken RegTok = Parser.getTok();
2849 Reg = tryParseRegister();
2851 return Error(RegLoc, "register expected");
2852 // Allow Q regs and just interpret them as the two D sub-registers.
2853 bool isQReg = false;
2854 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2855 Reg = getDRegFromQReg(Reg);
2858 // The register must be in the same register class as the first.
2859 if (!RC->contains(Reg))
2860 return Error(RegLoc, "invalid register in register list");
2861 // List must be monotonically increasing.
2862 if (getARMRegisterNumbering(Reg) < getARMRegisterNumbering(OldReg))
2863 return Error(RegLoc, "register list not in ascending order");
2864 if (getARMRegisterNumbering(Reg) == getARMRegisterNumbering(OldReg)) {
2865 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
2866 ") in register list");
2869 // VFP register lists must also be contiguous.
2870 // It's OK to use the enumeration values directly here rather, as the
2871 // VFP register classes have the enum sorted properly.
2872 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
2874 return Error(RegLoc, "non-contiguous register range");
2875 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2877 Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc));
2880 SMLoc E = Parser.getTok().getLoc();
2881 if (Parser.getTok().isNot(AsmToken::RCurly))
2882 return Error(E, "'}' expected");
2883 Parser.Lex(); // Eat '}' token.
2885 // Push the register list operand.
2886 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
2888 // The ARM system instruction variants for LDM/STM have a '^' token here.
2889 if (Parser.getTok().is(AsmToken::Caret)) {
2890 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
2891 Parser.Lex(); // Eat '^' token.
2897 // Helper function to parse the lane index for vector lists.
2898 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2899 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index) {
2900 Index = 0; // Always return a defined index value.
2901 if (Parser.getTok().is(AsmToken::LBrac)) {
2902 Parser.Lex(); // Eat the '['.
2903 if (Parser.getTok().is(AsmToken::RBrac)) {
2904 // "Dn[]" is the 'all lanes' syntax.
2905 LaneKind = AllLanes;
2906 Parser.Lex(); // Eat the ']'.
2907 return MatchOperand_Success;
2909 const MCExpr *LaneIndex;
2910 SMLoc Loc = Parser.getTok().getLoc();
2911 if (getParser().ParseExpression(LaneIndex)) {
2912 Error(Loc, "illegal expression");
2913 return MatchOperand_ParseFail;
2915 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
2917 Error(Loc, "lane index must be empty or an integer");
2918 return MatchOperand_ParseFail;
2920 if (Parser.getTok().isNot(AsmToken::RBrac)) {
2921 Error(Parser.getTok().getLoc(), "']' expected");
2922 return MatchOperand_ParseFail;
2924 Parser.Lex(); // Eat the ']'.
2925 int64_t Val = CE->getValue();
2927 // FIXME: Make this range check context sensitive for .8, .16, .32.
2928 if (Val < 0 || Val > 7) {
2929 Error(Parser.getTok().getLoc(), "lane index out of range");
2930 return MatchOperand_ParseFail;
2933 LaneKind = IndexedLane;
2934 return MatchOperand_Success;
2937 return MatchOperand_Success;
2940 // parse a vector register list
2941 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2942 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2943 VectorLaneTy LaneKind;
2945 SMLoc S = Parser.getTok().getLoc();
2946 // As an extension (to match gas), support a plain D register or Q register
2947 // (without encosing curly braces) as a single or double entry list,
2949 if (Parser.getTok().is(AsmToken::Identifier)) {
2950 int Reg = tryParseRegister();
2952 return MatchOperand_NoMatch;
2953 SMLoc E = Parser.getTok().getLoc();
2954 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
2955 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex);
2956 if (Res != MatchOperand_Success)
2960 E = Parser.getTok().getLoc();
2961 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
2964 E = Parser.getTok().getLoc();
2965 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
2969 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
2974 return MatchOperand_Success;
2976 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2977 Reg = getDRegFromQReg(Reg);
2978 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex);
2979 if (Res != MatchOperand_Success)
2983 E = Parser.getTok().getLoc();
2984 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
2985 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
2986 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
2989 E = Parser.getTok().getLoc();
2990 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
2991 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
2992 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
2996 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3001 return MatchOperand_Success;
3003 Error(S, "vector register expected");
3004 return MatchOperand_ParseFail;
3007 if (Parser.getTok().isNot(AsmToken::LCurly))
3008 return MatchOperand_NoMatch;
3010 Parser.Lex(); // Eat '{' token.
3011 SMLoc RegLoc = Parser.getTok().getLoc();
3013 int Reg = tryParseRegister();
3015 Error(RegLoc, "register expected");
3016 return MatchOperand_ParseFail;
3020 unsigned FirstReg = Reg;
3021 // The list is of D registers, but we also allow Q regs and just interpret
3022 // them as the two D sub-registers.
3023 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3024 FirstReg = Reg = getDRegFromQReg(Reg);
3025 Spacing = 1; // double-spacing requires explicit D registers, otherwise
3026 // it's ambiguous with four-register single spaced.
3030 if (parseVectorLane(LaneKind, LaneIndex) != MatchOperand_Success)
3031 return MatchOperand_ParseFail;
3033 while (Parser.getTok().is(AsmToken::Comma) ||
3034 Parser.getTok().is(AsmToken::Minus)) {
3035 if (Parser.getTok().is(AsmToken::Minus)) {
3037 Spacing = 1; // Register range implies a single spaced list.
3038 else if (Spacing == 2) {
3039 Error(Parser.getTok().getLoc(),
3040 "sequential registers in double spaced list");
3041 return MatchOperand_ParseFail;
3043 Parser.Lex(); // Eat the minus.
3044 SMLoc EndLoc = Parser.getTok().getLoc();
3045 int EndReg = tryParseRegister();
3047 Error(EndLoc, "register expected");
3048 return MatchOperand_ParseFail;
3050 // Allow Q regs and just interpret them as the two D sub-registers.
3051 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3052 EndReg = getDRegFromQReg(EndReg) + 1;
3053 // If the register is the same as the start reg, there's nothing
3057 // The register must be in the same register class as the first.
3058 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3059 Error(EndLoc, "invalid register in register list");
3060 return MatchOperand_ParseFail;
3062 // Ranges must go from low to high.
3064 Error(EndLoc, "bad range in register list");
3065 return MatchOperand_ParseFail;
3067 // Parse the lane specifier if present.
3068 VectorLaneTy NextLaneKind;
3069 unsigned NextLaneIndex;
3070 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
3071 return MatchOperand_ParseFail;
3072 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3073 Error(EndLoc, "mismatched lane index in register list");
3074 return MatchOperand_ParseFail;
3076 EndLoc = Parser.getTok().getLoc();
3078 // Add all the registers in the range to the register list.
3079 Count += EndReg - Reg;
3083 Parser.Lex(); // Eat the comma.
3084 RegLoc = Parser.getTok().getLoc();
3086 Reg = tryParseRegister();
3088 Error(RegLoc, "register expected");
3089 return MatchOperand_ParseFail;
3091 // vector register lists must be contiguous.
3092 // It's OK to use the enumeration values directly here rather, as the
3093 // VFP register classes have the enum sorted properly.
3095 // The list is of D registers, but we also allow Q regs and just interpret
3096 // them as the two D sub-registers.
3097 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3099 Spacing = 1; // Register range implies a single spaced list.
3100 else if (Spacing == 2) {
3102 "invalid register in double-spaced list (must be 'D' register')");
3103 return MatchOperand_ParseFail;
3105 Reg = getDRegFromQReg(Reg);
3106 if (Reg != OldReg + 1) {
3107 Error(RegLoc, "non-contiguous register range");
3108 return MatchOperand_ParseFail;
3112 // Parse the lane specifier if present.
3113 VectorLaneTy NextLaneKind;
3114 unsigned NextLaneIndex;
3115 SMLoc EndLoc = Parser.getTok().getLoc();
3116 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
3117 return MatchOperand_ParseFail;
3118 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3119 Error(EndLoc, "mismatched lane index in register list");
3120 return MatchOperand_ParseFail;
3124 // Normal D register.
3125 // Figure out the register spacing (single or double) of the list if
3126 // we don't know it already.
3128 Spacing = 1 + (Reg == OldReg + 2);
3130 // Just check that it's contiguous and keep going.
3131 if (Reg != OldReg + Spacing) {
3132 Error(RegLoc, "non-contiguous register range");
3133 return MatchOperand_ParseFail;
3136 // Parse the lane specifier if present.
3137 VectorLaneTy NextLaneKind;
3138 unsigned NextLaneIndex;
3139 SMLoc EndLoc = Parser.getTok().getLoc();
3140 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
3141 return MatchOperand_ParseFail;
3142 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3143 Error(EndLoc, "mismatched lane index in register list");
3144 return MatchOperand_ParseFail;
3148 SMLoc E = Parser.getTok().getLoc();
3149 if (Parser.getTok().isNot(AsmToken::RCurly)) {
3150 Error(E, "'}' expected");
3151 return MatchOperand_ParseFail;
3153 Parser.Lex(); // Eat '}' token.
3157 // Two-register operands have been converted to the
3158 // composite register classes.
3160 const MCRegisterClass *RC = (Spacing == 1) ?
3161 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3162 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3163 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3166 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3167 (Spacing == 2), S, E));
3170 // Two-register operands have been converted to the
3171 // composite register classes.
3172 if (Count == 2 && Spacing == 1) {
3173 const MCRegisterClass *RC = &ARMMCRegisterClasses[ARM::DPairRegClassID];
3174 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3176 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3181 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3187 return MatchOperand_Success;
3190 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3191 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3192 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3193 SMLoc S = Parser.getTok().getLoc();
3194 const AsmToken &Tok = Parser.getTok();
3195 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
3196 StringRef OptStr = Tok.getString();
3198 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
3199 .Case("sy", ARM_MB::SY)
3200 .Case("st", ARM_MB::ST)
3201 .Case("sh", ARM_MB::ISH)
3202 .Case("ish", ARM_MB::ISH)
3203 .Case("shst", ARM_MB::ISHST)
3204 .Case("ishst", ARM_MB::ISHST)
3205 .Case("nsh", ARM_MB::NSH)
3206 .Case("un", ARM_MB::NSH)
3207 .Case("nshst", ARM_MB::NSHST)
3208 .Case("unst", ARM_MB::NSHST)
3209 .Case("osh", ARM_MB::OSH)
3210 .Case("oshst", ARM_MB::OSHST)
3214 return MatchOperand_NoMatch;
3216 Parser.Lex(); // Eat identifier token.
3217 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3218 return MatchOperand_Success;
3221 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3222 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3223 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3224 SMLoc S = Parser.getTok().getLoc();
3225 const AsmToken &Tok = Parser.getTok();
3226 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
3227 StringRef IFlagsStr = Tok.getString();
3229 // An iflags string of "none" is interpreted to mean that none of the AIF
3230 // bits are set. Not a terribly useful instruction, but a valid encoding.
3231 unsigned IFlags = 0;
3232 if (IFlagsStr != "none") {
3233 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3234 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3235 .Case("a", ARM_PROC::A)
3236 .Case("i", ARM_PROC::I)
3237 .Case("f", ARM_PROC::F)
3240 // If some specific iflag is already set, it means that some letter is
3241 // present more than once, this is not acceptable.
3242 if (Flag == ~0U || (IFlags & Flag))
3243 return MatchOperand_NoMatch;
3249 Parser.Lex(); // Eat identifier token.
3250 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3251 return MatchOperand_Success;
3254 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3255 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3256 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3257 SMLoc S = Parser.getTok().getLoc();
3258 const AsmToken &Tok = Parser.getTok();
3259 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
3260 StringRef Mask = Tok.getString();
3263 // See ARMv6-M 10.1.1
3264 unsigned FlagsVal = StringSwitch<unsigned>(Mask)
3274 .Case("primask", 16)
3275 .Case("basepri", 17)
3276 .Case("basepri_max", 18)
3277 .Case("faultmask", 19)
3278 .Case("control", 20)
3281 if (FlagsVal == ~0U)
3282 return MatchOperand_NoMatch;
3284 if (!hasV7Ops() && FlagsVal >= 17 && FlagsVal <= 19)
3285 // basepri, basepri_max and faultmask only valid for V7m.
3286 return MatchOperand_NoMatch;
3288 Parser.Lex(); // Eat identifier token.
3289 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3290 return MatchOperand_Success;
3293 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3294 size_t Start = 0, Next = Mask.find('_');
3295 StringRef Flags = "";
3296 std::string SpecReg = Mask.slice(Start, Next).lower();
3297 if (Next != StringRef::npos)
3298 Flags = Mask.slice(Next+1, Mask.size());
3300 // FlagsVal contains the complete mask:
3302 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3303 unsigned FlagsVal = 0;
3305 if (SpecReg == "apsr") {
3306 FlagsVal = StringSwitch<unsigned>(Flags)
3307 .Case("nzcvq", 0x8) // same as CPSR_f
3308 .Case("g", 0x4) // same as CPSR_s
3309 .Case("nzcvqg", 0xc) // same as CPSR_fs
3312 if (FlagsVal == ~0U) {
3314 return MatchOperand_NoMatch;
3316 FlagsVal = 8; // No flag
3318 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3319 if (Flags == "all") // cpsr_all is an alias for cpsr_fc
3321 for (int i = 0, e = Flags.size(); i != e; ++i) {
3322 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3329 // If some specific flag is already set, it means that some letter is
3330 // present more than once, this is not acceptable.
3331 if (FlagsVal == ~0U || (FlagsVal & Flag))
3332 return MatchOperand_NoMatch;
3335 } else // No match for special register.
3336 return MatchOperand_NoMatch;
3338 // Special register without flags is NOT equivalent to "fc" flags.
3339 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
3340 // two lines would enable gas compatibility at the expense of breaking
3346 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3347 if (SpecReg == "spsr")
3350 Parser.Lex(); // Eat identifier token.
3351 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3352 return MatchOperand_Success;
3355 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3356 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3357 int Low, int High) {
3358 const AsmToken &Tok = Parser.getTok();
3359 if (Tok.isNot(AsmToken::Identifier)) {
3360 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3361 return MatchOperand_ParseFail;
3363 StringRef ShiftName = Tok.getString();
3364 std::string LowerOp = Op.lower();
3365 std::string UpperOp = Op.upper();
3366 if (ShiftName != LowerOp && ShiftName != UpperOp) {
3367 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3368 return MatchOperand_ParseFail;
3370 Parser.Lex(); // Eat shift type token.
3372 // There must be a '#' and a shift amount.
3373 if (Parser.getTok().isNot(AsmToken::Hash) &&
3374 Parser.getTok().isNot(AsmToken::Dollar)) {
3375 Error(Parser.getTok().getLoc(), "'#' expected");
3376 return MatchOperand_ParseFail;
3378 Parser.Lex(); // Eat hash token.
3380 const MCExpr *ShiftAmount;
3381 SMLoc Loc = Parser.getTok().getLoc();
3382 if (getParser().ParseExpression(ShiftAmount)) {
3383 Error(Loc, "illegal expression");
3384 return MatchOperand_ParseFail;
3386 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3388 Error(Loc, "constant expression expected");
3389 return MatchOperand_ParseFail;
3391 int Val = CE->getValue();
3392 if (Val < Low || Val > High) {
3393 Error(Loc, "immediate value out of range");
3394 return MatchOperand_ParseFail;
3397 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
3399 return MatchOperand_Success;
3402 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3403 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3404 const AsmToken &Tok = Parser.getTok();
3405 SMLoc S = Tok.getLoc();
3406 if (Tok.isNot(AsmToken::Identifier)) {
3407 Error(Tok.getLoc(), "'be' or 'le' operand expected");
3408 return MatchOperand_ParseFail;
3410 int Val = StringSwitch<int>(Tok.getString())
3414 Parser.Lex(); // Eat the token.
3417 Error(Tok.getLoc(), "'be' or 'le' operand expected");
3418 return MatchOperand_ParseFail;
3420 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3422 S, Parser.getTok().getLoc()));
3423 return MatchOperand_Success;
3426 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3427 /// instructions. Legal values are:
3428 /// lsl #n 'n' in [0,31]
3429 /// asr #n 'n' in [1,32]
3430 /// n == 32 encoded as n == 0.
3431 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3432 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3433 const AsmToken &Tok = Parser.getTok();
3434 SMLoc S = Tok.getLoc();
3435 if (Tok.isNot(AsmToken::Identifier)) {
3436 Error(S, "shift operator 'asr' or 'lsl' expected");
3437 return MatchOperand_ParseFail;
3439 StringRef ShiftName = Tok.getString();
3441 if (ShiftName == "lsl" || ShiftName == "LSL")
3443 else if (ShiftName == "asr" || ShiftName == "ASR")
3446 Error(S, "shift operator 'asr' or 'lsl' expected");
3447 return MatchOperand_ParseFail;
3449 Parser.Lex(); // Eat the operator.
3451 // A '#' and a shift amount.
3452 if (Parser.getTok().isNot(AsmToken::Hash) &&
3453 Parser.getTok().isNot(AsmToken::Dollar)) {
3454 Error(Parser.getTok().getLoc(), "'#' expected");
3455 return MatchOperand_ParseFail;
3457 Parser.Lex(); // Eat hash token.
3459 const MCExpr *ShiftAmount;
3460 SMLoc E = Parser.getTok().getLoc();
3461 if (getParser().ParseExpression(ShiftAmount)) {
3462 Error(E, "malformed shift expression");
3463 return MatchOperand_ParseFail;
3465 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3467 Error(E, "shift amount must be an immediate");
3468 return MatchOperand_ParseFail;
3471 int64_t Val = CE->getValue();
3473 // Shift amount must be in [1,32]
3474 if (Val < 1 || Val > 32) {
3475 Error(E, "'asr' shift amount must be in range [1,32]");
3476 return MatchOperand_ParseFail;
3478 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3479 if (isThumb() && Val == 32) {
3480 Error(E, "'asr #32' shift amount not allowed in Thumb mode");
3481 return MatchOperand_ParseFail;
3483 if (Val == 32) Val = 0;
3485 // Shift amount must be in [1,32]
3486 if (Val < 0 || Val > 31) {
3487 Error(E, "'lsr' shift amount must be in range [0,31]");
3488 return MatchOperand_ParseFail;
3492 E = Parser.getTok().getLoc();
3493 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
3495 return MatchOperand_Success;
3498 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3499 /// of instructions. Legal values are:
3500 /// ror #n 'n' in {0, 8, 16, 24}
3501 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3502 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3503 const AsmToken &Tok = Parser.getTok();
3504 SMLoc S = Tok.getLoc();
3505 if (Tok.isNot(AsmToken::Identifier))
3506 return MatchOperand_NoMatch;
3507 StringRef ShiftName = Tok.getString();
3508 if (ShiftName != "ror" && ShiftName != "ROR")
3509 return MatchOperand_NoMatch;
3510 Parser.Lex(); // Eat the operator.
3512 // A '#' and a rotate amount.
3513 if (Parser.getTok().isNot(AsmToken::Hash) &&
3514 Parser.getTok().isNot(AsmToken::Dollar)) {
3515 Error(Parser.getTok().getLoc(), "'#' expected");
3516 return MatchOperand_ParseFail;
3518 Parser.Lex(); // Eat hash token.
3520 const MCExpr *ShiftAmount;
3521 SMLoc E = Parser.getTok().getLoc();
3522 if (getParser().ParseExpression(ShiftAmount)) {
3523 Error(E, "malformed rotate expression");
3524 return MatchOperand_ParseFail;
3526 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3528 Error(E, "rotate amount must be an immediate");
3529 return MatchOperand_ParseFail;
3532 int64_t Val = CE->getValue();
3533 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
3534 // normally, zero is represented in asm by omitting the rotate operand
3536 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
3537 Error(E, "'ror' rotate amount must be 8, 16, or 24");
3538 return MatchOperand_ParseFail;
3541 E = Parser.getTok().getLoc();
3542 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
3544 return MatchOperand_Success;
3547 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3548 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3549 SMLoc S = Parser.getTok().getLoc();
3550 // The bitfield descriptor is really two operands, the LSB and the width.
3551 if (Parser.getTok().isNot(AsmToken::Hash) &&
3552 Parser.getTok().isNot(AsmToken::Dollar)) {
3553 Error(Parser.getTok().getLoc(), "'#' expected");
3554 return MatchOperand_ParseFail;
3556 Parser.Lex(); // Eat hash token.
3558 const MCExpr *LSBExpr;
3559 SMLoc E = Parser.getTok().getLoc();
3560 if (getParser().ParseExpression(LSBExpr)) {
3561 Error(E, "malformed immediate expression");
3562 return MatchOperand_ParseFail;
3564 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
3566 Error(E, "'lsb' operand must be an immediate");
3567 return MatchOperand_ParseFail;
3570 int64_t LSB = CE->getValue();
3571 // The LSB must be in the range [0,31]
3572 if (LSB < 0 || LSB > 31) {
3573 Error(E, "'lsb' operand must be in the range [0,31]");
3574 return MatchOperand_ParseFail;
3576 E = Parser.getTok().getLoc();
3578 // Expect another immediate operand.
3579 if (Parser.getTok().isNot(AsmToken::Comma)) {
3580 Error(Parser.getTok().getLoc(), "too few operands");
3581 return MatchOperand_ParseFail;
3583 Parser.Lex(); // Eat hash token.
3584 if (Parser.getTok().isNot(AsmToken::Hash) &&
3585 Parser.getTok().isNot(AsmToken::Dollar)) {
3586 Error(Parser.getTok().getLoc(), "'#' expected");
3587 return MatchOperand_ParseFail;
3589 Parser.Lex(); // Eat hash token.
3591 const MCExpr *WidthExpr;
3592 if (getParser().ParseExpression(WidthExpr)) {
3593 Error(E, "malformed immediate expression");
3594 return MatchOperand_ParseFail;
3596 CE = dyn_cast<MCConstantExpr>(WidthExpr);
3598 Error(E, "'width' operand must be an immediate");
3599 return MatchOperand_ParseFail;
3602 int64_t Width = CE->getValue();
3603 // The LSB must be in the range [1,32-lsb]
3604 if (Width < 1 || Width > 32 - LSB) {
3605 Error(E, "'width' operand must be in the range [1,32-lsb]");
3606 return MatchOperand_ParseFail;
3608 E = Parser.getTok().getLoc();
3610 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
3612 return MatchOperand_Success;
3615 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3616 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3617 // Check for a post-index addressing register operand. Specifically:
3618 // postidx_reg := '+' register {, shift}
3619 // | '-' register {, shift}
3620 // | register {, shift}
3622 // This method must return MatchOperand_NoMatch without consuming any tokens
3623 // in the case where there is no match, as other alternatives take other
3625 AsmToken Tok = Parser.getTok();
3626 SMLoc S = Tok.getLoc();
3627 bool haveEaten = false;
3630 if (Tok.is(AsmToken::Plus)) {
3631 Parser.Lex(); // Eat the '+' token.
3633 } else if (Tok.is(AsmToken::Minus)) {
3634 Parser.Lex(); // Eat the '-' token.
3638 if (Parser.getTok().is(AsmToken::Identifier))
3639 Reg = tryParseRegister();
3642 return MatchOperand_NoMatch;
3643 Error(Parser.getTok().getLoc(), "register expected");
3644 return MatchOperand_ParseFail;
3646 SMLoc E = Parser.getTok().getLoc();
3648 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
3649 unsigned ShiftImm = 0;
3650 if (Parser.getTok().is(AsmToken::Comma)) {
3651 Parser.Lex(); // Eat the ','.
3652 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
3653 return MatchOperand_ParseFail;
3656 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
3659 return MatchOperand_Success;
3662 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3663 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3664 // Check for a post-index addressing register operand. Specifically:
3665 // am3offset := '+' register
3672 // This method must return MatchOperand_NoMatch without consuming any tokens
3673 // in the case where there is no match, as other alternatives take other
3675 AsmToken Tok = Parser.getTok();
3676 SMLoc S = Tok.getLoc();
3678 // Do immediates first, as we always parse those if we have a '#'.
3679 if (Parser.getTok().is(AsmToken::Hash) ||
3680 Parser.getTok().is(AsmToken::Dollar)) {
3681 Parser.Lex(); // Eat the '#'.
3682 // Explicitly look for a '-', as we need to encode negative zero
3684 bool isNegative = Parser.getTok().is(AsmToken::Minus);
3685 const MCExpr *Offset;
3686 if (getParser().ParseExpression(Offset))
3687 return MatchOperand_ParseFail;
3688 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
3690 Error(S, "constant expression expected");
3691 return MatchOperand_ParseFail;
3693 SMLoc E = Tok.getLoc();
3694 // Negative zero is encoded as the flag value INT32_MIN.
3695 int32_t Val = CE->getValue();
3696 if (isNegative && Val == 0)
3700 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
3702 return MatchOperand_Success;
3706 bool haveEaten = false;
3709 if (Tok.is(AsmToken::Plus)) {
3710 Parser.Lex(); // Eat the '+' token.
3712 } else if (Tok.is(AsmToken::Minus)) {
3713 Parser.Lex(); // Eat the '-' token.
3717 if (Parser.getTok().is(AsmToken::Identifier))
3718 Reg = tryParseRegister();
3721 return MatchOperand_NoMatch;
3722 Error(Parser.getTok().getLoc(), "register expected");
3723 return MatchOperand_ParseFail;
3725 SMLoc E = Parser.getTok().getLoc();
3727 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
3730 return MatchOperand_Success;
3733 /// cvtT2LdrdPre - Convert parsed operands to MCInst.
3734 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3735 /// when they refer multiple MIOperands inside a single one.
3737 cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
3738 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3740 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3741 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3742 // Create a writeback register dummy placeholder.
3743 Inst.addOperand(MCOperand::CreateReg(0));
3745 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3747 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3751 /// cvtT2StrdPre - Convert parsed operands to MCInst.
3752 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3753 /// when they refer multiple MIOperands inside a single one.
3755 cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
3756 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3757 // Create a writeback register dummy placeholder.
3758 Inst.addOperand(MCOperand::CreateReg(0));
3760 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3761 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3763 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3765 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3769 /// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3770 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3771 /// when they refer multiple MIOperands inside a single one.
3773 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3774 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3775 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3777 // Create a writeback register dummy placeholder.
3778 Inst.addOperand(MCOperand::CreateImm(0));
3780 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3781 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3785 /// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3786 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3787 /// when they refer multiple MIOperands inside a single one.
3789 cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3790 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3791 // Create a writeback register dummy placeholder.
3792 Inst.addOperand(MCOperand::CreateImm(0));
3793 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3794 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3795 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3799 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3800 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3801 /// when they refer multiple MIOperands inside a single one.
3803 cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3804 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3805 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3807 // Create a writeback register dummy placeholder.
3808 Inst.addOperand(MCOperand::CreateImm(0));
3810 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3811 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3815 /// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3816 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3817 /// when they refer multiple MIOperands inside a single one.
3819 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3820 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3821 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3823 // Create a writeback register dummy placeholder.
3824 Inst.addOperand(MCOperand::CreateImm(0));
3826 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3827 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3832 /// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3833 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3834 /// when they refer multiple MIOperands inside a single one.
3836 cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3837 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3838 // Create a writeback register dummy placeholder.
3839 Inst.addOperand(MCOperand::CreateImm(0));
3840 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3841 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3842 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3846 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3847 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3848 /// when they refer multiple MIOperands inside a single one.
3850 cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3851 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3852 // Create a writeback register dummy placeholder.
3853 Inst.addOperand(MCOperand::CreateImm(0));
3854 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3855 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3856 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3860 /// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
3861 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3862 /// when they refer multiple MIOperands inside a single one.
3864 cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
3865 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3866 // Create a writeback register dummy placeholder.
3867 Inst.addOperand(MCOperand::CreateImm(0));
3868 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3869 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
3870 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3874 /// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
3875 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3876 /// when they refer multiple MIOperands inside a single one.
3878 cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
3879 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3881 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3882 // Create a writeback register dummy placeholder.
3883 Inst.addOperand(MCOperand::CreateImm(0));
3885 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3887 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
3889 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3893 /// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
3894 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3895 /// when they refer multiple MIOperands inside a single one.
3897 cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
3898 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3900 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3901 // Create a writeback register dummy placeholder.
3902 Inst.addOperand(MCOperand::CreateImm(0));
3904 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3906 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
3908 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3912 /// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
3913 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3914 /// when they refer multiple MIOperands inside a single one.
3916 cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
3917 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3918 // Create a writeback register dummy placeholder.
3919 Inst.addOperand(MCOperand::CreateImm(0));
3921 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3923 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3925 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
3927 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3931 /// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
3932 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3933 /// when they refer multiple MIOperands inside a single one.
3935 cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
3936 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3937 // Create a writeback register dummy placeholder.
3938 Inst.addOperand(MCOperand::CreateImm(0));
3940 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3942 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3944 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
3946 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3950 /// cvtLdrdPre - Convert parsed operands to MCInst.
3951 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3952 /// when they refer multiple MIOperands inside a single one.
3954 cvtLdrdPre(MCInst &Inst, unsigned Opcode,
3955 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3957 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3958 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3959 // Create a writeback register dummy placeholder.
3960 Inst.addOperand(MCOperand::CreateImm(0));
3962 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
3964 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3968 /// cvtStrdPre - Convert parsed operands to MCInst.
3969 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3970 /// when they refer multiple MIOperands inside a single one.
3972 cvtStrdPre(MCInst &Inst, unsigned Opcode,
3973 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3974 // Create a writeback register dummy placeholder.
3975 Inst.addOperand(MCOperand::CreateImm(0));
3977 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3978 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3980 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
3982 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3986 /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
3987 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3988 /// when they refer multiple MIOperands inside a single one.
3990 cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
3991 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3992 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3993 // Create a writeback register dummy placeholder.
3994 Inst.addOperand(MCOperand::CreateImm(0));
3995 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
3996 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4000 /// cvtThumbMultiple- Convert parsed operands to MCInst.
4001 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4002 /// when they refer multiple MIOperands inside a single one.
4004 cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
4005 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4006 // The second source operand must be the same register as the destination
4008 if (Operands.size() == 6 &&
4009 (((ARMOperand*)Operands[3])->getReg() !=
4010 ((ARMOperand*)Operands[5])->getReg()) &&
4011 (((ARMOperand*)Operands[3])->getReg() !=
4012 ((ARMOperand*)Operands[4])->getReg())) {
4013 Error(Operands[3]->getStartLoc(),
4014 "destination register must match source register");
4017 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4018 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4019 // If we have a three-operand form, make sure to set Rn to be the operand
4020 // that isn't the same as Rd.
4022 if (Operands.size() == 6 &&
4023 ((ARMOperand*)Operands[4])->getReg() ==
4024 ((ARMOperand*)Operands[3])->getReg())
4026 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4027 Inst.addOperand(Inst.getOperand(0));
4028 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4034 cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
4035 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4037 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4038 // Create a writeback register dummy placeholder.
4039 Inst.addOperand(MCOperand::CreateImm(0));
4041 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4043 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4048 cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
4049 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4051 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4052 // Create a writeback register dummy placeholder.
4053 Inst.addOperand(MCOperand::CreateImm(0));
4055 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4057 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4059 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4064 cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
4065 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4066 // Create a writeback register dummy placeholder.
4067 Inst.addOperand(MCOperand::CreateImm(0));
4069 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4071 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4073 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4078 cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
4079 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4080 // Create a writeback register dummy placeholder.
4081 Inst.addOperand(MCOperand::CreateImm(0));
4083 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4085 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4087 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4089 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4093 /// Parse an ARM memory expression, return false if successful else return true
4094 /// or an error. The first token must be a '[' when called.
4096 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4098 assert(Parser.getTok().is(AsmToken::LBrac) &&
4099 "Token is not a Left Bracket");
4100 S = Parser.getTok().getLoc();
4101 Parser.Lex(); // Eat left bracket token.
4103 const AsmToken &BaseRegTok = Parser.getTok();
4104 int BaseRegNum = tryParseRegister();
4105 if (BaseRegNum == -1)
4106 return Error(BaseRegTok.getLoc(), "register expected");
4108 // The next token must either be a comma or a closing bracket.
4109 const AsmToken &Tok = Parser.getTok();
4110 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
4111 return Error(Tok.getLoc(), "malformed memory operand");
4113 if (Tok.is(AsmToken::RBrac)) {
4115 Parser.Lex(); // Eat right bracket token.
4117 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4118 0, 0, false, S, E));
4120 // If there's a pre-indexing writeback marker, '!', just add it as a token
4121 // operand. It's rather odd, but syntactically valid.
4122 if (Parser.getTok().is(AsmToken::Exclaim)) {
4123 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4124 Parser.Lex(); // Eat the '!'.
4130 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
4131 Parser.Lex(); // Eat the comma.
4133 // If we have a ':', it's an alignment specifier.
4134 if (Parser.getTok().is(AsmToken::Colon)) {
4135 Parser.Lex(); // Eat the ':'.
4136 E = Parser.getTok().getLoc();
4139 if (getParser().ParseExpression(Expr))
4142 // The expression has to be a constant. Memory references with relocations
4143 // don't come through here, as they use the <label> forms of the relevant
4145 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4147 return Error (E, "constant expression expected");
4150 switch (CE->getValue()) {
4153 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4154 case 16: Align = 2; break;
4155 case 32: Align = 4; break;
4156 case 64: Align = 8; break;
4157 case 128: Align = 16; break;
4158 case 256: Align = 32; break;
4161 // Now we should have the closing ']'
4162 E = Parser.getTok().getLoc();
4163 if (Parser.getTok().isNot(AsmToken::RBrac))
4164 return Error(E, "']' expected");
4165 Parser.Lex(); // Eat right bracket token.
4167 // Don't worry about range checking the value here. That's handled by
4168 // the is*() predicates.
4169 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4170 ARM_AM::no_shift, 0, Align,
4173 // If there's a pre-indexing writeback marker, '!', just add it as a token
4175 if (Parser.getTok().is(AsmToken::Exclaim)) {
4176 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4177 Parser.Lex(); // Eat the '!'.
4183 // If we have a '#', it's an immediate offset, else assume it's a register
4184 // offset. Be friendly and also accept a plain integer (without a leading
4185 // hash) for gas compatibility.
4186 if (Parser.getTok().is(AsmToken::Hash) ||
4187 Parser.getTok().is(AsmToken::Dollar) ||
4188 Parser.getTok().is(AsmToken::Integer)) {
4189 if (Parser.getTok().isNot(AsmToken::Integer))
4190 Parser.Lex(); // Eat the '#'.
4191 E = Parser.getTok().getLoc();
4193 bool isNegative = getParser().getTok().is(AsmToken::Minus);
4194 const MCExpr *Offset;
4195 if (getParser().ParseExpression(Offset))
4198 // The expression has to be a constant. Memory references with relocations
4199 // don't come through here, as they use the <label> forms of the relevant
4201 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4203 return Error (E, "constant expression expected");
4205 // If the constant was #-0, represent it as INT32_MIN.
4206 int32_t Val = CE->getValue();
4207 if (isNegative && Val == 0)
4208 CE = MCConstantExpr::Create(INT32_MIN, getContext());
4210 // Now we should have the closing ']'
4211 E = Parser.getTok().getLoc();
4212 if (Parser.getTok().isNot(AsmToken::RBrac))
4213 return Error(E, "']' expected");
4214 Parser.Lex(); // Eat right bracket token.
4216 // Don't worry about range checking the value here. That's handled by
4217 // the is*() predicates.
4218 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4219 ARM_AM::no_shift, 0, 0,
4222 // If there's a pre-indexing writeback marker, '!', just add it as a token
4224 if (Parser.getTok().is(AsmToken::Exclaim)) {
4225 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4226 Parser.Lex(); // Eat the '!'.
4232 // The register offset is optionally preceded by a '+' or '-'
4233 bool isNegative = false;
4234 if (Parser.getTok().is(AsmToken::Minus)) {
4236 Parser.Lex(); // Eat the '-'.
4237 } else if (Parser.getTok().is(AsmToken::Plus)) {
4239 Parser.Lex(); // Eat the '+'.
4242 E = Parser.getTok().getLoc();
4243 int OffsetRegNum = tryParseRegister();
4244 if (OffsetRegNum == -1)
4245 return Error(E, "register expected");
4247 // If there's a shift operator, handle it.
4248 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4249 unsigned ShiftImm = 0;
4250 if (Parser.getTok().is(AsmToken::Comma)) {
4251 Parser.Lex(); // Eat the ','.
4252 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4256 // Now we should have the closing ']'
4257 E = Parser.getTok().getLoc();
4258 if (Parser.getTok().isNot(AsmToken::RBrac))
4259 return Error(E, "']' expected");
4260 Parser.Lex(); // Eat right bracket token.
4262 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4263 ShiftType, ShiftImm, 0, isNegative,
4266 // If there's a pre-indexing writeback marker, '!', just add it as a token
4268 if (Parser.getTok().is(AsmToken::Exclaim)) {
4269 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4270 Parser.Lex(); // Eat the '!'.
4276 /// parseMemRegOffsetShift - one of these two:
4277 /// ( lsl | lsr | asr | ror ) , # shift_amount
4279 /// return true if it parses a shift otherwise it returns false.
4280 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4282 SMLoc Loc = Parser.getTok().getLoc();
4283 const AsmToken &Tok = Parser.getTok();
4284 if (Tok.isNot(AsmToken::Identifier))
4286 StringRef ShiftName = Tok.getString();
4287 if (ShiftName == "lsl" || ShiftName == "LSL" ||
4288 ShiftName == "asl" || ShiftName == "ASL")
4290 else if (ShiftName == "lsr" || ShiftName == "LSR")
4292 else if (ShiftName == "asr" || ShiftName == "ASR")
4294 else if (ShiftName == "ror" || ShiftName == "ROR")
4296 else if (ShiftName == "rrx" || ShiftName == "RRX")
4299 return Error(Loc, "illegal shift operator");
4300 Parser.Lex(); // Eat shift type token.
4302 // rrx stands alone.
4304 if (St != ARM_AM::rrx) {
4305 Loc = Parser.getTok().getLoc();
4306 // A '#' and a shift amount.
4307 const AsmToken &HashTok = Parser.getTok();
4308 if (HashTok.isNot(AsmToken::Hash) &&
4309 HashTok.isNot(AsmToken::Dollar))
4310 return Error(HashTok.getLoc(), "'#' expected");
4311 Parser.Lex(); // Eat hash token.
4314 if (getParser().ParseExpression(Expr))
4316 // Range check the immediate.
4317 // lsl, ror: 0 <= imm <= 31
4318 // lsr, asr: 0 <= imm <= 32
4319 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4321 return Error(Loc, "shift amount must be an immediate");
4322 int64_t Imm = CE->getValue();
4324 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4325 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4326 return Error(Loc, "immediate shift value out of range");
4333 /// parseFPImm - A floating point immediate expression operand.
4334 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4335 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4336 // Anything that can accept a floating point constant as an operand
4337 // needs to go through here, as the regular ParseExpression is
4340 // This routine still creates a generic Immediate operand, containing
4341 // a bitcast of the 64-bit floating point value. The various operands
4342 // that accept floats can check whether the value is valid for them
4343 // via the standard is*() predicates.
4345 SMLoc S = Parser.getTok().getLoc();
4347 if (Parser.getTok().isNot(AsmToken::Hash) &&
4348 Parser.getTok().isNot(AsmToken::Dollar))
4349 return MatchOperand_NoMatch;
4351 // Disambiguate the VMOV forms that can accept an FP immediate.
4352 // vmov.f32 <sreg>, #imm
4353 // vmov.f64 <dreg>, #imm
4354 // vmov.f32 <dreg>, #imm @ vector f32x2
4355 // vmov.f32 <qreg>, #imm @ vector f32x4
4357 // There are also the NEON VMOV instructions which expect an
4358 // integer constant. Make sure we don't try to parse an FPImm
4360 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4361 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4362 if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
4363 TyOp->getToken() != ".f64"))
4364 return MatchOperand_NoMatch;
4366 Parser.Lex(); // Eat the '#'.
4368 // Handle negation, as that still comes through as a separate token.
4369 bool isNegative = false;
4370 if (Parser.getTok().is(AsmToken::Minus)) {
4374 const AsmToken &Tok = Parser.getTok();
4375 SMLoc Loc = Tok.getLoc();
4376 if (Tok.is(AsmToken::Real)) {
4377 APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4378 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4379 // If we had a '-' in front, toggle the sign bit.
4380 IntVal ^= (uint64_t)isNegative << 31;
4381 Parser.Lex(); // Eat the token.
4382 Operands.push_back(ARMOperand::CreateImm(
4383 MCConstantExpr::Create(IntVal, getContext()),
4384 S, Parser.getTok().getLoc()));
4385 return MatchOperand_Success;
4387 // Also handle plain integers. Instructions which allow floating point
4388 // immediates also allow a raw encoded 8-bit value.
4389 if (Tok.is(AsmToken::Integer)) {
4390 int64_t Val = Tok.getIntVal();
4391 Parser.Lex(); // Eat the token.
4392 if (Val > 255 || Val < 0) {
4393 Error(Loc, "encoded floating point value out of range");
4394 return MatchOperand_ParseFail;
4396 double RealVal = ARM_AM::getFPImmFloat(Val);
4397 Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue();
4398 Operands.push_back(ARMOperand::CreateImm(
4399 MCConstantExpr::Create(Val, getContext()), S,
4400 Parser.getTok().getLoc()));
4401 return MatchOperand_Success;
4404 Error(Loc, "invalid floating point immediate");
4405 return MatchOperand_ParseFail;
4408 /// Parse a arm instruction operand. For now this parses the operand regardless
4409 /// of the mnemonic.
4410 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4411 StringRef Mnemonic) {
4414 // Check if the current operand has a custom associated parser, if so, try to
4415 // custom parse the operand, or fallback to the general approach.
4416 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4417 if (ResTy == MatchOperand_Success)
4419 // If there wasn't a custom match, try the generic matcher below. Otherwise,
4420 // there was a match, but an error occurred, in which case, just return that
4421 // the operand parsing failed.
4422 if (ResTy == MatchOperand_ParseFail)
4425 switch (getLexer().getKind()) {
4427 Error(Parser.getTok().getLoc(), "unexpected token in operand");
4429 case AsmToken::Identifier: {
4430 if (!tryParseRegisterWithWriteBack(Operands))
4432 int Res = tryParseShiftRegister(Operands);
4433 if (Res == 0) // success
4435 else if (Res == -1) // irrecoverable error
4437 // If this is VMRS, check for the apsr_nzcv operand.
4438 if (Mnemonic == "vmrs" && Parser.getTok().getString() == "apsr_nzcv") {
4439 S = Parser.getTok().getLoc();
4441 Operands.push_back(ARMOperand::CreateToken("apsr_nzcv", S));
4445 // Fall though for the Identifier case that is not a register or a
4448 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
4449 case AsmToken::Integer: // things like 1f and 2b as a branch targets
4450 case AsmToken::String: // quoted label names.
4451 case AsmToken::Dot: { // . as a branch target
4452 // This was not a register so parse other operands that start with an
4453 // identifier (like labels) as expressions and create them as immediates.
4454 const MCExpr *IdVal;
4455 S = Parser.getTok().getLoc();
4456 if (getParser().ParseExpression(IdVal))
4458 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4459 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4462 case AsmToken::LBrac:
4463 return parseMemory(Operands);
4464 case AsmToken::LCurly:
4465 return parseRegisterList(Operands);
4466 case AsmToken::Dollar:
4467 case AsmToken::Hash: {
4468 // #42 -> immediate.
4469 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
4470 S = Parser.getTok().getLoc();
4472 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4473 const MCExpr *ImmVal;
4474 if (getParser().ParseExpression(ImmVal))
4476 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4478 int32_t Val = CE->getValue();
4479 if (isNegative && Val == 0)
4480 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4482 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4483 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4486 case AsmToken::Colon: {
4487 // ":lower16:" and ":upper16:" expression prefixes
4488 // FIXME: Check it's an expression prefix,
4489 // e.g. (FOO - :lower16:BAR) isn't legal.
4490 ARMMCExpr::VariantKind RefKind;
4491 if (parsePrefix(RefKind))
4494 const MCExpr *SubExprVal;
4495 if (getParser().ParseExpression(SubExprVal))
4498 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4500 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4501 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4507 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4508 // :lower16: and :upper16:.
4509 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4510 RefKind = ARMMCExpr::VK_ARM_None;
4512 // :lower16: and :upper16: modifiers
4513 assert(getLexer().is(AsmToken::Colon) && "expected a :");
4514 Parser.Lex(); // Eat ':'
4516 if (getLexer().isNot(AsmToken::Identifier)) {
4517 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4521 StringRef IDVal = Parser.getTok().getIdentifier();
4522 if (IDVal == "lower16") {
4523 RefKind = ARMMCExpr::VK_ARM_LO16;
4524 } else if (IDVal == "upper16") {
4525 RefKind = ARMMCExpr::VK_ARM_HI16;
4527 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4532 if (getLexer().isNot(AsmToken::Colon)) {
4533 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4536 Parser.Lex(); // Eat the last ':'
4540 /// \brief Given a mnemonic, split out possible predication code and carry
4541 /// setting letters to form a canonical mnemonic and flags.
4543 // FIXME: Would be nice to autogen this.
4544 // FIXME: This is a bit of a maze of special cases.
4545 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4546 unsigned &PredicationCode,
4548 unsigned &ProcessorIMod,
4549 StringRef &ITMask) {
4550 PredicationCode = ARMCC::AL;
4551 CarrySetting = false;
4554 // Ignore some mnemonics we know aren't predicated forms.
4556 // FIXME: Would be nice to autogen this.
4557 if ((Mnemonic == "movs" && isThumb()) ||
4558 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
4559 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
4560 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
4561 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
4562 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
4563 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
4564 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4565 Mnemonic == "fmuls")
4568 // First, split out any predication code. Ignore mnemonics we know aren't
4569 // predicated but do have a carry-set and so weren't caught above.
4570 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4571 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4572 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4573 Mnemonic != "sbcs" && Mnemonic != "rscs") {
4574 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4575 .Case("eq", ARMCC::EQ)
4576 .Case("ne", ARMCC::NE)
4577 .Case("hs", ARMCC::HS)
4578 .Case("cs", ARMCC::HS)
4579 .Case("lo", ARMCC::LO)
4580 .Case("cc", ARMCC::LO)
4581 .Case("mi", ARMCC::MI)
4582 .Case("pl", ARMCC::PL)
4583 .Case("vs", ARMCC::VS)
4584 .Case("vc", ARMCC::VC)
4585 .Case("hi", ARMCC::HI)
4586 .Case("ls", ARMCC::LS)
4587 .Case("ge", ARMCC::GE)
4588 .Case("lt", ARMCC::LT)
4589 .Case("gt", ARMCC::GT)
4590 .Case("le", ARMCC::LE)
4591 .Case("al", ARMCC::AL)
4594 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4595 PredicationCode = CC;
4599 // Next, determine if we have a carry setting bit. We explicitly ignore all
4600 // the instructions we know end in 's'.
4601 if (Mnemonic.endswith("s") &&
4602 !(Mnemonic == "cps" || Mnemonic == "mls" ||
4603 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4604 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4605 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4606 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4607 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4608 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4609 Mnemonic == "fmuls" || Mnemonic == "fcmps" ||
4610 (Mnemonic == "movs" && isThumb()))) {
4611 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4612 CarrySetting = true;
4615 // The "cps" instruction can have a interrupt mode operand which is glued into
4616 // the mnemonic. Check if this is the case, split it and parse the imod op
4617 if (Mnemonic.startswith("cps")) {
4618 // Split out any imod code.
4620 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4621 .Case("ie", ARM_PROC::IE)
4622 .Case("id", ARM_PROC::ID)
4625 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4626 ProcessorIMod = IMod;
4630 // The "it" instruction has the condition mask on the end of the mnemonic.
4631 if (Mnemonic.startswith("it")) {
4632 ITMask = Mnemonic.slice(2, Mnemonic.size());
4633 Mnemonic = Mnemonic.slice(0, 2);
4639 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
4640 /// inclusion of carry set or predication code operands.
4642 // FIXME: It would be nice to autogen this.
4644 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
4645 bool &CanAcceptPredicationCode) {
4646 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4647 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4648 Mnemonic == "add" || Mnemonic == "adc" ||
4649 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4650 Mnemonic == "orr" || Mnemonic == "mvn" ||
4651 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4652 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4653 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4654 Mnemonic == "mla" || Mnemonic == "smlal" ||
4655 Mnemonic == "umlal" || Mnemonic == "umull"))) {
4656 CanAcceptCarrySet = true;
4658 CanAcceptCarrySet = false;
4660 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
4661 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
4662 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
4663 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
4664 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
4665 (Mnemonic == "clrex" && !isThumb()) ||
4666 (Mnemonic == "nop" && isThumbOne()) ||
4667 ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" ||
4668 Mnemonic == "ldc2" || Mnemonic == "ldc2l" ||
4669 Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) ||
4670 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
4672 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
4673 CanAcceptPredicationCode = false;
4675 CanAcceptPredicationCode = true;
4678 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
4679 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
4680 CanAcceptPredicationCode = false;
4684 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4685 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4686 // FIXME: This is all horribly hacky. We really need a better way to deal
4687 // with optional operands like this in the matcher table.
4689 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4690 // another does not. Specifically, the MOVW instruction does not. So we
4691 // special case it here and remove the defaulted (non-setting) cc_out
4692 // operand if that's the instruction we're trying to match.
4694 // We do this as post-processing of the explicit operands rather than just
4695 // conditionally adding the cc_out in the first place because we need
4696 // to check the type of the parsed immediate operand.
4697 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4698 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4699 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4700 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4703 // Register-register 'add' for thumb does not have a cc_out operand
4704 // when there are only two register operands.
4705 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4706 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4707 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4708 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4710 // Register-register 'add' for thumb does not have a cc_out operand
4711 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4712 // have to check the immediate range here since Thumb2 has a variant
4713 // that can handle a different range and has a cc_out operand.
4714 if (((isThumb() && Mnemonic == "add") ||
4715 (isThumbTwo() && Mnemonic == "sub")) &&
4716 Operands.size() == 6 &&
4717 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4718 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4719 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4720 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4721 (static_cast<ARMOperand*>(Operands[5])->isReg() ||
4722 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4724 // For Thumb2, add/sub immediate does not have a cc_out operand for the
4725 // imm0_4095 variant. That's the least-preferred variant when
4726 // selecting via the generic "add" mnemonic, so to know that we
4727 // should remove the cc_out operand, we have to explicitly check that
4728 // it's not one of the other variants. Ugh.
4729 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4730 Operands.size() == 6 &&
4731 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4732 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4733 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4734 // Nest conditions rather than one big 'if' statement for readability.
4736 // If either register is a high reg, it's either one of the SP
4737 // variants (handled above) or a 32-bit encoding, so we just
4738 // check against T3. If the second register is the PC, this is an
4739 // alternate form of ADR, which uses encoding T4, so check for that too.
4740 if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4741 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
4742 static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
4743 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
4745 // If both registers are low, we're in an IT block, and the immediate is
4746 // in range, we should use encoding T1 instead, which has a cc_out.
4748 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4749 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4750 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
4753 // Otherwise, we use encoding T4, which does not have a cc_out
4758 // The thumb2 multiply instruction doesn't have a CCOut register, so
4759 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
4760 // use the 16-bit encoding or not.
4761 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
4762 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4763 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4764 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4765 static_cast<ARMOperand*>(Operands[5])->isReg() &&
4766 // If the registers aren't low regs, the destination reg isn't the
4767 // same as one of the source regs, or the cc_out operand is zero
4768 // outside of an IT block, we have to use the 32-bit encoding, so
4769 // remove the cc_out operand.
4770 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4771 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4772 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
4774 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4775 static_cast<ARMOperand*>(Operands[5])->getReg() &&
4776 static_cast<ARMOperand*>(Operands[3])->getReg() !=
4777 static_cast<ARMOperand*>(Operands[4])->getReg())))
4780 // Also check the 'mul' syntax variant that doesn't specify an explicit
4781 // destination register.
4782 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
4783 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4784 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4785 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4786 // If the registers aren't low regs or the cc_out operand is zero
4787 // outside of an IT block, we have to use the 32-bit encoding, so
4788 // remove the cc_out operand.
4789 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4790 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4796 // Register-register 'add/sub' for thumb does not have a cc_out operand
4797 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
4798 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
4799 // right, this will result in better diagnostics (which operand is off)
4801 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
4802 (Operands.size() == 5 || Operands.size() == 6) &&
4803 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4804 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4805 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4811 static bool isDataTypeToken(StringRef Tok) {
4812 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
4813 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
4814 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
4815 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
4816 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
4817 Tok == ".f" || Tok == ".d";
4820 // FIXME: This bit should probably be handled via an explicit match class
4821 // in the .td files that matches the suffix instead of having it be
4822 // a literal string token the way it is now.
4823 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
4824 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
4827 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features);
4828 /// Parse an arm instruction mnemonic followed by its operands.
4829 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
4830 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4831 // Apply mnemonic aliases before doing anything else, as the destination
4832 // mnemnonic may include suffices and we want to handle them normally.
4833 // The generic tblgen'erated code does this later, at the start of
4834 // MatchInstructionImpl(), but that's too late for aliases that include
4835 // any sort of suffix.
4836 unsigned AvailableFeatures = getAvailableFeatures();
4837 applyMnemonicAliases(Name, AvailableFeatures);
4839 // First check for the ARM-specific .req directive.
4840 if (Parser.getTok().is(AsmToken::Identifier) &&
4841 Parser.getTok().getIdentifier() == ".req") {
4842 parseDirectiveReq(Name, NameLoc);
4843 // We always return 'error' for this, as we're done with this
4844 // statement and don't need to match the 'instruction."
4848 // Create the leading tokens for the mnemonic, split by '.' characters.
4849 size_t Start = 0, Next = Name.find('.');
4850 StringRef Mnemonic = Name.slice(Start, Next);
4852 // Split out the predication code and carry setting flag from the mnemonic.
4853 unsigned PredicationCode;
4854 unsigned ProcessorIMod;
4857 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
4858 ProcessorIMod, ITMask);
4860 // In Thumb1, only the branch (B) instruction can be predicated.
4861 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
4862 Parser.EatToEndOfStatement();
4863 return Error(NameLoc, "conditional execution not supported in Thumb1");
4866 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
4868 // Handle the IT instruction ITMask. Convert it to a bitmask. This
4869 // is the mask as it will be for the IT encoding if the conditional
4870 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
4871 // where the conditional bit0 is zero, the instruction post-processing
4872 // will adjust the mask accordingly.
4873 if (Mnemonic == "it") {
4874 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
4875 if (ITMask.size() > 3) {
4876 Parser.EatToEndOfStatement();
4877 return Error(Loc, "too many conditions on IT instruction");
4880 for (unsigned i = ITMask.size(); i != 0; --i) {
4881 char pos = ITMask[i - 1];
4882 if (pos != 't' && pos != 'e') {
4883 Parser.EatToEndOfStatement();
4884 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
4887 if (ITMask[i - 1] == 't')
4890 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
4893 // FIXME: This is all a pretty gross hack. We should automatically handle
4894 // optional operands like this via tblgen.
4896 // Next, add the CCOut and ConditionCode operands, if needed.
4898 // For mnemonics which can ever incorporate a carry setting bit or predication
4899 // code, our matching model involves us always generating CCOut and
4900 // ConditionCode operands to match the mnemonic "as written" and then we let
4901 // the matcher deal with finding the right instruction or generating an
4902 // appropriate error.
4903 bool CanAcceptCarrySet, CanAcceptPredicationCode;
4904 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
4906 // If we had a carry-set on an instruction that can't do that, issue an
4908 if (!CanAcceptCarrySet && CarrySetting) {
4909 Parser.EatToEndOfStatement();
4910 return Error(NameLoc, "instruction '" + Mnemonic +
4911 "' can not set flags, but 's' suffix specified");
4913 // If we had a predication code on an instruction that can't do that, issue an
4915 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
4916 Parser.EatToEndOfStatement();
4917 return Error(NameLoc, "instruction '" + Mnemonic +
4918 "' is not predicable, but condition code specified");
4921 // Add the carry setting operand, if necessary.
4922 if (CanAcceptCarrySet) {
4923 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
4924 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
4928 // Add the predication code operand, if necessary.
4929 if (CanAcceptPredicationCode) {
4930 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
4932 Operands.push_back(ARMOperand::CreateCondCode(
4933 ARMCC::CondCodes(PredicationCode), Loc));
4936 // Add the processor imod operand, if necessary.
4937 if (ProcessorIMod) {
4938 Operands.push_back(ARMOperand::CreateImm(
4939 MCConstantExpr::Create(ProcessorIMod, getContext()),
4943 // Add the remaining tokens in the mnemonic.
4944 while (Next != StringRef::npos) {
4946 Next = Name.find('.', Start + 1);
4947 StringRef ExtraToken = Name.slice(Start, Next);
4949 // Some NEON instructions have an optional datatype suffix that is
4950 // completely ignored. Check for that.
4951 if (isDataTypeToken(ExtraToken) &&
4952 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
4955 if (ExtraToken != ".n") {
4956 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
4957 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
4961 // Read the remaining operands.
4962 if (getLexer().isNot(AsmToken::EndOfStatement)) {
4963 // Read the first operand.
4964 if (parseOperand(Operands, Mnemonic)) {
4965 Parser.EatToEndOfStatement();
4969 while (getLexer().is(AsmToken::Comma)) {
4970 Parser.Lex(); // Eat the comma.
4972 // Parse and remember the operand.
4973 if (parseOperand(Operands, Mnemonic)) {
4974 Parser.EatToEndOfStatement();
4980 if (getLexer().isNot(AsmToken::EndOfStatement)) {
4981 SMLoc Loc = getLexer().getLoc();
4982 Parser.EatToEndOfStatement();
4983 return Error(Loc, "unexpected token in argument list");
4986 Parser.Lex(); // Consume the EndOfStatement
4988 // Some instructions, mostly Thumb, have forms for the same mnemonic that
4989 // do and don't have a cc_out optional-def operand. With some spot-checks
4990 // of the operand list, we can figure out which variant we're trying to
4991 // parse and adjust accordingly before actually matching. We shouldn't ever
4992 // try to remove a cc_out operand that was explicitly set on the the
4993 // mnemonic, of course (CarrySetting == true). Reason number #317 the
4994 // table driven matcher doesn't fit well with the ARM instruction set.
4995 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
4996 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
4997 Operands.erase(Operands.begin() + 1);
5001 // ARM mode 'blx' need special handling, as the register operand version
5002 // is predicable, but the label operand version is not. So, we can't rely
5003 // on the Mnemonic based checking to correctly figure out when to put
5004 // a k_CondCode operand in the list. If we're trying to match the label
5005 // version, remove the k_CondCode operand here.
5006 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5007 static_cast<ARMOperand*>(Operands[2])->isImm()) {
5008 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5009 Operands.erase(Operands.begin() + 1);
5013 // The vector-compare-to-zero instructions have a literal token "#0" at
5014 // the end that comes to here as an immediate operand. Convert it to a
5015 // token to play nicely with the matcher.
5016 if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
5017 Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
5018 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5019 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
5020 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5021 if (CE && CE->getValue() == 0) {
5022 Operands.erase(Operands.begin() + 5);
5023 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5027 // VCMP{E} does the same thing, but with a different operand count.
5028 if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 &&
5029 static_cast<ARMOperand*>(Operands[4])->isImm()) {
5030 ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]);
5031 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5032 if (CE && CE->getValue() == 0) {
5033 Operands.erase(Operands.begin() + 4);
5034 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5038 // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
5039 // end. Convert it to a token here. Take care not to convert those
5040 // that should hit the Thumb2 encoding.
5041 if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
5042 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5043 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5044 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5045 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
5046 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5047 if (CE && CE->getValue() == 0 &&
5049 // The cc_out operand matches the IT block.
5050 ((inITBlock() != CarrySetting) &&
5051 // Neither register operand is a high register.
5052 (isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
5053 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()))))){
5054 Operands.erase(Operands.begin() + 5);
5055 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5063 // Validate context-sensitive operand constraints.
5065 // return 'true' if register list contains non-low GPR registers,
5066 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5067 // 'containsReg' to true.
5068 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5069 unsigned HiReg, bool &containsReg) {
5070 containsReg = false;
5071 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5072 unsigned OpReg = Inst.getOperand(i).getReg();
5075 // Anything other than a low register isn't legal here.
5076 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5082 // Check if the specified regisgter is in the register list of the inst,
5083 // starting at the indicated operand number.
5084 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5085 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5086 unsigned OpReg = Inst.getOperand(i).getReg();
5093 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around
5094 // the ARMInsts array) instead. Getting that here requires awkward
5095 // API changes, though. Better way?
5097 extern const MCInstrDesc ARMInsts[];
5099 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
5100 return ARMInsts[Opcode];
5103 // FIXME: We would really like to be able to tablegen'erate this.
5105 validateInstruction(MCInst &Inst,
5106 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5107 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
5108 SMLoc Loc = Operands[0]->getStartLoc();
5109 // Check the IT block state first.
5110 // NOTE: BKPT instruction has the interesting property of being
5111 // allowed in IT blocks, but not being predicable. It just always
5113 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT &&
5114 Inst.getOpcode() != ARM::BKPT) {
5116 if (ITState.FirstCond)
5117 ITState.FirstCond = false;
5119 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5120 // The instruction must be predicable.
5121 if (!MCID.isPredicable())
5122 return Error(Loc, "instructions in IT block must be predicable");
5123 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5124 unsigned ITCond = bit ? ITState.Cond :
5125 ARMCC::getOppositeCondition(ITState.Cond);
5126 if (Cond != ITCond) {
5127 // Find the condition code Operand to get its SMLoc information.
5129 for (unsigned i = 1; i < Operands.size(); ++i)
5130 if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
5131 CondLoc = Operands[i]->getStartLoc();
5132 return Error(CondLoc, "incorrect condition in IT block; got '" +
5133 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5134 "', but expected '" +
5135 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5137 // Check for non-'al' condition codes outside of the IT block.
5138 } else if (isThumbTwo() && MCID.isPredicable() &&
5139 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5140 ARMCC::AL && Inst.getOpcode() != ARM::tB &&
5141 Inst.getOpcode() != ARM::t2B)
5142 return Error(Loc, "predicated instructions must be in IT block");
5144 switch (Inst.getOpcode()) {
5147 case ARM::LDRD_POST:
5149 // Rt2 must be Rt + 1.
5150 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
5151 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
5153 return Error(Operands[3]->getStartLoc(),
5154 "destination operands must be sequential");
5158 // Rt2 must be Rt + 1.
5159 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
5160 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
5162 return Error(Operands[3]->getStartLoc(),
5163 "source operands must be sequential");
5167 case ARM::STRD_POST:
5169 // Rt2 must be Rt + 1.
5170 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
5171 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
5173 return Error(Operands[3]->getStartLoc(),
5174 "source operands must be sequential");
5179 // width must be in range [1, 32-lsb]
5180 unsigned lsb = Inst.getOperand(2).getImm();
5181 unsigned widthm1 = Inst.getOperand(3).getImm();
5182 if (widthm1 >= 32 - lsb)
5183 return Error(Operands[5]->getStartLoc(),
5184 "bitfield width must be in range [1,32-lsb]");
5188 // If we're parsing Thumb2, the .w variant is available and handles
5189 // most cases that are normally illegal for a Thumb1 LDM
5190 // instruction. We'll make the transformation in processInstruction()
5193 // Thumb LDM instructions are writeback iff the base register is not
5194 // in the register list.
5195 unsigned Rn = Inst.getOperand(0).getReg();
5196 bool hasWritebackToken =
5197 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5198 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5199 bool listContainsBase;
5200 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
5201 return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
5202 "registers must be in range r0-r7");
5203 // If we should have writeback, then there should be a '!' token.
5204 if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
5205 return Error(Operands[2]->getStartLoc(),
5206 "writeback operator '!' expected");
5207 // If we should not have writeback, there must not be a '!'. This is
5208 // true even for the 32-bit wide encodings.
5209 if (listContainsBase && hasWritebackToken)
5210 return Error(Operands[3]->getStartLoc(),
5211 "writeback operator '!' not allowed when base register "
5212 "in register list");
5216 case ARM::t2LDMIA_UPD: {
5217 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5218 return Error(Operands[4]->getStartLoc(),
5219 "writeback operator '!' not allowed when base register "
5220 "in register list");
5223 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5224 // so only issue a diagnostic for thumb1. The instructions will be
5225 // switched to the t2 encodings in processInstruction() if necessary.
5227 bool listContainsBase;
5228 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
5230 return Error(Operands[2]->getStartLoc(),
5231 "registers must be in range r0-r7 or pc");
5235 bool listContainsBase;
5236 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
5238 return Error(Operands[2]->getStartLoc(),
5239 "registers must be in range r0-r7 or lr");
5242 case ARM::tSTMIA_UPD: {
5243 bool listContainsBase;
5244 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
5245 return Error(Operands[4]->getStartLoc(),
5246 "registers must be in range r0-r7");
5254 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5256 default: llvm_unreachable("unexpected opcode!");
5258 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5259 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5260 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5261 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5262 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5263 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5264 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
5265 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5266 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5269 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5270 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5271 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5272 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5273 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5275 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5276 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5277 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5278 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5279 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5281 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
5282 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5283 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5284 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5285 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5288 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5289 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5290 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5291 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5292 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5293 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5294 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5295 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5296 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5297 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5298 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
5299 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5300 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5301 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5302 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5305 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5306 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5307 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5308 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5309 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5310 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5311 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5312 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5313 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5314 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5315 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5316 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5317 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
5318 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5319 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5320 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
5321 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5322 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5325 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5326 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5327 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5328 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5329 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5330 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5331 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5332 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5333 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5334 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5335 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
5336 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5337 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5338 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5339 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5342 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5343 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5344 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5345 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5346 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5347 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5348 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5349 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5350 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5351 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5352 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5353 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5354 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
5355 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5356 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5357 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
5358 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5359 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5363 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
5365 default: llvm_unreachable("unexpected opcode!");
5367 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5368 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5369 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5370 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5371 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5372 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5373 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
5374 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5375 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5378 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5379 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5380 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5381 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5382 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5383 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5384 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5385 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5386 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5387 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5388 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
5389 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5390 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5391 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5392 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5395 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5396 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5397 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5398 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5399 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5400 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5401 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5402 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5403 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5404 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5405 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5406 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5407 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
5408 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5409 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5410 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5411 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5412 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5415 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5416 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5417 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5418 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5419 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5420 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5421 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5422 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5423 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5424 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5425 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
5426 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5427 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5428 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5429 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5432 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5433 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5434 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5435 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5436 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5437 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5438 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5439 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5440 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5441 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5442 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5443 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5444 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
5445 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5446 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5447 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
5448 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5449 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
5452 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5453 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5454 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5455 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
5456 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5457 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5458 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5459 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5460 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5461 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5462 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
5463 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5464 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5465 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5466 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5469 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5470 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5471 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5472 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5473 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5474 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5475 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5476 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5477 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5478 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
5479 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
5480 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5481 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
5482 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
5483 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
5484 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
5485 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
5486 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
5489 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5490 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5491 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5492 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5493 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5494 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5495 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5496 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5497 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5498 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5499 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5500 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5501 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
5502 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
5503 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
5504 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
5505 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
5506 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
5511 processInstruction(MCInst &Inst,
5512 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5513 switch (Inst.getOpcode()) {
5514 // Aliases for alternate PC+imm syntax of LDR instructions.
5515 case ARM::t2LDRpcrel:
5516 Inst.setOpcode(ARM::t2LDRpci);
5518 case ARM::t2LDRBpcrel:
5519 Inst.setOpcode(ARM::t2LDRBpci);
5521 case ARM::t2LDRHpcrel:
5522 Inst.setOpcode(ARM::t2LDRHpci);
5524 case ARM::t2LDRSBpcrel:
5525 Inst.setOpcode(ARM::t2LDRSBpci);
5527 case ARM::t2LDRSHpcrel:
5528 Inst.setOpcode(ARM::t2LDRSHpci);
5530 // Handle NEON VST complex aliases.
5531 case ARM::VST1LNdWB_register_Asm_8:
5532 case ARM::VST1LNdWB_register_Asm_16:
5533 case ARM::VST1LNdWB_register_Asm_32: {
5535 // Shuffle the operands around so the lane index operand is in the
5538 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5539 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5540 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5541 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5542 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5543 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5544 TmpInst.addOperand(Inst.getOperand(1)); // lane
5545 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5546 TmpInst.addOperand(Inst.getOperand(6));
5551 case ARM::VST2LNdWB_register_Asm_8:
5552 case ARM::VST2LNdWB_register_Asm_16:
5553 case ARM::VST2LNdWB_register_Asm_32:
5554 case ARM::VST2LNqWB_register_Asm_16:
5555 case ARM::VST2LNqWB_register_Asm_32: {
5557 // Shuffle the operands around so the lane index operand is in the
5560 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5561 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5562 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5563 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5564 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5565 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5566 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5568 TmpInst.addOperand(Inst.getOperand(1)); // lane
5569 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5570 TmpInst.addOperand(Inst.getOperand(6));
5575 case ARM::VST3LNdWB_register_Asm_8:
5576 case ARM::VST3LNdWB_register_Asm_16:
5577 case ARM::VST3LNdWB_register_Asm_32:
5578 case ARM::VST3LNqWB_register_Asm_16:
5579 case ARM::VST3LNqWB_register_Asm_32: {
5581 // Shuffle the operands around so the lane index operand is in the
5584 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5585 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5586 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5587 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5588 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5589 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5590 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5592 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5594 TmpInst.addOperand(Inst.getOperand(1)); // lane
5595 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5596 TmpInst.addOperand(Inst.getOperand(6));
5601 case ARM::VST4LNdWB_register_Asm_8:
5602 case ARM::VST4LNdWB_register_Asm_16:
5603 case ARM::VST4LNdWB_register_Asm_32:
5604 case ARM::VST4LNqWB_register_Asm_16:
5605 case ARM::VST4LNqWB_register_Asm_32: {
5607 // Shuffle the operands around so the lane index operand is in the
5610 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5611 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5612 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5613 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5614 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5615 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5616 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5618 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5620 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5622 TmpInst.addOperand(Inst.getOperand(1)); // lane
5623 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5624 TmpInst.addOperand(Inst.getOperand(6));
5629 case ARM::VST1LNdWB_fixed_Asm_8:
5630 case ARM::VST1LNdWB_fixed_Asm_16:
5631 case ARM::VST1LNdWB_fixed_Asm_32: {
5633 // Shuffle the operands around so the lane index operand is in the
5636 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5637 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5638 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5639 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5640 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5641 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5642 TmpInst.addOperand(Inst.getOperand(1)); // lane
5643 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5644 TmpInst.addOperand(Inst.getOperand(5));
5649 case ARM::VST2LNdWB_fixed_Asm_8:
5650 case ARM::VST2LNdWB_fixed_Asm_16:
5651 case ARM::VST2LNdWB_fixed_Asm_32:
5652 case ARM::VST2LNqWB_fixed_Asm_16:
5653 case ARM::VST2LNqWB_fixed_Asm_32: {
5655 // Shuffle the operands around so the lane index operand is in the
5658 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5659 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5660 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5661 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5662 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5663 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5664 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5666 TmpInst.addOperand(Inst.getOperand(1)); // lane
5667 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5668 TmpInst.addOperand(Inst.getOperand(5));
5673 case ARM::VST3LNdWB_fixed_Asm_8:
5674 case ARM::VST3LNdWB_fixed_Asm_16:
5675 case ARM::VST3LNdWB_fixed_Asm_32:
5676 case ARM::VST3LNqWB_fixed_Asm_16:
5677 case ARM::VST3LNqWB_fixed_Asm_32: {
5679 // Shuffle the operands around so the lane index operand is in the
5682 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5683 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5684 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5685 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5686 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5687 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5688 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5690 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5692 TmpInst.addOperand(Inst.getOperand(1)); // lane
5693 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5694 TmpInst.addOperand(Inst.getOperand(5));
5699 case ARM::VST4LNdWB_fixed_Asm_8:
5700 case ARM::VST4LNdWB_fixed_Asm_16:
5701 case ARM::VST4LNdWB_fixed_Asm_32:
5702 case ARM::VST4LNqWB_fixed_Asm_16:
5703 case ARM::VST4LNqWB_fixed_Asm_32: {
5705 // Shuffle the operands around so the lane index operand is in the
5708 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5709 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5710 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5711 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5712 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5713 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5714 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5716 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5718 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5720 TmpInst.addOperand(Inst.getOperand(1)); // lane
5721 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5722 TmpInst.addOperand(Inst.getOperand(5));
5727 case ARM::VST1LNdAsm_8:
5728 case ARM::VST1LNdAsm_16:
5729 case ARM::VST1LNdAsm_32: {
5731 // Shuffle the operands around so the lane index operand is in the
5734 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5735 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5736 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5737 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5738 TmpInst.addOperand(Inst.getOperand(1)); // lane
5739 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5740 TmpInst.addOperand(Inst.getOperand(5));
5745 case ARM::VST2LNdAsm_8:
5746 case ARM::VST2LNdAsm_16:
5747 case ARM::VST2LNdAsm_32:
5748 case ARM::VST2LNqAsm_16:
5749 case ARM::VST2LNqAsm_32: {
5751 // Shuffle the operands around so the lane index operand is in the
5754 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5755 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5756 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5757 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5758 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5760 TmpInst.addOperand(Inst.getOperand(1)); // lane
5761 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5762 TmpInst.addOperand(Inst.getOperand(5));
5767 case ARM::VST3LNdAsm_8:
5768 case ARM::VST3LNdAsm_16:
5769 case ARM::VST3LNdAsm_32:
5770 case ARM::VST3LNqAsm_16:
5771 case ARM::VST3LNqAsm_32: {
5773 // Shuffle the operands around so the lane index operand is in the
5776 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5777 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5778 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5779 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5780 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5782 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5784 TmpInst.addOperand(Inst.getOperand(1)); // lane
5785 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5786 TmpInst.addOperand(Inst.getOperand(5));
5791 case ARM::VST4LNdAsm_8:
5792 case ARM::VST4LNdAsm_16:
5793 case ARM::VST4LNdAsm_32:
5794 case ARM::VST4LNqAsm_16:
5795 case ARM::VST4LNqAsm_32: {
5797 // Shuffle the operands around so the lane index operand is in the
5800 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5801 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5802 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5803 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5804 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5806 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5808 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5810 TmpInst.addOperand(Inst.getOperand(1)); // lane
5811 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5812 TmpInst.addOperand(Inst.getOperand(5));
5817 // Handle NEON VLD complex aliases.
5818 case ARM::VLD1LNdWB_register_Asm_8:
5819 case ARM::VLD1LNdWB_register_Asm_16:
5820 case ARM::VLD1LNdWB_register_Asm_32: {
5822 // Shuffle the operands around so the lane index operand is in the
5825 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
5826 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5827 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5828 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5829 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5830 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5831 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5832 TmpInst.addOperand(Inst.getOperand(1)); // lane
5833 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5834 TmpInst.addOperand(Inst.getOperand(6));
5839 case ARM::VLD2LNdWB_register_Asm_8:
5840 case ARM::VLD2LNdWB_register_Asm_16:
5841 case ARM::VLD2LNdWB_register_Asm_32:
5842 case ARM::VLD2LNqWB_register_Asm_16:
5843 case ARM::VLD2LNqWB_register_Asm_32: {
5845 // Shuffle the operands around so the lane index operand is in the
5848 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
5849 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5850 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5852 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5853 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5854 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5855 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5856 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5857 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5859 TmpInst.addOperand(Inst.getOperand(1)); // lane
5860 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5861 TmpInst.addOperand(Inst.getOperand(6));
5866 case ARM::VLD3LNdWB_register_Asm_8:
5867 case ARM::VLD3LNdWB_register_Asm_16:
5868 case ARM::VLD3LNdWB_register_Asm_32:
5869 case ARM::VLD3LNqWB_register_Asm_16:
5870 case ARM::VLD3LNqWB_register_Asm_32: {
5872 // Shuffle the operands around so the lane index operand is in the
5875 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
5876 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5877 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5879 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5881 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5882 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5883 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5884 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5885 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5886 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5888 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5890 TmpInst.addOperand(Inst.getOperand(1)); // lane
5891 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5892 TmpInst.addOperand(Inst.getOperand(6));
5897 case ARM::VLD4LNdWB_register_Asm_8:
5898 case ARM::VLD4LNdWB_register_Asm_16:
5899 case ARM::VLD4LNdWB_register_Asm_32:
5900 case ARM::VLD4LNqWB_register_Asm_16:
5901 case ARM::VLD4LNqWB_register_Asm_32: {
5903 // Shuffle the operands around so the lane index operand is in the
5906 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
5907 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5908 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5910 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5912 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5914 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5915 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5916 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5917 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5918 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5919 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5921 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5923 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5925 TmpInst.addOperand(Inst.getOperand(1)); // lane
5926 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5927 TmpInst.addOperand(Inst.getOperand(6));
5932 case ARM::VLD1LNdWB_fixed_Asm_8:
5933 case ARM::VLD1LNdWB_fixed_Asm_16:
5934 case ARM::VLD1LNdWB_fixed_Asm_32: {
5936 // Shuffle the operands around so the lane index operand is in the
5939 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
5940 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5941 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5942 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5943 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5944 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5945 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5946 TmpInst.addOperand(Inst.getOperand(1)); // lane
5947 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5948 TmpInst.addOperand(Inst.getOperand(5));
5953 case ARM::VLD2LNdWB_fixed_Asm_8:
5954 case ARM::VLD2LNdWB_fixed_Asm_16:
5955 case ARM::VLD2LNdWB_fixed_Asm_32:
5956 case ARM::VLD2LNqWB_fixed_Asm_16:
5957 case ARM::VLD2LNqWB_fixed_Asm_32: {
5959 // Shuffle the operands around so the lane index operand is in the
5962 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
5963 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5964 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5966 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5967 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5968 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5969 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5970 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5971 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5973 TmpInst.addOperand(Inst.getOperand(1)); // lane
5974 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5975 TmpInst.addOperand(Inst.getOperand(5));
5980 case ARM::VLD3LNdWB_fixed_Asm_8:
5981 case ARM::VLD3LNdWB_fixed_Asm_16:
5982 case ARM::VLD3LNdWB_fixed_Asm_32:
5983 case ARM::VLD3LNqWB_fixed_Asm_16:
5984 case ARM::VLD3LNqWB_fixed_Asm_32: {
5986 // Shuffle the operands around so the lane index operand is in the
5989 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
5990 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5991 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5993 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5995 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5996 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5997 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5998 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5999 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6000 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6002 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6004 TmpInst.addOperand(Inst.getOperand(1)); // lane
6005 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6006 TmpInst.addOperand(Inst.getOperand(5));
6011 case ARM::VLD4LNdWB_fixed_Asm_8:
6012 case ARM::VLD4LNdWB_fixed_Asm_16:
6013 case ARM::VLD4LNdWB_fixed_Asm_32:
6014 case ARM::VLD4LNqWB_fixed_Asm_16:
6015 case ARM::VLD4LNqWB_fixed_Asm_32: {
6017 // Shuffle the operands around so the lane index operand is in the
6020 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6021 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6022 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6024 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6026 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6028 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6029 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6030 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6031 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6032 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6033 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6035 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6037 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6039 TmpInst.addOperand(Inst.getOperand(1)); // lane
6040 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6041 TmpInst.addOperand(Inst.getOperand(5));
6046 case ARM::VLD1LNdAsm_8:
6047 case ARM::VLD1LNdAsm_16:
6048 case ARM::VLD1LNdAsm_32: {
6050 // Shuffle the operands around so the lane index operand is in the
6053 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6054 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6055 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6056 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6057 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6058 TmpInst.addOperand(Inst.getOperand(1)); // lane
6059 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6060 TmpInst.addOperand(Inst.getOperand(5));
6065 case ARM::VLD2LNdAsm_8:
6066 case ARM::VLD2LNdAsm_16:
6067 case ARM::VLD2LNdAsm_32:
6068 case ARM::VLD2LNqAsm_16:
6069 case ARM::VLD2LNqAsm_32: {
6071 // Shuffle the operands around so the lane index operand is in the
6074 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6075 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6076 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6078 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6079 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6080 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6081 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6083 TmpInst.addOperand(Inst.getOperand(1)); // lane
6084 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6085 TmpInst.addOperand(Inst.getOperand(5));
6090 case ARM::VLD3LNdAsm_8:
6091 case ARM::VLD3LNdAsm_16:
6092 case ARM::VLD3LNdAsm_32:
6093 case ARM::VLD3LNqAsm_16:
6094 case ARM::VLD3LNqAsm_32: {
6096 // Shuffle the operands around so the lane index operand is in the
6099 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6100 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6101 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6103 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6105 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6106 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6107 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6108 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6110 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6112 TmpInst.addOperand(Inst.getOperand(1)); // lane
6113 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6114 TmpInst.addOperand(Inst.getOperand(5));
6119 case ARM::VLD4LNdAsm_8:
6120 case ARM::VLD4LNdAsm_16:
6121 case ARM::VLD4LNdAsm_32:
6122 case ARM::VLD4LNqAsm_16:
6123 case ARM::VLD4LNqAsm_32: {
6125 // Shuffle the operands around so the lane index operand is in the
6128 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6129 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6130 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6132 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6134 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6136 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6137 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6138 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6139 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6141 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6143 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6145 TmpInst.addOperand(Inst.getOperand(1)); // lane
6146 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6147 TmpInst.addOperand(Inst.getOperand(5));
6152 // VLD3DUP single 3-element structure to all lanes instructions.
6153 case ARM::VLD3DUPdAsm_8:
6154 case ARM::VLD3DUPdAsm_16:
6155 case ARM::VLD3DUPdAsm_32:
6156 case ARM::VLD3DUPqAsm_8:
6157 case ARM::VLD3DUPqAsm_16:
6158 case ARM::VLD3DUPqAsm_32: {
6161 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6162 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6163 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6165 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6167 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6168 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6169 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6170 TmpInst.addOperand(Inst.getOperand(4));
6175 case ARM::VLD3DUPdWB_fixed_Asm_8:
6176 case ARM::VLD3DUPdWB_fixed_Asm_16:
6177 case ARM::VLD3DUPdWB_fixed_Asm_32:
6178 case ARM::VLD3DUPqWB_fixed_Asm_8:
6179 case ARM::VLD3DUPqWB_fixed_Asm_16:
6180 case ARM::VLD3DUPqWB_fixed_Asm_32: {
6183 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6184 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6185 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6187 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6189 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6190 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6191 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6192 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6193 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6194 TmpInst.addOperand(Inst.getOperand(4));
6199 case ARM::VLD3DUPdWB_register_Asm_8:
6200 case ARM::VLD3DUPdWB_register_Asm_16:
6201 case ARM::VLD3DUPdWB_register_Asm_32:
6202 case ARM::VLD3DUPqWB_register_Asm_8:
6203 case ARM::VLD3DUPqWB_register_Asm_16:
6204 case ARM::VLD3DUPqWB_register_Asm_32: {
6207 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6208 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6209 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6211 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6213 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6214 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6215 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6216 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6217 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6218 TmpInst.addOperand(Inst.getOperand(5));
6223 // VLD3 multiple 3-element structure instructions.
6224 case ARM::VLD3dAsm_8:
6225 case ARM::VLD3dAsm_16:
6226 case ARM::VLD3dAsm_32:
6227 case ARM::VLD3qAsm_8:
6228 case ARM::VLD3qAsm_16:
6229 case ARM::VLD3qAsm_32: {
6232 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6233 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6234 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6236 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6238 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6239 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6240 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6241 TmpInst.addOperand(Inst.getOperand(4));
6246 case ARM::VLD3dWB_fixed_Asm_8:
6247 case ARM::VLD3dWB_fixed_Asm_16:
6248 case ARM::VLD3dWB_fixed_Asm_32:
6249 case ARM::VLD3qWB_fixed_Asm_8:
6250 case ARM::VLD3qWB_fixed_Asm_16:
6251 case ARM::VLD3qWB_fixed_Asm_32: {
6254 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6255 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6256 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6258 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6260 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6261 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6262 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6263 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6264 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6265 TmpInst.addOperand(Inst.getOperand(4));
6270 case ARM::VLD3dWB_register_Asm_8:
6271 case ARM::VLD3dWB_register_Asm_16:
6272 case ARM::VLD3dWB_register_Asm_32:
6273 case ARM::VLD3qWB_register_Asm_8:
6274 case ARM::VLD3qWB_register_Asm_16:
6275 case ARM::VLD3qWB_register_Asm_32: {
6278 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6279 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6280 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6282 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6284 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6285 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6286 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6287 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6288 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6289 TmpInst.addOperand(Inst.getOperand(5));
6294 // VLD4DUP single 3-element structure to all lanes instructions.
6295 case ARM::VLD4DUPdAsm_8:
6296 case ARM::VLD4DUPdAsm_16:
6297 case ARM::VLD4DUPdAsm_32:
6298 case ARM::VLD4DUPqAsm_8:
6299 case ARM::VLD4DUPqAsm_16:
6300 case ARM::VLD4DUPqAsm_32: {
6303 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6304 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6305 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6307 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6309 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6311 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6312 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6313 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6314 TmpInst.addOperand(Inst.getOperand(4));
6319 case ARM::VLD4DUPdWB_fixed_Asm_8:
6320 case ARM::VLD4DUPdWB_fixed_Asm_16:
6321 case ARM::VLD4DUPdWB_fixed_Asm_32:
6322 case ARM::VLD4DUPqWB_fixed_Asm_8:
6323 case ARM::VLD4DUPqWB_fixed_Asm_16:
6324 case ARM::VLD4DUPqWB_fixed_Asm_32: {
6327 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6328 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6329 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6331 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6333 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6335 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6336 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6337 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6338 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6339 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6340 TmpInst.addOperand(Inst.getOperand(4));
6345 case ARM::VLD4DUPdWB_register_Asm_8:
6346 case ARM::VLD4DUPdWB_register_Asm_16:
6347 case ARM::VLD4DUPdWB_register_Asm_32:
6348 case ARM::VLD4DUPqWB_register_Asm_8:
6349 case ARM::VLD4DUPqWB_register_Asm_16:
6350 case ARM::VLD4DUPqWB_register_Asm_32: {
6353 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6354 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6355 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6357 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6359 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6361 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6362 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6363 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6364 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6365 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6366 TmpInst.addOperand(Inst.getOperand(5));
6371 // VLD4 multiple 4-element structure instructions.
6372 case ARM::VLD4dAsm_8:
6373 case ARM::VLD4dAsm_16:
6374 case ARM::VLD4dAsm_32:
6375 case ARM::VLD4qAsm_8:
6376 case ARM::VLD4qAsm_16:
6377 case ARM::VLD4qAsm_32: {
6380 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6381 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6382 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6384 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6386 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6388 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6389 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6390 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6391 TmpInst.addOperand(Inst.getOperand(4));
6396 case ARM::VLD4dWB_fixed_Asm_8:
6397 case ARM::VLD4dWB_fixed_Asm_16:
6398 case ARM::VLD4dWB_fixed_Asm_32:
6399 case ARM::VLD4qWB_fixed_Asm_8:
6400 case ARM::VLD4qWB_fixed_Asm_16:
6401 case ARM::VLD4qWB_fixed_Asm_32: {
6404 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6405 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6406 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6408 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6410 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6412 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6413 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6414 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6415 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6416 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6417 TmpInst.addOperand(Inst.getOperand(4));
6422 case ARM::VLD4dWB_register_Asm_8:
6423 case ARM::VLD4dWB_register_Asm_16:
6424 case ARM::VLD4dWB_register_Asm_32:
6425 case ARM::VLD4qWB_register_Asm_8:
6426 case ARM::VLD4qWB_register_Asm_16:
6427 case ARM::VLD4qWB_register_Asm_32: {
6430 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6431 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6432 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6434 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6436 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6438 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6439 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6440 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6441 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6442 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6443 TmpInst.addOperand(Inst.getOperand(5));
6448 // VST3 multiple 3-element structure instructions.
6449 case ARM::VST3dAsm_8:
6450 case ARM::VST3dAsm_16:
6451 case ARM::VST3dAsm_32:
6452 case ARM::VST3qAsm_8:
6453 case ARM::VST3qAsm_16:
6454 case ARM::VST3qAsm_32: {
6457 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6458 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6459 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6460 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6461 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6463 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6465 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6466 TmpInst.addOperand(Inst.getOperand(4));
6471 case ARM::VST3dWB_fixed_Asm_8:
6472 case ARM::VST3dWB_fixed_Asm_16:
6473 case ARM::VST3dWB_fixed_Asm_32:
6474 case ARM::VST3qWB_fixed_Asm_8:
6475 case ARM::VST3qWB_fixed_Asm_16:
6476 case ARM::VST3qWB_fixed_Asm_32: {
6479 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6480 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6481 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6482 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6483 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6484 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6485 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6487 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6489 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6490 TmpInst.addOperand(Inst.getOperand(4));
6495 case ARM::VST3dWB_register_Asm_8:
6496 case ARM::VST3dWB_register_Asm_16:
6497 case ARM::VST3dWB_register_Asm_32:
6498 case ARM::VST3qWB_register_Asm_8:
6499 case ARM::VST3qWB_register_Asm_16:
6500 case ARM::VST3qWB_register_Asm_32: {
6503 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6504 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6505 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6506 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6507 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6508 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6509 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6511 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6513 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6514 TmpInst.addOperand(Inst.getOperand(5));
6519 // VST4 multiple 3-element structure instructions.
6520 case ARM::VST4dAsm_8:
6521 case ARM::VST4dAsm_16:
6522 case ARM::VST4dAsm_32:
6523 case ARM::VST4qAsm_8:
6524 case ARM::VST4qAsm_16:
6525 case ARM::VST4qAsm_32: {
6528 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6529 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6530 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6531 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6532 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6534 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6536 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6538 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6539 TmpInst.addOperand(Inst.getOperand(4));
6544 case ARM::VST4dWB_fixed_Asm_8:
6545 case ARM::VST4dWB_fixed_Asm_16:
6546 case ARM::VST4dWB_fixed_Asm_32:
6547 case ARM::VST4qWB_fixed_Asm_8:
6548 case ARM::VST4qWB_fixed_Asm_16:
6549 case ARM::VST4qWB_fixed_Asm_32: {
6552 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6553 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6554 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6555 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6556 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6557 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6558 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6560 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6562 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6564 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6565 TmpInst.addOperand(Inst.getOperand(4));
6570 case ARM::VST4dWB_register_Asm_8:
6571 case ARM::VST4dWB_register_Asm_16:
6572 case ARM::VST4dWB_register_Asm_32:
6573 case ARM::VST4qWB_register_Asm_8:
6574 case ARM::VST4qWB_register_Asm_16:
6575 case ARM::VST4qWB_register_Asm_32: {
6578 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6579 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6580 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6581 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6582 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6583 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6584 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6586 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6588 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6590 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6591 TmpInst.addOperand(Inst.getOperand(5));
6596 // Handle the Thumb2 mode MOV complex aliases.
6598 case ARM::t2MOVSsr: {
6599 // Which instruction to expand to depends on the CCOut operand and
6600 // whether we're in an IT block if the register operands are low
6602 bool isNarrow = false;
6603 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6604 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6605 isARMLowRegister(Inst.getOperand(2).getReg()) &&
6606 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6607 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
6611 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
6612 default: llvm_unreachable("unexpected opcode!");
6613 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
6614 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
6615 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
6616 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
6618 TmpInst.setOpcode(newOpc);
6619 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6621 TmpInst.addOperand(MCOperand::CreateReg(
6622 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6623 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6624 TmpInst.addOperand(Inst.getOperand(2)); // Rm
6625 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6626 TmpInst.addOperand(Inst.getOperand(5));
6628 TmpInst.addOperand(MCOperand::CreateReg(
6629 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6634 case ARM::t2MOVSsi: {
6635 // Which instruction to expand to depends on the CCOut operand and
6636 // whether we're in an IT block if the register operands are low
6638 bool isNarrow = false;
6639 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6640 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6641 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
6645 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
6646 default: llvm_unreachable("unexpected opcode!");
6647 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
6648 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
6649 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
6650 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
6651 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
6653 unsigned Ammount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
6654 if (Ammount == 32) Ammount = 0;
6655 TmpInst.setOpcode(newOpc);
6656 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6658 TmpInst.addOperand(MCOperand::CreateReg(
6659 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6660 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6661 if (newOpc != ARM::t2RRX)
6662 TmpInst.addOperand(MCOperand::CreateImm(Ammount));
6663 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6664 TmpInst.addOperand(Inst.getOperand(4));
6666 TmpInst.addOperand(MCOperand::CreateReg(
6667 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6671 // Handle the ARM mode MOV complex aliases.
6676 ARM_AM::ShiftOpc ShiftTy;
6677 switch(Inst.getOpcode()) {
6678 default: llvm_unreachable("unexpected opcode!");
6679 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
6680 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
6681 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
6682 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
6684 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
6686 TmpInst.setOpcode(ARM::MOVsr);
6687 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6688 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6689 TmpInst.addOperand(Inst.getOperand(2)); // Rm
6690 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6691 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6692 TmpInst.addOperand(Inst.getOperand(4));
6693 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6701 ARM_AM::ShiftOpc ShiftTy;
6702 switch(Inst.getOpcode()) {
6703 default: llvm_unreachable("unexpected opcode!");
6704 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
6705 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
6706 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
6707 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
6709 // A shift by zero is a plain MOVr, not a MOVsi.
6710 unsigned Amt = Inst.getOperand(2).getImm();
6711 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
6712 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
6714 TmpInst.setOpcode(Opc);
6715 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6716 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6717 if (Opc == ARM::MOVsi)
6718 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6719 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6720 TmpInst.addOperand(Inst.getOperand(4));
6721 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6726 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
6728 TmpInst.setOpcode(ARM::MOVsi);
6729 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6730 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6731 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6732 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6733 TmpInst.addOperand(Inst.getOperand(3));
6734 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
6738 case ARM::t2LDMIA_UPD: {
6739 // If this is a load of a single register, then we should use
6740 // a post-indexed LDR instruction instead, per the ARM ARM.
6741 if (Inst.getNumOperands() != 5)
6744 TmpInst.setOpcode(ARM::t2LDR_POST);
6745 TmpInst.addOperand(Inst.getOperand(4)); // Rt
6746 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6747 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6748 TmpInst.addOperand(MCOperand::CreateImm(4));
6749 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6750 TmpInst.addOperand(Inst.getOperand(3));
6754 case ARM::t2STMDB_UPD: {
6755 // If this is a store of a single register, then we should use
6756 // a pre-indexed STR instruction instead, per the ARM ARM.
6757 if (Inst.getNumOperands() != 5)
6760 TmpInst.setOpcode(ARM::t2STR_PRE);
6761 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6762 TmpInst.addOperand(Inst.getOperand(4)); // Rt
6763 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6764 TmpInst.addOperand(MCOperand::CreateImm(-4));
6765 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6766 TmpInst.addOperand(Inst.getOperand(3));
6770 case ARM::LDMIA_UPD:
6771 // If this is a load of a single register via a 'pop', then we should use
6772 // a post-indexed LDR instruction instead, per the ARM ARM.
6773 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
6774 Inst.getNumOperands() == 5) {
6776 TmpInst.setOpcode(ARM::LDR_POST_IMM);
6777 TmpInst.addOperand(Inst.getOperand(4)); // Rt
6778 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6779 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6780 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
6781 TmpInst.addOperand(MCOperand::CreateImm(4));
6782 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6783 TmpInst.addOperand(Inst.getOperand(3));
6788 case ARM::STMDB_UPD:
6789 // If this is a store of a single register via a 'push', then we should use
6790 // a pre-indexed STR instruction instead, per the ARM ARM.
6791 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
6792 Inst.getNumOperands() == 5) {
6794 TmpInst.setOpcode(ARM::STR_PRE_IMM);
6795 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6796 TmpInst.addOperand(Inst.getOperand(4)); // Rt
6797 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
6798 TmpInst.addOperand(MCOperand::CreateImm(-4));
6799 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6800 TmpInst.addOperand(Inst.getOperand(3));
6804 case ARM::t2ADDri12:
6805 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
6806 // mnemonic was used (not "addw"), encoding T3 is preferred.
6807 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
6808 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
6810 Inst.setOpcode(ARM::t2ADDri);
6811 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
6813 case ARM::t2SUBri12:
6814 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
6815 // mnemonic was used (not "subw"), encoding T3 is preferred.
6816 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
6817 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
6819 Inst.setOpcode(ARM::t2SUBri);
6820 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
6823 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
6824 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
6825 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
6826 // to encoding T1 if <Rd> is omitted."
6827 if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
6828 Inst.setOpcode(ARM::tADDi3);
6833 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
6834 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
6835 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
6836 // to encoding T1 if <Rd> is omitted."
6837 if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
6838 Inst.setOpcode(ARM::tSUBi3);
6842 case ARM::t2ADDrr: {
6843 // If the destination and first source operand are the same, and
6844 // there's no setting of the flags, use encoding T2 instead of T3.
6845 // Note that this is only for ADD, not SUB. This mirrors the system
6846 // 'as' behaviour. Make sure the wide encoding wasn't explicit.
6847 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
6848 Inst.getOperand(5).getReg() != 0 ||
6849 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
6850 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
6853 TmpInst.setOpcode(ARM::tADDhirr);
6854 TmpInst.addOperand(Inst.getOperand(0));
6855 TmpInst.addOperand(Inst.getOperand(0));
6856 TmpInst.addOperand(Inst.getOperand(2));
6857 TmpInst.addOperand(Inst.getOperand(3));
6858 TmpInst.addOperand(Inst.getOperand(4));
6863 // A Thumb conditional branch outside of an IT block is a tBcc.
6864 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
6865 Inst.setOpcode(ARM::tBcc);
6870 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
6871 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
6872 Inst.setOpcode(ARM::t2Bcc);
6877 // If the conditional is AL or we're in an IT block, we really want t2B.
6878 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
6879 Inst.setOpcode(ARM::t2B);
6884 // If the conditional is AL, we really want tB.
6885 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
6886 Inst.setOpcode(ARM::tB);
6891 // If the register list contains any high registers, or if the writeback
6892 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
6893 // instead if we're in Thumb2. Otherwise, this should have generated
6894 // an error in validateInstruction().
6895 unsigned Rn = Inst.getOperand(0).getReg();
6896 bool hasWritebackToken =
6897 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
6898 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
6899 bool listContainsBase;
6900 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
6901 (!listContainsBase && !hasWritebackToken) ||
6902 (listContainsBase && hasWritebackToken)) {
6903 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
6904 assert (isThumbTwo());
6905 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
6906 // If we're switching to the updating version, we need to insert
6907 // the writeback tied operand.
6908 if (hasWritebackToken)
6909 Inst.insert(Inst.begin(),
6910 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
6915 case ARM::tSTMIA_UPD: {
6916 // If the register list contains any high registers, we need to use
6917 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
6918 // should have generated an error in validateInstruction().
6919 unsigned Rn = Inst.getOperand(0).getReg();
6920 bool listContainsBase;
6921 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
6922 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
6923 assert (isThumbTwo());
6924 Inst.setOpcode(ARM::t2STMIA_UPD);
6930 bool listContainsBase;
6931 // If the register list contains any high registers, we need to use
6932 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
6933 // should have generated an error in validateInstruction().
6934 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
6936 assert (isThumbTwo());
6937 Inst.setOpcode(ARM::t2LDMIA_UPD);
6938 // Add the base register and writeback operands.
6939 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
6940 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
6944 bool listContainsBase;
6945 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
6947 assert (isThumbTwo());
6948 Inst.setOpcode(ARM::t2STMDB_UPD);
6949 // Add the base register and writeback operands.
6950 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
6951 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
6955 // If we can use the 16-bit encoding and the user didn't explicitly
6956 // request the 32-bit variant, transform it here.
6957 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6958 Inst.getOperand(1).getImm() <= 255 &&
6959 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
6960 Inst.getOperand(4).getReg() == ARM::CPSR) ||
6961 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
6962 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
6963 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
6964 // The operands aren't in the same order for tMOVi8...
6966 TmpInst.setOpcode(ARM::tMOVi8);
6967 TmpInst.addOperand(Inst.getOperand(0));
6968 TmpInst.addOperand(Inst.getOperand(4));
6969 TmpInst.addOperand(Inst.getOperand(1));
6970 TmpInst.addOperand(Inst.getOperand(2));
6971 TmpInst.addOperand(Inst.getOperand(3));
6978 // If we can use the 16-bit encoding and the user didn't explicitly
6979 // request the 32-bit variant, transform it here.
6980 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6981 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6982 Inst.getOperand(2).getImm() == ARMCC::AL &&
6983 Inst.getOperand(4).getReg() == ARM::CPSR &&
6984 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
6985 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
6986 // The operands aren't the same for tMOV[S]r... (no cc_out)
6988 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
6989 TmpInst.addOperand(Inst.getOperand(0));
6990 TmpInst.addOperand(Inst.getOperand(1));
6991 TmpInst.addOperand(Inst.getOperand(2));
6992 TmpInst.addOperand(Inst.getOperand(3));
7002 // If we can use the 16-bit encoding and the user didn't explicitly
7003 // request the 32-bit variant, transform it here.
7004 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7005 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7006 Inst.getOperand(2).getImm() == 0 &&
7007 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7008 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7010 switch (Inst.getOpcode()) {
7011 default: llvm_unreachable("Illegal opcode!");
7012 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7013 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7014 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7015 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7017 // The operands aren't the same for thumb1 (no rotate operand).
7019 TmpInst.setOpcode(NewOpc);
7020 TmpInst.addOperand(Inst.getOperand(0));
7021 TmpInst.addOperand(Inst.getOperand(1));
7022 TmpInst.addOperand(Inst.getOperand(3));
7023 TmpInst.addOperand(Inst.getOperand(4));
7030 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7031 if (SOpc == ARM_AM::rrx) return false;
7032 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7033 // Shifting by zero is accepted as a vanilla 'MOVr'
7035 TmpInst.setOpcode(ARM::MOVr);
7036 TmpInst.addOperand(Inst.getOperand(0));
7037 TmpInst.addOperand(Inst.getOperand(1));
7038 TmpInst.addOperand(Inst.getOperand(3));
7039 TmpInst.addOperand(Inst.getOperand(4));
7040 TmpInst.addOperand(Inst.getOperand(5));
7053 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7054 if (SOpc == ARM_AM::rrx) return false;
7055 switch (Inst.getOpcode()) {
7056 default: llvm_unreachable("unexpected opcode!");
7057 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7058 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7059 case ARM::EORrsi: newOpc = ARM::EORrr; break;
7060 case ARM::BICrsi: newOpc = ARM::BICrr; break;
7061 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7062 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7064 // If the shift is by zero, use the non-shifted instruction definition.
7065 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0) {
7067 TmpInst.setOpcode(newOpc);
7068 TmpInst.addOperand(Inst.getOperand(0));
7069 TmpInst.addOperand(Inst.getOperand(1));
7070 TmpInst.addOperand(Inst.getOperand(2));
7071 TmpInst.addOperand(Inst.getOperand(4));
7072 TmpInst.addOperand(Inst.getOperand(5));
7073 TmpInst.addOperand(Inst.getOperand(6));
7081 // The mask bits for all but the first condition are represented as
7082 // the low bit of the condition code value implies 't'. We currently
7083 // always have 1 implies 't', so XOR toggle the bits if the low bit
7084 // of the condition code is zero. The encoding also expects the low
7085 // bit of the condition to be encoded as bit 4 of the mask operand,
7086 // so mask that in if needed
7087 MCOperand &MO = Inst.getOperand(1);
7088 unsigned Mask = MO.getImm();
7089 unsigned OrigMask = Mask;
7090 unsigned TZ = CountTrailingZeros_32(Mask);
7091 if ((Inst.getOperand(0).getImm() & 1) == 0) {
7092 assert(Mask && TZ <= 3 && "illegal IT mask value!");
7093 for (unsigned i = 3; i != TZ; --i)
7099 // Set up the IT block state according to the IT instruction we just
7101 assert(!inITBlock() && "nested IT blocks?!");
7102 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7103 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7104 ITState.CurPosition = 0;
7105 ITState.FirstCond = true;
7112 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7113 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7114 // suffix depending on whether they're in an IT block or not.
7115 unsigned Opc = Inst.getOpcode();
7116 const MCInstrDesc &MCID = getInstDesc(Opc);
7117 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7118 assert(MCID.hasOptionalDef() &&
7119 "optionally flag setting instruction missing optional def operand");
7120 assert(MCID.NumOperands == Inst.getNumOperands() &&
7121 "operand count mismatch!");
7122 // Find the optional-def operand (cc_out).
7125 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7128 // If we're parsing Thumb1, reject it completely.
7129 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7130 return Match_MnemonicFail;
7131 // If we're parsing Thumb2, which form is legal depends on whether we're
7133 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7135 return Match_RequiresITBlock;
7136 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7138 return Match_RequiresNotITBlock;
7140 // Some high-register supporting Thumb1 encodings only allow both registers
7141 // to be from r0-r7 when in Thumb2.
7142 else if (Opc == ARM::tADDhirr && isThumbOne() &&
7143 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7144 isARMLowRegister(Inst.getOperand(2).getReg()))
7145 return Match_RequiresThumb2;
7146 // Others only require ARMv6 or later.
7147 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7148 isARMLowRegister(Inst.getOperand(0).getReg()) &&
7149 isARMLowRegister(Inst.getOperand(1).getReg()))
7150 return Match_RequiresV6;
7151 return Match_Success;
7155 MatchAndEmitInstruction(SMLoc IDLoc,
7156 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
7160 unsigned MatchResult;
7161 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
7162 switch (MatchResult) {
7165 // Context sensitive operand constraints aren't handled by the matcher,
7166 // so check them here.
7167 if (validateInstruction(Inst, Operands)) {
7168 // Still progress the IT block, otherwise one wrong condition causes
7169 // nasty cascading errors.
7170 forwardITPosition();
7174 // Some instructions need post-processing to, for example, tweak which
7175 // encoding is selected. Loop on it while changes happen so the
7176 // individual transformations can chain off each other. E.g.,
7177 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
7178 while (processInstruction(Inst, Operands))
7181 // Only move forward at the very end so that everything in validate
7182 // and process gets a consistent answer about whether we're in an IT
7184 forwardITPosition();
7186 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7187 // doesn't actually encode.
7188 if (Inst.getOpcode() == ARM::ITasm)
7192 Out.EmitInstruction(Inst);
7194 case Match_MissingFeature:
7195 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
7197 case Match_InvalidOperand: {
7198 SMLoc ErrorLoc = IDLoc;
7199 if (ErrorInfo != ~0U) {
7200 if (ErrorInfo >= Operands.size())
7201 return Error(IDLoc, "too few operands for instruction");
7203 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7204 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7207 return Error(ErrorLoc, "invalid operand for instruction");
7209 case Match_MnemonicFail:
7210 return Error(IDLoc, "invalid instruction");
7211 case Match_ConversionFail:
7212 // The converter function will have already emited a diagnostic.
7214 case Match_RequiresNotITBlock:
7215 return Error(IDLoc, "flag setting instruction only valid outside IT block");
7216 case Match_RequiresITBlock:
7217 return Error(IDLoc, "instruction only valid inside IT block");
7218 case Match_RequiresV6:
7219 return Error(IDLoc, "instruction variant requires ARMv6 or later");
7220 case Match_RequiresThumb2:
7221 return Error(IDLoc, "instruction variant requires Thumb2");
7224 llvm_unreachable("Implement any new match types added!");
7227 /// parseDirective parses the arm specific directives
7228 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
7229 StringRef IDVal = DirectiveID.getIdentifier();
7230 if (IDVal == ".word")
7231 return parseDirectiveWord(4, DirectiveID.getLoc());
7232 else if (IDVal == ".thumb")
7233 return parseDirectiveThumb(DirectiveID.getLoc());
7234 else if (IDVal == ".arm")
7235 return parseDirectiveARM(DirectiveID.getLoc());
7236 else if (IDVal == ".thumb_func")
7237 return parseDirectiveThumbFunc(DirectiveID.getLoc());
7238 else if (IDVal == ".code")
7239 return parseDirectiveCode(DirectiveID.getLoc());
7240 else if (IDVal == ".syntax")
7241 return parseDirectiveSyntax(DirectiveID.getLoc());
7242 else if (IDVal == ".unreq")
7243 return parseDirectiveUnreq(DirectiveID.getLoc());
7244 else if (IDVal == ".arch")
7245 return parseDirectiveArch(DirectiveID.getLoc());
7246 else if (IDVal == ".eabi_attribute")
7247 return parseDirectiveEabiAttr(DirectiveID.getLoc());
7251 /// parseDirectiveWord
7252 /// ::= .word [ expression (, expression)* ]
7253 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
7254 if (getLexer().isNot(AsmToken::EndOfStatement)) {
7256 const MCExpr *Value;
7257 if (getParser().ParseExpression(Value))
7260 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
7262 if (getLexer().is(AsmToken::EndOfStatement))
7265 // FIXME: Improve diagnostic.
7266 if (getLexer().isNot(AsmToken::Comma))
7267 return Error(L, "unexpected token in directive");
7276 /// parseDirectiveThumb
7278 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
7279 if (getLexer().isNot(AsmToken::EndOfStatement))
7280 return Error(L, "unexpected token in directive");
7285 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7289 /// parseDirectiveARM
7291 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
7292 if (getLexer().isNot(AsmToken::EndOfStatement))
7293 return Error(L, "unexpected token in directive");
7298 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7302 /// parseDirectiveThumbFunc
7303 /// ::= .thumbfunc symbol_name
7304 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
7305 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
7306 bool isMachO = MAI.hasSubsectionsViaSymbols();
7308 bool needFuncName = true;
7310 // Darwin asm has (optionally) function name after .thumb_func direction
7313 const AsmToken &Tok = Parser.getTok();
7314 if (Tok.isNot(AsmToken::EndOfStatement)) {
7315 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
7316 return Error(L, "unexpected token in .thumb_func directive");
7317 Name = Tok.getIdentifier();
7318 Parser.Lex(); // Consume the identifier token.
7319 needFuncName = false;
7323 if (getLexer().isNot(AsmToken::EndOfStatement))
7324 return Error(L, "unexpected token in directive");
7326 // Eat the end of statement and any blank lines that follow.
7327 while (getLexer().is(AsmToken::EndOfStatement))
7330 // FIXME: assuming function name will be the line following .thumb_func
7331 // We really should be checking the next symbol definition even if there's
7332 // stuff in between.
7334 Name = Parser.getTok().getIdentifier();
7337 // Mark symbol as a thumb symbol.
7338 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
7339 getParser().getStreamer().EmitThumbFunc(Func);
7343 /// parseDirectiveSyntax
7344 /// ::= .syntax unified | divided
7345 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
7346 const AsmToken &Tok = Parser.getTok();
7347 if (Tok.isNot(AsmToken::Identifier))
7348 return Error(L, "unexpected token in .syntax directive");
7349 StringRef Mode = Tok.getString();
7350 if (Mode == "unified" || Mode == "UNIFIED")
7352 else if (Mode == "divided" || Mode == "DIVIDED")
7353 return Error(L, "'.syntax divided' arm asssembly not supported");
7355 return Error(L, "unrecognized syntax mode in .syntax directive");
7357 if (getLexer().isNot(AsmToken::EndOfStatement))
7358 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7361 // TODO tell the MC streamer the mode
7362 // getParser().getStreamer().Emit???();
7366 /// parseDirectiveCode
7367 /// ::= .code 16 | 32
7368 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
7369 const AsmToken &Tok = Parser.getTok();
7370 if (Tok.isNot(AsmToken::Integer))
7371 return Error(L, "unexpected token in .code directive");
7372 int64_t Val = Parser.getTok().getIntVal();
7378 return Error(L, "invalid operand to .code directive");
7380 if (getLexer().isNot(AsmToken::EndOfStatement))
7381 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7387 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7391 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7397 /// parseDirectiveReq
7398 /// ::= name .req registername
7399 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
7400 Parser.Lex(); // Eat the '.req' token.
7402 SMLoc SRegLoc, ERegLoc;
7403 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
7404 Parser.EatToEndOfStatement();
7405 return Error(SRegLoc, "register name expected");
7408 // Shouldn't be anything else.
7409 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
7410 Parser.EatToEndOfStatement();
7411 return Error(Parser.getTok().getLoc(),
7412 "unexpected input in .req directive.");
7415 Parser.Lex(); // Consume the EndOfStatement
7417 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg)
7418 return Error(SRegLoc, "redefinition of '" + Name +
7419 "' does not match original.");
7424 /// parseDirectiveUneq
7425 /// ::= .unreq registername
7426 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
7427 if (Parser.getTok().isNot(AsmToken::Identifier)) {
7428 Parser.EatToEndOfStatement();
7429 return Error(L, "unexpected input in .unreq directive.");
7431 RegisterReqs.erase(Parser.getTok().getIdentifier());
7432 Parser.Lex(); // Eat the identifier.
7436 /// parseDirectiveArch
7438 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
7442 /// parseDirectiveEabiAttr
7443 /// ::= .eabi_attribute int, int
7444 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
7448 extern "C" void LLVMInitializeARMAsmLexer();
7450 /// Force static initialization.
7451 extern "C" void LLVMInitializeARMAsmParser() {
7452 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
7453 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
7454 LLVMInitializeARMAsmLexer();
7457 #define GET_REGISTER_MATCHER
7458 #define GET_MATCHER_IMPLEMENTATION
7459 #include "ARMGenAsmMatcher.inc"