1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMBaseInfo.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMMCExpr.h"
13 #include "llvm/MC/MCParser/MCAsmLexer.h"
14 #include "llvm/MC/MCParser/MCAsmParser.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCAsmInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCTargetAsmParser.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/SourceMgr.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/ADT/BitVector.h"
30 #include "llvm/ADT/OwningPtr.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/StringSwitch.h"
34 #include "llvm/ADT/Twine.h"
42 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
44 class ARMAsmParser : public MCTargetAsmParser {
47 const MCRegisterInfo *MRI;
49 // Map of register aliases registers via the .req directive.
50 StringMap<unsigned> RegisterReqs;
53 ARMCC::CondCodes Cond; // Condition for IT block.
54 unsigned Mask:4; // Condition mask for instructions.
55 // Starting at first 1 (from lsb).
56 // '1' condition as indicated in IT.
57 // '0' inverse of condition (else).
58 // Count of instructions in IT block is
59 // 4 - trailingzeroes(mask)
61 bool FirstCond; // Explicit flag for when we're parsing the
62 // First instruction in the IT block. It's
63 // implied in the mask, so needs special
66 unsigned CurPosition; // Current position in parsing of IT
67 // block. In range [0,3]. Initialized
68 // according to count of instructions in block.
69 // ~0U if no active IT block.
71 bool inITBlock() { return ITState.CurPosition != ~0U;}
72 void forwardITPosition() {
73 if (!inITBlock()) return;
74 // Move to the next instruction in the IT block, if there is one. If not,
75 // mark the block as done.
76 unsigned TZ = CountTrailingZeros_32(ITState.Mask);
77 if (++ITState.CurPosition == 5 - TZ)
78 ITState.CurPosition = ~0U; // Done with the IT block after this.
82 MCAsmParser &getParser() const { return Parser; }
83 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
85 bool Warning(SMLoc L, const Twine &Msg,
86 ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) {
87 return Parser.Warning(L, Msg, Ranges);
89 bool Error(SMLoc L, const Twine &Msg,
90 ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) {
91 return Parser.Error(L, Msg, Ranges);
94 int tryParseRegister();
95 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
96 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
97 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
98 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
99 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
100 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
101 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
102 unsigned &ShiftAmount);
103 bool parseDirectiveWord(unsigned Size, SMLoc L);
104 bool parseDirectiveThumb(SMLoc L);
105 bool parseDirectiveARM(SMLoc L);
106 bool parseDirectiveThumbFunc(SMLoc L);
107 bool parseDirectiveCode(SMLoc L);
108 bool parseDirectiveSyntax(SMLoc L);
109 bool parseDirectiveReq(StringRef Name, SMLoc L);
110 bool parseDirectiveUnreq(SMLoc L);
111 bool parseDirectiveArch(SMLoc L);
112 bool parseDirectiveEabiAttr(SMLoc L);
114 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
115 bool &CarrySetting, unsigned &ProcessorIMod,
117 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
118 bool &CanAcceptPredicationCode);
120 bool isThumb() const {
121 // FIXME: Can tablegen auto-generate this?
122 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
124 bool isThumbOne() const {
125 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
127 bool isThumbTwo() const {
128 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
130 bool hasV6Ops() const {
131 return STI.getFeatureBits() & ARM::HasV6Ops;
133 bool hasV7Ops() const {
134 return STI.getFeatureBits() & ARM::HasV7Ops;
137 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
138 setAvailableFeatures(FB);
140 bool isMClass() const {
141 return STI.getFeatureBits() & ARM::FeatureMClass;
144 /// @name Auto-generated Match Functions
147 #define GET_ASSEMBLER_HEADER
148 #include "ARMGenAsmMatcher.inc"
152 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
153 OperandMatchResultTy parseCoprocNumOperand(
154 SmallVectorImpl<MCParsedAsmOperand*>&);
155 OperandMatchResultTy parseCoprocRegOperand(
156 SmallVectorImpl<MCParsedAsmOperand*>&);
157 OperandMatchResultTy parseCoprocOptionOperand(
158 SmallVectorImpl<MCParsedAsmOperand*>&);
159 OperandMatchResultTy parseMemBarrierOptOperand(
160 SmallVectorImpl<MCParsedAsmOperand*>&);
161 OperandMatchResultTy parseProcIFlagsOperand(
162 SmallVectorImpl<MCParsedAsmOperand*>&);
163 OperandMatchResultTy parseMSRMaskOperand(
164 SmallVectorImpl<MCParsedAsmOperand*>&);
165 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
166 StringRef Op, int Low, int High);
167 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
168 return parsePKHImm(O, "lsl", 0, 31);
170 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
171 return parsePKHImm(O, "asr", 1, 32);
173 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
174 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
175 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
176 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
177 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
178 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
179 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
180 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
181 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index);
183 // Asm Match Converter Methods
184 bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
185 const SmallVectorImpl<MCParsedAsmOperand*> &);
186 bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
187 const SmallVectorImpl<MCParsedAsmOperand*> &);
188 bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
189 const SmallVectorImpl<MCParsedAsmOperand*> &);
190 bool cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
191 const SmallVectorImpl<MCParsedAsmOperand*> &);
192 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
193 const SmallVectorImpl<MCParsedAsmOperand*> &);
194 bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
195 const SmallVectorImpl<MCParsedAsmOperand*> &);
196 bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
197 const SmallVectorImpl<MCParsedAsmOperand*> &);
198 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
199 const SmallVectorImpl<MCParsedAsmOperand*> &);
200 bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
201 const SmallVectorImpl<MCParsedAsmOperand*> &);
202 bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
203 const SmallVectorImpl<MCParsedAsmOperand*> &);
204 bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
205 const SmallVectorImpl<MCParsedAsmOperand*> &);
206 bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
207 const SmallVectorImpl<MCParsedAsmOperand*> &);
208 bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
209 const SmallVectorImpl<MCParsedAsmOperand*> &);
210 bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
211 const SmallVectorImpl<MCParsedAsmOperand*> &);
212 bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
213 const SmallVectorImpl<MCParsedAsmOperand*> &);
214 bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
215 const SmallVectorImpl<MCParsedAsmOperand*> &);
216 bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
217 const SmallVectorImpl<MCParsedAsmOperand*> &);
218 bool cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
219 const SmallVectorImpl<MCParsedAsmOperand*> &);
220 bool cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
221 const SmallVectorImpl<MCParsedAsmOperand*> &);
222 bool cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
223 const SmallVectorImpl<MCParsedAsmOperand*> &);
224 bool cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
225 const SmallVectorImpl<MCParsedAsmOperand*> &);
227 bool validateInstruction(MCInst &Inst,
228 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
229 bool processInstruction(MCInst &Inst,
230 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
231 bool shouldOmitCCOutOperand(StringRef Mnemonic,
232 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
235 enum ARMMatchResultTy {
236 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
237 Match_RequiresNotITBlock,
239 Match_RequiresThumb2,
240 #define GET_OPERAND_DIAGNOSTIC_TYPES
241 #include "ARMGenAsmMatcher.inc"
245 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
246 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
247 MCAsmParserExtension::Initialize(_Parser);
249 // Cache the MCRegisterInfo.
250 MRI = &getContext().getRegisterInfo();
252 // Initialize the set of available features.
253 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
255 // Not in an ITBlock to start with.
256 ITState.CurPosition = ~0U;
259 // Implementation of the MCTargetAsmParser interface:
260 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
261 bool ParseInstruction(StringRef Name, SMLoc NameLoc,
262 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
263 bool ParseDirective(AsmToken DirectiveID);
265 unsigned checkTargetMatchPredicate(MCInst &Inst);
267 bool MatchAndEmitInstruction(SMLoc IDLoc,
268 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
271 } // end anonymous namespace
275 /// ARMOperand - Instances of this class represent a parsed ARM machine
277 class ARMOperand : public MCParsedAsmOperand {
297 k_VectorListAllLanes,
303 k_BitfieldDescriptor,
307 SMLoc StartLoc, EndLoc;
308 SmallVector<unsigned, 8> Registers;
312 ARMCC::CondCodes Val;
332 ARM_PROC::IFlags Val;
348 // A vector register list is a sequential list of 1 to 4 registers.
364 /// Combined record for all forms of ARM address expressions.
367 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
369 const MCConstantExpr *OffsetImm; // Offset immediate value
370 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
371 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
372 unsigned ShiftImm; // shift for OffsetReg.
373 unsigned Alignment; // 0 = no alignment specified
374 // n = alignment in bytes (2, 4, 8, 16, or 32)
375 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
381 ARM_AM::ShiftOpc ShiftTy;
390 ARM_AM::ShiftOpc ShiftTy;
396 ARM_AM::ShiftOpc ShiftTy;
409 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
411 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
413 StartLoc = o.StartLoc;
430 case k_DPRRegisterList:
431 case k_SPRRegisterList:
432 Registers = o.Registers;
435 case k_VectorListAllLanes:
436 case k_VectorListIndexed:
437 VectorList = o.VectorList;
444 CoprocOption = o.CoprocOption;
449 case k_MemBarrierOpt:
455 case k_PostIndexRegister:
456 PostIdxReg = o.PostIdxReg;
464 case k_ShifterImmediate:
465 ShifterImm = o.ShifterImm;
467 case k_ShiftedRegister:
468 RegShiftedReg = o.RegShiftedReg;
470 case k_ShiftedImmediate:
471 RegShiftedImm = o.RegShiftedImm;
473 case k_RotateImmediate:
476 case k_BitfieldDescriptor:
477 Bitfield = o.Bitfield;
480 VectorIndex = o.VectorIndex;
485 /// getStartLoc - Get the location of the first token of this operand.
486 SMLoc getStartLoc() const { return StartLoc; }
487 /// getEndLoc - Get the location of the last token of this operand.
488 SMLoc getEndLoc() const { return EndLoc; }
490 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
492 ARMCC::CondCodes getCondCode() const {
493 assert(Kind == k_CondCode && "Invalid access!");
497 unsigned getCoproc() const {
498 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
502 StringRef getToken() const {
503 assert(Kind == k_Token && "Invalid access!");
504 return StringRef(Tok.Data, Tok.Length);
507 unsigned getReg() const {
508 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
512 const SmallVectorImpl<unsigned> &getRegList() const {
513 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
514 Kind == k_SPRRegisterList) && "Invalid access!");
518 const MCExpr *getImm() const {
519 assert(isImm() && "Invalid access!");
523 unsigned getVectorIndex() const {
524 assert(Kind == k_VectorIndex && "Invalid access!");
525 return VectorIndex.Val;
528 ARM_MB::MemBOpt getMemBarrierOpt() const {
529 assert(Kind == k_MemBarrierOpt && "Invalid access!");
533 ARM_PROC::IFlags getProcIFlags() const {
534 assert(Kind == k_ProcIFlags && "Invalid access!");
538 unsigned getMSRMask() const {
539 assert(Kind == k_MSRMask && "Invalid access!");
543 bool isCoprocNum() const { return Kind == k_CoprocNum; }
544 bool isCoprocReg() const { return Kind == k_CoprocReg; }
545 bool isCoprocOption() const { return Kind == k_CoprocOption; }
546 bool isCondCode() const { return Kind == k_CondCode; }
547 bool isCCOut() const { return Kind == k_CCOut; }
548 bool isITMask() const { return Kind == k_ITCondMask; }
549 bool isITCondCode() const { return Kind == k_CondCode; }
550 bool isImm() const { return Kind == k_Immediate; }
551 bool isFPImm() const {
552 if (!isImm()) return false;
553 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
554 if (!CE) return false;
555 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
558 bool isFBits16() const {
559 if (!isImm()) return false;
560 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
561 if (!CE) return false;
562 int64_t Value = CE->getValue();
563 return Value >= 0 && Value <= 16;
565 bool isFBits32() const {
566 if (!isImm()) return false;
567 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
568 if (!CE) return false;
569 int64_t Value = CE->getValue();
570 return Value >= 1 && Value <= 32;
572 bool isImm8s4() const {
573 if (!isImm()) return false;
574 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
575 if (!CE) return false;
576 int64_t Value = CE->getValue();
577 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
579 bool isImm0_1020s4() const {
580 if (!isImm()) return false;
581 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
582 if (!CE) return false;
583 int64_t Value = CE->getValue();
584 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
586 bool isImm0_508s4() const {
587 if (!isImm()) return false;
588 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
589 if (!CE) return false;
590 int64_t Value = CE->getValue();
591 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
593 bool isImm0_508s4Neg() const {
594 if (!isImm()) return false;
595 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
596 if (!CE) return false;
597 int64_t Value = -CE->getValue();
598 // explicitly exclude zero. we want that to use the normal 0_508 version.
599 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
601 bool isImm0_255() const {
602 if (!isImm()) return false;
603 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
604 if (!CE) return false;
605 int64_t Value = CE->getValue();
606 return Value >= 0 && Value < 256;
608 bool isImm0_4095() const {
609 if (!isImm()) return false;
610 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
611 if (!CE) return false;
612 int64_t Value = CE->getValue();
613 return Value >= 0 && Value < 4096;
615 bool isImm0_4095Neg() const {
616 if (!isImm()) return false;
617 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
618 if (!CE) return false;
619 int64_t Value = -CE->getValue();
620 return Value > 0 && Value < 4096;
622 bool isImm0_1() const {
623 if (!isImm()) return false;
624 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
625 if (!CE) return false;
626 int64_t Value = CE->getValue();
627 return Value >= 0 && Value < 2;
629 bool isImm0_3() const {
630 if (!isImm()) return false;
631 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
632 if (!CE) return false;
633 int64_t Value = CE->getValue();
634 return Value >= 0 && Value < 4;
636 bool isImm0_7() const {
637 if (!isImm()) return false;
638 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
639 if (!CE) return false;
640 int64_t Value = CE->getValue();
641 return Value >= 0 && Value < 8;
643 bool isImm0_15() const {
644 if (!isImm()) return false;
645 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
646 if (!CE) return false;
647 int64_t Value = CE->getValue();
648 return Value >= 0 && Value < 16;
650 bool isImm0_31() const {
651 if (!isImm()) return false;
652 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
653 if (!CE) return false;
654 int64_t Value = CE->getValue();
655 return Value >= 0 && Value < 32;
657 bool isImm0_63() const {
658 if (!isImm()) return false;
659 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
660 if (!CE) return false;
661 int64_t Value = CE->getValue();
662 return Value >= 0 && Value < 64;
664 bool isImm8() const {
665 if (!isImm()) return false;
666 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
667 if (!CE) return false;
668 int64_t Value = CE->getValue();
671 bool isImm16() const {
672 if (!isImm()) return false;
673 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
674 if (!CE) return false;
675 int64_t Value = CE->getValue();
678 bool isImm32() const {
679 if (!isImm()) return false;
680 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
681 if (!CE) return false;
682 int64_t Value = CE->getValue();
685 bool isShrImm8() const {
686 if (!isImm()) return false;
687 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
688 if (!CE) return false;
689 int64_t Value = CE->getValue();
690 return Value > 0 && Value <= 8;
692 bool isShrImm16() const {
693 if (!isImm()) return false;
694 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
695 if (!CE) return false;
696 int64_t Value = CE->getValue();
697 return Value > 0 && Value <= 16;
699 bool isShrImm32() const {
700 if (!isImm()) return false;
701 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
702 if (!CE) return false;
703 int64_t Value = CE->getValue();
704 return Value > 0 && Value <= 32;
706 bool isShrImm64() const {
707 if (!isImm()) return false;
708 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
709 if (!CE) return false;
710 int64_t Value = CE->getValue();
711 return Value > 0 && Value <= 64;
713 bool isImm1_7() const {
714 if (!isImm()) return false;
715 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
716 if (!CE) return false;
717 int64_t Value = CE->getValue();
718 return Value > 0 && Value < 8;
720 bool isImm1_15() const {
721 if (!isImm()) return false;
722 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
723 if (!CE) return false;
724 int64_t Value = CE->getValue();
725 return Value > 0 && Value < 16;
727 bool isImm1_31() const {
728 if (!isImm()) return false;
729 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
730 if (!CE) return false;
731 int64_t Value = CE->getValue();
732 return Value > 0 && Value < 32;
734 bool isImm1_16() const {
735 if (!isImm()) return false;
736 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
737 if (!CE) return false;
738 int64_t Value = CE->getValue();
739 return Value > 0 && Value < 17;
741 bool isImm1_32() const {
742 if (!isImm()) return false;
743 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
744 if (!CE) return false;
745 int64_t Value = CE->getValue();
746 return Value > 0 && Value < 33;
748 bool isImm0_32() const {
749 if (!isImm()) return false;
750 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
751 if (!CE) return false;
752 int64_t Value = CE->getValue();
753 return Value >= 0 && Value < 33;
755 bool isImm0_65535() const {
756 if (!isImm()) return false;
757 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
758 if (!CE) return false;
759 int64_t Value = CE->getValue();
760 return Value >= 0 && Value < 65536;
762 bool isImm0_65535Expr() const {
763 if (!isImm()) return false;
764 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
765 // If it's not a constant expression, it'll generate a fixup and be
767 if (!CE) return true;
768 int64_t Value = CE->getValue();
769 return Value >= 0 && Value < 65536;
771 bool isImm24bit() const {
772 if (!isImm()) return false;
773 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
774 if (!CE) return false;
775 int64_t Value = CE->getValue();
776 return Value >= 0 && Value <= 0xffffff;
778 bool isImmThumbSR() const {
779 if (!isImm()) return false;
780 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
781 if (!CE) return false;
782 int64_t Value = CE->getValue();
783 return Value > 0 && Value < 33;
785 bool isPKHLSLImm() const {
786 if (!isImm()) return false;
787 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
788 if (!CE) return false;
789 int64_t Value = CE->getValue();
790 return Value >= 0 && Value < 32;
792 bool isPKHASRImm() const {
793 if (!isImm()) return false;
794 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
795 if (!CE) return false;
796 int64_t Value = CE->getValue();
797 return Value > 0 && Value <= 32;
799 bool isAdrLabel() const {
800 // If we have an immediate that's not a constant, treat it as a label
801 // reference needing a fixup. If it is a constant, but it can't fit
802 // into shift immediate encoding, we reject it.
803 if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
804 else return (isARMSOImm() || isARMSOImmNeg());
806 bool isARMSOImm() const {
807 if (!isImm()) return false;
808 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
809 if (!CE) return false;
810 int64_t Value = CE->getValue();
811 return ARM_AM::getSOImmVal(Value) != -1;
813 bool isARMSOImmNot() const {
814 if (!isImm()) return false;
815 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
816 if (!CE) return false;
817 int64_t Value = CE->getValue();
818 return ARM_AM::getSOImmVal(~Value) != -1;
820 bool isARMSOImmNeg() const {
821 if (!isImm()) return false;
822 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
823 if (!CE) return false;
824 int64_t Value = CE->getValue();
825 // Only use this when not representable as a plain so_imm.
826 return ARM_AM::getSOImmVal(Value) == -1 &&
827 ARM_AM::getSOImmVal(-Value) != -1;
829 bool isT2SOImm() const {
830 if (!isImm()) return false;
831 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
832 if (!CE) return false;
833 int64_t Value = CE->getValue();
834 return ARM_AM::getT2SOImmVal(Value) != -1;
836 bool isT2SOImmNot() const {
837 if (!isImm()) return false;
838 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
839 if (!CE) return false;
840 int64_t Value = CE->getValue();
841 return ARM_AM::getT2SOImmVal(~Value) != -1;
843 bool isT2SOImmNeg() const {
844 if (!isImm()) return false;
845 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
846 if (!CE) return false;
847 int64_t Value = CE->getValue();
848 // Only use this when not representable as a plain so_imm.
849 return ARM_AM::getT2SOImmVal(Value) == -1 &&
850 ARM_AM::getT2SOImmVal(-Value) != -1;
852 bool isSetEndImm() const {
853 if (!isImm()) return false;
854 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
855 if (!CE) return false;
856 int64_t Value = CE->getValue();
857 return Value == 1 || Value == 0;
859 bool isReg() const { return Kind == k_Register; }
860 bool isRegList() const { return Kind == k_RegisterList; }
861 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
862 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
863 bool isToken() const { return Kind == k_Token; }
864 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
865 bool isMemory() const { return Kind == k_Memory; }
866 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
867 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
868 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
869 bool isRotImm() const { return Kind == k_RotateImmediate; }
870 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
871 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
872 bool isPostIdxReg() const {
873 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
875 bool isMemNoOffset(bool alignOK = false) const {
878 // No offset of any kind.
879 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
880 (alignOK || Memory.Alignment == 0);
882 bool isMemPCRelImm12() const {
883 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
885 // Base register must be PC.
886 if (Memory.BaseRegNum != ARM::PC)
888 // Immediate offset in range [-4095, 4095].
889 if (!Memory.OffsetImm) return true;
890 int64_t Val = Memory.OffsetImm->getValue();
891 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
893 bool isAlignedMemory() const {
894 return isMemNoOffset(true);
896 bool isAddrMode2() const {
897 if (!isMemory() || Memory.Alignment != 0) return false;
898 // Check for register offset.
899 if (Memory.OffsetRegNum) return true;
900 // Immediate offset in range [-4095, 4095].
901 if (!Memory.OffsetImm) return true;
902 int64_t Val = Memory.OffsetImm->getValue();
903 return Val > -4096 && Val < 4096;
905 bool isAM2OffsetImm() const {
906 if (!isImm()) return false;
907 // Immediate offset in range [-4095, 4095].
908 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
909 if (!CE) return false;
910 int64_t Val = CE->getValue();
911 return Val > -4096 && Val < 4096;
913 bool isAddrMode3() const {
914 // If we have an immediate that's not a constant, treat it as a label
915 // reference needing a fixup. If it is a constant, it's something else
917 if (isImm() && !isa<MCConstantExpr>(getImm()))
919 if (!isMemory() || Memory.Alignment != 0) return false;
920 // No shifts are legal for AM3.
921 if (Memory.ShiftType != ARM_AM::no_shift) return false;
922 // Check for register offset.
923 if (Memory.OffsetRegNum) return true;
924 // Immediate offset in range [-255, 255].
925 if (!Memory.OffsetImm) return true;
926 int64_t Val = Memory.OffsetImm->getValue();
927 // The #-0 offset is encoded as INT32_MIN, and we have to check
929 return (Val > -256 && Val < 256) || Val == INT32_MIN;
931 bool isAM3Offset() const {
932 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
934 if (Kind == k_PostIndexRegister)
935 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
936 // Immediate offset in range [-255, 255].
937 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
938 if (!CE) return false;
939 int64_t Val = CE->getValue();
940 // Special case, #-0 is INT32_MIN.
941 return (Val > -256 && Val < 256) || Val == INT32_MIN;
943 bool isAddrMode5() const {
944 // If we have an immediate that's not a constant, treat it as a label
945 // reference needing a fixup. If it is a constant, it's something else
947 if (isImm() && !isa<MCConstantExpr>(getImm()))
949 if (!isMemory() || Memory.Alignment != 0) return false;
950 // Check for register offset.
951 if (Memory.OffsetRegNum) return false;
952 // Immediate offset in range [-1020, 1020] and a multiple of 4.
953 if (!Memory.OffsetImm) return true;
954 int64_t Val = Memory.OffsetImm->getValue();
955 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
958 bool isMemTBB() const {
959 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
960 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
964 bool isMemTBH() const {
965 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
966 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
967 Memory.Alignment != 0 )
971 bool isMemRegOffset() const {
972 if (!isMemory() || !Memory.OffsetRegNum || Memory.Alignment != 0)
976 bool isT2MemRegOffset() const {
977 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
978 Memory.Alignment != 0)
980 // Only lsl #{0, 1, 2, 3} allowed.
981 if (Memory.ShiftType == ARM_AM::no_shift)
983 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
987 bool isMemThumbRR() const {
988 // Thumb reg+reg addressing is simple. Just two registers, a base and
989 // an offset. No shifts, negations or any other complicating factors.
990 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
991 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
993 return isARMLowRegister(Memory.BaseRegNum) &&
994 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
996 bool isMemThumbRIs4() const {
997 if (!isMemory() || Memory.OffsetRegNum != 0 ||
998 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1000 // Immediate offset, multiple of 4 in range [0, 124].
1001 if (!Memory.OffsetImm) return true;
1002 int64_t Val = Memory.OffsetImm->getValue();
1003 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1005 bool isMemThumbRIs2() const {
1006 if (!isMemory() || Memory.OffsetRegNum != 0 ||
1007 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1009 // Immediate offset, multiple of 4 in range [0, 62].
1010 if (!Memory.OffsetImm) return true;
1011 int64_t Val = Memory.OffsetImm->getValue();
1012 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1014 bool isMemThumbRIs1() const {
1015 if (!isMemory() || Memory.OffsetRegNum != 0 ||
1016 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1018 // Immediate offset in range [0, 31].
1019 if (!Memory.OffsetImm) return true;
1020 int64_t Val = Memory.OffsetImm->getValue();
1021 return Val >= 0 && Val <= 31;
1023 bool isMemThumbSPI() const {
1024 if (!isMemory() || Memory.OffsetRegNum != 0 ||
1025 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1027 // Immediate offset, multiple of 4 in range [0, 1020].
1028 if (!Memory.OffsetImm) return true;
1029 int64_t Val = Memory.OffsetImm->getValue();
1030 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1032 bool isMemImm8s4Offset() const {
1033 // If we have an immediate that's not a constant, treat it as a label
1034 // reference needing a fixup. If it is a constant, it's something else
1035 // and we reject it.
1036 if (isImm() && !isa<MCConstantExpr>(getImm()))
1038 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1040 // Immediate offset a multiple of 4 in range [-1020, 1020].
1041 if (!Memory.OffsetImm) return true;
1042 int64_t Val = Memory.OffsetImm->getValue();
1043 return Val >= -1020 && Val <= 1020 && (Val & 3) == 0;
1045 bool isMemImm0_1020s4Offset() const {
1046 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1048 // Immediate offset a multiple of 4 in range [0, 1020].
1049 if (!Memory.OffsetImm) return true;
1050 int64_t Val = Memory.OffsetImm->getValue();
1051 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1053 bool isMemImm8Offset() const {
1054 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1056 // Base reg of PC isn't allowed for these encodings.
1057 if (Memory.BaseRegNum == ARM::PC) return false;
1058 // Immediate offset in range [-255, 255].
1059 if (!Memory.OffsetImm) return true;
1060 int64_t Val = Memory.OffsetImm->getValue();
1061 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1063 bool isMemPosImm8Offset() const {
1064 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1066 // Immediate offset in range [0, 255].
1067 if (!Memory.OffsetImm) return true;
1068 int64_t Val = Memory.OffsetImm->getValue();
1069 return Val >= 0 && Val < 256;
1071 bool isMemNegImm8Offset() const {
1072 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1074 // Base reg of PC isn't allowed for these encodings.
1075 if (Memory.BaseRegNum == ARM::PC) return false;
1076 // Immediate offset in range [-255, -1].
1077 if (!Memory.OffsetImm) return false;
1078 int64_t Val = Memory.OffsetImm->getValue();
1079 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1081 bool isMemUImm12Offset() const {
1082 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1084 // Immediate offset in range [0, 4095].
1085 if (!Memory.OffsetImm) return true;
1086 int64_t Val = Memory.OffsetImm->getValue();
1087 return (Val >= 0 && Val < 4096);
1089 bool isMemImm12Offset() const {
1090 // If we have an immediate that's not a constant, treat it as a label
1091 // reference needing a fixup. If it is a constant, it's something else
1092 // and we reject it.
1093 if (isImm() && !isa<MCConstantExpr>(getImm()))
1096 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1098 // Immediate offset in range [-4095, 4095].
1099 if (!Memory.OffsetImm) return true;
1100 int64_t Val = Memory.OffsetImm->getValue();
1101 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1103 bool isPostIdxImm8() const {
1104 if (!isImm()) return false;
1105 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1106 if (!CE) return false;
1107 int64_t Val = CE->getValue();
1108 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1110 bool isPostIdxImm8s4() const {
1111 if (!isImm()) return false;
1112 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1113 if (!CE) return false;
1114 int64_t Val = CE->getValue();
1115 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1119 bool isMSRMask() const { return Kind == k_MSRMask; }
1120 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1123 bool isSingleSpacedVectorList() const {
1124 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1126 bool isDoubleSpacedVectorList() const {
1127 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1129 bool isVecListOneD() const {
1130 if (!isSingleSpacedVectorList()) return false;
1131 return VectorList.Count == 1;
1134 bool isVecListDPair() const {
1135 if (!isSingleSpacedVectorList()) return false;
1136 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1137 .contains(VectorList.RegNum));
1140 bool isVecListThreeD() const {
1141 if (!isSingleSpacedVectorList()) return false;
1142 return VectorList.Count == 3;
1145 bool isVecListFourD() const {
1146 if (!isSingleSpacedVectorList()) return false;
1147 return VectorList.Count == 4;
1150 bool isVecListDPairSpaced() const {
1151 if (isSingleSpacedVectorList()) return false;
1152 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1153 .contains(VectorList.RegNum));
1156 bool isVecListThreeQ() const {
1157 if (!isDoubleSpacedVectorList()) return false;
1158 return VectorList.Count == 3;
1161 bool isVecListFourQ() const {
1162 if (!isDoubleSpacedVectorList()) return false;
1163 return VectorList.Count == 4;
1166 bool isSingleSpacedVectorAllLanes() const {
1167 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1169 bool isDoubleSpacedVectorAllLanes() const {
1170 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1172 bool isVecListOneDAllLanes() const {
1173 if (!isSingleSpacedVectorAllLanes()) return false;
1174 return VectorList.Count == 1;
1177 bool isVecListDPairAllLanes() const {
1178 if (!isSingleSpacedVectorAllLanes()) return false;
1179 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1180 .contains(VectorList.RegNum));
1183 bool isVecListDPairSpacedAllLanes() const {
1184 if (!isDoubleSpacedVectorAllLanes()) return false;
1185 return VectorList.Count == 2;
1188 bool isVecListThreeDAllLanes() const {
1189 if (!isSingleSpacedVectorAllLanes()) return false;
1190 return VectorList.Count == 3;
1193 bool isVecListThreeQAllLanes() const {
1194 if (!isDoubleSpacedVectorAllLanes()) return false;
1195 return VectorList.Count == 3;
1198 bool isVecListFourDAllLanes() const {
1199 if (!isSingleSpacedVectorAllLanes()) return false;
1200 return VectorList.Count == 4;
1203 bool isVecListFourQAllLanes() const {
1204 if (!isDoubleSpacedVectorAllLanes()) return false;
1205 return VectorList.Count == 4;
1208 bool isSingleSpacedVectorIndexed() const {
1209 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1211 bool isDoubleSpacedVectorIndexed() const {
1212 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1214 bool isVecListOneDByteIndexed() const {
1215 if (!isSingleSpacedVectorIndexed()) return false;
1216 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1219 bool isVecListOneDHWordIndexed() const {
1220 if (!isSingleSpacedVectorIndexed()) return false;
1221 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1224 bool isVecListOneDWordIndexed() const {
1225 if (!isSingleSpacedVectorIndexed()) return false;
1226 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1229 bool isVecListTwoDByteIndexed() const {
1230 if (!isSingleSpacedVectorIndexed()) return false;
1231 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1234 bool isVecListTwoDHWordIndexed() const {
1235 if (!isSingleSpacedVectorIndexed()) return false;
1236 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1239 bool isVecListTwoQWordIndexed() const {
1240 if (!isDoubleSpacedVectorIndexed()) return false;
1241 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1244 bool isVecListTwoQHWordIndexed() const {
1245 if (!isDoubleSpacedVectorIndexed()) return false;
1246 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1249 bool isVecListTwoDWordIndexed() const {
1250 if (!isSingleSpacedVectorIndexed()) return false;
1251 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1254 bool isVecListThreeDByteIndexed() const {
1255 if (!isSingleSpacedVectorIndexed()) return false;
1256 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1259 bool isVecListThreeDHWordIndexed() const {
1260 if (!isSingleSpacedVectorIndexed()) return false;
1261 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1264 bool isVecListThreeQWordIndexed() const {
1265 if (!isDoubleSpacedVectorIndexed()) return false;
1266 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1269 bool isVecListThreeQHWordIndexed() const {
1270 if (!isDoubleSpacedVectorIndexed()) return false;
1271 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1274 bool isVecListThreeDWordIndexed() const {
1275 if (!isSingleSpacedVectorIndexed()) return false;
1276 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1279 bool isVecListFourDByteIndexed() const {
1280 if (!isSingleSpacedVectorIndexed()) return false;
1281 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1284 bool isVecListFourDHWordIndexed() const {
1285 if (!isSingleSpacedVectorIndexed()) return false;
1286 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1289 bool isVecListFourQWordIndexed() const {
1290 if (!isDoubleSpacedVectorIndexed()) return false;
1291 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1294 bool isVecListFourQHWordIndexed() const {
1295 if (!isDoubleSpacedVectorIndexed()) return false;
1296 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1299 bool isVecListFourDWordIndexed() const {
1300 if (!isSingleSpacedVectorIndexed()) return false;
1301 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1304 bool isVectorIndex8() const {
1305 if (Kind != k_VectorIndex) return false;
1306 return VectorIndex.Val < 8;
1308 bool isVectorIndex16() const {
1309 if (Kind != k_VectorIndex) return false;
1310 return VectorIndex.Val < 4;
1312 bool isVectorIndex32() const {
1313 if (Kind != k_VectorIndex) return false;
1314 return VectorIndex.Val < 2;
1317 bool isNEONi8splat() const {
1318 if (!isImm()) return false;
1319 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1320 // Must be a constant.
1321 if (!CE) return false;
1322 int64_t Value = CE->getValue();
1323 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1325 return Value >= 0 && Value < 256;
1328 bool isNEONi16splat() const {
1329 if (!isImm()) return false;
1330 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1331 // Must be a constant.
1332 if (!CE) return false;
1333 int64_t Value = CE->getValue();
1334 // i16 value in the range [0,255] or [0x0100, 0xff00]
1335 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1338 bool isNEONi32splat() const {
1339 if (!isImm()) return false;
1340 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1341 // Must be a constant.
1342 if (!CE) return false;
1343 int64_t Value = CE->getValue();
1344 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1345 return (Value >= 0 && Value < 256) ||
1346 (Value >= 0x0100 && Value <= 0xff00) ||
1347 (Value >= 0x010000 && Value <= 0xff0000) ||
1348 (Value >= 0x01000000 && Value <= 0xff000000);
1351 bool isNEONi32vmov() const {
1352 if (!isImm()) return false;
1353 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1354 // Must be a constant.
1355 if (!CE) return false;
1356 int64_t Value = CE->getValue();
1357 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1358 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1359 return (Value >= 0 && Value < 256) ||
1360 (Value >= 0x0100 && Value <= 0xff00) ||
1361 (Value >= 0x010000 && Value <= 0xff0000) ||
1362 (Value >= 0x01000000 && Value <= 0xff000000) ||
1363 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1364 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1366 bool isNEONi32vmovNeg() const {
1367 if (!isImm()) return false;
1368 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1369 // Must be a constant.
1370 if (!CE) return false;
1371 int64_t Value = ~CE->getValue();
1372 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1373 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1374 return (Value >= 0 && Value < 256) ||
1375 (Value >= 0x0100 && Value <= 0xff00) ||
1376 (Value >= 0x010000 && Value <= 0xff0000) ||
1377 (Value >= 0x01000000 && Value <= 0xff000000) ||
1378 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1379 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1382 bool isNEONi64splat() const {
1383 if (!isImm()) return false;
1384 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1385 // Must be a constant.
1386 if (!CE) return false;
1387 uint64_t Value = CE->getValue();
1388 // i64 value with each byte being either 0 or 0xff.
1389 for (unsigned i = 0; i < 8; ++i)
1390 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1394 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1395 // Add as immediates when possible. Null MCExpr = 0.
1397 Inst.addOperand(MCOperand::CreateImm(0));
1398 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1399 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1401 Inst.addOperand(MCOperand::CreateExpr(Expr));
1404 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1405 assert(N == 2 && "Invalid number of operands!");
1406 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1407 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1408 Inst.addOperand(MCOperand::CreateReg(RegNum));
1411 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1412 assert(N == 1 && "Invalid number of operands!");
1413 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1416 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1417 assert(N == 1 && "Invalid number of operands!");
1418 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1421 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1422 assert(N == 1 && "Invalid number of operands!");
1423 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1426 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1427 assert(N == 1 && "Invalid number of operands!");
1428 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1431 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1432 assert(N == 1 && "Invalid number of operands!");
1433 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1436 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1437 assert(N == 1 && "Invalid number of operands!");
1438 Inst.addOperand(MCOperand::CreateReg(getReg()));
1441 void addRegOperands(MCInst &Inst, unsigned N) const {
1442 assert(N == 1 && "Invalid number of operands!");
1443 Inst.addOperand(MCOperand::CreateReg(getReg()));
1446 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1447 assert(N == 3 && "Invalid number of operands!");
1448 assert(isRegShiftedReg() &&
1449 "addRegShiftedRegOperands() on non RegShiftedReg!");
1450 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1451 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1452 Inst.addOperand(MCOperand::CreateImm(
1453 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1456 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1457 assert(N == 2 && "Invalid number of operands!");
1458 assert(isRegShiftedImm() &&
1459 "addRegShiftedImmOperands() on non RegShiftedImm!");
1460 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1461 // Shift of #32 is encoded as 0 where permitted
1462 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1463 Inst.addOperand(MCOperand::CreateImm(
1464 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1467 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1468 assert(N == 1 && "Invalid number of operands!");
1469 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1473 void addRegListOperands(MCInst &Inst, unsigned N) const {
1474 assert(N == 1 && "Invalid number of operands!");
1475 const SmallVectorImpl<unsigned> &RegList = getRegList();
1476 for (SmallVectorImpl<unsigned>::const_iterator
1477 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1478 Inst.addOperand(MCOperand::CreateReg(*I));
1481 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1482 addRegListOperands(Inst, N);
1485 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1486 addRegListOperands(Inst, N);
1489 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1490 assert(N == 1 && "Invalid number of operands!");
1491 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1492 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1495 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1496 assert(N == 1 && "Invalid number of operands!");
1497 // Munge the lsb/width into a bitfield mask.
1498 unsigned lsb = Bitfield.LSB;
1499 unsigned width = Bitfield.Width;
1500 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1501 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1502 (32 - (lsb + width)));
1503 Inst.addOperand(MCOperand::CreateImm(Mask));
1506 void addImmOperands(MCInst &Inst, unsigned N) const {
1507 assert(N == 1 && "Invalid number of operands!");
1508 addExpr(Inst, getImm());
1511 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1512 assert(N == 1 && "Invalid number of operands!");
1513 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1514 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1517 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1518 assert(N == 1 && "Invalid number of operands!");
1519 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1520 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1523 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1524 assert(N == 1 && "Invalid number of operands!");
1525 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1526 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1527 Inst.addOperand(MCOperand::CreateImm(Val));
1530 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1531 assert(N == 1 && "Invalid number of operands!");
1532 // FIXME: We really want to scale the value here, but the LDRD/STRD
1533 // instruction don't encode operands that way yet.
1534 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1535 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1538 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1539 assert(N == 1 && "Invalid number of operands!");
1540 // The immediate is scaled by four in the encoding and is stored
1541 // in the MCInst as such. Lop off the low two bits here.
1542 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1543 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1546 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1547 assert(N == 1 && "Invalid number of operands!");
1548 // The immediate is scaled by four in the encoding and is stored
1549 // in the MCInst as such. Lop off the low two bits here.
1550 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1551 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1554 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1555 assert(N == 1 && "Invalid number of operands!");
1556 // The immediate is scaled by four in the encoding and is stored
1557 // in the MCInst as such. Lop off the low two bits here.
1558 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1559 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1562 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1563 assert(N == 1 && "Invalid number of operands!");
1564 // The constant encodes as the immediate-1, and we store in the instruction
1565 // the bits as encoded, so subtract off one here.
1566 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1567 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1570 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1571 assert(N == 1 && "Invalid number of operands!");
1572 // The constant encodes as the immediate-1, and we store in the instruction
1573 // the bits as encoded, so subtract off one here.
1574 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1575 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1578 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1579 assert(N == 1 && "Invalid number of operands!");
1580 // The constant encodes as the immediate, except for 32, which encodes as
1582 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1583 unsigned Imm = CE->getValue();
1584 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1587 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1588 assert(N == 1 && "Invalid number of operands!");
1589 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1590 // the instruction as well.
1591 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1592 int Val = CE->getValue();
1593 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1596 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1597 assert(N == 1 && "Invalid number of operands!");
1598 // The operand is actually a t2_so_imm, but we have its bitwise
1599 // negation in the assembly source, so twiddle it here.
1600 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1601 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1604 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1605 assert(N == 1 && "Invalid number of operands!");
1606 // The operand is actually a t2_so_imm, but we have its
1607 // negation in the assembly source, so twiddle it here.
1608 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1609 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1612 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1613 assert(N == 1 && "Invalid number of operands!");
1614 // The operand is actually an imm0_4095, but we have its
1615 // negation in the assembly source, so twiddle it here.
1616 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1617 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1620 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1621 assert(N == 1 && "Invalid number of operands!");
1622 // The operand is actually a so_imm, but we have its bitwise
1623 // negation in the assembly source, so twiddle it here.
1624 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1625 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1628 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1629 assert(N == 1 && "Invalid number of operands!");
1630 // The operand is actually a so_imm, but we have its
1631 // negation in the assembly source, so twiddle it here.
1632 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1633 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1636 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1637 assert(N == 1 && "Invalid number of operands!");
1638 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1641 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1642 assert(N == 1 && "Invalid number of operands!");
1643 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1646 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1647 assert(N == 1 && "Invalid number of operands!");
1648 int32_t Imm = Memory.OffsetImm->getValue();
1649 // FIXME: Handle #-0
1650 if (Imm == INT32_MIN) Imm = 0;
1651 Inst.addOperand(MCOperand::CreateImm(Imm));
1654 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1655 assert(N == 1 && "Invalid number of operands!");
1656 assert(isImm() && "Not an immediate!");
1658 // If we have an immediate that's not a constant, treat it as a label
1659 // reference needing a fixup.
1660 if (!isa<MCConstantExpr>(getImm())) {
1661 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1665 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1666 int Val = CE->getValue();
1667 Inst.addOperand(MCOperand::CreateImm(Val));
1670 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1671 assert(N == 2 && "Invalid number of operands!");
1672 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1673 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1676 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1677 assert(N == 3 && "Invalid number of operands!");
1678 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1679 if (!Memory.OffsetRegNum) {
1680 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1681 // Special case for #-0
1682 if (Val == INT32_MIN) Val = 0;
1683 if (Val < 0) Val = -Val;
1684 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1686 // For register offset, we encode the shift type and negation flag
1688 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1689 Memory.ShiftImm, Memory.ShiftType);
1691 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1692 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1693 Inst.addOperand(MCOperand::CreateImm(Val));
1696 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1697 assert(N == 2 && "Invalid number of operands!");
1698 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1699 assert(CE && "non-constant AM2OffsetImm operand!");
1700 int32_t Val = CE->getValue();
1701 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1702 // Special case for #-0
1703 if (Val == INT32_MIN) Val = 0;
1704 if (Val < 0) Val = -Val;
1705 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1706 Inst.addOperand(MCOperand::CreateReg(0));
1707 Inst.addOperand(MCOperand::CreateImm(Val));
1710 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1711 assert(N == 3 && "Invalid number of operands!");
1712 // If we have an immediate that's not a constant, treat it as a label
1713 // reference needing a fixup. If it is a constant, it's something else
1714 // and we reject it.
1716 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1717 Inst.addOperand(MCOperand::CreateReg(0));
1718 Inst.addOperand(MCOperand::CreateImm(0));
1722 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1723 if (!Memory.OffsetRegNum) {
1724 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1725 // Special case for #-0
1726 if (Val == INT32_MIN) Val = 0;
1727 if (Val < 0) Val = -Val;
1728 Val = ARM_AM::getAM3Opc(AddSub, Val);
1730 // For register offset, we encode the shift type and negation flag
1732 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1734 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1735 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1736 Inst.addOperand(MCOperand::CreateImm(Val));
1739 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1740 assert(N == 2 && "Invalid number of operands!");
1741 if (Kind == k_PostIndexRegister) {
1743 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1744 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1745 Inst.addOperand(MCOperand::CreateImm(Val));
1750 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1751 int32_t Val = CE->getValue();
1752 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1753 // Special case for #-0
1754 if (Val == INT32_MIN) Val = 0;
1755 if (Val < 0) Val = -Val;
1756 Val = ARM_AM::getAM3Opc(AddSub, Val);
1757 Inst.addOperand(MCOperand::CreateReg(0));
1758 Inst.addOperand(MCOperand::CreateImm(Val));
1761 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1762 assert(N == 2 && "Invalid number of operands!");
1763 // If we have an immediate that's not a constant, treat it as a label
1764 // reference needing a fixup. If it is a constant, it's something else
1765 // and we reject it.
1767 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1768 Inst.addOperand(MCOperand::CreateImm(0));
1772 // The lower two bits are always zero and as such are not encoded.
1773 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1774 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1775 // Special case for #-0
1776 if (Val == INT32_MIN) Val = 0;
1777 if (Val < 0) Val = -Val;
1778 Val = ARM_AM::getAM5Opc(AddSub, Val);
1779 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1780 Inst.addOperand(MCOperand::CreateImm(Val));
1783 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1784 assert(N == 2 && "Invalid number of operands!");
1785 // If we have an immediate that's not a constant, treat it as a label
1786 // reference needing a fixup. If it is a constant, it's something else
1787 // and we reject it.
1789 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1790 Inst.addOperand(MCOperand::CreateImm(0));
1794 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1795 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1796 Inst.addOperand(MCOperand::CreateImm(Val));
1799 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1800 assert(N == 2 && "Invalid number of operands!");
1801 // The lower two bits are always zero and as such are not encoded.
1802 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1803 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1804 Inst.addOperand(MCOperand::CreateImm(Val));
1807 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1808 assert(N == 2 && "Invalid number of operands!");
1809 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1810 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1811 Inst.addOperand(MCOperand::CreateImm(Val));
1814 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1815 addMemImm8OffsetOperands(Inst, N);
1818 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1819 addMemImm8OffsetOperands(Inst, N);
1822 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1823 assert(N == 2 && "Invalid number of operands!");
1824 // If this is an immediate, it's a label reference.
1826 addExpr(Inst, getImm());
1827 Inst.addOperand(MCOperand::CreateImm(0));
1831 // Otherwise, it's a normal memory reg+offset.
1832 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1833 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1834 Inst.addOperand(MCOperand::CreateImm(Val));
1837 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1838 assert(N == 2 && "Invalid number of operands!");
1839 // If this is an immediate, it's a label reference.
1841 addExpr(Inst, getImm());
1842 Inst.addOperand(MCOperand::CreateImm(0));
1846 // Otherwise, it's a normal memory reg+offset.
1847 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1848 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1849 Inst.addOperand(MCOperand::CreateImm(Val));
1852 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1853 assert(N == 2 && "Invalid number of operands!");
1854 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1855 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1858 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
1859 assert(N == 2 && "Invalid number of operands!");
1860 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1861 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1864 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1865 assert(N == 3 && "Invalid number of operands!");
1867 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1868 Memory.ShiftImm, Memory.ShiftType);
1869 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1870 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1871 Inst.addOperand(MCOperand::CreateImm(Val));
1874 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1875 assert(N == 3 && "Invalid number of operands!");
1876 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1877 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1878 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
1881 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1882 assert(N == 2 && "Invalid number of operands!");
1883 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1884 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1887 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1888 assert(N == 2 && "Invalid number of operands!");
1889 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1890 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1891 Inst.addOperand(MCOperand::CreateImm(Val));
1894 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1895 assert(N == 2 && "Invalid number of operands!");
1896 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
1897 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1898 Inst.addOperand(MCOperand::CreateImm(Val));
1901 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1902 assert(N == 2 && "Invalid number of operands!");
1903 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
1904 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1905 Inst.addOperand(MCOperand::CreateImm(Val));
1908 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1909 assert(N == 2 && "Invalid number of operands!");
1910 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1911 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1912 Inst.addOperand(MCOperand::CreateImm(Val));
1915 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1916 assert(N == 1 && "Invalid number of operands!");
1917 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1918 assert(CE && "non-constant post-idx-imm8 operand!");
1919 int Imm = CE->getValue();
1920 bool isAdd = Imm >= 0;
1921 if (Imm == INT32_MIN) Imm = 0;
1922 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1923 Inst.addOperand(MCOperand::CreateImm(Imm));
1926 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
1927 assert(N == 1 && "Invalid number of operands!");
1928 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1929 assert(CE && "non-constant post-idx-imm8s4 operand!");
1930 int Imm = CE->getValue();
1931 bool isAdd = Imm >= 0;
1932 if (Imm == INT32_MIN) Imm = 0;
1933 // Immediate is scaled by 4.
1934 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
1935 Inst.addOperand(MCOperand::CreateImm(Imm));
1938 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1939 assert(N == 2 && "Invalid number of operands!");
1940 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1941 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1944 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1945 assert(N == 2 && "Invalid number of operands!");
1946 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1947 // The sign, shift type, and shift amount are encoded in a single operand
1948 // using the AM2 encoding helpers.
1949 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1950 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1951 PostIdxReg.ShiftTy);
1952 Inst.addOperand(MCOperand::CreateImm(Imm));
1955 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1956 assert(N == 1 && "Invalid number of operands!");
1957 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1960 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1961 assert(N == 1 && "Invalid number of operands!");
1962 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1965 void addVecListOperands(MCInst &Inst, unsigned N) const {
1966 assert(N == 1 && "Invalid number of operands!");
1967 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1970 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
1971 assert(N == 2 && "Invalid number of operands!");
1972 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1973 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
1976 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
1977 assert(N == 1 && "Invalid number of operands!");
1978 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1981 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
1982 assert(N == 1 && "Invalid number of operands!");
1983 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1986 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
1987 assert(N == 1 && "Invalid number of operands!");
1988 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1991 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
1992 assert(N == 1 && "Invalid number of operands!");
1993 // The immediate encodes the type of constant as well as the value.
1994 // Mask in that this is an i8 splat.
1995 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1996 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
1999 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2000 assert(N == 1 && "Invalid number of operands!");
2001 // The immediate encodes the type of constant as well as the value.
2002 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2003 unsigned Value = CE->getValue();
2005 Value = (Value >> 8) | 0xa00;
2008 Inst.addOperand(MCOperand::CreateImm(Value));
2011 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2012 assert(N == 1 && "Invalid number of operands!");
2013 // The immediate encodes the type of constant as well as the value.
2014 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2015 unsigned Value = CE->getValue();
2016 if (Value >= 256 && Value <= 0xff00)
2017 Value = (Value >> 8) | 0x200;
2018 else if (Value > 0xffff && Value <= 0xff0000)
2019 Value = (Value >> 16) | 0x400;
2020 else if (Value > 0xffffff)
2021 Value = (Value >> 24) | 0x600;
2022 Inst.addOperand(MCOperand::CreateImm(Value));
2025 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2026 assert(N == 1 && "Invalid number of operands!");
2027 // The immediate encodes the type of constant as well as the value.
2028 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2029 unsigned Value = CE->getValue();
2030 if (Value >= 256 && Value <= 0xffff)
2031 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2032 else if (Value > 0xffff && Value <= 0xffffff)
2033 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2034 else if (Value > 0xffffff)
2035 Value = (Value >> 24) | 0x600;
2036 Inst.addOperand(MCOperand::CreateImm(Value));
2039 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2040 assert(N == 1 && "Invalid number of operands!");
2041 // The immediate encodes the type of constant as well as the value.
2042 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2043 unsigned Value = ~CE->getValue();
2044 if (Value >= 256 && Value <= 0xffff)
2045 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2046 else if (Value > 0xffff && Value <= 0xffffff)
2047 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2048 else if (Value > 0xffffff)
2049 Value = (Value >> 24) | 0x600;
2050 Inst.addOperand(MCOperand::CreateImm(Value));
2053 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2054 assert(N == 1 && "Invalid number of operands!");
2055 // The immediate encodes the type of constant as well as the value.
2056 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2057 uint64_t Value = CE->getValue();
2059 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2060 Imm |= (Value & 1) << i;
2062 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2065 virtual void print(raw_ostream &OS) const;
2067 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2068 ARMOperand *Op = new ARMOperand(k_ITCondMask);
2069 Op->ITMask.Mask = Mask;
2075 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2076 ARMOperand *Op = new ARMOperand(k_CondCode);
2083 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2084 ARMOperand *Op = new ARMOperand(k_CoprocNum);
2085 Op->Cop.Val = CopVal;
2091 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2092 ARMOperand *Op = new ARMOperand(k_CoprocReg);
2093 Op->Cop.Val = CopVal;
2099 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2100 ARMOperand *Op = new ARMOperand(k_CoprocOption);
2107 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2108 ARMOperand *Op = new ARMOperand(k_CCOut);
2109 Op->Reg.RegNum = RegNum;
2115 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2116 ARMOperand *Op = new ARMOperand(k_Token);
2117 Op->Tok.Data = Str.data();
2118 Op->Tok.Length = Str.size();
2124 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2125 ARMOperand *Op = new ARMOperand(k_Register);
2126 Op->Reg.RegNum = RegNum;
2132 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2137 ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2138 Op->RegShiftedReg.ShiftTy = ShTy;
2139 Op->RegShiftedReg.SrcReg = SrcReg;
2140 Op->RegShiftedReg.ShiftReg = ShiftReg;
2141 Op->RegShiftedReg.ShiftImm = ShiftImm;
2147 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2151 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2152 Op->RegShiftedImm.ShiftTy = ShTy;
2153 Op->RegShiftedImm.SrcReg = SrcReg;
2154 Op->RegShiftedImm.ShiftImm = ShiftImm;
2160 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2162 ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2163 Op->ShifterImm.isASR = isASR;
2164 Op->ShifterImm.Imm = Imm;
2170 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2171 ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2172 Op->RotImm.Imm = Imm;
2178 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2180 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2181 Op->Bitfield.LSB = LSB;
2182 Op->Bitfield.Width = Width;
2189 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
2190 SMLoc StartLoc, SMLoc EndLoc) {
2191 KindTy Kind = k_RegisterList;
2193 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
2194 Kind = k_DPRRegisterList;
2195 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2196 contains(Regs.front().first))
2197 Kind = k_SPRRegisterList;
2199 ARMOperand *Op = new ARMOperand(Kind);
2200 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
2201 I = Regs.begin(), E = Regs.end(); I != E; ++I)
2202 Op->Registers.push_back(I->first);
2203 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
2204 Op->StartLoc = StartLoc;
2205 Op->EndLoc = EndLoc;
2209 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2210 bool isDoubleSpaced, SMLoc S, SMLoc E) {
2211 ARMOperand *Op = new ARMOperand(k_VectorList);
2212 Op->VectorList.RegNum = RegNum;
2213 Op->VectorList.Count = Count;
2214 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2220 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2221 bool isDoubleSpaced,
2223 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2224 Op->VectorList.RegNum = RegNum;
2225 Op->VectorList.Count = Count;
2226 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2232 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2234 bool isDoubleSpaced,
2236 ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2237 Op->VectorList.RegNum = RegNum;
2238 Op->VectorList.Count = Count;
2239 Op->VectorList.LaneIndex = Index;
2240 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2246 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2248 ARMOperand *Op = new ARMOperand(k_VectorIndex);
2249 Op->VectorIndex.Val = Idx;
2255 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2256 ARMOperand *Op = new ARMOperand(k_Immediate);
2263 static ARMOperand *CreateMem(unsigned BaseRegNum,
2264 const MCConstantExpr *OffsetImm,
2265 unsigned OffsetRegNum,
2266 ARM_AM::ShiftOpc ShiftType,
2271 ARMOperand *Op = new ARMOperand(k_Memory);
2272 Op->Memory.BaseRegNum = BaseRegNum;
2273 Op->Memory.OffsetImm = OffsetImm;
2274 Op->Memory.OffsetRegNum = OffsetRegNum;
2275 Op->Memory.ShiftType = ShiftType;
2276 Op->Memory.ShiftImm = ShiftImm;
2277 Op->Memory.Alignment = Alignment;
2278 Op->Memory.isNegative = isNegative;
2284 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2285 ARM_AM::ShiftOpc ShiftTy,
2288 ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2289 Op->PostIdxReg.RegNum = RegNum;
2290 Op->PostIdxReg.isAdd = isAdd;
2291 Op->PostIdxReg.ShiftTy = ShiftTy;
2292 Op->PostIdxReg.ShiftImm = ShiftImm;
2298 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2299 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2300 Op->MBOpt.Val = Opt;
2306 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2307 ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2308 Op->IFlags.Val = IFlags;
2314 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2315 ARMOperand *Op = new ARMOperand(k_MSRMask);
2316 Op->MMask.Val = MMask;
2323 } // end anonymous namespace.
2325 void ARMOperand::print(raw_ostream &OS) const {
2328 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2331 OS << "<ccout " << getReg() << ">";
2333 case k_ITCondMask: {
2334 static const char *const MaskStr[] = {
2335 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2336 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2338 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2339 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2343 OS << "<coprocessor number: " << getCoproc() << ">";
2346 OS << "<coprocessor register: " << getCoproc() << ">";
2348 case k_CoprocOption:
2349 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2352 OS << "<mask: " << getMSRMask() << ">";
2355 getImm()->print(OS);
2357 case k_MemBarrierOpt:
2358 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
2362 << " base:" << Memory.BaseRegNum;
2365 case k_PostIndexRegister:
2366 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2367 << PostIdxReg.RegNum;
2368 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2369 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2370 << PostIdxReg.ShiftImm;
2373 case k_ProcIFlags: {
2374 OS << "<ARM_PROC::";
2375 unsigned IFlags = getProcIFlags();
2376 for (int i=2; i >= 0; --i)
2377 if (IFlags & (1 << i))
2378 OS << ARM_PROC::IFlagsToString(1 << i);
2383 OS << "<register " << getReg() << ">";
2385 case k_ShifterImmediate:
2386 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2387 << " #" << ShifterImm.Imm << ">";
2389 case k_ShiftedRegister:
2390 OS << "<so_reg_reg "
2391 << RegShiftedReg.SrcReg << " "
2392 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2393 << " " << RegShiftedReg.ShiftReg << ">";
2395 case k_ShiftedImmediate:
2396 OS << "<so_reg_imm "
2397 << RegShiftedImm.SrcReg << " "
2398 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2399 << " #" << RegShiftedImm.ShiftImm << ">";
2401 case k_RotateImmediate:
2402 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2404 case k_BitfieldDescriptor:
2405 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2406 << ", width: " << Bitfield.Width << ">";
2408 case k_RegisterList:
2409 case k_DPRRegisterList:
2410 case k_SPRRegisterList: {
2411 OS << "<register_list ";
2413 const SmallVectorImpl<unsigned> &RegList = getRegList();
2414 for (SmallVectorImpl<unsigned>::const_iterator
2415 I = RegList.begin(), E = RegList.end(); I != E; ) {
2417 if (++I < E) OS << ", ";
2424 OS << "<vector_list " << VectorList.Count << " * "
2425 << VectorList.RegNum << ">";
2427 case k_VectorListAllLanes:
2428 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2429 << VectorList.RegNum << ">";
2431 case k_VectorListIndexed:
2432 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2433 << VectorList.Count << " * " << VectorList.RegNum << ">";
2436 OS << "'" << getToken() << "'";
2439 OS << "<vectorindex " << getVectorIndex() << ">";
2444 /// @name Auto-generated Match Functions
2447 static unsigned MatchRegisterName(StringRef Name);
2451 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2452 SMLoc &StartLoc, SMLoc &EndLoc) {
2453 StartLoc = Parser.getTok().getLoc();
2454 RegNo = tryParseRegister();
2455 EndLoc = Parser.getTok().getLoc();
2457 return (RegNo == (unsigned)-1);
2460 /// Try to parse a register name. The token must be an Identifier when called,
2461 /// and if it is a register name the token is eaten and the register number is
2462 /// returned. Otherwise return -1.
2464 int ARMAsmParser::tryParseRegister() {
2465 const AsmToken &Tok = Parser.getTok();
2466 if (Tok.isNot(AsmToken::Identifier)) return -1;
2468 std::string lowerCase = Tok.getString().lower();
2469 unsigned RegNum = MatchRegisterName(lowerCase);
2471 RegNum = StringSwitch<unsigned>(lowerCase)
2472 .Case("r13", ARM::SP)
2473 .Case("r14", ARM::LR)
2474 .Case("r15", ARM::PC)
2475 .Case("ip", ARM::R12)
2476 // Additional register name aliases for 'gas' compatibility.
2477 .Case("a1", ARM::R0)
2478 .Case("a2", ARM::R1)
2479 .Case("a3", ARM::R2)
2480 .Case("a4", ARM::R3)
2481 .Case("v1", ARM::R4)
2482 .Case("v2", ARM::R5)
2483 .Case("v3", ARM::R6)
2484 .Case("v4", ARM::R7)
2485 .Case("v5", ARM::R8)
2486 .Case("v6", ARM::R9)
2487 .Case("v7", ARM::R10)
2488 .Case("v8", ARM::R11)
2489 .Case("sb", ARM::R9)
2490 .Case("sl", ARM::R10)
2491 .Case("fp", ARM::R11)
2495 // Check for aliases registered via .req. Canonicalize to lower case.
2496 // That's more consistent since register names are case insensitive, and
2497 // it's how the original entry was passed in from MC/MCParser/AsmParser.
2498 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2499 // If no match, return failure.
2500 if (Entry == RegisterReqs.end())
2502 Parser.Lex(); // Eat identifier token.
2503 return Entry->getValue();
2506 Parser.Lex(); // Eat identifier token.
2511 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
2512 // If a recoverable error occurs, return 1. If an irrecoverable error
2513 // occurs, return -1. An irrecoverable error is one where tokens have been
2514 // consumed in the process of trying to parse the shifter (i.e., when it is
2515 // indeed a shifter operand, but malformed).
2516 int ARMAsmParser::tryParseShiftRegister(
2517 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2518 SMLoc S = Parser.getTok().getLoc();
2519 const AsmToken &Tok = Parser.getTok();
2520 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2522 std::string lowerCase = Tok.getString().lower();
2523 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2524 .Case("asl", ARM_AM::lsl)
2525 .Case("lsl", ARM_AM::lsl)
2526 .Case("lsr", ARM_AM::lsr)
2527 .Case("asr", ARM_AM::asr)
2528 .Case("ror", ARM_AM::ror)
2529 .Case("rrx", ARM_AM::rrx)
2530 .Default(ARM_AM::no_shift);
2532 if (ShiftTy == ARM_AM::no_shift)
2535 Parser.Lex(); // Eat the operator.
2537 // The source register for the shift has already been added to the
2538 // operand list, so we need to pop it off and combine it into the shifted
2539 // register operand instead.
2540 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2541 if (!PrevOp->isReg())
2542 return Error(PrevOp->getStartLoc(), "shift must be of a register");
2543 int SrcReg = PrevOp->getReg();
2546 if (ShiftTy == ARM_AM::rrx) {
2547 // RRX Doesn't have an explicit shift amount. The encoder expects
2548 // the shift register to be the same as the source register. Seems odd,
2552 // Figure out if this is shifted by a constant or a register (for non-RRX).
2553 if (Parser.getTok().is(AsmToken::Hash) ||
2554 Parser.getTok().is(AsmToken::Dollar)) {
2555 Parser.Lex(); // Eat hash.
2556 SMLoc ImmLoc = Parser.getTok().getLoc();
2557 const MCExpr *ShiftExpr = 0;
2558 if (getParser().ParseExpression(ShiftExpr)) {
2559 Error(ImmLoc, "invalid immediate shift value");
2562 // The expression must be evaluatable as an immediate.
2563 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2565 Error(ImmLoc, "invalid immediate shift value");
2568 // Range check the immediate.
2569 // lsl, ror: 0 <= imm <= 31
2570 // lsr, asr: 0 <= imm <= 32
2571 Imm = CE->getValue();
2573 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2574 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2575 Error(ImmLoc, "immediate shift value out of range");
2578 // shift by zero is a nop. Always send it through as lsl.
2579 // ('as' compatibility)
2581 ShiftTy = ARM_AM::lsl;
2582 } else if (Parser.getTok().is(AsmToken::Identifier)) {
2583 ShiftReg = tryParseRegister();
2584 SMLoc L = Parser.getTok().getLoc();
2585 if (ShiftReg == -1) {
2586 Error (L, "expected immediate or register in shift operand");
2590 Error (Parser.getTok().getLoc(),
2591 "expected immediate or register in shift operand");
2596 if (ShiftReg && ShiftTy != ARM_AM::rrx)
2597 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2599 S, Parser.getTok().getLoc()));
2601 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2602 S, Parser.getTok().getLoc()));
2608 /// Try to parse a register name. The token must be an Identifier when called.
2609 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
2610 /// if there is a "writeback". 'true' if it's not a register.
2612 /// TODO this is likely to change to allow different register types and or to
2613 /// parse for a specific register type.
2615 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2616 SMLoc S = Parser.getTok().getLoc();
2617 int RegNo = tryParseRegister();
2621 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
2623 const AsmToken &ExclaimTok = Parser.getTok();
2624 if (ExclaimTok.is(AsmToken::Exclaim)) {
2625 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2626 ExclaimTok.getLoc()));
2627 Parser.Lex(); // Eat exclaim token
2631 // Also check for an index operand. This is only legal for vector registers,
2632 // but that'll get caught OK in operand matching, so we don't need to
2633 // explicitly filter everything else out here.
2634 if (Parser.getTok().is(AsmToken::LBrac)) {
2635 SMLoc SIdx = Parser.getTok().getLoc();
2636 Parser.Lex(); // Eat left bracket token.
2638 const MCExpr *ImmVal;
2639 if (getParser().ParseExpression(ImmVal))
2641 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2643 return TokError("immediate value expected for vector index");
2645 SMLoc E = Parser.getTok().getLoc();
2646 if (Parser.getTok().isNot(AsmToken::RBrac))
2647 return Error(E, "']' expected");
2649 Parser.Lex(); // Eat right bracket token.
2651 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2659 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
2660 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2662 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2663 // Use the same layout as the tablegen'erated register name matcher. Ugly,
2665 switch (Name.size()) {
2668 if (Name[0] != CoprocOp)
2684 if (Name[0] != CoprocOp || Name[1] != '1')
2688 case '0': return 10;
2689 case '1': return 11;
2690 case '2': return 12;
2691 case '3': return 13;
2692 case '4': return 14;
2693 case '5': return 15;
2698 /// parseITCondCode - Try to parse a condition code for an IT instruction.
2699 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2700 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2701 SMLoc S = Parser.getTok().getLoc();
2702 const AsmToken &Tok = Parser.getTok();
2703 if (!Tok.is(AsmToken::Identifier))
2704 return MatchOperand_NoMatch;
2705 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
2706 .Case("eq", ARMCC::EQ)
2707 .Case("ne", ARMCC::NE)
2708 .Case("hs", ARMCC::HS)
2709 .Case("cs", ARMCC::HS)
2710 .Case("lo", ARMCC::LO)
2711 .Case("cc", ARMCC::LO)
2712 .Case("mi", ARMCC::MI)
2713 .Case("pl", ARMCC::PL)
2714 .Case("vs", ARMCC::VS)
2715 .Case("vc", ARMCC::VC)
2716 .Case("hi", ARMCC::HI)
2717 .Case("ls", ARMCC::LS)
2718 .Case("ge", ARMCC::GE)
2719 .Case("lt", ARMCC::LT)
2720 .Case("gt", ARMCC::GT)
2721 .Case("le", ARMCC::LE)
2722 .Case("al", ARMCC::AL)
2725 return MatchOperand_NoMatch;
2726 Parser.Lex(); // Eat the token.
2728 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2730 return MatchOperand_Success;
2733 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2734 /// token must be an Identifier when called, and if it is a coprocessor
2735 /// number, the token is eaten and the operand is added to the operand list.
2736 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2737 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2738 SMLoc S = Parser.getTok().getLoc();
2739 const AsmToken &Tok = Parser.getTok();
2740 if (Tok.isNot(AsmToken::Identifier))
2741 return MatchOperand_NoMatch;
2743 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2745 return MatchOperand_NoMatch;
2747 Parser.Lex(); // Eat identifier token.
2748 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2749 return MatchOperand_Success;
2752 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2753 /// token must be an Identifier when called, and if it is a coprocessor
2754 /// number, the token is eaten and the operand is added to the operand list.
2755 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2756 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2757 SMLoc S = Parser.getTok().getLoc();
2758 const AsmToken &Tok = Parser.getTok();
2759 if (Tok.isNot(AsmToken::Identifier))
2760 return MatchOperand_NoMatch;
2762 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2764 return MatchOperand_NoMatch;
2766 Parser.Lex(); // Eat identifier token.
2767 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2768 return MatchOperand_Success;
2771 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2772 /// coproc_option : '{' imm0_255 '}'
2773 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2774 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2775 SMLoc S = Parser.getTok().getLoc();
2777 // If this isn't a '{', this isn't a coprocessor immediate operand.
2778 if (Parser.getTok().isNot(AsmToken::LCurly))
2779 return MatchOperand_NoMatch;
2780 Parser.Lex(); // Eat the '{'
2783 SMLoc Loc = Parser.getTok().getLoc();
2784 if (getParser().ParseExpression(Expr)) {
2785 Error(Loc, "illegal expression");
2786 return MatchOperand_ParseFail;
2788 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2789 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2790 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2791 return MatchOperand_ParseFail;
2793 int Val = CE->getValue();
2795 // Check for and consume the closing '}'
2796 if (Parser.getTok().isNot(AsmToken::RCurly))
2797 return MatchOperand_ParseFail;
2798 SMLoc E = Parser.getTok().getLoc();
2799 Parser.Lex(); // Eat the '}'
2801 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2802 return MatchOperand_Success;
2805 // For register list parsing, we need to map from raw GPR register numbering
2806 // to the enumeration values. The enumeration values aren't sorted by
2807 // register number due to our using "sp", "lr" and "pc" as canonical names.
2808 static unsigned getNextRegister(unsigned Reg) {
2809 // If this is a GPR, we need to do it manually, otherwise we can rely
2810 // on the sort ordering of the enumeration since the other reg-classes
2812 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2815 default: llvm_unreachable("Invalid GPR number!");
2816 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
2817 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
2818 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
2819 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
2820 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
2821 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2822 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
2823 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
2827 // Return the low-subreg of a given Q register.
2828 static unsigned getDRegFromQReg(unsigned QReg) {
2830 default: llvm_unreachable("expected a Q register!");
2831 case ARM::Q0: return ARM::D0;
2832 case ARM::Q1: return ARM::D2;
2833 case ARM::Q2: return ARM::D4;
2834 case ARM::Q3: return ARM::D6;
2835 case ARM::Q4: return ARM::D8;
2836 case ARM::Q5: return ARM::D10;
2837 case ARM::Q6: return ARM::D12;
2838 case ARM::Q7: return ARM::D14;
2839 case ARM::Q8: return ARM::D16;
2840 case ARM::Q9: return ARM::D18;
2841 case ARM::Q10: return ARM::D20;
2842 case ARM::Q11: return ARM::D22;
2843 case ARM::Q12: return ARM::D24;
2844 case ARM::Q13: return ARM::D26;
2845 case ARM::Q14: return ARM::D28;
2846 case ARM::Q15: return ARM::D30;
2850 /// Parse a register list.
2852 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2853 assert(Parser.getTok().is(AsmToken::LCurly) &&
2854 "Token is not a Left Curly Brace");
2855 SMLoc S = Parser.getTok().getLoc();
2856 Parser.Lex(); // Eat '{' token.
2857 SMLoc RegLoc = Parser.getTok().getLoc();
2859 // Check the first register in the list to see what register class
2860 // this is a list of.
2861 int Reg = tryParseRegister();
2863 return Error(RegLoc, "register expected");
2865 // The reglist instructions have at most 16 registers, so reserve
2866 // space for that many.
2867 SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
2869 // Allow Q regs and just interpret them as the two D sub-registers.
2870 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2871 Reg = getDRegFromQReg(Reg);
2872 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2875 const MCRegisterClass *RC;
2876 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2877 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
2878 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
2879 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
2880 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
2881 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
2883 return Error(RegLoc, "invalid register in register list");
2885 // Store the register.
2886 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2888 // This starts immediately after the first register token in the list,
2889 // so we can see either a comma or a minus (range separator) as a legal
2891 while (Parser.getTok().is(AsmToken::Comma) ||
2892 Parser.getTok().is(AsmToken::Minus)) {
2893 if (Parser.getTok().is(AsmToken::Minus)) {
2894 Parser.Lex(); // Eat the minus.
2895 SMLoc EndLoc = Parser.getTok().getLoc();
2896 int EndReg = tryParseRegister();
2898 return Error(EndLoc, "register expected");
2899 // Allow Q regs and just interpret them as the two D sub-registers.
2900 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
2901 EndReg = getDRegFromQReg(EndReg) + 1;
2902 // If the register is the same as the start reg, there's nothing
2906 // The register must be in the same register class as the first.
2907 if (!RC->contains(EndReg))
2908 return Error(EndLoc, "invalid register in register list");
2909 // Ranges must go from low to high.
2910 if (getARMRegisterNumbering(Reg) > getARMRegisterNumbering(EndReg))
2911 return Error(EndLoc, "bad range in register list");
2913 // Add all the registers in the range to the register list.
2914 while (Reg != EndReg) {
2915 Reg = getNextRegister(Reg);
2916 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2920 Parser.Lex(); // Eat the comma.
2921 RegLoc = Parser.getTok().getLoc();
2923 const AsmToken RegTok = Parser.getTok();
2924 Reg = tryParseRegister();
2926 return Error(RegLoc, "register expected");
2927 // Allow Q regs and just interpret them as the two D sub-registers.
2928 bool isQReg = false;
2929 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2930 Reg = getDRegFromQReg(Reg);
2933 // The register must be in the same register class as the first.
2934 if (!RC->contains(Reg))
2935 return Error(RegLoc, "invalid register in register list");
2936 // List must be monotonically increasing.
2937 if (getARMRegisterNumbering(Reg) < getARMRegisterNumbering(OldReg)) {
2938 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2939 Warning(RegLoc, "register list not in ascending order");
2941 return Error(RegLoc, "register list not in ascending order");
2943 if (getARMRegisterNumbering(Reg) == getARMRegisterNumbering(OldReg)) {
2944 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
2945 ") in register list");
2948 // VFP register lists must also be contiguous.
2949 // It's OK to use the enumeration values directly here rather, as the
2950 // VFP register classes have the enum sorted properly.
2951 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
2953 return Error(RegLoc, "non-contiguous register range");
2954 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2956 Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc));
2959 SMLoc E = Parser.getTok().getLoc();
2960 if (Parser.getTok().isNot(AsmToken::RCurly))
2961 return Error(E, "'}' expected");
2962 Parser.Lex(); // Eat '}' token.
2964 // Push the register list operand.
2965 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
2967 // The ARM system instruction variants for LDM/STM have a '^' token here.
2968 if (Parser.getTok().is(AsmToken::Caret)) {
2969 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
2970 Parser.Lex(); // Eat '^' token.
2976 // Helper function to parse the lane index for vector lists.
2977 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2978 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index) {
2979 Index = 0; // Always return a defined index value.
2980 if (Parser.getTok().is(AsmToken::LBrac)) {
2981 Parser.Lex(); // Eat the '['.
2982 if (Parser.getTok().is(AsmToken::RBrac)) {
2983 // "Dn[]" is the 'all lanes' syntax.
2984 LaneKind = AllLanes;
2985 Parser.Lex(); // Eat the ']'.
2986 return MatchOperand_Success;
2989 // There's an optional '#' token here. Normally there wouldn't be, but
2990 // inline assemble puts one in, and it's friendly to accept that.
2991 if (Parser.getTok().is(AsmToken::Hash))
2992 Parser.Lex(); // Eat the '#'
2994 const MCExpr *LaneIndex;
2995 SMLoc Loc = Parser.getTok().getLoc();
2996 if (getParser().ParseExpression(LaneIndex)) {
2997 Error(Loc, "illegal expression");
2998 return MatchOperand_ParseFail;
3000 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3002 Error(Loc, "lane index must be empty or an integer");
3003 return MatchOperand_ParseFail;
3005 if (Parser.getTok().isNot(AsmToken::RBrac)) {
3006 Error(Parser.getTok().getLoc(), "']' expected");
3007 return MatchOperand_ParseFail;
3009 Parser.Lex(); // Eat the ']'.
3010 int64_t Val = CE->getValue();
3012 // FIXME: Make this range check context sensitive for .8, .16, .32.
3013 if (Val < 0 || Val > 7) {
3014 Error(Parser.getTok().getLoc(), "lane index out of range");
3015 return MatchOperand_ParseFail;
3018 LaneKind = IndexedLane;
3019 return MatchOperand_Success;
3022 return MatchOperand_Success;
3025 // parse a vector register list
3026 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3027 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3028 VectorLaneTy LaneKind;
3030 SMLoc S = Parser.getTok().getLoc();
3031 // As an extension (to match gas), support a plain D register or Q register
3032 // (without encosing curly braces) as a single or double entry list,
3034 if (Parser.getTok().is(AsmToken::Identifier)) {
3035 int Reg = tryParseRegister();
3037 return MatchOperand_NoMatch;
3038 SMLoc E = Parser.getTok().getLoc();
3039 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3040 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex);
3041 if (Res != MatchOperand_Success)
3045 E = Parser.getTok().getLoc();
3046 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3049 E = Parser.getTok().getLoc();
3050 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3054 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3059 return MatchOperand_Success;
3061 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3062 Reg = getDRegFromQReg(Reg);
3063 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex);
3064 if (Res != MatchOperand_Success)
3068 E = Parser.getTok().getLoc();
3069 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3070 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3071 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3074 E = Parser.getTok().getLoc();
3075 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3076 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3077 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3081 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3086 return MatchOperand_Success;
3088 Error(S, "vector register expected");
3089 return MatchOperand_ParseFail;
3092 if (Parser.getTok().isNot(AsmToken::LCurly))
3093 return MatchOperand_NoMatch;
3095 Parser.Lex(); // Eat '{' token.
3096 SMLoc RegLoc = Parser.getTok().getLoc();
3098 int Reg = tryParseRegister();
3100 Error(RegLoc, "register expected");
3101 return MatchOperand_ParseFail;
3105 unsigned FirstReg = Reg;
3106 // The list is of D registers, but we also allow Q regs and just interpret
3107 // them as the two D sub-registers.
3108 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3109 FirstReg = Reg = getDRegFromQReg(Reg);
3110 Spacing = 1; // double-spacing requires explicit D registers, otherwise
3111 // it's ambiguous with four-register single spaced.
3115 if (parseVectorLane(LaneKind, LaneIndex) != MatchOperand_Success)
3116 return MatchOperand_ParseFail;
3118 while (Parser.getTok().is(AsmToken::Comma) ||
3119 Parser.getTok().is(AsmToken::Minus)) {
3120 if (Parser.getTok().is(AsmToken::Minus)) {
3122 Spacing = 1; // Register range implies a single spaced list.
3123 else if (Spacing == 2) {
3124 Error(Parser.getTok().getLoc(),
3125 "sequential registers in double spaced list");
3126 return MatchOperand_ParseFail;
3128 Parser.Lex(); // Eat the minus.
3129 SMLoc EndLoc = Parser.getTok().getLoc();
3130 int EndReg = tryParseRegister();
3132 Error(EndLoc, "register expected");
3133 return MatchOperand_ParseFail;
3135 // Allow Q regs and just interpret them as the two D sub-registers.
3136 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3137 EndReg = getDRegFromQReg(EndReg) + 1;
3138 // If the register is the same as the start reg, there's nothing
3142 // The register must be in the same register class as the first.
3143 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3144 Error(EndLoc, "invalid register in register list");
3145 return MatchOperand_ParseFail;
3147 // Ranges must go from low to high.
3149 Error(EndLoc, "bad range in register list");
3150 return MatchOperand_ParseFail;
3152 // Parse the lane specifier if present.
3153 VectorLaneTy NextLaneKind;
3154 unsigned NextLaneIndex;
3155 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
3156 return MatchOperand_ParseFail;
3157 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3158 Error(EndLoc, "mismatched lane index in register list");
3159 return MatchOperand_ParseFail;
3161 EndLoc = Parser.getTok().getLoc();
3163 // Add all the registers in the range to the register list.
3164 Count += EndReg - Reg;
3168 Parser.Lex(); // Eat the comma.
3169 RegLoc = Parser.getTok().getLoc();
3171 Reg = tryParseRegister();
3173 Error(RegLoc, "register expected");
3174 return MatchOperand_ParseFail;
3176 // vector register lists must be contiguous.
3177 // It's OK to use the enumeration values directly here rather, as the
3178 // VFP register classes have the enum sorted properly.
3180 // The list is of D registers, but we also allow Q regs and just interpret
3181 // them as the two D sub-registers.
3182 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3184 Spacing = 1; // Register range implies a single spaced list.
3185 else if (Spacing == 2) {
3187 "invalid register in double-spaced list (must be 'D' register')");
3188 return MatchOperand_ParseFail;
3190 Reg = getDRegFromQReg(Reg);
3191 if (Reg != OldReg + 1) {
3192 Error(RegLoc, "non-contiguous register range");
3193 return MatchOperand_ParseFail;
3197 // Parse the lane specifier if present.
3198 VectorLaneTy NextLaneKind;
3199 unsigned NextLaneIndex;
3200 SMLoc EndLoc = Parser.getTok().getLoc();
3201 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
3202 return MatchOperand_ParseFail;
3203 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3204 Error(EndLoc, "mismatched lane index in register list");
3205 return MatchOperand_ParseFail;
3209 // Normal D register.
3210 // Figure out the register spacing (single or double) of the list if
3211 // we don't know it already.
3213 Spacing = 1 + (Reg == OldReg + 2);
3215 // Just check that it's contiguous and keep going.
3216 if (Reg != OldReg + Spacing) {
3217 Error(RegLoc, "non-contiguous register range");
3218 return MatchOperand_ParseFail;
3221 // Parse the lane specifier if present.
3222 VectorLaneTy NextLaneKind;
3223 unsigned NextLaneIndex;
3224 SMLoc EndLoc = Parser.getTok().getLoc();
3225 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
3226 return MatchOperand_ParseFail;
3227 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3228 Error(EndLoc, "mismatched lane index in register list");
3229 return MatchOperand_ParseFail;
3233 SMLoc E = Parser.getTok().getLoc();
3234 if (Parser.getTok().isNot(AsmToken::RCurly)) {
3235 Error(E, "'}' expected");
3236 return MatchOperand_ParseFail;
3238 Parser.Lex(); // Eat '}' token.
3242 // Two-register operands have been converted to the
3243 // composite register classes.
3245 const MCRegisterClass *RC = (Spacing == 1) ?
3246 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3247 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3248 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3251 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3252 (Spacing == 2), S, E));
3255 // Two-register operands have been converted to the
3256 // composite register classes.
3258 const MCRegisterClass *RC = (Spacing == 1) ?
3259 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3260 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3261 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3263 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3268 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3274 return MatchOperand_Success;
3277 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3278 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3279 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3280 SMLoc S = Parser.getTok().getLoc();
3281 const AsmToken &Tok = Parser.getTok();
3284 if (Tok.is(AsmToken::Identifier)) {
3285 StringRef OptStr = Tok.getString();
3287 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3288 .Case("sy", ARM_MB::SY)
3289 .Case("st", ARM_MB::ST)
3290 .Case("sh", ARM_MB::ISH)
3291 .Case("ish", ARM_MB::ISH)
3292 .Case("shst", ARM_MB::ISHST)
3293 .Case("ishst", ARM_MB::ISHST)
3294 .Case("nsh", ARM_MB::NSH)
3295 .Case("un", ARM_MB::NSH)
3296 .Case("nshst", ARM_MB::NSHST)
3297 .Case("unst", ARM_MB::NSHST)
3298 .Case("osh", ARM_MB::OSH)
3299 .Case("oshst", ARM_MB::OSHST)
3303 return MatchOperand_NoMatch;
3305 Parser.Lex(); // Eat identifier token.
3306 } else if (Tok.is(AsmToken::Hash) ||
3307 Tok.is(AsmToken::Dollar) ||
3308 Tok.is(AsmToken::Integer)) {
3309 if (Parser.getTok().isNot(AsmToken::Integer))
3310 Parser.Lex(); // Eat the '#'.
3311 SMLoc Loc = Parser.getTok().getLoc();
3313 const MCExpr *MemBarrierID;
3314 if (getParser().ParseExpression(MemBarrierID)) {
3315 Error(Loc, "illegal expression");
3316 return MatchOperand_ParseFail;
3319 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3321 Error(Loc, "constant expression expected");
3322 return MatchOperand_ParseFail;
3325 int Val = CE->getValue();
3327 Error(Loc, "immediate value out of range");
3328 return MatchOperand_ParseFail;
3331 Opt = ARM_MB::RESERVED_0 + Val;
3333 return MatchOperand_ParseFail;
3335 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3336 return MatchOperand_Success;
3339 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3340 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3341 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3342 SMLoc S = Parser.getTok().getLoc();
3343 const AsmToken &Tok = Parser.getTok();
3344 if (!Tok.is(AsmToken::Identifier))
3345 return MatchOperand_NoMatch;
3346 StringRef IFlagsStr = Tok.getString();
3348 // An iflags string of "none" is interpreted to mean that none of the AIF
3349 // bits are set. Not a terribly useful instruction, but a valid encoding.
3350 unsigned IFlags = 0;
3351 if (IFlagsStr != "none") {
3352 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3353 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3354 .Case("a", ARM_PROC::A)
3355 .Case("i", ARM_PROC::I)
3356 .Case("f", ARM_PROC::F)
3359 // If some specific iflag is already set, it means that some letter is
3360 // present more than once, this is not acceptable.
3361 if (Flag == ~0U || (IFlags & Flag))
3362 return MatchOperand_NoMatch;
3368 Parser.Lex(); // Eat identifier token.
3369 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3370 return MatchOperand_Success;
3373 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3374 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3375 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3376 SMLoc S = Parser.getTok().getLoc();
3377 const AsmToken &Tok = Parser.getTok();
3378 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
3379 StringRef Mask = Tok.getString();
3382 // See ARMv6-M 10.1.1
3383 std::string Name = Mask.lower();
3384 unsigned FlagsVal = StringSwitch<unsigned>(Name)
3385 // Note: in the documentation:
3386 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3387 // for MSR APSR_nzcvq.
3388 // but we do make it an alias here. This is so to get the "mask encoding"
3389 // bits correct on MSR APSR writes.
3391 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3392 // should really only be allowed when writing a special register. Note
3393 // they get dropped in the MRS instruction reading a special register as
3394 // the SYSm field is only 8 bits.
3396 // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3397 // includes the DSP extension but that is not checked.
3398 .Case("apsr", 0x800)
3399 .Case("apsr_nzcvq", 0x800)
3400 .Case("apsr_g", 0x400)
3401 .Case("apsr_nzcvqg", 0xc00)
3402 .Case("iapsr", 0x801)
3403 .Case("iapsr_nzcvq", 0x801)
3404 .Case("iapsr_g", 0x401)
3405 .Case("iapsr_nzcvqg", 0xc01)
3406 .Case("eapsr", 0x802)
3407 .Case("eapsr_nzcvq", 0x802)
3408 .Case("eapsr_g", 0x402)
3409 .Case("eapsr_nzcvqg", 0xc02)
3410 .Case("xpsr", 0x803)
3411 .Case("xpsr_nzcvq", 0x803)
3412 .Case("xpsr_g", 0x403)
3413 .Case("xpsr_nzcvqg", 0xc03)
3414 .Case("ipsr", 0x805)
3415 .Case("epsr", 0x806)
3416 .Case("iepsr", 0x807)
3419 .Case("primask", 0x810)
3420 .Case("basepri", 0x811)
3421 .Case("basepri_max", 0x812)
3422 .Case("faultmask", 0x813)
3423 .Case("control", 0x814)
3426 if (FlagsVal == ~0U)
3427 return MatchOperand_NoMatch;
3429 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3430 // basepri, basepri_max and faultmask only valid for V7m.
3431 return MatchOperand_NoMatch;
3433 Parser.Lex(); // Eat identifier token.
3434 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3435 return MatchOperand_Success;
3438 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3439 size_t Start = 0, Next = Mask.find('_');
3440 StringRef Flags = "";
3441 std::string SpecReg = Mask.slice(Start, Next).lower();
3442 if (Next != StringRef::npos)
3443 Flags = Mask.slice(Next+1, Mask.size());
3445 // FlagsVal contains the complete mask:
3447 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3448 unsigned FlagsVal = 0;
3450 if (SpecReg == "apsr") {
3451 FlagsVal = StringSwitch<unsigned>(Flags)
3452 .Case("nzcvq", 0x8) // same as CPSR_f
3453 .Case("g", 0x4) // same as CPSR_s
3454 .Case("nzcvqg", 0xc) // same as CPSR_fs
3457 if (FlagsVal == ~0U) {
3459 return MatchOperand_NoMatch;
3461 FlagsVal = 8; // No flag
3463 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3464 // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3465 if (Flags == "all" || Flags == "")
3467 for (int i = 0, e = Flags.size(); i != e; ++i) {
3468 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3475 // If some specific flag is already set, it means that some letter is
3476 // present more than once, this is not acceptable.
3477 if (FlagsVal == ~0U || (FlagsVal & Flag))
3478 return MatchOperand_NoMatch;
3481 } else // No match for special register.
3482 return MatchOperand_NoMatch;
3484 // Special register without flags is NOT equivalent to "fc" flags.
3485 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
3486 // two lines would enable gas compatibility at the expense of breaking
3492 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3493 if (SpecReg == "spsr")
3496 Parser.Lex(); // Eat identifier token.
3497 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3498 return MatchOperand_Success;
3501 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3502 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3503 int Low, int High) {
3504 const AsmToken &Tok = Parser.getTok();
3505 if (Tok.isNot(AsmToken::Identifier)) {
3506 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3507 return MatchOperand_ParseFail;
3509 StringRef ShiftName = Tok.getString();
3510 std::string LowerOp = Op.lower();
3511 std::string UpperOp = Op.upper();
3512 if (ShiftName != LowerOp && ShiftName != UpperOp) {
3513 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3514 return MatchOperand_ParseFail;
3516 Parser.Lex(); // Eat shift type token.
3518 // There must be a '#' and a shift amount.
3519 if (Parser.getTok().isNot(AsmToken::Hash) &&
3520 Parser.getTok().isNot(AsmToken::Dollar)) {
3521 Error(Parser.getTok().getLoc(), "'#' expected");
3522 return MatchOperand_ParseFail;
3524 Parser.Lex(); // Eat hash token.
3526 const MCExpr *ShiftAmount;
3527 SMLoc Loc = Parser.getTok().getLoc();
3528 if (getParser().ParseExpression(ShiftAmount)) {
3529 Error(Loc, "illegal expression");
3530 return MatchOperand_ParseFail;
3532 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3534 Error(Loc, "constant expression expected");
3535 return MatchOperand_ParseFail;
3537 int Val = CE->getValue();
3538 if (Val < Low || Val > High) {
3539 Error(Loc, "immediate value out of range");
3540 return MatchOperand_ParseFail;
3543 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
3545 return MatchOperand_Success;
3548 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3549 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3550 const AsmToken &Tok = Parser.getTok();
3551 SMLoc S = Tok.getLoc();
3552 if (Tok.isNot(AsmToken::Identifier)) {
3553 Error(Tok.getLoc(), "'be' or 'le' operand expected");
3554 return MatchOperand_ParseFail;
3556 int Val = StringSwitch<int>(Tok.getString())
3560 Parser.Lex(); // Eat the token.
3563 Error(Tok.getLoc(), "'be' or 'le' operand expected");
3564 return MatchOperand_ParseFail;
3566 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3568 S, Parser.getTok().getLoc()));
3569 return MatchOperand_Success;
3572 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3573 /// instructions. Legal values are:
3574 /// lsl #n 'n' in [0,31]
3575 /// asr #n 'n' in [1,32]
3576 /// n == 32 encoded as n == 0.
3577 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3578 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3579 const AsmToken &Tok = Parser.getTok();
3580 SMLoc S = Tok.getLoc();
3581 if (Tok.isNot(AsmToken::Identifier)) {
3582 Error(S, "shift operator 'asr' or 'lsl' expected");
3583 return MatchOperand_ParseFail;
3585 StringRef ShiftName = Tok.getString();
3587 if (ShiftName == "lsl" || ShiftName == "LSL")
3589 else if (ShiftName == "asr" || ShiftName == "ASR")
3592 Error(S, "shift operator 'asr' or 'lsl' expected");
3593 return MatchOperand_ParseFail;
3595 Parser.Lex(); // Eat the operator.
3597 // A '#' and a shift amount.
3598 if (Parser.getTok().isNot(AsmToken::Hash) &&
3599 Parser.getTok().isNot(AsmToken::Dollar)) {
3600 Error(Parser.getTok().getLoc(), "'#' expected");
3601 return MatchOperand_ParseFail;
3603 Parser.Lex(); // Eat hash token.
3605 const MCExpr *ShiftAmount;
3606 SMLoc E = Parser.getTok().getLoc();
3607 if (getParser().ParseExpression(ShiftAmount)) {
3608 Error(E, "malformed shift expression");
3609 return MatchOperand_ParseFail;
3611 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3613 Error(E, "shift amount must be an immediate");
3614 return MatchOperand_ParseFail;
3617 int64_t Val = CE->getValue();
3619 // Shift amount must be in [1,32]
3620 if (Val < 1 || Val > 32) {
3621 Error(E, "'asr' shift amount must be in range [1,32]");
3622 return MatchOperand_ParseFail;
3624 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3625 if (isThumb() && Val == 32) {
3626 Error(E, "'asr #32' shift amount not allowed in Thumb mode");
3627 return MatchOperand_ParseFail;
3629 if (Val == 32) Val = 0;
3631 // Shift amount must be in [1,32]
3632 if (Val < 0 || Val > 31) {
3633 Error(E, "'lsr' shift amount must be in range [0,31]");
3634 return MatchOperand_ParseFail;
3638 E = Parser.getTok().getLoc();
3639 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
3641 return MatchOperand_Success;
3644 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3645 /// of instructions. Legal values are:
3646 /// ror #n 'n' in {0, 8, 16, 24}
3647 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3648 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3649 const AsmToken &Tok = Parser.getTok();
3650 SMLoc S = Tok.getLoc();
3651 if (Tok.isNot(AsmToken::Identifier))
3652 return MatchOperand_NoMatch;
3653 StringRef ShiftName = Tok.getString();
3654 if (ShiftName != "ror" && ShiftName != "ROR")
3655 return MatchOperand_NoMatch;
3656 Parser.Lex(); // Eat the operator.
3658 // A '#' and a rotate amount.
3659 if (Parser.getTok().isNot(AsmToken::Hash) &&
3660 Parser.getTok().isNot(AsmToken::Dollar)) {
3661 Error(Parser.getTok().getLoc(), "'#' expected");
3662 return MatchOperand_ParseFail;
3664 Parser.Lex(); // Eat hash token.
3666 const MCExpr *ShiftAmount;
3667 SMLoc E = Parser.getTok().getLoc();
3668 if (getParser().ParseExpression(ShiftAmount)) {
3669 Error(E, "malformed rotate expression");
3670 return MatchOperand_ParseFail;
3672 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3674 Error(E, "rotate amount must be an immediate");
3675 return MatchOperand_ParseFail;
3678 int64_t Val = CE->getValue();
3679 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
3680 // normally, zero is represented in asm by omitting the rotate operand
3682 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
3683 Error(E, "'ror' rotate amount must be 8, 16, or 24");
3684 return MatchOperand_ParseFail;
3687 E = Parser.getTok().getLoc();
3688 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
3690 return MatchOperand_Success;
3693 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3694 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3695 SMLoc S = Parser.getTok().getLoc();
3696 // The bitfield descriptor is really two operands, the LSB and the width.
3697 if (Parser.getTok().isNot(AsmToken::Hash) &&
3698 Parser.getTok().isNot(AsmToken::Dollar)) {
3699 Error(Parser.getTok().getLoc(), "'#' expected");
3700 return MatchOperand_ParseFail;
3702 Parser.Lex(); // Eat hash token.
3704 const MCExpr *LSBExpr;
3705 SMLoc E = Parser.getTok().getLoc();
3706 if (getParser().ParseExpression(LSBExpr)) {
3707 Error(E, "malformed immediate expression");
3708 return MatchOperand_ParseFail;
3710 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
3712 Error(E, "'lsb' operand must be an immediate");
3713 return MatchOperand_ParseFail;
3716 int64_t LSB = CE->getValue();
3717 // The LSB must be in the range [0,31]
3718 if (LSB < 0 || LSB > 31) {
3719 Error(E, "'lsb' operand must be in the range [0,31]");
3720 return MatchOperand_ParseFail;
3722 E = Parser.getTok().getLoc();
3724 // Expect another immediate operand.
3725 if (Parser.getTok().isNot(AsmToken::Comma)) {
3726 Error(Parser.getTok().getLoc(), "too few operands");
3727 return MatchOperand_ParseFail;
3729 Parser.Lex(); // Eat hash token.
3730 if (Parser.getTok().isNot(AsmToken::Hash) &&
3731 Parser.getTok().isNot(AsmToken::Dollar)) {
3732 Error(Parser.getTok().getLoc(), "'#' expected");
3733 return MatchOperand_ParseFail;
3735 Parser.Lex(); // Eat hash token.
3737 const MCExpr *WidthExpr;
3738 if (getParser().ParseExpression(WidthExpr)) {
3739 Error(E, "malformed immediate expression");
3740 return MatchOperand_ParseFail;
3742 CE = dyn_cast<MCConstantExpr>(WidthExpr);
3744 Error(E, "'width' operand must be an immediate");
3745 return MatchOperand_ParseFail;
3748 int64_t Width = CE->getValue();
3749 // The LSB must be in the range [1,32-lsb]
3750 if (Width < 1 || Width > 32 - LSB) {
3751 Error(E, "'width' operand must be in the range [1,32-lsb]");
3752 return MatchOperand_ParseFail;
3754 E = Parser.getTok().getLoc();
3756 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
3758 return MatchOperand_Success;
3761 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3762 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3763 // Check for a post-index addressing register operand. Specifically:
3764 // postidx_reg := '+' register {, shift}
3765 // | '-' register {, shift}
3766 // | register {, shift}
3768 // This method must return MatchOperand_NoMatch without consuming any tokens
3769 // in the case where there is no match, as other alternatives take other
3771 AsmToken Tok = Parser.getTok();
3772 SMLoc S = Tok.getLoc();
3773 bool haveEaten = false;
3776 if (Tok.is(AsmToken::Plus)) {
3777 Parser.Lex(); // Eat the '+' token.
3779 } else if (Tok.is(AsmToken::Minus)) {
3780 Parser.Lex(); // Eat the '-' token.
3784 if (Parser.getTok().is(AsmToken::Identifier))
3785 Reg = tryParseRegister();
3788 return MatchOperand_NoMatch;
3789 Error(Parser.getTok().getLoc(), "register expected");
3790 return MatchOperand_ParseFail;
3792 SMLoc E = Parser.getTok().getLoc();
3794 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
3795 unsigned ShiftImm = 0;
3796 if (Parser.getTok().is(AsmToken::Comma)) {
3797 Parser.Lex(); // Eat the ','.
3798 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
3799 return MatchOperand_ParseFail;
3802 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
3805 return MatchOperand_Success;
3808 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3809 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3810 // Check for a post-index addressing register operand. Specifically:
3811 // am3offset := '+' register
3818 // This method must return MatchOperand_NoMatch without consuming any tokens
3819 // in the case where there is no match, as other alternatives take other
3821 AsmToken Tok = Parser.getTok();
3822 SMLoc S = Tok.getLoc();
3824 // Do immediates first, as we always parse those if we have a '#'.
3825 if (Parser.getTok().is(AsmToken::Hash) ||
3826 Parser.getTok().is(AsmToken::Dollar)) {
3827 Parser.Lex(); // Eat the '#'.
3828 // Explicitly look for a '-', as we need to encode negative zero
3830 bool isNegative = Parser.getTok().is(AsmToken::Minus);
3831 const MCExpr *Offset;
3832 if (getParser().ParseExpression(Offset))
3833 return MatchOperand_ParseFail;
3834 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
3836 Error(S, "constant expression expected");
3837 return MatchOperand_ParseFail;
3839 SMLoc E = Tok.getLoc();
3840 // Negative zero is encoded as the flag value INT32_MIN.
3841 int32_t Val = CE->getValue();
3842 if (isNegative && Val == 0)
3846 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
3848 return MatchOperand_Success;
3852 bool haveEaten = false;
3855 if (Tok.is(AsmToken::Plus)) {
3856 Parser.Lex(); // Eat the '+' token.
3858 } else if (Tok.is(AsmToken::Minus)) {
3859 Parser.Lex(); // Eat the '-' token.
3863 if (Parser.getTok().is(AsmToken::Identifier))
3864 Reg = tryParseRegister();
3867 return MatchOperand_NoMatch;
3868 Error(Parser.getTok().getLoc(), "register expected");
3869 return MatchOperand_ParseFail;
3871 SMLoc E = Parser.getTok().getLoc();
3873 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
3876 return MatchOperand_Success;
3879 /// cvtT2LdrdPre - Convert parsed operands to MCInst.
3880 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3881 /// when they refer multiple MIOperands inside a single one.
3883 cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
3884 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3886 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3887 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3888 // Create a writeback register dummy placeholder.
3889 Inst.addOperand(MCOperand::CreateReg(0));
3891 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3893 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3897 /// cvtT2StrdPre - Convert parsed operands to MCInst.
3898 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3899 /// when they refer multiple MIOperands inside a single one.
3901 cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
3902 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3903 // Create a writeback register dummy placeholder.
3904 Inst.addOperand(MCOperand::CreateReg(0));
3906 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3907 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3909 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3911 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3915 /// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3916 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3917 /// when they refer multiple MIOperands inside a single one.
3919 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3920 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3921 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3923 // Create a writeback register dummy placeholder.
3924 Inst.addOperand(MCOperand::CreateImm(0));
3926 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3927 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3931 /// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3932 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3933 /// when they refer multiple MIOperands inside a single one.
3935 cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3936 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3937 // Create a writeback register dummy placeholder.
3938 Inst.addOperand(MCOperand::CreateImm(0));
3939 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3940 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3941 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3945 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3946 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3947 /// when they refer multiple MIOperands inside a single one.
3949 cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3950 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3951 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3953 // Create a writeback register dummy placeholder.
3954 Inst.addOperand(MCOperand::CreateImm(0));
3956 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3957 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3961 /// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3962 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3963 /// when they refer multiple MIOperands inside a single one.
3965 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3966 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3967 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3969 // Create a writeback register dummy placeholder.
3970 Inst.addOperand(MCOperand::CreateImm(0));
3972 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3973 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3978 /// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3979 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3980 /// when they refer multiple MIOperands inside a single one.
3982 cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3983 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3984 // Create a writeback register dummy placeholder.
3985 Inst.addOperand(MCOperand::CreateImm(0));
3986 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3987 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3988 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3992 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3993 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3994 /// when they refer multiple MIOperands inside a single one.
3996 cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3997 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3998 // Create a writeback register dummy placeholder.
3999 Inst.addOperand(MCOperand::CreateImm(0));
4000 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4001 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
4002 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4006 /// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
4007 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4008 /// when they refer multiple MIOperands inside a single one.
4010 cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
4011 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4012 // Create a writeback register dummy placeholder.
4013 Inst.addOperand(MCOperand::CreateImm(0));
4014 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4015 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4016 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4020 /// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
4021 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4022 /// when they refer multiple MIOperands inside a single one.
4024 cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
4025 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4027 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4028 // Create a writeback register dummy placeholder.
4029 Inst.addOperand(MCOperand::CreateImm(0));
4031 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4033 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4035 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4039 /// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
4040 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4041 /// when they refer multiple MIOperands inside a single one.
4043 cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
4044 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4046 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4047 // Create a writeback register dummy placeholder.
4048 Inst.addOperand(MCOperand::CreateImm(0));
4050 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4052 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4054 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4058 /// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
4059 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4060 /// when they refer multiple MIOperands inside a single one.
4062 cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
4063 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4064 // Create a writeback register dummy placeholder.
4065 Inst.addOperand(MCOperand::CreateImm(0));
4067 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4069 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4071 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4073 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4077 /// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
4078 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4079 /// when they refer multiple MIOperands inside a single one.
4081 cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
4082 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4083 // Create a writeback register dummy placeholder.
4084 Inst.addOperand(MCOperand::CreateImm(0));
4086 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4088 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4090 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4092 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4096 /// cvtLdrdPre - Convert parsed operands to MCInst.
4097 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4098 /// when they refer multiple MIOperands inside a single one.
4100 cvtLdrdPre(MCInst &Inst, unsigned Opcode,
4101 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4103 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4104 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4105 // Create a writeback register dummy placeholder.
4106 Inst.addOperand(MCOperand::CreateImm(0));
4108 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4110 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4114 /// cvtStrdPre - Convert parsed operands to MCInst.
4115 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4116 /// when they refer multiple MIOperands inside a single one.
4118 cvtStrdPre(MCInst &Inst, unsigned Opcode,
4119 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4120 // Create a writeback register dummy placeholder.
4121 Inst.addOperand(MCOperand::CreateImm(0));
4123 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4124 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4126 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4128 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4132 /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
4133 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4134 /// when they refer multiple MIOperands inside a single one.
4136 cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
4137 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4138 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4139 // Create a writeback register dummy placeholder.
4140 Inst.addOperand(MCOperand::CreateImm(0));
4141 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4142 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4146 /// cvtThumbMultiple- Convert parsed operands to MCInst.
4147 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4148 /// when they refer multiple MIOperands inside a single one.
4150 cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
4151 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4152 // The second source operand must be the same register as the destination
4154 if (Operands.size() == 6 &&
4155 (((ARMOperand*)Operands[3])->getReg() !=
4156 ((ARMOperand*)Operands[5])->getReg()) &&
4157 (((ARMOperand*)Operands[3])->getReg() !=
4158 ((ARMOperand*)Operands[4])->getReg())) {
4159 Error(Operands[3]->getStartLoc(),
4160 "destination register must match source register");
4163 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4164 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4165 // If we have a three-operand form, make sure to set Rn to be the operand
4166 // that isn't the same as Rd.
4168 if (Operands.size() == 6 &&
4169 ((ARMOperand*)Operands[4])->getReg() ==
4170 ((ARMOperand*)Operands[3])->getReg())
4172 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4173 Inst.addOperand(Inst.getOperand(0));
4174 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4180 cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
4181 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4183 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4184 // Create a writeback register dummy placeholder.
4185 Inst.addOperand(MCOperand::CreateImm(0));
4187 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4189 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4194 cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
4195 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4197 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4198 // Create a writeback register dummy placeholder.
4199 Inst.addOperand(MCOperand::CreateImm(0));
4201 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4203 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4205 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4210 cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
4211 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4212 // Create a writeback register dummy placeholder.
4213 Inst.addOperand(MCOperand::CreateImm(0));
4215 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4217 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4219 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4224 cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
4225 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4226 // Create a writeback register dummy placeholder.
4227 Inst.addOperand(MCOperand::CreateImm(0));
4229 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4231 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4233 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4235 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4239 /// Parse an ARM memory expression, return false if successful else return true
4240 /// or an error. The first token must be a '[' when called.
4242 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4244 assert(Parser.getTok().is(AsmToken::LBrac) &&
4245 "Token is not a Left Bracket");
4246 S = Parser.getTok().getLoc();
4247 Parser.Lex(); // Eat left bracket token.
4249 const AsmToken &BaseRegTok = Parser.getTok();
4250 int BaseRegNum = tryParseRegister();
4251 if (BaseRegNum == -1)
4252 return Error(BaseRegTok.getLoc(), "register expected");
4254 // The next token must either be a comma or a closing bracket.
4255 const AsmToken &Tok = Parser.getTok();
4256 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
4257 return Error(Tok.getLoc(), "malformed memory operand");
4259 if (Tok.is(AsmToken::RBrac)) {
4261 Parser.Lex(); // Eat right bracket token.
4263 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4264 0, 0, false, S, E));
4266 // If there's a pre-indexing writeback marker, '!', just add it as a token
4267 // operand. It's rather odd, but syntactically valid.
4268 if (Parser.getTok().is(AsmToken::Exclaim)) {
4269 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4270 Parser.Lex(); // Eat the '!'.
4276 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
4277 Parser.Lex(); // Eat the comma.
4279 // If we have a ':', it's an alignment specifier.
4280 if (Parser.getTok().is(AsmToken::Colon)) {
4281 Parser.Lex(); // Eat the ':'.
4282 E = Parser.getTok().getLoc();
4285 if (getParser().ParseExpression(Expr))
4288 // The expression has to be a constant. Memory references with relocations
4289 // don't come through here, as they use the <label> forms of the relevant
4291 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4293 return Error (E, "constant expression expected");
4296 switch (CE->getValue()) {
4299 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4300 case 16: Align = 2; break;
4301 case 32: Align = 4; break;
4302 case 64: Align = 8; break;
4303 case 128: Align = 16; break;
4304 case 256: Align = 32; break;
4307 // Now we should have the closing ']'
4308 E = Parser.getTok().getLoc();
4309 if (Parser.getTok().isNot(AsmToken::RBrac))
4310 return Error(E, "']' expected");
4311 Parser.Lex(); // Eat right bracket token.
4313 // Don't worry about range checking the value here. That's handled by
4314 // the is*() predicates.
4315 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4316 ARM_AM::no_shift, 0, Align,
4319 // If there's a pre-indexing writeback marker, '!', just add it as a token
4321 if (Parser.getTok().is(AsmToken::Exclaim)) {
4322 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4323 Parser.Lex(); // Eat the '!'.
4329 // If we have a '#', it's an immediate offset, else assume it's a register
4330 // offset. Be friendly and also accept a plain integer (without a leading
4331 // hash) for gas compatibility.
4332 if (Parser.getTok().is(AsmToken::Hash) ||
4333 Parser.getTok().is(AsmToken::Dollar) ||
4334 Parser.getTok().is(AsmToken::Integer)) {
4335 if (Parser.getTok().isNot(AsmToken::Integer))
4336 Parser.Lex(); // Eat the '#'.
4337 E = Parser.getTok().getLoc();
4339 bool isNegative = getParser().getTok().is(AsmToken::Minus);
4340 const MCExpr *Offset;
4341 if (getParser().ParseExpression(Offset))
4344 // The expression has to be a constant. Memory references with relocations
4345 // don't come through here, as they use the <label> forms of the relevant
4347 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4349 return Error (E, "constant expression expected");
4351 // If the constant was #-0, represent it as INT32_MIN.
4352 int32_t Val = CE->getValue();
4353 if (isNegative && Val == 0)
4354 CE = MCConstantExpr::Create(INT32_MIN, getContext());
4356 // Now we should have the closing ']'
4357 E = Parser.getTok().getLoc();
4358 if (Parser.getTok().isNot(AsmToken::RBrac))
4359 return Error(E, "']' expected");
4360 Parser.Lex(); // Eat right bracket token.
4362 // Don't worry about range checking the value here. That's handled by
4363 // the is*() predicates.
4364 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4365 ARM_AM::no_shift, 0, 0,
4368 // If there's a pre-indexing writeback marker, '!', just add it as a token
4370 if (Parser.getTok().is(AsmToken::Exclaim)) {
4371 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4372 Parser.Lex(); // Eat the '!'.
4378 // The register offset is optionally preceded by a '+' or '-'
4379 bool isNegative = false;
4380 if (Parser.getTok().is(AsmToken::Minus)) {
4382 Parser.Lex(); // Eat the '-'.
4383 } else if (Parser.getTok().is(AsmToken::Plus)) {
4385 Parser.Lex(); // Eat the '+'.
4388 E = Parser.getTok().getLoc();
4389 int OffsetRegNum = tryParseRegister();
4390 if (OffsetRegNum == -1)
4391 return Error(E, "register expected");
4393 // If there's a shift operator, handle it.
4394 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4395 unsigned ShiftImm = 0;
4396 if (Parser.getTok().is(AsmToken::Comma)) {
4397 Parser.Lex(); // Eat the ','.
4398 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4402 // Now we should have the closing ']'
4403 E = Parser.getTok().getLoc();
4404 if (Parser.getTok().isNot(AsmToken::RBrac))
4405 return Error(E, "']' expected");
4406 Parser.Lex(); // Eat right bracket token.
4408 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4409 ShiftType, ShiftImm, 0, isNegative,
4412 // If there's a pre-indexing writeback marker, '!', just add it as a token
4414 if (Parser.getTok().is(AsmToken::Exclaim)) {
4415 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4416 Parser.Lex(); // Eat the '!'.
4422 /// parseMemRegOffsetShift - one of these two:
4423 /// ( lsl | lsr | asr | ror ) , # shift_amount
4425 /// return true if it parses a shift otherwise it returns false.
4426 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4428 SMLoc Loc = Parser.getTok().getLoc();
4429 const AsmToken &Tok = Parser.getTok();
4430 if (Tok.isNot(AsmToken::Identifier))
4432 StringRef ShiftName = Tok.getString();
4433 if (ShiftName == "lsl" || ShiftName == "LSL" ||
4434 ShiftName == "asl" || ShiftName == "ASL")
4436 else if (ShiftName == "lsr" || ShiftName == "LSR")
4438 else if (ShiftName == "asr" || ShiftName == "ASR")
4440 else if (ShiftName == "ror" || ShiftName == "ROR")
4442 else if (ShiftName == "rrx" || ShiftName == "RRX")
4445 return Error(Loc, "illegal shift operator");
4446 Parser.Lex(); // Eat shift type token.
4448 // rrx stands alone.
4450 if (St != ARM_AM::rrx) {
4451 Loc = Parser.getTok().getLoc();
4452 // A '#' and a shift amount.
4453 const AsmToken &HashTok = Parser.getTok();
4454 if (HashTok.isNot(AsmToken::Hash) &&
4455 HashTok.isNot(AsmToken::Dollar))
4456 return Error(HashTok.getLoc(), "'#' expected");
4457 Parser.Lex(); // Eat hash token.
4460 if (getParser().ParseExpression(Expr))
4462 // Range check the immediate.
4463 // lsl, ror: 0 <= imm <= 31
4464 // lsr, asr: 0 <= imm <= 32
4465 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4467 return Error(Loc, "shift amount must be an immediate");
4468 int64_t Imm = CE->getValue();
4470 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4471 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4472 return Error(Loc, "immediate shift value out of range");
4479 /// parseFPImm - A floating point immediate expression operand.
4480 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4481 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4482 // Anything that can accept a floating point constant as an operand
4483 // needs to go through here, as the regular ParseExpression is
4486 // This routine still creates a generic Immediate operand, containing
4487 // a bitcast of the 64-bit floating point value. The various operands
4488 // that accept floats can check whether the value is valid for them
4489 // via the standard is*() predicates.
4491 SMLoc S = Parser.getTok().getLoc();
4493 if (Parser.getTok().isNot(AsmToken::Hash) &&
4494 Parser.getTok().isNot(AsmToken::Dollar))
4495 return MatchOperand_NoMatch;
4497 // Disambiguate the VMOV forms that can accept an FP immediate.
4498 // vmov.f32 <sreg>, #imm
4499 // vmov.f64 <dreg>, #imm
4500 // vmov.f32 <dreg>, #imm @ vector f32x2
4501 // vmov.f32 <qreg>, #imm @ vector f32x4
4503 // There are also the NEON VMOV instructions which expect an
4504 // integer constant. Make sure we don't try to parse an FPImm
4506 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4507 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4508 if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
4509 TyOp->getToken() != ".f64"))
4510 return MatchOperand_NoMatch;
4512 Parser.Lex(); // Eat the '#'.
4514 // Handle negation, as that still comes through as a separate token.
4515 bool isNegative = false;
4516 if (Parser.getTok().is(AsmToken::Minus)) {
4520 const AsmToken &Tok = Parser.getTok();
4521 SMLoc Loc = Tok.getLoc();
4522 if (Tok.is(AsmToken::Real)) {
4523 APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4524 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4525 // If we had a '-' in front, toggle the sign bit.
4526 IntVal ^= (uint64_t)isNegative << 31;
4527 Parser.Lex(); // Eat the token.
4528 Operands.push_back(ARMOperand::CreateImm(
4529 MCConstantExpr::Create(IntVal, getContext()),
4530 S, Parser.getTok().getLoc()));
4531 return MatchOperand_Success;
4533 // Also handle plain integers. Instructions which allow floating point
4534 // immediates also allow a raw encoded 8-bit value.
4535 if (Tok.is(AsmToken::Integer)) {
4536 int64_t Val = Tok.getIntVal();
4537 Parser.Lex(); // Eat the token.
4538 if (Val > 255 || Val < 0) {
4539 Error(Loc, "encoded floating point value out of range");
4540 return MatchOperand_ParseFail;
4542 double RealVal = ARM_AM::getFPImmFloat(Val);
4543 Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue();
4544 Operands.push_back(ARMOperand::CreateImm(
4545 MCConstantExpr::Create(Val, getContext()), S,
4546 Parser.getTok().getLoc()));
4547 return MatchOperand_Success;
4550 Error(Loc, "invalid floating point immediate");
4551 return MatchOperand_ParseFail;
4554 /// Parse a arm instruction operand. For now this parses the operand regardless
4555 /// of the mnemonic.
4556 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4557 StringRef Mnemonic) {
4560 // Check if the current operand has a custom associated parser, if so, try to
4561 // custom parse the operand, or fallback to the general approach.
4562 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4563 if (ResTy == MatchOperand_Success)
4565 // If there wasn't a custom match, try the generic matcher below. Otherwise,
4566 // there was a match, but an error occurred, in which case, just return that
4567 // the operand parsing failed.
4568 if (ResTy == MatchOperand_ParseFail)
4571 switch (getLexer().getKind()) {
4573 Error(Parser.getTok().getLoc(), "unexpected token in operand");
4575 case AsmToken::Identifier: {
4576 if (!tryParseRegisterWithWriteBack(Operands))
4578 int Res = tryParseShiftRegister(Operands);
4579 if (Res == 0) // success
4581 else if (Res == -1) // irrecoverable error
4583 // If this is VMRS, check for the apsr_nzcv operand.
4584 if (Mnemonic == "vmrs" &&
4585 Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4586 S = Parser.getTok().getLoc();
4588 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4592 // Fall though for the Identifier case that is not a register or a
4595 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
4596 case AsmToken::Integer: // things like 1f and 2b as a branch targets
4597 case AsmToken::String: // quoted label names.
4598 case AsmToken::Dot: { // . as a branch target
4599 // This was not a register so parse other operands that start with an
4600 // identifier (like labels) as expressions and create them as immediates.
4601 const MCExpr *IdVal;
4602 S = Parser.getTok().getLoc();
4603 if (getParser().ParseExpression(IdVal))
4605 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4606 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4609 case AsmToken::LBrac:
4610 return parseMemory(Operands);
4611 case AsmToken::LCurly:
4612 return parseRegisterList(Operands);
4613 case AsmToken::Dollar:
4614 case AsmToken::Hash: {
4615 // #42 -> immediate.
4616 S = Parser.getTok().getLoc();
4619 if (Parser.getTok().isNot(AsmToken::Colon)) {
4620 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4621 const MCExpr *ImmVal;
4622 if (getParser().ParseExpression(ImmVal))
4624 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4626 int32_t Val = CE->getValue();
4627 if (isNegative && Val == 0)
4628 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4630 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4631 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4634 // w/ a ':' after the '#', it's just like a plain ':'.
4637 case AsmToken::Colon: {
4638 // ":lower16:" and ":upper16:" expression prefixes
4639 // FIXME: Check it's an expression prefix,
4640 // e.g. (FOO - :lower16:BAR) isn't legal.
4641 ARMMCExpr::VariantKind RefKind;
4642 if (parsePrefix(RefKind))
4645 const MCExpr *SubExprVal;
4646 if (getParser().ParseExpression(SubExprVal))
4649 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4651 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4652 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4658 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4659 // :lower16: and :upper16:.
4660 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4661 RefKind = ARMMCExpr::VK_ARM_None;
4663 // :lower16: and :upper16: modifiers
4664 assert(getLexer().is(AsmToken::Colon) && "expected a :");
4665 Parser.Lex(); // Eat ':'
4667 if (getLexer().isNot(AsmToken::Identifier)) {
4668 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4672 StringRef IDVal = Parser.getTok().getIdentifier();
4673 if (IDVal == "lower16") {
4674 RefKind = ARMMCExpr::VK_ARM_LO16;
4675 } else if (IDVal == "upper16") {
4676 RefKind = ARMMCExpr::VK_ARM_HI16;
4678 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4683 if (getLexer().isNot(AsmToken::Colon)) {
4684 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4687 Parser.Lex(); // Eat the last ':'
4691 /// \brief Given a mnemonic, split out possible predication code and carry
4692 /// setting letters to form a canonical mnemonic and flags.
4694 // FIXME: Would be nice to autogen this.
4695 // FIXME: This is a bit of a maze of special cases.
4696 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4697 unsigned &PredicationCode,
4699 unsigned &ProcessorIMod,
4700 StringRef &ITMask) {
4701 PredicationCode = ARMCC::AL;
4702 CarrySetting = false;
4705 // Ignore some mnemonics we know aren't predicated forms.
4707 // FIXME: Would be nice to autogen this.
4708 if ((Mnemonic == "movs" && isThumb()) ||
4709 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
4710 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
4711 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
4712 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
4713 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
4714 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
4715 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4716 Mnemonic == "fmuls")
4719 // First, split out any predication code. Ignore mnemonics we know aren't
4720 // predicated but do have a carry-set and so weren't caught above.
4721 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4722 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4723 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4724 Mnemonic != "sbcs" && Mnemonic != "rscs") {
4725 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4726 .Case("eq", ARMCC::EQ)
4727 .Case("ne", ARMCC::NE)
4728 .Case("hs", ARMCC::HS)
4729 .Case("cs", ARMCC::HS)
4730 .Case("lo", ARMCC::LO)
4731 .Case("cc", ARMCC::LO)
4732 .Case("mi", ARMCC::MI)
4733 .Case("pl", ARMCC::PL)
4734 .Case("vs", ARMCC::VS)
4735 .Case("vc", ARMCC::VC)
4736 .Case("hi", ARMCC::HI)
4737 .Case("ls", ARMCC::LS)
4738 .Case("ge", ARMCC::GE)
4739 .Case("lt", ARMCC::LT)
4740 .Case("gt", ARMCC::GT)
4741 .Case("le", ARMCC::LE)
4742 .Case("al", ARMCC::AL)
4745 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4746 PredicationCode = CC;
4750 // Next, determine if we have a carry setting bit. We explicitly ignore all
4751 // the instructions we know end in 's'.
4752 if (Mnemonic.endswith("s") &&
4753 !(Mnemonic == "cps" || Mnemonic == "mls" ||
4754 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4755 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4756 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4757 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4758 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4759 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4760 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
4761 Mnemonic == "vfms" || Mnemonic == "vfnms" ||
4762 (Mnemonic == "movs" && isThumb()))) {
4763 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4764 CarrySetting = true;
4767 // The "cps" instruction can have a interrupt mode operand which is glued into
4768 // the mnemonic. Check if this is the case, split it and parse the imod op
4769 if (Mnemonic.startswith("cps")) {
4770 // Split out any imod code.
4772 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4773 .Case("ie", ARM_PROC::IE)
4774 .Case("id", ARM_PROC::ID)
4777 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4778 ProcessorIMod = IMod;
4782 // The "it" instruction has the condition mask on the end of the mnemonic.
4783 if (Mnemonic.startswith("it")) {
4784 ITMask = Mnemonic.slice(2, Mnemonic.size());
4785 Mnemonic = Mnemonic.slice(0, 2);
4791 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
4792 /// inclusion of carry set or predication code operands.
4794 // FIXME: It would be nice to autogen this.
4796 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
4797 bool &CanAcceptPredicationCode) {
4798 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4799 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4800 Mnemonic == "add" || Mnemonic == "adc" ||
4801 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4802 Mnemonic == "orr" || Mnemonic == "mvn" ||
4803 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4804 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4805 Mnemonic == "vfm" || Mnemonic == "vfnm" ||
4806 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4807 Mnemonic == "mla" || Mnemonic == "smlal" ||
4808 Mnemonic == "umlal" || Mnemonic == "umull"))) {
4809 CanAcceptCarrySet = true;
4811 CanAcceptCarrySet = false;
4813 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
4814 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
4815 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
4816 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
4817 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
4818 (Mnemonic == "clrex" && !isThumb()) ||
4819 (Mnemonic == "nop" && isThumbOne()) ||
4820 ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" ||
4821 Mnemonic == "ldc2" || Mnemonic == "ldc2l" ||
4822 Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) ||
4823 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
4825 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
4826 CanAcceptPredicationCode = false;
4828 CanAcceptPredicationCode = true;
4831 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
4832 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
4833 CanAcceptPredicationCode = false;
4837 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4838 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4839 // FIXME: This is all horribly hacky. We really need a better way to deal
4840 // with optional operands like this in the matcher table.
4842 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4843 // another does not. Specifically, the MOVW instruction does not. So we
4844 // special case it here and remove the defaulted (non-setting) cc_out
4845 // operand if that's the instruction we're trying to match.
4847 // We do this as post-processing of the explicit operands rather than just
4848 // conditionally adding the cc_out in the first place because we need
4849 // to check the type of the parsed immediate operand.
4850 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4851 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4852 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4853 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4856 // Register-register 'add' for thumb does not have a cc_out operand
4857 // when there are only two register operands.
4858 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4859 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4860 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4861 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4863 // Register-register 'add' for thumb does not have a cc_out operand
4864 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4865 // have to check the immediate range here since Thumb2 has a variant
4866 // that can handle a different range and has a cc_out operand.
4867 if (((isThumb() && Mnemonic == "add") ||
4868 (isThumbTwo() && Mnemonic == "sub")) &&
4869 Operands.size() == 6 &&
4870 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4871 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4872 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4873 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4874 ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
4875 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4877 // For Thumb2, add/sub immediate does not have a cc_out operand for the
4878 // imm0_4095 variant. That's the least-preferred variant when
4879 // selecting via the generic "add" mnemonic, so to know that we
4880 // should remove the cc_out operand, we have to explicitly check that
4881 // it's not one of the other variants. Ugh.
4882 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4883 Operands.size() == 6 &&
4884 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4885 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4886 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4887 // Nest conditions rather than one big 'if' statement for readability.
4889 // If either register is a high reg, it's either one of the SP
4890 // variants (handled above) or a 32-bit encoding, so we just
4891 // check against T3. If the second register is the PC, this is an
4892 // alternate form of ADR, which uses encoding T4, so check for that too.
4893 if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4894 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
4895 static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
4896 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
4898 // If both registers are low, we're in an IT block, and the immediate is
4899 // in range, we should use encoding T1 instead, which has a cc_out.
4901 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4902 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4903 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
4906 // Otherwise, we use encoding T4, which does not have a cc_out
4911 // The thumb2 multiply instruction doesn't have a CCOut register, so
4912 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
4913 // use the 16-bit encoding or not.
4914 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
4915 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4916 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4917 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4918 static_cast<ARMOperand*>(Operands[5])->isReg() &&
4919 // If the registers aren't low regs, the destination reg isn't the
4920 // same as one of the source regs, or the cc_out operand is zero
4921 // outside of an IT block, we have to use the 32-bit encoding, so
4922 // remove the cc_out operand.
4923 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4924 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4925 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
4927 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4928 static_cast<ARMOperand*>(Operands[5])->getReg() &&
4929 static_cast<ARMOperand*>(Operands[3])->getReg() !=
4930 static_cast<ARMOperand*>(Operands[4])->getReg())))
4933 // Also check the 'mul' syntax variant that doesn't specify an explicit
4934 // destination register.
4935 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
4936 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4937 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4938 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4939 // If the registers aren't low regs or the cc_out operand is zero
4940 // outside of an IT block, we have to use the 32-bit encoding, so
4941 // remove the cc_out operand.
4942 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4943 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4949 // Register-register 'add/sub' for thumb does not have a cc_out operand
4950 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
4951 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
4952 // right, this will result in better diagnostics (which operand is off)
4954 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
4955 (Operands.size() == 5 || Operands.size() == 6) &&
4956 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4957 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4958 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4959 (static_cast<ARMOperand*>(Operands[4])->isImm() ||
4960 (Operands.size() == 6 &&
4961 static_cast<ARMOperand*>(Operands[5])->isImm())))
4967 static bool isDataTypeToken(StringRef Tok) {
4968 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
4969 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
4970 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
4971 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
4972 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
4973 Tok == ".f" || Tok == ".d";
4976 // FIXME: This bit should probably be handled via an explicit match class
4977 // in the .td files that matches the suffix instead of having it be
4978 // a literal string token the way it is now.
4979 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
4980 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
4983 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features);
4984 /// Parse an arm instruction mnemonic followed by its operands.
4985 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
4986 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4987 // Apply mnemonic aliases before doing anything else, as the destination
4988 // mnemnonic may include suffices and we want to handle them normally.
4989 // The generic tblgen'erated code does this later, at the start of
4990 // MatchInstructionImpl(), but that's too late for aliases that include
4991 // any sort of suffix.
4992 unsigned AvailableFeatures = getAvailableFeatures();
4993 applyMnemonicAliases(Name, AvailableFeatures);
4995 // First check for the ARM-specific .req directive.
4996 if (Parser.getTok().is(AsmToken::Identifier) &&
4997 Parser.getTok().getIdentifier() == ".req") {
4998 parseDirectiveReq(Name, NameLoc);
4999 // We always return 'error' for this, as we're done with this
5000 // statement and don't need to match the 'instruction."
5004 // Create the leading tokens for the mnemonic, split by '.' characters.
5005 size_t Start = 0, Next = Name.find('.');
5006 StringRef Mnemonic = Name.slice(Start, Next);
5008 // Split out the predication code and carry setting flag from the mnemonic.
5009 unsigned PredicationCode;
5010 unsigned ProcessorIMod;
5013 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5014 ProcessorIMod, ITMask);
5016 // In Thumb1, only the branch (B) instruction can be predicated.
5017 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5018 Parser.EatToEndOfStatement();
5019 return Error(NameLoc, "conditional execution not supported in Thumb1");
5022 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5024 // Handle the IT instruction ITMask. Convert it to a bitmask. This
5025 // is the mask as it will be for the IT encoding if the conditional
5026 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5027 // where the conditional bit0 is zero, the instruction post-processing
5028 // will adjust the mask accordingly.
5029 if (Mnemonic == "it") {
5030 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5031 if (ITMask.size() > 3) {
5032 Parser.EatToEndOfStatement();
5033 return Error(Loc, "too many conditions on IT instruction");
5036 for (unsigned i = ITMask.size(); i != 0; --i) {
5037 char pos = ITMask[i - 1];
5038 if (pos != 't' && pos != 'e') {
5039 Parser.EatToEndOfStatement();
5040 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5043 if (ITMask[i - 1] == 't')
5046 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5049 // FIXME: This is all a pretty gross hack. We should automatically handle
5050 // optional operands like this via tblgen.
5052 // Next, add the CCOut and ConditionCode operands, if needed.
5054 // For mnemonics which can ever incorporate a carry setting bit or predication
5055 // code, our matching model involves us always generating CCOut and
5056 // ConditionCode operands to match the mnemonic "as written" and then we let
5057 // the matcher deal with finding the right instruction or generating an
5058 // appropriate error.
5059 bool CanAcceptCarrySet, CanAcceptPredicationCode;
5060 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
5062 // If we had a carry-set on an instruction that can't do that, issue an
5064 if (!CanAcceptCarrySet && CarrySetting) {
5065 Parser.EatToEndOfStatement();
5066 return Error(NameLoc, "instruction '" + Mnemonic +
5067 "' can not set flags, but 's' suffix specified");
5069 // If we had a predication code on an instruction that can't do that, issue an
5071 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5072 Parser.EatToEndOfStatement();
5073 return Error(NameLoc, "instruction '" + Mnemonic +
5074 "' is not predicable, but condition code specified");
5077 // Add the carry setting operand, if necessary.
5078 if (CanAcceptCarrySet) {
5079 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5080 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5084 // Add the predication code operand, if necessary.
5085 if (CanAcceptPredicationCode) {
5086 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5088 Operands.push_back(ARMOperand::CreateCondCode(
5089 ARMCC::CondCodes(PredicationCode), Loc));
5092 // Add the processor imod operand, if necessary.
5093 if (ProcessorIMod) {
5094 Operands.push_back(ARMOperand::CreateImm(
5095 MCConstantExpr::Create(ProcessorIMod, getContext()),
5099 // Add the remaining tokens in the mnemonic.
5100 while (Next != StringRef::npos) {
5102 Next = Name.find('.', Start + 1);
5103 StringRef ExtraToken = Name.slice(Start, Next);
5105 // Some NEON instructions have an optional datatype suffix that is
5106 // completely ignored. Check for that.
5107 if (isDataTypeToken(ExtraToken) &&
5108 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5111 if (ExtraToken != ".n") {
5112 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5113 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5117 // Read the remaining operands.
5118 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5119 // Read the first operand.
5120 if (parseOperand(Operands, Mnemonic)) {
5121 Parser.EatToEndOfStatement();
5125 while (getLexer().is(AsmToken::Comma)) {
5126 Parser.Lex(); // Eat the comma.
5128 // Parse and remember the operand.
5129 if (parseOperand(Operands, Mnemonic)) {
5130 Parser.EatToEndOfStatement();
5136 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5137 SMLoc Loc = getLexer().getLoc();
5138 Parser.EatToEndOfStatement();
5139 return Error(Loc, "unexpected token in argument list");
5142 Parser.Lex(); // Consume the EndOfStatement
5144 // Some instructions, mostly Thumb, have forms for the same mnemonic that
5145 // do and don't have a cc_out optional-def operand. With some spot-checks
5146 // of the operand list, we can figure out which variant we're trying to
5147 // parse and adjust accordingly before actually matching. We shouldn't ever
5148 // try to remove a cc_out operand that was explicitly set on the the
5149 // mnemonic, of course (CarrySetting == true). Reason number #317 the
5150 // table driven matcher doesn't fit well with the ARM instruction set.
5151 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5152 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5153 Operands.erase(Operands.begin() + 1);
5157 // ARM mode 'blx' need special handling, as the register operand version
5158 // is predicable, but the label operand version is not. So, we can't rely
5159 // on the Mnemonic based checking to correctly figure out when to put
5160 // a k_CondCode operand in the list. If we're trying to match the label
5161 // version, remove the k_CondCode operand here.
5162 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5163 static_cast<ARMOperand*>(Operands[2])->isImm()) {
5164 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5165 Operands.erase(Operands.begin() + 1);
5169 // The vector-compare-to-zero instructions have a literal token "#0" at
5170 // the end that comes to here as an immediate operand. Convert it to a
5171 // token to play nicely with the matcher.
5172 if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
5173 Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
5174 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5175 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
5176 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5177 if (CE && CE->getValue() == 0) {
5178 Operands.erase(Operands.begin() + 5);
5179 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5183 // VCMP{E} does the same thing, but with a different operand count.
5184 if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 &&
5185 static_cast<ARMOperand*>(Operands[4])->isImm()) {
5186 ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]);
5187 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5188 if (CE && CE->getValue() == 0) {
5189 Operands.erase(Operands.begin() + 4);
5190 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5194 // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
5195 // end. Convert it to a token here. Take care not to convert those
5196 // that should hit the Thumb2 encoding.
5197 if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
5198 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5199 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5200 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5201 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
5202 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5203 if (CE && CE->getValue() == 0 &&
5205 // The cc_out operand matches the IT block.
5206 ((inITBlock() != CarrySetting) &&
5207 // Neither register operand is a high register.
5208 (isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
5209 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()))))){
5210 Operands.erase(Operands.begin() + 5);
5211 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5219 // Validate context-sensitive operand constraints.
5221 // return 'true' if register list contains non-low GPR registers,
5222 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5223 // 'containsReg' to true.
5224 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5225 unsigned HiReg, bool &containsReg) {
5226 containsReg = false;
5227 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5228 unsigned OpReg = Inst.getOperand(i).getReg();
5231 // Anything other than a low register isn't legal here.
5232 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5238 // Check if the specified regisgter is in the register list of the inst,
5239 // starting at the indicated operand number.
5240 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5241 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5242 unsigned OpReg = Inst.getOperand(i).getReg();
5249 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around
5250 // the ARMInsts array) instead. Getting that here requires awkward
5251 // API changes, though. Better way?
5253 extern const MCInstrDesc ARMInsts[];
5255 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
5256 return ARMInsts[Opcode];
5259 // FIXME: We would really like to be able to tablegen'erate this.
5261 validateInstruction(MCInst &Inst,
5262 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5263 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
5264 SMLoc Loc = Operands[0]->getStartLoc();
5265 // Check the IT block state first.
5266 // NOTE: BKPT instruction has the interesting property of being
5267 // allowed in IT blocks, but not being predicable. It just always
5269 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT &&
5270 Inst.getOpcode() != ARM::BKPT) {
5272 if (ITState.FirstCond)
5273 ITState.FirstCond = false;
5275 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5276 // The instruction must be predicable.
5277 if (!MCID.isPredicable())
5278 return Error(Loc, "instructions in IT block must be predicable");
5279 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5280 unsigned ITCond = bit ? ITState.Cond :
5281 ARMCC::getOppositeCondition(ITState.Cond);
5282 if (Cond != ITCond) {
5283 // Find the condition code Operand to get its SMLoc information.
5285 for (unsigned i = 1; i < Operands.size(); ++i)
5286 if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
5287 CondLoc = Operands[i]->getStartLoc();
5288 return Error(CondLoc, "incorrect condition in IT block; got '" +
5289 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5290 "', but expected '" +
5291 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5293 // Check for non-'al' condition codes outside of the IT block.
5294 } else if (isThumbTwo() && MCID.isPredicable() &&
5295 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5296 ARMCC::AL && Inst.getOpcode() != ARM::tB &&
5297 Inst.getOpcode() != ARM::t2B)
5298 return Error(Loc, "predicated instructions must be in IT block");
5300 switch (Inst.getOpcode()) {
5303 case ARM::LDRD_POST:
5305 // Rt2 must be Rt + 1.
5306 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
5307 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
5309 return Error(Operands[3]->getStartLoc(),
5310 "destination operands must be sequential");
5314 // Rt2 must be Rt + 1.
5315 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
5316 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
5318 return Error(Operands[3]->getStartLoc(),
5319 "source operands must be sequential");
5323 case ARM::STRD_POST:
5325 // Rt2 must be Rt + 1.
5326 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
5327 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
5329 return Error(Operands[3]->getStartLoc(),
5330 "source operands must be sequential");
5335 // width must be in range [1, 32-lsb]
5336 unsigned lsb = Inst.getOperand(2).getImm();
5337 unsigned widthm1 = Inst.getOperand(3).getImm();
5338 if (widthm1 >= 32 - lsb)
5339 return Error(Operands[5]->getStartLoc(),
5340 "bitfield width must be in range [1,32-lsb]");
5344 // If we're parsing Thumb2, the .w variant is available and handles
5345 // most cases that are normally illegal for a Thumb1 LDM
5346 // instruction. We'll make the transformation in processInstruction()
5349 // Thumb LDM instructions are writeback iff the base register is not
5350 // in the register list.
5351 unsigned Rn = Inst.getOperand(0).getReg();
5352 bool hasWritebackToken =
5353 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5354 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5355 bool listContainsBase;
5356 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
5357 return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
5358 "registers must be in range r0-r7");
5359 // If we should have writeback, then there should be a '!' token.
5360 if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
5361 return Error(Operands[2]->getStartLoc(),
5362 "writeback operator '!' expected");
5363 // If we should not have writeback, there must not be a '!'. This is
5364 // true even for the 32-bit wide encodings.
5365 if (listContainsBase && hasWritebackToken)
5366 return Error(Operands[3]->getStartLoc(),
5367 "writeback operator '!' not allowed when base register "
5368 "in register list");
5372 case ARM::t2LDMIA_UPD: {
5373 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5374 return Error(Operands[4]->getStartLoc(),
5375 "writeback operator '!' not allowed when base register "
5376 "in register list");
5379 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5380 // so only issue a diagnostic for thumb1. The instructions will be
5381 // switched to the t2 encodings in processInstruction() if necessary.
5383 bool listContainsBase;
5384 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
5386 return Error(Operands[2]->getStartLoc(),
5387 "registers must be in range r0-r7 or pc");
5391 bool listContainsBase;
5392 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
5394 return Error(Operands[2]->getStartLoc(),
5395 "registers must be in range r0-r7 or lr");
5398 case ARM::tSTMIA_UPD: {
5399 bool listContainsBase;
5400 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
5401 return Error(Operands[4]->getStartLoc(),
5402 "registers must be in range r0-r7");
5405 case ARM::tADDrSP: {
5406 // If the non-SP source operand and the destination operand are not the
5407 // same, we need thumb2 (for the wide encoding), or we have an error.
5408 if (!isThumbTwo() &&
5409 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5410 return Error(Operands[4]->getStartLoc(),
5411 "source register must be the same as destination");
5420 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5422 default: llvm_unreachable("unexpected opcode!");
5424 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5425 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5426 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5427 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5428 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5429 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5430 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
5431 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5432 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5435 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5436 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5437 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5438 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5439 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5441 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5442 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5443 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5444 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5445 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5447 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
5448 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5449 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5450 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5451 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5454 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5455 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5456 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5457 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5458 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5459 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5460 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5461 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5462 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5463 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5464 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
5465 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5466 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5467 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5468 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5471 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5472 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5473 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5474 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5475 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5476 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5477 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5478 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5479 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5480 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5481 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5482 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5483 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
5484 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5485 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5486 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
5487 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5488 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5491 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5492 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5493 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5494 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5495 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5496 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5497 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5498 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5499 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5500 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5501 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
5502 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5503 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5504 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5505 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5508 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5509 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5510 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5511 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5512 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5513 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5514 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5515 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5516 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5517 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5518 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5519 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5520 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
5521 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5522 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5523 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
5524 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5525 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5529 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
5531 default: llvm_unreachable("unexpected opcode!");
5533 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5534 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5535 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5536 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5537 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5538 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5539 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
5540 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5541 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5544 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5545 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5546 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5547 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5548 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5549 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5550 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5551 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5552 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5553 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5554 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
5555 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5556 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5557 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5558 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5561 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5562 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5563 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5564 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5565 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5566 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5567 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5568 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5569 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5570 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5571 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5572 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5573 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
5574 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5575 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5576 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5577 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5578 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5581 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5582 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5583 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5584 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5585 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5586 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5587 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5588 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5589 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5590 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5591 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
5592 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5593 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5594 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5595 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5598 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5599 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5600 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5601 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5602 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5603 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5604 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5605 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5606 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5607 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5608 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5609 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5610 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
5611 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5612 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5613 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
5614 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5615 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
5618 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5619 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5620 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5621 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
5622 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5623 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5624 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5625 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5626 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5627 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5628 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
5629 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5630 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5631 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5632 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5635 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5636 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5637 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5638 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5639 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5640 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5641 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5642 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5643 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5644 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
5645 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
5646 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5647 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
5648 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
5649 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
5650 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
5651 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
5652 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
5655 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5656 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5657 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5658 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5659 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5660 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5661 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5662 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5663 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5664 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5665 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5666 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5667 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
5668 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
5669 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
5670 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
5671 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
5672 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
5677 processInstruction(MCInst &Inst,
5678 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5679 switch (Inst.getOpcode()) {
5680 // Aliases for alternate PC+imm syntax of LDR instructions.
5681 case ARM::t2LDRpcrel:
5682 Inst.setOpcode(ARM::t2LDRpci);
5684 case ARM::t2LDRBpcrel:
5685 Inst.setOpcode(ARM::t2LDRBpci);
5687 case ARM::t2LDRHpcrel:
5688 Inst.setOpcode(ARM::t2LDRHpci);
5690 case ARM::t2LDRSBpcrel:
5691 Inst.setOpcode(ARM::t2LDRSBpci);
5693 case ARM::t2LDRSHpcrel:
5694 Inst.setOpcode(ARM::t2LDRSHpci);
5696 // Handle NEON VST complex aliases.
5697 case ARM::VST1LNdWB_register_Asm_8:
5698 case ARM::VST1LNdWB_register_Asm_16:
5699 case ARM::VST1LNdWB_register_Asm_32: {
5701 // Shuffle the operands around so the lane index operand is in the
5704 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5705 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5706 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5707 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5708 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5709 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5710 TmpInst.addOperand(Inst.getOperand(1)); // lane
5711 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5712 TmpInst.addOperand(Inst.getOperand(6));
5717 case ARM::VST2LNdWB_register_Asm_8:
5718 case ARM::VST2LNdWB_register_Asm_16:
5719 case ARM::VST2LNdWB_register_Asm_32:
5720 case ARM::VST2LNqWB_register_Asm_16:
5721 case ARM::VST2LNqWB_register_Asm_32: {
5723 // Shuffle the operands around so the lane index operand is in the
5726 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5727 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5728 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5729 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5730 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5731 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5732 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5734 TmpInst.addOperand(Inst.getOperand(1)); // lane
5735 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5736 TmpInst.addOperand(Inst.getOperand(6));
5741 case ARM::VST3LNdWB_register_Asm_8:
5742 case ARM::VST3LNdWB_register_Asm_16:
5743 case ARM::VST3LNdWB_register_Asm_32:
5744 case ARM::VST3LNqWB_register_Asm_16:
5745 case ARM::VST3LNqWB_register_Asm_32: {
5747 // Shuffle the operands around so the lane index operand is in the
5750 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5751 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5752 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5753 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5754 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5755 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5756 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5758 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5760 TmpInst.addOperand(Inst.getOperand(1)); // lane
5761 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5762 TmpInst.addOperand(Inst.getOperand(6));
5767 case ARM::VST4LNdWB_register_Asm_8:
5768 case ARM::VST4LNdWB_register_Asm_16:
5769 case ARM::VST4LNdWB_register_Asm_32:
5770 case ARM::VST4LNqWB_register_Asm_16:
5771 case ARM::VST4LNqWB_register_Asm_32: {
5773 // Shuffle the operands around so the lane index operand is in the
5776 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5777 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5778 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5779 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5780 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5781 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5782 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5784 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5786 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5788 TmpInst.addOperand(Inst.getOperand(1)); // lane
5789 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5790 TmpInst.addOperand(Inst.getOperand(6));
5795 case ARM::VST1LNdWB_fixed_Asm_8:
5796 case ARM::VST1LNdWB_fixed_Asm_16:
5797 case ARM::VST1LNdWB_fixed_Asm_32: {
5799 // Shuffle the operands around so the lane index operand is in the
5802 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5803 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5804 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5805 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5806 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5807 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5808 TmpInst.addOperand(Inst.getOperand(1)); // lane
5809 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5810 TmpInst.addOperand(Inst.getOperand(5));
5815 case ARM::VST2LNdWB_fixed_Asm_8:
5816 case ARM::VST2LNdWB_fixed_Asm_16:
5817 case ARM::VST2LNdWB_fixed_Asm_32:
5818 case ARM::VST2LNqWB_fixed_Asm_16:
5819 case ARM::VST2LNqWB_fixed_Asm_32: {
5821 // Shuffle the operands around so the lane index operand is in the
5824 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5825 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5826 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5827 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5828 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5829 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5830 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5832 TmpInst.addOperand(Inst.getOperand(1)); // lane
5833 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5834 TmpInst.addOperand(Inst.getOperand(5));
5839 case ARM::VST3LNdWB_fixed_Asm_8:
5840 case ARM::VST3LNdWB_fixed_Asm_16:
5841 case ARM::VST3LNdWB_fixed_Asm_32:
5842 case ARM::VST3LNqWB_fixed_Asm_16:
5843 case ARM::VST3LNqWB_fixed_Asm_32: {
5845 // Shuffle the operands around so the lane index operand is in the
5848 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5849 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5850 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5851 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5852 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5853 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5854 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5856 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5858 TmpInst.addOperand(Inst.getOperand(1)); // lane
5859 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5860 TmpInst.addOperand(Inst.getOperand(5));
5865 case ARM::VST4LNdWB_fixed_Asm_8:
5866 case ARM::VST4LNdWB_fixed_Asm_16:
5867 case ARM::VST4LNdWB_fixed_Asm_32:
5868 case ARM::VST4LNqWB_fixed_Asm_16:
5869 case ARM::VST4LNqWB_fixed_Asm_32: {
5871 // Shuffle the operands around so the lane index operand is in the
5874 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5875 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5876 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5877 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5878 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5879 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5880 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5882 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5884 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5886 TmpInst.addOperand(Inst.getOperand(1)); // lane
5887 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5888 TmpInst.addOperand(Inst.getOperand(5));
5893 case ARM::VST1LNdAsm_8:
5894 case ARM::VST1LNdAsm_16:
5895 case ARM::VST1LNdAsm_32: {
5897 // Shuffle the operands around so the lane index operand is in the
5900 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5901 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5902 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5903 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5904 TmpInst.addOperand(Inst.getOperand(1)); // lane
5905 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5906 TmpInst.addOperand(Inst.getOperand(5));
5911 case ARM::VST2LNdAsm_8:
5912 case ARM::VST2LNdAsm_16:
5913 case ARM::VST2LNdAsm_32:
5914 case ARM::VST2LNqAsm_16:
5915 case ARM::VST2LNqAsm_32: {
5917 // Shuffle the operands around so the lane index operand is in the
5920 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5921 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5922 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5923 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5924 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5926 TmpInst.addOperand(Inst.getOperand(1)); // lane
5927 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5928 TmpInst.addOperand(Inst.getOperand(5));
5933 case ARM::VST3LNdAsm_8:
5934 case ARM::VST3LNdAsm_16:
5935 case ARM::VST3LNdAsm_32:
5936 case ARM::VST3LNqAsm_16:
5937 case ARM::VST3LNqAsm_32: {
5939 // Shuffle the operands around so the lane index operand is in the
5942 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5943 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5944 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5945 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5946 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5948 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5950 TmpInst.addOperand(Inst.getOperand(1)); // lane
5951 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5952 TmpInst.addOperand(Inst.getOperand(5));
5957 case ARM::VST4LNdAsm_8:
5958 case ARM::VST4LNdAsm_16:
5959 case ARM::VST4LNdAsm_32:
5960 case ARM::VST4LNqAsm_16:
5961 case ARM::VST4LNqAsm_32: {
5963 // Shuffle the operands around so the lane index operand is in the
5966 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5967 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5968 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5969 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5970 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5972 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5974 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5976 TmpInst.addOperand(Inst.getOperand(1)); // lane
5977 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5978 TmpInst.addOperand(Inst.getOperand(5));
5983 // Handle NEON VLD complex aliases.
5984 case ARM::VLD1LNdWB_register_Asm_8:
5985 case ARM::VLD1LNdWB_register_Asm_16:
5986 case ARM::VLD1LNdWB_register_Asm_32: {
5988 // Shuffle the operands around so the lane index operand is in the
5991 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
5992 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5993 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5994 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5995 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5996 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5997 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5998 TmpInst.addOperand(Inst.getOperand(1)); // lane
5999 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6000 TmpInst.addOperand(Inst.getOperand(6));
6005 case ARM::VLD2LNdWB_register_Asm_8:
6006 case ARM::VLD2LNdWB_register_Asm_16:
6007 case ARM::VLD2LNdWB_register_Asm_32:
6008 case ARM::VLD2LNqWB_register_Asm_16:
6009 case ARM::VLD2LNqWB_register_Asm_32: {
6011 // Shuffle the operands around so the lane index operand is in the
6014 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6015 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6016 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6018 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6019 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6020 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6021 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6022 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6023 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6025 TmpInst.addOperand(Inst.getOperand(1)); // lane
6026 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6027 TmpInst.addOperand(Inst.getOperand(6));
6032 case ARM::VLD3LNdWB_register_Asm_8:
6033 case ARM::VLD3LNdWB_register_Asm_16:
6034 case ARM::VLD3LNdWB_register_Asm_32:
6035 case ARM::VLD3LNqWB_register_Asm_16:
6036 case ARM::VLD3LNqWB_register_Asm_32: {
6038 // Shuffle the operands around so the lane index operand is in the
6041 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6042 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6043 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6045 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6047 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6048 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6049 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6050 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6051 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6052 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6054 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6056 TmpInst.addOperand(Inst.getOperand(1)); // lane
6057 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6058 TmpInst.addOperand(Inst.getOperand(6));
6063 case ARM::VLD4LNdWB_register_Asm_8:
6064 case ARM::VLD4LNdWB_register_Asm_16:
6065 case ARM::VLD4LNdWB_register_Asm_32:
6066 case ARM::VLD4LNqWB_register_Asm_16:
6067 case ARM::VLD4LNqWB_register_Asm_32: {
6069 // Shuffle the operands around so the lane index operand is in the
6072 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6073 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6074 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6076 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6078 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6080 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6081 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6082 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6083 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6084 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6085 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6087 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6089 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6091 TmpInst.addOperand(Inst.getOperand(1)); // lane
6092 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6093 TmpInst.addOperand(Inst.getOperand(6));
6098 case ARM::VLD1LNdWB_fixed_Asm_8:
6099 case ARM::VLD1LNdWB_fixed_Asm_16:
6100 case ARM::VLD1LNdWB_fixed_Asm_32: {
6102 // Shuffle the operands around so the lane index operand is in the
6105 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6106 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6107 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6108 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6109 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6110 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6111 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6112 TmpInst.addOperand(Inst.getOperand(1)); // lane
6113 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6114 TmpInst.addOperand(Inst.getOperand(5));
6119 case ARM::VLD2LNdWB_fixed_Asm_8:
6120 case ARM::VLD2LNdWB_fixed_Asm_16:
6121 case ARM::VLD2LNdWB_fixed_Asm_32:
6122 case ARM::VLD2LNqWB_fixed_Asm_16:
6123 case ARM::VLD2LNqWB_fixed_Asm_32: {
6125 // Shuffle the operands around so the lane index operand is in the
6128 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6129 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6130 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6132 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6133 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6134 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6135 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6136 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6137 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6139 TmpInst.addOperand(Inst.getOperand(1)); // lane
6140 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6141 TmpInst.addOperand(Inst.getOperand(5));
6146 case ARM::VLD3LNdWB_fixed_Asm_8:
6147 case ARM::VLD3LNdWB_fixed_Asm_16:
6148 case ARM::VLD3LNdWB_fixed_Asm_32:
6149 case ARM::VLD3LNqWB_fixed_Asm_16:
6150 case ARM::VLD3LNqWB_fixed_Asm_32: {
6152 // Shuffle the operands around so the lane index operand is in the
6155 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6156 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6157 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6159 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6161 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6162 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6163 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6164 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6165 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6166 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6168 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6170 TmpInst.addOperand(Inst.getOperand(1)); // lane
6171 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6172 TmpInst.addOperand(Inst.getOperand(5));
6177 case ARM::VLD4LNdWB_fixed_Asm_8:
6178 case ARM::VLD4LNdWB_fixed_Asm_16:
6179 case ARM::VLD4LNdWB_fixed_Asm_32:
6180 case ARM::VLD4LNqWB_fixed_Asm_16:
6181 case ARM::VLD4LNqWB_fixed_Asm_32: {
6183 // Shuffle the operands around so the lane index operand is in the
6186 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6187 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6188 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6190 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6192 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6194 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6195 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6196 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6197 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6198 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6199 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6201 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6203 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6205 TmpInst.addOperand(Inst.getOperand(1)); // lane
6206 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6207 TmpInst.addOperand(Inst.getOperand(5));
6212 case ARM::VLD1LNdAsm_8:
6213 case ARM::VLD1LNdAsm_16:
6214 case ARM::VLD1LNdAsm_32: {
6216 // Shuffle the operands around so the lane index operand is in the
6219 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6220 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6221 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6222 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6223 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6224 TmpInst.addOperand(Inst.getOperand(1)); // lane
6225 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6226 TmpInst.addOperand(Inst.getOperand(5));
6231 case ARM::VLD2LNdAsm_8:
6232 case ARM::VLD2LNdAsm_16:
6233 case ARM::VLD2LNdAsm_32:
6234 case ARM::VLD2LNqAsm_16:
6235 case ARM::VLD2LNqAsm_32: {
6237 // Shuffle the operands around so the lane index operand is in the
6240 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6241 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6242 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6244 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6245 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6246 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6247 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6249 TmpInst.addOperand(Inst.getOperand(1)); // lane
6250 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6251 TmpInst.addOperand(Inst.getOperand(5));
6256 case ARM::VLD3LNdAsm_8:
6257 case ARM::VLD3LNdAsm_16:
6258 case ARM::VLD3LNdAsm_32:
6259 case ARM::VLD3LNqAsm_16:
6260 case ARM::VLD3LNqAsm_32: {
6262 // Shuffle the operands around so the lane index operand is in the
6265 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6266 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6267 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6269 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6271 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6272 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6273 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6274 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6276 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6278 TmpInst.addOperand(Inst.getOperand(1)); // lane
6279 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6280 TmpInst.addOperand(Inst.getOperand(5));
6285 case ARM::VLD4LNdAsm_8:
6286 case ARM::VLD4LNdAsm_16:
6287 case ARM::VLD4LNdAsm_32:
6288 case ARM::VLD4LNqAsm_16:
6289 case ARM::VLD4LNqAsm_32: {
6291 // Shuffle the operands around so the lane index operand is in the
6294 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6295 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6296 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6298 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6300 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6302 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6303 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6304 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6305 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6307 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6309 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6311 TmpInst.addOperand(Inst.getOperand(1)); // lane
6312 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6313 TmpInst.addOperand(Inst.getOperand(5));
6318 // VLD3DUP single 3-element structure to all lanes instructions.
6319 case ARM::VLD3DUPdAsm_8:
6320 case ARM::VLD3DUPdAsm_16:
6321 case ARM::VLD3DUPdAsm_32:
6322 case ARM::VLD3DUPqAsm_8:
6323 case ARM::VLD3DUPqAsm_16:
6324 case ARM::VLD3DUPqAsm_32: {
6327 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6328 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6329 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6331 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6333 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6334 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6335 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6336 TmpInst.addOperand(Inst.getOperand(4));
6341 case ARM::VLD3DUPdWB_fixed_Asm_8:
6342 case ARM::VLD3DUPdWB_fixed_Asm_16:
6343 case ARM::VLD3DUPdWB_fixed_Asm_32:
6344 case ARM::VLD3DUPqWB_fixed_Asm_8:
6345 case ARM::VLD3DUPqWB_fixed_Asm_16:
6346 case ARM::VLD3DUPqWB_fixed_Asm_32: {
6349 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6350 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6351 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6353 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6355 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6356 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6357 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6358 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6359 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6360 TmpInst.addOperand(Inst.getOperand(4));
6365 case ARM::VLD3DUPdWB_register_Asm_8:
6366 case ARM::VLD3DUPdWB_register_Asm_16:
6367 case ARM::VLD3DUPdWB_register_Asm_32:
6368 case ARM::VLD3DUPqWB_register_Asm_8:
6369 case ARM::VLD3DUPqWB_register_Asm_16:
6370 case ARM::VLD3DUPqWB_register_Asm_32: {
6373 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6374 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6375 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6377 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6379 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6380 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6381 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6382 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6383 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6384 TmpInst.addOperand(Inst.getOperand(5));
6389 // VLD3 multiple 3-element structure instructions.
6390 case ARM::VLD3dAsm_8:
6391 case ARM::VLD3dAsm_16:
6392 case ARM::VLD3dAsm_32:
6393 case ARM::VLD3qAsm_8:
6394 case ARM::VLD3qAsm_16:
6395 case ARM::VLD3qAsm_32: {
6398 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6399 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6400 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6402 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6404 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6405 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6406 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6407 TmpInst.addOperand(Inst.getOperand(4));
6412 case ARM::VLD3dWB_fixed_Asm_8:
6413 case ARM::VLD3dWB_fixed_Asm_16:
6414 case ARM::VLD3dWB_fixed_Asm_32:
6415 case ARM::VLD3qWB_fixed_Asm_8:
6416 case ARM::VLD3qWB_fixed_Asm_16:
6417 case ARM::VLD3qWB_fixed_Asm_32: {
6420 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6421 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6422 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6424 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6426 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6427 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6428 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6429 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6430 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6431 TmpInst.addOperand(Inst.getOperand(4));
6436 case ARM::VLD3dWB_register_Asm_8:
6437 case ARM::VLD3dWB_register_Asm_16:
6438 case ARM::VLD3dWB_register_Asm_32:
6439 case ARM::VLD3qWB_register_Asm_8:
6440 case ARM::VLD3qWB_register_Asm_16:
6441 case ARM::VLD3qWB_register_Asm_32: {
6444 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6445 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6446 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6448 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6450 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6451 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6452 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6453 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6454 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6455 TmpInst.addOperand(Inst.getOperand(5));
6460 // VLD4DUP single 3-element structure to all lanes instructions.
6461 case ARM::VLD4DUPdAsm_8:
6462 case ARM::VLD4DUPdAsm_16:
6463 case ARM::VLD4DUPdAsm_32:
6464 case ARM::VLD4DUPqAsm_8:
6465 case ARM::VLD4DUPqAsm_16:
6466 case ARM::VLD4DUPqAsm_32: {
6469 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6470 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6471 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6473 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6475 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6477 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6478 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6479 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6480 TmpInst.addOperand(Inst.getOperand(4));
6485 case ARM::VLD4DUPdWB_fixed_Asm_8:
6486 case ARM::VLD4DUPdWB_fixed_Asm_16:
6487 case ARM::VLD4DUPdWB_fixed_Asm_32:
6488 case ARM::VLD4DUPqWB_fixed_Asm_8:
6489 case ARM::VLD4DUPqWB_fixed_Asm_16:
6490 case ARM::VLD4DUPqWB_fixed_Asm_32: {
6493 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6494 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6495 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6497 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6499 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6501 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6502 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6503 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6504 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6505 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6506 TmpInst.addOperand(Inst.getOperand(4));
6511 case ARM::VLD4DUPdWB_register_Asm_8:
6512 case ARM::VLD4DUPdWB_register_Asm_16:
6513 case ARM::VLD4DUPdWB_register_Asm_32:
6514 case ARM::VLD4DUPqWB_register_Asm_8:
6515 case ARM::VLD4DUPqWB_register_Asm_16:
6516 case ARM::VLD4DUPqWB_register_Asm_32: {
6519 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6520 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6521 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6523 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6525 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6527 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6528 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6529 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6530 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6531 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6532 TmpInst.addOperand(Inst.getOperand(5));
6537 // VLD4 multiple 4-element structure instructions.
6538 case ARM::VLD4dAsm_8:
6539 case ARM::VLD4dAsm_16:
6540 case ARM::VLD4dAsm_32:
6541 case ARM::VLD4qAsm_8:
6542 case ARM::VLD4qAsm_16:
6543 case ARM::VLD4qAsm_32: {
6546 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6547 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6548 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6550 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6552 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6554 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6555 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6556 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6557 TmpInst.addOperand(Inst.getOperand(4));
6562 case ARM::VLD4dWB_fixed_Asm_8:
6563 case ARM::VLD4dWB_fixed_Asm_16:
6564 case ARM::VLD4dWB_fixed_Asm_32:
6565 case ARM::VLD4qWB_fixed_Asm_8:
6566 case ARM::VLD4qWB_fixed_Asm_16:
6567 case ARM::VLD4qWB_fixed_Asm_32: {
6570 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6571 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6572 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6574 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6576 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6578 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6579 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6580 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6581 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6582 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6583 TmpInst.addOperand(Inst.getOperand(4));
6588 case ARM::VLD4dWB_register_Asm_8:
6589 case ARM::VLD4dWB_register_Asm_16:
6590 case ARM::VLD4dWB_register_Asm_32:
6591 case ARM::VLD4qWB_register_Asm_8:
6592 case ARM::VLD4qWB_register_Asm_16:
6593 case ARM::VLD4qWB_register_Asm_32: {
6596 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6597 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6598 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6600 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6602 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6604 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6605 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6606 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6607 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6608 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6609 TmpInst.addOperand(Inst.getOperand(5));
6614 // VST3 multiple 3-element structure instructions.
6615 case ARM::VST3dAsm_8:
6616 case ARM::VST3dAsm_16:
6617 case ARM::VST3dAsm_32:
6618 case ARM::VST3qAsm_8:
6619 case ARM::VST3qAsm_16:
6620 case ARM::VST3qAsm_32: {
6623 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6624 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6625 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6626 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6627 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6629 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6631 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6632 TmpInst.addOperand(Inst.getOperand(4));
6637 case ARM::VST3dWB_fixed_Asm_8:
6638 case ARM::VST3dWB_fixed_Asm_16:
6639 case ARM::VST3dWB_fixed_Asm_32:
6640 case ARM::VST3qWB_fixed_Asm_8:
6641 case ARM::VST3qWB_fixed_Asm_16:
6642 case ARM::VST3qWB_fixed_Asm_32: {
6645 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6646 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6647 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6648 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6649 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6650 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6651 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6653 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6655 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6656 TmpInst.addOperand(Inst.getOperand(4));
6661 case ARM::VST3dWB_register_Asm_8:
6662 case ARM::VST3dWB_register_Asm_16:
6663 case ARM::VST3dWB_register_Asm_32:
6664 case ARM::VST3qWB_register_Asm_8:
6665 case ARM::VST3qWB_register_Asm_16:
6666 case ARM::VST3qWB_register_Asm_32: {
6669 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6670 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6671 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6672 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6673 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6674 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6675 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6677 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6679 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6680 TmpInst.addOperand(Inst.getOperand(5));
6685 // VST4 multiple 3-element structure instructions.
6686 case ARM::VST4dAsm_8:
6687 case ARM::VST4dAsm_16:
6688 case ARM::VST4dAsm_32:
6689 case ARM::VST4qAsm_8:
6690 case ARM::VST4qAsm_16:
6691 case ARM::VST4qAsm_32: {
6694 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6695 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6696 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6697 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6698 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6700 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6702 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6704 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6705 TmpInst.addOperand(Inst.getOperand(4));
6710 case ARM::VST4dWB_fixed_Asm_8:
6711 case ARM::VST4dWB_fixed_Asm_16:
6712 case ARM::VST4dWB_fixed_Asm_32:
6713 case ARM::VST4qWB_fixed_Asm_8:
6714 case ARM::VST4qWB_fixed_Asm_16:
6715 case ARM::VST4qWB_fixed_Asm_32: {
6718 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6719 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6720 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6721 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6722 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6723 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6724 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6726 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6728 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6730 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6731 TmpInst.addOperand(Inst.getOperand(4));
6736 case ARM::VST4dWB_register_Asm_8:
6737 case ARM::VST4dWB_register_Asm_16:
6738 case ARM::VST4dWB_register_Asm_32:
6739 case ARM::VST4qWB_register_Asm_8:
6740 case ARM::VST4qWB_register_Asm_16:
6741 case ARM::VST4qWB_register_Asm_32: {
6744 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6745 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6746 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6747 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6748 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6749 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6750 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6752 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6754 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6756 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6757 TmpInst.addOperand(Inst.getOperand(5));
6762 // Handle encoding choice for the shift-immediate instructions.
6765 case ARM::t2ASRri: {
6766 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6767 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6768 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
6769 !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
6770 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
6772 switch (Inst.getOpcode()) {
6773 default: llvm_unreachable("unexpected opcode");
6774 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
6775 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
6776 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
6778 // The Thumb1 operands aren't in the same order. Awesome, eh?
6780 TmpInst.setOpcode(NewOpc);
6781 TmpInst.addOperand(Inst.getOperand(0));
6782 TmpInst.addOperand(Inst.getOperand(5));
6783 TmpInst.addOperand(Inst.getOperand(1));
6784 TmpInst.addOperand(Inst.getOperand(2));
6785 TmpInst.addOperand(Inst.getOperand(3));
6786 TmpInst.addOperand(Inst.getOperand(4));
6793 // Handle the Thumb2 mode MOV complex aliases.
6795 case ARM::t2MOVSsr: {
6796 // Which instruction to expand to depends on the CCOut operand and
6797 // whether we're in an IT block if the register operands are low
6799 bool isNarrow = false;
6800 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6801 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6802 isARMLowRegister(Inst.getOperand(2).getReg()) &&
6803 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6804 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
6808 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
6809 default: llvm_unreachable("unexpected opcode!");
6810 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
6811 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
6812 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
6813 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
6815 TmpInst.setOpcode(newOpc);
6816 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6818 TmpInst.addOperand(MCOperand::CreateReg(
6819 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6820 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6821 TmpInst.addOperand(Inst.getOperand(2)); // Rm
6822 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6823 TmpInst.addOperand(Inst.getOperand(5));
6825 TmpInst.addOperand(MCOperand::CreateReg(
6826 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6831 case ARM::t2MOVSsi: {
6832 // Which instruction to expand to depends on the CCOut operand and
6833 // whether we're in an IT block if the register operands are low
6835 bool isNarrow = false;
6836 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6837 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6838 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
6842 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
6843 default: llvm_unreachable("unexpected opcode!");
6844 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
6845 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
6846 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
6847 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
6848 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
6850 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
6851 if (Amount == 32) Amount = 0;
6852 TmpInst.setOpcode(newOpc);
6853 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6855 TmpInst.addOperand(MCOperand::CreateReg(
6856 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6857 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6858 if (newOpc != ARM::t2RRX)
6859 TmpInst.addOperand(MCOperand::CreateImm(Amount));
6860 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6861 TmpInst.addOperand(Inst.getOperand(4));
6863 TmpInst.addOperand(MCOperand::CreateReg(
6864 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6868 // Handle the ARM mode MOV complex aliases.
6873 ARM_AM::ShiftOpc ShiftTy;
6874 switch(Inst.getOpcode()) {
6875 default: llvm_unreachable("unexpected opcode!");
6876 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
6877 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
6878 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
6879 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
6881 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
6883 TmpInst.setOpcode(ARM::MOVsr);
6884 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6885 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6886 TmpInst.addOperand(Inst.getOperand(2)); // Rm
6887 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6888 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6889 TmpInst.addOperand(Inst.getOperand(4));
6890 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6898 ARM_AM::ShiftOpc ShiftTy;
6899 switch(Inst.getOpcode()) {
6900 default: llvm_unreachable("unexpected opcode!");
6901 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
6902 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
6903 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
6904 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
6906 // A shift by zero is a plain MOVr, not a MOVsi.
6907 unsigned Amt = Inst.getOperand(2).getImm();
6908 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
6909 // A shift by 32 should be encoded as 0 when permitted
6910 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
6912 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
6914 TmpInst.setOpcode(Opc);
6915 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6916 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6917 if (Opc == ARM::MOVsi)
6918 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6919 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6920 TmpInst.addOperand(Inst.getOperand(4));
6921 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6926 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
6928 TmpInst.setOpcode(ARM::MOVsi);
6929 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6930 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6931 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6932 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6933 TmpInst.addOperand(Inst.getOperand(3));
6934 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
6938 case ARM::t2LDMIA_UPD: {
6939 // If this is a load of a single register, then we should use
6940 // a post-indexed LDR instruction instead, per the ARM ARM.
6941 if (Inst.getNumOperands() != 5)
6944 TmpInst.setOpcode(ARM::t2LDR_POST);
6945 TmpInst.addOperand(Inst.getOperand(4)); // Rt
6946 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6947 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6948 TmpInst.addOperand(MCOperand::CreateImm(4));
6949 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6950 TmpInst.addOperand(Inst.getOperand(3));
6954 case ARM::t2STMDB_UPD: {
6955 // If this is a store of a single register, then we should use
6956 // a pre-indexed STR instruction instead, per the ARM ARM.
6957 if (Inst.getNumOperands() != 5)
6960 TmpInst.setOpcode(ARM::t2STR_PRE);
6961 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6962 TmpInst.addOperand(Inst.getOperand(4)); // Rt
6963 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6964 TmpInst.addOperand(MCOperand::CreateImm(-4));
6965 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6966 TmpInst.addOperand(Inst.getOperand(3));
6970 case ARM::LDMIA_UPD:
6971 // If this is a load of a single register via a 'pop', then we should use
6972 // a post-indexed LDR instruction instead, per the ARM ARM.
6973 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
6974 Inst.getNumOperands() == 5) {
6976 TmpInst.setOpcode(ARM::LDR_POST_IMM);
6977 TmpInst.addOperand(Inst.getOperand(4)); // Rt
6978 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6979 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6980 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
6981 TmpInst.addOperand(MCOperand::CreateImm(4));
6982 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6983 TmpInst.addOperand(Inst.getOperand(3));
6988 case ARM::STMDB_UPD:
6989 // If this is a store of a single register via a 'push', then we should use
6990 // a pre-indexed STR instruction instead, per the ARM ARM.
6991 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
6992 Inst.getNumOperands() == 5) {
6994 TmpInst.setOpcode(ARM::STR_PRE_IMM);
6995 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6996 TmpInst.addOperand(Inst.getOperand(4)); // Rt
6997 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
6998 TmpInst.addOperand(MCOperand::CreateImm(-4));
6999 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7000 TmpInst.addOperand(Inst.getOperand(3));
7004 case ARM::t2ADDri12:
7005 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7006 // mnemonic was used (not "addw"), encoding T3 is preferred.
7007 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
7008 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7010 Inst.setOpcode(ARM::t2ADDri);
7011 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7013 case ARM::t2SUBri12:
7014 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7015 // mnemonic was used (not "subw"), encoding T3 is preferred.
7016 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7017 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7019 Inst.setOpcode(ARM::t2SUBri);
7020 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7023 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7024 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7025 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7026 // to encoding T1 if <Rd> is omitted."
7027 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7028 Inst.setOpcode(ARM::tADDi3);
7033 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7034 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7035 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7036 // to encoding T1 if <Rd> is omitted."
7037 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7038 Inst.setOpcode(ARM::tSUBi3);
7043 case ARM::t2SUBri: {
7044 // If the destination and first source operand are the same, and
7045 // the flags are compatible with the current IT status, use encoding T2
7046 // instead of T3. For compatibility with the system 'as'. Make sure the
7047 // wide encoding wasn't explicit.
7048 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7049 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7050 (unsigned)Inst.getOperand(2).getImm() > 255 ||
7051 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7052 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7053 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7054 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7057 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7058 ARM::tADDi8 : ARM::tSUBi8);
7059 TmpInst.addOperand(Inst.getOperand(0));
7060 TmpInst.addOperand(Inst.getOperand(5));
7061 TmpInst.addOperand(Inst.getOperand(0));
7062 TmpInst.addOperand(Inst.getOperand(2));
7063 TmpInst.addOperand(Inst.getOperand(3));
7064 TmpInst.addOperand(Inst.getOperand(4));
7068 case ARM::t2ADDrr: {
7069 // If the destination and first source operand are the same, and
7070 // there's no setting of the flags, use encoding T2 instead of T3.
7071 // Note that this is only for ADD, not SUB. This mirrors the system
7072 // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7073 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7074 Inst.getOperand(5).getReg() != 0 ||
7075 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7076 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7079 TmpInst.setOpcode(ARM::tADDhirr);
7080 TmpInst.addOperand(Inst.getOperand(0));
7081 TmpInst.addOperand(Inst.getOperand(0));
7082 TmpInst.addOperand(Inst.getOperand(2));
7083 TmpInst.addOperand(Inst.getOperand(3));
7084 TmpInst.addOperand(Inst.getOperand(4));
7088 case ARM::tADDrSP: {
7089 // If the non-SP source operand and the destination operand are not the
7090 // same, we need to use the 32-bit encoding if it's available.
7091 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7092 Inst.setOpcode(ARM::t2ADDrr);
7093 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7099 // A Thumb conditional branch outside of an IT block is a tBcc.
7100 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7101 Inst.setOpcode(ARM::tBcc);
7106 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7107 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7108 Inst.setOpcode(ARM::t2Bcc);
7113 // If the conditional is AL or we're in an IT block, we really want t2B.
7114 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7115 Inst.setOpcode(ARM::t2B);
7120 // If the conditional is AL, we really want tB.
7121 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7122 Inst.setOpcode(ARM::tB);
7127 // If the register list contains any high registers, or if the writeback
7128 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7129 // instead if we're in Thumb2. Otherwise, this should have generated
7130 // an error in validateInstruction().
7131 unsigned Rn = Inst.getOperand(0).getReg();
7132 bool hasWritebackToken =
7133 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7134 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7135 bool listContainsBase;
7136 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7137 (!listContainsBase && !hasWritebackToken) ||
7138 (listContainsBase && hasWritebackToken)) {
7139 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7140 assert (isThumbTwo());
7141 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7142 // If we're switching to the updating version, we need to insert
7143 // the writeback tied operand.
7144 if (hasWritebackToken)
7145 Inst.insert(Inst.begin(),
7146 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7151 case ARM::tSTMIA_UPD: {
7152 // If the register list contains any high registers, we need to use
7153 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7154 // should have generated an error in validateInstruction().
7155 unsigned Rn = Inst.getOperand(0).getReg();
7156 bool listContainsBase;
7157 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7158 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7159 assert (isThumbTwo());
7160 Inst.setOpcode(ARM::t2STMIA_UPD);
7166 bool listContainsBase;
7167 // If the register list contains any high registers, we need to use
7168 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7169 // should have generated an error in validateInstruction().
7170 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7172 assert (isThumbTwo());
7173 Inst.setOpcode(ARM::t2LDMIA_UPD);
7174 // Add the base register and writeback operands.
7175 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7176 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7180 bool listContainsBase;
7181 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7183 assert (isThumbTwo());
7184 Inst.setOpcode(ARM::t2STMDB_UPD);
7185 // Add the base register and writeback operands.
7186 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7187 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7191 // If we can use the 16-bit encoding and the user didn't explicitly
7192 // request the 32-bit variant, transform it here.
7193 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7194 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7195 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7196 Inst.getOperand(4).getReg() == ARM::CPSR) ||
7197 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7198 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7199 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7200 // The operands aren't in the same order for tMOVi8...
7202 TmpInst.setOpcode(ARM::tMOVi8);
7203 TmpInst.addOperand(Inst.getOperand(0));
7204 TmpInst.addOperand(Inst.getOperand(4));
7205 TmpInst.addOperand(Inst.getOperand(1));
7206 TmpInst.addOperand(Inst.getOperand(2));
7207 TmpInst.addOperand(Inst.getOperand(3));
7214 // If we can use the 16-bit encoding and the user didn't explicitly
7215 // request the 32-bit variant, transform it here.
7216 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7217 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7218 Inst.getOperand(2).getImm() == ARMCC::AL &&
7219 Inst.getOperand(4).getReg() == ARM::CPSR &&
7220 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7221 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7222 // The operands aren't the same for tMOV[S]r... (no cc_out)
7224 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7225 TmpInst.addOperand(Inst.getOperand(0));
7226 TmpInst.addOperand(Inst.getOperand(1));
7227 TmpInst.addOperand(Inst.getOperand(2));
7228 TmpInst.addOperand(Inst.getOperand(3));
7238 // If we can use the 16-bit encoding and the user didn't explicitly
7239 // request the 32-bit variant, transform it here.
7240 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7241 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7242 Inst.getOperand(2).getImm() == 0 &&
7243 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7244 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7246 switch (Inst.getOpcode()) {
7247 default: llvm_unreachable("Illegal opcode!");
7248 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7249 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7250 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7251 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7253 // The operands aren't the same for thumb1 (no rotate operand).
7255 TmpInst.setOpcode(NewOpc);
7256 TmpInst.addOperand(Inst.getOperand(0));
7257 TmpInst.addOperand(Inst.getOperand(1));
7258 TmpInst.addOperand(Inst.getOperand(3));
7259 TmpInst.addOperand(Inst.getOperand(4));
7266 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7267 // rrx shifts and asr/lsr of #32 is encoded as 0
7268 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7270 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7271 // Shifting by zero is accepted as a vanilla 'MOVr'
7273 TmpInst.setOpcode(ARM::MOVr);
7274 TmpInst.addOperand(Inst.getOperand(0));
7275 TmpInst.addOperand(Inst.getOperand(1));
7276 TmpInst.addOperand(Inst.getOperand(3));
7277 TmpInst.addOperand(Inst.getOperand(4));
7278 TmpInst.addOperand(Inst.getOperand(5));
7291 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7292 if (SOpc == ARM_AM::rrx) return false;
7293 switch (Inst.getOpcode()) {
7294 default: llvm_unreachable("unexpected opcode!");
7295 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7296 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7297 case ARM::EORrsi: newOpc = ARM::EORrr; break;
7298 case ARM::BICrsi: newOpc = ARM::BICrr; break;
7299 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7300 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7302 // If the shift is by zero, use the non-shifted instruction definition.
7303 // The exception is for right shifts, where 0 == 32
7304 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7305 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7307 TmpInst.setOpcode(newOpc);
7308 TmpInst.addOperand(Inst.getOperand(0));
7309 TmpInst.addOperand(Inst.getOperand(1));
7310 TmpInst.addOperand(Inst.getOperand(2));
7311 TmpInst.addOperand(Inst.getOperand(4));
7312 TmpInst.addOperand(Inst.getOperand(5));
7313 TmpInst.addOperand(Inst.getOperand(6));
7321 // The mask bits for all but the first condition are represented as
7322 // the low bit of the condition code value implies 't'. We currently
7323 // always have 1 implies 't', so XOR toggle the bits if the low bit
7324 // of the condition code is zero.
7325 MCOperand &MO = Inst.getOperand(1);
7326 unsigned Mask = MO.getImm();
7327 unsigned OrigMask = Mask;
7328 unsigned TZ = CountTrailingZeros_32(Mask);
7329 if ((Inst.getOperand(0).getImm() & 1) == 0) {
7330 assert(Mask && TZ <= 3 && "illegal IT mask value!");
7331 for (unsigned i = 3; i != TZ; --i)
7336 // Set up the IT block state according to the IT instruction we just
7338 assert(!inITBlock() && "nested IT blocks?!");
7339 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7340 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7341 ITState.CurPosition = 0;
7342 ITState.FirstCond = true;
7352 // Assemblers should use the narrow encodings of these instructions when permissible.
7353 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7354 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7355 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7356 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7357 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7358 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7359 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7361 switch (Inst.getOpcode()) {
7362 default: llvm_unreachable("unexpected opcode");
7363 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7364 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7365 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7366 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7367 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7368 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7371 TmpInst.setOpcode(NewOpc);
7372 TmpInst.addOperand(Inst.getOperand(0));
7373 TmpInst.addOperand(Inst.getOperand(5));
7374 TmpInst.addOperand(Inst.getOperand(1));
7375 TmpInst.addOperand(Inst.getOperand(2));
7376 TmpInst.addOperand(Inst.getOperand(3));
7377 TmpInst.addOperand(Inst.getOperand(4));
7388 // Assemblers should use the narrow encodings of these instructions when permissible.
7389 // These instructions are special in that they are commutable, so shorter encodings
7390 // are available more often.
7391 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7392 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7393 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7394 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7395 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7396 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7397 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7398 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7400 switch (Inst.getOpcode()) {
7401 default: llvm_unreachable("unexpected opcode");
7402 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7403 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7404 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7405 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7408 TmpInst.setOpcode(NewOpc);
7409 TmpInst.addOperand(Inst.getOperand(0));
7410 TmpInst.addOperand(Inst.getOperand(5));
7411 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7412 TmpInst.addOperand(Inst.getOperand(1));
7413 TmpInst.addOperand(Inst.getOperand(2));
7415 TmpInst.addOperand(Inst.getOperand(2));
7416 TmpInst.addOperand(Inst.getOperand(1));
7418 TmpInst.addOperand(Inst.getOperand(3));
7419 TmpInst.addOperand(Inst.getOperand(4));
7429 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7430 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7431 // suffix depending on whether they're in an IT block or not.
7432 unsigned Opc = Inst.getOpcode();
7433 const MCInstrDesc &MCID = getInstDesc(Opc);
7434 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7435 assert(MCID.hasOptionalDef() &&
7436 "optionally flag setting instruction missing optional def operand");
7437 assert(MCID.NumOperands == Inst.getNumOperands() &&
7438 "operand count mismatch!");
7439 // Find the optional-def operand (cc_out).
7442 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7445 // If we're parsing Thumb1, reject it completely.
7446 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7447 return Match_MnemonicFail;
7448 // If we're parsing Thumb2, which form is legal depends on whether we're
7450 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7452 return Match_RequiresITBlock;
7453 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7455 return Match_RequiresNotITBlock;
7457 // Some high-register supporting Thumb1 encodings only allow both registers
7458 // to be from r0-r7 when in Thumb2.
7459 else if (Opc == ARM::tADDhirr && isThumbOne() &&
7460 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7461 isARMLowRegister(Inst.getOperand(2).getReg()))
7462 return Match_RequiresThumb2;
7463 // Others only require ARMv6 or later.
7464 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7465 isARMLowRegister(Inst.getOperand(0).getReg()) &&
7466 isARMLowRegister(Inst.getOperand(1).getReg()))
7467 return Match_RequiresV6;
7468 return Match_Success;
7471 static const char *getSubtargetFeatureName(unsigned Val);
7473 MatchAndEmitInstruction(SMLoc IDLoc,
7474 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
7478 unsigned MatchResult;
7479 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
7480 switch (MatchResult) {
7483 // Context sensitive operand constraints aren't handled by the matcher,
7484 // so check them here.
7485 if (validateInstruction(Inst, Operands)) {
7486 // Still progress the IT block, otherwise one wrong condition causes
7487 // nasty cascading errors.
7488 forwardITPosition();
7492 // Some instructions need post-processing to, for example, tweak which
7493 // encoding is selected. Loop on it while changes happen so the
7494 // individual transformations can chain off each other. E.g.,
7495 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
7496 while (processInstruction(Inst, Operands))
7499 // Only move forward at the very end so that everything in validate
7500 // and process gets a consistent answer about whether we're in an IT
7502 forwardITPosition();
7504 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7505 // doesn't actually encode.
7506 if (Inst.getOpcode() == ARM::ITasm)
7510 Out.EmitInstruction(Inst);
7512 case Match_MissingFeature: {
7513 assert(ErrorInfo && "Unknown missing feature!");
7514 // Special case the error message for the very common case where only
7515 // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
7516 std::string Msg = "instruction requires:";
7518 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
7519 if (ErrorInfo & Mask) {
7521 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
7525 return Error(IDLoc, Msg);
7527 case Match_InvalidOperand: {
7528 SMLoc ErrorLoc = IDLoc;
7529 if (ErrorInfo != ~0U) {
7530 if (ErrorInfo >= Operands.size())
7531 return Error(IDLoc, "too few operands for instruction");
7533 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7534 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7537 return Error(ErrorLoc, "invalid operand for instruction");
7539 case Match_MnemonicFail:
7540 return Error(IDLoc, "invalid instruction",
7541 ((ARMOperand*)Operands[0])->getLocRange());
7542 case Match_ConversionFail:
7543 // The converter function will have already emitted a diagnostic.
7545 case Match_RequiresNotITBlock:
7546 return Error(IDLoc, "flag setting instruction only valid outside IT block");
7547 case Match_RequiresITBlock:
7548 return Error(IDLoc, "instruction only valid inside IT block");
7549 case Match_RequiresV6:
7550 return Error(IDLoc, "instruction variant requires ARMv6 or later");
7551 case Match_RequiresThumb2:
7552 return Error(IDLoc, "instruction variant requires Thumb2");
7553 case Match_ImmRange0_15: {
7554 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7555 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7556 return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
7560 llvm_unreachable("Implement any new match types added!");
7563 /// parseDirective parses the arm specific directives
7564 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
7565 StringRef IDVal = DirectiveID.getIdentifier();
7566 if (IDVal == ".word")
7567 return parseDirectiveWord(4, DirectiveID.getLoc());
7568 else if (IDVal == ".thumb")
7569 return parseDirectiveThumb(DirectiveID.getLoc());
7570 else if (IDVal == ".arm")
7571 return parseDirectiveARM(DirectiveID.getLoc());
7572 else if (IDVal == ".thumb_func")
7573 return parseDirectiveThumbFunc(DirectiveID.getLoc());
7574 else if (IDVal == ".code")
7575 return parseDirectiveCode(DirectiveID.getLoc());
7576 else if (IDVal == ".syntax")
7577 return parseDirectiveSyntax(DirectiveID.getLoc());
7578 else if (IDVal == ".unreq")
7579 return parseDirectiveUnreq(DirectiveID.getLoc());
7580 else if (IDVal == ".arch")
7581 return parseDirectiveArch(DirectiveID.getLoc());
7582 else if (IDVal == ".eabi_attribute")
7583 return parseDirectiveEabiAttr(DirectiveID.getLoc());
7587 /// parseDirectiveWord
7588 /// ::= .word [ expression (, expression)* ]
7589 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
7590 if (getLexer().isNot(AsmToken::EndOfStatement)) {
7592 const MCExpr *Value;
7593 if (getParser().ParseExpression(Value))
7596 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
7598 if (getLexer().is(AsmToken::EndOfStatement))
7601 // FIXME: Improve diagnostic.
7602 if (getLexer().isNot(AsmToken::Comma))
7603 return Error(L, "unexpected token in directive");
7612 /// parseDirectiveThumb
7614 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
7615 if (getLexer().isNot(AsmToken::EndOfStatement))
7616 return Error(L, "unexpected token in directive");
7621 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7625 /// parseDirectiveARM
7627 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
7628 if (getLexer().isNot(AsmToken::EndOfStatement))
7629 return Error(L, "unexpected token in directive");
7634 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7638 /// parseDirectiveThumbFunc
7639 /// ::= .thumbfunc symbol_name
7640 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
7641 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
7642 bool isMachO = MAI.hasSubsectionsViaSymbols();
7644 bool needFuncName = true;
7646 // Darwin asm has (optionally) function name after .thumb_func direction
7649 const AsmToken &Tok = Parser.getTok();
7650 if (Tok.isNot(AsmToken::EndOfStatement)) {
7651 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
7652 return Error(L, "unexpected token in .thumb_func directive");
7653 Name = Tok.getIdentifier();
7654 Parser.Lex(); // Consume the identifier token.
7655 needFuncName = false;
7659 if (getLexer().isNot(AsmToken::EndOfStatement))
7660 return Error(L, "unexpected token in directive");
7662 // Eat the end of statement and any blank lines that follow.
7663 while (getLexer().is(AsmToken::EndOfStatement))
7666 // FIXME: assuming function name will be the line following .thumb_func
7667 // We really should be checking the next symbol definition even if there's
7668 // stuff in between.
7670 Name = Parser.getTok().getIdentifier();
7673 // Mark symbol as a thumb symbol.
7674 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
7675 getParser().getStreamer().EmitThumbFunc(Func);
7679 /// parseDirectiveSyntax
7680 /// ::= .syntax unified | divided
7681 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
7682 const AsmToken &Tok = Parser.getTok();
7683 if (Tok.isNot(AsmToken::Identifier))
7684 return Error(L, "unexpected token in .syntax directive");
7685 StringRef Mode = Tok.getString();
7686 if (Mode == "unified" || Mode == "UNIFIED")
7688 else if (Mode == "divided" || Mode == "DIVIDED")
7689 return Error(L, "'.syntax divided' arm asssembly not supported");
7691 return Error(L, "unrecognized syntax mode in .syntax directive");
7693 if (getLexer().isNot(AsmToken::EndOfStatement))
7694 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7697 // TODO tell the MC streamer the mode
7698 // getParser().getStreamer().Emit???();
7702 /// parseDirectiveCode
7703 /// ::= .code 16 | 32
7704 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
7705 const AsmToken &Tok = Parser.getTok();
7706 if (Tok.isNot(AsmToken::Integer))
7707 return Error(L, "unexpected token in .code directive");
7708 int64_t Val = Parser.getTok().getIntVal();
7714 return Error(L, "invalid operand to .code directive");
7716 if (getLexer().isNot(AsmToken::EndOfStatement))
7717 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7723 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7727 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7733 /// parseDirectiveReq
7734 /// ::= name .req registername
7735 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
7736 Parser.Lex(); // Eat the '.req' token.
7738 SMLoc SRegLoc, ERegLoc;
7739 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
7740 Parser.EatToEndOfStatement();
7741 return Error(SRegLoc, "register name expected");
7744 // Shouldn't be anything else.
7745 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
7746 Parser.EatToEndOfStatement();
7747 return Error(Parser.getTok().getLoc(),
7748 "unexpected input in .req directive.");
7751 Parser.Lex(); // Consume the EndOfStatement
7753 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg)
7754 return Error(SRegLoc, "redefinition of '" + Name +
7755 "' does not match original.");
7760 /// parseDirectiveUneq
7761 /// ::= .unreq registername
7762 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
7763 if (Parser.getTok().isNot(AsmToken::Identifier)) {
7764 Parser.EatToEndOfStatement();
7765 return Error(L, "unexpected input in .unreq directive.");
7767 RegisterReqs.erase(Parser.getTok().getIdentifier());
7768 Parser.Lex(); // Eat the identifier.
7772 /// parseDirectiveArch
7774 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
7778 /// parseDirectiveEabiAttr
7779 /// ::= .eabi_attribute int, int
7780 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
7784 extern "C" void LLVMInitializeARMAsmLexer();
7786 /// Force static initialization.
7787 extern "C" void LLVMInitializeARMAsmParser() {
7788 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
7789 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
7790 LLVMInitializeARMAsmLexer();
7793 #define GET_REGISTER_MATCHER
7794 #define GET_SUBTARGET_FEATURE_NAME
7795 #define GET_MATCHER_IMPLEMENTATION
7796 #include "ARMGenAsmMatcher.inc"