1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMSubtarget.h"
12 #include "llvm/MC/MCParser/MCAsmLexer.h"
13 #include "llvm/MC/MCParser/MCAsmParser.h"
14 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
15 #include "llvm/MC/MCStreamer.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/Target/TargetRegistry.h"
19 #include "llvm/Target/TargetAsmParser.h"
20 #include "llvm/Support/Compiler.h"
21 #include "llvm/Support/SourceMgr.h"
22 #include "llvm/Support/raw_ostream.h"
23 #include "llvm/ADT/OwningPtr.h"
24 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/ADT/StringSwitch.h"
26 #include "llvm/ADT/Twine.h"
32 // The shift types for register controlled shifts in arm memory addressing
41 class ARMAsmParser : public TargetAsmParser {
46 MCAsmParser &getParser() const { return Parser; }
48 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
50 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
52 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
54 bool MaybeParseRegister(OwningPtr<ARMOperand> &Op, bool ParseWriteBack);
56 bool ParseRegisterList(OwningPtr<ARMOperand> &Op);
58 bool ParseMemory(OwningPtr<ARMOperand> &Op);
60 bool ParseMemoryOffsetReg(bool &Negative,
61 bool &OffsetRegShifted,
62 enum ShiftType &ShiftType,
63 const MCExpr *&ShiftAmount,
64 const MCExpr *&Offset,
69 bool ParseShift(enum ShiftType &St, const MCExpr *&ShiftAmount, SMLoc &E);
71 bool ParseOperand(OwningPtr<ARMOperand> &Op);
73 bool ParseDirectiveWord(unsigned Size, SMLoc L);
75 bool ParseDirectiveThumb(SMLoc L);
77 bool ParseDirectiveThumbFunc(SMLoc L);
79 bool ParseDirectiveCode(SMLoc L);
81 bool ParseDirectiveSyntax(SMLoc L);
83 bool MatchInstruction(SMLoc IDLoc,
84 const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
87 if (MatchInstructionImpl(Operands, Inst, ErrorInfo) == Match_Success)
90 // FIXME: We should give nicer diagnostics about the exact failure.
91 Error(IDLoc, "unrecognized instruction");
96 /// @name Auto-generated Match Functions
99 #define GET_ASSEMBLER_HEADER
100 #include "ARMGenAsmMatcher.inc"
106 ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
107 : TargetAsmParser(T), Parser(_Parser), TM(_TM) {}
109 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
110 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
112 virtual bool ParseDirective(AsmToken DirectiveID);
115 /// ARMOperand - Instances of this class represent a parsed ARM machine
117 struct ARMOperand : public MCParsedAsmOperand {
129 SMLoc StartLoc, EndLoc;
133 ARMCC::CondCodes Val;
150 // This is for all forms of ARM address expressions
153 unsigned OffsetRegNum; // used when OffsetIsReg is true
154 const MCExpr *Offset; // used when OffsetIsReg is false
155 const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
156 enum ShiftType ShiftType; // used when OffsetRegShifted is true
158 OffsetRegShifted : 1, // only used when OffsetIsReg is true
162 Negative : 1, // only used when OffsetIsReg is true
168 //ARMOperand(KindTy K, SMLoc S, SMLoc E)
169 // : Kind(K), StartLoc(S), EndLoc(E) {}
171 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
173 StartLoc = o.StartLoc;
194 /// getStartLoc - Get the location of the first token of this operand.
195 SMLoc getStartLoc() const { return StartLoc; }
196 /// getEndLoc - Get the location of the last token of this operand.
197 SMLoc getEndLoc() const { return EndLoc; }
199 ARMCC::CondCodes getCondCode() const {
200 assert(Kind == CondCode && "Invalid access!");
204 StringRef getToken() const {
205 assert(Kind == Token && "Invalid access!");
206 return StringRef(Tok.Data, Tok.Length);
209 unsigned getReg() const {
210 assert(Kind == Register && "Invalid access!");
214 const MCExpr *getImm() const {
215 assert(Kind == Immediate && "Invalid access!");
219 bool isCondCode() const { return Kind == CondCode; }
221 bool isImm() const { return Kind == Immediate; }
223 bool isReg() const { return Kind == Register; }
225 bool isToken() const {return Kind == Token; }
227 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
228 // Add as immediates when possible.
229 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
230 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
232 Inst.addOperand(MCOperand::CreateExpr(Expr));
235 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
236 assert(N == 2 && "Invalid number of operands!");
237 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
238 // FIXME: What belongs here?
239 Inst.addOperand(MCOperand::CreateReg(0));
242 void addRegOperands(MCInst &Inst, unsigned N) const {
243 assert(N == 1 && "Invalid number of operands!");
244 Inst.addOperand(MCOperand::CreateReg(getReg()));
247 void addImmOperands(MCInst &Inst, unsigned N) const {
248 assert(N == 1 && "Invalid number of operands!");
249 addExpr(Inst, getImm());
252 virtual void dump(raw_ostream &OS) const;
254 static void CreateCondCode(OwningPtr<ARMOperand> &Op, ARMCC::CondCodes CC,
256 Op.reset(new ARMOperand);
263 static void CreateToken(OwningPtr<ARMOperand> &Op, StringRef Str,
265 Op.reset(new ARMOperand);
267 Op->Tok.Data = Str.data();
268 Op->Tok.Length = Str.size();
273 static void CreateReg(OwningPtr<ARMOperand> &Op, unsigned RegNum,
274 bool Writeback, SMLoc S, SMLoc E) {
275 Op.reset(new ARMOperand);
277 Op->Reg.RegNum = RegNum;
278 Op->Reg.Writeback = Writeback;
284 static void CreateImm(OwningPtr<ARMOperand> &Op, const MCExpr *Val,
286 Op.reset(new ARMOperand);
287 Op->Kind = Immediate;
294 static void CreateMem(OwningPtr<ARMOperand> &Op,
295 unsigned BaseRegNum, bool OffsetIsReg,
296 const MCExpr *Offset, unsigned OffsetRegNum,
297 bool OffsetRegShifted, enum ShiftType ShiftType,
298 const MCExpr *ShiftAmount, bool Preindexed,
299 bool Postindexed, bool Negative, bool Writeback,
301 Op.reset(new ARMOperand);
303 Op->Mem.BaseRegNum = BaseRegNum;
304 Op->Mem.OffsetIsReg = OffsetIsReg;
305 Op->Mem.Offset = Offset;
306 Op->Mem.OffsetRegNum = OffsetRegNum;
307 Op->Mem.OffsetRegShifted = OffsetRegShifted;
308 Op->Mem.ShiftType = ShiftType;
309 Op->Mem.ShiftAmount = ShiftAmount;
310 Op->Mem.Preindexed = Preindexed;
311 Op->Mem.Postindexed = Postindexed;
312 Op->Mem.Negative = Negative;
313 Op->Mem.Writeback = Writeback;
320 } // end anonymous namespace.
322 void ARMOperand::dump(raw_ostream &OS) const {
325 OS << ARMCondCodeToString(getCondCode());
334 OS << "<register " << getReg() << ">";
337 OS << "'" << getToken() << "'";
342 /// @name Auto-generated Match Functions
345 static unsigned MatchRegisterName(StringRef Name);
349 /// Try to parse a register name. The token must be an Identifier when called,
350 /// and if it is a register name a Reg operand is created, the token is eaten
351 /// and false is returned. Else true is returned and no token is eaten.
352 /// TODO this is likely to change to allow different register types and or to
353 /// parse for a specific register type.
354 bool ARMAsmParser::MaybeParseRegister
355 (OwningPtr<ARMOperand> &Op, bool ParseWriteBack) {
357 const AsmToken &Tok = Parser.getTok();
358 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
360 // FIXME: Validate register for the current architecture; we have to do
361 // validation later, so maybe there is no need for this here.
364 RegNum = MatchRegisterName(Tok.getString());
370 Parser.Lex(); // Eat identifier token.
372 E = Parser.getTok().getLoc();
374 bool Writeback = false;
375 if (ParseWriteBack) {
376 const AsmToken &ExclaimTok = Parser.getTok();
377 if (ExclaimTok.is(AsmToken::Exclaim)) {
378 E = ExclaimTok.getLoc();
380 Parser.Lex(); // Eat exclaim token
384 ARMOperand::CreateReg(Op, RegNum, Writeback, S, E);
389 /// Parse a register list, return false if successful else return true or an
390 /// error. The first token must be a '{' when called.
391 bool ARMAsmParser::ParseRegisterList(OwningPtr<ARMOperand> &Op) {
393 assert(Parser.getTok().is(AsmToken::LCurly) &&
394 "Token is not an Left Curly Brace");
395 S = Parser.getTok().getLoc();
396 Parser.Lex(); // Eat left curly brace token.
398 const AsmToken &RegTok = Parser.getTok();
399 SMLoc RegLoc = RegTok.getLoc();
400 if (RegTok.isNot(AsmToken::Identifier))
401 return Error(RegLoc, "register expected");
402 int RegNum = MatchRegisterName(RegTok.getString());
404 return Error(RegLoc, "register expected");
405 Parser.Lex(); // Eat identifier token.
406 unsigned RegList = 1 << RegNum;
408 int HighRegNum = RegNum;
409 // TODO ranges like "{Rn-Rm}"
410 while (Parser.getTok().is(AsmToken::Comma)) {
411 Parser.Lex(); // Eat comma token.
413 const AsmToken &RegTok = Parser.getTok();
414 SMLoc RegLoc = RegTok.getLoc();
415 if (RegTok.isNot(AsmToken::Identifier))
416 return Error(RegLoc, "register expected");
417 int RegNum = MatchRegisterName(RegTok.getString());
419 return Error(RegLoc, "register expected");
421 if (RegList & (1 << RegNum))
422 Warning(RegLoc, "register duplicated in register list");
423 else if (RegNum <= HighRegNum)
424 Warning(RegLoc, "register not in ascending order in register list");
425 RegList |= 1 << RegNum;
428 Parser.Lex(); // Eat identifier token.
430 const AsmToken &RCurlyTok = Parser.getTok();
431 if (RCurlyTok.isNot(AsmToken::RCurly))
432 return Error(RCurlyTok.getLoc(), "'}' expected");
433 E = RCurlyTok.getLoc();
434 Parser.Lex(); // Eat left curly brace token.
439 /// Parse an arm memory expression, return false if successful else return true
440 /// or an error. The first token must be a '[' when called.
441 /// TODO Only preindexing and postindexing addressing are started, unindexed
442 /// with option, etc are still to do.
443 bool ARMAsmParser::ParseMemory(OwningPtr<ARMOperand> &Op) {
445 assert(Parser.getTok().is(AsmToken::LBrac) &&
446 "Token is not an Left Bracket");
447 S = Parser.getTok().getLoc();
448 Parser.Lex(); // Eat left bracket token.
450 const AsmToken &BaseRegTok = Parser.getTok();
451 if (BaseRegTok.isNot(AsmToken::Identifier))
452 return Error(BaseRegTok.getLoc(), "register expected");
453 if (MaybeParseRegister(Op, false))
454 return Error(BaseRegTok.getLoc(), "register expected");
455 int BaseRegNum = Op->getReg();
457 bool Preindexed = false;
458 bool Postindexed = false;
459 bool OffsetIsReg = false;
460 bool Negative = false;
461 bool Writeback = false;
463 // First look for preindexed address forms, that is after the "[Rn" we now
464 // have to see if the next token is a comma.
465 const AsmToken &Tok = Parser.getTok();
466 if (Tok.is(AsmToken::Comma)) {
468 Parser.Lex(); // Eat comma token.
470 bool OffsetRegShifted;
471 enum ShiftType ShiftType;
472 const MCExpr *ShiftAmount;
473 const MCExpr *Offset;
474 if(ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
475 Offset, OffsetIsReg, OffsetRegNum, E))
477 const AsmToken &RBracTok = Parser.getTok();
478 if (RBracTok.isNot(AsmToken::RBrac))
479 return Error(RBracTok.getLoc(), "']' expected");
480 E = RBracTok.getLoc();
481 Parser.Lex(); // Eat right bracket token.
483 const AsmToken &ExclaimTok = Parser.getTok();
484 if (ExclaimTok.is(AsmToken::Exclaim)) {
485 E = ExclaimTok.getLoc();
487 Parser.Lex(); // Eat exclaim token
489 ARMOperand::CreateMem(Op, BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
490 OffsetRegShifted, ShiftType, ShiftAmount,
491 Preindexed, Postindexed, Negative, Writeback, S, E);
494 // The "[Rn" we have so far was not followed by a comma.
495 else if (Tok.is(AsmToken::RBrac)) {
496 // This is a post indexing addressing forms, that is a ']' follows after
501 Parser.Lex(); // Eat right bracket token.
503 int OffsetRegNum = 0;
504 bool OffsetRegShifted = false;
505 enum ShiftType ShiftType;
506 const MCExpr *ShiftAmount;
507 const MCExpr *Offset;
509 const AsmToken &NextTok = Parser.getTok();
510 if (NextTok.isNot(AsmToken::EndOfStatement)) {
511 if (NextTok.isNot(AsmToken::Comma))
512 return Error(NextTok.getLoc(), "',' expected");
513 Parser.Lex(); // Eat comma token.
514 if(ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
515 ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
520 ARMOperand::CreateMem(Op, BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
521 OffsetRegShifted, ShiftType, ShiftAmount,
522 Preindexed, Postindexed, Negative, Writeback, S, E);
529 /// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
530 /// we will parse the following (were +/- means that a plus or minus is
535 /// we return false on success or an error otherwise.
536 bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
537 bool &OffsetRegShifted,
538 enum ShiftType &ShiftType,
539 const MCExpr *&ShiftAmount,
540 const MCExpr *&Offset,
544 OwningPtr<ARMOperand> Op;
546 OffsetRegShifted = false;
549 const AsmToken &NextTok = Parser.getTok();
550 E = NextTok.getLoc();
551 if (NextTok.is(AsmToken::Plus))
552 Parser.Lex(); // Eat plus token.
553 else if (NextTok.is(AsmToken::Minus)) {
555 Parser.Lex(); // Eat minus token
557 // See if there is a register following the "[Rn," or "[Rn]," we have so far.
558 const AsmToken &OffsetRegTok = Parser.getTok();
559 if (OffsetRegTok.is(AsmToken::Identifier)) {
560 OffsetIsReg = !MaybeParseRegister(Op, false);
563 OffsetRegNum = Op->getReg();
566 // If we parsed a register as the offset then their can be a shift after that
567 if (OffsetRegNum != -1) {
568 // Look for a comma then a shift
569 const AsmToken &Tok = Parser.getTok();
570 if (Tok.is(AsmToken::Comma)) {
571 Parser.Lex(); // Eat comma token.
573 const AsmToken &Tok = Parser.getTok();
574 if (ParseShift(ShiftType, ShiftAmount, E))
575 return Error(Tok.getLoc(), "shift expected");
576 OffsetRegShifted = true;
579 else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
580 // Look for #offset following the "[Rn," or "[Rn],"
581 const AsmToken &HashTok = Parser.getTok();
582 if (HashTok.isNot(AsmToken::Hash))
583 return Error(HashTok.getLoc(), "'#' expected");
585 Parser.Lex(); // Eat hash token.
587 if (getParser().ParseExpression(Offset))
589 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
594 /// ParseShift as one of these two:
595 /// ( lsl | lsr | asr | ror ) , # shift_amount
597 /// and returns true if it parses a shift otherwise it returns false.
598 bool ARMAsmParser::ParseShift(ShiftType &St,
599 const MCExpr *&ShiftAmount,
601 const AsmToken &Tok = Parser.getTok();
602 if (Tok.isNot(AsmToken::Identifier))
604 StringRef ShiftName = Tok.getString();
605 if (ShiftName == "lsl" || ShiftName == "LSL")
607 else if (ShiftName == "lsr" || ShiftName == "LSR")
609 else if (ShiftName == "asr" || ShiftName == "ASR")
611 else if (ShiftName == "ror" || ShiftName == "ROR")
613 else if (ShiftName == "rrx" || ShiftName == "RRX")
617 Parser.Lex(); // Eat shift type token.
623 // Otherwise, there must be a '#' and a shift amount.
624 const AsmToken &HashTok = Parser.getTok();
625 if (HashTok.isNot(AsmToken::Hash))
626 return Error(HashTok.getLoc(), "'#' expected");
627 Parser.Lex(); // Eat hash token.
629 if (getParser().ParseExpression(ShiftAmount))
635 /// Parse a arm instruction operand. For now this parses the operand regardless
637 bool ARMAsmParser::ParseOperand(OwningPtr<ARMOperand> &Op) {
640 switch (getLexer().getKind()) {
641 case AsmToken::Identifier:
642 if (!MaybeParseRegister(Op, true))
644 // This was not a register so parse other operands that start with an
645 // identifier (like labels) as expressions and create them as immediates.
647 S = Parser.getTok().getLoc();
648 if (getParser().ParseExpression(IdVal))
650 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
651 ARMOperand::CreateImm(Op, IdVal, S, E);
653 case AsmToken::LBrac:
654 return ParseMemory(Op);
655 case AsmToken::LCurly:
656 return ParseRegisterList(Op);
659 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
660 S = Parser.getTok().getLoc();
662 const MCExpr *ImmVal;
663 if (getParser().ParseExpression(ImmVal))
665 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
666 ARMOperand::CreateImm(Op, ImmVal, S, E);
669 return Error(Parser.getTok().getLoc(), "unexpected token in operand");
673 /// Parse an arm instruction mnemonic followed by its operands.
674 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
675 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
676 OwningPtr<ARMOperand> Op;
678 // Create the leading tokens for the mnemonic, split by '.' characters.
679 size_t Start = 0, Next = Name.find('.');
680 StringRef Head = Name.slice(Start, Next);
682 // Determine the predicate, if any.
684 // FIXME: We need a way to check whether a prefix supports predication,
685 // otherwise we will end up with an ambiguity for instructions that happen to
686 // end with a predicate name.
687 unsigned CC = StringSwitch<unsigned>(Head.substr(Head.size()-2))
688 .Case("eq", ARMCC::EQ)
689 .Case("ne", ARMCC::NE)
690 .Case("hs", ARMCC::HS)
691 .Case("lo", ARMCC::LO)
692 .Case("mi", ARMCC::MI)
693 .Case("pl", ARMCC::PL)
694 .Case("vs", ARMCC::VS)
695 .Case("vc", ARMCC::VC)
696 .Case("hi", ARMCC::HI)
697 .Case("ls", ARMCC::LS)
698 .Case("ge", ARMCC::GE)
699 .Case("lt", ARMCC::LT)
700 .Case("gt", ARMCC::GT)
701 .Case("le", ARMCC::LE)
702 .Case("al", ARMCC::AL)
705 Head = Head.slice(0, Head.size() - 2);
709 ARMOperand::CreateToken(Op, Head, NameLoc);
710 Operands.push_back(Op.take());
712 ARMOperand::CreateCondCode(Op, ARMCC::CondCodes(CC), NameLoc);
713 Operands.push_back(Op.take());
715 // Add the remaining tokens in the mnemonic.
716 while (Next != StringRef::npos) {
718 Next = Name.find('.', Start + 1);
719 Head = Name.slice(Start, Next);
721 ARMOperand::CreateToken(Op, Head, NameLoc);
722 Operands.push_back(Op.take());
725 // Read the remaining operands.
726 if (getLexer().isNot(AsmToken::EndOfStatement)) {
727 // Read the first operand.
728 OwningPtr<ARMOperand> Op;
729 if (ParseOperand(Op)) return true;
730 Operands.push_back(Op.take());
732 while (getLexer().is(AsmToken::Comma)) {
733 Parser.Lex(); // Eat the comma.
735 // Parse and remember the operand.
736 if (ParseOperand(Op)) return true;
737 Operands.push_back(Op.take());
743 /// ParseDirective parses the arm specific directives
744 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
745 StringRef IDVal = DirectiveID.getIdentifier();
746 if (IDVal == ".word")
747 return ParseDirectiveWord(4, DirectiveID.getLoc());
748 else if (IDVal == ".thumb")
749 return ParseDirectiveThumb(DirectiveID.getLoc());
750 else if (IDVal == ".thumb_func")
751 return ParseDirectiveThumbFunc(DirectiveID.getLoc());
752 else if (IDVal == ".code")
753 return ParseDirectiveCode(DirectiveID.getLoc());
754 else if (IDVal == ".syntax")
755 return ParseDirectiveSyntax(DirectiveID.getLoc());
759 /// ParseDirectiveWord
760 /// ::= .word [ expression (, expression)* ]
761 bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
762 if (getLexer().isNot(AsmToken::EndOfStatement)) {
765 if (getParser().ParseExpression(Value))
768 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
770 if (getLexer().is(AsmToken::EndOfStatement))
773 // FIXME: Improve diagnostic.
774 if (getLexer().isNot(AsmToken::Comma))
775 return Error(L, "unexpected token in directive");
784 /// ParseDirectiveThumb
786 bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
787 if (getLexer().isNot(AsmToken::EndOfStatement))
788 return Error(L, "unexpected token in directive");
791 // TODO: set thumb mode
792 // TODO: tell the MC streamer the mode
793 // getParser().getStreamer().Emit???();
797 /// ParseDirectiveThumbFunc
798 /// ::= .thumbfunc symbol_name
799 bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
800 const AsmToken &Tok = Parser.getTok();
801 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
802 return Error(L, "unexpected token in .syntax directive");
803 StringRef ATTRIBUTE_UNUSED SymbolName = Parser.getTok().getIdentifier();
804 Parser.Lex(); // Consume the identifier token.
806 if (getLexer().isNot(AsmToken::EndOfStatement))
807 return Error(L, "unexpected token in directive");
810 // TODO: mark symbol as a thumb symbol
811 // getParser().getStreamer().Emit???();
815 /// ParseDirectiveSyntax
816 /// ::= .syntax unified | divided
817 bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
818 const AsmToken &Tok = Parser.getTok();
819 if (Tok.isNot(AsmToken::Identifier))
820 return Error(L, "unexpected token in .syntax directive");
821 StringRef Mode = Tok.getString();
822 if (Mode == "unified" || Mode == "UNIFIED")
824 else if (Mode == "divided" || Mode == "DIVIDED")
827 return Error(L, "unrecognized syntax mode in .syntax directive");
829 if (getLexer().isNot(AsmToken::EndOfStatement))
830 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
833 // TODO tell the MC streamer the mode
834 // getParser().getStreamer().Emit???();
838 /// ParseDirectiveCode
839 /// ::= .code 16 | 32
840 bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
841 const AsmToken &Tok = Parser.getTok();
842 if (Tok.isNot(AsmToken::Integer))
843 return Error(L, "unexpected token in .code directive");
844 int64_t Val = Parser.getTok().getIntVal();
850 return Error(L, "invalid operand to .code directive");
852 if (getLexer().isNot(AsmToken::EndOfStatement))
853 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
856 // TODO tell the MC streamer the mode
857 // getParser().getStreamer().Emit???();
861 extern "C" void LLVMInitializeARMAsmLexer();
863 /// Force static initialization.
864 extern "C" void LLVMInitializeARMAsmParser() {
865 RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
866 RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
867 LLVMInitializeARMAsmLexer();
870 #define GET_REGISTER_MATCHER
871 #define GET_MATCHER_IMPLEMENTATION
872 #include "ARMGenAsmMatcher.inc"