1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "ARMBuildAttrs.h"
11 #include "ARMFPUName.h"
12 #include "ARMFeatures.h"
13 #include "llvm/MC/MCTargetAsmParser.h"
14 #include "MCTargetDesc/ARMAddressingModes.h"
15 #include "MCTargetDesc/ARMArchName.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "MCTargetDesc/ARMMCExpr.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/MapVector.h"
20 #include "llvm/ADT/OwningPtr.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/StringExtras.h"
24 #include "llvm/ADT/StringSwitch.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/MC/MCAsmInfo.h"
27 #include "llvm/MC/MCAssembler.h"
28 #include "llvm/MC/MCContext.h"
29 #include "llvm/MC/MCELFStreamer.h"
30 #include "llvm/MC/MCExpr.h"
31 #include "llvm/MC/MCInst.h"
32 #include "llvm/MC/MCInstrDesc.h"
33 #include "llvm/MC/MCInstrInfo.h"
34 #include "llvm/MC/MCSection.h"
35 #include "llvm/MC/MCParser/MCAsmLexer.h"
36 #include "llvm/MC/MCParser/MCAsmParser.h"
37 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
38 #include "llvm/MC/MCRegisterInfo.h"
39 #include "llvm/MC/MCStreamer.h"
40 #include "llvm/MC/MCSubtargetInfo.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/Support/ELF.h"
43 #include "llvm/Support/MathExtras.h"
44 #include "llvm/Support/SourceMgr.h"
45 #include "llvm/Support/TargetRegistry.h"
46 #include "llvm/Support/raw_ostream.h"
54 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
56 // A class to keep track of assembler-generated constant pools that are use to
57 // implement the ldr-pseudo.
59 typedef SmallVector<std::pair<MCSymbol *, const MCExpr *>, 4> EntryVecTy;
63 // Initialize a new empty constant pool
66 // Add a new entry to the constant pool in the next slot.
67 // \param Value is the new entry to put in the constant pool.
69 // \returns a MCExpr that references the newly inserted value
70 const MCExpr *addEntry(const MCExpr *Value, MCContext &Context) {
71 MCSymbol *CPEntryLabel = Context.CreateTempSymbol();
73 Entries.push_back(std::make_pair(CPEntryLabel, Value));
74 return MCSymbolRefExpr::Create(CPEntryLabel, Context);
77 // Emit the contents of the constant pool using the provided streamer.
78 void emitEntries(MCStreamer &Streamer) {
81 Streamer.EmitCodeAlignment(4); // align to 4-byte address
82 Streamer.EmitDataRegion(MCDR_DataRegion);
83 for (EntryVecTy::const_iterator I = Entries.begin(), E = Entries.end();
85 Streamer.EmitLabel(I->first);
86 Streamer.EmitValue(I->second, 4);
88 Streamer.EmitDataRegion(MCDR_DataRegionEnd);
92 // Return true if the constant pool is empty
94 return Entries.empty();
98 // Map type used to keep track of per-Section constant pools used by the
99 // ldr-pseudo opcode. The map associates a section to its constant pool. The
100 // constant pool is a vector of (label, value) pairs. When the ldr
101 // pseudo is parsed we insert a new (label, value) pair into the constant pool
102 // for the current section and add MCSymbolRefExpr to the new label as
103 // an opcode to the ldr. After we have parsed all the user input we
104 // output the (label, value) pairs in each constant pool at the end of the
107 // We use the MapVector for the map type to ensure stable iteration of
108 // the sections at the end of the parse. We need to iterate over the
109 // sections in a stable order to ensure that we have print the
110 // constant pools in a deterministic order when printing an assembly
112 typedef MapVector<const MCSection *, ConstantPool> ConstantPoolMapTy;
114 class ARMAsmParser : public MCTargetAsmParser {
115 MCSubtargetInfo &STI;
117 const MCInstrInfo &MII;
118 const MCRegisterInfo *MRI;
119 ConstantPoolMapTy ConstantPools;
121 // Assembler created constant pools for ldr pseudo
122 ConstantPool *getConstantPool(const MCSection *Section) {
123 ConstantPoolMapTy::iterator CP = ConstantPools.find(Section);
124 if (CP == ConstantPools.end())
130 ConstantPool &getOrCreateConstantPool(const MCSection *Section) {
131 return ConstantPools[Section];
134 ARMTargetStreamer &getTargetStreamer() {
135 MCTargetStreamer &TS = getParser().getStreamer().getTargetStreamer();
136 return static_cast<ARMTargetStreamer &>(TS);
139 // Unwind directives state
142 SMLoc PersonalityLoc;
143 SMLoc HandlerDataLoc;
145 void resetUnwindDirectiveParserState() {
146 FnStartLoc = SMLoc();
147 CantUnwindLoc = SMLoc();
148 PersonalityLoc = SMLoc();
149 HandlerDataLoc = SMLoc();
153 // Map of register aliases registers via the .req directive.
154 StringMap<unsigned> RegisterReqs;
156 bool NextSymbolIsThumb;
159 ARMCC::CondCodes Cond; // Condition for IT block.
160 unsigned Mask:4; // Condition mask for instructions.
161 // Starting at first 1 (from lsb).
162 // '1' condition as indicated in IT.
163 // '0' inverse of condition (else).
164 // Count of instructions in IT block is
165 // 4 - trailingzeroes(mask)
167 bool FirstCond; // Explicit flag for when we're parsing the
168 // First instruction in the IT block. It's
169 // implied in the mask, so needs special
172 unsigned CurPosition; // Current position in parsing of IT
173 // block. In range [0,3]. Initialized
174 // according to count of instructions in block.
175 // ~0U if no active IT block.
177 bool inITBlock() { return ITState.CurPosition != ~0U;}
178 void forwardITPosition() {
179 if (!inITBlock()) return;
180 // Move to the next instruction in the IT block, if there is one. If not,
181 // mark the block as done.
182 unsigned TZ = countTrailingZeros(ITState.Mask);
183 if (++ITState.CurPosition == 5 - TZ)
184 ITState.CurPosition = ~0U; // Done with the IT block after this.
188 MCAsmParser &getParser() const { return Parser; }
189 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
191 bool Warning(SMLoc L, const Twine &Msg,
192 ArrayRef<SMRange> Ranges = None) {
193 return Parser.Warning(L, Msg, Ranges);
195 bool Error(SMLoc L, const Twine &Msg,
196 ArrayRef<SMRange> Ranges = None) {
197 return Parser.Error(L, Msg, Ranges);
200 int tryParseRegister();
201 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
202 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
203 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
204 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
205 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
206 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
207 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
208 unsigned &ShiftAmount);
209 bool parseDirectiveWord(unsigned Size, SMLoc L);
210 bool parseDirectiveThumb(SMLoc L);
211 bool parseDirectiveARM(SMLoc L);
212 bool parseDirectiveThumbFunc(SMLoc L);
213 bool parseDirectiveCode(SMLoc L);
214 bool parseDirectiveSyntax(SMLoc L);
215 bool parseDirectiveReq(StringRef Name, SMLoc L);
216 bool parseDirectiveUnreq(SMLoc L);
217 bool parseDirectiveArch(SMLoc L);
218 bool parseDirectiveEabiAttr(SMLoc L);
219 bool parseDirectiveCPU(SMLoc L);
220 bool parseDirectiveFPU(SMLoc L);
221 bool parseDirectiveFnStart(SMLoc L);
222 bool parseDirectiveFnEnd(SMLoc L);
223 bool parseDirectiveCantUnwind(SMLoc L);
224 bool parseDirectivePersonality(SMLoc L);
225 bool parseDirectiveHandlerData(SMLoc L);
226 bool parseDirectiveSetFP(SMLoc L);
227 bool parseDirectivePad(SMLoc L);
228 bool parseDirectiveRegSave(SMLoc L, bool IsVector);
229 bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
230 bool parseDirectiveLtorg(SMLoc L);
231 bool parseDirectiveEven(SMLoc L);
233 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
234 bool &CarrySetting, unsigned &ProcessorIMod,
236 void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
237 bool &CanAcceptCarrySet,
238 bool &CanAcceptPredicationCode);
240 bool isThumb() const {
241 // FIXME: Can tablegen auto-generate this?
242 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
244 bool isThumbOne() const {
245 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
247 bool isThumbTwo() const {
248 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
250 bool hasThumb() const {
251 return STI.getFeatureBits() & ARM::HasV4TOps;
253 bool hasV6Ops() const {
254 return STI.getFeatureBits() & ARM::HasV6Ops;
256 bool hasV6MOps() const {
257 return STI.getFeatureBits() & ARM::HasV6MOps;
259 bool hasV7Ops() const {
260 return STI.getFeatureBits() & ARM::HasV7Ops;
262 bool hasV8Ops() const {
263 return STI.getFeatureBits() & ARM::HasV8Ops;
265 bool hasARM() const {
266 return !(STI.getFeatureBits() & ARM::FeatureNoARM);
270 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
271 setAvailableFeatures(FB);
273 bool isMClass() const {
274 return STI.getFeatureBits() & ARM::FeatureMClass;
277 /// @name Auto-generated Match Functions
280 #define GET_ASSEMBLER_HEADER
281 #include "ARMGenAsmMatcher.inc"
285 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
286 OperandMatchResultTy parseCoprocNumOperand(
287 SmallVectorImpl<MCParsedAsmOperand*>&);
288 OperandMatchResultTy parseCoprocRegOperand(
289 SmallVectorImpl<MCParsedAsmOperand*>&);
290 OperandMatchResultTy parseCoprocOptionOperand(
291 SmallVectorImpl<MCParsedAsmOperand*>&);
292 OperandMatchResultTy parseMemBarrierOptOperand(
293 SmallVectorImpl<MCParsedAsmOperand*>&);
294 OperandMatchResultTy parseInstSyncBarrierOptOperand(
295 SmallVectorImpl<MCParsedAsmOperand*>&);
296 OperandMatchResultTy parseProcIFlagsOperand(
297 SmallVectorImpl<MCParsedAsmOperand*>&);
298 OperandMatchResultTy parseMSRMaskOperand(
299 SmallVectorImpl<MCParsedAsmOperand*>&);
300 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
301 StringRef Op, int Low, int High);
302 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
303 return parsePKHImm(O, "lsl", 0, 31);
305 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
306 return parsePKHImm(O, "asr", 1, 32);
308 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
309 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
310 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
311 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
312 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
313 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
314 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
315 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
316 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
319 // Asm Match Converter Methods
320 void cvtThumbMultiply(MCInst &Inst,
321 const SmallVectorImpl<MCParsedAsmOperand*> &);
322 void cvtThumbBranches(MCInst &Inst,
323 const SmallVectorImpl<MCParsedAsmOperand*> &);
325 bool validateInstruction(MCInst &Inst,
326 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
327 bool processInstruction(MCInst &Inst,
328 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
329 bool shouldOmitCCOutOperand(StringRef Mnemonic,
330 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
331 bool shouldOmitPredicateOperand(StringRef Mnemonic,
332 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
334 enum ARMMatchResultTy {
335 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
336 Match_RequiresNotITBlock,
338 Match_RequiresThumb2,
339 #define GET_OPERAND_DIAGNOSTIC_TYPES
340 #include "ARMGenAsmMatcher.inc"
344 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
345 const MCInstrInfo &MII)
346 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(MII), FPReg(-1) {
347 MCAsmParserExtension::Initialize(_Parser);
349 // Cache the MCRegisterInfo.
350 MRI = getContext().getRegisterInfo();
352 // Initialize the set of available features.
353 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
355 // Not in an ITBlock to start with.
356 ITState.CurPosition = ~0U;
358 NextSymbolIsThumb = false;
361 // Implementation of the MCTargetAsmParser interface:
362 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
363 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
365 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
366 bool ParseDirective(AsmToken DirectiveID);
368 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
369 unsigned checkTargetMatchPredicate(MCInst &Inst);
371 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
372 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
373 MCStreamer &Out, unsigned &ErrorInfo,
374 bool MatchingInlineAsm);
375 void onLabelParsed(MCSymbol *Symbol);
378 } // end anonymous namespace
382 /// ARMOperand - Instances of this class represent a parsed ARM machine
384 class ARMOperand : public MCParsedAsmOperand {
394 k_InstSyncBarrierOpt,
405 k_VectorListAllLanes,
411 k_BitfieldDescriptor,
415 SMLoc StartLoc, EndLoc;
416 SmallVector<unsigned, 8> Registers;
419 ARMCC::CondCodes Val;
426 struct CoprocOptionOp {
439 ARM_ISB::InstSyncBOpt Val;
443 ARM_PROC::IFlags Val;
459 // A vector register list is a sequential list of 1 to 4 registers.
460 struct VectorListOp {
467 struct VectorIndexOp {
475 /// Combined record for all forms of ARM address expressions.
478 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
480 const MCConstantExpr *OffsetImm; // Offset immediate value
481 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
482 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
483 unsigned ShiftImm; // shift for OffsetReg.
484 unsigned Alignment; // 0 = no alignment specified
485 // n = alignment in bytes (2, 4, 8, 16, or 32)
486 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
489 struct PostIdxRegOp {
492 ARM_AM::ShiftOpc ShiftTy;
496 struct ShifterImmOp {
501 struct RegShiftedRegOp {
502 ARM_AM::ShiftOpc ShiftTy;
508 struct RegShiftedImmOp {
509 ARM_AM::ShiftOpc ShiftTy;
526 struct CoprocOptionOp CoprocOption;
527 struct MBOptOp MBOpt;
528 struct ISBOptOp ISBOpt;
529 struct ITMaskOp ITMask;
530 struct IFlagsOp IFlags;
531 struct MMaskOp MMask;
534 struct VectorListOp VectorList;
535 struct VectorIndexOp VectorIndex;
537 struct MemoryOp Memory;
538 struct PostIdxRegOp PostIdxReg;
539 struct ShifterImmOp ShifterImm;
540 struct RegShiftedRegOp RegShiftedReg;
541 struct RegShiftedImmOp RegShiftedImm;
542 struct RotImmOp RotImm;
543 struct BitfieldOp Bitfield;
546 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
548 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
550 StartLoc = o.StartLoc;
567 case k_DPRRegisterList:
568 case k_SPRRegisterList:
569 Registers = o.Registers;
572 case k_VectorListAllLanes:
573 case k_VectorListIndexed:
574 VectorList = o.VectorList;
581 CoprocOption = o.CoprocOption;
586 case k_MemBarrierOpt:
589 case k_InstSyncBarrierOpt:
594 case k_PostIndexRegister:
595 PostIdxReg = o.PostIdxReg;
603 case k_ShifterImmediate:
604 ShifterImm = o.ShifterImm;
606 case k_ShiftedRegister:
607 RegShiftedReg = o.RegShiftedReg;
609 case k_ShiftedImmediate:
610 RegShiftedImm = o.RegShiftedImm;
612 case k_RotateImmediate:
615 case k_BitfieldDescriptor:
616 Bitfield = o.Bitfield;
619 VectorIndex = o.VectorIndex;
624 /// getStartLoc - Get the location of the first token of this operand.
625 SMLoc getStartLoc() const { return StartLoc; }
626 /// getEndLoc - Get the location of the last token of this operand.
627 SMLoc getEndLoc() const { return EndLoc; }
628 /// getLocRange - Get the range between the first and last token of this
630 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
632 ARMCC::CondCodes getCondCode() const {
633 assert(Kind == k_CondCode && "Invalid access!");
637 unsigned getCoproc() const {
638 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
642 StringRef getToken() const {
643 assert(Kind == k_Token && "Invalid access!");
644 return StringRef(Tok.Data, Tok.Length);
647 unsigned getReg() const {
648 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
652 const SmallVectorImpl<unsigned> &getRegList() const {
653 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
654 Kind == k_SPRRegisterList) && "Invalid access!");
658 const MCExpr *getImm() const {
659 assert(isImm() && "Invalid access!");
663 unsigned getVectorIndex() const {
664 assert(Kind == k_VectorIndex && "Invalid access!");
665 return VectorIndex.Val;
668 ARM_MB::MemBOpt getMemBarrierOpt() const {
669 assert(Kind == k_MemBarrierOpt && "Invalid access!");
673 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
674 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
678 ARM_PROC::IFlags getProcIFlags() const {
679 assert(Kind == k_ProcIFlags && "Invalid access!");
683 unsigned getMSRMask() const {
684 assert(Kind == k_MSRMask && "Invalid access!");
688 bool isCoprocNum() const { return Kind == k_CoprocNum; }
689 bool isCoprocReg() const { return Kind == k_CoprocReg; }
690 bool isCoprocOption() const { return Kind == k_CoprocOption; }
691 bool isCondCode() const { return Kind == k_CondCode; }
692 bool isCCOut() const { return Kind == k_CCOut; }
693 bool isITMask() const { return Kind == k_ITCondMask; }
694 bool isITCondCode() const { return Kind == k_CondCode; }
695 bool isImm() const { return Kind == k_Immediate; }
696 // checks whether this operand is an unsigned offset which fits is a field
697 // of specified width and scaled by a specific number of bits
698 template<unsigned width, unsigned scale>
699 bool isUnsignedOffset() const {
700 if (!isImm()) return false;
701 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
702 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
703 int64_t Val = CE->getValue();
704 int64_t Align = 1LL << scale;
705 int64_t Max = Align * ((1LL << width) - 1);
706 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
710 // checks whether this operand is an signed offset which fits is a field
711 // of specified width and scaled by a specific number of bits
712 template<unsigned width, unsigned scale>
713 bool isSignedOffset() const {
714 if (!isImm()) return false;
715 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
716 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
717 int64_t Val = CE->getValue();
718 int64_t Align = 1LL << scale;
719 int64_t Max = Align * ((1LL << (width-1)) - 1);
720 int64_t Min = -Align * (1LL << (width-1));
721 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
726 // checks whether this operand is a memory operand computed as an offset
727 // applied to PC. the offset may have 8 bits of magnitude and is represented
728 // with two bits of shift. textually it may be either [pc, #imm], #imm or
729 // relocable expression...
730 bool isThumbMemPC() const {
733 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
734 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
735 if (!CE) return false;
736 Val = CE->getValue();
739 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
740 if(Memory.BaseRegNum != ARM::PC) return false;
741 Val = Memory.OffsetImm->getValue();
744 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
746 bool isFPImm() const {
747 if (!isImm()) return false;
748 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
749 if (!CE) return false;
750 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
753 bool isFBits16() const {
754 if (!isImm()) return false;
755 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
756 if (!CE) return false;
757 int64_t Value = CE->getValue();
758 return Value >= 0 && Value <= 16;
760 bool isFBits32() const {
761 if (!isImm()) return false;
762 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
763 if (!CE) return false;
764 int64_t Value = CE->getValue();
765 return Value >= 1 && Value <= 32;
767 bool isImm8s4() const {
768 if (!isImm()) return false;
769 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
770 if (!CE) return false;
771 int64_t Value = CE->getValue();
772 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
774 bool isImm0_1020s4() const {
775 if (!isImm()) return false;
776 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
777 if (!CE) return false;
778 int64_t Value = CE->getValue();
779 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
781 bool isImm0_508s4() const {
782 if (!isImm()) return false;
783 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
784 if (!CE) return false;
785 int64_t Value = CE->getValue();
786 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
788 bool isImm0_508s4Neg() const {
789 if (!isImm()) return false;
790 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
791 if (!CE) return false;
792 int64_t Value = -CE->getValue();
793 // explicitly exclude zero. we want that to use the normal 0_508 version.
794 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
796 bool isImm0_239() const {
797 if (!isImm()) return false;
798 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
799 if (!CE) return false;
800 int64_t Value = CE->getValue();
801 return Value >= 0 && Value < 240;
803 bool isImm0_255() const {
804 if (!isImm()) return false;
805 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
806 if (!CE) return false;
807 int64_t Value = CE->getValue();
808 return Value >= 0 && Value < 256;
810 bool isImm0_4095() const {
811 if (!isImm()) return false;
812 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
813 if (!CE) return false;
814 int64_t Value = CE->getValue();
815 return Value >= 0 && Value < 4096;
817 bool isImm0_4095Neg() const {
818 if (!isImm()) return false;
819 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
820 if (!CE) return false;
821 int64_t Value = -CE->getValue();
822 return Value > 0 && Value < 4096;
824 bool isImm0_1() const {
825 if (!isImm()) return false;
826 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
827 if (!CE) return false;
828 int64_t Value = CE->getValue();
829 return Value >= 0 && Value < 2;
831 bool isImm0_3() const {
832 if (!isImm()) return false;
833 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
834 if (!CE) return false;
835 int64_t Value = CE->getValue();
836 return Value >= 0 && Value < 4;
838 bool isImm0_7() const {
839 if (!isImm()) return false;
840 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
841 if (!CE) return false;
842 int64_t Value = CE->getValue();
843 return Value >= 0 && Value < 8;
845 bool isImm0_15() const {
846 if (!isImm()) return false;
847 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
848 if (!CE) return false;
849 int64_t Value = CE->getValue();
850 return Value >= 0 && Value < 16;
852 bool isImm0_31() const {
853 if (!isImm()) return false;
854 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
855 if (!CE) return false;
856 int64_t Value = CE->getValue();
857 return Value >= 0 && Value < 32;
859 bool isImm0_63() const {
860 if (!isImm()) return false;
861 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
862 if (!CE) return false;
863 int64_t Value = CE->getValue();
864 return Value >= 0 && Value < 64;
866 bool isImm8() const {
867 if (!isImm()) return false;
868 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
869 if (!CE) return false;
870 int64_t Value = CE->getValue();
873 bool isImm16() const {
874 if (!isImm()) return false;
875 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
876 if (!CE) return false;
877 int64_t Value = CE->getValue();
880 bool isImm32() const {
881 if (!isImm()) return false;
882 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
883 if (!CE) return false;
884 int64_t Value = CE->getValue();
887 bool isShrImm8() const {
888 if (!isImm()) return false;
889 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
890 if (!CE) return false;
891 int64_t Value = CE->getValue();
892 return Value > 0 && Value <= 8;
894 bool isShrImm16() const {
895 if (!isImm()) return false;
896 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
897 if (!CE) return false;
898 int64_t Value = CE->getValue();
899 return Value > 0 && Value <= 16;
901 bool isShrImm32() const {
902 if (!isImm()) return false;
903 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
904 if (!CE) return false;
905 int64_t Value = CE->getValue();
906 return Value > 0 && Value <= 32;
908 bool isShrImm64() const {
909 if (!isImm()) return false;
910 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
911 if (!CE) return false;
912 int64_t Value = CE->getValue();
913 return Value > 0 && Value <= 64;
915 bool isImm1_7() const {
916 if (!isImm()) return false;
917 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
918 if (!CE) return false;
919 int64_t Value = CE->getValue();
920 return Value > 0 && Value < 8;
922 bool isImm1_15() const {
923 if (!isImm()) return false;
924 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
925 if (!CE) return false;
926 int64_t Value = CE->getValue();
927 return Value > 0 && Value < 16;
929 bool isImm1_31() const {
930 if (!isImm()) return false;
931 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
932 if (!CE) return false;
933 int64_t Value = CE->getValue();
934 return Value > 0 && Value < 32;
936 bool isImm1_16() const {
937 if (!isImm()) return false;
938 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
939 if (!CE) return false;
940 int64_t Value = CE->getValue();
941 return Value > 0 && Value < 17;
943 bool isImm1_32() const {
944 if (!isImm()) return false;
945 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
946 if (!CE) return false;
947 int64_t Value = CE->getValue();
948 return Value > 0 && Value < 33;
950 bool isImm0_32() const {
951 if (!isImm()) return false;
952 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
953 if (!CE) return false;
954 int64_t Value = CE->getValue();
955 return Value >= 0 && Value < 33;
957 bool isImm0_65535() const {
958 if (!isImm()) return false;
959 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
960 if (!CE) return false;
961 int64_t Value = CE->getValue();
962 return Value >= 0 && Value < 65536;
964 bool isImm256_65535Expr() const {
965 if (!isImm()) return false;
966 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
967 // If it's not a constant expression, it'll generate a fixup and be
969 if (!CE) return true;
970 int64_t Value = CE->getValue();
971 return Value >= 256 && Value < 65536;
973 bool isImm0_65535Expr() const {
974 if (!isImm()) return false;
975 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
976 // If it's not a constant expression, it'll generate a fixup and be
978 if (!CE) return true;
979 int64_t Value = CE->getValue();
980 return Value >= 0 && Value < 65536;
982 bool isImm24bit() const {
983 if (!isImm()) return false;
984 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
985 if (!CE) return false;
986 int64_t Value = CE->getValue();
987 return Value >= 0 && Value <= 0xffffff;
989 bool isImmThumbSR() const {
990 if (!isImm()) return false;
991 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
992 if (!CE) return false;
993 int64_t Value = CE->getValue();
994 return Value > 0 && Value < 33;
996 bool isPKHLSLImm() const {
997 if (!isImm()) return false;
998 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
999 if (!CE) return false;
1000 int64_t Value = CE->getValue();
1001 return Value >= 0 && Value < 32;
1003 bool isPKHASRImm() const {
1004 if (!isImm()) return false;
1005 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1006 if (!CE) return false;
1007 int64_t Value = CE->getValue();
1008 return Value > 0 && Value <= 32;
1010 bool isAdrLabel() const {
1011 // If we have an immediate that's not a constant, treat it as a label
1012 // reference needing a fixup. If it is a constant, but it can't fit
1013 // into shift immediate encoding, we reject it.
1014 if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
1015 else return (isARMSOImm() || isARMSOImmNeg());
1017 bool isARMSOImm() const {
1018 if (!isImm()) return false;
1019 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1020 if (!CE) return false;
1021 int64_t Value = CE->getValue();
1022 return ARM_AM::getSOImmVal(Value) != -1;
1024 bool isARMSOImmNot() const {
1025 if (!isImm()) return false;
1026 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1027 if (!CE) return false;
1028 int64_t Value = CE->getValue();
1029 return ARM_AM::getSOImmVal(~Value) != -1;
1031 bool isARMSOImmNeg() const {
1032 if (!isImm()) return false;
1033 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1034 if (!CE) return false;
1035 int64_t Value = CE->getValue();
1036 // Only use this when not representable as a plain so_imm.
1037 return ARM_AM::getSOImmVal(Value) == -1 &&
1038 ARM_AM::getSOImmVal(-Value) != -1;
1040 bool isT2SOImm() const {
1041 if (!isImm()) return false;
1042 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1043 if (!CE) return false;
1044 int64_t Value = CE->getValue();
1045 return ARM_AM::getT2SOImmVal(Value) != -1;
1047 bool isT2SOImmNot() const {
1048 if (!isImm()) return false;
1049 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1050 if (!CE) return false;
1051 int64_t Value = CE->getValue();
1052 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1053 ARM_AM::getT2SOImmVal(~Value) != -1;
1055 bool isT2SOImmNeg() const {
1056 if (!isImm()) return false;
1057 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1058 if (!CE) return false;
1059 int64_t Value = CE->getValue();
1060 // Only use this when not representable as a plain so_imm.
1061 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1062 ARM_AM::getT2SOImmVal(-Value) != -1;
1064 bool isSetEndImm() const {
1065 if (!isImm()) return false;
1066 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1067 if (!CE) return false;
1068 int64_t Value = CE->getValue();
1069 return Value == 1 || Value == 0;
1071 bool isReg() const { return Kind == k_Register; }
1072 bool isRegList() const { return Kind == k_RegisterList; }
1073 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1074 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1075 bool isToken() const { return Kind == k_Token; }
1076 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1077 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1078 bool isMem() const { return Kind == k_Memory; }
1079 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1080 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
1081 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
1082 bool isRotImm() const { return Kind == k_RotateImmediate; }
1083 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1084 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
1085 bool isPostIdxReg() const {
1086 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
1088 bool isMemNoOffset(bool alignOK = false) const {
1091 // No offset of any kind.
1092 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
1093 (alignOK || Memory.Alignment == 0);
1095 bool isMemPCRelImm12() const {
1096 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1098 // Base register must be PC.
1099 if (Memory.BaseRegNum != ARM::PC)
1101 // Immediate offset in range [-4095, 4095].
1102 if (!Memory.OffsetImm) return true;
1103 int64_t Val = Memory.OffsetImm->getValue();
1104 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1106 bool isAlignedMemory() const {
1107 return isMemNoOffset(true);
1109 bool isAddrMode2() const {
1110 if (!isMem() || Memory.Alignment != 0) return false;
1111 // Check for register offset.
1112 if (Memory.OffsetRegNum) return true;
1113 // Immediate offset in range [-4095, 4095].
1114 if (!Memory.OffsetImm) return true;
1115 int64_t Val = Memory.OffsetImm->getValue();
1116 return Val > -4096 && Val < 4096;
1118 bool isAM2OffsetImm() const {
1119 if (!isImm()) return false;
1120 // Immediate offset in range [-4095, 4095].
1121 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1122 if (!CE) return false;
1123 int64_t Val = CE->getValue();
1124 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1126 bool isAddrMode3() const {
1127 // If we have an immediate that's not a constant, treat it as a label
1128 // reference needing a fixup. If it is a constant, it's something else
1129 // and we reject it.
1130 if (isImm() && !isa<MCConstantExpr>(getImm()))
1132 if (!isMem() || Memory.Alignment != 0) return false;
1133 // No shifts are legal for AM3.
1134 if (Memory.ShiftType != ARM_AM::no_shift) return false;
1135 // Check for register offset.
1136 if (Memory.OffsetRegNum) return true;
1137 // Immediate offset in range [-255, 255].
1138 if (!Memory.OffsetImm) return true;
1139 int64_t Val = Memory.OffsetImm->getValue();
1140 // The #-0 offset is encoded as INT32_MIN, and we have to check
1142 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1144 bool isAM3Offset() const {
1145 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1147 if (Kind == k_PostIndexRegister)
1148 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1149 // Immediate offset in range [-255, 255].
1150 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1151 if (!CE) return false;
1152 int64_t Val = CE->getValue();
1153 // Special case, #-0 is INT32_MIN.
1154 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1156 bool isAddrMode5() const {
1157 // If we have an immediate that's not a constant, treat it as a label
1158 // reference needing a fixup. If it is a constant, it's something else
1159 // and we reject it.
1160 if (isImm() && !isa<MCConstantExpr>(getImm()))
1162 if (!isMem() || Memory.Alignment != 0) return false;
1163 // Check for register offset.
1164 if (Memory.OffsetRegNum) return false;
1165 // Immediate offset in range [-1020, 1020] and a multiple of 4.
1166 if (!Memory.OffsetImm) return true;
1167 int64_t Val = Memory.OffsetImm->getValue();
1168 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1171 bool isMemTBB() const {
1172 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1173 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1177 bool isMemTBH() const {
1178 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1179 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1180 Memory.Alignment != 0 )
1184 bool isMemRegOffset() const {
1185 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1189 bool isT2MemRegOffset() const {
1190 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1191 Memory.Alignment != 0)
1193 // Only lsl #{0, 1, 2, 3} allowed.
1194 if (Memory.ShiftType == ARM_AM::no_shift)
1196 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1200 bool isMemThumbRR() const {
1201 // Thumb reg+reg addressing is simple. Just two registers, a base and
1202 // an offset. No shifts, negations or any other complicating factors.
1203 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1204 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1206 return isARMLowRegister(Memory.BaseRegNum) &&
1207 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1209 bool isMemThumbRIs4() const {
1210 if (!isMem() || Memory.OffsetRegNum != 0 ||
1211 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1213 // Immediate offset, multiple of 4 in range [0, 124].
1214 if (!Memory.OffsetImm) return true;
1215 int64_t Val = Memory.OffsetImm->getValue();
1216 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1218 bool isMemThumbRIs2() const {
1219 if (!isMem() || Memory.OffsetRegNum != 0 ||
1220 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1222 // Immediate offset, multiple of 4 in range [0, 62].
1223 if (!Memory.OffsetImm) return true;
1224 int64_t Val = Memory.OffsetImm->getValue();
1225 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1227 bool isMemThumbRIs1() const {
1228 if (!isMem() || Memory.OffsetRegNum != 0 ||
1229 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1231 // Immediate offset in range [0, 31].
1232 if (!Memory.OffsetImm) return true;
1233 int64_t Val = Memory.OffsetImm->getValue();
1234 return Val >= 0 && Val <= 31;
1236 bool isMemThumbSPI() const {
1237 if (!isMem() || Memory.OffsetRegNum != 0 ||
1238 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1240 // Immediate offset, multiple of 4 in range [0, 1020].
1241 if (!Memory.OffsetImm) return true;
1242 int64_t Val = Memory.OffsetImm->getValue();
1243 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1245 bool isMemImm8s4Offset() const {
1246 // If we have an immediate that's not a constant, treat it as a label
1247 // reference needing a fixup. If it is a constant, it's something else
1248 // and we reject it.
1249 if (isImm() && !isa<MCConstantExpr>(getImm()))
1251 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1253 // Immediate offset a multiple of 4 in range [-1020, 1020].
1254 if (!Memory.OffsetImm) return true;
1255 int64_t Val = Memory.OffsetImm->getValue();
1256 // Special case, #-0 is INT32_MIN.
1257 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1259 bool isMemImm0_1020s4Offset() const {
1260 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1262 // Immediate offset a multiple of 4 in range [0, 1020].
1263 if (!Memory.OffsetImm) return true;
1264 int64_t Val = Memory.OffsetImm->getValue();
1265 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1267 bool isMemImm8Offset() const {
1268 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1270 // Base reg of PC isn't allowed for these encodings.
1271 if (Memory.BaseRegNum == ARM::PC) return false;
1272 // Immediate offset in range [-255, 255].
1273 if (!Memory.OffsetImm) return true;
1274 int64_t Val = Memory.OffsetImm->getValue();
1275 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1277 bool isMemPosImm8Offset() const {
1278 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1280 // Immediate offset in range [0, 255].
1281 if (!Memory.OffsetImm) return true;
1282 int64_t Val = Memory.OffsetImm->getValue();
1283 return Val >= 0 && Val < 256;
1285 bool isMemNegImm8Offset() const {
1286 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1288 // Base reg of PC isn't allowed for these encodings.
1289 if (Memory.BaseRegNum == ARM::PC) return false;
1290 // Immediate offset in range [-255, -1].
1291 if (!Memory.OffsetImm) return false;
1292 int64_t Val = Memory.OffsetImm->getValue();
1293 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1295 bool isMemUImm12Offset() const {
1296 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1298 // Immediate offset in range [0, 4095].
1299 if (!Memory.OffsetImm) return true;
1300 int64_t Val = Memory.OffsetImm->getValue();
1301 return (Val >= 0 && Val < 4096);
1303 bool isMemImm12Offset() const {
1304 // If we have an immediate that's not a constant, treat it as a label
1305 // reference needing a fixup. If it is a constant, it's something else
1306 // and we reject it.
1307 if (isImm() && !isa<MCConstantExpr>(getImm()))
1310 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1312 // Immediate offset in range [-4095, 4095].
1313 if (!Memory.OffsetImm) return true;
1314 int64_t Val = Memory.OffsetImm->getValue();
1315 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1317 bool isPostIdxImm8() const {
1318 if (!isImm()) return false;
1319 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1320 if (!CE) return false;
1321 int64_t Val = CE->getValue();
1322 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1324 bool isPostIdxImm8s4() const {
1325 if (!isImm()) return false;
1326 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1327 if (!CE) return false;
1328 int64_t Val = CE->getValue();
1329 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1333 bool isMSRMask() const { return Kind == k_MSRMask; }
1334 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1337 bool isSingleSpacedVectorList() const {
1338 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1340 bool isDoubleSpacedVectorList() const {
1341 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1343 bool isVecListOneD() const {
1344 if (!isSingleSpacedVectorList()) return false;
1345 return VectorList.Count == 1;
1348 bool isVecListDPair() const {
1349 if (!isSingleSpacedVectorList()) return false;
1350 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1351 .contains(VectorList.RegNum));
1354 bool isVecListThreeD() const {
1355 if (!isSingleSpacedVectorList()) return false;
1356 return VectorList.Count == 3;
1359 bool isVecListFourD() const {
1360 if (!isSingleSpacedVectorList()) return false;
1361 return VectorList.Count == 4;
1364 bool isVecListDPairSpaced() const {
1365 if (isSingleSpacedVectorList()) return false;
1366 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1367 .contains(VectorList.RegNum));
1370 bool isVecListThreeQ() const {
1371 if (!isDoubleSpacedVectorList()) return false;
1372 return VectorList.Count == 3;
1375 bool isVecListFourQ() const {
1376 if (!isDoubleSpacedVectorList()) return false;
1377 return VectorList.Count == 4;
1380 bool isSingleSpacedVectorAllLanes() const {
1381 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1383 bool isDoubleSpacedVectorAllLanes() const {
1384 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1386 bool isVecListOneDAllLanes() const {
1387 if (!isSingleSpacedVectorAllLanes()) return false;
1388 return VectorList.Count == 1;
1391 bool isVecListDPairAllLanes() const {
1392 if (!isSingleSpacedVectorAllLanes()) return false;
1393 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1394 .contains(VectorList.RegNum));
1397 bool isVecListDPairSpacedAllLanes() const {
1398 if (!isDoubleSpacedVectorAllLanes()) return false;
1399 return VectorList.Count == 2;
1402 bool isVecListThreeDAllLanes() const {
1403 if (!isSingleSpacedVectorAllLanes()) return false;
1404 return VectorList.Count == 3;
1407 bool isVecListThreeQAllLanes() const {
1408 if (!isDoubleSpacedVectorAllLanes()) return false;
1409 return VectorList.Count == 3;
1412 bool isVecListFourDAllLanes() const {
1413 if (!isSingleSpacedVectorAllLanes()) return false;
1414 return VectorList.Count == 4;
1417 bool isVecListFourQAllLanes() const {
1418 if (!isDoubleSpacedVectorAllLanes()) return false;
1419 return VectorList.Count == 4;
1422 bool isSingleSpacedVectorIndexed() const {
1423 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1425 bool isDoubleSpacedVectorIndexed() const {
1426 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1428 bool isVecListOneDByteIndexed() const {
1429 if (!isSingleSpacedVectorIndexed()) return false;
1430 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1433 bool isVecListOneDHWordIndexed() const {
1434 if (!isSingleSpacedVectorIndexed()) return false;
1435 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1438 bool isVecListOneDWordIndexed() const {
1439 if (!isSingleSpacedVectorIndexed()) return false;
1440 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1443 bool isVecListTwoDByteIndexed() const {
1444 if (!isSingleSpacedVectorIndexed()) return false;
1445 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1448 bool isVecListTwoDHWordIndexed() const {
1449 if (!isSingleSpacedVectorIndexed()) return false;
1450 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1453 bool isVecListTwoQWordIndexed() const {
1454 if (!isDoubleSpacedVectorIndexed()) return false;
1455 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1458 bool isVecListTwoQHWordIndexed() const {
1459 if (!isDoubleSpacedVectorIndexed()) return false;
1460 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1463 bool isVecListTwoDWordIndexed() const {
1464 if (!isSingleSpacedVectorIndexed()) return false;
1465 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1468 bool isVecListThreeDByteIndexed() const {
1469 if (!isSingleSpacedVectorIndexed()) return false;
1470 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1473 bool isVecListThreeDHWordIndexed() const {
1474 if (!isSingleSpacedVectorIndexed()) return false;
1475 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1478 bool isVecListThreeQWordIndexed() const {
1479 if (!isDoubleSpacedVectorIndexed()) return false;
1480 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1483 bool isVecListThreeQHWordIndexed() const {
1484 if (!isDoubleSpacedVectorIndexed()) return false;
1485 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1488 bool isVecListThreeDWordIndexed() const {
1489 if (!isSingleSpacedVectorIndexed()) return false;
1490 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1493 bool isVecListFourDByteIndexed() const {
1494 if (!isSingleSpacedVectorIndexed()) return false;
1495 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1498 bool isVecListFourDHWordIndexed() const {
1499 if (!isSingleSpacedVectorIndexed()) return false;
1500 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1503 bool isVecListFourQWordIndexed() const {
1504 if (!isDoubleSpacedVectorIndexed()) return false;
1505 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1508 bool isVecListFourQHWordIndexed() const {
1509 if (!isDoubleSpacedVectorIndexed()) return false;
1510 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1513 bool isVecListFourDWordIndexed() const {
1514 if (!isSingleSpacedVectorIndexed()) return false;
1515 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1518 bool isVectorIndex8() const {
1519 if (Kind != k_VectorIndex) return false;
1520 return VectorIndex.Val < 8;
1522 bool isVectorIndex16() const {
1523 if (Kind != k_VectorIndex) return false;
1524 return VectorIndex.Val < 4;
1526 bool isVectorIndex32() const {
1527 if (Kind != k_VectorIndex) return false;
1528 return VectorIndex.Val < 2;
1531 bool isNEONi8splat() const {
1532 if (!isImm()) return false;
1533 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1534 // Must be a constant.
1535 if (!CE) return false;
1536 int64_t Value = CE->getValue();
1537 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1539 return Value >= 0 && Value < 256;
1542 bool isNEONi16splat() const {
1543 if (!isImm()) return false;
1544 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1545 // Must be a constant.
1546 if (!CE) return false;
1547 int64_t Value = CE->getValue();
1548 // i16 value in the range [0,255] or [0x0100, 0xff00]
1549 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1552 bool isNEONi32splat() const {
1553 if (!isImm()) return false;
1554 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1555 // Must be a constant.
1556 if (!CE) return false;
1557 int64_t Value = CE->getValue();
1558 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1559 return (Value >= 0 && Value < 256) ||
1560 (Value >= 0x0100 && Value <= 0xff00) ||
1561 (Value >= 0x010000 && Value <= 0xff0000) ||
1562 (Value >= 0x01000000 && Value <= 0xff000000);
1565 bool isNEONi32vmov() const {
1566 if (!isImm()) return false;
1567 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1568 // Must be a constant.
1569 if (!CE) return false;
1570 int64_t Value = CE->getValue();
1571 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1572 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1573 return (Value >= 0 && Value < 256) ||
1574 (Value >= 0x0100 && Value <= 0xff00) ||
1575 (Value >= 0x010000 && Value <= 0xff0000) ||
1576 (Value >= 0x01000000 && Value <= 0xff000000) ||
1577 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1578 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1580 bool isNEONi32vmovNeg() const {
1581 if (!isImm()) return false;
1582 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1583 // Must be a constant.
1584 if (!CE) return false;
1585 int64_t Value = ~CE->getValue();
1586 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1587 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1588 return (Value >= 0 && Value < 256) ||
1589 (Value >= 0x0100 && Value <= 0xff00) ||
1590 (Value >= 0x010000 && Value <= 0xff0000) ||
1591 (Value >= 0x01000000 && Value <= 0xff000000) ||
1592 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1593 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1596 bool isNEONi64splat() const {
1597 if (!isImm()) return false;
1598 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1599 // Must be a constant.
1600 if (!CE) return false;
1601 uint64_t Value = CE->getValue();
1602 // i64 value with each byte being either 0 or 0xff.
1603 for (unsigned i = 0; i < 8; ++i)
1604 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1608 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1609 // Add as immediates when possible. Null MCExpr = 0.
1611 Inst.addOperand(MCOperand::CreateImm(0));
1612 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1613 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1615 Inst.addOperand(MCOperand::CreateExpr(Expr));
1618 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1619 assert(N == 2 && "Invalid number of operands!");
1620 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1621 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1622 Inst.addOperand(MCOperand::CreateReg(RegNum));
1625 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1626 assert(N == 1 && "Invalid number of operands!");
1627 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1630 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1631 assert(N == 1 && "Invalid number of operands!");
1632 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1635 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1636 assert(N == 1 && "Invalid number of operands!");
1637 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1640 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1641 assert(N == 1 && "Invalid number of operands!");
1642 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1645 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1646 assert(N == 1 && "Invalid number of operands!");
1647 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1650 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1651 assert(N == 1 && "Invalid number of operands!");
1652 Inst.addOperand(MCOperand::CreateReg(getReg()));
1655 void addRegOperands(MCInst &Inst, unsigned N) const {
1656 assert(N == 1 && "Invalid number of operands!");
1657 Inst.addOperand(MCOperand::CreateReg(getReg()));
1660 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1661 assert(N == 3 && "Invalid number of operands!");
1662 assert(isRegShiftedReg() &&
1663 "addRegShiftedRegOperands() on non-RegShiftedReg!");
1664 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1665 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1666 Inst.addOperand(MCOperand::CreateImm(
1667 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1670 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1671 assert(N == 2 && "Invalid number of operands!");
1672 assert(isRegShiftedImm() &&
1673 "addRegShiftedImmOperands() on non-RegShiftedImm!");
1674 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1675 // Shift of #32 is encoded as 0 where permitted
1676 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1677 Inst.addOperand(MCOperand::CreateImm(
1678 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1681 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1682 assert(N == 1 && "Invalid number of operands!");
1683 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1687 void addRegListOperands(MCInst &Inst, unsigned N) const {
1688 assert(N == 1 && "Invalid number of operands!");
1689 const SmallVectorImpl<unsigned> &RegList = getRegList();
1690 for (SmallVectorImpl<unsigned>::const_iterator
1691 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1692 Inst.addOperand(MCOperand::CreateReg(*I));
1695 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1696 addRegListOperands(Inst, N);
1699 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1700 addRegListOperands(Inst, N);
1703 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1704 assert(N == 1 && "Invalid number of operands!");
1705 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1706 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1709 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1710 assert(N == 1 && "Invalid number of operands!");
1711 // Munge the lsb/width into a bitfield mask.
1712 unsigned lsb = Bitfield.LSB;
1713 unsigned width = Bitfield.Width;
1714 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1715 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1716 (32 - (lsb + width)));
1717 Inst.addOperand(MCOperand::CreateImm(Mask));
1720 void addImmOperands(MCInst &Inst, unsigned N) const {
1721 assert(N == 1 && "Invalid number of operands!");
1722 addExpr(Inst, getImm());
1725 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1726 assert(N == 1 && "Invalid number of operands!");
1727 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1728 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1731 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1732 assert(N == 1 && "Invalid number of operands!");
1733 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1734 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1737 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1738 assert(N == 1 && "Invalid number of operands!");
1739 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1740 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1741 Inst.addOperand(MCOperand::CreateImm(Val));
1744 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1745 assert(N == 1 && "Invalid number of operands!");
1746 // FIXME: We really want to scale the value here, but the LDRD/STRD
1747 // instruction don't encode operands that way yet.
1748 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1749 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1752 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1753 assert(N == 1 && "Invalid number of operands!");
1754 // The immediate is scaled by four in the encoding and is stored
1755 // in the MCInst as such. Lop off the low two bits here.
1756 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1757 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1760 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1761 assert(N == 1 && "Invalid number of operands!");
1762 // The immediate is scaled by four in the encoding and is stored
1763 // in the MCInst as such. Lop off the low two bits here.
1764 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1765 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1768 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1769 assert(N == 1 && "Invalid number of operands!");
1770 // The immediate is scaled by four in the encoding and is stored
1771 // in the MCInst as such. Lop off the low two bits here.
1772 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1773 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1776 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1777 assert(N == 1 && "Invalid number of operands!");
1778 // The constant encodes as the immediate-1, and we store in the instruction
1779 // the bits as encoded, so subtract off one here.
1780 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1781 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1784 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1785 assert(N == 1 && "Invalid number of operands!");
1786 // The constant encodes as the immediate-1, and we store in the instruction
1787 // the bits as encoded, so subtract off one here.
1788 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1789 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1792 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1793 assert(N == 1 && "Invalid number of operands!");
1794 // The constant encodes as the immediate, except for 32, which encodes as
1796 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1797 unsigned Imm = CE->getValue();
1798 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1801 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1802 assert(N == 1 && "Invalid number of operands!");
1803 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1804 // the instruction as well.
1805 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1806 int Val = CE->getValue();
1807 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1810 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1811 assert(N == 1 && "Invalid number of operands!");
1812 // The operand is actually a t2_so_imm, but we have its bitwise
1813 // negation in the assembly source, so twiddle it here.
1814 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1815 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1818 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1819 assert(N == 1 && "Invalid number of operands!");
1820 // The operand is actually a t2_so_imm, but we have its
1821 // negation in the assembly source, so twiddle it here.
1822 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1823 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1826 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1827 assert(N == 1 && "Invalid number of operands!");
1828 // The operand is actually an imm0_4095, but we have its
1829 // negation in the assembly source, so twiddle it here.
1830 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1831 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1834 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1835 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1836 Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
1840 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1841 assert(SR && "Unknown value type!");
1842 Inst.addOperand(MCOperand::CreateExpr(SR));
1845 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
1846 assert(N == 1 && "Invalid number of operands!");
1848 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1850 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1854 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1855 assert(SR && "Unknown value type!");
1856 Inst.addOperand(MCOperand::CreateExpr(SR));
1860 assert(isMem() && "Unknown value type!");
1861 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
1862 Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
1865 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1866 assert(N == 1 && "Invalid number of operands!");
1867 // The operand is actually a so_imm, but we have its bitwise
1868 // negation in the assembly source, so twiddle it here.
1869 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1870 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1873 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1874 assert(N == 1 && "Invalid number of operands!");
1875 // The operand is actually a so_imm, but we have its
1876 // negation in the assembly source, so twiddle it here.
1877 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1878 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1881 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1882 assert(N == 1 && "Invalid number of operands!");
1883 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1886 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
1887 assert(N == 1 && "Invalid number of operands!");
1888 Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
1891 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1892 assert(N == 1 && "Invalid number of operands!");
1893 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1896 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1897 assert(N == 1 && "Invalid number of operands!");
1898 int32_t Imm = Memory.OffsetImm->getValue();
1899 Inst.addOperand(MCOperand::CreateImm(Imm));
1902 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1903 assert(N == 1 && "Invalid number of operands!");
1904 assert(isImm() && "Not an immediate!");
1906 // If we have an immediate that's not a constant, treat it as a label
1907 // reference needing a fixup.
1908 if (!isa<MCConstantExpr>(getImm())) {
1909 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1913 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1914 int Val = CE->getValue();
1915 Inst.addOperand(MCOperand::CreateImm(Val));
1918 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1919 assert(N == 2 && "Invalid number of operands!");
1920 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1921 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1924 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1925 assert(N == 3 && "Invalid number of operands!");
1926 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1927 if (!Memory.OffsetRegNum) {
1928 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1929 // Special case for #-0
1930 if (Val == INT32_MIN) Val = 0;
1931 if (Val < 0) Val = -Val;
1932 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1934 // For register offset, we encode the shift type and negation flag
1936 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1937 Memory.ShiftImm, Memory.ShiftType);
1939 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1940 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1941 Inst.addOperand(MCOperand::CreateImm(Val));
1944 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1945 assert(N == 2 && "Invalid number of operands!");
1946 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1947 assert(CE && "non-constant AM2OffsetImm operand!");
1948 int32_t Val = CE->getValue();
1949 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1950 // Special case for #-0
1951 if (Val == INT32_MIN) Val = 0;
1952 if (Val < 0) Val = -Val;
1953 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1954 Inst.addOperand(MCOperand::CreateReg(0));
1955 Inst.addOperand(MCOperand::CreateImm(Val));
1958 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1959 assert(N == 3 && "Invalid number of operands!");
1960 // If we have an immediate that's not a constant, treat it as a label
1961 // reference needing a fixup. If it is a constant, it's something else
1962 // and we reject it.
1964 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1965 Inst.addOperand(MCOperand::CreateReg(0));
1966 Inst.addOperand(MCOperand::CreateImm(0));
1970 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1971 if (!Memory.OffsetRegNum) {
1972 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1973 // Special case for #-0
1974 if (Val == INT32_MIN) Val = 0;
1975 if (Val < 0) Val = -Val;
1976 Val = ARM_AM::getAM3Opc(AddSub, Val);
1978 // For register offset, we encode the shift type and negation flag
1980 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1982 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1983 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1984 Inst.addOperand(MCOperand::CreateImm(Val));
1987 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1988 assert(N == 2 && "Invalid number of operands!");
1989 if (Kind == k_PostIndexRegister) {
1991 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1992 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1993 Inst.addOperand(MCOperand::CreateImm(Val));
1998 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1999 int32_t Val = CE->getValue();
2000 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2001 // Special case for #-0
2002 if (Val == INT32_MIN) Val = 0;
2003 if (Val < 0) Val = -Val;
2004 Val = ARM_AM::getAM3Opc(AddSub, Val);
2005 Inst.addOperand(MCOperand::CreateReg(0));
2006 Inst.addOperand(MCOperand::CreateImm(Val));
2009 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2010 assert(N == 2 && "Invalid number of operands!");
2011 // If we have an immediate that's not a constant, treat it as a label
2012 // reference needing a fixup. If it is a constant, it's something else
2013 // and we reject it.
2015 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2016 Inst.addOperand(MCOperand::CreateImm(0));
2020 // The lower two bits are always zero and as such are not encoded.
2021 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2022 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2023 // Special case for #-0
2024 if (Val == INT32_MIN) Val = 0;
2025 if (Val < 0) Val = -Val;
2026 Val = ARM_AM::getAM5Opc(AddSub, Val);
2027 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2028 Inst.addOperand(MCOperand::CreateImm(Val));
2031 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2032 assert(N == 2 && "Invalid number of operands!");
2033 // If we have an immediate that's not a constant, treat it as a label
2034 // reference needing a fixup. If it is a constant, it's something else
2035 // and we reject it.
2037 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2038 Inst.addOperand(MCOperand::CreateImm(0));
2042 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2043 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2044 Inst.addOperand(MCOperand::CreateImm(Val));
2047 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2048 assert(N == 2 && "Invalid number of operands!");
2049 // The lower two bits are always zero and as such are not encoded.
2050 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2051 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2052 Inst.addOperand(MCOperand::CreateImm(Val));
2055 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2056 assert(N == 2 && "Invalid number of operands!");
2057 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2058 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2059 Inst.addOperand(MCOperand::CreateImm(Val));
2062 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2063 addMemImm8OffsetOperands(Inst, N);
2066 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2067 addMemImm8OffsetOperands(Inst, N);
2070 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2071 assert(N == 2 && "Invalid number of operands!");
2072 // If this is an immediate, it's a label reference.
2074 addExpr(Inst, getImm());
2075 Inst.addOperand(MCOperand::CreateImm(0));
2079 // Otherwise, it's a normal memory reg+offset.
2080 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2081 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2082 Inst.addOperand(MCOperand::CreateImm(Val));
2085 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2086 assert(N == 2 && "Invalid number of operands!");
2087 // If this is an immediate, it's a label reference.
2089 addExpr(Inst, getImm());
2090 Inst.addOperand(MCOperand::CreateImm(0));
2094 // Otherwise, it's a normal memory reg+offset.
2095 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2096 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2097 Inst.addOperand(MCOperand::CreateImm(Val));
2100 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2101 assert(N == 2 && "Invalid number of operands!");
2102 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2103 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2106 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2107 assert(N == 2 && "Invalid number of operands!");
2108 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2109 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2112 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2113 assert(N == 3 && "Invalid number of operands!");
2115 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2116 Memory.ShiftImm, Memory.ShiftType);
2117 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2118 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2119 Inst.addOperand(MCOperand::CreateImm(Val));
2122 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2123 assert(N == 3 && "Invalid number of operands!");
2124 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2125 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2126 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
2129 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2130 assert(N == 2 && "Invalid number of operands!");
2131 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2132 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2135 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2136 assert(N == 2 && "Invalid number of operands!");
2137 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2138 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2139 Inst.addOperand(MCOperand::CreateImm(Val));
2142 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2143 assert(N == 2 && "Invalid number of operands!");
2144 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2145 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2146 Inst.addOperand(MCOperand::CreateImm(Val));
2149 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2150 assert(N == 2 && "Invalid number of operands!");
2151 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2152 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2153 Inst.addOperand(MCOperand::CreateImm(Val));
2156 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2157 assert(N == 2 && "Invalid number of operands!");
2158 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2159 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2160 Inst.addOperand(MCOperand::CreateImm(Val));
2163 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2164 assert(N == 1 && "Invalid number of operands!");
2165 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2166 assert(CE && "non-constant post-idx-imm8 operand!");
2167 int Imm = CE->getValue();
2168 bool isAdd = Imm >= 0;
2169 if (Imm == INT32_MIN) Imm = 0;
2170 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2171 Inst.addOperand(MCOperand::CreateImm(Imm));
2174 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2175 assert(N == 1 && "Invalid number of operands!");
2176 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2177 assert(CE && "non-constant post-idx-imm8s4 operand!");
2178 int Imm = CE->getValue();
2179 bool isAdd = Imm >= 0;
2180 if (Imm == INT32_MIN) Imm = 0;
2181 // Immediate is scaled by 4.
2182 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2183 Inst.addOperand(MCOperand::CreateImm(Imm));
2186 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2187 assert(N == 2 && "Invalid number of operands!");
2188 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2189 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2192 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2193 assert(N == 2 && "Invalid number of operands!");
2194 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2195 // The sign, shift type, and shift amount are encoded in a single operand
2196 // using the AM2 encoding helpers.
2197 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2198 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2199 PostIdxReg.ShiftTy);
2200 Inst.addOperand(MCOperand::CreateImm(Imm));
2203 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2204 assert(N == 1 && "Invalid number of operands!");
2205 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2208 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2209 assert(N == 1 && "Invalid number of operands!");
2210 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2213 void addVecListOperands(MCInst &Inst, unsigned N) const {
2214 assert(N == 1 && "Invalid number of operands!");
2215 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2218 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2219 assert(N == 2 && "Invalid number of operands!");
2220 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2221 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2224 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2225 assert(N == 1 && "Invalid number of operands!");
2226 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2229 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2230 assert(N == 1 && "Invalid number of operands!");
2231 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2234 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2235 assert(N == 1 && "Invalid number of operands!");
2236 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2239 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2240 assert(N == 1 && "Invalid number of operands!");
2241 // The immediate encodes the type of constant as well as the value.
2242 // Mask in that this is an i8 splat.
2243 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2244 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2247 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2248 assert(N == 1 && "Invalid number of operands!");
2249 // The immediate encodes the type of constant as well as the value.
2250 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2251 unsigned Value = CE->getValue();
2253 Value = (Value >> 8) | 0xa00;
2256 Inst.addOperand(MCOperand::CreateImm(Value));
2259 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2260 assert(N == 1 && "Invalid number of operands!");
2261 // The immediate encodes the type of constant as well as the value.
2262 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2263 unsigned Value = CE->getValue();
2264 if (Value >= 256 && Value <= 0xff00)
2265 Value = (Value >> 8) | 0x200;
2266 else if (Value > 0xffff && Value <= 0xff0000)
2267 Value = (Value >> 16) | 0x400;
2268 else if (Value > 0xffffff)
2269 Value = (Value >> 24) | 0x600;
2270 Inst.addOperand(MCOperand::CreateImm(Value));
2273 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2274 assert(N == 1 && "Invalid number of operands!");
2275 // The immediate encodes the type of constant as well as the value.
2276 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2277 unsigned Value = CE->getValue();
2278 if (Value >= 256 && Value <= 0xffff)
2279 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2280 else if (Value > 0xffff && Value <= 0xffffff)
2281 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2282 else if (Value > 0xffffff)
2283 Value = (Value >> 24) | 0x600;
2284 Inst.addOperand(MCOperand::CreateImm(Value));
2287 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2288 assert(N == 1 && "Invalid number of operands!");
2289 // The immediate encodes the type of constant as well as the value.
2290 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2291 unsigned Value = ~CE->getValue();
2292 if (Value >= 256 && Value <= 0xffff)
2293 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2294 else if (Value > 0xffff && Value <= 0xffffff)
2295 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2296 else if (Value > 0xffffff)
2297 Value = (Value >> 24) | 0x600;
2298 Inst.addOperand(MCOperand::CreateImm(Value));
2301 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2302 assert(N == 1 && "Invalid number of operands!");
2303 // The immediate encodes the type of constant as well as the value.
2304 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2305 uint64_t Value = CE->getValue();
2307 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2308 Imm |= (Value & 1) << i;
2310 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2313 virtual void print(raw_ostream &OS) const;
2315 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2316 ARMOperand *Op = new ARMOperand(k_ITCondMask);
2317 Op->ITMask.Mask = Mask;
2323 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2324 ARMOperand *Op = new ARMOperand(k_CondCode);
2331 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2332 ARMOperand *Op = new ARMOperand(k_CoprocNum);
2333 Op->Cop.Val = CopVal;
2339 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2340 ARMOperand *Op = new ARMOperand(k_CoprocReg);
2341 Op->Cop.Val = CopVal;
2347 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2348 ARMOperand *Op = new ARMOperand(k_CoprocOption);
2355 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2356 ARMOperand *Op = new ARMOperand(k_CCOut);
2357 Op->Reg.RegNum = RegNum;
2363 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2364 ARMOperand *Op = new ARMOperand(k_Token);
2365 Op->Tok.Data = Str.data();
2366 Op->Tok.Length = Str.size();
2372 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2373 ARMOperand *Op = new ARMOperand(k_Register);
2374 Op->Reg.RegNum = RegNum;
2380 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2385 ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2386 Op->RegShiftedReg.ShiftTy = ShTy;
2387 Op->RegShiftedReg.SrcReg = SrcReg;
2388 Op->RegShiftedReg.ShiftReg = ShiftReg;
2389 Op->RegShiftedReg.ShiftImm = ShiftImm;
2395 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2399 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2400 Op->RegShiftedImm.ShiftTy = ShTy;
2401 Op->RegShiftedImm.SrcReg = SrcReg;
2402 Op->RegShiftedImm.ShiftImm = ShiftImm;
2408 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2410 ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2411 Op->ShifterImm.isASR = isASR;
2412 Op->ShifterImm.Imm = Imm;
2418 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2419 ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2420 Op->RotImm.Imm = Imm;
2426 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2428 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2429 Op->Bitfield.LSB = LSB;
2430 Op->Bitfield.Width = Width;
2437 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned> > &Regs,
2438 SMLoc StartLoc, SMLoc EndLoc) {
2439 assert (Regs.size() > 0 && "RegList contains no registers?");
2440 KindTy Kind = k_RegisterList;
2442 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2443 Kind = k_DPRRegisterList;
2444 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2445 contains(Regs.front().second))
2446 Kind = k_SPRRegisterList;
2448 // Sort based on the register encoding values.
2449 array_pod_sort(Regs.begin(), Regs.end());
2451 ARMOperand *Op = new ARMOperand(Kind);
2452 for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2453 I = Regs.begin(), E = Regs.end(); I != E; ++I)
2454 Op->Registers.push_back(I->second);
2455 Op->StartLoc = StartLoc;
2456 Op->EndLoc = EndLoc;
2460 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2461 bool isDoubleSpaced, SMLoc S, SMLoc E) {
2462 ARMOperand *Op = new ARMOperand(k_VectorList);
2463 Op->VectorList.RegNum = RegNum;
2464 Op->VectorList.Count = Count;
2465 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2471 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2472 bool isDoubleSpaced,
2474 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2475 Op->VectorList.RegNum = RegNum;
2476 Op->VectorList.Count = Count;
2477 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2483 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2485 bool isDoubleSpaced,
2487 ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2488 Op->VectorList.RegNum = RegNum;
2489 Op->VectorList.Count = Count;
2490 Op->VectorList.LaneIndex = Index;
2491 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2497 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2499 ARMOperand *Op = new ARMOperand(k_VectorIndex);
2500 Op->VectorIndex.Val = Idx;
2506 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2507 ARMOperand *Op = new ARMOperand(k_Immediate);
2514 static ARMOperand *CreateMem(unsigned BaseRegNum,
2515 const MCConstantExpr *OffsetImm,
2516 unsigned OffsetRegNum,
2517 ARM_AM::ShiftOpc ShiftType,
2522 ARMOperand *Op = new ARMOperand(k_Memory);
2523 Op->Memory.BaseRegNum = BaseRegNum;
2524 Op->Memory.OffsetImm = OffsetImm;
2525 Op->Memory.OffsetRegNum = OffsetRegNum;
2526 Op->Memory.ShiftType = ShiftType;
2527 Op->Memory.ShiftImm = ShiftImm;
2528 Op->Memory.Alignment = Alignment;
2529 Op->Memory.isNegative = isNegative;
2535 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2536 ARM_AM::ShiftOpc ShiftTy,
2539 ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2540 Op->PostIdxReg.RegNum = RegNum;
2541 Op->PostIdxReg.isAdd = isAdd;
2542 Op->PostIdxReg.ShiftTy = ShiftTy;
2543 Op->PostIdxReg.ShiftImm = ShiftImm;
2549 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2550 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2551 Op->MBOpt.Val = Opt;
2557 static ARMOperand *CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt,
2559 ARMOperand *Op = new ARMOperand(k_InstSyncBarrierOpt);
2560 Op->ISBOpt.Val = Opt;
2566 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2567 ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2568 Op->IFlags.Val = IFlags;
2574 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2575 ARMOperand *Op = new ARMOperand(k_MSRMask);
2576 Op->MMask.Val = MMask;
2583 } // end anonymous namespace.
2585 void ARMOperand::print(raw_ostream &OS) const {
2588 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2591 OS << "<ccout " << getReg() << ">";
2593 case k_ITCondMask: {
2594 static const char *const MaskStr[] = {
2595 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2596 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2598 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2599 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2603 OS << "<coprocessor number: " << getCoproc() << ">";
2606 OS << "<coprocessor register: " << getCoproc() << ">";
2608 case k_CoprocOption:
2609 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2612 OS << "<mask: " << getMSRMask() << ">";
2615 getImm()->print(OS);
2617 case k_MemBarrierOpt:
2618 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
2620 case k_InstSyncBarrierOpt:
2621 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2625 << " base:" << Memory.BaseRegNum;
2628 case k_PostIndexRegister:
2629 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2630 << PostIdxReg.RegNum;
2631 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2632 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2633 << PostIdxReg.ShiftImm;
2636 case k_ProcIFlags: {
2637 OS << "<ARM_PROC::";
2638 unsigned IFlags = getProcIFlags();
2639 for (int i=2; i >= 0; --i)
2640 if (IFlags & (1 << i))
2641 OS << ARM_PROC::IFlagsToString(1 << i);
2646 OS << "<register " << getReg() << ">";
2648 case k_ShifterImmediate:
2649 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2650 << " #" << ShifterImm.Imm << ">";
2652 case k_ShiftedRegister:
2653 OS << "<so_reg_reg "
2654 << RegShiftedReg.SrcReg << " "
2655 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2656 << " " << RegShiftedReg.ShiftReg << ">";
2658 case k_ShiftedImmediate:
2659 OS << "<so_reg_imm "
2660 << RegShiftedImm.SrcReg << " "
2661 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2662 << " #" << RegShiftedImm.ShiftImm << ">";
2664 case k_RotateImmediate:
2665 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2667 case k_BitfieldDescriptor:
2668 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2669 << ", width: " << Bitfield.Width << ">";
2671 case k_RegisterList:
2672 case k_DPRRegisterList:
2673 case k_SPRRegisterList: {
2674 OS << "<register_list ";
2676 const SmallVectorImpl<unsigned> &RegList = getRegList();
2677 for (SmallVectorImpl<unsigned>::const_iterator
2678 I = RegList.begin(), E = RegList.end(); I != E; ) {
2680 if (++I < E) OS << ", ";
2687 OS << "<vector_list " << VectorList.Count << " * "
2688 << VectorList.RegNum << ">";
2690 case k_VectorListAllLanes:
2691 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2692 << VectorList.RegNum << ">";
2694 case k_VectorListIndexed:
2695 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2696 << VectorList.Count << " * " << VectorList.RegNum << ">";
2699 OS << "'" << getToken() << "'";
2702 OS << "<vectorindex " << getVectorIndex() << ">";
2707 /// @name Auto-generated Match Functions
2710 static unsigned MatchRegisterName(StringRef Name);
2714 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2715 SMLoc &StartLoc, SMLoc &EndLoc) {
2716 StartLoc = Parser.getTok().getLoc();
2717 EndLoc = Parser.getTok().getEndLoc();
2718 RegNo = tryParseRegister();
2720 return (RegNo == (unsigned)-1);
2723 /// Try to parse a register name. The token must be an Identifier when called,
2724 /// and if it is a register name the token is eaten and the register number is
2725 /// returned. Otherwise return -1.
2727 int ARMAsmParser::tryParseRegister() {
2728 const AsmToken &Tok = Parser.getTok();
2729 if (Tok.isNot(AsmToken::Identifier)) return -1;
2731 std::string lowerCase = Tok.getString().lower();
2732 unsigned RegNum = MatchRegisterName(lowerCase);
2734 RegNum = StringSwitch<unsigned>(lowerCase)
2735 .Case("r13", ARM::SP)
2736 .Case("r14", ARM::LR)
2737 .Case("r15", ARM::PC)
2738 .Case("ip", ARM::R12)
2739 // Additional register name aliases for 'gas' compatibility.
2740 .Case("a1", ARM::R0)
2741 .Case("a2", ARM::R1)
2742 .Case("a3", ARM::R2)
2743 .Case("a4", ARM::R3)
2744 .Case("v1", ARM::R4)
2745 .Case("v2", ARM::R5)
2746 .Case("v3", ARM::R6)
2747 .Case("v4", ARM::R7)
2748 .Case("v5", ARM::R8)
2749 .Case("v6", ARM::R9)
2750 .Case("v7", ARM::R10)
2751 .Case("v8", ARM::R11)
2752 .Case("sb", ARM::R9)
2753 .Case("sl", ARM::R10)
2754 .Case("fp", ARM::R11)
2758 // Check for aliases registered via .req. Canonicalize to lower case.
2759 // That's more consistent since register names are case insensitive, and
2760 // it's how the original entry was passed in from MC/MCParser/AsmParser.
2761 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2762 // If no match, return failure.
2763 if (Entry == RegisterReqs.end())
2765 Parser.Lex(); // Eat identifier token.
2766 return Entry->getValue();
2769 Parser.Lex(); // Eat identifier token.
2774 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
2775 // If a recoverable error occurs, return 1. If an irrecoverable error
2776 // occurs, return -1. An irrecoverable error is one where tokens have been
2777 // consumed in the process of trying to parse the shifter (i.e., when it is
2778 // indeed a shifter operand, but malformed).
2779 int ARMAsmParser::tryParseShiftRegister(
2780 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2781 SMLoc S = Parser.getTok().getLoc();
2782 const AsmToken &Tok = Parser.getTok();
2783 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2785 std::string lowerCase = Tok.getString().lower();
2786 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2787 .Case("asl", ARM_AM::lsl)
2788 .Case("lsl", ARM_AM::lsl)
2789 .Case("lsr", ARM_AM::lsr)
2790 .Case("asr", ARM_AM::asr)
2791 .Case("ror", ARM_AM::ror)
2792 .Case("rrx", ARM_AM::rrx)
2793 .Default(ARM_AM::no_shift);
2795 if (ShiftTy == ARM_AM::no_shift)
2798 Parser.Lex(); // Eat the operator.
2800 // The source register for the shift has already been added to the
2801 // operand list, so we need to pop it off and combine it into the shifted
2802 // register operand instead.
2803 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2804 if (!PrevOp->isReg())
2805 return Error(PrevOp->getStartLoc(), "shift must be of a register");
2806 int SrcReg = PrevOp->getReg();
2811 if (ShiftTy == ARM_AM::rrx) {
2812 // RRX Doesn't have an explicit shift amount. The encoder expects
2813 // the shift register to be the same as the source register. Seems odd,
2817 // Figure out if this is shifted by a constant or a register (for non-RRX).
2818 if (Parser.getTok().is(AsmToken::Hash) ||
2819 Parser.getTok().is(AsmToken::Dollar)) {
2820 Parser.Lex(); // Eat hash.
2821 SMLoc ImmLoc = Parser.getTok().getLoc();
2822 const MCExpr *ShiftExpr = 0;
2823 if (getParser().parseExpression(ShiftExpr, EndLoc)) {
2824 Error(ImmLoc, "invalid immediate shift value");
2827 // The expression must be evaluatable as an immediate.
2828 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2830 Error(ImmLoc, "invalid immediate shift value");
2833 // Range check the immediate.
2834 // lsl, ror: 0 <= imm <= 31
2835 // lsr, asr: 0 <= imm <= 32
2836 Imm = CE->getValue();
2838 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2839 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2840 Error(ImmLoc, "immediate shift value out of range");
2843 // shift by zero is a nop. Always send it through as lsl.
2844 // ('as' compatibility)
2846 ShiftTy = ARM_AM::lsl;
2847 } else if (Parser.getTok().is(AsmToken::Identifier)) {
2848 SMLoc L = Parser.getTok().getLoc();
2849 EndLoc = Parser.getTok().getEndLoc();
2850 ShiftReg = tryParseRegister();
2851 if (ShiftReg == -1) {
2852 Error (L, "expected immediate or register in shift operand");
2856 Error (Parser.getTok().getLoc(),
2857 "expected immediate or register in shift operand");
2862 if (ShiftReg && ShiftTy != ARM_AM::rrx)
2863 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2867 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2874 /// Try to parse a register name. The token must be an Identifier when called.
2875 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
2876 /// if there is a "writeback". 'true' if it's not a register.
2878 /// TODO this is likely to change to allow different register types and or to
2879 /// parse for a specific register type.
2881 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2882 const AsmToken &RegTok = Parser.getTok();
2883 int RegNo = tryParseRegister();
2887 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
2888 RegTok.getEndLoc()));
2890 const AsmToken &ExclaimTok = Parser.getTok();
2891 if (ExclaimTok.is(AsmToken::Exclaim)) {
2892 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2893 ExclaimTok.getLoc()));
2894 Parser.Lex(); // Eat exclaim token
2898 // Also check for an index operand. This is only legal for vector registers,
2899 // but that'll get caught OK in operand matching, so we don't need to
2900 // explicitly filter everything else out here.
2901 if (Parser.getTok().is(AsmToken::LBrac)) {
2902 SMLoc SIdx = Parser.getTok().getLoc();
2903 Parser.Lex(); // Eat left bracket token.
2905 const MCExpr *ImmVal;
2906 if (getParser().parseExpression(ImmVal))
2908 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2910 return TokError("immediate value expected for vector index");
2912 if (Parser.getTok().isNot(AsmToken::RBrac))
2913 return Error(Parser.getTok().getLoc(), "']' expected");
2915 SMLoc E = Parser.getTok().getEndLoc();
2916 Parser.Lex(); // Eat right bracket token.
2918 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2926 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
2927 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2929 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2930 // Use the same layout as the tablegen'erated register name matcher. Ugly,
2932 switch (Name.size()) {
2935 if (Name[0] != CoprocOp)
2951 if (Name[0] != CoprocOp || Name[1] != '1')
2955 // p10 and p11 are invalid for coproc instructions (reserved for FP/NEON)
2956 case '0': return CoprocOp == 'p'? -1: 10;
2957 case '1': return CoprocOp == 'p'? -1: 11;
2958 case '2': return 12;
2959 case '3': return 13;
2960 case '4': return 14;
2961 case '5': return 15;
2966 /// parseITCondCode - Try to parse a condition code for an IT instruction.
2967 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2968 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2969 SMLoc S = Parser.getTok().getLoc();
2970 const AsmToken &Tok = Parser.getTok();
2971 if (!Tok.is(AsmToken::Identifier))
2972 return MatchOperand_NoMatch;
2973 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
2974 .Case("eq", ARMCC::EQ)
2975 .Case("ne", ARMCC::NE)
2976 .Case("hs", ARMCC::HS)
2977 .Case("cs", ARMCC::HS)
2978 .Case("lo", ARMCC::LO)
2979 .Case("cc", ARMCC::LO)
2980 .Case("mi", ARMCC::MI)
2981 .Case("pl", ARMCC::PL)
2982 .Case("vs", ARMCC::VS)
2983 .Case("vc", ARMCC::VC)
2984 .Case("hi", ARMCC::HI)
2985 .Case("ls", ARMCC::LS)
2986 .Case("ge", ARMCC::GE)
2987 .Case("lt", ARMCC::LT)
2988 .Case("gt", ARMCC::GT)
2989 .Case("le", ARMCC::LE)
2990 .Case("al", ARMCC::AL)
2993 return MatchOperand_NoMatch;
2994 Parser.Lex(); // Eat the token.
2996 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2998 return MatchOperand_Success;
3001 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
3002 /// token must be an Identifier when called, and if it is a coprocessor
3003 /// number, the token is eaten and the operand is added to the operand list.
3004 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3005 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3006 SMLoc S = Parser.getTok().getLoc();
3007 const AsmToken &Tok = Parser.getTok();
3008 if (Tok.isNot(AsmToken::Identifier))
3009 return MatchOperand_NoMatch;
3011 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
3013 return MatchOperand_NoMatch;
3015 Parser.Lex(); // Eat identifier token.
3016 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
3017 return MatchOperand_Success;
3020 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
3021 /// token must be an Identifier when called, and if it is a coprocessor
3022 /// number, the token is eaten and the operand is added to the operand list.
3023 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3024 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3025 SMLoc S = Parser.getTok().getLoc();
3026 const AsmToken &Tok = Parser.getTok();
3027 if (Tok.isNot(AsmToken::Identifier))
3028 return MatchOperand_NoMatch;
3030 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
3032 return MatchOperand_NoMatch;
3034 Parser.Lex(); // Eat identifier token.
3035 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
3036 return MatchOperand_Success;
3039 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
3040 /// coproc_option : '{' imm0_255 '}'
3041 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3042 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3043 SMLoc S = Parser.getTok().getLoc();
3045 // If this isn't a '{', this isn't a coprocessor immediate operand.
3046 if (Parser.getTok().isNot(AsmToken::LCurly))
3047 return MatchOperand_NoMatch;
3048 Parser.Lex(); // Eat the '{'
3051 SMLoc Loc = Parser.getTok().getLoc();
3052 if (getParser().parseExpression(Expr)) {
3053 Error(Loc, "illegal expression");
3054 return MatchOperand_ParseFail;
3056 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3057 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
3058 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
3059 return MatchOperand_ParseFail;
3061 int Val = CE->getValue();
3063 // Check for and consume the closing '}'
3064 if (Parser.getTok().isNot(AsmToken::RCurly))
3065 return MatchOperand_ParseFail;
3066 SMLoc E = Parser.getTok().getEndLoc();
3067 Parser.Lex(); // Eat the '}'
3069 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
3070 return MatchOperand_Success;
3073 // For register list parsing, we need to map from raw GPR register numbering
3074 // to the enumeration values. The enumeration values aren't sorted by
3075 // register number due to our using "sp", "lr" and "pc" as canonical names.
3076 static unsigned getNextRegister(unsigned Reg) {
3077 // If this is a GPR, we need to do it manually, otherwise we can rely
3078 // on the sort ordering of the enumeration since the other reg-classes
3080 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3083 default: llvm_unreachable("Invalid GPR number!");
3084 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
3085 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
3086 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
3087 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
3088 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
3089 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3090 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
3091 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
3095 // Return the low-subreg of a given Q register.
3096 static unsigned getDRegFromQReg(unsigned QReg) {
3098 default: llvm_unreachable("expected a Q register!");
3099 case ARM::Q0: return ARM::D0;
3100 case ARM::Q1: return ARM::D2;
3101 case ARM::Q2: return ARM::D4;
3102 case ARM::Q3: return ARM::D6;
3103 case ARM::Q4: return ARM::D8;
3104 case ARM::Q5: return ARM::D10;
3105 case ARM::Q6: return ARM::D12;
3106 case ARM::Q7: return ARM::D14;
3107 case ARM::Q8: return ARM::D16;
3108 case ARM::Q9: return ARM::D18;
3109 case ARM::Q10: return ARM::D20;
3110 case ARM::Q11: return ARM::D22;
3111 case ARM::Q12: return ARM::D24;
3112 case ARM::Q13: return ARM::D26;
3113 case ARM::Q14: return ARM::D28;
3114 case ARM::Q15: return ARM::D30;
3118 /// Parse a register list.
3120 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3121 assert(Parser.getTok().is(AsmToken::LCurly) &&
3122 "Token is not a Left Curly Brace");
3123 SMLoc S = Parser.getTok().getLoc();
3124 Parser.Lex(); // Eat '{' token.
3125 SMLoc RegLoc = Parser.getTok().getLoc();
3127 // Check the first register in the list to see what register class
3128 // this is a list of.
3129 int Reg = tryParseRegister();
3131 return Error(RegLoc, "register expected");
3133 // The reglist instructions have at most 16 registers, so reserve
3134 // space for that many.
3136 SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3138 // Allow Q regs and just interpret them as the two D sub-registers.
3139 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3140 Reg = getDRegFromQReg(Reg);
3141 EReg = MRI->getEncodingValue(Reg);
3142 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3145 const MCRegisterClass *RC;
3146 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3147 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3148 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3149 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3150 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3151 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3153 return Error(RegLoc, "invalid register in register list");
3155 // Store the register.
3156 EReg = MRI->getEncodingValue(Reg);
3157 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3159 // This starts immediately after the first register token in the list,
3160 // so we can see either a comma or a minus (range separator) as a legal
3162 while (Parser.getTok().is(AsmToken::Comma) ||
3163 Parser.getTok().is(AsmToken::Minus)) {
3164 if (Parser.getTok().is(AsmToken::Minus)) {
3165 Parser.Lex(); // Eat the minus.
3166 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3167 int EndReg = tryParseRegister();
3169 return Error(AfterMinusLoc, "register expected");
3170 // Allow Q regs and just interpret them as the two D sub-registers.
3171 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3172 EndReg = getDRegFromQReg(EndReg) + 1;
3173 // If the register is the same as the start reg, there's nothing
3177 // The register must be in the same register class as the first.
3178 if (!RC->contains(EndReg))
3179 return Error(AfterMinusLoc, "invalid register in register list");
3180 // Ranges must go from low to high.
3181 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3182 return Error(AfterMinusLoc, "bad range in register list");
3184 // Add all the registers in the range to the register list.
3185 while (Reg != EndReg) {
3186 Reg = getNextRegister(Reg);
3187 EReg = MRI->getEncodingValue(Reg);
3188 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3192 Parser.Lex(); // Eat the comma.
3193 RegLoc = Parser.getTok().getLoc();
3195 const AsmToken RegTok = Parser.getTok();
3196 Reg = tryParseRegister();
3198 return Error(RegLoc, "register expected");
3199 // Allow Q regs and just interpret them as the two D sub-registers.
3200 bool isQReg = false;
3201 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3202 Reg = getDRegFromQReg(Reg);
3205 // The register must be in the same register class as the first.
3206 if (!RC->contains(Reg))
3207 return Error(RegLoc, "invalid register in register list");
3208 // List must be monotonically increasing.
3209 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3210 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3211 Warning(RegLoc, "register list not in ascending order");
3213 return Error(RegLoc, "register list not in ascending order");
3215 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3216 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3217 ") in register list");
3220 // VFP register lists must also be contiguous.
3221 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3223 return Error(RegLoc, "non-contiguous register range");
3224 EReg = MRI->getEncodingValue(Reg);
3225 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3227 EReg = MRI->getEncodingValue(++Reg);
3228 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3232 if (Parser.getTok().isNot(AsmToken::RCurly))
3233 return Error(Parser.getTok().getLoc(), "'}' expected");
3234 SMLoc E = Parser.getTok().getEndLoc();
3235 Parser.Lex(); // Eat '}' token.
3237 // Push the register list operand.
3238 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3240 // The ARM system instruction variants for LDM/STM have a '^' token here.
3241 if (Parser.getTok().is(AsmToken::Caret)) {
3242 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3243 Parser.Lex(); // Eat '^' token.
3249 // Helper function to parse the lane index for vector lists.
3250 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3251 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3252 Index = 0; // Always return a defined index value.
3253 if (Parser.getTok().is(AsmToken::LBrac)) {
3254 Parser.Lex(); // Eat the '['.
3255 if (Parser.getTok().is(AsmToken::RBrac)) {
3256 // "Dn[]" is the 'all lanes' syntax.
3257 LaneKind = AllLanes;
3258 EndLoc = Parser.getTok().getEndLoc();
3259 Parser.Lex(); // Eat the ']'.
3260 return MatchOperand_Success;
3263 // There's an optional '#' token here. Normally there wouldn't be, but
3264 // inline assemble puts one in, and it's friendly to accept that.
3265 if (Parser.getTok().is(AsmToken::Hash))
3266 Parser.Lex(); // Eat '#' or '$'.
3268 const MCExpr *LaneIndex;
3269 SMLoc Loc = Parser.getTok().getLoc();
3270 if (getParser().parseExpression(LaneIndex)) {
3271 Error(Loc, "illegal expression");
3272 return MatchOperand_ParseFail;
3274 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3276 Error(Loc, "lane index must be empty or an integer");
3277 return MatchOperand_ParseFail;
3279 if (Parser.getTok().isNot(AsmToken::RBrac)) {
3280 Error(Parser.getTok().getLoc(), "']' expected");
3281 return MatchOperand_ParseFail;
3283 EndLoc = Parser.getTok().getEndLoc();
3284 Parser.Lex(); // Eat the ']'.
3285 int64_t Val = CE->getValue();
3287 // FIXME: Make this range check context sensitive for .8, .16, .32.
3288 if (Val < 0 || Val > 7) {
3289 Error(Parser.getTok().getLoc(), "lane index out of range");
3290 return MatchOperand_ParseFail;
3293 LaneKind = IndexedLane;
3294 return MatchOperand_Success;
3297 return MatchOperand_Success;
3300 // parse a vector register list
3301 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3302 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3303 VectorLaneTy LaneKind;
3305 SMLoc S = Parser.getTok().getLoc();
3306 // As an extension (to match gas), support a plain D register or Q register
3307 // (without encosing curly braces) as a single or double entry list,
3309 if (Parser.getTok().is(AsmToken::Identifier)) {
3310 SMLoc E = Parser.getTok().getEndLoc();
3311 int Reg = tryParseRegister();
3313 return MatchOperand_NoMatch;
3314 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3315 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3316 if (Res != MatchOperand_Success)
3320 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3323 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3327 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3332 return MatchOperand_Success;
3334 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3335 Reg = getDRegFromQReg(Reg);
3336 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3337 if (Res != MatchOperand_Success)
3341 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3342 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3343 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3346 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3347 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3348 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3352 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3357 return MatchOperand_Success;
3359 Error(S, "vector register expected");
3360 return MatchOperand_ParseFail;
3363 if (Parser.getTok().isNot(AsmToken::LCurly))
3364 return MatchOperand_NoMatch;
3366 Parser.Lex(); // Eat '{' token.
3367 SMLoc RegLoc = Parser.getTok().getLoc();
3369 int Reg = tryParseRegister();
3371 Error(RegLoc, "register expected");
3372 return MatchOperand_ParseFail;
3376 unsigned FirstReg = Reg;
3377 // The list is of D registers, but we also allow Q regs and just interpret
3378 // them as the two D sub-registers.
3379 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3380 FirstReg = Reg = getDRegFromQReg(Reg);
3381 Spacing = 1; // double-spacing requires explicit D registers, otherwise
3382 // it's ambiguous with four-register single spaced.
3388 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3389 return MatchOperand_ParseFail;
3391 while (Parser.getTok().is(AsmToken::Comma) ||
3392 Parser.getTok().is(AsmToken::Minus)) {
3393 if (Parser.getTok().is(AsmToken::Minus)) {
3395 Spacing = 1; // Register range implies a single spaced list.
3396 else if (Spacing == 2) {
3397 Error(Parser.getTok().getLoc(),
3398 "sequential registers in double spaced list");
3399 return MatchOperand_ParseFail;
3401 Parser.Lex(); // Eat the minus.
3402 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3403 int EndReg = tryParseRegister();
3405 Error(AfterMinusLoc, "register expected");
3406 return MatchOperand_ParseFail;
3408 // Allow Q regs and just interpret them as the two D sub-registers.
3409 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3410 EndReg = getDRegFromQReg(EndReg) + 1;
3411 // If the register is the same as the start reg, there's nothing
3415 // The register must be in the same register class as the first.
3416 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3417 Error(AfterMinusLoc, "invalid register in register list");
3418 return MatchOperand_ParseFail;
3420 // Ranges must go from low to high.
3422 Error(AfterMinusLoc, "bad range in register list");
3423 return MatchOperand_ParseFail;
3425 // Parse the lane specifier if present.
3426 VectorLaneTy NextLaneKind;
3427 unsigned NextLaneIndex;
3428 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3429 MatchOperand_Success)
3430 return MatchOperand_ParseFail;
3431 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3432 Error(AfterMinusLoc, "mismatched lane index in register list");
3433 return MatchOperand_ParseFail;
3436 // Add all the registers in the range to the register list.
3437 Count += EndReg - Reg;
3441 Parser.Lex(); // Eat the comma.
3442 RegLoc = Parser.getTok().getLoc();
3444 Reg = tryParseRegister();
3446 Error(RegLoc, "register expected");
3447 return MatchOperand_ParseFail;
3449 // vector register lists must be contiguous.
3450 // It's OK to use the enumeration values directly here rather, as the
3451 // VFP register classes have the enum sorted properly.
3453 // The list is of D registers, but we also allow Q regs and just interpret
3454 // them as the two D sub-registers.
3455 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3457 Spacing = 1; // Register range implies a single spaced list.
3458 else if (Spacing == 2) {
3460 "invalid register in double-spaced list (must be 'D' register')");
3461 return MatchOperand_ParseFail;
3463 Reg = getDRegFromQReg(Reg);
3464 if (Reg != OldReg + 1) {
3465 Error(RegLoc, "non-contiguous register range");
3466 return MatchOperand_ParseFail;
3470 // Parse the lane specifier if present.
3471 VectorLaneTy NextLaneKind;
3472 unsigned NextLaneIndex;
3473 SMLoc LaneLoc = Parser.getTok().getLoc();
3474 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3475 MatchOperand_Success)
3476 return MatchOperand_ParseFail;
3477 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3478 Error(LaneLoc, "mismatched lane index in register list");
3479 return MatchOperand_ParseFail;
3483 // Normal D register.
3484 // Figure out the register spacing (single or double) of the list if
3485 // we don't know it already.
3487 Spacing = 1 + (Reg == OldReg + 2);
3489 // Just check that it's contiguous and keep going.
3490 if (Reg != OldReg + Spacing) {
3491 Error(RegLoc, "non-contiguous register range");
3492 return MatchOperand_ParseFail;
3495 // Parse the lane specifier if present.
3496 VectorLaneTy NextLaneKind;
3497 unsigned NextLaneIndex;
3498 SMLoc EndLoc = Parser.getTok().getLoc();
3499 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3500 return MatchOperand_ParseFail;
3501 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3502 Error(EndLoc, "mismatched lane index in register list");
3503 return MatchOperand_ParseFail;
3507 if (Parser.getTok().isNot(AsmToken::RCurly)) {
3508 Error(Parser.getTok().getLoc(), "'}' expected");
3509 return MatchOperand_ParseFail;
3511 E = Parser.getTok().getEndLoc();
3512 Parser.Lex(); // Eat '}' token.
3516 // Two-register operands have been converted to the
3517 // composite register classes.
3519 const MCRegisterClass *RC = (Spacing == 1) ?
3520 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3521 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3522 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3525 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3526 (Spacing == 2), S, E));
3529 // Two-register operands have been converted to the
3530 // composite register classes.
3532 const MCRegisterClass *RC = (Spacing == 1) ?
3533 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3534 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3535 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3537 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3542 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3548 return MatchOperand_Success;
3551 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3552 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3553 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3554 SMLoc S = Parser.getTok().getLoc();
3555 const AsmToken &Tok = Parser.getTok();
3558 if (Tok.is(AsmToken::Identifier)) {
3559 StringRef OptStr = Tok.getString();
3561 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3562 .Case("sy", ARM_MB::SY)
3563 .Case("st", ARM_MB::ST)
3564 .Case("ld", ARM_MB::LD)
3565 .Case("sh", ARM_MB::ISH)
3566 .Case("ish", ARM_MB::ISH)
3567 .Case("shst", ARM_MB::ISHST)
3568 .Case("ishst", ARM_MB::ISHST)
3569 .Case("ishld", ARM_MB::ISHLD)
3570 .Case("nsh", ARM_MB::NSH)
3571 .Case("un", ARM_MB::NSH)
3572 .Case("nshst", ARM_MB::NSHST)
3573 .Case("nshld", ARM_MB::NSHLD)
3574 .Case("unst", ARM_MB::NSHST)
3575 .Case("osh", ARM_MB::OSH)
3576 .Case("oshst", ARM_MB::OSHST)
3577 .Case("oshld", ARM_MB::OSHLD)
3580 // ishld, oshld, nshld and ld are only available from ARMv8.
3581 if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
3582 Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
3586 return MatchOperand_NoMatch;
3588 Parser.Lex(); // Eat identifier token.
3589 } else if (Tok.is(AsmToken::Hash) ||
3590 Tok.is(AsmToken::Dollar) ||
3591 Tok.is(AsmToken::Integer)) {
3592 if (Parser.getTok().isNot(AsmToken::Integer))
3593 Parser.Lex(); // Eat '#' or '$'.
3594 SMLoc Loc = Parser.getTok().getLoc();
3596 const MCExpr *MemBarrierID;
3597 if (getParser().parseExpression(MemBarrierID)) {
3598 Error(Loc, "illegal expression");
3599 return MatchOperand_ParseFail;
3602 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3604 Error(Loc, "constant expression expected");
3605 return MatchOperand_ParseFail;
3608 int Val = CE->getValue();
3610 Error(Loc, "immediate value out of range");
3611 return MatchOperand_ParseFail;
3614 Opt = ARM_MB::RESERVED_0 + Val;
3616 return MatchOperand_ParseFail;
3618 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3619 return MatchOperand_Success;
3622 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3623 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3624 parseInstSyncBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3625 SMLoc S = Parser.getTok().getLoc();
3626 const AsmToken &Tok = Parser.getTok();
3629 if (Tok.is(AsmToken::Identifier)) {
3630 StringRef OptStr = Tok.getString();
3632 if (OptStr.equals_lower("sy"))
3635 return MatchOperand_NoMatch;
3637 Parser.Lex(); // Eat identifier token.
3638 } else if (Tok.is(AsmToken::Hash) ||
3639 Tok.is(AsmToken::Dollar) ||
3640 Tok.is(AsmToken::Integer)) {
3641 if (Parser.getTok().isNot(AsmToken::Integer))
3642 Parser.Lex(); // Eat '#' or '$'.
3643 SMLoc Loc = Parser.getTok().getLoc();
3645 const MCExpr *ISBarrierID;
3646 if (getParser().parseExpression(ISBarrierID)) {
3647 Error(Loc, "illegal expression");
3648 return MatchOperand_ParseFail;
3651 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3653 Error(Loc, "constant expression expected");
3654 return MatchOperand_ParseFail;
3657 int Val = CE->getValue();
3659 Error(Loc, "immediate value out of range");
3660 return MatchOperand_ParseFail;
3663 Opt = ARM_ISB::RESERVED_0 + Val;
3665 return MatchOperand_ParseFail;
3667 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3668 (ARM_ISB::InstSyncBOpt)Opt, S));
3669 return MatchOperand_Success;
3673 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3674 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3675 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3676 SMLoc S = Parser.getTok().getLoc();
3677 const AsmToken &Tok = Parser.getTok();
3678 if (!Tok.is(AsmToken::Identifier))
3679 return MatchOperand_NoMatch;
3680 StringRef IFlagsStr = Tok.getString();
3682 // An iflags string of "none" is interpreted to mean that none of the AIF
3683 // bits are set. Not a terribly useful instruction, but a valid encoding.
3684 unsigned IFlags = 0;
3685 if (IFlagsStr != "none") {
3686 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3687 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3688 .Case("a", ARM_PROC::A)
3689 .Case("i", ARM_PROC::I)
3690 .Case("f", ARM_PROC::F)
3693 // If some specific iflag is already set, it means that some letter is
3694 // present more than once, this is not acceptable.
3695 if (Flag == ~0U || (IFlags & Flag))
3696 return MatchOperand_NoMatch;
3702 Parser.Lex(); // Eat identifier token.
3703 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3704 return MatchOperand_Success;
3707 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3708 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3709 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3710 SMLoc S = Parser.getTok().getLoc();
3711 const AsmToken &Tok = Parser.getTok();
3712 if (!Tok.is(AsmToken::Identifier))
3713 return MatchOperand_NoMatch;
3714 StringRef Mask = Tok.getString();
3717 // See ARMv6-M 10.1.1
3718 std::string Name = Mask.lower();
3719 unsigned FlagsVal = StringSwitch<unsigned>(Name)
3720 // Note: in the documentation:
3721 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3722 // for MSR APSR_nzcvq.
3723 // but we do make it an alias here. This is so to get the "mask encoding"
3724 // bits correct on MSR APSR writes.
3726 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3727 // should really only be allowed when writing a special register. Note
3728 // they get dropped in the MRS instruction reading a special register as
3729 // the SYSm field is only 8 bits.
3731 // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3732 // includes the DSP extension but that is not checked.
3733 .Case("apsr", 0x800)
3734 .Case("apsr_nzcvq", 0x800)
3735 .Case("apsr_g", 0x400)
3736 .Case("apsr_nzcvqg", 0xc00)
3737 .Case("iapsr", 0x801)
3738 .Case("iapsr_nzcvq", 0x801)
3739 .Case("iapsr_g", 0x401)
3740 .Case("iapsr_nzcvqg", 0xc01)
3741 .Case("eapsr", 0x802)
3742 .Case("eapsr_nzcvq", 0x802)
3743 .Case("eapsr_g", 0x402)
3744 .Case("eapsr_nzcvqg", 0xc02)
3745 .Case("xpsr", 0x803)
3746 .Case("xpsr_nzcvq", 0x803)
3747 .Case("xpsr_g", 0x403)
3748 .Case("xpsr_nzcvqg", 0xc03)
3749 .Case("ipsr", 0x805)
3750 .Case("epsr", 0x806)
3751 .Case("iepsr", 0x807)
3754 .Case("primask", 0x810)
3755 .Case("basepri", 0x811)
3756 .Case("basepri_max", 0x812)
3757 .Case("faultmask", 0x813)
3758 .Case("control", 0x814)
3761 if (FlagsVal == ~0U)
3762 return MatchOperand_NoMatch;
3764 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3765 // basepri, basepri_max and faultmask only valid for V7m.
3766 return MatchOperand_NoMatch;
3768 Parser.Lex(); // Eat identifier token.
3769 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3770 return MatchOperand_Success;
3773 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3774 size_t Start = 0, Next = Mask.find('_');
3775 StringRef Flags = "";
3776 std::string SpecReg = Mask.slice(Start, Next).lower();
3777 if (Next != StringRef::npos)
3778 Flags = Mask.slice(Next+1, Mask.size());
3780 // FlagsVal contains the complete mask:
3782 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3783 unsigned FlagsVal = 0;
3785 if (SpecReg == "apsr") {
3786 FlagsVal = StringSwitch<unsigned>(Flags)
3787 .Case("nzcvq", 0x8) // same as CPSR_f
3788 .Case("g", 0x4) // same as CPSR_s
3789 .Case("nzcvqg", 0xc) // same as CPSR_fs
3792 if (FlagsVal == ~0U) {
3794 return MatchOperand_NoMatch;
3796 FlagsVal = 8; // No flag
3798 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3799 // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3800 if (Flags == "all" || Flags == "")
3802 for (int i = 0, e = Flags.size(); i != e; ++i) {
3803 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3810 // If some specific flag is already set, it means that some letter is
3811 // present more than once, this is not acceptable.
3812 if (FlagsVal == ~0U || (FlagsVal & Flag))
3813 return MatchOperand_NoMatch;
3816 } else // No match for special register.
3817 return MatchOperand_NoMatch;
3819 // Special register without flags is NOT equivalent to "fc" flags.
3820 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
3821 // two lines would enable gas compatibility at the expense of breaking
3827 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3828 if (SpecReg == "spsr")
3831 Parser.Lex(); // Eat identifier token.
3832 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3833 return MatchOperand_Success;
3836 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3837 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3838 int Low, int High) {
3839 const AsmToken &Tok = Parser.getTok();
3840 if (Tok.isNot(AsmToken::Identifier)) {
3841 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3842 return MatchOperand_ParseFail;
3844 StringRef ShiftName = Tok.getString();
3845 std::string LowerOp = Op.lower();
3846 std::string UpperOp = Op.upper();
3847 if (ShiftName != LowerOp && ShiftName != UpperOp) {
3848 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3849 return MatchOperand_ParseFail;
3851 Parser.Lex(); // Eat shift type token.
3853 // There must be a '#' and a shift amount.
3854 if (Parser.getTok().isNot(AsmToken::Hash) &&
3855 Parser.getTok().isNot(AsmToken::Dollar)) {
3856 Error(Parser.getTok().getLoc(), "'#' expected");
3857 return MatchOperand_ParseFail;
3859 Parser.Lex(); // Eat hash token.
3861 const MCExpr *ShiftAmount;
3862 SMLoc Loc = Parser.getTok().getLoc();
3864 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3865 Error(Loc, "illegal expression");
3866 return MatchOperand_ParseFail;
3868 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3870 Error(Loc, "constant expression expected");
3871 return MatchOperand_ParseFail;
3873 int Val = CE->getValue();
3874 if (Val < Low || Val > High) {
3875 Error(Loc, "immediate value out of range");
3876 return MatchOperand_ParseFail;
3879 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
3881 return MatchOperand_Success;
3884 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3885 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3886 const AsmToken &Tok = Parser.getTok();
3887 SMLoc S = Tok.getLoc();
3888 if (Tok.isNot(AsmToken::Identifier)) {
3889 Error(S, "'be' or 'le' operand expected");
3890 return MatchOperand_ParseFail;
3892 int Val = StringSwitch<int>(Tok.getString().lower())
3896 Parser.Lex(); // Eat the token.
3899 Error(S, "'be' or 'le' operand expected");
3900 return MatchOperand_ParseFail;
3902 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3904 S, Tok.getEndLoc()));
3905 return MatchOperand_Success;
3908 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3909 /// instructions. Legal values are:
3910 /// lsl #n 'n' in [0,31]
3911 /// asr #n 'n' in [1,32]
3912 /// n == 32 encoded as n == 0.
3913 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3914 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3915 const AsmToken &Tok = Parser.getTok();
3916 SMLoc S = Tok.getLoc();
3917 if (Tok.isNot(AsmToken::Identifier)) {
3918 Error(S, "shift operator 'asr' or 'lsl' expected");
3919 return MatchOperand_ParseFail;
3921 StringRef ShiftName = Tok.getString();
3923 if (ShiftName == "lsl" || ShiftName == "LSL")
3925 else if (ShiftName == "asr" || ShiftName == "ASR")
3928 Error(S, "shift operator 'asr' or 'lsl' expected");
3929 return MatchOperand_ParseFail;
3931 Parser.Lex(); // Eat the operator.
3933 // A '#' and a shift amount.
3934 if (Parser.getTok().isNot(AsmToken::Hash) &&
3935 Parser.getTok().isNot(AsmToken::Dollar)) {
3936 Error(Parser.getTok().getLoc(), "'#' expected");
3937 return MatchOperand_ParseFail;
3939 Parser.Lex(); // Eat hash token.
3940 SMLoc ExLoc = Parser.getTok().getLoc();
3942 const MCExpr *ShiftAmount;
3944 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3945 Error(ExLoc, "malformed shift expression");
3946 return MatchOperand_ParseFail;
3948 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3950 Error(ExLoc, "shift amount must be an immediate");
3951 return MatchOperand_ParseFail;
3954 int64_t Val = CE->getValue();
3956 // Shift amount must be in [1,32]
3957 if (Val < 1 || Val > 32) {
3958 Error(ExLoc, "'asr' shift amount must be in range [1,32]");
3959 return MatchOperand_ParseFail;
3961 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3962 if (isThumb() && Val == 32) {
3963 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
3964 return MatchOperand_ParseFail;
3966 if (Val == 32) Val = 0;
3968 // Shift amount must be in [1,32]
3969 if (Val < 0 || Val > 31) {
3970 Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
3971 return MatchOperand_ParseFail;
3975 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
3977 return MatchOperand_Success;
3980 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3981 /// of instructions. Legal values are:
3982 /// ror #n 'n' in {0, 8, 16, 24}
3983 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3984 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3985 const AsmToken &Tok = Parser.getTok();
3986 SMLoc S = Tok.getLoc();
3987 if (Tok.isNot(AsmToken::Identifier))
3988 return MatchOperand_NoMatch;
3989 StringRef ShiftName = Tok.getString();
3990 if (ShiftName != "ror" && ShiftName != "ROR")
3991 return MatchOperand_NoMatch;
3992 Parser.Lex(); // Eat the operator.
3994 // A '#' and a rotate amount.
3995 if (Parser.getTok().isNot(AsmToken::Hash) &&
3996 Parser.getTok().isNot(AsmToken::Dollar)) {
3997 Error(Parser.getTok().getLoc(), "'#' expected");
3998 return MatchOperand_ParseFail;
4000 Parser.Lex(); // Eat hash token.
4001 SMLoc ExLoc = Parser.getTok().getLoc();
4003 const MCExpr *ShiftAmount;
4005 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4006 Error(ExLoc, "malformed rotate expression");
4007 return MatchOperand_ParseFail;
4009 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4011 Error(ExLoc, "rotate amount must be an immediate");
4012 return MatchOperand_ParseFail;
4015 int64_t Val = CE->getValue();
4016 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
4017 // normally, zero is represented in asm by omitting the rotate operand
4019 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
4020 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
4021 return MatchOperand_ParseFail;
4024 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
4026 return MatchOperand_Success;
4029 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4030 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4031 SMLoc S = Parser.getTok().getLoc();
4032 // The bitfield descriptor is really two operands, the LSB and the width.
4033 if (Parser.getTok().isNot(AsmToken::Hash) &&
4034 Parser.getTok().isNot(AsmToken::Dollar)) {
4035 Error(Parser.getTok().getLoc(), "'#' expected");
4036 return MatchOperand_ParseFail;
4038 Parser.Lex(); // Eat hash token.
4040 const MCExpr *LSBExpr;
4041 SMLoc E = Parser.getTok().getLoc();
4042 if (getParser().parseExpression(LSBExpr)) {
4043 Error(E, "malformed immediate expression");
4044 return MatchOperand_ParseFail;
4046 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
4048 Error(E, "'lsb' operand must be an immediate");
4049 return MatchOperand_ParseFail;
4052 int64_t LSB = CE->getValue();
4053 // The LSB must be in the range [0,31]
4054 if (LSB < 0 || LSB > 31) {
4055 Error(E, "'lsb' operand must be in the range [0,31]");
4056 return MatchOperand_ParseFail;
4058 E = Parser.getTok().getLoc();
4060 // Expect another immediate operand.
4061 if (Parser.getTok().isNot(AsmToken::Comma)) {
4062 Error(Parser.getTok().getLoc(), "too few operands");
4063 return MatchOperand_ParseFail;
4065 Parser.Lex(); // Eat hash token.
4066 if (Parser.getTok().isNot(AsmToken::Hash) &&
4067 Parser.getTok().isNot(AsmToken::Dollar)) {
4068 Error(Parser.getTok().getLoc(), "'#' expected");
4069 return MatchOperand_ParseFail;
4071 Parser.Lex(); // Eat hash token.
4073 const MCExpr *WidthExpr;
4075 if (getParser().parseExpression(WidthExpr, EndLoc)) {
4076 Error(E, "malformed immediate expression");
4077 return MatchOperand_ParseFail;
4079 CE = dyn_cast<MCConstantExpr>(WidthExpr);
4081 Error(E, "'width' operand must be an immediate");
4082 return MatchOperand_ParseFail;
4085 int64_t Width = CE->getValue();
4086 // The LSB must be in the range [1,32-lsb]
4087 if (Width < 1 || Width > 32 - LSB) {
4088 Error(E, "'width' operand must be in the range [1,32-lsb]");
4089 return MatchOperand_ParseFail;
4092 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4094 return MatchOperand_Success;
4097 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4098 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4099 // Check for a post-index addressing register operand. Specifically:
4100 // postidx_reg := '+' register {, shift}
4101 // | '-' register {, shift}
4102 // | register {, shift}
4104 // This method must return MatchOperand_NoMatch without consuming any tokens
4105 // in the case where there is no match, as other alternatives take other
4107 AsmToken Tok = Parser.getTok();
4108 SMLoc S = Tok.getLoc();
4109 bool haveEaten = false;
4111 if (Tok.is(AsmToken::Plus)) {
4112 Parser.Lex(); // Eat the '+' token.
4114 } else if (Tok.is(AsmToken::Minus)) {
4115 Parser.Lex(); // Eat the '-' token.
4120 SMLoc E = Parser.getTok().getEndLoc();
4121 int Reg = tryParseRegister();
4124 return MatchOperand_NoMatch;
4125 Error(Parser.getTok().getLoc(), "register expected");
4126 return MatchOperand_ParseFail;
4129 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4130 unsigned ShiftImm = 0;
4131 if (Parser.getTok().is(AsmToken::Comma)) {
4132 Parser.Lex(); // Eat the ','.
4133 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4134 return MatchOperand_ParseFail;
4136 // FIXME: Only approximates end...may include intervening whitespace.
4137 E = Parser.getTok().getLoc();
4140 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4143 return MatchOperand_Success;
4146 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4147 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4148 // Check for a post-index addressing register operand. Specifically:
4149 // am3offset := '+' register
4156 // This method must return MatchOperand_NoMatch without consuming any tokens
4157 // in the case where there is no match, as other alternatives take other
4159 AsmToken Tok = Parser.getTok();
4160 SMLoc S = Tok.getLoc();
4162 // Do immediates first, as we always parse those if we have a '#'.
4163 if (Parser.getTok().is(AsmToken::Hash) ||
4164 Parser.getTok().is(AsmToken::Dollar)) {
4165 Parser.Lex(); // Eat '#' or '$'.
4166 // Explicitly look for a '-', as we need to encode negative zero
4168 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4169 const MCExpr *Offset;
4171 if (getParser().parseExpression(Offset, E))
4172 return MatchOperand_ParseFail;
4173 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4175 Error(S, "constant expression expected");
4176 return MatchOperand_ParseFail;
4178 // Negative zero is encoded as the flag value INT32_MIN.
4179 int32_t Val = CE->getValue();
4180 if (isNegative && Val == 0)
4184 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4186 return MatchOperand_Success;
4190 bool haveEaten = false;
4192 if (Tok.is(AsmToken::Plus)) {
4193 Parser.Lex(); // Eat the '+' token.
4195 } else if (Tok.is(AsmToken::Minus)) {
4196 Parser.Lex(); // Eat the '-' token.
4201 Tok = Parser.getTok();
4202 int Reg = tryParseRegister();
4205 return MatchOperand_NoMatch;
4206 Error(Tok.getLoc(), "register expected");
4207 return MatchOperand_ParseFail;
4210 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4211 0, S, Tok.getEndLoc()));
4213 return MatchOperand_Success;
4216 /// Convert parsed operands to MCInst. Needed here because this instruction
4217 /// only has two register operands, but multiplication is commutative so
4218 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4220 cvtThumbMultiply(MCInst &Inst,
4221 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4222 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4223 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4224 // If we have a three-operand form, make sure to set Rn to be the operand
4225 // that isn't the same as Rd.
4227 if (Operands.size() == 6 &&
4228 ((ARMOperand*)Operands[4])->getReg() ==
4229 ((ARMOperand*)Operands[3])->getReg())
4231 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4232 Inst.addOperand(Inst.getOperand(0));
4233 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4237 cvtThumbBranches(MCInst &Inst,
4238 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4239 int CondOp = -1, ImmOp = -1;
4240 switch(Inst.getOpcode()) {
4242 case ARM::tBcc: CondOp = 1; ImmOp = 2; break;
4245 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4247 default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4249 // first decide whether or not the branch should be conditional
4250 // by looking at it's location relative to an IT block
4252 // inside an IT block we cannot have any conditional branches. any
4253 // such instructions needs to be converted to unconditional form
4254 switch(Inst.getOpcode()) {
4255 case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4256 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4259 // outside IT blocks we can only have unconditional branches with AL
4260 // condition code or conditional branches with non-AL condition code
4261 unsigned Cond = static_cast<ARMOperand*>(Operands[CondOp])->getCondCode();
4262 switch(Inst.getOpcode()) {
4265 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4269 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4274 // now decide on encoding size based on branch target range
4275 switch(Inst.getOpcode()) {
4276 // classify tB as either t2B or t1B based on range of immediate operand
4278 ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4279 if(!op->isSignedOffset<11, 1>() && isThumbTwo())
4280 Inst.setOpcode(ARM::t2B);
4283 // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4285 ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4286 if(!op->isSignedOffset<8, 1>() && isThumbTwo())
4287 Inst.setOpcode(ARM::t2Bcc);
4291 ((ARMOperand*)Operands[ImmOp])->addImmOperands(Inst, 1);
4292 ((ARMOperand*)Operands[CondOp])->addCondCodeOperands(Inst, 2);
4295 /// Parse an ARM memory expression, return false if successful else return true
4296 /// or an error. The first token must be a '[' when called.
4298 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4300 assert(Parser.getTok().is(AsmToken::LBrac) &&
4301 "Token is not a Left Bracket");
4302 S = Parser.getTok().getLoc();
4303 Parser.Lex(); // Eat left bracket token.
4305 const AsmToken &BaseRegTok = Parser.getTok();
4306 int BaseRegNum = tryParseRegister();
4307 if (BaseRegNum == -1)
4308 return Error(BaseRegTok.getLoc(), "register expected");
4310 // The next token must either be a comma, a colon or a closing bracket.
4311 const AsmToken &Tok = Parser.getTok();
4312 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4313 !Tok.is(AsmToken::RBrac))
4314 return Error(Tok.getLoc(), "malformed memory operand");
4316 if (Tok.is(AsmToken::RBrac)) {
4317 E = Tok.getEndLoc();
4318 Parser.Lex(); // Eat right bracket token.
4320 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4321 0, 0, false, S, E));
4323 // If there's a pre-indexing writeback marker, '!', just add it as a token
4324 // operand. It's rather odd, but syntactically valid.
4325 if (Parser.getTok().is(AsmToken::Exclaim)) {
4326 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4327 Parser.Lex(); // Eat the '!'.
4333 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4334 "Lost colon or comma in memory operand?!");
4335 if (Tok.is(AsmToken::Comma)) {
4336 Parser.Lex(); // Eat the comma.
4339 // If we have a ':', it's an alignment specifier.
4340 if (Parser.getTok().is(AsmToken::Colon)) {
4341 Parser.Lex(); // Eat the ':'.
4342 E = Parser.getTok().getLoc();
4345 if (getParser().parseExpression(Expr))
4348 // The expression has to be a constant. Memory references with relocations
4349 // don't come through here, as they use the <label> forms of the relevant
4351 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4353 return Error (E, "constant expression expected");
4356 switch (CE->getValue()) {
4359 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4360 case 16: Align = 2; break;
4361 case 32: Align = 4; break;
4362 case 64: Align = 8; break;
4363 case 128: Align = 16; break;
4364 case 256: Align = 32; break;
4367 // Now we should have the closing ']'
4368 if (Parser.getTok().isNot(AsmToken::RBrac))
4369 return Error(Parser.getTok().getLoc(), "']' expected");
4370 E = Parser.getTok().getEndLoc();
4371 Parser.Lex(); // Eat right bracket token.
4373 // Don't worry about range checking the value here. That's handled by
4374 // the is*() predicates.
4375 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4376 ARM_AM::no_shift, 0, Align,
4379 // If there's a pre-indexing writeback marker, '!', just add it as a token
4381 if (Parser.getTok().is(AsmToken::Exclaim)) {
4382 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4383 Parser.Lex(); // Eat the '!'.
4389 // If we have a '#', it's an immediate offset, else assume it's a register
4390 // offset. Be friendly and also accept a plain integer (without a leading
4391 // hash) for gas compatibility.
4392 if (Parser.getTok().is(AsmToken::Hash) ||
4393 Parser.getTok().is(AsmToken::Dollar) ||
4394 Parser.getTok().is(AsmToken::Integer)) {
4395 if (Parser.getTok().isNot(AsmToken::Integer))
4396 Parser.Lex(); // Eat '#' or '$'.
4397 E = Parser.getTok().getLoc();
4399 bool isNegative = getParser().getTok().is(AsmToken::Minus);
4400 const MCExpr *Offset;
4401 if (getParser().parseExpression(Offset))
4404 // The expression has to be a constant. Memory references with relocations
4405 // don't come through here, as they use the <label> forms of the relevant
4407 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4409 return Error (E, "constant expression expected");
4411 // If the constant was #-0, represent it as INT32_MIN.
4412 int32_t Val = CE->getValue();
4413 if (isNegative && Val == 0)
4414 CE = MCConstantExpr::Create(INT32_MIN, getContext());
4416 // Now we should have the closing ']'
4417 if (Parser.getTok().isNot(AsmToken::RBrac))
4418 return Error(Parser.getTok().getLoc(), "']' expected");
4419 E = Parser.getTok().getEndLoc();
4420 Parser.Lex(); // Eat right bracket token.
4422 // Don't worry about range checking the value here. That's handled by
4423 // the is*() predicates.
4424 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4425 ARM_AM::no_shift, 0, 0,
4428 // If there's a pre-indexing writeback marker, '!', just add it as a token
4430 if (Parser.getTok().is(AsmToken::Exclaim)) {
4431 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4432 Parser.Lex(); // Eat the '!'.
4438 // The register offset is optionally preceded by a '+' or '-'
4439 bool isNegative = false;
4440 if (Parser.getTok().is(AsmToken::Minus)) {
4442 Parser.Lex(); // Eat the '-'.
4443 } else if (Parser.getTok().is(AsmToken::Plus)) {
4445 Parser.Lex(); // Eat the '+'.
4448 E = Parser.getTok().getLoc();
4449 int OffsetRegNum = tryParseRegister();
4450 if (OffsetRegNum == -1)
4451 return Error(E, "register expected");
4453 // If there's a shift operator, handle it.
4454 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4455 unsigned ShiftImm = 0;
4456 if (Parser.getTok().is(AsmToken::Comma)) {
4457 Parser.Lex(); // Eat the ','.
4458 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4462 // Now we should have the closing ']'
4463 if (Parser.getTok().isNot(AsmToken::RBrac))
4464 return Error(Parser.getTok().getLoc(), "']' expected");
4465 E = Parser.getTok().getEndLoc();
4466 Parser.Lex(); // Eat right bracket token.
4468 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4469 ShiftType, ShiftImm, 0, isNegative,
4472 // If there's a pre-indexing writeback marker, '!', just add it as a token
4474 if (Parser.getTok().is(AsmToken::Exclaim)) {
4475 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4476 Parser.Lex(); // Eat the '!'.
4482 /// parseMemRegOffsetShift - one of these two:
4483 /// ( lsl | lsr | asr | ror ) , # shift_amount
4485 /// return true if it parses a shift otherwise it returns false.
4486 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4488 SMLoc Loc = Parser.getTok().getLoc();
4489 const AsmToken &Tok = Parser.getTok();
4490 if (Tok.isNot(AsmToken::Identifier))
4492 StringRef ShiftName = Tok.getString();
4493 if (ShiftName == "lsl" || ShiftName == "LSL" ||
4494 ShiftName == "asl" || ShiftName == "ASL")
4496 else if (ShiftName == "lsr" || ShiftName == "LSR")
4498 else if (ShiftName == "asr" || ShiftName == "ASR")
4500 else if (ShiftName == "ror" || ShiftName == "ROR")
4502 else if (ShiftName == "rrx" || ShiftName == "RRX")
4505 return Error(Loc, "illegal shift operator");
4506 Parser.Lex(); // Eat shift type token.
4508 // rrx stands alone.
4510 if (St != ARM_AM::rrx) {
4511 Loc = Parser.getTok().getLoc();
4512 // A '#' and a shift amount.
4513 const AsmToken &HashTok = Parser.getTok();
4514 if (HashTok.isNot(AsmToken::Hash) &&
4515 HashTok.isNot(AsmToken::Dollar))
4516 return Error(HashTok.getLoc(), "'#' expected");
4517 Parser.Lex(); // Eat hash token.
4520 if (getParser().parseExpression(Expr))
4522 // Range check the immediate.
4523 // lsl, ror: 0 <= imm <= 31
4524 // lsr, asr: 0 <= imm <= 32
4525 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4527 return Error(Loc, "shift amount must be an immediate");
4528 int64_t Imm = CE->getValue();
4530 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4531 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4532 return Error(Loc, "immediate shift value out of range");
4533 // If <ShiftTy> #0, turn it into a no_shift.
4536 // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4545 /// parseFPImm - A floating point immediate expression operand.
4546 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4547 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4548 // Anything that can accept a floating point constant as an operand
4549 // needs to go through here, as the regular parseExpression is
4552 // This routine still creates a generic Immediate operand, containing
4553 // a bitcast of the 64-bit floating point value. The various operands
4554 // that accept floats can check whether the value is valid for them
4555 // via the standard is*() predicates.
4557 SMLoc S = Parser.getTok().getLoc();
4559 if (Parser.getTok().isNot(AsmToken::Hash) &&
4560 Parser.getTok().isNot(AsmToken::Dollar))
4561 return MatchOperand_NoMatch;
4563 // Disambiguate the VMOV forms that can accept an FP immediate.
4564 // vmov.f32 <sreg>, #imm
4565 // vmov.f64 <dreg>, #imm
4566 // vmov.f32 <dreg>, #imm @ vector f32x2
4567 // vmov.f32 <qreg>, #imm @ vector f32x4
4569 // There are also the NEON VMOV instructions which expect an
4570 // integer constant. Make sure we don't try to parse an FPImm
4572 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4573 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4574 if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
4575 TyOp->getToken() != ".f64"))
4576 return MatchOperand_NoMatch;
4578 Parser.Lex(); // Eat '#' or '$'.
4580 // Handle negation, as that still comes through as a separate token.
4581 bool isNegative = false;
4582 if (Parser.getTok().is(AsmToken::Minus)) {
4586 const AsmToken &Tok = Parser.getTok();
4587 SMLoc Loc = Tok.getLoc();
4588 if (Tok.is(AsmToken::Real)) {
4589 APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4590 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4591 // If we had a '-' in front, toggle the sign bit.
4592 IntVal ^= (uint64_t)isNegative << 31;
4593 Parser.Lex(); // Eat the token.
4594 Operands.push_back(ARMOperand::CreateImm(
4595 MCConstantExpr::Create(IntVal, getContext()),
4596 S, Parser.getTok().getLoc()));
4597 return MatchOperand_Success;
4599 // Also handle plain integers. Instructions which allow floating point
4600 // immediates also allow a raw encoded 8-bit value.
4601 if (Tok.is(AsmToken::Integer)) {
4602 int64_t Val = Tok.getIntVal();
4603 Parser.Lex(); // Eat the token.
4604 if (Val > 255 || Val < 0) {
4605 Error(Loc, "encoded floating point value out of range");
4606 return MatchOperand_ParseFail;
4608 double RealVal = ARM_AM::getFPImmFloat(Val);
4609 Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue();
4610 Operands.push_back(ARMOperand::CreateImm(
4611 MCConstantExpr::Create(Val, getContext()), S,
4612 Parser.getTok().getLoc()));
4613 return MatchOperand_Success;
4616 Error(Loc, "invalid floating point immediate");
4617 return MatchOperand_ParseFail;
4620 /// Parse a arm instruction operand. For now this parses the operand regardless
4621 /// of the mnemonic.
4622 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4623 StringRef Mnemonic) {
4626 // Check if the current operand has a custom associated parser, if so, try to
4627 // custom parse the operand, or fallback to the general approach.
4628 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4629 if (ResTy == MatchOperand_Success)
4631 // If there wasn't a custom match, try the generic matcher below. Otherwise,
4632 // there was a match, but an error occurred, in which case, just return that
4633 // the operand parsing failed.
4634 if (ResTy == MatchOperand_ParseFail)
4637 switch (getLexer().getKind()) {
4639 Error(Parser.getTok().getLoc(), "unexpected token in operand");
4641 case AsmToken::Identifier: {
4642 // If we've seen a branch mnemonic, the next operand must be a label. This
4643 // is true even if the label is a register name. So "br r1" means branch to
4645 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
4647 if (!tryParseRegisterWithWriteBack(Operands))
4649 int Res = tryParseShiftRegister(Operands);
4650 if (Res == 0) // success
4652 else if (Res == -1) // irrecoverable error
4654 // If this is VMRS, check for the apsr_nzcv operand.
4655 if (Mnemonic == "vmrs" &&
4656 Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4657 S = Parser.getTok().getLoc();
4659 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4664 // Fall though for the Identifier case that is not a register or a
4667 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
4668 case AsmToken::Integer: // things like 1f and 2b as a branch targets
4669 case AsmToken::String: // quoted label names.
4670 case AsmToken::Dot: { // . as a branch target
4671 // This was not a register so parse other operands that start with an
4672 // identifier (like labels) as expressions and create them as immediates.
4673 const MCExpr *IdVal;
4674 S = Parser.getTok().getLoc();
4675 if (getParser().parseExpression(IdVal))
4677 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4678 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4681 case AsmToken::LBrac:
4682 return parseMemory(Operands);
4683 case AsmToken::LCurly:
4684 return parseRegisterList(Operands);
4685 case AsmToken::Dollar:
4686 case AsmToken::Hash: {
4687 // #42 -> immediate.
4688 S = Parser.getTok().getLoc();
4691 if (Parser.getTok().isNot(AsmToken::Colon)) {
4692 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4693 const MCExpr *ImmVal;
4694 if (getParser().parseExpression(ImmVal))
4696 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4698 int32_t Val = CE->getValue();
4699 if (isNegative && Val == 0)
4700 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4702 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4703 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4705 // There can be a trailing '!' on operands that we want as a separate
4706 // '!' Token operand. Handle that here. For example, the compatibility
4707 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
4708 if (Parser.getTok().is(AsmToken::Exclaim)) {
4709 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
4710 Parser.getTok().getLoc()));
4711 Parser.Lex(); // Eat exclaim token
4715 // w/ a ':' after the '#', it's just like a plain ':'.
4718 case AsmToken::Colon: {
4719 // ":lower16:" and ":upper16:" expression prefixes
4720 // FIXME: Check it's an expression prefix,
4721 // e.g. (FOO - :lower16:BAR) isn't legal.
4722 ARMMCExpr::VariantKind RefKind;
4723 if (parsePrefix(RefKind))
4726 const MCExpr *SubExprVal;
4727 if (getParser().parseExpression(SubExprVal))
4730 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4732 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4733 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4736 case AsmToken::Equal: {
4737 if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
4738 return Error(Parser.getTok().getLoc(), "unexpected token in operand");
4740 const MCSection *Section =
4741 getParser().getStreamer().getCurrentSection().first;
4743 Parser.Lex(); // Eat '='
4744 const MCExpr *SubExprVal;
4745 if (getParser().parseExpression(SubExprVal))
4747 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4749 const MCExpr *CPLoc =
4750 getOrCreateConstantPool(Section).addEntry(SubExprVal, getContext());
4751 Operands.push_back(ARMOperand::CreateImm(CPLoc, S, E));
4757 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4758 // :lower16: and :upper16:.
4759 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4760 RefKind = ARMMCExpr::VK_ARM_None;
4762 // :lower16: and :upper16: modifiers
4763 assert(getLexer().is(AsmToken::Colon) && "expected a :");
4764 Parser.Lex(); // Eat ':'
4766 if (getLexer().isNot(AsmToken::Identifier)) {
4767 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4771 StringRef IDVal = Parser.getTok().getIdentifier();
4772 if (IDVal == "lower16") {
4773 RefKind = ARMMCExpr::VK_ARM_LO16;
4774 } else if (IDVal == "upper16") {
4775 RefKind = ARMMCExpr::VK_ARM_HI16;
4777 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4782 if (getLexer().isNot(AsmToken::Colon)) {
4783 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4786 Parser.Lex(); // Eat the last ':'
4790 /// \brief Given a mnemonic, split out possible predication code and carry
4791 /// setting letters to form a canonical mnemonic and flags.
4793 // FIXME: Would be nice to autogen this.
4794 // FIXME: This is a bit of a maze of special cases.
4795 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4796 unsigned &PredicationCode,
4798 unsigned &ProcessorIMod,
4799 StringRef &ITMask) {
4800 PredicationCode = ARMCC::AL;
4801 CarrySetting = false;
4804 // Ignore some mnemonics we know aren't predicated forms.
4806 // FIXME: Would be nice to autogen this.
4807 if ((Mnemonic == "movs" && isThumb()) ||
4808 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
4809 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
4810 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
4811 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
4812 Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" ||
4813 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
4814 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
4815 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4816 Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
4817 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" ||
4818 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
4819 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel"))
4822 // First, split out any predication code. Ignore mnemonics we know aren't
4823 // predicated but do have a carry-set and so weren't caught above.
4824 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4825 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4826 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4827 Mnemonic != "sbcs" && Mnemonic != "rscs") {
4828 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4829 .Case("eq", ARMCC::EQ)
4830 .Case("ne", ARMCC::NE)
4831 .Case("hs", ARMCC::HS)
4832 .Case("cs", ARMCC::HS)
4833 .Case("lo", ARMCC::LO)
4834 .Case("cc", ARMCC::LO)
4835 .Case("mi", ARMCC::MI)
4836 .Case("pl", ARMCC::PL)
4837 .Case("vs", ARMCC::VS)
4838 .Case("vc", ARMCC::VC)
4839 .Case("hi", ARMCC::HI)
4840 .Case("ls", ARMCC::LS)
4841 .Case("ge", ARMCC::GE)
4842 .Case("lt", ARMCC::LT)
4843 .Case("gt", ARMCC::GT)
4844 .Case("le", ARMCC::LE)
4845 .Case("al", ARMCC::AL)
4848 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4849 PredicationCode = CC;
4853 // Next, determine if we have a carry setting bit. We explicitly ignore all
4854 // the instructions we know end in 's'.
4855 if (Mnemonic.endswith("s") &&
4856 !(Mnemonic == "cps" || Mnemonic == "mls" ||
4857 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4858 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4859 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4860 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4861 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4862 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4863 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
4864 Mnemonic == "vfms" || Mnemonic == "vfnms" ||
4865 (Mnemonic == "movs" && isThumb()))) {
4866 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4867 CarrySetting = true;
4870 // The "cps" instruction can have a interrupt mode operand which is glued into
4871 // the mnemonic. Check if this is the case, split it and parse the imod op
4872 if (Mnemonic.startswith("cps")) {
4873 // Split out any imod code.
4875 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4876 .Case("ie", ARM_PROC::IE)
4877 .Case("id", ARM_PROC::ID)
4880 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4881 ProcessorIMod = IMod;
4885 // The "it" instruction has the condition mask on the end of the mnemonic.
4886 if (Mnemonic.startswith("it")) {
4887 ITMask = Mnemonic.slice(2, Mnemonic.size());
4888 Mnemonic = Mnemonic.slice(0, 2);
4894 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
4895 /// inclusion of carry set or predication code operands.
4897 // FIXME: It would be nice to autogen this.
4899 getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
4900 bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) {
4901 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4902 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4903 Mnemonic == "add" || Mnemonic == "adc" ||
4904 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4905 Mnemonic == "orr" || Mnemonic == "mvn" ||
4906 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4907 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4908 Mnemonic == "vfm" || Mnemonic == "vfnm" ||
4909 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4910 Mnemonic == "mla" || Mnemonic == "smlal" ||
4911 Mnemonic == "umlal" || Mnemonic == "umull"))) {
4912 CanAcceptCarrySet = true;
4914 CanAcceptCarrySet = false;
4916 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
4917 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
4918 Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic.startswith("crc32") ||
4919 Mnemonic.startswith("cps") || Mnemonic.startswith("vsel") ||
4920 Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
4921 Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
4922 Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
4923 Mnemonic == "vrintm" || Mnemonic.startswith("aes") ||
4924 Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
4925 (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) {
4926 // These mnemonics are never predicable
4927 CanAcceptPredicationCode = false;
4928 } else if (!isThumb()) {
4929 // Some instructions are only predicable in Thumb mode
4930 CanAcceptPredicationCode
4931 = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
4932 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
4933 Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
4934 Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
4935 Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
4936 Mnemonic != "stc2" && Mnemonic != "stc2l" &&
4937 !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
4938 } else if (isThumbOne()) {
4940 CanAcceptPredicationCode = Mnemonic != "movs";
4942 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
4944 CanAcceptPredicationCode = true;
4947 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4948 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4949 // FIXME: This is all horribly hacky. We really need a better way to deal
4950 // with optional operands like this in the matcher table.
4952 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4953 // another does not. Specifically, the MOVW instruction does not. So we
4954 // special case it here and remove the defaulted (non-setting) cc_out
4955 // operand if that's the instruction we're trying to match.
4957 // We do this as post-processing of the explicit operands rather than just
4958 // conditionally adding the cc_out in the first place because we need
4959 // to check the type of the parsed immediate operand.
4960 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4961 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4962 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4963 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4966 // Register-register 'add' for thumb does not have a cc_out operand
4967 // when there are only two register operands.
4968 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4969 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4970 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4971 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4973 // Register-register 'add' for thumb does not have a cc_out operand
4974 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4975 // have to check the immediate range here since Thumb2 has a variant
4976 // that can handle a different range and has a cc_out operand.
4977 if (((isThumb() && Mnemonic == "add") ||
4978 (isThumbTwo() && Mnemonic == "sub")) &&
4979 Operands.size() == 6 &&
4980 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4981 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4982 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4983 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4984 ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
4985 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4987 // For Thumb2, add/sub immediate does not have a cc_out operand for the
4988 // imm0_4095 variant. That's the least-preferred variant when
4989 // selecting via the generic "add" mnemonic, so to know that we
4990 // should remove the cc_out operand, we have to explicitly check that
4991 // it's not one of the other variants. Ugh.
4992 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4993 Operands.size() == 6 &&
4994 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4995 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4996 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4997 // Nest conditions rather than one big 'if' statement for readability.
4999 // If both registers are low, we're in an IT block, and the immediate is
5000 // in range, we should use encoding T1 instead, which has a cc_out.
5002 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
5003 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
5004 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
5006 // Check against T3. If the second register is the PC, this is an
5007 // alternate form of ADR, which uses encoding T4, so check for that too.
5008 if (static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
5009 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
5012 // Otherwise, we use encoding T4, which does not have a cc_out
5017 // The thumb2 multiply instruction doesn't have a CCOut register, so
5018 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
5019 // use the 16-bit encoding or not.
5020 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5021 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5022 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5023 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5024 static_cast<ARMOperand*>(Operands[5])->isReg() &&
5025 // If the registers aren't low regs, the destination reg isn't the
5026 // same as one of the source regs, or the cc_out operand is zero
5027 // outside of an IT block, we have to use the 32-bit encoding, so
5028 // remove the cc_out operand.
5029 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
5030 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
5031 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
5033 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
5034 static_cast<ARMOperand*>(Operands[5])->getReg() &&
5035 static_cast<ARMOperand*>(Operands[3])->getReg() !=
5036 static_cast<ARMOperand*>(Operands[4])->getReg())))
5039 // Also check the 'mul' syntax variant that doesn't specify an explicit
5040 // destination register.
5041 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5042 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5043 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5044 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5045 // If the registers aren't low regs or the cc_out operand is zero
5046 // outside of an IT block, we have to use the 32-bit encoding, so
5047 // remove the cc_out operand.
5048 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
5049 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
5055 // Register-register 'add/sub' for thumb does not have a cc_out operand
5056 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5057 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
5058 // right, this will result in better diagnostics (which operand is off)
5060 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
5061 (Operands.size() == 5 || Operands.size() == 6) &&
5062 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5063 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
5064 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5065 (static_cast<ARMOperand*>(Operands[4])->isImm() ||
5066 (Operands.size() == 6 &&
5067 static_cast<ARMOperand*>(Operands[5])->isImm())))
5073 bool ARMAsmParser::shouldOmitPredicateOperand(
5074 StringRef Mnemonic, SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
5075 // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
5076 unsigned RegIdx = 3;
5077 if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
5078 static_cast<ARMOperand *>(Operands[2])->getToken() == ".f32") {
5079 if (static_cast<ARMOperand *>(Operands[3])->isToken() &&
5080 static_cast<ARMOperand *>(Operands[3])->getToken() == ".f32")
5083 if (static_cast<ARMOperand *>(Operands[RegIdx])->isReg() &&
5084 (ARMMCRegisterClasses[ARM::DPRRegClassID]
5085 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg()) ||
5086 ARMMCRegisterClasses[ARM::QPRRegClassID]
5087 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg())))
5093 static bool isDataTypeToken(StringRef Tok) {
5094 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5095 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5096 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5097 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5098 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5099 Tok == ".f" || Tok == ".d";
5102 // FIXME: This bit should probably be handled via an explicit match class
5103 // in the .td files that matches the suffix instead of having it be
5104 // a literal string token the way it is now.
5105 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5106 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5108 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
5109 unsigned VariantID);
5110 /// Parse an arm instruction mnemonic followed by its operands.
5111 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5113 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5114 // FIXME: Can this be done via tablegen in some fashion?
5115 bool HasPrecisionRestrictions;
5116 bool AcceptDoublePrecisionOnly;
5117 bool AcceptSinglePrecisionOnly;
5118 HasPrecisionRestrictions = Name.startswith("fldm") || Name.startswith("fstm");
5119 AcceptDoublePrecisionOnly =
5120 HasPrecisionRestrictions && (Name.back() == 'd' || Name.back() == 'x');
5121 AcceptSinglePrecisionOnly = HasPrecisionRestrictions && Name.back() == 's';
5123 // Apply mnemonic aliases before doing anything else, as the destination
5124 // mnemonic may include suffices and we want to handle them normally.
5125 // The generic tblgen'erated code does this later, at the start of
5126 // MatchInstructionImpl(), but that's too late for aliases that include
5127 // any sort of suffix.
5128 unsigned AvailableFeatures = getAvailableFeatures();
5129 unsigned AssemblerDialect = getParser().getAssemblerDialect();
5130 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5132 // First check for the ARM-specific .req directive.
5133 if (Parser.getTok().is(AsmToken::Identifier) &&
5134 Parser.getTok().getIdentifier() == ".req") {
5135 parseDirectiveReq(Name, NameLoc);
5136 // We always return 'error' for this, as we're done with this
5137 // statement and don't need to match the 'instruction."
5141 // Create the leading tokens for the mnemonic, split by '.' characters.
5142 size_t Start = 0, Next = Name.find('.');
5143 StringRef Mnemonic = Name.slice(Start, Next);
5145 // Split out the predication code and carry setting flag from the mnemonic.
5146 unsigned PredicationCode;
5147 unsigned ProcessorIMod;
5150 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5151 ProcessorIMod, ITMask);
5153 // In Thumb1, only the branch (B) instruction can be predicated.
5154 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5155 Parser.eatToEndOfStatement();
5156 return Error(NameLoc, "conditional execution not supported in Thumb1");
5159 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5161 // Handle the IT instruction ITMask. Convert it to a bitmask. This
5162 // is the mask as it will be for the IT encoding if the conditional
5163 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5164 // where the conditional bit0 is zero, the instruction post-processing
5165 // will adjust the mask accordingly.
5166 if (Mnemonic == "it") {
5167 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5168 if (ITMask.size() > 3) {
5169 Parser.eatToEndOfStatement();
5170 return Error(Loc, "too many conditions on IT instruction");
5173 for (unsigned i = ITMask.size(); i != 0; --i) {
5174 char pos = ITMask[i - 1];
5175 if (pos != 't' && pos != 'e') {
5176 Parser.eatToEndOfStatement();
5177 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5180 if (ITMask[i - 1] == 't')
5183 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5186 // FIXME: This is all a pretty gross hack. We should automatically handle
5187 // optional operands like this via tblgen.
5189 // Next, add the CCOut and ConditionCode operands, if needed.
5191 // For mnemonics which can ever incorporate a carry setting bit or predication
5192 // code, our matching model involves us always generating CCOut and
5193 // ConditionCode operands to match the mnemonic "as written" and then we let
5194 // the matcher deal with finding the right instruction or generating an
5195 // appropriate error.
5196 bool CanAcceptCarrySet, CanAcceptPredicationCode;
5197 getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
5199 // If we had a carry-set on an instruction that can't do that, issue an
5201 if (!CanAcceptCarrySet && CarrySetting) {
5202 Parser.eatToEndOfStatement();
5203 return Error(NameLoc, "instruction '" + Mnemonic +
5204 "' can not set flags, but 's' suffix specified");
5206 // If we had a predication code on an instruction that can't do that, issue an
5208 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5209 Parser.eatToEndOfStatement();
5210 return Error(NameLoc, "instruction '" + Mnemonic +
5211 "' is not predicable, but condition code specified");
5214 // Add the carry setting operand, if necessary.
5215 if (CanAcceptCarrySet) {
5216 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5217 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5221 // Add the predication code operand, if necessary.
5222 if (CanAcceptPredicationCode) {
5223 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5225 Operands.push_back(ARMOperand::CreateCondCode(
5226 ARMCC::CondCodes(PredicationCode), Loc));
5229 // Add the processor imod operand, if necessary.
5230 if (ProcessorIMod) {
5231 Operands.push_back(ARMOperand::CreateImm(
5232 MCConstantExpr::Create(ProcessorIMod, getContext()),
5236 // Add the remaining tokens in the mnemonic.
5237 while (Next != StringRef::npos) {
5239 Next = Name.find('.', Start + 1);
5240 StringRef ExtraToken = Name.slice(Start, Next);
5242 // Some NEON instructions have an optional datatype suffix that is
5243 // completely ignored. Check for that.
5244 if (isDataTypeToken(ExtraToken) &&
5245 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5248 // For for ARM mode generate an error if the .n qualifier is used.
5249 if (ExtraToken == ".n" && !isThumb()) {
5250 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5251 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5255 // The .n qualifier is always discarded as that is what the tables
5256 // and matcher expect. In ARM mode the .w qualifier has no effect,
5257 // so discard it to avoid errors that can be caused by the matcher.
5258 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5259 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5260 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5264 // Read the remaining operands.
5265 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5266 // Read the first operand.
5267 if (parseOperand(Operands, Mnemonic)) {
5268 Parser.eatToEndOfStatement();
5272 while (getLexer().is(AsmToken::Comma)) {
5273 Parser.Lex(); // Eat the comma.
5275 // Parse and remember the operand.
5276 if (parseOperand(Operands, Mnemonic)) {
5277 Parser.eatToEndOfStatement();
5283 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5284 SMLoc Loc = getLexer().getLoc();
5285 Parser.eatToEndOfStatement();
5286 return Error(Loc, "unexpected token in argument list");
5289 Parser.Lex(); // Consume the EndOfStatement
5291 if (HasPrecisionRestrictions) {
5292 ARMOperand *Op = static_cast<ARMOperand*>(Operands.back());
5293 assert(Op->isRegList());
5294 const SmallVectorImpl<unsigned> &RegList = Op->getRegList();
5295 for (SmallVectorImpl<unsigned>::const_iterator RLI = RegList.begin(),
5296 RLE = RegList.end();
5297 RLI != RLE; ++RLI) {
5298 if (AcceptSinglePrecisionOnly &&
5299 !ARMMCRegisterClasses[ARM::SPRRegClassID].contains(*RLI))
5300 return Error(Op->getStartLoc(),
5301 "VFP/Neon single precision register expected");
5302 else if (AcceptDoublePrecisionOnly &&
5303 !ARMMCRegisterClasses[ARM::DPRRegClassID].contains(*RLI))
5304 return Error(Op->getStartLoc(),
5305 "VFP/Neon double precision register expected");
5307 llvm_unreachable("must have single or double precision restrictions");
5311 // Some instructions, mostly Thumb, have forms for the same mnemonic that
5312 // do and don't have a cc_out optional-def operand. With some spot-checks
5313 // of the operand list, we can figure out which variant we're trying to
5314 // parse and adjust accordingly before actually matching. We shouldn't ever
5315 // try to remove a cc_out operand that was explicitly set on the the
5316 // mnemonic, of course (CarrySetting == true). Reason number #317 the
5317 // table driven matcher doesn't fit well with the ARM instruction set.
5318 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5319 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5320 Operands.erase(Operands.begin() + 1);
5324 // Some instructions have the same mnemonic, but don't always
5325 // have a predicate. Distinguish them here and delete the
5326 // predicate if needed.
5327 if (shouldOmitPredicateOperand(Mnemonic, Operands)) {
5328 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5329 Operands.erase(Operands.begin() + 1);
5333 // ARM mode 'blx' need special handling, as the register operand version
5334 // is predicable, but the label operand version is not. So, we can't rely
5335 // on the Mnemonic based checking to correctly figure out when to put
5336 // a k_CondCode operand in the list. If we're trying to match the label
5337 // version, remove the k_CondCode operand here.
5338 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5339 static_cast<ARMOperand*>(Operands[2])->isImm()) {
5340 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5341 Operands.erase(Operands.begin() + 1);
5345 // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5346 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5347 // a single GPRPair reg operand is used in the .td file to replace the two
5348 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5349 // expressed as a GPRPair, so we have to manually merge them.
5350 // FIXME: We would really like to be able to tablegen'erate this.
5351 if (!isThumb() && Operands.size() > 4 &&
5352 (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
5353 Mnemonic == "stlexd")) {
5354 bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
5355 unsigned Idx = isLoad ? 2 : 3;
5356 ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]);
5357 ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]);
5359 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5360 // Adjust only if Op1 and Op2 are GPRs.
5361 if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) &&
5362 MRC.contains(Op2->getReg())) {
5363 unsigned Reg1 = Op1->getReg();
5364 unsigned Reg2 = Op2->getReg();
5365 unsigned Rt = MRI->getEncodingValue(Reg1);
5366 unsigned Rt2 = MRI->getEncodingValue(Reg2);
5368 // Rt2 must be Rt + 1 and Rt must be even.
5369 if (Rt + 1 != Rt2 || (Rt & 1)) {
5370 Error(Op2->getStartLoc(), isLoad ?
5371 "destination operands must be sequential" :
5372 "source operands must be sequential");
5375 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5376 &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5377 Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2);
5378 Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg(
5379 NewReg, Op1->getStartLoc(), Op2->getEndLoc()));
5385 // FIXME: As said above, this is all a pretty gross hack. This instruction
5386 // does not fit with other "subs" and tblgen.
5387 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
5388 // so the Mnemonic is the original name "subs" and delete the predicate
5389 // operand so it will match the table entry.
5390 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
5391 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5392 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::PC &&
5393 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5394 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::LR &&
5395 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5396 ARMOperand *Op0 = static_cast<ARMOperand*>(Operands[0]);
5397 Operands.erase(Operands.begin());
5399 Operands.insert(Operands.begin(), ARMOperand::CreateToken(Name, NameLoc));
5401 ARMOperand *Op1 = static_cast<ARMOperand*>(Operands[1]);
5402 Operands.erase(Operands.begin() + 1);
5408 // Validate context-sensitive operand constraints.
5410 // return 'true' if register list contains non-low GPR registers,
5411 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5412 // 'containsReg' to true.
5413 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5414 unsigned HiReg, bool &containsReg) {
5415 containsReg = false;
5416 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5417 unsigned OpReg = Inst.getOperand(i).getReg();
5420 // Anything other than a low register isn't legal here.
5421 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5427 // Check if the specified regisgter is in the register list of the inst,
5428 // starting at the indicated operand number.
5429 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5430 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5431 unsigned OpReg = Inst.getOperand(i).getReg();
5438 // Return true if instruction has the interesting property of being
5439 // allowed in IT blocks, but not being predicable.
5440 static bool instIsBreakpoint(const MCInst &Inst) {
5441 return Inst.getOpcode() == ARM::tBKPT ||
5442 Inst.getOpcode() == ARM::BKPT ||
5443 Inst.getOpcode() == ARM::tHLT ||
5444 Inst.getOpcode() == ARM::HLT;
5448 // FIXME: We would really like to be able to tablegen'erate this.
5450 validateInstruction(MCInst &Inst,
5451 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5452 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
5453 SMLoc Loc = Operands[0]->getStartLoc();
5455 // Check the IT block state first.
5456 // NOTE: BKPT and HLT instructions have the interesting property of being
5457 // allowed in IT blocks, but not being predicable. They just always execute.
5458 if (inITBlock() && !instIsBreakpoint(Inst)) {
5460 if (ITState.FirstCond)
5461 ITState.FirstCond = false;
5463 Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5464 // The instruction must be predicable.
5465 if (!MCID.isPredicable())
5466 return Error(Loc, "instructions in IT block must be predicable");
5467 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5468 unsigned ITCond = Bit ? ITState.Cond :
5469 ARMCC::getOppositeCondition(ITState.Cond);
5470 if (Cond != ITCond) {
5471 // Find the condition code Operand to get its SMLoc information.
5473 for (unsigned I = 1; I < Operands.size(); ++I)
5474 if (static_cast<ARMOperand*>(Operands[I])->isCondCode())
5475 CondLoc = Operands[I]->getStartLoc();
5476 return Error(CondLoc, "incorrect condition in IT block; got '" +
5477 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5478 "', but expected '" +
5479 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5481 // Check for non-'al' condition codes outside of the IT block.
5482 } else if (isThumbTwo() && MCID.isPredicable() &&
5483 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5484 ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
5485 Inst.getOpcode() != ARM::t2Bcc)
5486 return Error(Loc, "predicated instructions must be in IT block");
5488 const unsigned Opcode = Inst.getOpcode();
5492 case ARM::LDRD_POST: {
5493 const unsigned RtReg = Inst.getOperand(0).getReg();
5496 if (RtReg == ARM::LR)
5497 return Error(Operands[3]->getStartLoc(),
5500 const unsigned Rt = MRI->getEncodingValue(RtReg);
5501 // Rt must be even-numbered.
5503 return Error(Operands[3]->getStartLoc(),
5504 "Rt must be even-numbered");
5506 // Rt2 must be Rt + 1.
5507 const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5509 return Error(Operands[3]->getStartLoc(),
5510 "destination operands must be sequential");
5512 if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) {
5513 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
5514 // For addressing modes with writeback, the base register needs to be
5515 // different from the destination registers.
5516 if (Rn == Rt || Rn == Rt2)
5517 return Error(Operands[3]->getStartLoc(),
5518 "base register needs to be different from destination "
5525 case ARM::t2LDRD_PRE:
5526 case ARM::t2LDRD_POST: {
5527 // Rt2 must be different from Rt.
5528 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5529 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5531 return Error(Operands[3]->getStartLoc(),
5532 "destination operands can't be identical");
5536 // Rt2 must be Rt + 1.
5537 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5538 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5540 return Error(Operands[3]->getStartLoc(),
5541 "source operands must be sequential");
5545 case ARM::STRD_POST: {
5546 // Rt2 must be Rt + 1.
5547 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5548 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5550 return Error(Operands[3]->getStartLoc(),
5551 "source operands must be sequential");
5556 // Width must be in range [1, 32-lsb].
5557 unsigned LSB = Inst.getOperand(2).getImm();
5558 unsigned Widthm1 = Inst.getOperand(3).getImm();
5559 if (Widthm1 >= 32 - LSB)
5560 return Error(Operands[5]->getStartLoc(),
5561 "bitfield width must be in range [1,32-lsb]");
5564 // Notionally handles ARM::tLDMIA_UPD too.
5566 // If we're parsing Thumb2, the .w variant is available and handles
5567 // most cases that are normally illegal for a Thumb1 LDM instruction.
5568 // We'll make the transformation in processInstruction() if necessary.
5570 // Thumb LDM instructions are writeback iff the base register is not
5571 // in the register list.
5572 unsigned Rn = Inst.getOperand(0).getReg();
5573 bool HasWritebackToken =
5574 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5575 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5576 bool ListContainsBase;
5577 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
5578 return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
5579 "registers must be in range r0-r7");
5580 // If we should have writeback, then there should be a '!' token.
5581 if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
5582 return Error(Operands[2]->getStartLoc(),
5583 "writeback operator '!' expected");
5584 // If we should not have writeback, there must not be a '!'. This is
5585 // true even for the 32-bit wide encodings.
5586 if (ListContainsBase && HasWritebackToken)
5587 return Error(Operands[3]->getStartLoc(),
5588 "writeback operator '!' not allowed when base register "
5589 "in register list");
5593 case ARM::LDMIA_UPD:
5594 case ARM::LDMDB_UPD:
5595 case ARM::LDMIB_UPD:
5596 case ARM::LDMDA_UPD:
5597 // ARM variants loading and updating the same register are only officially
5598 // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
5602 case ARM::t2LDMIA_UPD:
5603 case ARM::t2LDMDB_UPD:
5604 case ARM::t2STMIA_UPD:
5605 case ARM::t2STMDB_UPD: {
5606 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5607 return Error(Operands.back()->getStartLoc(),
5608 "writeback register not allowed in register list");
5611 case ARM::sysLDMIA_UPD:
5612 case ARM::sysLDMDA_UPD:
5613 case ARM::sysLDMDB_UPD:
5614 case ARM::sysLDMIB_UPD:
5615 if (!listContainsReg(Inst, 3, ARM::PC))
5616 return Error(Operands[4]->getStartLoc(),
5617 "writeback register only allowed on system LDM "
5618 "if PC in register-list");
5620 case ARM::sysSTMIA_UPD:
5621 case ARM::sysSTMDA_UPD:
5622 case ARM::sysSTMDB_UPD:
5623 case ARM::sysSTMIB_UPD:
5624 return Error(Operands[2]->getStartLoc(),
5625 "system STM cannot have writeback register");
5628 // The second source operand must be the same register as the destination
5631 // In this case, we must directly check the parsed operands because the
5632 // cvtThumbMultiply() function is written in such a way that it guarantees
5633 // this first statement is always true for the new Inst. Essentially, the
5634 // destination is unconditionally copied into the second source operand
5635 // without checking to see if it matches what we actually parsed.
5636 if (Operands.size() == 6 &&
5637 (((ARMOperand*)Operands[3])->getReg() !=
5638 ((ARMOperand*)Operands[5])->getReg()) &&
5639 (((ARMOperand*)Operands[3])->getReg() !=
5640 ((ARMOperand*)Operands[4])->getReg())) {
5641 return Error(Operands[3]->getStartLoc(),
5642 "destination register must match source register");
5646 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5647 // so only issue a diagnostic for thumb1. The instructions will be
5648 // switched to the t2 encodings in processInstruction() if necessary.
5650 bool ListContainsBase;
5651 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
5653 return Error(Operands[2]->getStartLoc(),
5654 "registers must be in range r0-r7 or pc");
5658 bool ListContainsBase;
5659 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
5661 return Error(Operands[2]->getStartLoc(),
5662 "registers must be in range r0-r7 or lr");
5665 case ARM::tSTMIA_UPD: {
5666 bool ListContainsBase, InvalidLowList;
5667 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
5668 0, ListContainsBase);
5669 if (InvalidLowList && !isThumbTwo())
5670 return Error(Operands[4]->getStartLoc(),
5671 "registers must be in range r0-r7");
5673 // This would be converted to a 32-bit stm, but that's not valid if the
5674 // writeback register is in the list.
5675 if (InvalidLowList && ListContainsBase)
5676 return Error(Operands[4]->getStartLoc(),
5677 "writeback operator '!' not allowed when base register "
5678 "in register list");
5681 case ARM::tADDrSP: {
5682 // If the non-SP source operand and the destination operand are not the
5683 // same, we need thumb2 (for the wide encoding), or we have an error.
5684 if (!isThumbTwo() &&
5685 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5686 return Error(Operands[4]->getStartLoc(),
5687 "source register must be the same as destination");
5691 // Final range checking for Thumb unconditional branch instructions.
5693 if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<11, 1>())
5694 return Error(Operands[2]->getStartLoc(), "branch target out of range");
5697 int op = (Operands[2]->isImm()) ? 2 : 3;
5698 if (!(static_cast<ARMOperand*>(Operands[op]))->isSignedOffset<24, 1>())
5699 return Error(Operands[op]->getStartLoc(), "branch target out of range");
5702 // Final range checking for Thumb conditional branch instructions.
5704 if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<8, 1>())
5705 return Error(Operands[2]->getStartLoc(), "branch target out of range");
5708 int Op = (Operands[2]->isImm()) ? 2 : 3;
5709 if (!(static_cast<ARMOperand*>(Operands[Op]))->isSignedOffset<20, 1>())
5710 return Error(Operands[Op]->getStartLoc(), "branch target out of range");
5718 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5720 default: llvm_unreachable("unexpected opcode!");
5722 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5723 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5724 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5725 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5726 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5727 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5728 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
5729 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5730 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5733 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5734 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5735 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5736 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5737 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5739 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5740 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5741 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5742 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5743 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5745 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
5746 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5747 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5748 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5749 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5752 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5753 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5754 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5755 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5756 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5757 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5758 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5759 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5760 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5761 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5762 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
5763 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5764 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5765 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5766 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5769 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5770 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5771 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5772 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5773 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5774 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5775 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5776 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5777 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5778 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5779 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5780 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5781 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
5782 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5783 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5784 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
5785 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5786 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5789 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5790 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5791 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5792 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5793 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5794 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5795 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5796 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5797 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5798 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5799 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
5800 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5801 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5802 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5803 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5806 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5807 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5808 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5809 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5810 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5811 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5812 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5813 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5814 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5815 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5816 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5817 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5818 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
5819 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5820 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5821 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
5822 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5823 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5827 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
5829 default: llvm_unreachable("unexpected opcode!");
5831 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5832 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5833 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5834 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5835 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5836 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5837 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
5838 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5839 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5842 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5843 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5844 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5845 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5846 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5847 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5848 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5849 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5850 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5851 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5852 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
5853 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5854 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5855 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5856 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5859 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5860 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5861 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5862 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5863 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5864 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5865 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5866 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5867 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5868 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5869 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5870 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5871 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
5872 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5873 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5874 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5875 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5876 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5879 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5880 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5881 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5882 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5883 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5884 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5885 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5886 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5887 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5888 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5889 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
5890 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5891 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5892 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5893 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5896 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5897 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5898 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5899 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5900 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5901 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5902 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5903 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5904 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5905 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5906 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5907 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5908 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
5909 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5910 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5911 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
5912 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5913 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
5916 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5917 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5918 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5919 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
5920 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5921 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5922 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5923 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5924 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5925 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5926 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
5927 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5928 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5929 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5930 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5933 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5934 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5935 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5936 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5937 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5938 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5939 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5940 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5941 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5942 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
5943 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
5944 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5945 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
5946 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
5947 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
5948 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
5949 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
5950 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
5953 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5954 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5955 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5956 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5957 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5958 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5959 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5960 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5961 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5962 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5963 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5964 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5965 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
5966 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
5967 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
5968 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
5969 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
5970 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
5975 processInstruction(MCInst &Inst,
5976 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5977 switch (Inst.getOpcode()) {
5978 // Alias for alternate form of 'ADR Rd, #imm' instruction.
5980 if (Inst.getOperand(1).getReg() != ARM::PC ||
5981 Inst.getOperand(5).getReg() != 0)
5984 TmpInst.setOpcode(ARM::ADR);
5985 TmpInst.addOperand(Inst.getOperand(0));
5986 TmpInst.addOperand(Inst.getOperand(2));
5987 TmpInst.addOperand(Inst.getOperand(3));
5988 TmpInst.addOperand(Inst.getOperand(4));
5992 // Aliases for alternate PC+imm syntax of LDR instructions.
5993 case ARM::t2LDRpcrel:
5994 // Select the narrow version if the immediate will fit.
5995 if (Inst.getOperand(1).getImm() > 0 &&
5996 Inst.getOperand(1).getImm() <= 0xff &&
5997 !(static_cast<ARMOperand*>(Operands[2])->isToken() &&
5998 static_cast<ARMOperand*>(Operands[2])->getToken() == ".w"))
5999 Inst.setOpcode(ARM::tLDRpci);
6001 Inst.setOpcode(ARM::t2LDRpci);
6003 case ARM::t2LDRBpcrel:
6004 Inst.setOpcode(ARM::t2LDRBpci);
6006 case ARM::t2LDRHpcrel:
6007 Inst.setOpcode(ARM::t2LDRHpci);
6009 case ARM::t2LDRSBpcrel:
6010 Inst.setOpcode(ARM::t2LDRSBpci);
6012 case ARM::t2LDRSHpcrel:
6013 Inst.setOpcode(ARM::t2LDRSHpci);
6015 // Handle NEON VST complex aliases.
6016 case ARM::VST1LNdWB_register_Asm_8:
6017 case ARM::VST1LNdWB_register_Asm_16:
6018 case ARM::VST1LNdWB_register_Asm_32: {
6020 // Shuffle the operands around so the lane index operand is in the
6023 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6024 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6025 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6026 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6027 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6028 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6029 TmpInst.addOperand(Inst.getOperand(1)); // lane
6030 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6031 TmpInst.addOperand(Inst.getOperand(6));
6036 case ARM::VST2LNdWB_register_Asm_8:
6037 case ARM::VST2LNdWB_register_Asm_16:
6038 case ARM::VST2LNdWB_register_Asm_32:
6039 case ARM::VST2LNqWB_register_Asm_16:
6040 case ARM::VST2LNqWB_register_Asm_32: {
6042 // Shuffle the operands around so the lane index operand is in the
6045 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6046 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6047 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6048 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6049 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6050 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6051 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6053 TmpInst.addOperand(Inst.getOperand(1)); // lane
6054 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6055 TmpInst.addOperand(Inst.getOperand(6));
6060 case ARM::VST3LNdWB_register_Asm_8:
6061 case ARM::VST3LNdWB_register_Asm_16:
6062 case ARM::VST3LNdWB_register_Asm_32:
6063 case ARM::VST3LNqWB_register_Asm_16:
6064 case ARM::VST3LNqWB_register_Asm_32: {
6066 // Shuffle the operands around so the lane index operand is in the
6069 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6070 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6071 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6072 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6073 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6074 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6075 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6077 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6079 TmpInst.addOperand(Inst.getOperand(1)); // lane
6080 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6081 TmpInst.addOperand(Inst.getOperand(6));
6086 case ARM::VST4LNdWB_register_Asm_8:
6087 case ARM::VST4LNdWB_register_Asm_16:
6088 case ARM::VST4LNdWB_register_Asm_32:
6089 case ARM::VST4LNqWB_register_Asm_16:
6090 case ARM::VST4LNqWB_register_Asm_32: {
6092 // Shuffle the operands around so the lane index operand is in the
6095 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6096 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6097 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6098 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6099 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6100 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6101 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6103 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6105 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6107 TmpInst.addOperand(Inst.getOperand(1)); // lane
6108 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6109 TmpInst.addOperand(Inst.getOperand(6));
6114 case ARM::VST1LNdWB_fixed_Asm_8:
6115 case ARM::VST1LNdWB_fixed_Asm_16:
6116 case ARM::VST1LNdWB_fixed_Asm_32: {
6118 // Shuffle the operands around so the lane index operand is in the
6121 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6122 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6123 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6124 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6125 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6126 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6127 TmpInst.addOperand(Inst.getOperand(1)); // lane
6128 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6129 TmpInst.addOperand(Inst.getOperand(5));
6134 case ARM::VST2LNdWB_fixed_Asm_8:
6135 case ARM::VST2LNdWB_fixed_Asm_16:
6136 case ARM::VST2LNdWB_fixed_Asm_32:
6137 case ARM::VST2LNqWB_fixed_Asm_16:
6138 case ARM::VST2LNqWB_fixed_Asm_32: {
6140 // Shuffle the operands around so the lane index operand is in the
6143 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6144 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6145 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6146 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6147 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6148 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6149 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6151 TmpInst.addOperand(Inst.getOperand(1)); // lane
6152 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6153 TmpInst.addOperand(Inst.getOperand(5));
6158 case ARM::VST3LNdWB_fixed_Asm_8:
6159 case ARM::VST3LNdWB_fixed_Asm_16:
6160 case ARM::VST3LNdWB_fixed_Asm_32:
6161 case ARM::VST3LNqWB_fixed_Asm_16:
6162 case ARM::VST3LNqWB_fixed_Asm_32: {
6164 // Shuffle the operands around so the lane index operand is in the
6167 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6168 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6169 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6170 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6171 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6172 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6173 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6175 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6177 TmpInst.addOperand(Inst.getOperand(1)); // lane
6178 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6179 TmpInst.addOperand(Inst.getOperand(5));
6184 case ARM::VST4LNdWB_fixed_Asm_8:
6185 case ARM::VST4LNdWB_fixed_Asm_16:
6186 case ARM::VST4LNdWB_fixed_Asm_32:
6187 case ARM::VST4LNqWB_fixed_Asm_16:
6188 case ARM::VST4LNqWB_fixed_Asm_32: {
6190 // Shuffle the operands around so the lane index operand is in the
6193 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6194 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6195 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6196 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6197 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6198 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6199 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6201 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6203 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6205 TmpInst.addOperand(Inst.getOperand(1)); // lane
6206 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6207 TmpInst.addOperand(Inst.getOperand(5));
6212 case ARM::VST1LNdAsm_8:
6213 case ARM::VST1LNdAsm_16:
6214 case ARM::VST1LNdAsm_32: {
6216 // Shuffle the operands around so the lane index operand is in the
6219 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6220 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6221 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6222 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6223 TmpInst.addOperand(Inst.getOperand(1)); // lane
6224 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6225 TmpInst.addOperand(Inst.getOperand(5));
6230 case ARM::VST2LNdAsm_8:
6231 case ARM::VST2LNdAsm_16:
6232 case ARM::VST2LNdAsm_32:
6233 case ARM::VST2LNqAsm_16:
6234 case ARM::VST2LNqAsm_32: {
6236 // Shuffle the operands around so the lane index operand is in the
6239 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6240 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6241 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6242 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6243 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6245 TmpInst.addOperand(Inst.getOperand(1)); // lane
6246 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6247 TmpInst.addOperand(Inst.getOperand(5));
6252 case ARM::VST3LNdAsm_8:
6253 case ARM::VST3LNdAsm_16:
6254 case ARM::VST3LNdAsm_32:
6255 case ARM::VST3LNqAsm_16:
6256 case ARM::VST3LNqAsm_32: {
6258 // Shuffle the operands around so the lane index operand is in the
6261 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6262 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6263 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6264 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6265 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6267 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6269 TmpInst.addOperand(Inst.getOperand(1)); // lane
6270 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6271 TmpInst.addOperand(Inst.getOperand(5));
6276 case ARM::VST4LNdAsm_8:
6277 case ARM::VST4LNdAsm_16:
6278 case ARM::VST4LNdAsm_32:
6279 case ARM::VST4LNqAsm_16:
6280 case ARM::VST4LNqAsm_32: {
6282 // Shuffle the operands around so the lane index operand is in the
6285 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6286 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6287 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6288 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6289 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6291 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6293 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6295 TmpInst.addOperand(Inst.getOperand(1)); // lane
6296 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6297 TmpInst.addOperand(Inst.getOperand(5));
6302 // Handle NEON VLD complex aliases.
6303 case ARM::VLD1LNdWB_register_Asm_8:
6304 case ARM::VLD1LNdWB_register_Asm_16:
6305 case ARM::VLD1LNdWB_register_Asm_32: {
6307 // Shuffle the operands around so the lane index operand is in the
6310 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6311 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6312 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6313 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6314 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6315 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6316 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6317 TmpInst.addOperand(Inst.getOperand(1)); // lane
6318 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6319 TmpInst.addOperand(Inst.getOperand(6));
6324 case ARM::VLD2LNdWB_register_Asm_8:
6325 case ARM::VLD2LNdWB_register_Asm_16:
6326 case ARM::VLD2LNdWB_register_Asm_32:
6327 case ARM::VLD2LNqWB_register_Asm_16:
6328 case ARM::VLD2LNqWB_register_Asm_32: {
6330 // Shuffle the operands around so the lane index operand is in the
6333 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6334 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6335 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6337 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6338 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6339 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6340 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6341 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6342 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6344 TmpInst.addOperand(Inst.getOperand(1)); // lane
6345 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6346 TmpInst.addOperand(Inst.getOperand(6));
6351 case ARM::VLD3LNdWB_register_Asm_8:
6352 case ARM::VLD3LNdWB_register_Asm_16:
6353 case ARM::VLD3LNdWB_register_Asm_32:
6354 case ARM::VLD3LNqWB_register_Asm_16:
6355 case ARM::VLD3LNqWB_register_Asm_32: {
6357 // Shuffle the operands around so the lane index operand is in the
6360 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6361 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6362 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6364 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6366 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6367 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6368 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6369 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6370 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6371 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6373 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6375 TmpInst.addOperand(Inst.getOperand(1)); // lane
6376 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6377 TmpInst.addOperand(Inst.getOperand(6));
6382 case ARM::VLD4LNdWB_register_Asm_8:
6383 case ARM::VLD4LNdWB_register_Asm_16:
6384 case ARM::VLD4LNdWB_register_Asm_32:
6385 case ARM::VLD4LNqWB_register_Asm_16:
6386 case ARM::VLD4LNqWB_register_Asm_32: {
6388 // Shuffle the operands around so the lane index operand is in the
6391 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6392 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6393 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6395 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6397 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6399 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6400 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6401 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6402 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6403 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6404 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6406 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6408 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6410 TmpInst.addOperand(Inst.getOperand(1)); // lane
6411 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6412 TmpInst.addOperand(Inst.getOperand(6));
6417 case ARM::VLD1LNdWB_fixed_Asm_8:
6418 case ARM::VLD1LNdWB_fixed_Asm_16:
6419 case ARM::VLD1LNdWB_fixed_Asm_32: {
6421 // Shuffle the operands around so the lane index operand is in the
6424 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6425 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6426 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6427 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6428 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6429 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6430 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6431 TmpInst.addOperand(Inst.getOperand(1)); // lane
6432 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6433 TmpInst.addOperand(Inst.getOperand(5));
6438 case ARM::VLD2LNdWB_fixed_Asm_8:
6439 case ARM::VLD2LNdWB_fixed_Asm_16:
6440 case ARM::VLD2LNdWB_fixed_Asm_32:
6441 case ARM::VLD2LNqWB_fixed_Asm_16:
6442 case ARM::VLD2LNqWB_fixed_Asm_32: {
6444 // Shuffle the operands around so the lane index operand is in the
6447 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6448 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6449 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6451 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6452 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6453 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6454 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6455 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6456 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6458 TmpInst.addOperand(Inst.getOperand(1)); // lane
6459 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6460 TmpInst.addOperand(Inst.getOperand(5));
6465 case ARM::VLD3LNdWB_fixed_Asm_8:
6466 case ARM::VLD3LNdWB_fixed_Asm_16:
6467 case ARM::VLD3LNdWB_fixed_Asm_32:
6468 case ARM::VLD3LNqWB_fixed_Asm_16:
6469 case ARM::VLD3LNqWB_fixed_Asm_32: {
6471 // Shuffle the operands around so the lane index operand is in the
6474 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6475 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6476 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6478 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6480 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6481 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6482 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6483 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6484 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6485 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6487 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6489 TmpInst.addOperand(Inst.getOperand(1)); // lane
6490 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6491 TmpInst.addOperand(Inst.getOperand(5));
6496 case ARM::VLD4LNdWB_fixed_Asm_8:
6497 case ARM::VLD4LNdWB_fixed_Asm_16:
6498 case ARM::VLD4LNdWB_fixed_Asm_32:
6499 case ARM::VLD4LNqWB_fixed_Asm_16:
6500 case ARM::VLD4LNqWB_fixed_Asm_32: {
6502 // Shuffle the operands around so the lane index operand is in the
6505 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6506 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6507 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6509 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6511 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6513 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6514 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6515 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6516 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6517 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6518 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6520 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6522 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6524 TmpInst.addOperand(Inst.getOperand(1)); // lane
6525 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6526 TmpInst.addOperand(Inst.getOperand(5));
6531 case ARM::VLD1LNdAsm_8:
6532 case ARM::VLD1LNdAsm_16:
6533 case ARM::VLD1LNdAsm_32: {
6535 // Shuffle the operands around so the lane index operand is in the
6538 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6539 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6540 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6541 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6542 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6543 TmpInst.addOperand(Inst.getOperand(1)); // lane
6544 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6545 TmpInst.addOperand(Inst.getOperand(5));
6550 case ARM::VLD2LNdAsm_8:
6551 case ARM::VLD2LNdAsm_16:
6552 case ARM::VLD2LNdAsm_32:
6553 case ARM::VLD2LNqAsm_16:
6554 case ARM::VLD2LNqAsm_32: {
6556 // Shuffle the operands around so the lane index operand is in the
6559 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6560 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6561 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6563 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6564 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6565 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6566 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6568 TmpInst.addOperand(Inst.getOperand(1)); // lane
6569 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6570 TmpInst.addOperand(Inst.getOperand(5));
6575 case ARM::VLD3LNdAsm_8:
6576 case ARM::VLD3LNdAsm_16:
6577 case ARM::VLD3LNdAsm_32:
6578 case ARM::VLD3LNqAsm_16:
6579 case ARM::VLD3LNqAsm_32: {
6581 // Shuffle the operands around so the lane index operand is in the
6584 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6585 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6586 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6588 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6590 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6591 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6592 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6593 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6595 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6597 TmpInst.addOperand(Inst.getOperand(1)); // lane
6598 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6599 TmpInst.addOperand(Inst.getOperand(5));
6604 case ARM::VLD4LNdAsm_8:
6605 case ARM::VLD4LNdAsm_16:
6606 case ARM::VLD4LNdAsm_32:
6607 case ARM::VLD4LNqAsm_16:
6608 case ARM::VLD4LNqAsm_32: {
6610 // Shuffle the operands around so the lane index operand is in the
6613 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6614 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6615 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6617 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6619 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6621 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6622 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6623 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6624 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6626 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6628 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6630 TmpInst.addOperand(Inst.getOperand(1)); // lane
6631 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6632 TmpInst.addOperand(Inst.getOperand(5));
6637 // VLD3DUP single 3-element structure to all lanes instructions.
6638 case ARM::VLD3DUPdAsm_8:
6639 case ARM::VLD3DUPdAsm_16:
6640 case ARM::VLD3DUPdAsm_32:
6641 case ARM::VLD3DUPqAsm_8:
6642 case ARM::VLD3DUPqAsm_16:
6643 case ARM::VLD3DUPqAsm_32: {
6646 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6647 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6648 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6650 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6652 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6653 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6654 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6655 TmpInst.addOperand(Inst.getOperand(4));
6660 case ARM::VLD3DUPdWB_fixed_Asm_8:
6661 case ARM::VLD3DUPdWB_fixed_Asm_16:
6662 case ARM::VLD3DUPdWB_fixed_Asm_32:
6663 case ARM::VLD3DUPqWB_fixed_Asm_8:
6664 case ARM::VLD3DUPqWB_fixed_Asm_16:
6665 case ARM::VLD3DUPqWB_fixed_Asm_32: {
6668 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6669 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6670 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6672 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6674 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6675 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6676 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6677 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6678 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6679 TmpInst.addOperand(Inst.getOperand(4));
6684 case ARM::VLD3DUPdWB_register_Asm_8:
6685 case ARM::VLD3DUPdWB_register_Asm_16:
6686 case ARM::VLD3DUPdWB_register_Asm_32:
6687 case ARM::VLD3DUPqWB_register_Asm_8:
6688 case ARM::VLD3DUPqWB_register_Asm_16:
6689 case ARM::VLD3DUPqWB_register_Asm_32: {
6692 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6693 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6694 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6696 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6698 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6699 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6700 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6701 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6702 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6703 TmpInst.addOperand(Inst.getOperand(5));
6708 // VLD3 multiple 3-element structure instructions.
6709 case ARM::VLD3dAsm_8:
6710 case ARM::VLD3dAsm_16:
6711 case ARM::VLD3dAsm_32:
6712 case ARM::VLD3qAsm_8:
6713 case ARM::VLD3qAsm_16:
6714 case ARM::VLD3qAsm_32: {
6717 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6718 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6719 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6721 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6723 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6724 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6725 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6726 TmpInst.addOperand(Inst.getOperand(4));
6731 case ARM::VLD3dWB_fixed_Asm_8:
6732 case ARM::VLD3dWB_fixed_Asm_16:
6733 case ARM::VLD3dWB_fixed_Asm_32:
6734 case ARM::VLD3qWB_fixed_Asm_8:
6735 case ARM::VLD3qWB_fixed_Asm_16:
6736 case ARM::VLD3qWB_fixed_Asm_32: {
6739 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6740 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6741 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6743 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6745 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6746 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6747 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6748 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6749 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6750 TmpInst.addOperand(Inst.getOperand(4));
6755 case ARM::VLD3dWB_register_Asm_8:
6756 case ARM::VLD3dWB_register_Asm_16:
6757 case ARM::VLD3dWB_register_Asm_32:
6758 case ARM::VLD3qWB_register_Asm_8:
6759 case ARM::VLD3qWB_register_Asm_16:
6760 case ARM::VLD3qWB_register_Asm_32: {
6763 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6764 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6765 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6767 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6769 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6770 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6771 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6772 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6773 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6774 TmpInst.addOperand(Inst.getOperand(5));
6779 // VLD4DUP single 3-element structure to all lanes instructions.
6780 case ARM::VLD4DUPdAsm_8:
6781 case ARM::VLD4DUPdAsm_16:
6782 case ARM::VLD4DUPdAsm_32:
6783 case ARM::VLD4DUPqAsm_8:
6784 case ARM::VLD4DUPqAsm_16:
6785 case ARM::VLD4DUPqAsm_32: {
6788 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6789 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6790 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6792 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6794 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6796 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6797 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6798 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6799 TmpInst.addOperand(Inst.getOperand(4));
6804 case ARM::VLD4DUPdWB_fixed_Asm_8:
6805 case ARM::VLD4DUPdWB_fixed_Asm_16:
6806 case ARM::VLD4DUPdWB_fixed_Asm_32:
6807 case ARM::VLD4DUPqWB_fixed_Asm_8:
6808 case ARM::VLD4DUPqWB_fixed_Asm_16:
6809 case ARM::VLD4DUPqWB_fixed_Asm_32: {
6812 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6813 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6814 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6816 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6818 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6820 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6821 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6822 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6823 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6824 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6825 TmpInst.addOperand(Inst.getOperand(4));
6830 case ARM::VLD4DUPdWB_register_Asm_8:
6831 case ARM::VLD4DUPdWB_register_Asm_16:
6832 case ARM::VLD4DUPdWB_register_Asm_32:
6833 case ARM::VLD4DUPqWB_register_Asm_8:
6834 case ARM::VLD4DUPqWB_register_Asm_16:
6835 case ARM::VLD4DUPqWB_register_Asm_32: {
6838 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6839 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6840 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6842 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6844 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6846 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6847 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6848 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6849 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6850 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6851 TmpInst.addOperand(Inst.getOperand(5));
6856 // VLD4 multiple 4-element structure instructions.
6857 case ARM::VLD4dAsm_8:
6858 case ARM::VLD4dAsm_16:
6859 case ARM::VLD4dAsm_32:
6860 case ARM::VLD4qAsm_8:
6861 case ARM::VLD4qAsm_16:
6862 case ARM::VLD4qAsm_32: {
6865 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6866 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6867 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6869 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6871 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6873 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6874 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6875 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6876 TmpInst.addOperand(Inst.getOperand(4));
6881 case ARM::VLD4dWB_fixed_Asm_8:
6882 case ARM::VLD4dWB_fixed_Asm_16:
6883 case ARM::VLD4dWB_fixed_Asm_32:
6884 case ARM::VLD4qWB_fixed_Asm_8:
6885 case ARM::VLD4qWB_fixed_Asm_16:
6886 case ARM::VLD4qWB_fixed_Asm_32: {
6889 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6890 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6891 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6893 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6895 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6897 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6898 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6899 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6900 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6901 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6902 TmpInst.addOperand(Inst.getOperand(4));
6907 case ARM::VLD4dWB_register_Asm_8:
6908 case ARM::VLD4dWB_register_Asm_16:
6909 case ARM::VLD4dWB_register_Asm_32:
6910 case ARM::VLD4qWB_register_Asm_8:
6911 case ARM::VLD4qWB_register_Asm_16:
6912 case ARM::VLD4qWB_register_Asm_32: {
6915 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6916 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6917 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6919 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6921 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6923 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6924 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6925 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6926 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6927 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6928 TmpInst.addOperand(Inst.getOperand(5));
6933 // VST3 multiple 3-element structure instructions.
6934 case ARM::VST3dAsm_8:
6935 case ARM::VST3dAsm_16:
6936 case ARM::VST3dAsm_32:
6937 case ARM::VST3qAsm_8:
6938 case ARM::VST3qAsm_16:
6939 case ARM::VST3qAsm_32: {
6942 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6943 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6944 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6945 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6946 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6948 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6950 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6951 TmpInst.addOperand(Inst.getOperand(4));
6956 case ARM::VST3dWB_fixed_Asm_8:
6957 case ARM::VST3dWB_fixed_Asm_16:
6958 case ARM::VST3dWB_fixed_Asm_32:
6959 case ARM::VST3qWB_fixed_Asm_8:
6960 case ARM::VST3qWB_fixed_Asm_16:
6961 case ARM::VST3qWB_fixed_Asm_32: {
6964 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6965 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6966 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6967 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6968 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6969 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6970 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6972 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6974 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6975 TmpInst.addOperand(Inst.getOperand(4));
6980 case ARM::VST3dWB_register_Asm_8:
6981 case ARM::VST3dWB_register_Asm_16:
6982 case ARM::VST3dWB_register_Asm_32:
6983 case ARM::VST3qWB_register_Asm_8:
6984 case ARM::VST3qWB_register_Asm_16:
6985 case ARM::VST3qWB_register_Asm_32: {
6988 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6989 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6990 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6991 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6992 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6993 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6994 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6996 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6998 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6999 TmpInst.addOperand(Inst.getOperand(5));
7004 // VST4 multiple 3-element structure instructions.
7005 case ARM::VST4dAsm_8:
7006 case ARM::VST4dAsm_16:
7007 case ARM::VST4dAsm_32:
7008 case ARM::VST4qAsm_8:
7009 case ARM::VST4qAsm_16:
7010 case ARM::VST4qAsm_32: {
7013 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7014 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7015 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7016 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7017 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7019 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7021 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7023 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7024 TmpInst.addOperand(Inst.getOperand(4));
7029 case ARM::VST4dWB_fixed_Asm_8:
7030 case ARM::VST4dWB_fixed_Asm_16:
7031 case ARM::VST4dWB_fixed_Asm_32:
7032 case ARM::VST4qWB_fixed_Asm_8:
7033 case ARM::VST4qWB_fixed_Asm_16:
7034 case ARM::VST4qWB_fixed_Asm_32: {
7037 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7038 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7039 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7040 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7041 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7042 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7043 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7045 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7047 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7049 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7050 TmpInst.addOperand(Inst.getOperand(4));
7055 case ARM::VST4dWB_register_Asm_8:
7056 case ARM::VST4dWB_register_Asm_16:
7057 case ARM::VST4dWB_register_Asm_32:
7058 case ARM::VST4qWB_register_Asm_8:
7059 case ARM::VST4qWB_register_Asm_16:
7060 case ARM::VST4qWB_register_Asm_32: {
7063 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7064 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7065 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7066 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7067 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7068 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7069 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7071 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7073 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7075 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7076 TmpInst.addOperand(Inst.getOperand(5));
7081 // Handle encoding choice for the shift-immediate instructions.
7084 case ARM::t2ASRri: {
7085 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7086 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7087 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
7088 !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
7089 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
7091 switch (Inst.getOpcode()) {
7092 default: llvm_unreachable("unexpected opcode");
7093 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
7094 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
7095 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
7097 // The Thumb1 operands aren't in the same order. Awesome, eh?
7099 TmpInst.setOpcode(NewOpc);
7100 TmpInst.addOperand(Inst.getOperand(0));
7101 TmpInst.addOperand(Inst.getOperand(5));
7102 TmpInst.addOperand(Inst.getOperand(1));
7103 TmpInst.addOperand(Inst.getOperand(2));
7104 TmpInst.addOperand(Inst.getOperand(3));
7105 TmpInst.addOperand(Inst.getOperand(4));
7112 // Handle the Thumb2 mode MOV complex aliases.
7114 case ARM::t2MOVSsr: {
7115 // Which instruction to expand to depends on the CCOut operand and
7116 // whether we're in an IT block if the register operands are low
7118 bool isNarrow = false;
7119 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7120 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7121 isARMLowRegister(Inst.getOperand(2).getReg()) &&
7122 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7123 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
7127 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
7128 default: llvm_unreachable("unexpected opcode!");
7129 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7130 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7131 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7132 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
7134 TmpInst.setOpcode(newOpc);
7135 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7137 TmpInst.addOperand(MCOperand::CreateReg(
7138 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7139 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7140 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7141 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7142 TmpInst.addOperand(Inst.getOperand(5));
7144 TmpInst.addOperand(MCOperand::CreateReg(
7145 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7150 case ARM::t2MOVSsi: {
7151 // Which instruction to expand to depends on the CCOut operand and
7152 // whether we're in an IT block if the register operands are low
7154 bool isNarrow = false;
7155 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7156 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7157 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
7161 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
7162 default: llvm_unreachable("unexpected opcode!");
7163 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7164 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7165 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7166 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7167 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7169 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
7170 if (Amount == 32) Amount = 0;
7171 TmpInst.setOpcode(newOpc);
7172 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7174 TmpInst.addOperand(MCOperand::CreateReg(
7175 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7176 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7177 if (newOpc != ARM::t2RRX)
7178 TmpInst.addOperand(MCOperand::CreateImm(Amount));
7179 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7180 TmpInst.addOperand(Inst.getOperand(4));
7182 TmpInst.addOperand(MCOperand::CreateReg(
7183 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7187 // Handle the ARM mode MOV complex aliases.
7192 ARM_AM::ShiftOpc ShiftTy;
7193 switch(Inst.getOpcode()) {
7194 default: llvm_unreachable("unexpected opcode!");
7195 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
7196 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
7197 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
7198 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
7200 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
7202 TmpInst.setOpcode(ARM::MOVsr);
7203 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7204 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7205 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7206 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7207 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7208 TmpInst.addOperand(Inst.getOperand(4));
7209 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7217 ARM_AM::ShiftOpc ShiftTy;
7218 switch(Inst.getOpcode()) {
7219 default: llvm_unreachable("unexpected opcode!");
7220 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
7221 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
7222 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7223 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
7225 // A shift by zero is a plain MOVr, not a MOVsi.
7226 unsigned Amt = Inst.getOperand(2).getImm();
7227 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
7228 // A shift by 32 should be encoded as 0 when permitted
7229 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
7231 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
7233 TmpInst.setOpcode(Opc);
7234 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7235 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7236 if (Opc == ARM::MOVsi)
7237 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7238 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7239 TmpInst.addOperand(Inst.getOperand(4));
7240 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7245 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
7247 TmpInst.setOpcode(ARM::MOVsi);
7248 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7249 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7250 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7251 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7252 TmpInst.addOperand(Inst.getOperand(3));
7253 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7257 case ARM::t2LDMIA_UPD: {
7258 // If this is a load of a single register, then we should use
7259 // a post-indexed LDR instruction instead, per the ARM ARM.
7260 if (Inst.getNumOperands() != 5)
7263 TmpInst.setOpcode(ARM::t2LDR_POST);
7264 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7265 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7266 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7267 TmpInst.addOperand(MCOperand::CreateImm(4));
7268 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7269 TmpInst.addOperand(Inst.getOperand(3));
7273 case ARM::t2STMDB_UPD: {
7274 // If this is a store of a single register, then we should use
7275 // a pre-indexed STR instruction instead, per the ARM ARM.
7276 if (Inst.getNumOperands() != 5)
7279 TmpInst.setOpcode(ARM::t2STR_PRE);
7280 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7281 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7282 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7283 TmpInst.addOperand(MCOperand::CreateImm(-4));
7284 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7285 TmpInst.addOperand(Inst.getOperand(3));
7289 case ARM::LDMIA_UPD:
7290 // If this is a load of a single register via a 'pop', then we should use
7291 // a post-indexed LDR instruction instead, per the ARM ARM.
7292 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
7293 Inst.getNumOperands() == 5) {
7295 TmpInst.setOpcode(ARM::LDR_POST_IMM);
7296 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7297 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7298 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7299 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
7300 TmpInst.addOperand(MCOperand::CreateImm(4));
7301 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7302 TmpInst.addOperand(Inst.getOperand(3));
7307 case ARM::STMDB_UPD:
7308 // If this is a store of a single register via a 'push', then we should use
7309 // a pre-indexed STR instruction instead, per the ARM ARM.
7310 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
7311 Inst.getNumOperands() == 5) {
7313 TmpInst.setOpcode(ARM::STR_PRE_IMM);
7314 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7315 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7316 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7317 TmpInst.addOperand(MCOperand::CreateImm(-4));
7318 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7319 TmpInst.addOperand(Inst.getOperand(3));
7323 case ARM::t2ADDri12:
7324 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7325 // mnemonic was used (not "addw"), encoding T3 is preferred.
7326 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
7327 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7329 Inst.setOpcode(ARM::t2ADDri);
7330 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7332 case ARM::t2SUBri12:
7333 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7334 // mnemonic was used (not "subw"), encoding T3 is preferred.
7335 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7336 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7338 Inst.setOpcode(ARM::t2SUBri);
7339 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7342 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7343 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7344 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7345 // to encoding T1 if <Rd> is omitted."
7346 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7347 Inst.setOpcode(ARM::tADDi3);
7352 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7353 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7354 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7355 // to encoding T1 if <Rd> is omitted."
7356 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7357 Inst.setOpcode(ARM::tSUBi3);
7362 case ARM::t2SUBri: {
7363 // If the destination and first source operand are the same, and
7364 // the flags are compatible with the current IT status, use encoding T2
7365 // instead of T3. For compatibility with the system 'as'. Make sure the
7366 // wide encoding wasn't explicit.
7367 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7368 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7369 (unsigned)Inst.getOperand(2).getImm() > 255 ||
7370 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7371 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7372 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7373 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7376 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7377 ARM::tADDi8 : ARM::tSUBi8);
7378 TmpInst.addOperand(Inst.getOperand(0));
7379 TmpInst.addOperand(Inst.getOperand(5));
7380 TmpInst.addOperand(Inst.getOperand(0));
7381 TmpInst.addOperand(Inst.getOperand(2));
7382 TmpInst.addOperand(Inst.getOperand(3));
7383 TmpInst.addOperand(Inst.getOperand(4));
7387 case ARM::t2ADDrr: {
7388 // If the destination and first source operand are the same, and
7389 // there's no setting of the flags, use encoding T2 instead of T3.
7390 // Note that this is only for ADD, not SUB. This mirrors the system
7391 // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7392 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7393 Inst.getOperand(5).getReg() != 0 ||
7394 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7395 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7398 TmpInst.setOpcode(ARM::tADDhirr);
7399 TmpInst.addOperand(Inst.getOperand(0));
7400 TmpInst.addOperand(Inst.getOperand(0));
7401 TmpInst.addOperand(Inst.getOperand(2));
7402 TmpInst.addOperand(Inst.getOperand(3));
7403 TmpInst.addOperand(Inst.getOperand(4));
7407 case ARM::tADDrSP: {
7408 // If the non-SP source operand and the destination operand are not the
7409 // same, we need to use the 32-bit encoding if it's available.
7410 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7411 Inst.setOpcode(ARM::t2ADDrr);
7412 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7418 // A Thumb conditional branch outside of an IT block is a tBcc.
7419 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7420 Inst.setOpcode(ARM::tBcc);
7425 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7426 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7427 Inst.setOpcode(ARM::t2Bcc);
7432 // If the conditional is AL or we're in an IT block, we really want t2B.
7433 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7434 Inst.setOpcode(ARM::t2B);
7439 // If the conditional is AL, we really want tB.
7440 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7441 Inst.setOpcode(ARM::tB);
7446 // If the register list contains any high registers, or if the writeback
7447 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7448 // instead if we're in Thumb2. Otherwise, this should have generated
7449 // an error in validateInstruction().
7450 unsigned Rn = Inst.getOperand(0).getReg();
7451 bool hasWritebackToken =
7452 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7453 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7454 bool listContainsBase;
7455 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7456 (!listContainsBase && !hasWritebackToken) ||
7457 (listContainsBase && hasWritebackToken)) {
7458 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7459 assert (isThumbTwo());
7460 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7461 // If we're switching to the updating version, we need to insert
7462 // the writeback tied operand.
7463 if (hasWritebackToken)
7464 Inst.insert(Inst.begin(),
7465 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7470 case ARM::tSTMIA_UPD: {
7471 // If the register list contains any high registers, we need to use
7472 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7473 // should have generated an error in validateInstruction().
7474 unsigned Rn = Inst.getOperand(0).getReg();
7475 bool listContainsBase;
7476 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7477 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7478 assert (isThumbTwo());
7479 Inst.setOpcode(ARM::t2STMIA_UPD);
7485 bool listContainsBase;
7486 // If the register list contains any high registers, we need to use
7487 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7488 // should have generated an error in validateInstruction().
7489 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7491 assert (isThumbTwo());
7492 Inst.setOpcode(ARM::t2LDMIA_UPD);
7493 // Add the base register and writeback operands.
7494 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7495 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7499 bool listContainsBase;
7500 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7502 assert (isThumbTwo());
7503 Inst.setOpcode(ARM::t2STMDB_UPD);
7504 // Add the base register and writeback operands.
7505 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7506 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7510 // If we can use the 16-bit encoding and the user didn't explicitly
7511 // request the 32-bit variant, transform it here.
7512 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7513 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7514 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7515 Inst.getOperand(4).getReg() == ARM::CPSR) ||
7516 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7517 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7518 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7519 // The operands aren't in the same order for tMOVi8...
7521 TmpInst.setOpcode(ARM::tMOVi8);
7522 TmpInst.addOperand(Inst.getOperand(0));
7523 TmpInst.addOperand(Inst.getOperand(4));
7524 TmpInst.addOperand(Inst.getOperand(1));
7525 TmpInst.addOperand(Inst.getOperand(2));
7526 TmpInst.addOperand(Inst.getOperand(3));
7533 // If we can use the 16-bit encoding and the user didn't explicitly
7534 // request the 32-bit variant, transform it here.
7535 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7536 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7537 Inst.getOperand(2).getImm() == ARMCC::AL &&
7538 Inst.getOperand(4).getReg() == ARM::CPSR &&
7539 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7540 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7541 // The operands aren't the same for tMOV[S]r... (no cc_out)
7543 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7544 TmpInst.addOperand(Inst.getOperand(0));
7545 TmpInst.addOperand(Inst.getOperand(1));
7546 TmpInst.addOperand(Inst.getOperand(2));
7547 TmpInst.addOperand(Inst.getOperand(3));
7557 // If we can use the 16-bit encoding and the user didn't explicitly
7558 // request the 32-bit variant, transform it here.
7559 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7560 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7561 Inst.getOperand(2).getImm() == 0 &&
7562 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7563 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7565 switch (Inst.getOpcode()) {
7566 default: llvm_unreachable("Illegal opcode!");
7567 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7568 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7569 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7570 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7572 // The operands aren't the same for thumb1 (no rotate operand).
7574 TmpInst.setOpcode(NewOpc);
7575 TmpInst.addOperand(Inst.getOperand(0));
7576 TmpInst.addOperand(Inst.getOperand(1));
7577 TmpInst.addOperand(Inst.getOperand(3));
7578 TmpInst.addOperand(Inst.getOperand(4));
7585 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7586 // rrx shifts and asr/lsr of #32 is encoded as 0
7587 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7589 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7590 // Shifting by zero is accepted as a vanilla 'MOVr'
7592 TmpInst.setOpcode(ARM::MOVr);
7593 TmpInst.addOperand(Inst.getOperand(0));
7594 TmpInst.addOperand(Inst.getOperand(1));
7595 TmpInst.addOperand(Inst.getOperand(3));
7596 TmpInst.addOperand(Inst.getOperand(4));
7597 TmpInst.addOperand(Inst.getOperand(5));
7610 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7611 if (SOpc == ARM_AM::rrx) return false;
7612 switch (Inst.getOpcode()) {
7613 default: llvm_unreachable("unexpected opcode!");
7614 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7615 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7616 case ARM::EORrsi: newOpc = ARM::EORrr; break;
7617 case ARM::BICrsi: newOpc = ARM::BICrr; break;
7618 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7619 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7621 // If the shift is by zero, use the non-shifted instruction definition.
7622 // The exception is for right shifts, where 0 == 32
7623 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7624 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7626 TmpInst.setOpcode(newOpc);
7627 TmpInst.addOperand(Inst.getOperand(0));
7628 TmpInst.addOperand(Inst.getOperand(1));
7629 TmpInst.addOperand(Inst.getOperand(2));
7630 TmpInst.addOperand(Inst.getOperand(4));
7631 TmpInst.addOperand(Inst.getOperand(5));
7632 TmpInst.addOperand(Inst.getOperand(6));
7640 // The mask bits for all but the first condition are represented as
7641 // the low bit of the condition code value implies 't'. We currently
7642 // always have 1 implies 't', so XOR toggle the bits if the low bit
7643 // of the condition code is zero.
7644 MCOperand &MO = Inst.getOperand(1);
7645 unsigned Mask = MO.getImm();
7646 unsigned OrigMask = Mask;
7647 unsigned TZ = countTrailingZeros(Mask);
7648 if ((Inst.getOperand(0).getImm() & 1) == 0) {
7649 assert(Mask && TZ <= 3 && "illegal IT mask value!");
7650 Mask ^= (0xE << TZ) & 0xF;
7654 // Set up the IT block state according to the IT instruction we just
7656 assert(!inITBlock() && "nested IT blocks?!");
7657 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7658 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7659 ITState.CurPosition = 0;
7660 ITState.FirstCond = true;
7670 // Assemblers should use the narrow encodings of these instructions when permissible.
7671 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7672 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7673 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7674 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7675 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7676 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7677 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7679 switch (Inst.getOpcode()) {
7680 default: llvm_unreachable("unexpected opcode");
7681 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7682 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7683 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7684 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7685 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7686 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7689 TmpInst.setOpcode(NewOpc);
7690 TmpInst.addOperand(Inst.getOperand(0));
7691 TmpInst.addOperand(Inst.getOperand(5));
7692 TmpInst.addOperand(Inst.getOperand(1));
7693 TmpInst.addOperand(Inst.getOperand(2));
7694 TmpInst.addOperand(Inst.getOperand(3));
7695 TmpInst.addOperand(Inst.getOperand(4));
7706 // Assemblers should use the narrow encodings of these instructions when permissible.
7707 // These instructions are special in that they are commutable, so shorter encodings
7708 // are available more often.
7709 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7710 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7711 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7712 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7713 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7714 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7715 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7716 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7718 switch (Inst.getOpcode()) {
7719 default: llvm_unreachable("unexpected opcode");
7720 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7721 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7722 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7723 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7726 TmpInst.setOpcode(NewOpc);
7727 TmpInst.addOperand(Inst.getOperand(0));
7728 TmpInst.addOperand(Inst.getOperand(5));
7729 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7730 TmpInst.addOperand(Inst.getOperand(1));
7731 TmpInst.addOperand(Inst.getOperand(2));
7733 TmpInst.addOperand(Inst.getOperand(2));
7734 TmpInst.addOperand(Inst.getOperand(1));
7736 TmpInst.addOperand(Inst.getOperand(3));
7737 TmpInst.addOperand(Inst.getOperand(4));
7747 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7748 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7749 // suffix depending on whether they're in an IT block or not.
7750 unsigned Opc = Inst.getOpcode();
7751 const MCInstrDesc &MCID = MII.get(Opc);
7752 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7753 assert(MCID.hasOptionalDef() &&
7754 "optionally flag setting instruction missing optional def operand");
7755 assert(MCID.NumOperands == Inst.getNumOperands() &&
7756 "operand count mismatch!");
7757 // Find the optional-def operand (cc_out).
7760 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7763 // If we're parsing Thumb1, reject it completely.
7764 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7765 return Match_MnemonicFail;
7766 // If we're parsing Thumb2, which form is legal depends on whether we're
7768 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7770 return Match_RequiresITBlock;
7771 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7773 return Match_RequiresNotITBlock;
7775 // Some high-register supporting Thumb1 encodings only allow both registers
7776 // to be from r0-r7 when in Thumb2.
7777 else if (Opc == ARM::tADDhirr && isThumbOne() &&
7778 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7779 isARMLowRegister(Inst.getOperand(2).getReg()))
7780 return Match_RequiresThumb2;
7781 // Others only require ARMv6 or later.
7782 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7783 isARMLowRegister(Inst.getOperand(0).getReg()) &&
7784 isARMLowRegister(Inst.getOperand(1).getReg()))
7785 return Match_RequiresV6;
7786 return Match_Success;
7789 static const char *getSubtargetFeatureName(unsigned Val);
7791 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
7792 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
7793 MCStreamer &Out, unsigned &ErrorInfo,
7794 bool MatchingInlineAsm) {
7796 unsigned MatchResult;
7798 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
7800 switch (MatchResult) {
7803 // Context sensitive operand constraints aren't handled by the matcher,
7804 // so check them here.
7805 if (validateInstruction(Inst, Operands)) {
7806 // Still progress the IT block, otherwise one wrong condition causes
7807 // nasty cascading errors.
7808 forwardITPosition();
7812 { // processInstruction() updates inITBlock state, we need to save it away
7813 bool wasInITBlock = inITBlock();
7815 // Some instructions need post-processing to, for example, tweak which
7816 // encoding is selected. Loop on it while changes happen so the
7817 // individual transformations can chain off each other. E.g.,
7818 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
7819 while (processInstruction(Inst, Operands))
7822 // Only after the instruction is fully processed, we can validate it
7823 if (wasInITBlock && hasV8Ops() && isThumb() &&
7824 !isV8EligibleForIT(&Inst, 2)) {
7825 Warning(IDLoc, "deprecated instruction in IT block");
7829 // Only move forward at the very end so that everything in validate
7830 // and process gets a consistent answer about whether we're in an IT
7832 forwardITPosition();
7834 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7835 // doesn't actually encode.
7836 if (Inst.getOpcode() == ARM::ITasm)
7840 Out.EmitInstruction(Inst);
7842 case Match_MissingFeature: {
7843 assert(ErrorInfo && "Unknown missing feature!");
7844 // Special case the error message for the very common case where only
7845 // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
7846 std::string Msg = "instruction requires:";
7848 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
7849 if (ErrorInfo & Mask) {
7851 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
7855 return Error(IDLoc, Msg);
7857 case Match_InvalidOperand: {
7858 SMLoc ErrorLoc = IDLoc;
7859 if (ErrorInfo != ~0U) {
7860 if (ErrorInfo >= Operands.size())
7861 return Error(IDLoc, "too few operands for instruction");
7863 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7864 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7867 return Error(ErrorLoc, "invalid operand for instruction");
7869 case Match_MnemonicFail:
7870 return Error(IDLoc, "invalid instruction",
7871 ((ARMOperand*)Operands[0])->getLocRange());
7872 case Match_RequiresNotITBlock:
7873 return Error(IDLoc, "flag setting instruction only valid outside IT block");
7874 case Match_RequiresITBlock:
7875 return Error(IDLoc, "instruction only valid inside IT block");
7876 case Match_RequiresV6:
7877 return Error(IDLoc, "instruction variant requires ARMv6 or later");
7878 case Match_RequiresThumb2:
7879 return Error(IDLoc, "instruction variant requires Thumb2");
7880 case Match_ImmRange0_15: {
7881 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7882 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7883 return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
7885 case Match_ImmRange0_239: {
7886 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7887 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7888 return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
7892 llvm_unreachable("Implement any new match types added!");
7895 /// parseDirective parses the arm specific directives
7896 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
7897 StringRef IDVal = DirectiveID.getIdentifier();
7898 if (IDVal == ".word")
7899 return parseDirectiveWord(4, DirectiveID.getLoc());
7900 else if (IDVal == ".thumb")
7901 return parseDirectiveThumb(DirectiveID.getLoc());
7902 else if (IDVal == ".arm")
7903 return parseDirectiveARM(DirectiveID.getLoc());
7904 else if (IDVal == ".thumb_func")
7905 return parseDirectiveThumbFunc(DirectiveID.getLoc());
7906 else if (IDVal == ".code")
7907 return parseDirectiveCode(DirectiveID.getLoc());
7908 else if (IDVal == ".syntax")
7909 return parseDirectiveSyntax(DirectiveID.getLoc());
7910 else if (IDVal == ".unreq")
7911 return parseDirectiveUnreq(DirectiveID.getLoc());
7912 else if (IDVal == ".arch")
7913 return parseDirectiveArch(DirectiveID.getLoc());
7914 else if (IDVal == ".eabi_attribute")
7915 return parseDirectiveEabiAttr(DirectiveID.getLoc());
7916 else if (IDVal == ".cpu")
7917 return parseDirectiveCPU(DirectiveID.getLoc());
7918 else if (IDVal == ".fpu")
7919 return parseDirectiveFPU(DirectiveID.getLoc());
7920 else if (IDVal == ".fnstart")
7921 return parseDirectiveFnStart(DirectiveID.getLoc());
7922 else if (IDVal == ".fnend")
7923 return parseDirectiveFnEnd(DirectiveID.getLoc());
7924 else if (IDVal == ".cantunwind")
7925 return parseDirectiveCantUnwind(DirectiveID.getLoc());
7926 else if (IDVal == ".personality")
7927 return parseDirectivePersonality(DirectiveID.getLoc());
7928 else if (IDVal == ".handlerdata")
7929 return parseDirectiveHandlerData(DirectiveID.getLoc());
7930 else if (IDVal == ".setfp")
7931 return parseDirectiveSetFP(DirectiveID.getLoc());
7932 else if (IDVal == ".pad")
7933 return parseDirectivePad(DirectiveID.getLoc());
7934 else if (IDVal == ".save")
7935 return parseDirectiveRegSave(DirectiveID.getLoc(), false);
7936 else if (IDVal == ".vsave")
7937 return parseDirectiveRegSave(DirectiveID.getLoc(), true);
7938 else if (IDVal == ".inst")
7939 return parseDirectiveInst(DirectiveID.getLoc());
7940 else if (IDVal == ".inst.n")
7941 return parseDirectiveInst(DirectiveID.getLoc(), 'n');
7942 else if (IDVal == ".inst.w")
7943 return parseDirectiveInst(DirectiveID.getLoc(), 'w');
7944 else if (IDVal == ".ltorg" || IDVal == ".pool")
7945 return parseDirectiveLtorg(DirectiveID.getLoc());
7946 else if (IDVal == ".even")
7947 return parseDirectiveEven(DirectiveID.getLoc());
7951 /// parseDirectiveWord
7952 /// ::= .word [ expression (, expression)* ]
7953 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
7954 if (getLexer().isNot(AsmToken::EndOfStatement)) {
7956 const MCExpr *Value;
7957 if (getParser().parseExpression(Value))
7960 getParser().getStreamer().EmitValue(Value, Size);
7962 if (getLexer().is(AsmToken::EndOfStatement))
7965 // FIXME: Improve diagnostic.
7966 if (getLexer().isNot(AsmToken::Comma))
7967 return Error(L, "unexpected token in directive");
7976 /// parseDirectiveThumb
7978 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
7979 if (getLexer().isNot(AsmToken::EndOfStatement))
7980 return Error(L, "unexpected token in directive");
7984 return Error(L, "target does not support Thumb mode");
7988 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7992 /// parseDirectiveARM
7994 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
7995 if (getLexer().isNot(AsmToken::EndOfStatement))
7996 return Error(L, "unexpected token in directive");
8000 return Error(L, "target does not support ARM mode");
8004 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8008 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
8009 if (NextSymbolIsThumb) {
8010 getParser().getStreamer().EmitThumbFunc(Symbol);
8011 NextSymbolIsThumb = false;
8015 /// parseDirectiveThumbFunc
8016 /// ::= .thumbfunc symbol_name
8017 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
8018 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
8019 bool isMachO = MAI->hasSubsectionsViaSymbols();
8021 // Darwin asm has (optionally) function name after .thumb_func direction
8024 const AsmToken &Tok = Parser.getTok();
8025 if (Tok.isNot(AsmToken::EndOfStatement)) {
8026 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
8027 return Error(L, "unexpected token in .thumb_func directive");
8029 getParser().getContext().GetOrCreateSymbol(Tok.getIdentifier());
8030 getParser().getStreamer().EmitThumbFunc(Func);
8031 Parser.Lex(); // Consume the identifier token.
8036 if (getLexer().isNot(AsmToken::EndOfStatement))
8037 return Error(L, "unexpected token in directive");
8039 NextSymbolIsThumb = true;
8044 /// parseDirectiveSyntax
8045 /// ::= .syntax unified | divided
8046 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
8047 const AsmToken &Tok = Parser.getTok();
8048 if (Tok.isNot(AsmToken::Identifier))
8049 return Error(L, "unexpected token in .syntax directive");
8050 StringRef Mode = Tok.getString();
8051 if (Mode == "unified" || Mode == "UNIFIED")
8053 else if (Mode == "divided" || Mode == "DIVIDED")
8054 return Error(L, "'.syntax divided' arm asssembly not supported");
8056 return Error(L, "unrecognized syntax mode in .syntax directive");
8058 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8059 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8064 // TODO tell the MC streamer the mode
8065 // getParser().getStreamer().Emit???();
8069 /// parseDirectiveCode
8070 /// ::= .code 16 | 32
8071 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
8072 const AsmToken &Tok = Parser.getTok();
8073 if (Tok.isNot(AsmToken::Integer)) {
8074 Error(L, "unexpected token in .code directive");
8077 int64_t Val = Parser.getTok().getIntVal();
8078 if (Val != 16 && Val != 32) {
8079 Error(L, "invalid operand to .code directive");
8084 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8085 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8092 Error(L, "target does not support Thumb mode");
8098 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8101 Error(L, "target does not support ARM mode");
8107 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8113 /// parseDirectiveReq
8114 /// ::= name .req registername
8115 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
8116 Parser.Lex(); // Eat the '.req' token.
8118 SMLoc SRegLoc, ERegLoc;
8119 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
8120 Parser.eatToEndOfStatement();
8121 Error(SRegLoc, "register name expected");
8125 // Shouldn't be anything else.
8126 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
8127 Parser.eatToEndOfStatement();
8128 Error(Parser.getTok().getLoc(), "unexpected input in .req directive.");
8132 Parser.Lex(); // Consume the EndOfStatement
8134 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg) {
8135 Error(SRegLoc, "redefinition of '" + Name + "' does not match original.");
8142 /// parseDirectiveUneq
8143 /// ::= .unreq registername
8144 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
8145 if (Parser.getTok().isNot(AsmToken::Identifier)) {
8146 Parser.eatToEndOfStatement();
8147 Error(L, "unexpected input in .unreq directive.");
8150 RegisterReqs.erase(Parser.getTok().getIdentifier());
8151 Parser.Lex(); // Eat the identifier.
8155 /// parseDirectiveArch
8157 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
8158 StringRef Arch = getParser().parseStringToEndOfStatement().trim();
8160 unsigned ID = StringSwitch<unsigned>(Arch)
8161 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
8162 .Case(NAME, ARM::ID)
8163 #define ARM_ARCH_ALIAS(NAME, ID) \
8164 .Case(NAME, ARM::ID)
8165 #include "MCTargetDesc/ARMArchName.def"
8166 .Default(ARM::INVALID_ARCH);
8168 if (ID == ARM::INVALID_ARCH) {
8169 Error(L, "Unknown arch name");
8173 getTargetStreamer().emitArch(ID);
8177 /// parseDirectiveEabiAttr
8178 /// ::= .eabi_attribute int, int
8179 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
8180 if (Parser.getTok().isNot(AsmToken::Integer)) {
8181 Error(L, "integer expected");
8184 int64_t Tag = Parser.getTok().getIntVal();
8185 Parser.Lex(); // eat tag integer
8187 if (Parser.getTok().isNot(AsmToken::Comma)) {
8188 Error(L, "comma expected");
8191 Parser.Lex(); // skip comma
8193 L = Parser.getTok().getLoc();
8194 if (Parser.getTok().isNot(AsmToken::Integer)) {
8195 Error(L, "integer expected");
8198 int64_t Value = Parser.getTok().getIntVal();
8199 Parser.Lex(); // eat value integer
8201 getTargetStreamer().emitAttribute(Tag, Value);
8205 /// parseDirectiveCPU
8207 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
8208 StringRef CPU = getParser().parseStringToEndOfStatement().trim();
8209 getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
8213 /// parseDirectiveFPU
8215 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
8216 StringRef FPU = getParser().parseStringToEndOfStatement().trim();
8218 unsigned ID = StringSwitch<unsigned>(FPU)
8219 #define ARM_FPU_NAME(NAME, ID) .Case(NAME, ARM::ID)
8220 #include "ARMFPUName.def"
8221 .Default(ARM::INVALID_FPU);
8223 if (ID == ARM::INVALID_FPU) {
8224 Error(L, "Unknown FPU name");
8228 getTargetStreamer().emitFPU(ID);
8232 /// parseDirectiveFnStart
8234 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
8235 if (FnStartLoc.isValid()) {
8236 Error(L, ".fnstart starts before the end of previous one");
8237 Error(FnStartLoc, "previous .fnstart starts here");
8242 getTargetStreamer().emitFnStart();
8246 /// parseDirectiveFnEnd
8248 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
8249 // Check the ordering of unwind directives
8250 if (!FnStartLoc.isValid()) {
8251 Error(L, ".fnstart must precede .fnend directive");
8255 // Reset the unwind directives parser state
8256 resetUnwindDirectiveParserState();
8257 getTargetStreamer().emitFnEnd();
8261 /// parseDirectiveCantUnwind
8263 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
8264 // Check the ordering of unwind directives
8266 if (!FnStartLoc.isValid()) {
8267 Error(L, ".fnstart must precede .cantunwind directive");
8270 if (HandlerDataLoc.isValid()) {
8271 Error(L, ".cantunwind can't be used with .handlerdata directive");
8272 Error(HandlerDataLoc, ".handlerdata was specified here");
8275 if (PersonalityLoc.isValid()) {
8276 Error(L, ".cantunwind can't be used with .personality directive");
8277 Error(PersonalityLoc, ".personality was specified here");
8281 getTargetStreamer().emitCantUnwind();
8285 /// parseDirectivePersonality
8286 /// ::= .personality name
8287 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
8288 // Check the ordering of unwind directives
8290 if (!FnStartLoc.isValid()) {
8291 Error(L, ".fnstart must precede .personality directive");
8294 if (CantUnwindLoc.isValid()) {
8295 Error(L, ".personality can't be used with .cantunwind directive");
8296 Error(CantUnwindLoc, ".cantunwind was specified here");
8299 if (HandlerDataLoc.isValid()) {
8300 Error(L, ".personality must precede .handlerdata directive");
8301 Error(HandlerDataLoc, ".handlerdata was specified here");
8305 // Parse the name of the personality routine
8306 if (Parser.getTok().isNot(AsmToken::Identifier)) {
8307 Parser.eatToEndOfStatement();
8308 Error(L, "unexpected input in .personality directive.");
8311 StringRef Name(Parser.getTok().getIdentifier());
8314 MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
8315 getTargetStreamer().emitPersonality(PR);
8319 /// parseDirectiveHandlerData
8320 /// ::= .handlerdata
8321 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
8322 // Check the ordering of unwind directives
8324 if (!FnStartLoc.isValid()) {
8325 Error(L, ".fnstart must precede .personality directive");
8328 if (CantUnwindLoc.isValid()) {
8329 Error(L, ".handlerdata can't be used with .cantunwind directive");
8330 Error(CantUnwindLoc, ".cantunwind was specified here");
8334 getTargetStreamer().emitHandlerData();
8338 /// parseDirectiveSetFP
8339 /// ::= .setfp fpreg, spreg [, offset]
8340 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
8341 // Check the ordering of unwind directives
8342 if (!FnStartLoc.isValid()) {
8343 Error(L, ".fnstart must precede .setfp directive");
8346 if (HandlerDataLoc.isValid()) {
8347 Error(L, ".setfp must precede .handlerdata directive");
8352 SMLoc NewFPRegLoc = Parser.getTok().getLoc();
8353 int NewFPReg = tryParseRegister();
8354 if (NewFPReg == -1) {
8355 Error(NewFPRegLoc, "frame pointer register expected");
8360 if (!Parser.getTok().is(AsmToken::Comma)) {
8361 Error(Parser.getTok().getLoc(), "comma expected");
8364 Parser.Lex(); // skip comma
8367 SMLoc NewSPRegLoc = Parser.getTok().getLoc();
8368 int NewSPReg = tryParseRegister();
8369 if (NewSPReg == -1) {
8370 Error(NewSPRegLoc, "stack pointer register expected");
8374 if (NewSPReg != ARM::SP && NewSPReg != FPReg) {
8376 "register should be either $sp or the latest fp register");
8380 // Update the frame pointer register
8385 if (Parser.getTok().is(AsmToken::Comma)) {
8386 Parser.Lex(); // skip comma
8388 if (Parser.getTok().isNot(AsmToken::Hash) &&
8389 Parser.getTok().isNot(AsmToken::Dollar)) {
8390 Error(Parser.getTok().getLoc(), "'#' expected");
8393 Parser.Lex(); // skip hash token.
8395 const MCExpr *OffsetExpr;
8396 SMLoc ExLoc = Parser.getTok().getLoc();
8398 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
8399 Error(ExLoc, "malformed setfp offset");
8402 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8404 Error(ExLoc, "setfp offset must be an immediate");
8408 Offset = CE->getValue();
8411 getTargetStreamer().emitSetFP(static_cast<unsigned>(NewFPReg),
8412 static_cast<unsigned>(NewSPReg), Offset);
8418 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
8419 // Check the ordering of unwind directives
8420 if (!FnStartLoc.isValid()) {
8421 Error(L, ".fnstart must precede .pad directive");
8424 if (HandlerDataLoc.isValid()) {
8425 Error(L, ".pad must precede .handlerdata directive");
8430 if (Parser.getTok().isNot(AsmToken::Hash) &&
8431 Parser.getTok().isNot(AsmToken::Dollar)) {
8432 Error(Parser.getTok().getLoc(), "'#' expected");
8435 Parser.Lex(); // skip hash token.
8437 const MCExpr *OffsetExpr;
8438 SMLoc ExLoc = Parser.getTok().getLoc();
8440 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
8441 Error(ExLoc, "malformed pad offset");
8444 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8446 Error(ExLoc, "pad offset must be an immediate");
8450 getTargetStreamer().emitPad(CE->getValue());
8454 /// parseDirectiveRegSave
8455 /// ::= .save { registers }
8456 /// ::= .vsave { registers }
8457 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
8458 // Check the ordering of unwind directives
8459 if (!FnStartLoc.isValid()) {
8460 Error(L, ".fnstart must precede .save or .vsave directives");
8463 if (HandlerDataLoc.isValid()) {
8464 Error(L, ".save or .vsave must precede .handlerdata directive");
8468 // RAII object to make sure parsed operands are deleted.
8469 struct CleanupObject {
8470 SmallVector<MCParsedAsmOperand *, 1> Operands;
8472 for (unsigned I = 0, E = Operands.size(); I != E; ++I)
8477 // Parse the register list
8478 if (parseRegisterList(CO.Operands))
8480 ARMOperand *Op = (ARMOperand*)CO.Operands[0];
8481 if (!IsVector && !Op->isRegList()) {
8482 Error(L, ".save expects GPR registers");
8485 if (IsVector && !Op->isDPRRegList()) {
8486 Error(L, ".vsave expects DPR registers");
8490 getTargetStreamer().emitRegSave(Op->getRegList(), IsVector);
8494 /// parseDirectiveInst
8495 /// ::= .inst opcode [, ...]
8496 /// ::= .inst.n opcode [, ...]
8497 /// ::= .inst.w opcode [, ...]
8498 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
8510 Parser.eatToEndOfStatement();
8511 Error(Loc, "cannot determine Thumb instruction size, "
8512 "use inst.n/inst.w instead");
8517 Parser.eatToEndOfStatement();
8518 Error(Loc, "width suffixes are invalid in ARM mode");
8524 if (getLexer().is(AsmToken::EndOfStatement)) {
8525 Parser.eatToEndOfStatement();
8526 Error(Loc, "expected expression following directive");
8533 if (getParser().parseExpression(Expr)) {
8534 Error(Loc, "expected expression");
8538 const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
8540 Error(Loc, "expected constant expression");
8546 if (Value->getValue() > 0xffff) {
8547 Error(Loc, "inst.n operand is too big, use inst.w instead");
8552 if (Value->getValue() > 0xffffffff) {
8554 StringRef(Suffix ? "inst.w" : "inst") + " operand is too big");
8559 llvm_unreachable("only supported widths are 2 and 4");
8562 getTargetStreamer().emitInst(Value->getValue(), Suffix);
8564 if (getLexer().is(AsmToken::EndOfStatement))
8567 if (getLexer().isNot(AsmToken::Comma)) {
8568 Error(Loc, "unexpected token in directive");
8579 /// parseDirectiveLtorg
8580 /// ::= .ltorg | .pool
8581 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
8582 MCStreamer &Streamer = getParser().getStreamer();
8583 const MCSection *Section = Streamer.getCurrentSection().first;
8585 if (ConstantPool *CP = getConstantPool(Section)) {
8587 CP->emitEntries(Streamer);
8592 bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
8593 const MCSection *Section = getStreamer().getCurrentSection().first;
8595 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8596 TokError("unexpected token in directive");
8601 getStreamer().InitToTextSection();
8602 Section = getStreamer().getCurrentSection().first;
8605 if (Section->UseCodeAlign())
8606 getStreamer().EmitCodeAlignment(2, 0);
8608 getStreamer().EmitValueToAlignment(2, 0, 1, 0);
8613 /// Force static initialization.
8614 extern "C" void LLVMInitializeARMAsmParser() {
8615 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
8616 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
8619 #define GET_REGISTER_MATCHER
8620 #define GET_SUBTARGET_FEATURE_NAME
8621 #define GET_MATCHER_IMPLEMENTATION
8622 #include "ARMGenAsmMatcher.inc"
8624 // Define this matcher function after the auto-generated include so we
8625 // have the match class enum definitions.
8626 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
8628 ARMOperand *Op = static_cast<ARMOperand*>(AsmOp);
8629 // If the kind is a token for a literal immediate, check if our asm
8630 // operand matches. This is for InstAliases which have a fixed-value
8631 // immediate in the syntax.
8632 if (Kind == MCK__35_0 && Op->isImm()) {
8633 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
8635 return Match_InvalidOperand;
8636 if (CE->getValue() == 0)
8637 return Match_Success;
8639 return Match_InvalidOperand;
8642 void ARMAsmParser::finishParse() {
8643 // Dump contents of assembler constant pools.
8644 MCStreamer &Streamer = getParser().getStreamer();
8645 for (ConstantPoolMapTy::iterator CPI = ConstantPools.begin(),
8646 CPE = ConstantPools.end();
8647 CPI != CPE; ++CPI) {
8648 const MCSection *Section = CPI->first;
8649 ConstantPool &CP = CPI->second;
8651 // Dump non-empty assembler constant pools at the end of the section.
8653 Streamer.SwitchSection(Section);
8654 CP.emitEntries(Streamer);