1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMBaseInfo.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMMCExpr.h"
13 #include "llvm/MC/MCParser/MCAsmLexer.h"
14 #include "llvm/MC/MCParser/MCAsmParser.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCAsmInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCTargetAsmParser.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/SourceMgr.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/ADT/BitVector.h"
30 #include "llvm/ADT/OwningPtr.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/StringSwitch.h"
34 #include "llvm/ADT/Twine.h"
42 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
44 class ARMAsmParser : public MCTargetAsmParser {
47 const MCRegisterInfo *MRI;
49 // Map of register aliases registers via the .req directive.
50 StringMap<unsigned> RegisterReqs;
53 ARMCC::CondCodes Cond; // Condition for IT block.
54 unsigned Mask:4; // Condition mask for instructions.
55 // Starting at first 1 (from lsb).
56 // '1' condition as indicated in IT.
57 // '0' inverse of condition (else).
58 // Count of instructions in IT block is
59 // 4 - trailingzeroes(mask)
61 bool FirstCond; // Explicit flag for when we're parsing the
62 // First instruction in the IT block. It's
63 // implied in the mask, so needs special
66 unsigned CurPosition; // Current position in parsing of IT
67 // block. In range [0,3]. Initialized
68 // according to count of instructions in block.
69 // ~0U if no active IT block.
71 bool inITBlock() { return ITState.CurPosition != ~0U;}
72 void forwardITPosition() {
73 if (!inITBlock()) return;
74 // Move to the next instruction in the IT block, if there is one. If not,
75 // mark the block as done.
76 unsigned TZ = CountTrailingZeros_32(ITState.Mask);
77 if (++ITState.CurPosition == 5 - TZ)
78 ITState.CurPosition = ~0U; // Done with the IT block after this.
82 MCAsmParser &getParser() const { return Parser; }
83 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
85 bool Warning(SMLoc L, const Twine &Msg,
86 ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) {
87 return Parser.Warning(L, Msg, Ranges);
89 bool Error(SMLoc L, const Twine &Msg,
90 ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) {
91 return Parser.Error(L, Msg, Ranges);
94 int tryParseRegister();
95 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
96 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
97 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
98 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
99 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
100 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
101 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
102 unsigned &ShiftAmount);
103 bool parseDirectiveWord(unsigned Size, SMLoc L);
104 bool parseDirectiveThumb(SMLoc L);
105 bool parseDirectiveARM(SMLoc L);
106 bool parseDirectiveThumbFunc(SMLoc L);
107 bool parseDirectiveCode(SMLoc L);
108 bool parseDirectiveSyntax(SMLoc L);
109 bool parseDirectiveReq(StringRef Name, SMLoc L);
110 bool parseDirectiveUnreq(SMLoc L);
111 bool parseDirectiveArch(SMLoc L);
112 bool parseDirectiveEabiAttr(SMLoc L);
114 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
115 bool &CarrySetting, unsigned &ProcessorIMod,
117 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
118 bool &CanAcceptPredicationCode);
120 bool isThumb() const {
121 // FIXME: Can tablegen auto-generate this?
122 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
124 bool isThumbOne() const {
125 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
127 bool isThumbTwo() const {
128 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
130 bool hasV6Ops() const {
131 return STI.getFeatureBits() & ARM::HasV6Ops;
133 bool hasV7Ops() const {
134 return STI.getFeatureBits() & ARM::HasV7Ops;
137 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
138 setAvailableFeatures(FB);
140 bool isMClass() const {
141 return STI.getFeatureBits() & ARM::FeatureMClass;
144 /// @name Auto-generated Match Functions
147 #define GET_ASSEMBLER_HEADER
148 #include "ARMGenAsmMatcher.inc"
152 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
153 OperandMatchResultTy parseCoprocNumOperand(
154 SmallVectorImpl<MCParsedAsmOperand*>&);
155 OperandMatchResultTy parseCoprocRegOperand(
156 SmallVectorImpl<MCParsedAsmOperand*>&);
157 OperandMatchResultTy parseCoprocOptionOperand(
158 SmallVectorImpl<MCParsedAsmOperand*>&);
159 OperandMatchResultTy parseMemBarrierOptOperand(
160 SmallVectorImpl<MCParsedAsmOperand*>&);
161 OperandMatchResultTy parseProcIFlagsOperand(
162 SmallVectorImpl<MCParsedAsmOperand*>&);
163 OperandMatchResultTy parseMSRMaskOperand(
164 SmallVectorImpl<MCParsedAsmOperand*>&);
165 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
166 StringRef Op, int Low, int High);
167 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
168 return parsePKHImm(O, "lsl", 0, 31);
170 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
171 return parsePKHImm(O, "asr", 1, 32);
173 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
174 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
175 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
176 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
177 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
178 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
179 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
180 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
181 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index);
183 // Asm Match Converter Methods
184 bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
185 const SmallVectorImpl<MCParsedAsmOperand*> &);
186 bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
187 const SmallVectorImpl<MCParsedAsmOperand*> &);
188 bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
189 const SmallVectorImpl<MCParsedAsmOperand*> &);
190 bool cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
191 const SmallVectorImpl<MCParsedAsmOperand*> &);
192 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
193 const SmallVectorImpl<MCParsedAsmOperand*> &);
194 bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
195 const SmallVectorImpl<MCParsedAsmOperand*> &);
196 bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
197 const SmallVectorImpl<MCParsedAsmOperand*> &);
198 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
199 const SmallVectorImpl<MCParsedAsmOperand*> &);
200 bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
201 const SmallVectorImpl<MCParsedAsmOperand*> &);
202 bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
203 const SmallVectorImpl<MCParsedAsmOperand*> &);
204 bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
205 const SmallVectorImpl<MCParsedAsmOperand*> &);
206 bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
207 const SmallVectorImpl<MCParsedAsmOperand*> &);
208 bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
209 const SmallVectorImpl<MCParsedAsmOperand*> &);
210 bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
211 const SmallVectorImpl<MCParsedAsmOperand*> &);
212 bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
213 const SmallVectorImpl<MCParsedAsmOperand*> &);
214 bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
215 const SmallVectorImpl<MCParsedAsmOperand*> &);
216 bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
217 const SmallVectorImpl<MCParsedAsmOperand*> &);
218 bool cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
219 const SmallVectorImpl<MCParsedAsmOperand*> &);
220 bool cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
221 const SmallVectorImpl<MCParsedAsmOperand*> &);
222 bool cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
223 const SmallVectorImpl<MCParsedAsmOperand*> &);
224 bool cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
225 const SmallVectorImpl<MCParsedAsmOperand*> &);
227 bool validateInstruction(MCInst &Inst,
228 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
229 bool processInstruction(MCInst &Inst,
230 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
231 bool shouldOmitCCOutOperand(StringRef Mnemonic,
232 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
235 enum ARMMatchResultTy {
236 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
237 Match_RequiresNotITBlock,
239 Match_RequiresThumb2,
240 #define GET_OPERAND_DIAGNOSTIC_TYPES
241 #include "ARMGenAsmMatcher.inc"
245 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
246 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
247 MCAsmParserExtension::Initialize(_Parser);
249 // Cache the MCRegisterInfo.
250 MRI = &getContext().getRegisterInfo();
252 // Initialize the set of available features.
253 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
255 // Not in an ITBlock to start with.
256 ITState.CurPosition = ~0U;
259 // Implementation of the MCTargetAsmParser interface:
260 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
261 bool ParseInstruction(StringRef Name, SMLoc NameLoc,
262 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
263 bool ParseDirective(AsmToken DirectiveID);
265 unsigned checkTargetMatchPredicate(MCInst &Inst);
267 bool MatchAndEmitInstruction(SMLoc IDLoc,
268 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
271 } // end anonymous namespace
275 /// ARMOperand - Instances of this class represent a parsed ARM machine
277 class ARMOperand : public MCParsedAsmOperand {
297 k_VectorListAllLanes,
303 k_BitfieldDescriptor,
307 SMLoc StartLoc, EndLoc;
308 SmallVector<unsigned, 8> Registers;
312 ARMCC::CondCodes Val;
332 ARM_PROC::IFlags Val;
348 // A vector register list is a sequential list of 1 to 4 registers.
364 /// Combined record for all forms of ARM address expressions.
367 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
369 const MCConstantExpr *OffsetImm; // Offset immediate value
370 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
371 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
372 unsigned ShiftImm; // shift for OffsetReg.
373 unsigned Alignment; // 0 = no alignment specified
374 // n = alignment in bytes (2, 4, 8, 16, or 32)
375 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
381 ARM_AM::ShiftOpc ShiftTy;
390 ARM_AM::ShiftOpc ShiftTy;
396 ARM_AM::ShiftOpc ShiftTy;
409 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
411 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
413 StartLoc = o.StartLoc;
430 case k_DPRRegisterList:
431 case k_SPRRegisterList:
432 Registers = o.Registers;
435 case k_VectorListAllLanes:
436 case k_VectorListIndexed:
437 VectorList = o.VectorList;
444 CoprocOption = o.CoprocOption;
449 case k_MemBarrierOpt:
455 case k_PostIndexRegister:
456 PostIdxReg = o.PostIdxReg;
464 case k_ShifterImmediate:
465 ShifterImm = o.ShifterImm;
467 case k_ShiftedRegister:
468 RegShiftedReg = o.RegShiftedReg;
470 case k_ShiftedImmediate:
471 RegShiftedImm = o.RegShiftedImm;
473 case k_RotateImmediate:
476 case k_BitfieldDescriptor:
477 Bitfield = o.Bitfield;
480 VectorIndex = o.VectorIndex;
485 /// getStartLoc - Get the location of the first token of this operand.
486 SMLoc getStartLoc() const { return StartLoc; }
487 /// getEndLoc - Get the location of the last token of this operand.
488 SMLoc getEndLoc() const { return EndLoc; }
490 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
492 ARMCC::CondCodes getCondCode() const {
493 assert(Kind == k_CondCode && "Invalid access!");
497 unsigned getCoproc() const {
498 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
502 StringRef getToken() const {
503 assert(Kind == k_Token && "Invalid access!");
504 return StringRef(Tok.Data, Tok.Length);
507 unsigned getReg() const {
508 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
512 const SmallVectorImpl<unsigned> &getRegList() const {
513 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
514 Kind == k_SPRRegisterList) && "Invalid access!");
518 const MCExpr *getImm() const {
519 assert(isImm() && "Invalid access!");
523 unsigned getVectorIndex() const {
524 assert(Kind == k_VectorIndex && "Invalid access!");
525 return VectorIndex.Val;
528 ARM_MB::MemBOpt getMemBarrierOpt() const {
529 assert(Kind == k_MemBarrierOpt && "Invalid access!");
533 ARM_PROC::IFlags getProcIFlags() const {
534 assert(Kind == k_ProcIFlags && "Invalid access!");
538 unsigned getMSRMask() const {
539 assert(Kind == k_MSRMask && "Invalid access!");
543 bool isCoprocNum() const { return Kind == k_CoprocNum; }
544 bool isCoprocReg() const { return Kind == k_CoprocReg; }
545 bool isCoprocOption() const { return Kind == k_CoprocOption; }
546 bool isCondCode() const { return Kind == k_CondCode; }
547 bool isCCOut() const { return Kind == k_CCOut; }
548 bool isITMask() const { return Kind == k_ITCondMask; }
549 bool isITCondCode() const { return Kind == k_CondCode; }
550 bool isImm() const { return Kind == k_Immediate; }
551 bool isFPImm() const {
552 if (!isImm()) return false;
553 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
554 if (!CE) return false;
555 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
558 bool isFBits16() const {
559 if (!isImm()) return false;
560 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
561 if (!CE) return false;
562 int64_t Value = CE->getValue();
563 return Value >= 0 && Value <= 16;
565 bool isFBits32() const {
566 if (!isImm()) return false;
567 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
568 if (!CE) return false;
569 int64_t Value = CE->getValue();
570 return Value >= 1 && Value <= 32;
572 bool isImm8s4() const {
573 if (!isImm()) return false;
574 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
575 if (!CE) return false;
576 int64_t Value = CE->getValue();
577 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
579 bool isImm0_1020s4() const {
580 if (!isImm()) return false;
581 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
582 if (!CE) return false;
583 int64_t Value = CE->getValue();
584 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
586 bool isImm0_508s4() const {
587 if (!isImm()) return false;
588 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
589 if (!CE) return false;
590 int64_t Value = CE->getValue();
591 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
593 bool isImm0_508s4Neg() const {
594 if (!isImm()) return false;
595 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
596 if (!CE) return false;
597 int64_t Value = -CE->getValue();
598 // explicitly exclude zero. we want that to use the normal 0_508 version.
599 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
601 bool isImm0_255() const {
602 if (!isImm()) return false;
603 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
604 if (!CE) return false;
605 int64_t Value = CE->getValue();
606 return Value >= 0 && Value < 256;
608 bool isImm0_4095() const {
609 if (!isImm()) return false;
610 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
611 if (!CE) return false;
612 int64_t Value = CE->getValue();
613 return Value >= 0 && Value < 4096;
615 bool isImm0_4095Neg() const {
616 if (!isImm()) return false;
617 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
618 if (!CE) return false;
619 int64_t Value = -CE->getValue();
620 return Value > 0 && Value < 4096;
622 bool isImm0_1() const {
623 if (!isImm()) return false;
624 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
625 if (!CE) return false;
626 int64_t Value = CE->getValue();
627 return Value >= 0 && Value < 2;
629 bool isImm0_3() const {
630 if (!isImm()) return false;
631 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
632 if (!CE) return false;
633 int64_t Value = CE->getValue();
634 return Value >= 0 && Value < 4;
636 bool isImm0_7() const {
637 if (!isImm()) return false;
638 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
639 if (!CE) return false;
640 int64_t Value = CE->getValue();
641 return Value >= 0 && Value < 8;
643 bool isImm0_15() const {
644 if (!isImm()) return false;
645 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
646 if (!CE) return false;
647 int64_t Value = CE->getValue();
648 return Value >= 0 && Value < 16;
650 bool isImm0_31() const {
651 if (!isImm()) return false;
652 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
653 if (!CE) return false;
654 int64_t Value = CE->getValue();
655 return Value >= 0 && Value < 32;
657 bool isImm0_63() const {
658 if (!isImm()) return false;
659 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
660 if (!CE) return false;
661 int64_t Value = CE->getValue();
662 return Value >= 0 && Value < 64;
664 bool isImm8() const {
665 if (!isImm()) return false;
666 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
667 if (!CE) return false;
668 int64_t Value = CE->getValue();
671 bool isImm16() const {
672 if (!isImm()) return false;
673 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
674 if (!CE) return false;
675 int64_t Value = CE->getValue();
678 bool isImm32() const {
679 if (!isImm()) return false;
680 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
681 if (!CE) return false;
682 int64_t Value = CE->getValue();
685 bool isShrImm8() const {
686 if (!isImm()) return false;
687 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
688 if (!CE) return false;
689 int64_t Value = CE->getValue();
690 return Value > 0 && Value <= 8;
692 bool isShrImm16() const {
693 if (!isImm()) return false;
694 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
695 if (!CE) return false;
696 int64_t Value = CE->getValue();
697 return Value > 0 && Value <= 16;
699 bool isShrImm32() const {
700 if (!isImm()) return false;
701 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
702 if (!CE) return false;
703 int64_t Value = CE->getValue();
704 return Value > 0 && Value <= 32;
706 bool isShrImm64() const {
707 if (!isImm()) return false;
708 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
709 if (!CE) return false;
710 int64_t Value = CE->getValue();
711 return Value > 0 && Value <= 64;
713 bool isImm1_7() const {
714 if (!isImm()) return false;
715 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
716 if (!CE) return false;
717 int64_t Value = CE->getValue();
718 return Value > 0 && Value < 8;
720 bool isImm1_15() const {
721 if (!isImm()) return false;
722 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
723 if (!CE) return false;
724 int64_t Value = CE->getValue();
725 return Value > 0 && Value < 16;
727 bool isImm1_31() const {
728 if (!isImm()) return false;
729 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
730 if (!CE) return false;
731 int64_t Value = CE->getValue();
732 return Value > 0 && Value < 32;
734 bool isImm1_16() const {
735 if (!isImm()) return false;
736 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
737 if (!CE) return false;
738 int64_t Value = CE->getValue();
739 return Value > 0 && Value < 17;
741 bool isImm1_32() const {
742 if (!isImm()) return false;
743 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
744 if (!CE) return false;
745 int64_t Value = CE->getValue();
746 return Value > 0 && Value < 33;
748 bool isImm0_32() const {
749 if (!isImm()) return false;
750 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
751 if (!CE) return false;
752 int64_t Value = CE->getValue();
753 return Value >= 0 && Value < 33;
755 bool isImm0_65535() const {
756 if (!isImm()) return false;
757 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
758 if (!CE) return false;
759 int64_t Value = CE->getValue();
760 return Value >= 0 && Value < 65536;
762 bool isImm0_65535Expr() const {
763 if (!isImm()) return false;
764 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
765 // If it's not a constant expression, it'll generate a fixup and be
767 if (!CE) return true;
768 int64_t Value = CE->getValue();
769 return Value >= 0 && Value < 65536;
771 bool isImm24bit() const {
772 if (!isImm()) return false;
773 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
774 if (!CE) return false;
775 int64_t Value = CE->getValue();
776 return Value >= 0 && Value <= 0xffffff;
778 bool isImmThumbSR() const {
779 if (!isImm()) return false;
780 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
781 if (!CE) return false;
782 int64_t Value = CE->getValue();
783 return Value > 0 && Value < 33;
785 bool isPKHLSLImm() const {
786 if (!isImm()) return false;
787 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
788 if (!CE) return false;
789 int64_t Value = CE->getValue();
790 return Value >= 0 && Value < 32;
792 bool isPKHASRImm() const {
793 if (!isImm()) return false;
794 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
795 if (!CE) return false;
796 int64_t Value = CE->getValue();
797 return Value > 0 && Value <= 32;
799 bool isAdrLabel() const {
800 // If we have an immediate that's not a constant, treat it as a label
801 // reference needing a fixup. If it is a constant, but it can't fit
802 // into shift immediate encoding, we reject it.
803 if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
804 else return (isARMSOImm() || isARMSOImmNeg());
806 bool isARMSOImm() const {
807 if (!isImm()) return false;
808 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
809 if (!CE) return false;
810 int64_t Value = CE->getValue();
811 return ARM_AM::getSOImmVal(Value) != -1;
813 bool isARMSOImmNot() const {
814 if (!isImm()) return false;
815 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
816 if (!CE) return false;
817 int64_t Value = CE->getValue();
818 return ARM_AM::getSOImmVal(~Value) != -1;
820 bool isARMSOImmNeg() const {
821 if (!isImm()) return false;
822 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
823 if (!CE) return false;
824 int64_t Value = CE->getValue();
825 // Only use this when not representable as a plain so_imm.
826 return ARM_AM::getSOImmVal(Value) == -1 &&
827 ARM_AM::getSOImmVal(-Value) != -1;
829 bool isT2SOImm() const {
830 if (!isImm()) return false;
831 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
832 if (!CE) return false;
833 int64_t Value = CE->getValue();
834 return ARM_AM::getT2SOImmVal(Value) != -1;
836 bool isT2SOImmNot() const {
837 if (!isImm()) return false;
838 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
839 if (!CE) return false;
840 int64_t Value = CE->getValue();
841 return ARM_AM::getT2SOImmVal(~Value) != -1;
843 bool isT2SOImmNeg() const {
844 if (!isImm()) return false;
845 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
846 if (!CE) return false;
847 int64_t Value = CE->getValue();
848 // Only use this when not representable as a plain so_imm.
849 return ARM_AM::getT2SOImmVal(Value) == -1 &&
850 ARM_AM::getT2SOImmVal(-Value) != -1;
852 bool isSetEndImm() const {
853 if (!isImm()) return false;
854 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
855 if (!CE) return false;
856 int64_t Value = CE->getValue();
857 return Value == 1 || Value == 0;
859 bool isReg() const { return Kind == k_Register; }
860 bool isRegList() const { return Kind == k_RegisterList; }
861 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
862 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
863 bool isToken() const { return Kind == k_Token; }
864 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
865 bool isMemory() const { return Kind == k_Memory; }
866 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
867 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
868 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
869 bool isRotImm() const { return Kind == k_RotateImmediate; }
870 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
871 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
872 bool isPostIdxReg() const {
873 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
875 bool isMemNoOffset(bool alignOK = false) const {
878 // No offset of any kind.
879 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
880 (alignOK || Memory.Alignment == 0);
882 bool isMemPCRelImm12() const {
883 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
885 // Base register must be PC.
886 if (Memory.BaseRegNum != ARM::PC)
888 // Immediate offset in range [-4095, 4095].
889 if (!Memory.OffsetImm) return true;
890 int64_t Val = Memory.OffsetImm->getValue();
891 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
893 bool isAlignedMemory() const {
894 return isMemNoOffset(true);
896 bool isAddrMode2() const {
897 if (!isMemory() || Memory.Alignment != 0) return false;
898 // Check for register offset.
899 if (Memory.OffsetRegNum) return true;
900 // Immediate offset in range [-4095, 4095].
901 if (!Memory.OffsetImm) return true;
902 int64_t Val = Memory.OffsetImm->getValue();
903 return Val > -4096 && Val < 4096;
905 bool isAM2OffsetImm() const {
906 if (!isImm()) return false;
907 // Immediate offset in range [-4095, 4095].
908 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
909 if (!CE) return false;
910 int64_t Val = CE->getValue();
911 return Val > -4096 && Val < 4096;
913 bool isAddrMode3() const {
914 // If we have an immediate that's not a constant, treat it as a label
915 // reference needing a fixup. If it is a constant, it's something else
917 if (isImm() && !isa<MCConstantExpr>(getImm()))
919 if (!isMemory() || Memory.Alignment != 0) return false;
920 // No shifts are legal for AM3.
921 if (Memory.ShiftType != ARM_AM::no_shift) return false;
922 // Check for register offset.
923 if (Memory.OffsetRegNum) return true;
924 // Immediate offset in range [-255, 255].
925 if (!Memory.OffsetImm) return true;
926 int64_t Val = Memory.OffsetImm->getValue();
927 // The #-0 offset is encoded as INT32_MIN, and we have to check
929 return (Val > -256 && Val < 256) || Val == INT32_MIN;
931 bool isAM3Offset() const {
932 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
934 if (Kind == k_PostIndexRegister)
935 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
936 // Immediate offset in range [-255, 255].
937 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
938 if (!CE) return false;
939 int64_t Val = CE->getValue();
940 // Special case, #-0 is INT32_MIN.
941 return (Val > -256 && Val < 256) || Val == INT32_MIN;
943 bool isAddrMode5() const {
944 // If we have an immediate that's not a constant, treat it as a label
945 // reference needing a fixup. If it is a constant, it's something else
947 if (isImm() && !isa<MCConstantExpr>(getImm()))
949 if (!isMemory() || Memory.Alignment != 0) return false;
950 // Check for register offset.
951 if (Memory.OffsetRegNum) return false;
952 // Immediate offset in range [-1020, 1020] and a multiple of 4.
953 if (!Memory.OffsetImm) return true;
954 int64_t Val = Memory.OffsetImm->getValue();
955 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
958 bool isMemTBB() const {
959 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
960 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
964 bool isMemTBH() const {
965 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
966 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
967 Memory.Alignment != 0 )
971 bool isMemRegOffset() const {
972 if (!isMemory() || !Memory.OffsetRegNum || Memory.Alignment != 0)
976 bool isT2MemRegOffset() const {
977 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
978 Memory.Alignment != 0)
980 // Only lsl #{0, 1, 2, 3} allowed.
981 if (Memory.ShiftType == ARM_AM::no_shift)
983 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
987 bool isMemThumbRR() const {
988 // Thumb reg+reg addressing is simple. Just two registers, a base and
989 // an offset. No shifts, negations or any other complicating factors.
990 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
991 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
993 return isARMLowRegister(Memory.BaseRegNum) &&
994 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
996 bool isMemThumbRIs4() const {
997 if (!isMemory() || Memory.OffsetRegNum != 0 ||
998 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1000 // Immediate offset, multiple of 4 in range [0, 124].
1001 if (!Memory.OffsetImm) return true;
1002 int64_t Val = Memory.OffsetImm->getValue();
1003 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1005 bool isMemThumbRIs2() const {
1006 if (!isMemory() || Memory.OffsetRegNum != 0 ||
1007 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1009 // Immediate offset, multiple of 4 in range [0, 62].
1010 if (!Memory.OffsetImm) return true;
1011 int64_t Val = Memory.OffsetImm->getValue();
1012 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1014 bool isMemThumbRIs1() const {
1015 if (!isMemory() || Memory.OffsetRegNum != 0 ||
1016 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1018 // Immediate offset in range [0, 31].
1019 if (!Memory.OffsetImm) return true;
1020 int64_t Val = Memory.OffsetImm->getValue();
1021 return Val >= 0 && Val <= 31;
1023 bool isMemThumbSPI() const {
1024 if (!isMemory() || Memory.OffsetRegNum != 0 ||
1025 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1027 // Immediate offset, multiple of 4 in range [0, 1020].
1028 if (!Memory.OffsetImm) return true;
1029 int64_t Val = Memory.OffsetImm->getValue();
1030 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1032 bool isMemImm8s4Offset() const {
1033 // If we have an immediate that's not a constant, treat it as a label
1034 // reference needing a fixup. If it is a constant, it's something else
1035 // and we reject it.
1036 if (isImm() && !isa<MCConstantExpr>(getImm()))
1038 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1040 // Immediate offset a multiple of 4 in range [-1020, 1020].
1041 if (!Memory.OffsetImm) return true;
1042 int64_t Val = Memory.OffsetImm->getValue();
1043 // Special case, #-0 is INT32_MIN.
1044 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1046 bool isMemImm0_1020s4Offset() const {
1047 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1049 // Immediate offset a multiple of 4 in range [0, 1020].
1050 if (!Memory.OffsetImm) return true;
1051 int64_t Val = Memory.OffsetImm->getValue();
1052 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1054 bool isMemImm8Offset() const {
1055 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1057 // Base reg of PC isn't allowed for these encodings.
1058 if (Memory.BaseRegNum == ARM::PC) return false;
1059 // Immediate offset in range [-255, 255].
1060 if (!Memory.OffsetImm) return true;
1061 int64_t Val = Memory.OffsetImm->getValue();
1062 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1064 bool isMemPosImm8Offset() const {
1065 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1067 // Immediate offset in range [0, 255].
1068 if (!Memory.OffsetImm) return true;
1069 int64_t Val = Memory.OffsetImm->getValue();
1070 return Val >= 0 && Val < 256;
1072 bool isMemNegImm8Offset() const {
1073 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1075 // Base reg of PC isn't allowed for these encodings.
1076 if (Memory.BaseRegNum == ARM::PC) return false;
1077 // Immediate offset in range [-255, -1].
1078 if (!Memory.OffsetImm) return false;
1079 int64_t Val = Memory.OffsetImm->getValue();
1080 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1082 bool isMemUImm12Offset() const {
1083 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1085 // Immediate offset in range [0, 4095].
1086 if (!Memory.OffsetImm) return true;
1087 int64_t Val = Memory.OffsetImm->getValue();
1088 return (Val >= 0 && Val < 4096);
1090 bool isMemImm12Offset() const {
1091 // If we have an immediate that's not a constant, treat it as a label
1092 // reference needing a fixup. If it is a constant, it's something else
1093 // and we reject it.
1094 if (isImm() && !isa<MCConstantExpr>(getImm()))
1097 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1099 // Immediate offset in range [-4095, 4095].
1100 if (!Memory.OffsetImm) return true;
1101 int64_t Val = Memory.OffsetImm->getValue();
1102 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1104 bool isPostIdxImm8() const {
1105 if (!isImm()) return false;
1106 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1107 if (!CE) return false;
1108 int64_t Val = CE->getValue();
1109 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1111 bool isPostIdxImm8s4() const {
1112 if (!isImm()) return false;
1113 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1114 if (!CE) return false;
1115 int64_t Val = CE->getValue();
1116 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1120 bool isMSRMask() const { return Kind == k_MSRMask; }
1121 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1124 bool isSingleSpacedVectorList() const {
1125 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1127 bool isDoubleSpacedVectorList() const {
1128 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1130 bool isVecListOneD() const {
1131 if (!isSingleSpacedVectorList()) return false;
1132 return VectorList.Count == 1;
1135 bool isVecListDPair() const {
1136 if (!isSingleSpacedVectorList()) return false;
1137 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1138 .contains(VectorList.RegNum));
1141 bool isVecListThreeD() const {
1142 if (!isSingleSpacedVectorList()) return false;
1143 return VectorList.Count == 3;
1146 bool isVecListFourD() const {
1147 if (!isSingleSpacedVectorList()) return false;
1148 return VectorList.Count == 4;
1151 bool isVecListDPairSpaced() const {
1152 if (isSingleSpacedVectorList()) return false;
1153 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1154 .contains(VectorList.RegNum));
1157 bool isVecListThreeQ() const {
1158 if (!isDoubleSpacedVectorList()) return false;
1159 return VectorList.Count == 3;
1162 bool isVecListFourQ() const {
1163 if (!isDoubleSpacedVectorList()) return false;
1164 return VectorList.Count == 4;
1167 bool isSingleSpacedVectorAllLanes() const {
1168 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1170 bool isDoubleSpacedVectorAllLanes() const {
1171 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1173 bool isVecListOneDAllLanes() const {
1174 if (!isSingleSpacedVectorAllLanes()) return false;
1175 return VectorList.Count == 1;
1178 bool isVecListDPairAllLanes() const {
1179 if (!isSingleSpacedVectorAllLanes()) return false;
1180 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1181 .contains(VectorList.RegNum));
1184 bool isVecListDPairSpacedAllLanes() const {
1185 if (!isDoubleSpacedVectorAllLanes()) return false;
1186 return VectorList.Count == 2;
1189 bool isVecListThreeDAllLanes() const {
1190 if (!isSingleSpacedVectorAllLanes()) return false;
1191 return VectorList.Count == 3;
1194 bool isVecListThreeQAllLanes() const {
1195 if (!isDoubleSpacedVectorAllLanes()) return false;
1196 return VectorList.Count == 3;
1199 bool isVecListFourDAllLanes() const {
1200 if (!isSingleSpacedVectorAllLanes()) return false;
1201 return VectorList.Count == 4;
1204 bool isVecListFourQAllLanes() const {
1205 if (!isDoubleSpacedVectorAllLanes()) return false;
1206 return VectorList.Count == 4;
1209 bool isSingleSpacedVectorIndexed() const {
1210 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1212 bool isDoubleSpacedVectorIndexed() const {
1213 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1215 bool isVecListOneDByteIndexed() const {
1216 if (!isSingleSpacedVectorIndexed()) return false;
1217 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1220 bool isVecListOneDHWordIndexed() const {
1221 if (!isSingleSpacedVectorIndexed()) return false;
1222 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1225 bool isVecListOneDWordIndexed() const {
1226 if (!isSingleSpacedVectorIndexed()) return false;
1227 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1230 bool isVecListTwoDByteIndexed() const {
1231 if (!isSingleSpacedVectorIndexed()) return false;
1232 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1235 bool isVecListTwoDHWordIndexed() const {
1236 if (!isSingleSpacedVectorIndexed()) return false;
1237 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1240 bool isVecListTwoQWordIndexed() const {
1241 if (!isDoubleSpacedVectorIndexed()) return false;
1242 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1245 bool isVecListTwoQHWordIndexed() const {
1246 if (!isDoubleSpacedVectorIndexed()) return false;
1247 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1250 bool isVecListTwoDWordIndexed() const {
1251 if (!isSingleSpacedVectorIndexed()) return false;
1252 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1255 bool isVecListThreeDByteIndexed() const {
1256 if (!isSingleSpacedVectorIndexed()) return false;
1257 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1260 bool isVecListThreeDHWordIndexed() const {
1261 if (!isSingleSpacedVectorIndexed()) return false;
1262 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1265 bool isVecListThreeQWordIndexed() const {
1266 if (!isDoubleSpacedVectorIndexed()) return false;
1267 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1270 bool isVecListThreeQHWordIndexed() const {
1271 if (!isDoubleSpacedVectorIndexed()) return false;
1272 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1275 bool isVecListThreeDWordIndexed() const {
1276 if (!isSingleSpacedVectorIndexed()) return false;
1277 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1280 bool isVecListFourDByteIndexed() const {
1281 if (!isSingleSpacedVectorIndexed()) return false;
1282 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1285 bool isVecListFourDHWordIndexed() const {
1286 if (!isSingleSpacedVectorIndexed()) return false;
1287 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1290 bool isVecListFourQWordIndexed() const {
1291 if (!isDoubleSpacedVectorIndexed()) return false;
1292 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1295 bool isVecListFourQHWordIndexed() const {
1296 if (!isDoubleSpacedVectorIndexed()) return false;
1297 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1300 bool isVecListFourDWordIndexed() const {
1301 if (!isSingleSpacedVectorIndexed()) return false;
1302 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1305 bool isVectorIndex8() const {
1306 if (Kind != k_VectorIndex) return false;
1307 return VectorIndex.Val < 8;
1309 bool isVectorIndex16() const {
1310 if (Kind != k_VectorIndex) return false;
1311 return VectorIndex.Val < 4;
1313 bool isVectorIndex32() const {
1314 if (Kind != k_VectorIndex) return false;
1315 return VectorIndex.Val < 2;
1318 bool isNEONi8splat() const {
1319 if (!isImm()) return false;
1320 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1321 // Must be a constant.
1322 if (!CE) return false;
1323 int64_t Value = CE->getValue();
1324 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1326 return Value >= 0 && Value < 256;
1329 bool isNEONi16splat() const {
1330 if (!isImm()) return false;
1331 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1332 // Must be a constant.
1333 if (!CE) return false;
1334 int64_t Value = CE->getValue();
1335 // i16 value in the range [0,255] or [0x0100, 0xff00]
1336 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1339 bool isNEONi32splat() const {
1340 if (!isImm()) return false;
1341 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1342 // Must be a constant.
1343 if (!CE) return false;
1344 int64_t Value = CE->getValue();
1345 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1346 return (Value >= 0 && Value < 256) ||
1347 (Value >= 0x0100 && Value <= 0xff00) ||
1348 (Value >= 0x010000 && Value <= 0xff0000) ||
1349 (Value >= 0x01000000 && Value <= 0xff000000);
1352 bool isNEONi32vmov() const {
1353 if (!isImm()) return false;
1354 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1355 // Must be a constant.
1356 if (!CE) return false;
1357 int64_t Value = CE->getValue();
1358 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1359 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1360 return (Value >= 0 && Value < 256) ||
1361 (Value >= 0x0100 && Value <= 0xff00) ||
1362 (Value >= 0x010000 && Value <= 0xff0000) ||
1363 (Value >= 0x01000000 && Value <= 0xff000000) ||
1364 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1365 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1367 bool isNEONi32vmovNeg() const {
1368 if (!isImm()) return false;
1369 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1370 // Must be a constant.
1371 if (!CE) return false;
1372 int64_t Value = ~CE->getValue();
1373 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1374 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1375 return (Value >= 0 && Value < 256) ||
1376 (Value >= 0x0100 && Value <= 0xff00) ||
1377 (Value >= 0x010000 && Value <= 0xff0000) ||
1378 (Value >= 0x01000000 && Value <= 0xff000000) ||
1379 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1380 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1383 bool isNEONi64splat() const {
1384 if (!isImm()) return false;
1385 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1386 // Must be a constant.
1387 if (!CE) return false;
1388 uint64_t Value = CE->getValue();
1389 // i64 value with each byte being either 0 or 0xff.
1390 for (unsigned i = 0; i < 8; ++i)
1391 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1395 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1396 // Add as immediates when possible. Null MCExpr = 0.
1398 Inst.addOperand(MCOperand::CreateImm(0));
1399 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1400 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1402 Inst.addOperand(MCOperand::CreateExpr(Expr));
1405 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1406 assert(N == 2 && "Invalid number of operands!");
1407 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1408 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1409 Inst.addOperand(MCOperand::CreateReg(RegNum));
1412 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1413 assert(N == 1 && "Invalid number of operands!");
1414 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1417 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1418 assert(N == 1 && "Invalid number of operands!");
1419 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1422 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1423 assert(N == 1 && "Invalid number of operands!");
1424 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1427 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1428 assert(N == 1 && "Invalid number of operands!");
1429 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1432 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1433 assert(N == 1 && "Invalid number of operands!");
1434 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1437 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1438 assert(N == 1 && "Invalid number of operands!");
1439 Inst.addOperand(MCOperand::CreateReg(getReg()));
1442 void addRegOperands(MCInst &Inst, unsigned N) const {
1443 assert(N == 1 && "Invalid number of operands!");
1444 Inst.addOperand(MCOperand::CreateReg(getReg()));
1447 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1448 assert(N == 3 && "Invalid number of operands!");
1449 assert(isRegShiftedReg() &&
1450 "addRegShiftedRegOperands() on non RegShiftedReg!");
1451 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1452 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1453 Inst.addOperand(MCOperand::CreateImm(
1454 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1457 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1458 assert(N == 2 && "Invalid number of operands!");
1459 assert(isRegShiftedImm() &&
1460 "addRegShiftedImmOperands() on non RegShiftedImm!");
1461 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1462 // Shift of #32 is encoded as 0 where permitted
1463 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1464 Inst.addOperand(MCOperand::CreateImm(
1465 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1468 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1469 assert(N == 1 && "Invalid number of operands!");
1470 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1474 void addRegListOperands(MCInst &Inst, unsigned N) const {
1475 assert(N == 1 && "Invalid number of operands!");
1476 const SmallVectorImpl<unsigned> &RegList = getRegList();
1477 for (SmallVectorImpl<unsigned>::const_iterator
1478 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1479 Inst.addOperand(MCOperand::CreateReg(*I));
1482 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1483 addRegListOperands(Inst, N);
1486 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1487 addRegListOperands(Inst, N);
1490 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1491 assert(N == 1 && "Invalid number of operands!");
1492 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1493 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1496 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1497 assert(N == 1 && "Invalid number of operands!");
1498 // Munge the lsb/width into a bitfield mask.
1499 unsigned lsb = Bitfield.LSB;
1500 unsigned width = Bitfield.Width;
1501 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1502 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1503 (32 - (lsb + width)));
1504 Inst.addOperand(MCOperand::CreateImm(Mask));
1507 void addImmOperands(MCInst &Inst, unsigned N) const {
1508 assert(N == 1 && "Invalid number of operands!");
1509 addExpr(Inst, getImm());
1512 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1513 assert(N == 1 && "Invalid number of operands!");
1514 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1515 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1518 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1519 assert(N == 1 && "Invalid number of operands!");
1520 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1521 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1524 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1525 assert(N == 1 && "Invalid number of operands!");
1526 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1527 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1528 Inst.addOperand(MCOperand::CreateImm(Val));
1531 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1532 assert(N == 1 && "Invalid number of operands!");
1533 // FIXME: We really want to scale the value here, but the LDRD/STRD
1534 // instruction don't encode operands that way yet.
1535 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1536 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1539 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1540 assert(N == 1 && "Invalid number of operands!");
1541 // The immediate is scaled by four in the encoding and is stored
1542 // in the MCInst as such. Lop off the low two bits here.
1543 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1544 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1547 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1548 assert(N == 1 && "Invalid number of operands!");
1549 // The immediate is scaled by four in the encoding and is stored
1550 // in the MCInst as such. Lop off the low two bits here.
1551 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1552 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1555 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1556 assert(N == 1 && "Invalid number of operands!");
1557 // The immediate is scaled by four in the encoding and is stored
1558 // in the MCInst as such. Lop off the low two bits here.
1559 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1560 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1563 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1564 assert(N == 1 && "Invalid number of operands!");
1565 // The constant encodes as the immediate-1, and we store in the instruction
1566 // the bits as encoded, so subtract off one here.
1567 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1568 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1571 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1572 assert(N == 1 && "Invalid number of operands!");
1573 // The constant encodes as the immediate-1, and we store in the instruction
1574 // the bits as encoded, so subtract off one here.
1575 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1576 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1579 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1580 assert(N == 1 && "Invalid number of operands!");
1581 // The constant encodes as the immediate, except for 32, which encodes as
1583 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1584 unsigned Imm = CE->getValue();
1585 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1588 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1589 assert(N == 1 && "Invalid number of operands!");
1590 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1591 // the instruction as well.
1592 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1593 int Val = CE->getValue();
1594 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1597 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1598 assert(N == 1 && "Invalid number of operands!");
1599 // The operand is actually a t2_so_imm, but we have its bitwise
1600 // negation in the assembly source, so twiddle it here.
1601 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1602 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1605 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1606 assert(N == 1 && "Invalid number of operands!");
1607 // The operand is actually a t2_so_imm, but we have its
1608 // negation in the assembly source, so twiddle it here.
1609 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1610 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1613 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1614 assert(N == 1 && "Invalid number of operands!");
1615 // The operand is actually an imm0_4095, but we have its
1616 // negation in the assembly source, so twiddle it here.
1617 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1618 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1621 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1622 assert(N == 1 && "Invalid number of operands!");
1623 // The operand is actually a so_imm, but we have its bitwise
1624 // negation in the assembly source, so twiddle it here.
1625 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1626 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1629 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1630 assert(N == 1 && "Invalid number of operands!");
1631 // The operand is actually a so_imm, but we have its
1632 // negation in the assembly source, so twiddle it here.
1633 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1634 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1637 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1638 assert(N == 1 && "Invalid number of operands!");
1639 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1642 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1643 assert(N == 1 && "Invalid number of operands!");
1644 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1647 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1648 assert(N == 1 && "Invalid number of operands!");
1649 int32_t Imm = Memory.OffsetImm->getValue();
1650 // FIXME: Handle #-0
1651 if (Imm == INT32_MIN) Imm = 0;
1652 Inst.addOperand(MCOperand::CreateImm(Imm));
1655 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1656 assert(N == 1 && "Invalid number of operands!");
1657 assert(isImm() && "Not an immediate!");
1659 // If we have an immediate that's not a constant, treat it as a label
1660 // reference needing a fixup.
1661 if (!isa<MCConstantExpr>(getImm())) {
1662 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1666 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1667 int Val = CE->getValue();
1668 Inst.addOperand(MCOperand::CreateImm(Val));
1671 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1672 assert(N == 2 && "Invalid number of operands!");
1673 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1674 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1677 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1678 assert(N == 3 && "Invalid number of operands!");
1679 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1680 if (!Memory.OffsetRegNum) {
1681 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1682 // Special case for #-0
1683 if (Val == INT32_MIN) Val = 0;
1684 if (Val < 0) Val = -Val;
1685 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1687 // For register offset, we encode the shift type and negation flag
1689 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1690 Memory.ShiftImm, Memory.ShiftType);
1692 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1693 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1694 Inst.addOperand(MCOperand::CreateImm(Val));
1697 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1698 assert(N == 2 && "Invalid number of operands!");
1699 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1700 assert(CE && "non-constant AM2OffsetImm operand!");
1701 int32_t Val = CE->getValue();
1702 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1703 // Special case for #-0
1704 if (Val == INT32_MIN) Val = 0;
1705 if (Val < 0) Val = -Val;
1706 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1707 Inst.addOperand(MCOperand::CreateReg(0));
1708 Inst.addOperand(MCOperand::CreateImm(Val));
1711 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1712 assert(N == 3 && "Invalid number of operands!");
1713 // If we have an immediate that's not a constant, treat it as a label
1714 // reference needing a fixup. If it is a constant, it's something else
1715 // and we reject it.
1717 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1718 Inst.addOperand(MCOperand::CreateReg(0));
1719 Inst.addOperand(MCOperand::CreateImm(0));
1723 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1724 if (!Memory.OffsetRegNum) {
1725 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1726 // Special case for #-0
1727 if (Val == INT32_MIN) Val = 0;
1728 if (Val < 0) Val = -Val;
1729 Val = ARM_AM::getAM3Opc(AddSub, Val);
1731 // For register offset, we encode the shift type and negation flag
1733 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1735 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1736 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1737 Inst.addOperand(MCOperand::CreateImm(Val));
1740 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1741 assert(N == 2 && "Invalid number of operands!");
1742 if (Kind == k_PostIndexRegister) {
1744 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1745 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1746 Inst.addOperand(MCOperand::CreateImm(Val));
1751 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1752 int32_t Val = CE->getValue();
1753 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1754 // Special case for #-0
1755 if (Val == INT32_MIN) Val = 0;
1756 if (Val < 0) Val = -Val;
1757 Val = ARM_AM::getAM3Opc(AddSub, Val);
1758 Inst.addOperand(MCOperand::CreateReg(0));
1759 Inst.addOperand(MCOperand::CreateImm(Val));
1762 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1763 assert(N == 2 && "Invalid number of operands!");
1764 // If we have an immediate that's not a constant, treat it as a label
1765 // reference needing a fixup. If it is a constant, it's something else
1766 // and we reject it.
1768 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1769 Inst.addOperand(MCOperand::CreateImm(0));
1773 // The lower two bits are always zero and as such are not encoded.
1774 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1775 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1776 // Special case for #-0
1777 if (Val == INT32_MIN) Val = 0;
1778 if (Val < 0) Val = -Val;
1779 Val = ARM_AM::getAM5Opc(AddSub, Val);
1780 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1781 Inst.addOperand(MCOperand::CreateImm(Val));
1784 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1785 assert(N == 2 && "Invalid number of operands!");
1786 // If we have an immediate that's not a constant, treat it as a label
1787 // reference needing a fixup. If it is a constant, it's something else
1788 // and we reject it.
1790 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1791 Inst.addOperand(MCOperand::CreateImm(0));
1795 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1796 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1797 Inst.addOperand(MCOperand::CreateImm(Val));
1800 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1801 assert(N == 2 && "Invalid number of operands!");
1802 // The lower two bits are always zero and as such are not encoded.
1803 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1804 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1805 Inst.addOperand(MCOperand::CreateImm(Val));
1808 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1809 assert(N == 2 && "Invalid number of operands!");
1810 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1811 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1812 Inst.addOperand(MCOperand::CreateImm(Val));
1815 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1816 addMemImm8OffsetOperands(Inst, N);
1819 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1820 addMemImm8OffsetOperands(Inst, N);
1823 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1824 assert(N == 2 && "Invalid number of operands!");
1825 // If this is an immediate, it's a label reference.
1827 addExpr(Inst, getImm());
1828 Inst.addOperand(MCOperand::CreateImm(0));
1832 // Otherwise, it's a normal memory reg+offset.
1833 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1834 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1835 Inst.addOperand(MCOperand::CreateImm(Val));
1838 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1839 assert(N == 2 && "Invalid number of operands!");
1840 // If this is an immediate, it's a label reference.
1842 addExpr(Inst, getImm());
1843 Inst.addOperand(MCOperand::CreateImm(0));
1847 // Otherwise, it's a normal memory reg+offset.
1848 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1849 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1850 Inst.addOperand(MCOperand::CreateImm(Val));
1853 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1854 assert(N == 2 && "Invalid number of operands!");
1855 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1856 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1859 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
1860 assert(N == 2 && "Invalid number of operands!");
1861 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1862 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1865 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1866 assert(N == 3 && "Invalid number of operands!");
1868 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1869 Memory.ShiftImm, Memory.ShiftType);
1870 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1871 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1872 Inst.addOperand(MCOperand::CreateImm(Val));
1875 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1876 assert(N == 3 && "Invalid number of operands!");
1877 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1878 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1879 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
1882 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1883 assert(N == 2 && "Invalid number of operands!");
1884 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1885 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1888 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1889 assert(N == 2 && "Invalid number of operands!");
1890 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1891 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1892 Inst.addOperand(MCOperand::CreateImm(Val));
1895 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1896 assert(N == 2 && "Invalid number of operands!");
1897 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
1898 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1899 Inst.addOperand(MCOperand::CreateImm(Val));
1902 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1903 assert(N == 2 && "Invalid number of operands!");
1904 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
1905 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1906 Inst.addOperand(MCOperand::CreateImm(Val));
1909 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1910 assert(N == 2 && "Invalid number of operands!");
1911 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1912 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1913 Inst.addOperand(MCOperand::CreateImm(Val));
1916 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1917 assert(N == 1 && "Invalid number of operands!");
1918 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1919 assert(CE && "non-constant post-idx-imm8 operand!");
1920 int Imm = CE->getValue();
1921 bool isAdd = Imm >= 0;
1922 if (Imm == INT32_MIN) Imm = 0;
1923 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1924 Inst.addOperand(MCOperand::CreateImm(Imm));
1927 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
1928 assert(N == 1 && "Invalid number of operands!");
1929 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1930 assert(CE && "non-constant post-idx-imm8s4 operand!");
1931 int Imm = CE->getValue();
1932 bool isAdd = Imm >= 0;
1933 if (Imm == INT32_MIN) Imm = 0;
1934 // Immediate is scaled by 4.
1935 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
1936 Inst.addOperand(MCOperand::CreateImm(Imm));
1939 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1940 assert(N == 2 && "Invalid number of operands!");
1941 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1942 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1945 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1946 assert(N == 2 && "Invalid number of operands!");
1947 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1948 // The sign, shift type, and shift amount are encoded in a single operand
1949 // using the AM2 encoding helpers.
1950 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1951 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1952 PostIdxReg.ShiftTy);
1953 Inst.addOperand(MCOperand::CreateImm(Imm));
1956 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1957 assert(N == 1 && "Invalid number of operands!");
1958 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1961 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1962 assert(N == 1 && "Invalid number of operands!");
1963 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1966 void addVecListOperands(MCInst &Inst, unsigned N) const {
1967 assert(N == 1 && "Invalid number of operands!");
1968 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1971 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
1972 assert(N == 2 && "Invalid number of operands!");
1973 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1974 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
1977 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
1978 assert(N == 1 && "Invalid number of operands!");
1979 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1982 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
1983 assert(N == 1 && "Invalid number of operands!");
1984 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1987 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
1988 assert(N == 1 && "Invalid number of operands!");
1989 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1992 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
1993 assert(N == 1 && "Invalid number of operands!");
1994 // The immediate encodes the type of constant as well as the value.
1995 // Mask in that this is an i8 splat.
1996 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1997 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2000 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2001 assert(N == 1 && "Invalid number of operands!");
2002 // The immediate encodes the type of constant as well as the value.
2003 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2004 unsigned Value = CE->getValue();
2006 Value = (Value >> 8) | 0xa00;
2009 Inst.addOperand(MCOperand::CreateImm(Value));
2012 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2013 assert(N == 1 && "Invalid number of operands!");
2014 // The immediate encodes the type of constant as well as the value.
2015 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2016 unsigned Value = CE->getValue();
2017 if (Value >= 256 && Value <= 0xff00)
2018 Value = (Value >> 8) | 0x200;
2019 else if (Value > 0xffff && Value <= 0xff0000)
2020 Value = (Value >> 16) | 0x400;
2021 else if (Value > 0xffffff)
2022 Value = (Value >> 24) | 0x600;
2023 Inst.addOperand(MCOperand::CreateImm(Value));
2026 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2027 assert(N == 1 && "Invalid number of operands!");
2028 // The immediate encodes the type of constant as well as the value.
2029 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2030 unsigned Value = CE->getValue();
2031 if (Value >= 256 && Value <= 0xffff)
2032 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2033 else if (Value > 0xffff && Value <= 0xffffff)
2034 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2035 else if (Value > 0xffffff)
2036 Value = (Value >> 24) | 0x600;
2037 Inst.addOperand(MCOperand::CreateImm(Value));
2040 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2041 assert(N == 1 && "Invalid number of operands!");
2042 // The immediate encodes the type of constant as well as the value.
2043 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2044 unsigned Value = ~CE->getValue();
2045 if (Value >= 256 && Value <= 0xffff)
2046 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2047 else if (Value > 0xffff && Value <= 0xffffff)
2048 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2049 else if (Value > 0xffffff)
2050 Value = (Value >> 24) | 0x600;
2051 Inst.addOperand(MCOperand::CreateImm(Value));
2054 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2055 assert(N == 1 && "Invalid number of operands!");
2056 // The immediate encodes the type of constant as well as the value.
2057 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2058 uint64_t Value = CE->getValue();
2060 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2061 Imm |= (Value & 1) << i;
2063 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2066 virtual void print(raw_ostream &OS) const;
2068 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2069 ARMOperand *Op = new ARMOperand(k_ITCondMask);
2070 Op->ITMask.Mask = Mask;
2076 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2077 ARMOperand *Op = new ARMOperand(k_CondCode);
2084 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2085 ARMOperand *Op = new ARMOperand(k_CoprocNum);
2086 Op->Cop.Val = CopVal;
2092 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2093 ARMOperand *Op = new ARMOperand(k_CoprocReg);
2094 Op->Cop.Val = CopVal;
2100 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2101 ARMOperand *Op = new ARMOperand(k_CoprocOption);
2108 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2109 ARMOperand *Op = new ARMOperand(k_CCOut);
2110 Op->Reg.RegNum = RegNum;
2116 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2117 ARMOperand *Op = new ARMOperand(k_Token);
2118 Op->Tok.Data = Str.data();
2119 Op->Tok.Length = Str.size();
2125 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2126 ARMOperand *Op = new ARMOperand(k_Register);
2127 Op->Reg.RegNum = RegNum;
2133 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2138 ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2139 Op->RegShiftedReg.ShiftTy = ShTy;
2140 Op->RegShiftedReg.SrcReg = SrcReg;
2141 Op->RegShiftedReg.ShiftReg = ShiftReg;
2142 Op->RegShiftedReg.ShiftImm = ShiftImm;
2148 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2152 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2153 Op->RegShiftedImm.ShiftTy = ShTy;
2154 Op->RegShiftedImm.SrcReg = SrcReg;
2155 Op->RegShiftedImm.ShiftImm = ShiftImm;
2161 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2163 ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2164 Op->ShifterImm.isASR = isASR;
2165 Op->ShifterImm.Imm = Imm;
2171 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2172 ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2173 Op->RotImm.Imm = Imm;
2179 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2181 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2182 Op->Bitfield.LSB = LSB;
2183 Op->Bitfield.Width = Width;
2190 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
2191 SMLoc StartLoc, SMLoc EndLoc) {
2192 KindTy Kind = k_RegisterList;
2194 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
2195 Kind = k_DPRRegisterList;
2196 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2197 contains(Regs.front().first))
2198 Kind = k_SPRRegisterList;
2200 ARMOperand *Op = new ARMOperand(Kind);
2201 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
2202 I = Regs.begin(), E = Regs.end(); I != E; ++I)
2203 Op->Registers.push_back(I->first);
2204 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
2205 Op->StartLoc = StartLoc;
2206 Op->EndLoc = EndLoc;
2210 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2211 bool isDoubleSpaced, SMLoc S, SMLoc E) {
2212 ARMOperand *Op = new ARMOperand(k_VectorList);
2213 Op->VectorList.RegNum = RegNum;
2214 Op->VectorList.Count = Count;
2215 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2221 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2222 bool isDoubleSpaced,
2224 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2225 Op->VectorList.RegNum = RegNum;
2226 Op->VectorList.Count = Count;
2227 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2233 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2235 bool isDoubleSpaced,
2237 ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2238 Op->VectorList.RegNum = RegNum;
2239 Op->VectorList.Count = Count;
2240 Op->VectorList.LaneIndex = Index;
2241 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2247 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2249 ARMOperand *Op = new ARMOperand(k_VectorIndex);
2250 Op->VectorIndex.Val = Idx;
2256 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2257 ARMOperand *Op = new ARMOperand(k_Immediate);
2264 static ARMOperand *CreateMem(unsigned BaseRegNum,
2265 const MCConstantExpr *OffsetImm,
2266 unsigned OffsetRegNum,
2267 ARM_AM::ShiftOpc ShiftType,
2272 ARMOperand *Op = new ARMOperand(k_Memory);
2273 Op->Memory.BaseRegNum = BaseRegNum;
2274 Op->Memory.OffsetImm = OffsetImm;
2275 Op->Memory.OffsetRegNum = OffsetRegNum;
2276 Op->Memory.ShiftType = ShiftType;
2277 Op->Memory.ShiftImm = ShiftImm;
2278 Op->Memory.Alignment = Alignment;
2279 Op->Memory.isNegative = isNegative;
2285 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2286 ARM_AM::ShiftOpc ShiftTy,
2289 ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2290 Op->PostIdxReg.RegNum = RegNum;
2291 Op->PostIdxReg.isAdd = isAdd;
2292 Op->PostIdxReg.ShiftTy = ShiftTy;
2293 Op->PostIdxReg.ShiftImm = ShiftImm;
2299 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2300 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2301 Op->MBOpt.Val = Opt;
2307 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2308 ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2309 Op->IFlags.Val = IFlags;
2315 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2316 ARMOperand *Op = new ARMOperand(k_MSRMask);
2317 Op->MMask.Val = MMask;
2324 } // end anonymous namespace.
2326 void ARMOperand::print(raw_ostream &OS) const {
2329 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2332 OS << "<ccout " << getReg() << ">";
2334 case k_ITCondMask: {
2335 static const char *const MaskStr[] = {
2336 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2337 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2339 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2340 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2344 OS << "<coprocessor number: " << getCoproc() << ">";
2347 OS << "<coprocessor register: " << getCoproc() << ">";
2349 case k_CoprocOption:
2350 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2353 OS << "<mask: " << getMSRMask() << ">";
2356 getImm()->print(OS);
2358 case k_MemBarrierOpt:
2359 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
2363 << " base:" << Memory.BaseRegNum;
2366 case k_PostIndexRegister:
2367 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2368 << PostIdxReg.RegNum;
2369 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2370 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2371 << PostIdxReg.ShiftImm;
2374 case k_ProcIFlags: {
2375 OS << "<ARM_PROC::";
2376 unsigned IFlags = getProcIFlags();
2377 for (int i=2; i >= 0; --i)
2378 if (IFlags & (1 << i))
2379 OS << ARM_PROC::IFlagsToString(1 << i);
2384 OS << "<register " << getReg() << ">";
2386 case k_ShifterImmediate:
2387 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2388 << " #" << ShifterImm.Imm << ">";
2390 case k_ShiftedRegister:
2391 OS << "<so_reg_reg "
2392 << RegShiftedReg.SrcReg << " "
2393 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2394 << " " << RegShiftedReg.ShiftReg << ">";
2396 case k_ShiftedImmediate:
2397 OS << "<so_reg_imm "
2398 << RegShiftedImm.SrcReg << " "
2399 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2400 << " #" << RegShiftedImm.ShiftImm << ">";
2402 case k_RotateImmediate:
2403 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2405 case k_BitfieldDescriptor:
2406 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2407 << ", width: " << Bitfield.Width << ">";
2409 case k_RegisterList:
2410 case k_DPRRegisterList:
2411 case k_SPRRegisterList: {
2412 OS << "<register_list ";
2414 const SmallVectorImpl<unsigned> &RegList = getRegList();
2415 for (SmallVectorImpl<unsigned>::const_iterator
2416 I = RegList.begin(), E = RegList.end(); I != E; ) {
2418 if (++I < E) OS << ", ";
2425 OS << "<vector_list " << VectorList.Count << " * "
2426 << VectorList.RegNum << ">";
2428 case k_VectorListAllLanes:
2429 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2430 << VectorList.RegNum << ">";
2432 case k_VectorListIndexed:
2433 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2434 << VectorList.Count << " * " << VectorList.RegNum << ">";
2437 OS << "'" << getToken() << "'";
2440 OS << "<vectorindex " << getVectorIndex() << ">";
2445 /// @name Auto-generated Match Functions
2448 static unsigned MatchRegisterName(StringRef Name);
2452 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2453 SMLoc &StartLoc, SMLoc &EndLoc) {
2454 StartLoc = Parser.getTok().getLoc();
2455 RegNo = tryParseRegister();
2456 EndLoc = Parser.getTok().getLoc();
2458 return (RegNo == (unsigned)-1);
2461 /// Try to parse a register name. The token must be an Identifier when called,
2462 /// and if it is a register name the token is eaten and the register number is
2463 /// returned. Otherwise return -1.
2465 int ARMAsmParser::tryParseRegister() {
2466 const AsmToken &Tok = Parser.getTok();
2467 if (Tok.isNot(AsmToken::Identifier)) return -1;
2469 std::string lowerCase = Tok.getString().lower();
2470 unsigned RegNum = MatchRegisterName(lowerCase);
2472 RegNum = StringSwitch<unsigned>(lowerCase)
2473 .Case("r13", ARM::SP)
2474 .Case("r14", ARM::LR)
2475 .Case("r15", ARM::PC)
2476 .Case("ip", ARM::R12)
2477 // Additional register name aliases for 'gas' compatibility.
2478 .Case("a1", ARM::R0)
2479 .Case("a2", ARM::R1)
2480 .Case("a3", ARM::R2)
2481 .Case("a4", ARM::R3)
2482 .Case("v1", ARM::R4)
2483 .Case("v2", ARM::R5)
2484 .Case("v3", ARM::R6)
2485 .Case("v4", ARM::R7)
2486 .Case("v5", ARM::R8)
2487 .Case("v6", ARM::R9)
2488 .Case("v7", ARM::R10)
2489 .Case("v8", ARM::R11)
2490 .Case("sb", ARM::R9)
2491 .Case("sl", ARM::R10)
2492 .Case("fp", ARM::R11)
2496 // Check for aliases registered via .req. Canonicalize to lower case.
2497 // That's more consistent since register names are case insensitive, and
2498 // it's how the original entry was passed in from MC/MCParser/AsmParser.
2499 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2500 // If no match, return failure.
2501 if (Entry == RegisterReqs.end())
2503 Parser.Lex(); // Eat identifier token.
2504 return Entry->getValue();
2507 Parser.Lex(); // Eat identifier token.
2512 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
2513 // If a recoverable error occurs, return 1. If an irrecoverable error
2514 // occurs, return -1. An irrecoverable error is one where tokens have been
2515 // consumed in the process of trying to parse the shifter (i.e., when it is
2516 // indeed a shifter operand, but malformed).
2517 int ARMAsmParser::tryParseShiftRegister(
2518 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2519 SMLoc S = Parser.getTok().getLoc();
2520 const AsmToken &Tok = Parser.getTok();
2521 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2523 std::string lowerCase = Tok.getString().lower();
2524 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2525 .Case("asl", ARM_AM::lsl)
2526 .Case("lsl", ARM_AM::lsl)
2527 .Case("lsr", ARM_AM::lsr)
2528 .Case("asr", ARM_AM::asr)
2529 .Case("ror", ARM_AM::ror)
2530 .Case("rrx", ARM_AM::rrx)
2531 .Default(ARM_AM::no_shift);
2533 if (ShiftTy == ARM_AM::no_shift)
2536 Parser.Lex(); // Eat the operator.
2538 // The source register for the shift has already been added to the
2539 // operand list, so we need to pop it off and combine it into the shifted
2540 // register operand instead.
2541 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2542 if (!PrevOp->isReg())
2543 return Error(PrevOp->getStartLoc(), "shift must be of a register");
2544 int SrcReg = PrevOp->getReg();
2547 if (ShiftTy == ARM_AM::rrx) {
2548 // RRX Doesn't have an explicit shift amount. The encoder expects
2549 // the shift register to be the same as the source register. Seems odd,
2553 // Figure out if this is shifted by a constant or a register (for non-RRX).
2554 if (Parser.getTok().is(AsmToken::Hash) ||
2555 Parser.getTok().is(AsmToken::Dollar)) {
2556 Parser.Lex(); // Eat hash.
2557 SMLoc ImmLoc = Parser.getTok().getLoc();
2558 const MCExpr *ShiftExpr = 0;
2559 if (getParser().ParseExpression(ShiftExpr)) {
2560 Error(ImmLoc, "invalid immediate shift value");
2563 // The expression must be evaluatable as an immediate.
2564 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2566 Error(ImmLoc, "invalid immediate shift value");
2569 // Range check the immediate.
2570 // lsl, ror: 0 <= imm <= 31
2571 // lsr, asr: 0 <= imm <= 32
2572 Imm = CE->getValue();
2574 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2575 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2576 Error(ImmLoc, "immediate shift value out of range");
2579 // shift by zero is a nop. Always send it through as lsl.
2580 // ('as' compatibility)
2582 ShiftTy = ARM_AM::lsl;
2583 } else if (Parser.getTok().is(AsmToken::Identifier)) {
2584 ShiftReg = tryParseRegister();
2585 SMLoc L = Parser.getTok().getLoc();
2586 if (ShiftReg == -1) {
2587 Error (L, "expected immediate or register in shift operand");
2591 Error (Parser.getTok().getLoc(),
2592 "expected immediate or register in shift operand");
2597 if (ShiftReg && ShiftTy != ARM_AM::rrx)
2598 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2600 S, Parser.getTok().getLoc()));
2602 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2603 S, Parser.getTok().getLoc()));
2609 /// Try to parse a register name. The token must be an Identifier when called.
2610 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
2611 /// if there is a "writeback". 'true' if it's not a register.
2613 /// TODO this is likely to change to allow different register types and or to
2614 /// parse for a specific register type.
2616 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2617 SMLoc S = Parser.getTok().getLoc();
2618 int RegNo = tryParseRegister();
2622 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
2624 const AsmToken &ExclaimTok = Parser.getTok();
2625 if (ExclaimTok.is(AsmToken::Exclaim)) {
2626 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2627 ExclaimTok.getLoc()));
2628 Parser.Lex(); // Eat exclaim token
2632 // Also check for an index operand. This is only legal for vector registers,
2633 // but that'll get caught OK in operand matching, so we don't need to
2634 // explicitly filter everything else out here.
2635 if (Parser.getTok().is(AsmToken::LBrac)) {
2636 SMLoc SIdx = Parser.getTok().getLoc();
2637 Parser.Lex(); // Eat left bracket token.
2639 const MCExpr *ImmVal;
2640 if (getParser().ParseExpression(ImmVal))
2642 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2644 return TokError("immediate value expected for vector index");
2646 SMLoc E = Parser.getTok().getLoc();
2647 if (Parser.getTok().isNot(AsmToken::RBrac))
2648 return Error(E, "']' expected");
2650 Parser.Lex(); // Eat right bracket token.
2652 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2660 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
2661 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2663 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2664 // Use the same layout as the tablegen'erated register name matcher. Ugly,
2666 switch (Name.size()) {
2669 if (Name[0] != CoprocOp)
2685 if (Name[0] != CoprocOp || Name[1] != '1')
2689 case '0': return 10;
2690 case '1': return 11;
2691 case '2': return 12;
2692 case '3': return 13;
2693 case '4': return 14;
2694 case '5': return 15;
2699 /// parseITCondCode - Try to parse a condition code for an IT instruction.
2700 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2701 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2702 SMLoc S = Parser.getTok().getLoc();
2703 const AsmToken &Tok = Parser.getTok();
2704 if (!Tok.is(AsmToken::Identifier))
2705 return MatchOperand_NoMatch;
2706 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
2707 .Case("eq", ARMCC::EQ)
2708 .Case("ne", ARMCC::NE)
2709 .Case("hs", ARMCC::HS)
2710 .Case("cs", ARMCC::HS)
2711 .Case("lo", ARMCC::LO)
2712 .Case("cc", ARMCC::LO)
2713 .Case("mi", ARMCC::MI)
2714 .Case("pl", ARMCC::PL)
2715 .Case("vs", ARMCC::VS)
2716 .Case("vc", ARMCC::VC)
2717 .Case("hi", ARMCC::HI)
2718 .Case("ls", ARMCC::LS)
2719 .Case("ge", ARMCC::GE)
2720 .Case("lt", ARMCC::LT)
2721 .Case("gt", ARMCC::GT)
2722 .Case("le", ARMCC::LE)
2723 .Case("al", ARMCC::AL)
2726 return MatchOperand_NoMatch;
2727 Parser.Lex(); // Eat the token.
2729 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2731 return MatchOperand_Success;
2734 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2735 /// token must be an Identifier when called, and if it is a coprocessor
2736 /// number, the token is eaten and the operand is added to the operand list.
2737 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2738 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2739 SMLoc S = Parser.getTok().getLoc();
2740 const AsmToken &Tok = Parser.getTok();
2741 if (Tok.isNot(AsmToken::Identifier))
2742 return MatchOperand_NoMatch;
2744 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2746 return MatchOperand_NoMatch;
2748 Parser.Lex(); // Eat identifier token.
2749 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2750 return MatchOperand_Success;
2753 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2754 /// token must be an Identifier when called, and if it is a coprocessor
2755 /// number, the token is eaten and the operand is added to the operand list.
2756 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2757 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2758 SMLoc S = Parser.getTok().getLoc();
2759 const AsmToken &Tok = Parser.getTok();
2760 if (Tok.isNot(AsmToken::Identifier))
2761 return MatchOperand_NoMatch;
2763 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2765 return MatchOperand_NoMatch;
2767 Parser.Lex(); // Eat identifier token.
2768 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2769 return MatchOperand_Success;
2772 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2773 /// coproc_option : '{' imm0_255 '}'
2774 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2775 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2776 SMLoc S = Parser.getTok().getLoc();
2778 // If this isn't a '{', this isn't a coprocessor immediate operand.
2779 if (Parser.getTok().isNot(AsmToken::LCurly))
2780 return MatchOperand_NoMatch;
2781 Parser.Lex(); // Eat the '{'
2784 SMLoc Loc = Parser.getTok().getLoc();
2785 if (getParser().ParseExpression(Expr)) {
2786 Error(Loc, "illegal expression");
2787 return MatchOperand_ParseFail;
2789 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2790 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2791 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2792 return MatchOperand_ParseFail;
2794 int Val = CE->getValue();
2796 // Check for and consume the closing '}'
2797 if (Parser.getTok().isNot(AsmToken::RCurly))
2798 return MatchOperand_ParseFail;
2799 SMLoc E = Parser.getTok().getLoc();
2800 Parser.Lex(); // Eat the '}'
2802 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2803 return MatchOperand_Success;
2806 // For register list parsing, we need to map from raw GPR register numbering
2807 // to the enumeration values. The enumeration values aren't sorted by
2808 // register number due to our using "sp", "lr" and "pc" as canonical names.
2809 static unsigned getNextRegister(unsigned Reg) {
2810 // If this is a GPR, we need to do it manually, otherwise we can rely
2811 // on the sort ordering of the enumeration since the other reg-classes
2813 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2816 default: llvm_unreachable("Invalid GPR number!");
2817 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
2818 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
2819 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
2820 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
2821 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
2822 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2823 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
2824 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
2828 // Return the low-subreg of a given Q register.
2829 static unsigned getDRegFromQReg(unsigned QReg) {
2831 default: llvm_unreachable("expected a Q register!");
2832 case ARM::Q0: return ARM::D0;
2833 case ARM::Q1: return ARM::D2;
2834 case ARM::Q2: return ARM::D4;
2835 case ARM::Q3: return ARM::D6;
2836 case ARM::Q4: return ARM::D8;
2837 case ARM::Q5: return ARM::D10;
2838 case ARM::Q6: return ARM::D12;
2839 case ARM::Q7: return ARM::D14;
2840 case ARM::Q8: return ARM::D16;
2841 case ARM::Q9: return ARM::D18;
2842 case ARM::Q10: return ARM::D20;
2843 case ARM::Q11: return ARM::D22;
2844 case ARM::Q12: return ARM::D24;
2845 case ARM::Q13: return ARM::D26;
2846 case ARM::Q14: return ARM::D28;
2847 case ARM::Q15: return ARM::D30;
2851 /// Parse a register list.
2853 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2854 assert(Parser.getTok().is(AsmToken::LCurly) &&
2855 "Token is not a Left Curly Brace");
2856 SMLoc S = Parser.getTok().getLoc();
2857 Parser.Lex(); // Eat '{' token.
2858 SMLoc RegLoc = Parser.getTok().getLoc();
2860 // Check the first register in the list to see what register class
2861 // this is a list of.
2862 int Reg = tryParseRegister();
2864 return Error(RegLoc, "register expected");
2866 // The reglist instructions have at most 16 registers, so reserve
2867 // space for that many.
2868 SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
2870 // Allow Q regs and just interpret them as the two D sub-registers.
2871 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2872 Reg = getDRegFromQReg(Reg);
2873 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2876 const MCRegisterClass *RC;
2877 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2878 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
2879 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
2880 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
2881 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
2882 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
2884 return Error(RegLoc, "invalid register in register list");
2886 // Store the register.
2887 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2889 // This starts immediately after the first register token in the list,
2890 // so we can see either a comma or a minus (range separator) as a legal
2892 while (Parser.getTok().is(AsmToken::Comma) ||
2893 Parser.getTok().is(AsmToken::Minus)) {
2894 if (Parser.getTok().is(AsmToken::Minus)) {
2895 Parser.Lex(); // Eat the minus.
2896 SMLoc EndLoc = Parser.getTok().getLoc();
2897 int EndReg = tryParseRegister();
2899 return Error(EndLoc, "register expected");
2900 // Allow Q regs and just interpret them as the two D sub-registers.
2901 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
2902 EndReg = getDRegFromQReg(EndReg) + 1;
2903 // If the register is the same as the start reg, there's nothing
2907 // The register must be in the same register class as the first.
2908 if (!RC->contains(EndReg))
2909 return Error(EndLoc, "invalid register in register list");
2910 // Ranges must go from low to high.
2911 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
2912 return Error(EndLoc, "bad range in register list");
2914 // Add all the registers in the range to the register list.
2915 while (Reg != EndReg) {
2916 Reg = getNextRegister(Reg);
2917 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2921 Parser.Lex(); // Eat the comma.
2922 RegLoc = Parser.getTok().getLoc();
2924 const AsmToken RegTok = Parser.getTok();
2925 Reg = tryParseRegister();
2927 return Error(RegLoc, "register expected");
2928 // Allow Q regs and just interpret them as the two D sub-registers.
2929 bool isQReg = false;
2930 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2931 Reg = getDRegFromQReg(Reg);
2934 // The register must be in the same register class as the first.
2935 if (!RC->contains(Reg))
2936 return Error(RegLoc, "invalid register in register list");
2937 // List must be monotonically increasing.
2938 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
2939 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2940 Warning(RegLoc, "register list not in ascending order");
2942 return Error(RegLoc, "register list not in ascending order");
2944 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
2945 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
2946 ") in register list");
2949 // VFP register lists must also be contiguous.
2950 // It's OK to use the enumeration values directly here rather, as the
2951 // VFP register classes have the enum sorted properly.
2952 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
2954 return Error(RegLoc, "non-contiguous register range");
2955 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2957 Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc));
2960 SMLoc E = Parser.getTok().getLoc();
2961 if (Parser.getTok().isNot(AsmToken::RCurly))
2962 return Error(E, "'}' expected");
2963 Parser.Lex(); // Eat '}' token.
2965 // Push the register list operand.
2966 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
2968 // The ARM system instruction variants for LDM/STM have a '^' token here.
2969 if (Parser.getTok().is(AsmToken::Caret)) {
2970 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
2971 Parser.Lex(); // Eat '^' token.
2977 // Helper function to parse the lane index for vector lists.
2978 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2979 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index) {
2980 Index = 0; // Always return a defined index value.
2981 if (Parser.getTok().is(AsmToken::LBrac)) {
2982 Parser.Lex(); // Eat the '['.
2983 if (Parser.getTok().is(AsmToken::RBrac)) {
2984 // "Dn[]" is the 'all lanes' syntax.
2985 LaneKind = AllLanes;
2986 Parser.Lex(); // Eat the ']'.
2987 return MatchOperand_Success;
2990 // There's an optional '#' token here. Normally there wouldn't be, but
2991 // inline assemble puts one in, and it's friendly to accept that.
2992 if (Parser.getTok().is(AsmToken::Hash))
2993 Parser.Lex(); // Eat the '#'
2995 const MCExpr *LaneIndex;
2996 SMLoc Loc = Parser.getTok().getLoc();
2997 if (getParser().ParseExpression(LaneIndex)) {
2998 Error(Loc, "illegal expression");
2999 return MatchOperand_ParseFail;
3001 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3003 Error(Loc, "lane index must be empty or an integer");
3004 return MatchOperand_ParseFail;
3006 if (Parser.getTok().isNot(AsmToken::RBrac)) {
3007 Error(Parser.getTok().getLoc(), "']' expected");
3008 return MatchOperand_ParseFail;
3010 Parser.Lex(); // Eat the ']'.
3011 int64_t Val = CE->getValue();
3013 // FIXME: Make this range check context sensitive for .8, .16, .32.
3014 if (Val < 0 || Val > 7) {
3015 Error(Parser.getTok().getLoc(), "lane index out of range");
3016 return MatchOperand_ParseFail;
3019 LaneKind = IndexedLane;
3020 return MatchOperand_Success;
3023 return MatchOperand_Success;
3026 // parse a vector register list
3027 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3028 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3029 VectorLaneTy LaneKind;
3031 SMLoc S = Parser.getTok().getLoc();
3032 // As an extension (to match gas), support a plain D register or Q register
3033 // (without encosing curly braces) as a single or double entry list,
3035 if (Parser.getTok().is(AsmToken::Identifier)) {
3036 int Reg = tryParseRegister();
3038 return MatchOperand_NoMatch;
3039 SMLoc E = Parser.getTok().getLoc();
3040 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3041 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex);
3042 if (Res != MatchOperand_Success)
3046 E = Parser.getTok().getLoc();
3047 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3050 E = Parser.getTok().getLoc();
3051 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3055 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3060 return MatchOperand_Success;
3062 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3063 Reg = getDRegFromQReg(Reg);
3064 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex);
3065 if (Res != MatchOperand_Success)
3069 E = Parser.getTok().getLoc();
3070 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3071 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3072 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3075 E = Parser.getTok().getLoc();
3076 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3077 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3078 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3082 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3087 return MatchOperand_Success;
3089 Error(S, "vector register expected");
3090 return MatchOperand_ParseFail;
3093 if (Parser.getTok().isNot(AsmToken::LCurly))
3094 return MatchOperand_NoMatch;
3096 Parser.Lex(); // Eat '{' token.
3097 SMLoc RegLoc = Parser.getTok().getLoc();
3099 int Reg = tryParseRegister();
3101 Error(RegLoc, "register expected");
3102 return MatchOperand_ParseFail;
3106 unsigned FirstReg = Reg;
3107 // The list is of D registers, but we also allow Q regs and just interpret
3108 // them as the two D sub-registers.
3109 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3110 FirstReg = Reg = getDRegFromQReg(Reg);
3111 Spacing = 1; // double-spacing requires explicit D registers, otherwise
3112 // it's ambiguous with four-register single spaced.
3116 if (parseVectorLane(LaneKind, LaneIndex) != MatchOperand_Success)
3117 return MatchOperand_ParseFail;
3119 while (Parser.getTok().is(AsmToken::Comma) ||
3120 Parser.getTok().is(AsmToken::Minus)) {
3121 if (Parser.getTok().is(AsmToken::Minus)) {
3123 Spacing = 1; // Register range implies a single spaced list.
3124 else if (Spacing == 2) {
3125 Error(Parser.getTok().getLoc(),
3126 "sequential registers in double spaced list");
3127 return MatchOperand_ParseFail;
3129 Parser.Lex(); // Eat the minus.
3130 SMLoc EndLoc = Parser.getTok().getLoc();
3131 int EndReg = tryParseRegister();
3133 Error(EndLoc, "register expected");
3134 return MatchOperand_ParseFail;
3136 // Allow Q regs and just interpret them as the two D sub-registers.
3137 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3138 EndReg = getDRegFromQReg(EndReg) + 1;
3139 // If the register is the same as the start reg, there's nothing
3143 // The register must be in the same register class as the first.
3144 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3145 Error(EndLoc, "invalid register in register list");
3146 return MatchOperand_ParseFail;
3148 // Ranges must go from low to high.
3150 Error(EndLoc, "bad range in register list");
3151 return MatchOperand_ParseFail;
3153 // Parse the lane specifier if present.
3154 VectorLaneTy NextLaneKind;
3155 unsigned NextLaneIndex;
3156 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
3157 return MatchOperand_ParseFail;
3158 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3159 Error(EndLoc, "mismatched lane index in register list");
3160 return MatchOperand_ParseFail;
3162 EndLoc = Parser.getTok().getLoc();
3164 // Add all the registers in the range to the register list.
3165 Count += EndReg - Reg;
3169 Parser.Lex(); // Eat the comma.
3170 RegLoc = Parser.getTok().getLoc();
3172 Reg = tryParseRegister();
3174 Error(RegLoc, "register expected");
3175 return MatchOperand_ParseFail;
3177 // vector register lists must be contiguous.
3178 // It's OK to use the enumeration values directly here rather, as the
3179 // VFP register classes have the enum sorted properly.
3181 // The list is of D registers, but we also allow Q regs and just interpret
3182 // them as the two D sub-registers.
3183 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3185 Spacing = 1; // Register range implies a single spaced list.
3186 else if (Spacing == 2) {
3188 "invalid register in double-spaced list (must be 'D' register')");
3189 return MatchOperand_ParseFail;
3191 Reg = getDRegFromQReg(Reg);
3192 if (Reg != OldReg + 1) {
3193 Error(RegLoc, "non-contiguous register range");
3194 return MatchOperand_ParseFail;
3198 // Parse the lane specifier if present.
3199 VectorLaneTy NextLaneKind;
3200 unsigned NextLaneIndex;
3201 SMLoc EndLoc = Parser.getTok().getLoc();
3202 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
3203 return MatchOperand_ParseFail;
3204 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3205 Error(EndLoc, "mismatched lane index in register list");
3206 return MatchOperand_ParseFail;
3210 // Normal D register.
3211 // Figure out the register spacing (single or double) of the list if
3212 // we don't know it already.
3214 Spacing = 1 + (Reg == OldReg + 2);
3216 // Just check that it's contiguous and keep going.
3217 if (Reg != OldReg + Spacing) {
3218 Error(RegLoc, "non-contiguous register range");
3219 return MatchOperand_ParseFail;
3222 // Parse the lane specifier if present.
3223 VectorLaneTy NextLaneKind;
3224 unsigned NextLaneIndex;
3225 SMLoc EndLoc = Parser.getTok().getLoc();
3226 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
3227 return MatchOperand_ParseFail;
3228 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3229 Error(EndLoc, "mismatched lane index in register list");
3230 return MatchOperand_ParseFail;
3234 SMLoc E = Parser.getTok().getLoc();
3235 if (Parser.getTok().isNot(AsmToken::RCurly)) {
3236 Error(E, "'}' expected");
3237 return MatchOperand_ParseFail;
3239 Parser.Lex(); // Eat '}' token.
3243 // Two-register operands have been converted to the
3244 // composite register classes.
3246 const MCRegisterClass *RC = (Spacing == 1) ?
3247 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3248 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3249 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3252 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3253 (Spacing == 2), S, E));
3256 // Two-register operands have been converted to the
3257 // composite register classes.
3259 const MCRegisterClass *RC = (Spacing == 1) ?
3260 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3261 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3262 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3264 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3269 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3275 return MatchOperand_Success;
3278 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3279 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3280 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3281 SMLoc S = Parser.getTok().getLoc();
3282 const AsmToken &Tok = Parser.getTok();
3285 if (Tok.is(AsmToken::Identifier)) {
3286 StringRef OptStr = Tok.getString();
3288 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3289 .Case("sy", ARM_MB::SY)
3290 .Case("st", ARM_MB::ST)
3291 .Case("sh", ARM_MB::ISH)
3292 .Case("ish", ARM_MB::ISH)
3293 .Case("shst", ARM_MB::ISHST)
3294 .Case("ishst", ARM_MB::ISHST)
3295 .Case("nsh", ARM_MB::NSH)
3296 .Case("un", ARM_MB::NSH)
3297 .Case("nshst", ARM_MB::NSHST)
3298 .Case("unst", ARM_MB::NSHST)
3299 .Case("osh", ARM_MB::OSH)
3300 .Case("oshst", ARM_MB::OSHST)
3304 return MatchOperand_NoMatch;
3306 Parser.Lex(); // Eat identifier token.
3307 } else if (Tok.is(AsmToken::Hash) ||
3308 Tok.is(AsmToken::Dollar) ||
3309 Tok.is(AsmToken::Integer)) {
3310 if (Parser.getTok().isNot(AsmToken::Integer))
3311 Parser.Lex(); // Eat the '#'.
3312 SMLoc Loc = Parser.getTok().getLoc();
3314 const MCExpr *MemBarrierID;
3315 if (getParser().ParseExpression(MemBarrierID)) {
3316 Error(Loc, "illegal expression");
3317 return MatchOperand_ParseFail;
3320 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3322 Error(Loc, "constant expression expected");
3323 return MatchOperand_ParseFail;
3326 int Val = CE->getValue();
3328 Error(Loc, "immediate value out of range");
3329 return MatchOperand_ParseFail;
3332 Opt = ARM_MB::RESERVED_0 + Val;
3334 return MatchOperand_ParseFail;
3336 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3337 return MatchOperand_Success;
3340 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3341 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3342 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3343 SMLoc S = Parser.getTok().getLoc();
3344 const AsmToken &Tok = Parser.getTok();
3345 if (!Tok.is(AsmToken::Identifier))
3346 return MatchOperand_NoMatch;
3347 StringRef IFlagsStr = Tok.getString();
3349 // An iflags string of "none" is interpreted to mean that none of the AIF
3350 // bits are set. Not a terribly useful instruction, but a valid encoding.
3351 unsigned IFlags = 0;
3352 if (IFlagsStr != "none") {
3353 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3354 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3355 .Case("a", ARM_PROC::A)
3356 .Case("i", ARM_PROC::I)
3357 .Case("f", ARM_PROC::F)
3360 // If some specific iflag is already set, it means that some letter is
3361 // present more than once, this is not acceptable.
3362 if (Flag == ~0U || (IFlags & Flag))
3363 return MatchOperand_NoMatch;
3369 Parser.Lex(); // Eat identifier token.
3370 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3371 return MatchOperand_Success;
3374 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3375 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3376 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3377 SMLoc S = Parser.getTok().getLoc();
3378 const AsmToken &Tok = Parser.getTok();
3379 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
3380 StringRef Mask = Tok.getString();
3383 // See ARMv6-M 10.1.1
3384 std::string Name = Mask.lower();
3385 unsigned FlagsVal = StringSwitch<unsigned>(Name)
3386 // Note: in the documentation:
3387 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3388 // for MSR APSR_nzcvq.
3389 // but we do make it an alias here. This is so to get the "mask encoding"
3390 // bits correct on MSR APSR writes.
3392 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3393 // should really only be allowed when writing a special register. Note
3394 // they get dropped in the MRS instruction reading a special register as
3395 // the SYSm field is only 8 bits.
3397 // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3398 // includes the DSP extension but that is not checked.
3399 .Case("apsr", 0x800)
3400 .Case("apsr_nzcvq", 0x800)
3401 .Case("apsr_g", 0x400)
3402 .Case("apsr_nzcvqg", 0xc00)
3403 .Case("iapsr", 0x801)
3404 .Case("iapsr_nzcvq", 0x801)
3405 .Case("iapsr_g", 0x401)
3406 .Case("iapsr_nzcvqg", 0xc01)
3407 .Case("eapsr", 0x802)
3408 .Case("eapsr_nzcvq", 0x802)
3409 .Case("eapsr_g", 0x402)
3410 .Case("eapsr_nzcvqg", 0xc02)
3411 .Case("xpsr", 0x803)
3412 .Case("xpsr_nzcvq", 0x803)
3413 .Case("xpsr_g", 0x403)
3414 .Case("xpsr_nzcvqg", 0xc03)
3415 .Case("ipsr", 0x805)
3416 .Case("epsr", 0x806)
3417 .Case("iepsr", 0x807)
3420 .Case("primask", 0x810)
3421 .Case("basepri", 0x811)
3422 .Case("basepri_max", 0x812)
3423 .Case("faultmask", 0x813)
3424 .Case("control", 0x814)
3427 if (FlagsVal == ~0U)
3428 return MatchOperand_NoMatch;
3430 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3431 // basepri, basepri_max and faultmask only valid for V7m.
3432 return MatchOperand_NoMatch;
3434 Parser.Lex(); // Eat identifier token.
3435 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3436 return MatchOperand_Success;
3439 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3440 size_t Start = 0, Next = Mask.find('_');
3441 StringRef Flags = "";
3442 std::string SpecReg = Mask.slice(Start, Next).lower();
3443 if (Next != StringRef::npos)
3444 Flags = Mask.slice(Next+1, Mask.size());
3446 // FlagsVal contains the complete mask:
3448 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3449 unsigned FlagsVal = 0;
3451 if (SpecReg == "apsr") {
3452 FlagsVal = StringSwitch<unsigned>(Flags)
3453 .Case("nzcvq", 0x8) // same as CPSR_f
3454 .Case("g", 0x4) // same as CPSR_s
3455 .Case("nzcvqg", 0xc) // same as CPSR_fs
3458 if (FlagsVal == ~0U) {
3460 return MatchOperand_NoMatch;
3462 FlagsVal = 8; // No flag
3464 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3465 // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3466 if (Flags == "all" || Flags == "")
3468 for (int i = 0, e = Flags.size(); i != e; ++i) {
3469 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3476 // If some specific flag is already set, it means that some letter is
3477 // present more than once, this is not acceptable.
3478 if (FlagsVal == ~0U || (FlagsVal & Flag))
3479 return MatchOperand_NoMatch;
3482 } else // No match for special register.
3483 return MatchOperand_NoMatch;
3485 // Special register without flags is NOT equivalent to "fc" flags.
3486 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
3487 // two lines would enable gas compatibility at the expense of breaking
3493 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3494 if (SpecReg == "spsr")
3497 Parser.Lex(); // Eat identifier token.
3498 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3499 return MatchOperand_Success;
3502 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3503 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3504 int Low, int High) {
3505 const AsmToken &Tok = Parser.getTok();
3506 if (Tok.isNot(AsmToken::Identifier)) {
3507 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3508 return MatchOperand_ParseFail;
3510 StringRef ShiftName = Tok.getString();
3511 std::string LowerOp = Op.lower();
3512 std::string UpperOp = Op.upper();
3513 if (ShiftName != LowerOp && ShiftName != UpperOp) {
3514 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3515 return MatchOperand_ParseFail;
3517 Parser.Lex(); // Eat shift type token.
3519 // There must be a '#' and a shift amount.
3520 if (Parser.getTok().isNot(AsmToken::Hash) &&
3521 Parser.getTok().isNot(AsmToken::Dollar)) {
3522 Error(Parser.getTok().getLoc(), "'#' expected");
3523 return MatchOperand_ParseFail;
3525 Parser.Lex(); // Eat hash token.
3527 const MCExpr *ShiftAmount;
3528 SMLoc Loc = Parser.getTok().getLoc();
3529 if (getParser().ParseExpression(ShiftAmount)) {
3530 Error(Loc, "illegal expression");
3531 return MatchOperand_ParseFail;
3533 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3535 Error(Loc, "constant expression expected");
3536 return MatchOperand_ParseFail;
3538 int Val = CE->getValue();
3539 if (Val < Low || Val > High) {
3540 Error(Loc, "immediate value out of range");
3541 return MatchOperand_ParseFail;
3544 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
3546 return MatchOperand_Success;
3549 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3550 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3551 const AsmToken &Tok = Parser.getTok();
3552 SMLoc S = Tok.getLoc();
3553 if (Tok.isNot(AsmToken::Identifier)) {
3554 Error(Tok.getLoc(), "'be' or 'le' operand expected");
3555 return MatchOperand_ParseFail;
3557 int Val = StringSwitch<int>(Tok.getString())
3561 Parser.Lex(); // Eat the token.
3564 Error(Tok.getLoc(), "'be' or 'le' operand expected");
3565 return MatchOperand_ParseFail;
3567 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3569 S, Parser.getTok().getLoc()));
3570 return MatchOperand_Success;
3573 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3574 /// instructions. Legal values are:
3575 /// lsl #n 'n' in [0,31]
3576 /// asr #n 'n' in [1,32]
3577 /// n == 32 encoded as n == 0.
3578 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3579 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3580 const AsmToken &Tok = Parser.getTok();
3581 SMLoc S = Tok.getLoc();
3582 if (Tok.isNot(AsmToken::Identifier)) {
3583 Error(S, "shift operator 'asr' or 'lsl' expected");
3584 return MatchOperand_ParseFail;
3586 StringRef ShiftName = Tok.getString();
3588 if (ShiftName == "lsl" || ShiftName == "LSL")
3590 else if (ShiftName == "asr" || ShiftName == "ASR")
3593 Error(S, "shift operator 'asr' or 'lsl' expected");
3594 return MatchOperand_ParseFail;
3596 Parser.Lex(); // Eat the operator.
3598 // A '#' and a shift amount.
3599 if (Parser.getTok().isNot(AsmToken::Hash) &&
3600 Parser.getTok().isNot(AsmToken::Dollar)) {
3601 Error(Parser.getTok().getLoc(), "'#' expected");
3602 return MatchOperand_ParseFail;
3604 Parser.Lex(); // Eat hash token.
3606 const MCExpr *ShiftAmount;
3607 SMLoc E = Parser.getTok().getLoc();
3608 if (getParser().ParseExpression(ShiftAmount)) {
3609 Error(E, "malformed shift expression");
3610 return MatchOperand_ParseFail;
3612 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3614 Error(E, "shift amount must be an immediate");
3615 return MatchOperand_ParseFail;
3618 int64_t Val = CE->getValue();
3620 // Shift amount must be in [1,32]
3621 if (Val < 1 || Val > 32) {
3622 Error(E, "'asr' shift amount must be in range [1,32]");
3623 return MatchOperand_ParseFail;
3625 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3626 if (isThumb() && Val == 32) {
3627 Error(E, "'asr #32' shift amount not allowed in Thumb mode");
3628 return MatchOperand_ParseFail;
3630 if (Val == 32) Val = 0;
3632 // Shift amount must be in [1,32]
3633 if (Val < 0 || Val > 31) {
3634 Error(E, "'lsr' shift amount must be in range [0,31]");
3635 return MatchOperand_ParseFail;
3639 E = Parser.getTok().getLoc();
3640 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
3642 return MatchOperand_Success;
3645 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3646 /// of instructions. Legal values are:
3647 /// ror #n 'n' in {0, 8, 16, 24}
3648 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3649 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3650 const AsmToken &Tok = Parser.getTok();
3651 SMLoc S = Tok.getLoc();
3652 if (Tok.isNot(AsmToken::Identifier))
3653 return MatchOperand_NoMatch;
3654 StringRef ShiftName = Tok.getString();
3655 if (ShiftName != "ror" && ShiftName != "ROR")
3656 return MatchOperand_NoMatch;
3657 Parser.Lex(); // Eat the operator.
3659 // A '#' and a rotate amount.
3660 if (Parser.getTok().isNot(AsmToken::Hash) &&
3661 Parser.getTok().isNot(AsmToken::Dollar)) {
3662 Error(Parser.getTok().getLoc(), "'#' expected");
3663 return MatchOperand_ParseFail;
3665 Parser.Lex(); // Eat hash token.
3667 const MCExpr *ShiftAmount;
3668 SMLoc E = Parser.getTok().getLoc();
3669 if (getParser().ParseExpression(ShiftAmount)) {
3670 Error(E, "malformed rotate expression");
3671 return MatchOperand_ParseFail;
3673 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3675 Error(E, "rotate amount must be an immediate");
3676 return MatchOperand_ParseFail;
3679 int64_t Val = CE->getValue();
3680 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
3681 // normally, zero is represented in asm by omitting the rotate operand
3683 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
3684 Error(E, "'ror' rotate amount must be 8, 16, or 24");
3685 return MatchOperand_ParseFail;
3688 E = Parser.getTok().getLoc();
3689 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
3691 return MatchOperand_Success;
3694 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3695 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3696 SMLoc S = Parser.getTok().getLoc();
3697 // The bitfield descriptor is really two operands, the LSB and the width.
3698 if (Parser.getTok().isNot(AsmToken::Hash) &&
3699 Parser.getTok().isNot(AsmToken::Dollar)) {
3700 Error(Parser.getTok().getLoc(), "'#' expected");
3701 return MatchOperand_ParseFail;
3703 Parser.Lex(); // Eat hash token.
3705 const MCExpr *LSBExpr;
3706 SMLoc E = Parser.getTok().getLoc();
3707 if (getParser().ParseExpression(LSBExpr)) {
3708 Error(E, "malformed immediate expression");
3709 return MatchOperand_ParseFail;
3711 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
3713 Error(E, "'lsb' operand must be an immediate");
3714 return MatchOperand_ParseFail;
3717 int64_t LSB = CE->getValue();
3718 // The LSB must be in the range [0,31]
3719 if (LSB < 0 || LSB > 31) {
3720 Error(E, "'lsb' operand must be in the range [0,31]");
3721 return MatchOperand_ParseFail;
3723 E = Parser.getTok().getLoc();
3725 // Expect another immediate operand.
3726 if (Parser.getTok().isNot(AsmToken::Comma)) {
3727 Error(Parser.getTok().getLoc(), "too few operands");
3728 return MatchOperand_ParseFail;
3730 Parser.Lex(); // Eat hash token.
3731 if (Parser.getTok().isNot(AsmToken::Hash) &&
3732 Parser.getTok().isNot(AsmToken::Dollar)) {
3733 Error(Parser.getTok().getLoc(), "'#' expected");
3734 return MatchOperand_ParseFail;
3736 Parser.Lex(); // Eat hash token.
3738 const MCExpr *WidthExpr;
3739 if (getParser().ParseExpression(WidthExpr)) {
3740 Error(E, "malformed immediate expression");
3741 return MatchOperand_ParseFail;
3743 CE = dyn_cast<MCConstantExpr>(WidthExpr);
3745 Error(E, "'width' operand must be an immediate");
3746 return MatchOperand_ParseFail;
3749 int64_t Width = CE->getValue();
3750 // The LSB must be in the range [1,32-lsb]
3751 if (Width < 1 || Width > 32 - LSB) {
3752 Error(E, "'width' operand must be in the range [1,32-lsb]");
3753 return MatchOperand_ParseFail;
3755 E = Parser.getTok().getLoc();
3757 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
3759 return MatchOperand_Success;
3762 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3763 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3764 // Check for a post-index addressing register operand. Specifically:
3765 // postidx_reg := '+' register {, shift}
3766 // | '-' register {, shift}
3767 // | register {, shift}
3769 // This method must return MatchOperand_NoMatch without consuming any tokens
3770 // in the case where there is no match, as other alternatives take other
3772 AsmToken Tok = Parser.getTok();
3773 SMLoc S = Tok.getLoc();
3774 bool haveEaten = false;
3777 if (Tok.is(AsmToken::Plus)) {
3778 Parser.Lex(); // Eat the '+' token.
3780 } else if (Tok.is(AsmToken::Minus)) {
3781 Parser.Lex(); // Eat the '-' token.
3785 if (Parser.getTok().is(AsmToken::Identifier))
3786 Reg = tryParseRegister();
3789 return MatchOperand_NoMatch;
3790 Error(Parser.getTok().getLoc(), "register expected");
3791 return MatchOperand_ParseFail;
3793 SMLoc E = Parser.getTok().getLoc();
3795 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
3796 unsigned ShiftImm = 0;
3797 if (Parser.getTok().is(AsmToken::Comma)) {
3798 Parser.Lex(); // Eat the ','.
3799 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
3800 return MatchOperand_ParseFail;
3803 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
3806 return MatchOperand_Success;
3809 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3810 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3811 // Check for a post-index addressing register operand. Specifically:
3812 // am3offset := '+' register
3819 // This method must return MatchOperand_NoMatch without consuming any tokens
3820 // in the case where there is no match, as other alternatives take other
3822 AsmToken Tok = Parser.getTok();
3823 SMLoc S = Tok.getLoc();
3825 // Do immediates first, as we always parse those if we have a '#'.
3826 if (Parser.getTok().is(AsmToken::Hash) ||
3827 Parser.getTok().is(AsmToken::Dollar)) {
3828 Parser.Lex(); // Eat the '#'.
3829 // Explicitly look for a '-', as we need to encode negative zero
3831 bool isNegative = Parser.getTok().is(AsmToken::Minus);
3832 const MCExpr *Offset;
3833 if (getParser().ParseExpression(Offset))
3834 return MatchOperand_ParseFail;
3835 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
3837 Error(S, "constant expression expected");
3838 return MatchOperand_ParseFail;
3840 SMLoc E = Tok.getLoc();
3841 // Negative zero is encoded as the flag value INT32_MIN.
3842 int32_t Val = CE->getValue();
3843 if (isNegative && Val == 0)
3847 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
3849 return MatchOperand_Success;
3853 bool haveEaten = false;
3856 if (Tok.is(AsmToken::Plus)) {
3857 Parser.Lex(); // Eat the '+' token.
3859 } else if (Tok.is(AsmToken::Minus)) {
3860 Parser.Lex(); // Eat the '-' token.
3864 if (Parser.getTok().is(AsmToken::Identifier))
3865 Reg = tryParseRegister();
3868 return MatchOperand_NoMatch;
3869 Error(Parser.getTok().getLoc(), "register expected");
3870 return MatchOperand_ParseFail;
3872 SMLoc E = Parser.getTok().getLoc();
3874 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
3877 return MatchOperand_Success;
3880 /// cvtT2LdrdPre - Convert parsed operands to MCInst.
3881 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3882 /// when they refer multiple MIOperands inside a single one.
3884 cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
3885 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3887 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3888 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3889 // Create a writeback register dummy placeholder.
3890 Inst.addOperand(MCOperand::CreateReg(0));
3892 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3894 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3898 /// cvtT2StrdPre - Convert parsed operands to MCInst.
3899 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3900 /// when they refer multiple MIOperands inside a single one.
3902 cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
3903 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3904 // Create a writeback register dummy placeholder.
3905 Inst.addOperand(MCOperand::CreateReg(0));
3907 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3908 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3910 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3912 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3916 /// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3917 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3918 /// when they refer multiple MIOperands inside a single one.
3920 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3921 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3922 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3924 // Create a writeback register dummy placeholder.
3925 Inst.addOperand(MCOperand::CreateImm(0));
3927 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3928 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3932 /// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3933 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3934 /// when they refer multiple MIOperands inside a single one.
3936 cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3937 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3938 // Create a writeback register dummy placeholder.
3939 Inst.addOperand(MCOperand::CreateImm(0));
3940 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3941 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3942 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3946 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3947 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3948 /// when they refer multiple MIOperands inside a single one.
3950 cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3951 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3952 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3954 // Create a writeback register dummy placeholder.
3955 Inst.addOperand(MCOperand::CreateImm(0));
3957 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3958 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3962 /// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3963 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3964 /// when they refer multiple MIOperands inside a single one.
3966 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3967 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3968 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3970 // Create a writeback register dummy placeholder.
3971 Inst.addOperand(MCOperand::CreateImm(0));
3973 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3974 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3979 /// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3980 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3981 /// when they refer multiple MIOperands inside a single one.
3983 cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3984 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3985 // Create a writeback register dummy placeholder.
3986 Inst.addOperand(MCOperand::CreateImm(0));
3987 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3988 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3989 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3993 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3994 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3995 /// when they refer multiple MIOperands inside a single one.
3997 cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3998 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3999 // Create a writeback register dummy placeholder.
4000 Inst.addOperand(MCOperand::CreateImm(0));
4001 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4002 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
4003 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4007 /// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
4008 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4009 /// when they refer multiple MIOperands inside a single one.
4011 cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
4012 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4013 // Create a writeback register dummy placeholder.
4014 Inst.addOperand(MCOperand::CreateImm(0));
4015 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4016 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4017 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4021 /// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
4022 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4023 /// when they refer multiple MIOperands inside a single one.
4025 cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
4026 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4028 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4029 // Create a writeback register dummy placeholder.
4030 Inst.addOperand(MCOperand::CreateImm(0));
4032 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4034 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4036 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4040 /// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
4041 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4042 /// when they refer multiple MIOperands inside a single one.
4044 cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
4045 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4047 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4048 // Create a writeback register dummy placeholder.
4049 Inst.addOperand(MCOperand::CreateImm(0));
4051 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4053 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4055 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4059 /// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
4060 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4061 /// when they refer multiple MIOperands inside a single one.
4063 cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
4064 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4065 // Create a writeback register dummy placeholder.
4066 Inst.addOperand(MCOperand::CreateImm(0));
4068 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4070 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4072 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4074 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4078 /// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
4079 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4080 /// when they refer multiple MIOperands inside a single one.
4082 cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
4083 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4084 // Create a writeback register dummy placeholder.
4085 Inst.addOperand(MCOperand::CreateImm(0));
4087 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4089 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4091 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4093 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4097 /// cvtLdrdPre - Convert parsed operands to MCInst.
4098 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4099 /// when they refer multiple MIOperands inside a single one.
4101 cvtLdrdPre(MCInst &Inst, unsigned Opcode,
4102 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4104 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4105 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4106 // Create a writeback register dummy placeholder.
4107 Inst.addOperand(MCOperand::CreateImm(0));
4109 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4111 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4115 /// cvtStrdPre - Convert parsed operands to MCInst.
4116 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4117 /// when they refer multiple MIOperands inside a single one.
4119 cvtStrdPre(MCInst &Inst, unsigned Opcode,
4120 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4121 // Create a writeback register dummy placeholder.
4122 Inst.addOperand(MCOperand::CreateImm(0));
4124 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4125 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4127 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4129 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4133 /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
4134 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4135 /// when they refer multiple MIOperands inside a single one.
4137 cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
4138 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4139 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4140 // Create a writeback register dummy placeholder.
4141 Inst.addOperand(MCOperand::CreateImm(0));
4142 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4143 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4147 /// cvtThumbMultiple- Convert parsed operands to MCInst.
4148 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4149 /// when they refer multiple MIOperands inside a single one.
4151 cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
4152 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4153 // The second source operand must be the same register as the destination
4155 if (Operands.size() == 6 &&
4156 (((ARMOperand*)Operands[3])->getReg() !=
4157 ((ARMOperand*)Operands[5])->getReg()) &&
4158 (((ARMOperand*)Operands[3])->getReg() !=
4159 ((ARMOperand*)Operands[4])->getReg())) {
4160 Error(Operands[3]->getStartLoc(),
4161 "destination register must match source register");
4164 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4165 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4166 // If we have a three-operand form, make sure to set Rn to be the operand
4167 // that isn't the same as Rd.
4169 if (Operands.size() == 6 &&
4170 ((ARMOperand*)Operands[4])->getReg() ==
4171 ((ARMOperand*)Operands[3])->getReg())
4173 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4174 Inst.addOperand(Inst.getOperand(0));
4175 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4181 cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
4182 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4184 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4185 // Create a writeback register dummy placeholder.
4186 Inst.addOperand(MCOperand::CreateImm(0));
4188 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4190 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4195 cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
4196 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4198 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4199 // Create a writeback register dummy placeholder.
4200 Inst.addOperand(MCOperand::CreateImm(0));
4202 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4204 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4206 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4211 cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
4212 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4213 // Create a writeback register dummy placeholder.
4214 Inst.addOperand(MCOperand::CreateImm(0));
4216 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4218 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4220 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4225 cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
4226 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4227 // Create a writeback register dummy placeholder.
4228 Inst.addOperand(MCOperand::CreateImm(0));
4230 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4232 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4234 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4236 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4240 /// Parse an ARM memory expression, return false if successful else return true
4241 /// or an error. The first token must be a '[' when called.
4243 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4245 assert(Parser.getTok().is(AsmToken::LBrac) &&
4246 "Token is not a Left Bracket");
4247 S = Parser.getTok().getLoc();
4248 Parser.Lex(); // Eat left bracket token.
4250 const AsmToken &BaseRegTok = Parser.getTok();
4251 int BaseRegNum = tryParseRegister();
4252 if (BaseRegNum == -1)
4253 return Error(BaseRegTok.getLoc(), "register expected");
4255 // The next token must either be a comma or a closing bracket.
4256 const AsmToken &Tok = Parser.getTok();
4257 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
4258 return Error(Tok.getLoc(), "malformed memory operand");
4260 if (Tok.is(AsmToken::RBrac)) {
4262 Parser.Lex(); // Eat right bracket token.
4264 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4265 0, 0, false, S, E));
4267 // If there's a pre-indexing writeback marker, '!', just add it as a token
4268 // operand. It's rather odd, but syntactically valid.
4269 if (Parser.getTok().is(AsmToken::Exclaim)) {
4270 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4271 Parser.Lex(); // Eat the '!'.
4277 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
4278 Parser.Lex(); // Eat the comma.
4280 // If we have a ':', it's an alignment specifier.
4281 if (Parser.getTok().is(AsmToken::Colon)) {
4282 Parser.Lex(); // Eat the ':'.
4283 E = Parser.getTok().getLoc();
4286 if (getParser().ParseExpression(Expr))
4289 // The expression has to be a constant. Memory references with relocations
4290 // don't come through here, as they use the <label> forms of the relevant
4292 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4294 return Error (E, "constant expression expected");
4297 switch (CE->getValue()) {
4300 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4301 case 16: Align = 2; break;
4302 case 32: Align = 4; break;
4303 case 64: Align = 8; break;
4304 case 128: Align = 16; break;
4305 case 256: Align = 32; break;
4308 // Now we should have the closing ']'
4309 E = Parser.getTok().getLoc();
4310 if (Parser.getTok().isNot(AsmToken::RBrac))
4311 return Error(E, "']' expected");
4312 Parser.Lex(); // Eat right bracket token.
4314 // Don't worry about range checking the value here. That's handled by
4315 // the is*() predicates.
4316 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4317 ARM_AM::no_shift, 0, Align,
4320 // If there's a pre-indexing writeback marker, '!', just add it as a token
4322 if (Parser.getTok().is(AsmToken::Exclaim)) {
4323 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4324 Parser.Lex(); // Eat the '!'.
4330 // If we have a '#', it's an immediate offset, else assume it's a register
4331 // offset. Be friendly and also accept a plain integer (without a leading
4332 // hash) for gas compatibility.
4333 if (Parser.getTok().is(AsmToken::Hash) ||
4334 Parser.getTok().is(AsmToken::Dollar) ||
4335 Parser.getTok().is(AsmToken::Integer)) {
4336 if (Parser.getTok().isNot(AsmToken::Integer))
4337 Parser.Lex(); // Eat the '#'.
4338 E = Parser.getTok().getLoc();
4340 bool isNegative = getParser().getTok().is(AsmToken::Minus);
4341 const MCExpr *Offset;
4342 if (getParser().ParseExpression(Offset))
4345 // The expression has to be a constant. Memory references with relocations
4346 // don't come through here, as they use the <label> forms of the relevant
4348 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4350 return Error (E, "constant expression expected");
4352 // If the constant was #-0, represent it as INT32_MIN.
4353 int32_t Val = CE->getValue();
4354 if (isNegative && Val == 0)
4355 CE = MCConstantExpr::Create(INT32_MIN, getContext());
4357 // Now we should have the closing ']'
4358 E = Parser.getTok().getLoc();
4359 if (Parser.getTok().isNot(AsmToken::RBrac))
4360 return Error(E, "']' expected");
4361 Parser.Lex(); // Eat right bracket token.
4363 // Don't worry about range checking the value here. That's handled by
4364 // the is*() predicates.
4365 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4366 ARM_AM::no_shift, 0, 0,
4369 // If there's a pre-indexing writeback marker, '!', just add it as a token
4371 if (Parser.getTok().is(AsmToken::Exclaim)) {
4372 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4373 Parser.Lex(); // Eat the '!'.
4379 // The register offset is optionally preceded by a '+' or '-'
4380 bool isNegative = false;
4381 if (Parser.getTok().is(AsmToken::Minus)) {
4383 Parser.Lex(); // Eat the '-'.
4384 } else if (Parser.getTok().is(AsmToken::Plus)) {
4386 Parser.Lex(); // Eat the '+'.
4389 E = Parser.getTok().getLoc();
4390 int OffsetRegNum = tryParseRegister();
4391 if (OffsetRegNum == -1)
4392 return Error(E, "register expected");
4394 // If there's a shift operator, handle it.
4395 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4396 unsigned ShiftImm = 0;
4397 if (Parser.getTok().is(AsmToken::Comma)) {
4398 Parser.Lex(); // Eat the ','.
4399 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4403 // Now we should have the closing ']'
4404 E = Parser.getTok().getLoc();
4405 if (Parser.getTok().isNot(AsmToken::RBrac))
4406 return Error(E, "']' expected");
4407 Parser.Lex(); // Eat right bracket token.
4409 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4410 ShiftType, ShiftImm, 0, isNegative,
4413 // If there's a pre-indexing writeback marker, '!', just add it as a token
4415 if (Parser.getTok().is(AsmToken::Exclaim)) {
4416 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4417 Parser.Lex(); // Eat the '!'.
4423 /// parseMemRegOffsetShift - one of these two:
4424 /// ( lsl | lsr | asr | ror ) , # shift_amount
4426 /// return true if it parses a shift otherwise it returns false.
4427 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4429 SMLoc Loc = Parser.getTok().getLoc();
4430 const AsmToken &Tok = Parser.getTok();
4431 if (Tok.isNot(AsmToken::Identifier))
4433 StringRef ShiftName = Tok.getString();
4434 if (ShiftName == "lsl" || ShiftName == "LSL" ||
4435 ShiftName == "asl" || ShiftName == "ASL")
4437 else if (ShiftName == "lsr" || ShiftName == "LSR")
4439 else if (ShiftName == "asr" || ShiftName == "ASR")
4441 else if (ShiftName == "ror" || ShiftName == "ROR")
4443 else if (ShiftName == "rrx" || ShiftName == "RRX")
4446 return Error(Loc, "illegal shift operator");
4447 Parser.Lex(); // Eat shift type token.
4449 // rrx stands alone.
4451 if (St != ARM_AM::rrx) {
4452 Loc = Parser.getTok().getLoc();
4453 // A '#' and a shift amount.
4454 const AsmToken &HashTok = Parser.getTok();
4455 if (HashTok.isNot(AsmToken::Hash) &&
4456 HashTok.isNot(AsmToken::Dollar))
4457 return Error(HashTok.getLoc(), "'#' expected");
4458 Parser.Lex(); // Eat hash token.
4461 if (getParser().ParseExpression(Expr))
4463 // Range check the immediate.
4464 // lsl, ror: 0 <= imm <= 31
4465 // lsr, asr: 0 <= imm <= 32
4466 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4468 return Error(Loc, "shift amount must be an immediate");
4469 int64_t Imm = CE->getValue();
4471 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4472 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4473 return Error(Loc, "immediate shift value out of range");
4480 /// parseFPImm - A floating point immediate expression operand.
4481 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4482 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4483 // Anything that can accept a floating point constant as an operand
4484 // needs to go through here, as the regular ParseExpression is
4487 // This routine still creates a generic Immediate operand, containing
4488 // a bitcast of the 64-bit floating point value. The various operands
4489 // that accept floats can check whether the value is valid for them
4490 // via the standard is*() predicates.
4492 SMLoc S = Parser.getTok().getLoc();
4494 if (Parser.getTok().isNot(AsmToken::Hash) &&
4495 Parser.getTok().isNot(AsmToken::Dollar))
4496 return MatchOperand_NoMatch;
4498 // Disambiguate the VMOV forms that can accept an FP immediate.
4499 // vmov.f32 <sreg>, #imm
4500 // vmov.f64 <dreg>, #imm
4501 // vmov.f32 <dreg>, #imm @ vector f32x2
4502 // vmov.f32 <qreg>, #imm @ vector f32x4
4504 // There are also the NEON VMOV instructions which expect an
4505 // integer constant. Make sure we don't try to parse an FPImm
4507 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4508 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4509 if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
4510 TyOp->getToken() != ".f64"))
4511 return MatchOperand_NoMatch;
4513 Parser.Lex(); // Eat the '#'.
4515 // Handle negation, as that still comes through as a separate token.
4516 bool isNegative = false;
4517 if (Parser.getTok().is(AsmToken::Minus)) {
4521 const AsmToken &Tok = Parser.getTok();
4522 SMLoc Loc = Tok.getLoc();
4523 if (Tok.is(AsmToken::Real)) {
4524 APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4525 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4526 // If we had a '-' in front, toggle the sign bit.
4527 IntVal ^= (uint64_t)isNegative << 31;
4528 Parser.Lex(); // Eat the token.
4529 Operands.push_back(ARMOperand::CreateImm(
4530 MCConstantExpr::Create(IntVal, getContext()),
4531 S, Parser.getTok().getLoc()));
4532 return MatchOperand_Success;
4534 // Also handle plain integers. Instructions which allow floating point
4535 // immediates also allow a raw encoded 8-bit value.
4536 if (Tok.is(AsmToken::Integer)) {
4537 int64_t Val = Tok.getIntVal();
4538 Parser.Lex(); // Eat the token.
4539 if (Val > 255 || Val < 0) {
4540 Error(Loc, "encoded floating point value out of range");
4541 return MatchOperand_ParseFail;
4543 double RealVal = ARM_AM::getFPImmFloat(Val);
4544 Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue();
4545 Operands.push_back(ARMOperand::CreateImm(
4546 MCConstantExpr::Create(Val, getContext()), S,
4547 Parser.getTok().getLoc()));
4548 return MatchOperand_Success;
4551 Error(Loc, "invalid floating point immediate");
4552 return MatchOperand_ParseFail;
4555 /// Parse a arm instruction operand. For now this parses the operand regardless
4556 /// of the mnemonic.
4557 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4558 StringRef Mnemonic) {
4561 // Check if the current operand has a custom associated parser, if so, try to
4562 // custom parse the operand, or fallback to the general approach.
4563 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4564 if (ResTy == MatchOperand_Success)
4566 // If there wasn't a custom match, try the generic matcher below. Otherwise,
4567 // there was a match, but an error occurred, in which case, just return that
4568 // the operand parsing failed.
4569 if (ResTy == MatchOperand_ParseFail)
4572 switch (getLexer().getKind()) {
4574 Error(Parser.getTok().getLoc(), "unexpected token in operand");
4576 case AsmToken::Identifier: {
4577 if (!tryParseRegisterWithWriteBack(Operands))
4579 int Res = tryParseShiftRegister(Operands);
4580 if (Res == 0) // success
4582 else if (Res == -1) // irrecoverable error
4584 // If this is VMRS, check for the apsr_nzcv operand.
4585 if (Mnemonic == "vmrs" &&
4586 Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4587 S = Parser.getTok().getLoc();
4589 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4593 // Fall though for the Identifier case that is not a register or a
4596 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
4597 case AsmToken::Integer: // things like 1f and 2b as a branch targets
4598 case AsmToken::String: // quoted label names.
4599 case AsmToken::Dot: { // . as a branch target
4600 // This was not a register so parse other operands that start with an
4601 // identifier (like labels) as expressions and create them as immediates.
4602 const MCExpr *IdVal;
4603 S = Parser.getTok().getLoc();
4604 if (getParser().ParseExpression(IdVal))
4606 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4607 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4610 case AsmToken::LBrac:
4611 return parseMemory(Operands);
4612 case AsmToken::LCurly:
4613 return parseRegisterList(Operands);
4614 case AsmToken::Dollar:
4615 case AsmToken::Hash: {
4616 // #42 -> immediate.
4617 S = Parser.getTok().getLoc();
4620 if (Parser.getTok().isNot(AsmToken::Colon)) {
4621 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4622 const MCExpr *ImmVal;
4623 if (getParser().ParseExpression(ImmVal))
4625 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4627 int32_t Val = CE->getValue();
4628 if (isNegative && Val == 0)
4629 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4631 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4632 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4635 // w/ a ':' after the '#', it's just like a plain ':'.
4638 case AsmToken::Colon: {
4639 // ":lower16:" and ":upper16:" expression prefixes
4640 // FIXME: Check it's an expression prefix,
4641 // e.g. (FOO - :lower16:BAR) isn't legal.
4642 ARMMCExpr::VariantKind RefKind;
4643 if (parsePrefix(RefKind))
4646 const MCExpr *SubExprVal;
4647 if (getParser().ParseExpression(SubExprVal))
4650 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4652 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4653 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4659 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4660 // :lower16: and :upper16:.
4661 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4662 RefKind = ARMMCExpr::VK_ARM_None;
4664 // :lower16: and :upper16: modifiers
4665 assert(getLexer().is(AsmToken::Colon) && "expected a :");
4666 Parser.Lex(); // Eat ':'
4668 if (getLexer().isNot(AsmToken::Identifier)) {
4669 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4673 StringRef IDVal = Parser.getTok().getIdentifier();
4674 if (IDVal == "lower16") {
4675 RefKind = ARMMCExpr::VK_ARM_LO16;
4676 } else if (IDVal == "upper16") {
4677 RefKind = ARMMCExpr::VK_ARM_HI16;
4679 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4684 if (getLexer().isNot(AsmToken::Colon)) {
4685 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4688 Parser.Lex(); // Eat the last ':'
4692 /// \brief Given a mnemonic, split out possible predication code and carry
4693 /// setting letters to form a canonical mnemonic and flags.
4695 // FIXME: Would be nice to autogen this.
4696 // FIXME: This is a bit of a maze of special cases.
4697 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4698 unsigned &PredicationCode,
4700 unsigned &ProcessorIMod,
4701 StringRef &ITMask) {
4702 PredicationCode = ARMCC::AL;
4703 CarrySetting = false;
4706 // Ignore some mnemonics we know aren't predicated forms.
4708 // FIXME: Would be nice to autogen this.
4709 if ((Mnemonic == "movs" && isThumb()) ||
4710 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
4711 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
4712 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
4713 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
4714 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
4715 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
4716 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4717 Mnemonic == "fmuls")
4720 // First, split out any predication code. Ignore mnemonics we know aren't
4721 // predicated but do have a carry-set and so weren't caught above.
4722 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4723 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4724 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4725 Mnemonic != "sbcs" && Mnemonic != "rscs") {
4726 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4727 .Case("eq", ARMCC::EQ)
4728 .Case("ne", ARMCC::NE)
4729 .Case("hs", ARMCC::HS)
4730 .Case("cs", ARMCC::HS)
4731 .Case("lo", ARMCC::LO)
4732 .Case("cc", ARMCC::LO)
4733 .Case("mi", ARMCC::MI)
4734 .Case("pl", ARMCC::PL)
4735 .Case("vs", ARMCC::VS)
4736 .Case("vc", ARMCC::VC)
4737 .Case("hi", ARMCC::HI)
4738 .Case("ls", ARMCC::LS)
4739 .Case("ge", ARMCC::GE)
4740 .Case("lt", ARMCC::LT)
4741 .Case("gt", ARMCC::GT)
4742 .Case("le", ARMCC::LE)
4743 .Case("al", ARMCC::AL)
4746 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4747 PredicationCode = CC;
4751 // Next, determine if we have a carry setting bit. We explicitly ignore all
4752 // the instructions we know end in 's'.
4753 if (Mnemonic.endswith("s") &&
4754 !(Mnemonic == "cps" || Mnemonic == "mls" ||
4755 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4756 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4757 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4758 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4759 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4760 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4761 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
4762 Mnemonic == "vfms" || Mnemonic == "vfnms" ||
4763 (Mnemonic == "movs" && isThumb()))) {
4764 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4765 CarrySetting = true;
4768 // The "cps" instruction can have a interrupt mode operand which is glued into
4769 // the mnemonic. Check if this is the case, split it and parse the imod op
4770 if (Mnemonic.startswith("cps")) {
4771 // Split out any imod code.
4773 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4774 .Case("ie", ARM_PROC::IE)
4775 .Case("id", ARM_PROC::ID)
4778 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4779 ProcessorIMod = IMod;
4783 // The "it" instruction has the condition mask on the end of the mnemonic.
4784 if (Mnemonic.startswith("it")) {
4785 ITMask = Mnemonic.slice(2, Mnemonic.size());
4786 Mnemonic = Mnemonic.slice(0, 2);
4792 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
4793 /// inclusion of carry set or predication code operands.
4795 // FIXME: It would be nice to autogen this.
4797 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
4798 bool &CanAcceptPredicationCode) {
4799 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4800 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4801 Mnemonic == "add" || Mnemonic == "adc" ||
4802 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4803 Mnemonic == "orr" || Mnemonic == "mvn" ||
4804 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4805 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4806 Mnemonic == "vfm" || Mnemonic == "vfnm" ||
4807 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4808 Mnemonic == "mla" || Mnemonic == "smlal" ||
4809 Mnemonic == "umlal" || Mnemonic == "umull"))) {
4810 CanAcceptCarrySet = true;
4812 CanAcceptCarrySet = false;
4814 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
4815 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
4816 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
4817 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
4818 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
4819 (Mnemonic == "clrex" && !isThumb()) ||
4820 (Mnemonic == "nop" && isThumbOne()) ||
4821 ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" ||
4822 Mnemonic == "ldc2" || Mnemonic == "ldc2l" ||
4823 Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) ||
4824 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
4826 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
4827 CanAcceptPredicationCode = false;
4829 CanAcceptPredicationCode = true;
4832 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
4833 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
4834 CanAcceptPredicationCode = false;
4838 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4839 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4840 // FIXME: This is all horribly hacky. We really need a better way to deal
4841 // with optional operands like this in the matcher table.
4843 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4844 // another does not. Specifically, the MOVW instruction does not. So we
4845 // special case it here and remove the defaulted (non-setting) cc_out
4846 // operand if that's the instruction we're trying to match.
4848 // We do this as post-processing of the explicit operands rather than just
4849 // conditionally adding the cc_out in the first place because we need
4850 // to check the type of the parsed immediate operand.
4851 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4852 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4853 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4854 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4857 // Register-register 'add' for thumb does not have a cc_out operand
4858 // when there are only two register operands.
4859 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4860 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4861 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4862 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4864 // Register-register 'add' for thumb does not have a cc_out operand
4865 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4866 // have to check the immediate range here since Thumb2 has a variant
4867 // that can handle a different range and has a cc_out operand.
4868 if (((isThumb() && Mnemonic == "add") ||
4869 (isThumbTwo() && Mnemonic == "sub")) &&
4870 Operands.size() == 6 &&
4871 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4872 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4873 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4874 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4875 ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
4876 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4878 // For Thumb2, add/sub immediate does not have a cc_out operand for the
4879 // imm0_4095 variant. That's the least-preferred variant when
4880 // selecting via the generic "add" mnemonic, so to know that we
4881 // should remove the cc_out operand, we have to explicitly check that
4882 // it's not one of the other variants. Ugh.
4883 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4884 Operands.size() == 6 &&
4885 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4886 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4887 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4888 // Nest conditions rather than one big 'if' statement for readability.
4890 // If either register is a high reg, it's either one of the SP
4891 // variants (handled above) or a 32-bit encoding, so we just
4892 // check against T3. If the second register is the PC, this is an
4893 // alternate form of ADR, which uses encoding T4, so check for that too.
4894 if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4895 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
4896 static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
4897 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
4899 // If both registers are low, we're in an IT block, and the immediate is
4900 // in range, we should use encoding T1 instead, which has a cc_out.
4902 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4903 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4904 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
4907 // Otherwise, we use encoding T4, which does not have a cc_out
4912 // The thumb2 multiply instruction doesn't have a CCOut register, so
4913 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
4914 // use the 16-bit encoding or not.
4915 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
4916 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4917 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4918 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4919 static_cast<ARMOperand*>(Operands[5])->isReg() &&
4920 // If the registers aren't low regs, the destination reg isn't the
4921 // same as one of the source regs, or the cc_out operand is zero
4922 // outside of an IT block, we have to use the 32-bit encoding, so
4923 // remove the cc_out operand.
4924 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4925 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4926 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
4928 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4929 static_cast<ARMOperand*>(Operands[5])->getReg() &&
4930 static_cast<ARMOperand*>(Operands[3])->getReg() !=
4931 static_cast<ARMOperand*>(Operands[4])->getReg())))
4934 // Also check the 'mul' syntax variant that doesn't specify an explicit
4935 // destination register.
4936 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
4937 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4938 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4939 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4940 // If the registers aren't low regs or the cc_out operand is zero
4941 // outside of an IT block, we have to use the 32-bit encoding, so
4942 // remove the cc_out operand.
4943 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4944 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4950 // Register-register 'add/sub' for thumb does not have a cc_out operand
4951 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
4952 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
4953 // right, this will result in better diagnostics (which operand is off)
4955 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
4956 (Operands.size() == 5 || Operands.size() == 6) &&
4957 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4958 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4959 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4960 (static_cast<ARMOperand*>(Operands[4])->isImm() ||
4961 (Operands.size() == 6 &&
4962 static_cast<ARMOperand*>(Operands[5])->isImm())))
4968 static bool isDataTypeToken(StringRef Tok) {
4969 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
4970 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
4971 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
4972 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
4973 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
4974 Tok == ".f" || Tok == ".d";
4977 // FIXME: This bit should probably be handled via an explicit match class
4978 // in the .td files that matches the suffix instead of having it be
4979 // a literal string token the way it is now.
4980 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
4981 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
4984 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features);
4985 /// Parse an arm instruction mnemonic followed by its operands.
4986 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
4987 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4988 // Apply mnemonic aliases before doing anything else, as the destination
4989 // mnemnonic may include suffices and we want to handle them normally.
4990 // The generic tblgen'erated code does this later, at the start of
4991 // MatchInstructionImpl(), but that's too late for aliases that include
4992 // any sort of suffix.
4993 unsigned AvailableFeatures = getAvailableFeatures();
4994 applyMnemonicAliases(Name, AvailableFeatures);
4996 // First check for the ARM-specific .req directive.
4997 if (Parser.getTok().is(AsmToken::Identifier) &&
4998 Parser.getTok().getIdentifier() == ".req") {
4999 parseDirectiveReq(Name, NameLoc);
5000 // We always return 'error' for this, as we're done with this
5001 // statement and don't need to match the 'instruction."
5005 // Create the leading tokens for the mnemonic, split by '.' characters.
5006 size_t Start = 0, Next = Name.find('.');
5007 StringRef Mnemonic = Name.slice(Start, Next);
5009 // Split out the predication code and carry setting flag from the mnemonic.
5010 unsigned PredicationCode;
5011 unsigned ProcessorIMod;
5014 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5015 ProcessorIMod, ITMask);
5017 // In Thumb1, only the branch (B) instruction can be predicated.
5018 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5019 Parser.EatToEndOfStatement();
5020 return Error(NameLoc, "conditional execution not supported in Thumb1");
5023 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5025 // Handle the IT instruction ITMask. Convert it to a bitmask. This
5026 // is the mask as it will be for the IT encoding if the conditional
5027 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5028 // where the conditional bit0 is zero, the instruction post-processing
5029 // will adjust the mask accordingly.
5030 if (Mnemonic == "it") {
5031 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5032 if (ITMask.size() > 3) {
5033 Parser.EatToEndOfStatement();
5034 return Error(Loc, "too many conditions on IT instruction");
5037 for (unsigned i = ITMask.size(); i != 0; --i) {
5038 char pos = ITMask[i - 1];
5039 if (pos != 't' && pos != 'e') {
5040 Parser.EatToEndOfStatement();
5041 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5044 if (ITMask[i - 1] == 't')
5047 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5050 // FIXME: This is all a pretty gross hack. We should automatically handle
5051 // optional operands like this via tblgen.
5053 // Next, add the CCOut and ConditionCode operands, if needed.
5055 // For mnemonics which can ever incorporate a carry setting bit or predication
5056 // code, our matching model involves us always generating CCOut and
5057 // ConditionCode operands to match the mnemonic "as written" and then we let
5058 // the matcher deal with finding the right instruction or generating an
5059 // appropriate error.
5060 bool CanAcceptCarrySet, CanAcceptPredicationCode;
5061 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
5063 // If we had a carry-set on an instruction that can't do that, issue an
5065 if (!CanAcceptCarrySet && CarrySetting) {
5066 Parser.EatToEndOfStatement();
5067 return Error(NameLoc, "instruction '" + Mnemonic +
5068 "' can not set flags, but 's' suffix specified");
5070 // If we had a predication code on an instruction that can't do that, issue an
5072 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5073 Parser.EatToEndOfStatement();
5074 return Error(NameLoc, "instruction '" + Mnemonic +
5075 "' is not predicable, but condition code specified");
5078 // Add the carry setting operand, if necessary.
5079 if (CanAcceptCarrySet) {
5080 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5081 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5085 // Add the predication code operand, if necessary.
5086 if (CanAcceptPredicationCode) {
5087 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5089 Operands.push_back(ARMOperand::CreateCondCode(
5090 ARMCC::CondCodes(PredicationCode), Loc));
5093 // Add the processor imod operand, if necessary.
5094 if (ProcessorIMod) {
5095 Operands.push_back(ARMOperand::CreateImm(
5096 MCConstantExpr::Create(ProcessorIMod, getContext()),
5100 // Add the remaining tokens in the mnemonic.
5101 while (Next != StringRef::npos) {
5103 Next = Name.find('.', Start + 1);
5104 StringRef ExtraToken = Name.slice(Start, Next);
5106 // Some NEON instructions have an optional datatype suffix that is
5107 // completely ignored. Check for that.
5108 if (isDataTypeToken(ExtraToken) &&
5109 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5112 if (ExtraToken != ".n") {
5113 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5114 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5118 // Read the remaining operands.
5119 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5120 // Read the first operand.
5121 if (parseOperand(Operands, Mnemonic)) {
5122 Parser.EatToEndOfStatement();
5126 while (getLexer().is(AsmToken::Comma)) {
5127 Parser.Lex(); // Eat the comma.
5129 // Parse and remember the operand.
5130 if (parseOperand(Operands, Mnemonic)) {
5131 Parser.EatToEndOfStatement();
5137 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5138 SMLoc Loc = getLexer().getLoc();
5139 Parser.EatToEndOfStatement();
5140 return Error(Loc, "unexpected token in argument list");
5143 Parser.Lex(); // Consume the EndOfStatement
5145 // Some instructions, mostly Thumb, have forms for the same mnemonic that
5146 // do and don't have a cc_out optional-def operand. With some spot-checks
5147 // of the operand list, we can figure out which variant we're trying to
5148 // parse and adjust accordingly before actually matching. We shouldn't ever
5149 // try to remove a cc_out operand that was explicitly set on the the
5150 // mnemonic, of course (CarrySetting == true). Reason number #317 the
5151 // table driven matcher doesn't fit well with the ARM instruction set.
5152 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5153 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5154 Operands.erase(Operands.begin() + 1);
5158 // ARM mode 'blx' need special handling, as the register operand version
5159 // is predicable, but the label operand version is not. So, we can't rely
5160 // on the Mnemonic based checking to correctly figure out when to put
5161 // a k_CondCode operand in the list. If we're trying to match the label
5162 // version, remove the k_CondCode operand here.
5163 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5164 static_cast<ARMOperand*>(Operands[2])->isImm()) {
5165 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5166 Operands.erase(Operands.begin() + 1);
5170 // The vector-compare-to-zero instructions have a literal token "#0" at
5171 // the end that comes to here as an immediate operand. Convert it to a
5172 // token to play nicely with the matcher.
5173 if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
5174 Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
5175 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5176 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
5177 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5178 if (CE && CE->getValue() == 0) {
5179 Operands.erase(Operands.begin() + 5);
5180 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5184 // VCMP{E} does the same thing, but with a different operand count.
5185 if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 &&
5186 static_cast<ARMOperand*>(Operands[4])->isImm()) {
5187 ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]);
5188 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5189 if (CE && CE->getValue() == 0) {
5190 Operands.erase(Operands.begin() + 4);
5191 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5195 // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
5196 // end. Convert it to a token here. Take care not to convert those
5197 // that should hit the Thumb2 encoding.
5198 if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
5199 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5200 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5201 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5202 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
5203 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5204 if (CE && CE->getValue() == 0 &&
5206 // The cc_out operand matches the IT block.
5207 ((inITBlock() != CarrySetting) &&
5208 // Neither register operand is a high register.
5209 (isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
5210 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()))))){
5211 Operands.erase(Operands.begin() + 5);
5212 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5220 // Validate context-sensitive operand constraints.
5222 // return 'true' if register list contains non-low GPR registers,
5223 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5224 // 'containsReg' to true.
5225 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5226 unsigned HiReg, bool &containsReg) {
5227 containsReg = false;
5228 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5229 unsigned OpReg = Inst.getOperand(i).getReg();
5232 // Anything other than a low register isn't legal here.
5233 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5239 // Check if the specified regisgter is in the register list of the inst,
5240 // starting at the indicated operand number.
5241 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5242 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5243 unsigned OpReg = Inst.getOperand(i).getReg();
5250 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around
5251 // the ARMInsts array) instead. Getting that here requires awkward
5252 // API changes, though. Better way?
5254 extern const MCInstrDesc ARMInsts[];
5256 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
5257 return ARMInsts[Opcode];
5260 // FIXME: We would really like to be able to tablegen'erate this.
5262 validateInstruction(MCInst &Inst,
5263 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5264 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
5265 SMLoc Loc = Operands[0]->getStartLoc();
5266 // Check the IT block state first.
5267 // NOTE: BKPT instruction has the interesting property of being
5268 // allowed in IT blocks, but not being predicable. It just always
5270 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT &&
5271 Inst.getOpcode() != ARM::BKPT) {
5273 if (ITState.FirstCond)
5274 ITState.FirstCond = false;
5276 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5277 // The instruction must be predicable.
5278 if (!MCID.isPredicable())
5279 return Error(Loc, "instructions in IT block must be predicable");
5280 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5281 unsigned ITCond = bit ? ITState.Cond :
5282 ARMCC::getOppositeCondition(ITState.Cond);
5283 if (Cond != ITCond) {
5284 // Find the condition code Operand to get its SMLoc information.
5286 for (unsigned i = 1; i < Operands.size(); ++i)
5287 if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
5288 CondLoc = Operands[i]->getStartLoc();
5289 return Error(CondLoc, "incorrect condition in IT block; got '" +
5290 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5291 "', but expected '" +
5292 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5294 // Check for non-'al' condition codes outside of the IT block.
5295 } else if (isThumbTwo() && MCID.isPredicable() &&
5296 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5297 ARMCC::AL && Inst.getOpcode() != ARM::tB &&
5298 Inst.getOpcode() != ARM::t2B)
5299 return Error(Loc, "predicated instructions must be in IT block");
5301 switch (Inst.getOpcode()) {
5304 case ARM::LDRD_POST:
5306 // Rt2 must be Rt + 1.
5307 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5308 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5310 return Error(Operands[3]->getStartLoc(),
5311 "destination operands must be sequential");
5315 // Rt2 must be Rt + 1.
5316 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5317 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5319 return Error(Operands[3]->getStartLoc(),
5320 "source operands must be sequential");
5324 case ARM::STRD_POST:
5326 // Rt2 must be Rt + 1.
5327 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5328 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5330 return Error(Operands[3]->getStartLoc(),
5331 "source operands must be sequential");
5336 // width must be in range [1, 32-lsb]
5337 unsigned lsb = Inst.getOperand(2).getImm();
5338 unsigned widthm1 = Inst.getOperand(3).getImm();
5339 if (widthm1 >= 32 - lsb)
5340 return Error(Operands[5]->getStartLoc(),
5341 "bitfield width must be in range [1,32-lsb]");
5345 // If we're parsing Thumb2, the .w variant is available and handles
5346 // most cases that are normally illegal for a Thumb1 LDM
5347 // instruction. We'll make the transformation in processInstruction()
5350 // Thumb LDM instructions are writeback iff the base register is not
5351 // in the register list.
5352 unsigned Rn = Inst.getOperand(0).getReg();
5353 bool hasWritebackToken =
5354 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5355 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5356 bool listContainsBase;
5357 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
5358 return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
5359 "registers must be in range r0-r7");
5360 // If we should have writeback, then there should be a '!' token.
5361 if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
5362 return Error(Operands[2]->getStartLoc(),
5363 "writeback operator '!' expected");
5364 // If we should not have writeback, there must not be a '!'. This is
5365 // true even for the 32-bit wide encodings.
5366 if (listContainsBase && hasWritebackToken)
5367 return Error(Operands[3]->getStartLoc(),
5368 "writeback operator '!' not allowed when base register "
5369 "in register list");
5373 case ARM::t2LDMIA_UPD: {
5374 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5375 return Error(Operands[4]->getStartLoc(),
5376 "writeback operator '!' not allowed when base register "
5377 "in register list");
5380 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5381 // so only issue a diagnostic for thumb1. The instructions will be
5382 // switched to the t2 encodings in processInstruction() if necessary.
5384 bool listContainsBase;
5385 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
5387 return Error(Operands[2]->getStartLoc(),
5388 "registers must be in range r0-r7 or pc");
5392 bool listContainsBase;
5393 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
5395 return Error(Operands[2]->getStartLoc(),
5396 "registers must be in range r0-r7 or lr");
5399 case ARM::tSTMIA_UPD: {
5400 bool listContainsBase;
5401 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
5402 return Error(Operands[4]->getStartLoc(),
5403 "registers must be in range r0-r7");
5406 case ARM::tADDrSP: {
5407 // If the non-SP source operand and the destination operand are not the
5408 // same, we need thumb2 (for the wide encoding), or we have an error.
5409 if (!isThumbTwo() &&
5410 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5411 return Error(Operands[4]->getStartLoc(),
5412 "source register must be the same as destination");
5421 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5423 default: llvm_unreachable("unexpected opcode!");
5425 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5426 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5427 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5428 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5429 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5430 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5431 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
5432 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5433 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5436 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5437 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5438 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5439 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5440 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5442 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5443 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5444 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5445 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5446 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5448 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
5449 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5450 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5451 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5452 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5455 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5456 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5457 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5458 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5459 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5460 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5461 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5462 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5463 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5464 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5465 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
5466 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5467 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5468 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5469 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5472 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5473 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5474 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5475 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5476 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5477 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5478 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5479 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5480 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5481 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5482 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5483 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5484 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
5485 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5486 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5487 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
5488 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5489 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5492 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5493 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5494 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5495 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5496 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5497 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5498 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5499 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5500 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5501 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5502 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
5503 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5504 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5505 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5506 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5509 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5510 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5511 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5512 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5513 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5514 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5515 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5516 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5517 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5518 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5519 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5520 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5521 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
5522 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5523 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5524 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
5525 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5526 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5530 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
5532 default: llvm_unreachable("unexpected opcode!");
5534 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5535 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5536 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5537 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5538 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5539 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5540 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
5541 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5542 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5545 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5546 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5547 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5548 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5549 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5550 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5551 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5552 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5553 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5554 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5555 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
5556 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5557 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5558 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5559 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5562 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5563 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5564 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5565 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5566 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5567 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5568 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5569 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5570 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5571 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5572 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5573 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5574 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
5575 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5576 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5577 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5578 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5579 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5582 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5583 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5584 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5585 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5586 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5587 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5588 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5589 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5590 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5591 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5592 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
5593 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5594 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5595 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5596 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5599 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5600 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5601 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5602 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5603 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5604 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5605 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5606 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5607 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5608 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5609 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5610 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5611 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
5612 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5613 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5614 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
5615 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5616 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
5619 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5620 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5621 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5622 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
5623 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5624 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5625 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5626 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5627 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5628 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5629 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
5630 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5631 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5632 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5633 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5636 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5637 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5638 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5639 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5640 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5641 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5642 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5643 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5644 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5645 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
5646 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
5647 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5648 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
5649 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
5650 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
5651 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
5652 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
5653 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
5656 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5657 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5658 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5659 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5660 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5661 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5662 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5663 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5664 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5665 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5666 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5667 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5668 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
5669 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
5670 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
5671 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
5672 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
5673 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
5678 processInstruction(MCInst &Inst,
5679 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5680 switch (Inst.getOpcode()) {
5681 // Aliases for alternate PC+imm syntax of LDR instructions.
5682 case ARM::t2LDRpcrel:
5683 Inst.setOpcode(ARM::t2LDRpci);
5685 case ARM::t2LDRBpcrel:
5686 Inst.setOpcode(ARM::t2LDRBpci);
5688 case ARM::t2LDRHpcrel:
5689 Inst.setOpcode(ARM::t2LDRHpci);
5691 case ARM::t2LDRSBpcrel:
5692 Inst.setOpcode(ARM::t2LDRSBpci);
5694 case ARM::t2LDRSHpcrel:
5695 Inst.setOpcode(ARM::t2LDRSHpci);
5697 // Handle NEON VST complex aliases.
5698 case ARM::VST1LNdWB_register_Asm_8:
5699 case ARM::VST1LNdWB_register_Asm_16:
5700 case ARM::VST1LNdWB_register_Asm_32: {
5702 // Shuffle the operands around so the lane index operand is in the
5705 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5706 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5707 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5708 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5709 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5710 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5711 TmpInst.addOperand(Inst.getOperand(1)); // lane
5712 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5713 TmpInst.addOperand(Inst.getOperand(6));
5718 case ARM::VST2LNdWB_register_Asm_8:
5719 case ARM::VST2LNdWB_register_Asm_16:
5720 case ARM::VST2LNdWB_register_Asm_32:
5721 case ARM::VST2LNqWB_register_Asm_16:
5722 case ARM::VST2LNqWB_register_Asm_32: {
5724 // Shuffle the operands around so the lane index operand is in the
5727 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5728 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5729 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5730 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5731 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5732 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5733 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5735 TmpInst.addOperand(Inst.getOperand(1)); // lane
5736 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5737 TmpInst.addOperand(Inst.getOperand(6));
5742 case ARM::VST3LNdWB_register_Asm_8:
5743 case ARM::VST3LNdWB_register_Asm_16:
5744 case ARM::VST3LNdWB_register_Asm_32:
5745 case ARM::VST3LNqWB_register_Asm_16:
5746 case ARM::VST3LNqWB_register_Asm_32: {
5748 // Shuffle the operands around so the lane index operand is in the
5751 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5752 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5753 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5754 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5755 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5756 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5757 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5759 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5761 TmpInst.addOperand(Inst.getOperand(1)); // lane
5762 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5763 TmpInst.addOperand(Inst.getOperand(6));
5768 case ARM::VST4LNdWB_register_Asm_8:
5769 case ARM::VST4LNdWB_register_Asm_16:
5770 case ARM::VST4LNdWB_register_Asm_32:
5771 case ARM::VST4LNqWB_register_Asm_16:
5772 case ARM::VST4LNqWB_register_Asm_32: {
5774 // Shuffle the operands around so the lane index operand is in the
5777 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5778 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5779 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5780 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5781 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5782 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5783 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5785 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5787 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5789 TmpInst.addOperand(Inst.getOperand(1)); // lane
5790 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5791 TmpInst.addOperand(Inst.getOperand(6));
5796 case ARM::VST1LNdWB_fixed_Asm_8:
5797 case ARM::VST1LNdWB_fixed_Asm_16:
5798 case ARM::VST1LNdWB_fixed_Asm_32: {
5800 // Shuffle the operands around so the lane index operand is in the
5803 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5804 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5805 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5806 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5807 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5808 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5809 TmpInst.addOperand(Inst.getOperand(1)); // lane
5810 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5811 TmpInst.addOperand(Inst.getOperand(5));
5816 case ARM::VST2LNdWB_fixed_Asm_8:
5817 case ARM::VST2LNdWB_fixed_Asm_16:
5818 case ARM::VST2LNdWB_fixed_Asm_32:
5819 case ARM::VST2LNqWB_fixed_Asm_16:
5820 case ARM::VST2LNqWB_fixed_Asm_32: {
5822 // Shuffle the operands around so the lane index operand is in the
5825 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5826 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5827 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5828 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5829 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5830 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5831 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5833 TmpInst.addOperand(Inst.getOperand(1)); // lane
5834 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5835 TmpInst.addOperand(Inst.getOperand(5));
5840 case ARM::VST3LNdWB_fixed_Asm_8:
5841 case ARM::VST3LNdWB_fixed_Asm_16:
5842 case ARM::VST3LNdWB_fixed_Asm_32:
5843 case ARM::VST3LNqWB_fixed_Asm_16:
5844 case ARM::VST3LNqWB_fixed_Asm_32: {
5846 // Shuffle the operands around so the lane index operand is in the
5849 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5850 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5851 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5852 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5853 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5854 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5855 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5857 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5859 TmpInst.addOperand(Inst.getOperand(1)); // lane
5860 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5861 TmpInst.addOperand(Inst.getOperand(5));
5866 case ARM::VST4LNdWB_fixed_Asm_8:
5867 case ARM::VST4LNdWB_fixed_Asm_16:
5868 case ARM::VST4LNdWB_fixed_Asm_32:
5869 case ARM::VST4LNqWB_fixed_Asm_16:
5870 case ARM::VST4LNqWB_fixed_Asm_32: {
5872 // Shuffle the operands around so the lane index operand is in the
5875 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5876 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5877 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5878 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5879 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5880 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5881 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5883 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5885 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5887 TmpInst.addOperand(Inst.getOperand(1)); // lane
5888 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5889 TmpInst.addOperand(Inst.getOperand(5));
5894 case ARM::VST1LNdAsm_8:
5895 case ARM::VST1LNdAsm_16:
5896 case ARM::VST1LNdAsm_32: {
5898 // Shuffle the operands around so the lane index operand is in the
5901 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5902 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5903 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5904 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5905 TmpInst.addOperand(Inst.getOperand(1)); // lane
5906 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5907 TmpInst.addOperand(Inst.getOperand(5));
5912 case ARM::VST2LNdAsm_8:
5913 case ARM::VST2LNdAsm_16:
5914 case ARM::VST2LNdAsm_32:
5915 case ARM::VST2LNqAsm_16:
5916 case ARM::VST2LNqAsm_32: {
5918 // Shuffle the operands around so the lane index operand is in the
5921 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5922 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5923 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5924 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5925 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5927 TmpInst.addOperand(Inst.getOperand(1)); // lane
5928 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5929 TmpInst.addOperand(Inst.getOperand(5));
5934 case ARM::VST3LNdAsm_8:
5935 case ARM::VST3LNdAsm_16:
5936 case ARM::VST3LNdAsm_32:
5937 case ARM::VST3LNqAsm_16:
5938 case ARM::VST3LNqAsm_32: {
5940 // Shuffle the operands around so the lane index operand is in the
5943 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5944 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5945 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5946 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5947 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5949 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5951 TmpInst.addOperand(Inst.getOperand(1)); // lane
5952 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5953 TmpInst.addOperand(Inst.getOperand(5));
5958 case ARM::VST4LNdAsm_8:
5959 case ARM::VST4LNdAsm_16:
5960 case ARM::VST4LNdAsm_32:
5961 case ARM::VST4LNqAsm_16:
5962 case ARM::VST4LNqAsm_32: {
5964 // Shuffle the operands around so the lane index operand is in the
5967 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5968 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5969 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5970 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5971 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5973 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5975 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5977 TmpInst.addOperand(Inst.getOperand(1)); // lane
5978 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5979 TmpInst.addOperand(Inst.getOperand(5));
5984 // Handle NEON VLD complex aliases.
5985 case ARM::VLD1LNdWB_register_Asm_8:
5986 case ARM::VLD1LNdWB_register_Asm_16:
5987 case ARM::VLD1LNdWB_register_Asm_32: {
5989 // Shuffle the operands around so the lane index operand is in the
5992 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
5993 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5994 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5995 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5996 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5997 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5998 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5999 TmpInst.addOperand(Inst.getOperand(1)); // lane
6000 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6001 TmpInst.addOperand(Inst.getOperand(6));
6006 case ARM::VLD2LNdWB_register_Asm_8:
6007 case ARM::VLD2LNdWB_register_Asm_16:
6008 case ARM::VLD2LNdWB_register_Asm_32:
6009 case ARM::VLD2LNqWB_register_Asm_16:
6010 case ARM::VLD2LNqWB_register_Asm_32: {
6012 // Shuffle the operands around so the lane index operand is in the
6015 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6016 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6017 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6019 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6020 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6021 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6022 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6023 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6024 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6026 TmpInst.addOperand(Inst.getOperand(1)); // lane
6027 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6028 TmpInst.addOperand(Inst.getOperand(6));
6033 case ARM::VLD3LNdWB_register_Asm_8:
6034 case ARM::VLD3LNdWB_register_Asm_16:
6035 case ARM::VLD3LNdWB_register_Asm_32:
6036 case ARM::VLD3LNqWB_register_Asm_16:
6037 case ARM::VLD3LNqWB_register_Asm_32: {
6039 // Shuffle the operands around so the lane index operand is in the
6042 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6043 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6044 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6046 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6048 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6049 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6050 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6051 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6052 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6053 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6055 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6057 TmpInst.addOperand(Inst.getOperand(1)); // lane
6058 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6059 TmpInst.addOperand(Inst.getOperand(6));
6064 case ARM::VLD4LNdWB_register_Asm_8:
6065 case ARM::VLD4LNdWB_register_Asm_16:
6066 case ARM::VLD4LNdWB_register_Asm_32:
6067 case ARM::VLD4LNqWB_register_Asm_16:
6068 case ARM::VLD4LNqWB_register_Asm_32: {
6070 // Shuffle the operands around so the lane index operand is in the
6073 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6074 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6075 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6077 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6079 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6081 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6082 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6083 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6084 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6085 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6086 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6088 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6090 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6092 TmpInst.addOperand(Inst.getOperand(1)); // lane
6093 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6094 TmpInst.addOperand(Inst.getOperand(6));
6099 case ARM::VLD1LNdWB_fixed_Asm_8:
6100 case ARM::VLD1LNdWB_fixed_Asm_16:
6101 case ARM::VLD1LNdWB_fixed_Asm_32: {
6103 // Shuffle the operands around so the lane index operand is in the
6106 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6107 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6108 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6109 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6110 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6111 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6112 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6113 TmpInst.addOperand(Inst.getOperand(1)); // lane
6114 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6115 TmpInst.addOperand(Inst.getOperand(5));
6120 case ARM::VLD2LNdWB_fixed_Asm_8:
6121 case ARM::VLD2LNdWB_fixed_Asm_16:
6122 case ARM::VLD2LNdWB_fixed_Asm_32:
6123 case ARM::VLD2LNqWB_fixed_Asm_16:
6124 case ARM::VLD2LNqWB_fixed_Asm_32: {
6126 // Shuffle the operands around so the lane index operand is in the
6129 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6130 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6131 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6133 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6134 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6135 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6136 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6137 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6138 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6140 TmpInst.addOperand(Inst.getOperand(1)); // lane
6141 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6142 TmpInst.addOperand(Inst.getOperand(5));
6147 case ARM::VLD3LNdWB_fixed_Asm_8:
6148 case ARM::VLD3LNdWB_fixed_Asm_16:
6149 case ARM::VLD3LNdWB_fixed_Asm_32:
6150 case ARM::VLD3LNqWB_fixed_Asm_16:
6151 case ARM::VLD3LNqWB_fixed_Asm_32: {
6153 // Shuffle the operands around so the lane index operand is in the
6156 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6157 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6158 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6160 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6162 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6163 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6164 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6165 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6166 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6167 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6169 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6171 TmpInst.addOperand(Inst.getOperand(1)); // lane
6172 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6173 TmpInst.addOperand(Inst.getOperand(5));
6178 case ARM::VLD4LNdWB_fixed_Asm_8:
6179 case ARM::VLD4LNdWB_fixed_Asm_16:
6180 case ARM::VLD4LNdWB_fixed_Asm_32:
6181 case ARM::VLD4LNqWB_fixed_Asm_16:
6182 case ARM::VLD4LNqWB_fixed_Asm_32: {
6184 // Shuffle the operands around so the lane index operand is in the
6187 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6188 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6189 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6191 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6193 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6195 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6196 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6197 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6198 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6199 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6200 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6202 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6204 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6206 TmpInst.addOperand(Inst.getOperand(1)); // lane
6207 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6208 TmpInst.addOperand(Inst.getOperand(5));
6213 case ARM::VLD1LNdAsm_8:
6214 case ARM::VLD1LNdAsm_16:
6215 case ARM::VLD1LNdAsm_32: {
6217 // Shuffle the operands around so the lane index operand is in the
6220 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6221 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6222 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6223 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6224 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6225 TmpInst.addOperand(Inst.getOperand(1)); // lane
6226 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6227 TmpInst.addOperand(Inst.getOperand(5));
6232 case ARM::VLD2LNdAsm_8:
6233 case ARM::VLD2LNdAsm_16:
6234 case ARM::VLD2LNdAsm_32:
6235 case ARM::VLD2LNqAsm_16:
6236 case ARM::VLD2LNqAsm_32: {
6238 // Shuffle the operands around so the lane index operand is in the
6241 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6242 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6243 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6245 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6246 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6247 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6248 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6250 TmpInst.addOperand(Inst.getOperand(1)); // lane
6251 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6252 TmpInst.addOperand(Inst.getOperand(5));
6257 case ARM::VLD3LNdAsm_8:
6258 case ARM::VLD3LNdAsm_16:
6259 case ARM::VLD3LNdAsm_32:
6260 case ARM::VLD3LNqAsm_16:
6261 case ARM::VLD3LNqAsm_32: {
6263 // Shuffle the operands around so the lane index operand is in the
6266 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6267 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6268 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6270 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6272 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6273 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6274 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6275 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6277 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6279 TmpInst.addOperand(Inst.getOperand(1)); // lane
6280 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6281 TmpInst.addOperand(Inst.getOperand(5));
6286 case ARM::VLD4LNdAsm_8:
6287 case ARM::VLD4LNdAsm_16:
6288 case ARM::VLD4LNdAsm_32:
6289 case ARM::VLD4LNqAsm_16:
6290 case ARM::VLD4LNqAsm_32: {
6292 // Shuffle the operands around so the lane index operand is in the
6295 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6296 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6297 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6299 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6301 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6303 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6304 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6305 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6306 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6308 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6310 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6312 TmpInst.addOperand(Inst.getOperand(1)); // lane
6313 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6314 TmpInst.addOperand(Inst.getOperand(5));
6319 // VLD3DUP single 3-element structure to all lanes instructions.
6320 case ARM::VLD3DUPdAsm_8:
6321 case ARM::VLD3DUPdAsm_16:
6322 case ARM::VLD3DUPdAsm_32:
6323 case ARM::VLD3DUPqAsm_8:
6324 case ARM::VLD3DUPqAsm_16:
6325 case ARM::VLD3DUPqAsm_32: {
6328 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6329 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6330 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6332 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6334 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6335 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6336 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6337 TmpInst.addOperand(Inst.getOperand(4));
6342 case ARM::VLD3DUPdWB_fixed_Asm_8:
6343 case ARM::VLD3DUPdWB_fixed_Asm_16:
6344 case ARM::VLD3DUPdWB_fixed_Asm_32:
6345 case ARM::VLD3DUPqWB_fixed_Asm_8:
6346 case ARM::VLD3DUPqWB_fixed_Asm_16:
6347 case ARM::VLD3DUPqWB_fixed_Asm_32: {
6350 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6351 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6352 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6354 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6356 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6357 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6358 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6359 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6360 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6361 TmpInst.addOperand(Inst.getOperand(4));
6366 case ARM::VLD3DUPdWB_register_Asm_8:
6367 case ARM::VLD3DUPdWB_register_Asm_16:
6368 case ARM::VLD3DUPdWB_register_Asm_32:
6369 case ARM::VLD3DUPqWB_register_Asm_8:
6370 case ARM::VLD3DUPqWB_register_Asm_16:
6371 case ARM::VLD3DUPqWB_register_Asm_32: {
6374 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6375 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6376 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6378 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6380 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6381 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6382 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6383 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6384 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6385 TmpInst.addOperand(Inst.getOperand(5));
6390 // VLD3 multiple 3-element structure instructions.
6391 case ARM::VLD3dAsm_8:
6392 case ARM::VLD3dAsm_16:
6393 case ARM::VLD3dAsm_32:
6394 case ARM::VLD3qAsm_8:
6395 case ARM::VLD3qAsm_16:
6396 case ARM::VLD3qAsm_32: {
6399 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6400 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6401 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6403 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6405 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6406 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6407 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6408 TmpInst.addOperand(Inst.getOperand(4));
6413 case ARM::VLD3dWB_fixed_Asm_8:
6414 case ARM::VLD3dWB_fixed_Asm_16:
6415 case ARM::VLD3dWB_fixed_Asm_32:
6416 case ARM::VLD3qWB_fixed_Asm_8:
6417 case ARM::VLD3qWB_fixed_Asm_16:
6418 case ARM::VLD3qWB_fixed_Asm_32: {
6421 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6422 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6423 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6425 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6427 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6428 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6429 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6430 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6431 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6432 TmpInst.addOperand(Inst.getOperand(4));
6437 case ARM::VLD3dWB_register_Asm_8:
6438 case ARM::VLD3dWB_register_Asm_16:
6439 case ARM::VLD3dWB_register_Asm_32:
6440 case ARM::VLD3qWB_register_Asm_8:
6441 case ARM::VLD3qWB_register_Asm_16:
6442 case ARM::VLD3qWB_register_Asm_32: {
6445 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6446 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6447 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6449 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6451 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6452 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6453 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6454 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6455 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6456 TmpInst.addOperand(Inst.getOperand(5));
6461 // VLD4DUP single 3-element structure to all lanes instructions.
6462 case ARM::VLD4DUPdAsm_8:
6463 case ARM::VLD4DUPdAsm_16:
6464 case ARM::VLD4DUPdAsm_32:
6465 case ARM::VLD4DUPqAsm_8:
6466 case ARM::VLD4DUPqAsm_16:
6467 case ARM::VLD4DUPqAsm_32: {
6470 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6471 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6472 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6474 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6476 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6478 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6479 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6480 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6481 TmpInst.addOperand(Inst.getOperand(4));
6486 case ARM::VLD4DUPdWB_fixed_Asm_8:
6487 case ARM::VLD4DUPdWB_fixed_Asm_16:
6488 case ARM::VLD4DUPdWB_fixed_Asm_32:
6489 case ARM::VLD4DUPqWB_fixed_Asm_8:
6490 case ARM::VLD4DUPqWB_fixed_Asm_16:
6491 case ARM::VLD4DUPqWB_fixed_Asm_32: {
6494 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6495 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6496 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6498 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6500 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6502 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6503 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6504 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6505 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6506 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6507 TmpInst.addOperand(Inst.getOperand(4));
6512 case ARM::VLD4DUPdWB_register_Asm_8:
6513 case ARM::VLD4DUPdWB_register_Asm_16:
6514 case ARM::VLD4DUPdWB_register_Asm_32:
6515 case ARM::VLD4DUPqWB_register_Asm_8:
6516 case ARM::VLD4DUPqWB_register_Asm_16:
6517 case ARM::VLD4DUPqWB_register_Asm_32: {
6520 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6521 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6522 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6524 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6526 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6528 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6529 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6530 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6531 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6532 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6533 TmpInst.addOperand(Inst.getOperand(5));
6538 // VLD4 multiple 4-element structure instructions.
6539 case ARM::VLD4dAsm_8:
6540 case ARM::VLD4dAsm_16:
6541 case ARM::VLD4dAsm_32:
6542 case ARM::VLD4qAsm_8:
6543 case ARM::VLD4qAsm_16:
6544 case ARM::VLD4qAsm_32: {
6547 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6548 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6549 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6551 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6553 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6555 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6556 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6557 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6558 TmpInst.addOperand(Inst.getOperand(4));
6563 case ARM::VLD4dWB_fixed_Asm_8:
6564 case ARM::VLD4dWB_fixed_Asm_16:
6565 case ARM::VLD4dWB_fixed_Asm_32:
6566 case ARM::VLD4qWB_fixed_Asm_8:
6567 case ARM::VLD4qWB_fixed_Asm_16:
6568 case ARM::VLD4qWB_fixed_Asm_32: {
6571 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6572 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6573 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6575 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6577 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6579 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6580 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6581 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6582 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6583 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6584 TmpInst.addOperand(Inst.getOperand(4));
6589 case ARM::VLD4dWB_register_Asm_8:
6590 case ARM::VLD4dWB_register_Asm_16:
6591 case ARM::VLD4dWB_register_Asm_32:
6592 case ARM::VLD4qWB_register_Asm_8:
6593 case ARM::VLD4qWB_register_Asm_16:
6594 case ARM::VLD4qWB_register_Asm_32: {
6597 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6598 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6599 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6601 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6603 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6605 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6606 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6607 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6608 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6609 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6610 TmpInst.addOperand(Inst.getOperand(5));
6615 // VST3 multiple 3-element structure instructions.
6616 case ARM::VST3dAsm_8:
6617 case ARM::VST3dAsm_16:
6618 case ARM::VST3dAsm_32:
6619 case ARM::VST3qAsm_8:
6620 case ARM::VST3qAsm_16:
6621 case ARM::VST3qAsm_32: {
6624 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6625 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6626 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6627 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6628 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6630 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6632 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6633 TmpInst.addOperand(Inst.getOperand(4));
6638 case ARM::VST3dWB_fixed_Asm_8:
6639 case ARM::VST3dWB_fixed_Asm_16:
6640 case ARM::VST3dWB_fixed_Asm_32:
6641 case ARM::VST3qWB_fixed_Asm_8:
6642 case ARM::VST3qWB_fixed_Asm_16:
6643 case ARM::VST3qWB_fixed_Asm_32: {
6646 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6647 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6648 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6649 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6650 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6651 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6652 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6654 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6656 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6657 TmpInst.addOperand(Inst.getOperand(4));
6662 case ARM::VST3dWB_register_Asm_8:
6663 case ARM::VST3dWB_register_Asm_16:
6664 case ARM::VST3dWB_register_Asm_32:
6665 case ARM::VST3qWB_register_Asm_8:
6666 case ARM::VST3qWB_register_Asm_16:
6667 case ARM::VST3qWB_register_Asm_32: {
6670 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6671 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6672 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6673 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6674 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6675 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6676 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6678 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6680 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6681 TmpInst.addOperand(Inst.getOperand(5));
6686 // VST4 multiple 3-element structure instructions.
6687 case ARM::VST4dAsm_8:
6688 case ARM::VST4dAsm_16:
6689 case ARM::VST4dAsm_32:
6690 case ARM::VST4qAsm_8:
6691 case ARM::VST4qAsm_16:
6692 case ARM::VST4qAsm_32: {
6695 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6696 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6697 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6698 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6699 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6701 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6703 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6705 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6706 TmpInst.addOperand(Inst.getOperand(4));
6711 case ARM::VST4dWB_fixed_Asm_8:
6712 case ARM::VST4dWB_fixed_Asm_16:
6713 case ARM::VST4dWB_fixed_Asm_32:
6714 case ARM::VST4qWB_fixed_Asm_8:
6715 case ARM::VST4qWB_fixed_Asm_16:
6716 case ARM::VST4qWB_fixed_Asm_32: {
6719 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6720 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6721 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6722 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6723 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6724 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6725 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6727 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6729 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6731 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6732 TmpInst.addOperand(Inst.getOperand(4));
6737 case ARM::VST4dWB_register_Asm_8:
6738 case ARM::VST4dWB_register_Asm_16:
6739 case ARM::VST4dWB_register_Asm_32:
6740 case ARM::VST4qWB_register_Asm_8:
6741 case ARM::VST4qWB_register_Asm_16:
6742 case ARM::VST4qWB_register_Asm_32: {
6745 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6746 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6747 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6748 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6749 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6750 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6751 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6753 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6755 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6757 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6758 TmpInst.addOperand(Inst.getOperand(5));
6763 // Handle encoding choice for the shift-immediate instructions.
6766 case ARM::t2ASRri: {
6767 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6768 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6769 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
6770 !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
6771 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
6773 switch (Inst.getOpcode()) {
6774 default: llvm_unreachable("unexpected opcode");
6775 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
6776 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
6777 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
6779 // The Thumb1 operands aren't in the same order. Awesome, eh?
6781 TmpInst.setOpcode(NewOpc);
6782 TmpInst.addOperand(Inst.getOperand(0));
6783 TmpInst.addOperand(Inst.getOperand(5));
6784 TmpInst.addOperand(Inst.getOperand(1));
6785 TmpInst.addOperand(Inst.getOperand(2));
6786 TmpInst.addOperand(Inst.getOperand(3));
6787 TmpInst.addOperand(Inst.getOperand(4));
6794 // Handle the Thumb2 mode MOV complex aliases.
6796 case ARM::t2MOVSsr: {
6797 // Which instruction to expand to depends on the CCOut operand and
6798 // whether we're in an IT block if the register operands are low
6800 bool isNarrow = false;
6801 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6802 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6803 isARMLowRegister(Inst.getOperand(2).getReg()) &&
6804 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6805 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
6809 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
6810 default: llvm_unreachable("unexpected opcode!");
6811 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
6812 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
6813 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
6814 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
6816 TmpInst.setOpcode(newOpc);
6817 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6819 TmpInst.addOperand(MCOperand::CreateReg(
6820 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6821 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6822 TmpInst.addOperand(Inst.getOperand(2)); // Rm
6823 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6824 TmpInst.addOperand(Inst.getOperand(5));
6826 TmpInst.addOperand(MCOperand::CreateReg(
6827 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6832 case ARM::t2MOVSsi: {
6833 // Which instruction to expand to depends on the CCOut operand and
6834 // whether we're in an IT block if the register operands are low
6836 bool isNarrow = false;
6837 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6838 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6839 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
6843 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
6844 default: llvm_unreachable("unexpected opcode!");
6845 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
6846 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
6847 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
6848 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
6849 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
6851 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
6852 if (Amount == 32) Amount = 0;
6853 TmpInst.setOpcode(newOpc);
6854 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6856 TmpInst.addOperand(MCOperand::CreateReg(
6857 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6858 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6859 if (newOpc != ARM::t2RRX)
6860 TmpInst.addOperand(MCOperand::CreateImm(Amount));
6861 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6862 TmpInst.addOperand(Inst.getOperand(4));
6864 TmpInst.addOperand(MCOperand::CreateReg(
6865 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6869 // Handle the ARM mode MOV complex aliases.
6874 ARM_AM::ShiftOpc ShiftTy;
6875 switch(Inst.getOpcode()) {
6876 default: llvm_unreachable("unexpected opcode!");
6877 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
6878 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
6879 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
6880 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
6882 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
6884 TmpInst.setOpcode(ARM::MOVsr);
6885 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6886 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6887 TmpInst.addOperand(Inst.getOperand(2)); // Rm
6888 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6889 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6890 TmpInst.addOperand(Inst.getOperand(4));
6891 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6899 ARM_AM::ShiftOpc ShiftTy;
6900 switch(Inst.getOpcode()) {
6901 default: llvm_unreachable("unexpected opcode!");
6902 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
6903 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
6904 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
6905 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
6907 // A shift by zero is a plain MOVr, not a MOVsi.
6908 unsigned Amt = Inst.getOperand(2).getImm();
6909 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
6910 // A shift by 32 should be encoded as 0 when permitted
6911 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
6913 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
6915 TmpInst.setOpcode(Opc);
6916 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6917 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6918 if (Opc == ARM::MOVsi)
6919 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6920 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6921 TmpInst.addOperand(Inst.getOperand(4));
6922 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6927 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
6929 TmpInst.setOpcode(ARM::MOVsi);
6930 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6931 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6932 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6933 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6934 TmpInst.addOperand(Inst.getOperand(3));
6935 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
6939 case ARM::t2LDMIA_UPD: {
6940 // If this is a load of a single register, then we should use
6941 // a post-indexed LDR instruction instead, per the ARM ARM.
6942 if (Inst.getNumOperands() != 5)
6945 TmpInst.setOpcode(ARM::t2LDR_POST);
6946 TmpInst.addOperand(Inst.getOperand(4)); // Rt
6947 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6948 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6949 TmpInst.addOperand(MCOperand::CreateImm(4));
6950 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6951 TmpInst.addOperand(Inst.getOperand(3));
6955 case ARM::t2STMDB_UPD: {
6956 // If this is a store of a single register, then we should use
6957 // a pre-indexed STR instruction instead, per the ARM ARM.
6958 if (Inst.getNumOperands() != 5)
6961 TmpInst.setOpcode(ARM::t2STR_PRE);
6962 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6963 TmpInst.addOperand(Inst.getOperand(4)); // Rt
6964 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6965 TmpInst.addOperand(MCOperand::CreateImm(-4));
6966 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6967 TmpInst.addOperand(Inst.getOperand(3));
6971 case ARM::LDMIA_UPD:
6972 // If this is a load of a single register via a 'pop', then we should use
6973 // a post-indexed LDR instruction instead, per the ARM ARM.
6974 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
6975 Inst.getNumOperands() == 5) {
6977 TmpInst.setOpcode(ARM::LDR_POST_IMM);
6978 TmpInst.addOperand(Inst.getOperand(4)); // Rt
6979 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6980 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6981 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
6982 TmpInst.addOperand(MCOperand::CreateImm(4));
6983 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6984 TmpInst.addOperand(Inst.getOperand(3));
6989 case ARM::STMDB_UPD:
6990 // If this is a store of a single register via a 'push', then we should use
6991 // a pre-indexed STR instruction instead, per the ARM ARM.
6992 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
6993 Inst.getNumOperands() == 5) {
6995 TmpInst.setOpcode(ARM::STR_PRE_IMM);
6996 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6997 TmpInst.addOperand(Inst.getOperand(4)); // Rt
6998 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
6999 TmpInst.addOperand(MCOperand::CreateImm(-4));
7000 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7001 TmpInst.addOperand(Inst.getOperand(3));
7005 case ARM::t2ADDri12:
7006 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7007 // mnemonic was used (not "addw"), encoding T3 is preferred.
7008 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
7009 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7011 Inst.setOpcode(ARM::t2ADDri);
7012 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7014 case ARM::t2SUBri12:
7015 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7016 // mnemonic was used (not "subw"), encoding T3 is preferred.
7017 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7018 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7020 Inst.setOpcode(ARM::t2SUBri);
7021 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7024 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7025 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7026 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7027 // to encoding T1 if <Rd> is omitted."
7028 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7029 Inst.setOpcode(ARM::tADDi3);
7034 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7035 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7036 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7037 // to encoding T1 if <Rd> is omitted."
7038 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7039 Inst.setOpcode(ARM::tSUBi3);
7044 case ARM::t2SUBri: {
7045 // If the destination and first source operand are the same, and
7046 // the flags are compatible with the current IT status, use encoding T2
7047 // instead of T3. For compatibility with the system 'as'. Make sure the
7048 // wide encoding wasn't explicit.
7049 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7050 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7051 (unsigned)Inst.getOperand(2).getImm() > 255 ||
7052 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7053 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7054 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7055 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7058 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7059 ARM::tADDi8 : ARM::tSUBi8);
7060 TmpInst.addOperand(Inst.getOperand(0));
7061 TmpInst.addOperand(Inst.getOperand(5));
7062 TmpInst.addOperand(Inst.getOperand(0));
7063 TmpInst.addOperand(Inst.getOperand(2));
7064 TmpInst.addOperand(Inst.getOperand(3));
7065 TmpInst.addOperand(Inst.getOperand(4));
7069 case ARM::t2ADDrr: {
7070 // If the destination and first source operand are the same, and
7071 // there's no setting of the flags, use encoding T2 instead of T3.
7072 // Note that this is only for ADD, not SUB. This mirrors the system
7073 // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7074 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7075 Inst.getOperand(5).getReg() != 0 ||
7076 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7077 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7080 TmpInst.setOpcode(ARM::tADDhirr);
7081 TmpInst.addOperand(Inst.getOperand(0));
7082 TmpInst.addOperand(Inst.getOperand(0));
7083 TmpInst.addOperand(Inst.getOperand(2));
7084 TmpInst.addOperand(Inst.getOperand(3));
7085 TmpInst.addOperand(Inst.getOperand(4));
7089 case ARM::tADDrSP: {
7090 // If the non-SP source operand and the destination operand are not the
7091 // same, we need to use the 32-bit encoding if it's available.
7092 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7093 Inst.setOpcode(ARM::t2ADDrr);
7094 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7100 // A Thumb conditional branch outside of an IT block is a tBcc.
7101 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7102 Inst.setOpcode(ARM::tBcc);
7107 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7108 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7109 Inst.setOpcode(ARM::t2Bcc);
7114 // If the conditional is AL or we're in an IT block, we really want t2B.
7115 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7116 Inst.setOpcode(ARM::t2B);
7121 // If the conditional is AL, we really want tB.
7122 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7123 Inst.setOpcode(ARM::tB);
7128 // If the register list contains any high registers, or if the writeback
7129 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7130 // instead if we're in Thumb2. Otherwise, this should have generated
7131 // an error in validateInstruction().
7132 unsigned Rn = Inst.getOperand(0).getReg();
7133 bool hasWritebackToken =
7134 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7135 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7136 bool listContainsBase;
7137 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7138 (!listContainsBase && !hasWritebackToken) ||
7139 (listContainsBase && hasWritebackToken)) {
7140 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7141 assert (isThumbTwo());
7142 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7143 // If we're switching to the updating version, we need to insert
7144 // the writeback tied operand.
7145 if (hasWritebackToken)
7146 Inst.insert(Inst.begin(),
7147 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7152 case ARM::tSTMIA_UPD: {
7153 // If the register list contains any high registers, we need to use
7154 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7155 // should have generated an error in validateInstruction().
7156 unsigned Rn = Inst.getOperand(0).getReg();
7157 bool listContainsBase;
7158 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7159 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7160 assert (isThumbTwo());
7161 Inst.setOpcode(ARM::t2STMIA_UPD);
7167 bool listContainsBase;
7168 // If the register list contains any high registers, we need to use
7169 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7170 // should have generated an error in validateInstruction().
7171 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7173 assert (isThumbTwo());
7174 Inst.setOpcode(ARM::t2LDMIA_UPD);
7175 // Add the base register and writeback operands.
7176 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7177 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7181 bool listContainsBase;
7182 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7184 assert (isThumbTwo());
7185 Inst.setOpcode(ARM::t2STMDB_UPD);
7186 // Add the base register and writeback operands.
7187 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7188 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7192 // If we can use the 16-bit encoding and the user didn't explicitly
7193 // request the 32-bit variant, transform it here.
7194 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7195 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7196 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7197 Inst.getOperand(4).getReg() == ARM::CPSR) ||
7198 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7199 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7200 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7201 // The operands aren't in the same order for tMOVi8...
7203 TmpInst.setOpcode(ARM::tMOVi8);
7204 TmpInst.addOperand(Inst.getOperand(0));
7205 TmpInst.addOperand(Inst.getOperand(4));
7206 TmpInst.addOperand(Inst.getOperand(1));
7207 TmpInst.addOperand(Inst.getOperand(2));
7208 TmpInst.addOperand(Inst.getOperand(3));
7215 // If we can use the 16-bit encoding and the user didn't explicitly
7216 // request the 32-bit variant, transform it here.
7217 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7218 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7219 Inst.getOperand(2).getImm() == ARMCC::AL &&
7220 Inst.getOperand(4).getReg() == ARM::CPSR &&
7221 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7222 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7223 // The operands aren't the same for tMOV[S]r... (no cc_out)
7225 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7226 TmpInst.addOperand(Inst.getOperand(0));
7227 TmpInst.addOperand(Inst.getOperand(1));
7228 TmpInst.addOperand(Inst.getOperand(2));
7229 TmpInst.addOperand(Inst.getOperand(3));
7239 // If we can use the 16-bit encoding and the user didn't explicitly
7240 // request the 32-bit variant, transform it here.
7241 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7242 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7243 Inst.getOperand(2).getImm() == 0 &&
7244 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7245 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7247 switch (Inst.getOpcode()) {
7248 default: llvm_unreachable("Illegal opcode!");
7249 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7250 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7251 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7252 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7254 // The operands aren't the same for thumb1 (no rotate operand).
7256 TmpInst.setOpcode(NewOpc);
7257 TmpInst.addOperand(Inst.getOperand(0));
7258 TmpInst.addOperand(Inst.getOperand(1));
7259 TmpInst.addOperand(Inst.getOperand(3));
7260 TmpInst.addOperand(Inst.getOperand(4));
7267 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7268 // rrx shifts and asr/lsr of #32 is encoded as 0
7269 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7271 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7272 // Shifting by zero is accepted as a vanilla 'MOVr'
7274 TmpInst.setOpcode(ARM::MOVr);
7275 TmpInst.addOperand(Inst.getOperand(0));
7276 TmpInst.addOperand(Inst.getOperand(1));
7277 TmpInst.addOperand(Inst.getOperand(3));
7278 TmpInst.addOperand(Inst.getOperand(4));
7279 TmpInst.addOperand(Inst.getOperand(5));
7292 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7293 if (SOpc == ARM_AM::rrx) return false;
7294 switch (Inst.getOpcode()) {
7295 default: llvm_unreachable("unexpected opcode!");
7296 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7297 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7298 case ARM::EORrsi: newOpc = ARM::EORrr; break;
7299 case ARM::BICrsi: newOpc = ARM::BICrr; break;
7300 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7301 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7303 // If the shift is by zero, use the non-shifted instruction definition.
7304 // The exception is for right shifts, where 0 == 32
7305 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7306 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7308 TmpInst.setOpcode(newOpc);
7309 TmpInst.addOperand(Inst.getOperand(0));
7310 TmpInst.addOperand(Inst.getOperand(1));
7311 TmpInst.addOperand(Inst.getOperand(2));
7312 TmpInst.addOperand(Inst.getOperand(4));
7313 TmpInst.addOperand(Inst.getOperand(5));
7314 TmpInst.addOperand(Inst.getOperand(6));
7322 // The mask bits for all but the first condition are represented as
7323 // the low bit of the condition code value implies 't'. We currently
7324 // always have 1 implies 't', so XOR toggle the bits if the low bit
7325 // of the condition code is zero.
7326 MCOperand &MO = Inst.getOperand(1);
7327 unsigned Mask = MO.getImm();
7328 unsigned OrigMask = Mask;
7329 unsigned TZ = CountTrailingZeros_32(Mask);
7330 if ((Inst.getOperand(0).getImm() & 1) == 0) {
7331 assert(Mask && TZ <= 3 && "illegal IT mask value!");
7332 for (unsigned i = 3; i != TZ; --i)
7337 // Set up the IT block state according to the IT instruction we just
7339 assert(!inITBlock() && "nested IT blocks?!");
7340 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7341 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7342 ITState.CurPosition = 0;
7343 ITState.FirstCond = true;
7353 // Assemblers should use the narrow encodings of these instructions when permissible.
7354 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7355 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7356 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7357 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7358 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7359 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7360 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7362 switch (Inst.getOpcode()) {
7363 default: llvm_unreachable("unexpected opcode");
7364 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7365 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7366 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7367 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7368 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7369 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7372 TmpInst.setOpcode(NewOpc);
7373 TmpInst.addOperand(Inst.getOperand(0));
7374 TmpInst.addOperand(Inst.getOperand(5));
7375 TmpInst.addOperand(Inst.getOperand(1));
7376 TmpInst.addOperand(Inst.getOperand(2));
7377 TmpInst.addOperand(Inst.getOperand(3));
7378 TmpInst.addOperand(Inst.getOperand(4));
7389 // Assemblers should use the narrow encodings of these instructions when permissible.
7390 // These instructions are special in that they are commutable, so shorter encodings
7391 // are available more often.
7392 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7393 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7394 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7395 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7396 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7397 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7398 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7399 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7401 switch (Inst.getOpcode()) {
7402 default: llvm_unreachable("unexpected opcode");
7403 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7404 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7405 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7406 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7409 TmpInst.setOpcode(NewOpc);
7410 TmpInst.addOperand(Inst.getOperand(0));
7411 TmpInst.addOperand(Inst.getOperand(5));
7412 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7413 TmpInst.addOperand(Inst.getOperand(1));
7414 TmpInst.addOperand(Inst.getOperand(2));
7416 TmpInst.addOperand(Inst.getOperand(2));
7417 TmpInst.addOperand(Inst.getOperand(1));
7419 TmpInst.addOperand(Inst.getOperand(3));
7420 TmpInst.addOperand(Inst.getOperand(4));
7430 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7431 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7432 // suffix depending on whether they're in an IT block or not.
7433 unsigned Opc = Inst.getOpcode();
7434 const MCInstrDesc &MCID = getInstDesc(Opc);
7435 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7436 assert(MCID.hasOptionalDef() &&
7437 "optionally flag setting instruction missing optional def operand");
7438 assert(MCID.NumOperands == Inst.getNumOperands() &&
7439 "operand count mismatch!");
7440 // Find the optional-def operand (cc_out).
7443 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7446 // If we're parsing Thumb1, reject it completely.
7447 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7448 return Match_MnemonicFail;
7449 // If we're parsing Thumb2, which form is legal depends on whether we're
7451 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7453 return Match_RequiresITBlock;
7454 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7456 return Match_RequiresNotITBlock;
7458 // Some high-register supporting Thumb1 encodings only allow both registers
7459 // to be from r0-r7 when in Thumb2.
7460 else if (Opc == ARM::tADDhirr && isThumbOne() &&
7461 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7462 isARMLowRegister(Inst.getOperand(2).getReg()))
7463 return Match_RequiresThumb2;
7464 // Others only require ARMv6 or later.
7465 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7466 isARMLowRegister(Inst.getOperand(0).getReg()) &&
7467 isARMLowRegister(Inst.getOperand(1).getReg()))
7468 return Match_RequiresV6;
7469 return Match_Success;
7472 static const char *getSubtargetFeatureName(unsigned Val);
7474 MatchAndEmitInstruction(SMLoc IDLoc,
7475 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
7479 unsigned MatchResult;
7480 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
7481 switch (MatchResult) {
7484 // Context sensitive operand constraints aren't handled by the matcher,
7485 // so check them here.
7486 if (validateInstruction(Inst, Operands)) {
7487 // Still progress the IT block, otherwise one wrong condition causes
7488 // nasty cascading errors.
7489 forwardITPosition();
7493 // Some instructions need post-processing to, for example, tweak which
7494 // encoding is selected. Loop on it while changes happen so the
7495 // individual transformations can chain off each other. E.g.,
7496 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
7497 while (processInstruction(Inst, Operands))
7500 // Only move forward at the very end so that everything in validate
7501 // and process gets a consistent answer about whether we're in an IT
7503 forwardITPosition();
7505 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7506 // doesn't actually encode.
7507 if (Inst.getOpcode() == ARM::ITasm)
7511 Out.EmitInstruction(Inst);
7513 case Match_MissingFeature: {
7514 assert(ErrorInfo && "Unknown missing feature!");
7515 // Special case the error message for the very common case where only
7516 // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
7517 std::string Msg = "instruction requires:";
7519 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
7520 if (ErrorInfo & Mask) {
7522 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
7526 return Error(IDLoc, Msg);
7528 case Match_InvalidOperand: {
7529 SMLoc ErrorLoc = IDLoc;
7530 if (ErrorInfo != ~0U) {
7531 if (ErrorInfo >= Operands.size())
7532 return Error(IDLoc, "too few operands for instruction");
7534 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7535 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7538 return Error(ErrorLoc, "invalid operand for instruction");
7540 case Match_MnemonicFail:
7541 return Error(IDLoc, "invalid instruction",
7542 ((ARMOperand*)Operands[0])->getLocRange());
7543 case Match_ConversionFail:
7544 // The converter function will have already emitted a diagnostic.
7546 case Match_RequiresNotITBlock:
7547 return Error(IDLoc, "flag setting instruction only valid outside IT block");
7548 case Match_RequiresITBlock:
7549 return Error(IDLoc, "instruction only valid inside IT block");
7550 case Match_RequiresV6:
7551 return Error(IDLoc, "instruction variant requires ARMv6 or later");
7552 case Match_RequiresThumb2:
7553 return Error(IDLoc, "instruction variant requires Thumb2");
7554 case Match_ImmRange0_15: {
7555 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7556 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7557 return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
7561 llvm_unreachable("Implement any new match types added!");
7564 /// parseDirective parses the arm specific directives
7565 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
7566 StringRef IDVal = DirectiveID.getIdentifier();
7567 if (IDVal == ".word")
7568 return parseDirectiveWord(4, DirectiveID.getLoc());
7569 else if (IDVal == ".thumb")
7570 return parseDirectiveThumb(DirectiveID.getLoc());
7571 else if (IDVal == ".arm")
7572 return parseDirectiveARM(DirectiveID.getLoc());
7573 else if (IDVal == ".thumb_func")
7574 return parseDirectiveThumbFunc(DirectiveID.getLoc());
7575 else if (IDVal == ".code")
7576 return parseDirectiveCode(DirectiveID.getLoc());
7577 else if (IDVal == ".syntax")
7578 return parseDirectiveSyntax(DirectiveID.getLoc());
7579 else if (IDVal == ".unreq")
7580 return parseDirectiveUnreq(DirectiveID.getLoc());
7581 else if (IDVal == ".arch")
7582 return parseDirectiveArch(DirectiveID.getLoc());
7583 else if (IDVal == ".eabi_attribute")
7584 return parseDirectiveEabiAttr(DirectiveID.getLoc());
7588 /// parseDirectiveWord
7589 /// ::= .word [ expression (, expression)* ]
7590 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
7591 if (getLexer().isNot(AsmToken::EndOfStatement)) {
7593 const MCExpr *Value;
7594 if (getParser().ParseExpression(Value))
7597 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
7599 if (getLexer().is(AsmToken::EndOfStatement))
7602 // FIXME: Improve diagnostic.
7603 if (getLexer().isNot(AsmToken::Comma))
7604 return Error(L, "unexpected token in directive");
7613 /// parseDirectiveThumb
7615 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
7616 if (getLexer().isNot(AsmToken::EndOfStatement))
7617 return Error(L, "unexpected token in directive");
7622 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7626 /// parseDirectiveARM
7628 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
7629 if (getLexer().isNot(AsmToken::EndOfStatement))
7630 return Error(L, "unexpected token in directive");
7635 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7639 /// parseDirectiveThumbFunc
7640 /// ::= .thumbfunc symbol_name
7641 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
7642 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
7643 bool isMachO = MAI.hasSubsectionsViaSymbols();
7645 bool needFuncName = true;
7647 // Darwin asm has (optionally) function name after .thumb_func direction
7650 const AsmToken &Tok = Parser.getTok();
7651 if (Tok.isNot(AsmToken::EndOfStatement)) {
7652 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
7653 return Error(L, "unexpected token in .thumb_func directive");
7654 Name = Tok.getIdentifier();
7655 Parser.Lex(); // Consume the identifier token.
7656 needFuncName = false;
7660 if (getLexer().isNot(AsmToken::EndOfStatement))
7661 return Error(L, "unexpected token in directive");
7663 // Eat the end of statement and any blank lines that follow.
7664 while (getLexer().is(AsmToken::EndOfStatement))
7667 // FIXME: assuming function name will be the line following .thumb_func
7668 // We really should be checking the next symbol definition even if there's
7669 // stuff in between.
7671 Name = Parser.getTok().getIdentifier();
7674 // Mark symbol as a thumb symbol.
7675 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
7676 getParser().getStreamer().EmitThumbFunc(Func);
7680 /// parseDirectiveSyntax
7681 /// ::= .syntax unified | divided
7682 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
7683 const AsmToken &Tok = Parser.getTok();
7684 if (Tok.isNot(AsmToken::Identifier))
7685 return Error(L, "unexpected token in .syntax directive");
7686 StringRef Mode = Tok.getString();
7687 if (Mode == "unified" || Mode == "UNIFIED")
7689 else if (Mode == "divided" || Mode == "DIVIDED")
7690 return Error(L, "'.syntax divided' arm asssembly not supported");
7692 return Error(L, "unrecognized syntax mode in .syntax directive");
7694 if (getLexer().isNot(AsmToken::EndOfStatement))
7695 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7698 // TODO tell the MC streamer the mode
7699 // getParser().getStreamer().Emit???();
7703 /// parseDirectiveCode
7704 /// ::= .code 16 | 32
7705 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
7706 const AsmToken &Tok = Parser.getTok();
7707 if (Tok.isNot(AsmToken::Integer))
7708 return Error(L, "unexpected token in .code directive");
7709 int64_t Val = Parser.getTok().getIntVal();
7715 return Error(L, "invalid operand to .code directive");
7717 if (getLexer().isNot(AsmToken::EndOfStatement))
7718 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7724 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7728 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7734 /// parseDirectiveReq
7735 /// ::= name .req registername
7736 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
7737 Parser.Lex(); // Eat the '.req' token.
7739 SMLoc SRegLoc, ERegLoc;
7740 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
7741 Parser.EatToEndOfStatement();
7742 return Error(SRegLoc, "register name expected");
7745 // Shouldn't be anything else.
7746 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
7747 Parser.EatToEndOfStatement();
7748 return Error(Parser.getTok().getLoc(),
7749 "unexpected input in .req directive.");
7752 Parser.Lex(); // Consume the EndOfStatement
7754 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg)
7755 return Error(SRegLoc, "redefinition of '" + Name +
7756 "' does not match original.");
7761 /// parseDirectiveUneq
7762 /// ::= .unreq registername
7763 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
7764 if (Parser.getTok().isNot(AsmToken::Identifier)) {
7765 Parser.EatToEndOfStatement();
7766 return Error(L, "unexpected input in .unreq directive.");
7768 RegisterReqs.erase(Parser.getTok().getIdentifier());
7769 Parser.Lex(); // Eat the identifier.
7773 /// parseDirectiveArch
7775 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
7779 /// parseDirectiveEabiAttr
7780 /// ::= .eabi_attribute int, int
7781 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
7785 extern "C" void LLVMInitializeARMAsmLexer();
7787 /// Force static initialization.
7788 extern "C" void LLVMInitializeARMAsmParser() {
7789 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
7790 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
7791 LLVMInitializeARMAsmLexer();
7794 #define GET_REGISTER_MATCHER
7795 #define GET_SUBTARGET_FEATURE_NAME
7796 #define GET_MATCHER_IMPLEMENTATION
7797 #include "ARMGenAsmMatcher.inc"