1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMAddressingModes.h"
12 #include "ARMMCExpr.h"
13 #include "ARMBaseRegisterInfo.h"
14 #include "ARMSubtarget.h"
15 #include "llvm/MC/MCParser/MCAsmLexer.h"
16 #include "llvm/MC/MCParser/MCAsmParser.h"
17 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
18 #include "llvm/MC/MCAsmInfo.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCStreamer.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/Target/TargetRegistry.h"
24 #include "llvm/Target/TargetAsmParser.h"
25 #include "llvm/Support/SourceMgr.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include "llvm/ADT/SmallVector.h"
28 #include "llvm/ADT/StringExtras.h"
29 #include "llvm/ADT/StringSwitch.h"
30 #include "llvm/ADT/Twine.h"
37 class ARMAsmParser : public TargetAsmParser {
41 MCAsmParser &getParser() const { return Parser; }
42 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
44 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
45 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
47 int TryParseRegister();
48 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
49 bool TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
50 bool TryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
51 bool ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
52 bool ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &,
53 ARMII::AddrMode AddrMode);
54 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
55 bool ParsePrefix(ARMMCExpr::VariantKind &RefKind);
56 const MCExpr *ApplyPrefixToExpr(const MCExpr *E,
57 MCSymbolRefExpr::VariantKind Variant);
60 bool ParseMemoryOffsetReg(bool &Negative,
61 bool &OffsetRegShifted,
62 enum ARM_AM::ShiftOpc &ShiftType,
63 const MCExpr *&ShiftAmount,
64 const MCExpr *&Offset,
68 bool ParseShift(enum ARM_AM::ShiftOpc &St,
69 const MCExpr *&ShiftAmount, SMLoc &E);
70 bool ParseDirectiveWord(unsigned Size, SMLoc L);
71 bool ParseDirectiveThumb(SMLoc L);
72 bool ParseDirectiveThumbFunc(SMLoc L);
73 bool ParseDirectiveCode(SMLoc L);
74 bool ParseDirectiveSyntax(SMLoc L);
76 bool MatchAndEmitInstruction(SMLoc IDLoc,
77 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
79 void GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
80 bool &CanAcceptPredicationCode);
82 /// @name Auto-generated Match Functions
85 #define GET_ASSEMBLER_HEADER
86 #include "ARMGenAsmMatcher.inc"
90 OperandMatchResultTy tryParseCoprocNumOperand(
91 SmallVectorImpl<MCParsedAsmOperand*>&);
92 OperandMatchResultTy tryParseCoprocRegOperand(
93 SmallVectorImpl<MCParsedAsmOperand*>&);
94 OperandMatchResultTy tryParseMemBarrierOptOperand(
95 SmallVectorImpl<MCParsedAsmOperand*>&);
96 OperandMatchResultTy tryParseProcIFlagsOperand(
97 SmallVectorImpl<MCParsedAsmOperand*>&);
98 OperandMatchResultTy tryParseMSRMaskOperand(
99 SmallVectorImpl<MCParsedAsmOperand*>&);
100 OperandMatchResultTy tryParseMemMode2Operand(
101 SmallVectorImpl<MCParsedAsmOperand*>&);
102 OperandMatchResultTy tryParseMemMode3Operand(
103 SmallVectorImpl<MCParsedAsmOperand*>&);
105 // Asm Match Converter Methods
106 bool CvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
107 const SmallVectorImpl<MCParsedAsmOperand*> &);
108 bool CvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
109 const SmallVectorImpl<MCParsedAsmOperand*> &);
110 bool CvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
111 const SmallVectorImpl<MCParsedAsmOperand*> &);
112 bool CvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
113 const SmallVectorImpl<MCParsedAsmOperand*> &);
116 ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
117 : TargetAsmParser(T), Parser(_Parser), TM(_TM) {
118 MCAsmParserExtension::Initialize(_Parser);
119 // Initialize the set of available features.
120 setAvailableFeatures(ComputeAvailableFeatures(
121 &TM.getSubtarget<ARMSubtarget>()));
124 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
125 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
126 virtual bool ParseDirective(AsmToken DirectiveID);
128 } // end anonymous namespace
132 /// ARMOperand - Instances of this class represent a parsed ARM machine
134 class ARMOperand : public MCParsedAsmOperand {
153 SMLoc StartLoc, EndLoc;
154 SmallVector<unsigned, 8> Registers;
158 ARMCC::CondCodes Val;
170 ARM_PROC::IFlags Val;
190 /// Combined record for all forms of ARM address expressions.
192 ARMII::AddrMode AddrMode;
195 unsigned RegNum; ///< Offset register num, when OffsetIsReg.
196 const MCExpr *Value; ///< Offset value, when !OffsetIsReg.
198 const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
199 enum ARM_AM::ShiftOpc ShiftType; // used when OffsetRegShifted is true
200 unsigned OffsetRegShifted : 1; // only used when OffsetIsReg is true
201 unsigned Preindexed : 1;
202 unsigned Postindexed : 1;
203 unsigned OffsetIsReg : 1;
204 unsigned Negative : 1; // only used when OffsetIsReg is true
205 unsigned Writeback : 1;
209 ARM_AM::ShiftOpc ShiftTy;
214 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
216 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
218 StartLoc = o.StartLoc;
232 case DPRRegisterList:
233 case SPRRegisterList:
234 Registers = o.Registers;
261 /// getStartLoc - Get the location of the first token of this operand.
262 SMLoc getStartLoc() const { return StartLoc; }
263 /// getEndLoc - Get the location of the last token of this operand.
264 SMLoc getEndLoc() const { return EndLoc; }
266 ARMCC::CondCodes getCondCode() const {
267 assert(Kind == CondCode && "Invalid access!");
271 unsigned getCoproc() const {
272 assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
276 StringRef getToken() const {
277 assert(Kind == Token && "Invalid access!");
278 return StringRef(Tok.Data, Tok.Length);
281 unsigned getReg() const {
282 assert((Kind == Register || Kind == CCOut) && "Invalid access!");
286 const SmallVectorImpl<unsigned> &getRegList() const {
287 assert((Kind == RegisterList || Kind == DPRRegisterList ||
288 Kind == SPRRegisterList) && "Invalid access!");
292 const MCExpr *getImm() const {
293 assert(Kind == Immediate && "Invalid access!");
297 ARM_MB::MemBOpt getMemBarrierOpt() const {
298 assert(Kind == MemBarrierOpt && "Invalid access!");
302 ARM_PROC::IFlags getProcIFlags() const {
303 assert(Kind == ProcIFlags && "Invalid access!");
307 unsigned getMSRMask() const {
308 assert(Kind == MSRMask && "Invalid access!");
312 /// @name Memory Operand Accessors
314 ARMII::AddrMode getMemAddrMode() const {
317 unsigned getMemBaseRegNum() const {
318 return Mem.BaseRegNum;
320 unsigned getMemOffsetRegNum() const {
321 assert(Mem.OffsetIsReg && "Invalid access!");
322 return Mem.Offset.RegNum;
324 const MCExpr *getMemOffset() const {
325 assert(!Mem.OffsetIsReg && "Invalid access!");
326 return Mem.Offset.Value;
328 unsigned getMemOffsetRegShifted() const {
329 assert(Mem.OffsetIsReg && "Invalid access!");
330 return Mem.OffsetRegShifted;
332 const MCExpr *getMemShiftAmount() const {
333 assert(Mem.OffsetIsReg && Mem.OffsetRegShifted && "Invalid access!");
334 return Mem.ShiftAmount;
336 enum ARM_AM::ShiftOpc getMemShiftType() const {
337 assert(Mem.OffsetIsReg && Mem.OffsetRegShifted && "Invalid access!");
338 return Mem.ShiftType;
340 bool getMemPreindexed() const { return Mem.Preindexed; }
341 bool getMemPostindexed() const { return Mem.Postindexed; }
342 bool getMemOffsetIsReg() const { return Mem.OffsetIsReg; }
343 bool getMemNegative() const { return Mem.Negative; }
344 bool getMemWriteback() const { return Mem.Writeback; }
348 bool isCoprocNum() const { return Kind == CoprocNum; }
349 bool isCoprocReg() const { return Kind == CoprocReg; }
350 bool isCondCode() const { return Kind == CondCode; }
351 bool isCCOut() const { return Kind == CCOut; }
352 bool isImm() const { return Kind == Immediate; }
353 bool isReg() const { return Kind == Register; }
354 bool isRegList() const { return Kind == RegisterList; }
355 bool isDPRRegList() const { return Kind == DPRRegisterList; }
356 bool isSPRRegList() const { return Kind == SPRRegisterList; }
357 bool isToken() const { return Kind == Token; }
358 bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
359 bool isMemory() const { return Kind == Memory; }
360 bool isShifter() const { return Kind == Shifter; }
361 bool isMemMode2() const {
362 if (getMemAddrMode() != ARMII::AddrMode2)
365 if (getMemOffsetIsReg())
368 if (getMemNegative() &&
369 !(getMemPostindexed() || getMemPreindexed()))
372 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
373 if (!CE) return false;
374 int64_t Value = CE->getValue();
376 // The offset must be in the range 0-4095 (imm12).
377 if (Value > 4095 || Value < -4095)
382 bool isMemMode3() const {
383 if (getMemAddrMode() != ARMII::AddrMode3)
386 if (getMemOffsetIsReg()) {
387 if (getMemOffsetRegShifted())
388 return false; // No shift with offset reg allowed
392 if (getMemNegative() &&
393 !(getMemPostindexed() || getMemPreindexed()))
396 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
397 if (!CE) return false;
398 int64_t Value = CE->getValue();
400 // The offset must be in the range 0-255 (imm8).
401 if (Value > 255 || Value < -255)
406 bool isMemMode5() const {
407 if (!isMemory() || getMemOffsetIsReg() || getMemWriteback() ||
411 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
412 if (!CE) return false;
414 // The offset must be a multiple of 4 in the range 0-1020.
415 int64_t Value = CE->getValue();
416 return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020);
418 bool isMemMode7() const {
420 getMemPreindexed() ||
421 getMemPostindexed() ||
422 getMemOffsetIsReg() ||
427 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
428 if (!CE) return false;
435 bool isMemModeRegThumb() const {
436 if (!isMemory() || !getMemOffsetIsReg() || getMemWriteback())
440 bool isMemModeImmThumb() const {
441 if (!isMemory() || getMemOffsetIsReg() || getMemWriteback())
444 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
445 if (!CE) return false;
447 // The offset must be a multiple of 4 in the range 0-124.
448 uint64_t Value = CE->getValue();
449 return ((Value & 0x3) == 0 && Value <= 124);
451 bool isMSRMask() const { return Kind == MSRMask; }
452 bool isProcIFlags() const { return Kind == ProcIFlags; }
454 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
455 // Add as immediates when possible. Null MCExpr = 0.
457 Inst.addOperand(MCOperand::CreateImm(0));
458 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
459 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
461 Inst.addOperand(MCOperand::CreateExpr(Expr));
464 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
465 assert(N == 2 && "Invalid number of operands!");
466 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
467 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
468 Inst.addOperand(MCOperand::CreateReg(RegNum));
471 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
472 assert(N == 1 && "Invalid number of operands!");
473 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
476 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
477 assert(N == 1 && "Invalid number of operands!");
478 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
481 void addCCOutOperands(MCInst &Inst, unsigned N) const {
482 assert(N == 1 && "Invalid number of operands!");
483 Inst.addOperand(MCOperand::CreateReg(getReg()));
486 void addRegOperands(MCInst &Inst, unsigned N) const {
487 assert(N == 1 && "Invalid number of operands!");
488 Inst.addOperand(MCOperand::CreateReg(getReg()));
491 void addShifterOperands(MCInst &Inst, unsigned N) const {
492 assert(N == 1 && "Invalid number of operands!");
493 Inst.addOperand(MCOperand::CreateImm(
494 ARM_AM::getSORegOpc(Shift.ShiftTy, 0)));
497 void addRegListOperands(MCInst &Inst, unsigned N) const {
498 assert(N == 1 && "Invalid number of operands!");
499 const SmallVectorImpl<unsigned> &RegList = getRegList();
500 for (SmallVectorImpl<unsigned>::const_iterator
501 I = RegList.begin(), E = RegList.end(); I != E; ++I)
502 Inst.addOperand(MCOperand::CreateReg(*I));
505 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
506 addRegListOperands(Inst, N);
509 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
510 addRegListOperands(Inst, N);
513 void addImmOperands(MCInst &Inst, unsigned N) const {
514 assert(N == 1 && "Invalid number of operands!");
515 addExpr(Inst, getImm());
518 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
519 assert(N == 1 && "Invalid number of operands!");
520 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
523 void addMemMode7Operands(MCInst &Inst, unsigned N) const {
524 assert(N == 1 && isMemMode7() && "Invalid number of operands!");
525 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
527 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
529 assert((CE || CE->getValue() == 0) &&
530 "No offset operand support in mode 7");
533 void addMemMode2Operands(MCInst &Inst, unsigned N) const {
534 assert(isMemMode2() && "Invalid mode or number of operands!");
535 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
536 unsigned IdxMode = (getMemPreindexed() | getMemPostindexed() << 1);
538 if (getMemOffsetIsReg()) {
539 Inst.addOperand(MCOperand::CreateReg(getMemOffsetRegNum()));
541 ARM_AM::AddrOpc AMOpc = getMemNegative() ? ARM_AM::sub : ARM_AM::add;
542 ARM_AM::ShiftOpc ShOpc = ARM_AM::no_shift;
543 int64_t ShiftAmount = 0;
545 if (getMemOffsetRegShifted()) {
546 ShOpc = getMemShiftType();
547 const MCConstantExpr *CE =
548 dyn_cast<MCConstantExpr>(getMemShiftAmount());
549 ShiftAmount = CE->getValue();
552 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(AMOpc, ShiftAmount,
557 // Create a operand placeholder to always yield the same number of operands.
558 Inst.addOperand(MCOperand::CreateReg(0));
560 // FIXME: #-0 is encoded differently than #0. Does the parser preserve
562 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
563 assert(CE && "Non-constant mode 2 offset operand!");
564 int64_t Offset = CE->getValue();
567 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(ARM_AM::add,
568 Offset, ARM_AM::no_shift, IdxMode)));
570 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(ARM_AM::sub,
571 -Offset, ARM_AM::no_shift, IdxMode)));
574 void addMemMode3Operands(MCInst &Inst, unsigned N) const {
575 assert(isMemMode3() && "Invalid mode or number of operands!");
576 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
577 unsigned IdxMode = (getMemPreindexed() | getMemPostindexed() << 1);
579 if (getMemOffsetIsReg()) {
580 Inst.addOperand(MCOperand::CreateReg(getMemOffsetRegNum()));
582 ARM_AM::AddrOpc AMOpc = getMemNegative() ? ARM_AM::sub : ARM_AM::add;
583 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM3Opc(AMOpc, 0,
588 // Create a operand placeholder to always yield the same number of operands.
589 Inst.addOperand(MCOperand::CreateReg(0));
591 // FIXME: #-0 is encoded differently than #0. Does the parser preserve
593 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
594 assert(CE && "Non-constant mode 3 offset operand!");
595 int64_t Offset = CE->getValue();
598 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM3Opc(ARM_AM::add,
601 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM3Opc(ARM_AM::sub,
605 void addMemMode5Operands(MCInst &Inst, unsigned N) const {
606 assert(N == 2 && isMemMode5() && "Invalid number of operands!");
608 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
609 assert(!getMemOffsetIsReg() && "Invalid mode 5 operand");
611 // FIXME: #-0 is encoded differently than #0. Does the parser preserve
613 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
614 assert(CE && "Non-constant mode 5 offset operand!");
616 // The MCInst offset operand doesn't include the low two bits (like
617 // the instruction encoding).
618 int64_t Offset = CE->getValue() / 4;
620 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add,
623 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub,
627 void addMemModeRegThumbOperands(MCInst &Inst, unsigned N) const {
628 assert(N == 2 && isMemModeRegThumb() && "Invalid number of operands!");
629 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
630 Inst.addOperand(MCOperand::CreateReg(getMemOffsetRegNum()));
633 void addMemModeImmThumbOperands(MCInst &Inst, unsigned N) const {
634 assert(N == 2 && isMemModeImmThumb() && "Invalid number of operands!");
635 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
636 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
637 assert(CE && "Non-constant mode offset operand!");
638 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
641 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
642 assert(N == 1 && "Invalid number of operands!");
643 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
646 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
647 assert(N == 1 && "Invalid number of operands!");
648 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
651 virtual void dump(raw_ostream &OS) const;
653 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
654 ARMOperand *Op = new ARMOperand(CondCode);
661 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
662 ARMOperand *Op = new ARMOperand(CoprocNum);
663 Op->Cop.Val = CopVal;
669 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
670 ARMOperand *Op = new ARMOperand(CoprocReg);
671 Op->Cop.Val = CopVal;
677 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
678 ARMOperand *Op = new ARMOperand(CCOut);
679 Op->Reg.RegNum = RegNum;
685 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
686 ARMOperand *Op = new ARMOperand(Token);
687 Op->Tok.Data = Str.data();
688 Op->Tok.Length = Str.size();
694 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
695 ARMOperand *Op = new ARMOperand(Register);
696 Op->Reg.RegNum = RegNum;
702 static ARMOperand *CreateShifter(ARM_AM::ShiftOpc ShTy,
704 ARMOperand *Op = new ARMOperand(Shifter);
705 Op->Shift.ShiftTy = ShTy;
712 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
713 SMLoc StartLoc, SMLoc EndLoc) {
714 KindTy Kind = RegisterList;
716 if (ARM::DPRRegClass.contains(Regs.front().first))
717 Kind = DPRRegisterList;
718 else if (ARM::SPRRegClass.contains(Regs.front().first))
719 Kind = SPRRegisterList;
721 ARMOperand *Op = new ARMOperand(Kind);
722 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
723 I = Regs.begin(), E = Regs.end(); I != E; ++I)
724 Op->Registers.push_back(I->first);
725 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
726 Op->StartLoc = StartLoc;
731 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
732 ARMOperand *Op = new ARMOperand(Immediate);
739 static ARMOperand *CreateMem(ARMII::AddrMode AddrMode, unsigned BaseRegNum,
740 bool OffsetIsReg, const MCExpr *Offset,
741 int OffsetRegNum, bool OffsetRegShifted,
742 enum ARM_AM::ShiftOpc ShiftType,
743 const MCExpr *ShiftAmount, bool Preindexed,
744 bool Postindexed, bool Negative, bool Writeback,
746 assert((OffsetRegNum == -1 || OffsetIsReg) &&
747 "OffsetRegNum must imply OffsetIsReg!");
748 assert((!OffsetRegShifted || OffsetIsReg) &&
749 "OffsetRegShifted must imply OffsetIsReg!");
750 assert((Offset || OffsetIsReg) &&
751 "Offset must exists unless register offset is used!");
752 assert((!ShiftAmount || (OffsetIsReg && OffsetRegShifted)) &&
753 "Cannot have shift amount without shifted register offset!");
754 assert((!Offset || !OffsetIsReg) &&
755 "Cannot have expression offset and register offset!");
757 ARMOperand *Op = new ARMOperand(Memory);
758 Op->Mem.AddrMode = AddrMode;
759 Op->Mem.BaseRegNum = BaseRegNum;
760 Op->Mem.OffsetIsReg = OffsetIsReg;
762 Op->Mem.Offset.RegNum = OffsetRegNum;
764 Op->Mem.Offset.Value = Offset;
765 Op->Mem.OffsetRegShifted = OffsetRegShifted;
766 Op->Mem.ShiftType = ShiftType;
767 Op->Mem.ShiftAmount = ShiftAmount;
768 Op->Mem.Preindexed = Preindexed;
769 Op->Mem.Postindexed = Postindexed;
770 Op->Mem.Negative = Negative;
771 Op->Mem.Writeback = Writeback;
778 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
779 ARMOperand *Op = new ARMOperand(MemBarrierOpt);
786 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
787 ARMOperand *Op = new ARMOperand(ProcIFlags);
788 Op->IFlags.Val = IFlags;
794 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
795 ARMOperand *Op = new ARMOperand(MSRMask);
796 Op->MMask.Val = MMask;
803 } // end anonymous namespace.
805 void ARMOperand::dump(raw_ostream &OS) const {
808 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
811 OS << "<ccout " << getReg() << ">";
814 OS << "<coprocessor number: " << getCoproc() << ">";
817 OS << "<coprocessor register: " << getCoproc() << ">";
820 OS << "<mask: " << getMSRMask() << ">";
826 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
830 << "am:" << ARMII::AddrModeToString(getMemAddrMode())
831 << " base:" << getMemBaseRegNum();
832 if (getMemOffsetIsReg()) {
833 OS << " offset:<register " << getMemOffsetRegNum();
834 if (getMemOffsetRegShifted()) {
835 OS << " offset-shift-type:" << getMemShiftType();
836 OS << " offset-shift-amount:" << *getMemShiftAmount();
839 OS << " offset:" << *getMemOffset();
841 if (getMemOffsetIsReg())
842 OS << " (offset-is-reg)";
843 if (getMemPreindexed())
844 OS << " (pre-indexed)";
845 if (getMemPostindexed())
846 OS << " (post-indexed)";
847 if (getMemNegative())
849 if (getMemWriteback())
850 OS << " (writeback)";
855 unsigned IFlags = getProcIFlags();
856 for (int i=2; i >= 0; --i)
857 if (IFlags & (1 << i))
858 OS << ARM_PROC::IFlagsToString(1 << i);
863 OS << "<register " << getReg() << ">";
866 OS << "<shifter " << getShiftOpcStr(Shift.ShiftTy) << ">";
869 case DPRRegisterList:
870 case SPRRegisterList: {
871 OS << "<register_list ";
873 const SmallVectorImpl<unsigned> &RegList = getRegList();
874 for (SmallVectorImpl<unsigned>::const_iterator
875 I = RegList.begin(), E = RegList.end(); I != E; ) {
877 if (++I < E) OS << ", ";
884 OS << "'" << getToken() << "'";
889 /// @name Auto-generated Match Functions
892 static unsigned MatchRegisterName(StringRef Name);
896 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
897 SMLoc &StartLoc, SMLoc &EndLoc) {
898 RegNo = TryParseRegister();
900 return (RegNo == (unsigned)-1);
903 /// Try to parse a register name. The token must be an Identifier when called,
904 /// and if it is a register name the token is eaten and the register number is
905 /// returned. Otherwise return -1.
907 int ARMAsmParser::TryParseRegister() {
908 const AsmToken &Tok = Parser.getTok();
909 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
911 // FIXME: Validate register for the current architecture; we have to do
912 // validation later, so maybe there is no need for this here.
913 std::string upperCase = Tok.getString().str();
914 std::string lowerCase = LowercaseString(upperCase);
915 unsigned RegNum = MatchRegisterName(lowerCase);
917 RegNum = StringSwitch<unsigned>(lowerCase)
918 .Case("r13", ARM::SP)
919 .Case("r14", ARM::LR)
920 .Case("r15", ARM::PC)
921 .Case("ip", ARM::R12)
924 if (!RegNum) return -1;
926 Parser.Lex(); // Eat identifier token.
930 /// Try to parse a register name. The token must be an Identifier when called,
931 /// and if it is a register name the token is eaten and the register number is
932 /// returned. Otherwise return -1.
934 bool ARMAsmParser::TryParseShiftRegister(
935 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
936 SMLoc S = Parser.getTok().getLoc();
937 const AsmToken &Tok = Parser.getTok();
938 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
940 std::string upperCase = Tok.getString().str();
941 std::string lowerCase = LowercaseString(upperCase);
942 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
943 .Case("lsl", ARM_AM::lsl)
944 .Case("lsr", ARM_AM::lsr)
945 .Case("asr", ARM_AM::asr)
946 .Case("ror", ARM_AM::ror)
947 .Case("rrx", ARM_AM::rrx)
948 .Default(ARM_AM::no_shift);
950 if (ShiftTy == ARM_AM::no_shift)
953 Parser.Lex(); // Eat shift-type operand;
954 int RegNum = TryParseRegister();
956 return Error(Parser.getTok().getLoc(), "register expected");
958 Operands.push_back(ARMOperand::CreateReg(RegNum,S, Parser.getTok().getLoc()));
959 Operands.push_back(ARMOperand::CreateShifter(ShiftTy,
960 S, Parser.getTok().getLoc()));
966 /// Try to parse a register name. The token must be an Identifier when called.
967 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
968 /// if there is a "writeback". 'true' if it's not a register.
970 /// TODO this is likely to change to allow different register types and or to
971 /// parse for a specific register type.
973 TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
974 SMLoc S = Parser.getTok().getLoc();
975 int RegNo = TryParseRegister();
979 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
981 const AsmToken &ExclaimTok = Parser.getTok();
982 if (ExclaimTok.is(AsmToken::Exclaim)) {
983 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
984 ExclaimTok.getLoc()));
985 Parser.Lex(); // Eat exclaim token
991 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
992 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
994 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
995 // Use the same layout as the tablegen'erated register name matcher. Ugly,
997 switch (Name.size()) {
1000 if (Name[0] != CoprocOp)
1017 if (Name[0] != CoprocOp || Name[1] != '1')
1021 case '0': return 10;
1022 case '1': return 11;
1023 case '2': return 12;
1024 case '3': return 13;
1025 case '4': return 14;
1026 case '5': return 15;
1034 /// tryParseCoprocNumOperand - Try to parse an coprocessor number operand. The
1035 /// token must be an Identifier when called, and if it is a coprocessor
1036 /// number, the token is eaten and the operand is added to the operand list.
1037 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1038 tryParseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1039 SMLoc S = Parser.getTok().getLoc();
1040 const AsmToken &Tok = Parser.getTok();
1041 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1043 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
1045 return MatchOperand_NoMatch;
1047 Parser.Lex(); // Eat identifier token.
1048 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
1049 return MatchOperand_Success;
1052 /// tryParseCoprocRegOperand - Try to parse an coprocessor register operand. The
1053 /// token must be an Identifier when called, and if it is a coprocessor
1054 /// number, the token is eaten and the operand is added to the operand list.
1055 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1056 tryParseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1057 SMLoc S = Parser.getTok().getLoc();
1058 const AsmToken &Tok = Parser.getTok();
1059 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1061 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
1063 return MatchOperand_NoMatch;
1065 Parser.Lex(); // Eat identifier token.
1066 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
1067 return MatchOperand_Success;
1070 /// Parse a register list, return it if successful else return null. The first
1071 /// token must be a '{' when called.
1073 ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1074 assert(Parser.getTok().is(AsmToken::LCurly) &&
1075 "Token is not a Left Curly Brace");
1076 SMLoc S = Parser.getTok().getLoc();
1078 // Read the rest of the registers in the list.
1079 unsigned PrevRegNum = 0;
1080 SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
1083 bool IsRange = Parser.getTok().is(AsmToken::Minus);
1084 Parser.Lex(); // Eat non-identifier token.
1086 const AsmToken &RegTok = Parser.getTok();
1087 SMLoc RegLoc = RegTok.getLoc();
1088 if (RegTok.isNot(AsmToken::Identifier)) {
1089 Error(RegLoc, "register expected");
1093 int RegNum = TryParseRegister();
1095 Error(RegLoc, "register expected");
1100 int Reg = PrevRegNum;
1103 Registers.push_back(std::make_pair(Reg, RegLoc));
1104 } while (Reg != RegNum);
1106 Registers.push_back(std::make_pair(RegNum, RegLoc));
1109 PrevRegNum = RegNum;
1110 } while (Parser.getTok().is(AsmToken::Comma) ||
1111 Parser.getTok().is(AsmToken::Minus));
1113 // Process the right curly brace of the list.
1114 const AsmToken &RCurlyTok = Parser.getTok();
1115 if (RCurlyTok.isNot(AsmToken::RCurly)) {
1116 Error(RCurlyTok.getLoc(), "'}' expected");
1120 SMLoc E = RCurlyTok.getLoc();
1121 Parser.Lex(); // Eat right curly brace token.
1123 // Verify the register list.
1124 SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1125 RI = Registers.begin(), RE = Registers.end();
1127 unsigned HighRegNum = getARMRegisterNumbering(RI->first);
1128 bool EmittedWarning = false;
1130 DenseMap<unsigned, bool> RegMap;
1131 RegMap[HighRegNum] = true;
1133 for (++RI; RI != RE; ++RI) {
1134 const std::pair<unsigned, SMLoc> &RegInfo = *RI;
1135 unsigned Reg = getARMRegisterNumbering(RegInfo.first);
1138 Error(RegInfo.second, "register duplicated in register list");
1142 if (!EmittedWarning && Reg < HighRegNum)
1143 Warning(RegInfo.second,
1144 "register not in ascending order in register list");
1147 HighRegNum = std::max(Reg, HighRegNum);
1150 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
1154 /// tryParseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
1155 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1156 tryParseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1157 SMLoc S = Parser.getTok().getLoc();
1158 const AsmToken &Tok = Parser.getTok();
1159 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1160 StringRef OptStr = Tok.getString();
1162 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
1163 .Case("sy", ARM_MB::SY)
1164 .Case("st", ARM_MB::ST)
1165 .Case("ish", ARM_MB::ISH)
1166 .Case("ishst", ARM_MB::ISHST)
1167 .Case("nsh", ARM_MB::NSH)
1168 .Case("nshst", ARM_MB::NSHST)
1169 .Case("osh", ARM_MB::OSH)
1170 .Case("oshst", ARM_MB::OSHST)
1174 return MatchOperand_NoMatch;
1176 Parser.Lex(); // Eat identifier token.
1177 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
1178 return MatchOperand_Success;
1181 /// tryParseProcIFlagsOperand - Try to parse iflags from CPS instruction.
1182 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1183 tryParseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1184 SMLoc S = Parser.getTok().getLoc();
1185 const AsmToken &Tok = Parser.getTok();
1186 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1187 StringRef IFlagsStr = Tok.getString();
1189 unsigned IFlags = 0;
1190 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
1191 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
1192 .Case("a", ARM_PROC::A)
1193 .Case("i", ARM_PROC::I)
1194 .Case("f", ARM_PROC::F)
1197 // If some specific iflag is already set, it means that some letter is
1198 // present more than once, this is not acceptable.
1199 if (Flag == ~0U || (IFlags & Flag))
1200 return MatchOperand_NoMatch;
1205 Parser.Lex(); // Eat identifier token.
1206 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
1207 return MatchOperand_Success;
1210 /// tryParseMSRMaskOperand - Try to parse mask flags from MSR instruction.
1211 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1212 tryParseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1213 SMLoc S = Parser.getTok().getLoc();
1214 const AsmToken &Tok = Parser.getTok();
1215 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1216 StringRef Mask = Tok.getString();
1218 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
1219 size_t Start = 0, Next = Mask.find('_');
1220 StringRef Flags = "";
1221 StringRef SpecReg = Mask.slice(Start, Next);
1222 if (Next != StringRef::npos)
1223 Flags = Mask.slice(Next+1, Mask.size());
1225 // FlagsVal contains the complete mask:
1227 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1228 unsigned FlagsVal = 0;
1230 if (SpecReg == "apsr") {
1231 FlagsVal = StringSwitch<unsigned>(Flags)
1232 .Case("nzcvq", 0x8) // same as CPSR_c
1233 .Case("g", 0x4) // same as CPSR_s
1234 .Case("nzcvqg", 0xc) // same as CPSR_fs
1237 if (FlagsVal == ~0U) {
1239 return MatchOperand_NoMatch;
1241 FlagsVal = 0; // No flag
1243 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
1244 if (Flags == "all") // cpsr_all is an alias for cpsr_fc
1246 for (int i = 0, e = Flags.size(); i != e; ++i) {
1247 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
1254 // If some specific flag is already set, it means that some letter is
1255 // present more than once, this is not acceptable.
1256 if (FlagsVal == ~0U || (FlagsVal & Flag))
1257 return MatchOperand_NoMatch;
1260 } else // No match for special register.
1261 return MatchOperand_NoMatch;
1263 // Special register without flags are equivalent to "fc" flags.
1267 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1268 if (SpecReg == "spsr")
1271 Parser.Lex(); // Eat identifier token.
1272 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
1273 return MatchOperand_Success;
1276 /// tryParseMemMode2Operand - Try to parse memory addressing mode 2 operand.
1277 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1278 tryParseMemMode2Operand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1279 assert(Parser.getTok().is(AsmToken::LBrac) && "Token is not a \"[\"");
1281 if (ParseMemory(Operands, ARMII::AddrMode2))
1282 return MatchOperand_NoMatch;
1284 return MatchOperand_Success;
1287 /// tryParseMemMode3Operand - Try to parse memory addressing mode 3 operand.
1288 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1289 tryParseMemMode3Operand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1290 assert(Parser.getTok().is(AsmToken::LBrac) && "Token is not a \"[\"");
1292 if (ParseMemory(Operands, ARMII::AddrMode3))
1293 return MatchOperand_NoMatch;
1295 return MatchOperand_Success;
1298 /// CvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
1299 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
1300 /// when they refer multiple MIOperands inside a single one.
1302 CvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
1303 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1304 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
1306 // Create a writeback register dummy placeholder.
1307 Inst.addOperand(MCOperand::CreateImm(0));
1309 ((ARMOperand*)Operands[3])->addMemMode2Operands(Inst, 3);
1310 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
1314 /// CvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
1315 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
1316 /// when they refer multiple MIOperands inside a single one.
1318 CvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
1319 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1320 // Create a writeback register dummy placeholder.
1321 Inst.addOperand(MCOperand::CreateImm(0));
1322 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
1323 ((ARMOperand*)Operands[3])->addMemMode2Operands(Inst, 3);
1324 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
1328 /// CvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
1329 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
1330 /// when they refer multiple MIOperands inside a single one.
1332 CvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
1333 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1334 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
1336 // Create a writeback register dummy placeholder.
1337 Inst.addOperand(MCOperand::CreateImm(0));
1339 ((ARMOperand*)Operands[3])->addMemMode3Operands(Inst, 3);
1340 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
1344 /// CvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
1345 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
1346 /// when they refer multiple MIOperands inside a single one.
1348 CvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
1349 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1350 // Create a writeback register dummy placeholder.
1351 Inst.addOperand(MCOperand::CreateImm(0));
1352 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
1353 ((ARMOperand*)Operands[3])->addMemMode3Operands(Inst, 3);
1354 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
1358 /// Parse an ARM memory expression, return false if successful else return true
1359 /// or an error. The first token must be a '[' when called.
1361 /// TODO Only preindexing and postindexing addressing are started, unindexed
1362 /// with option, etc are still to do.
1364 ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1365 ARMII::AddrMode AddrMode = ARMII::AddrModeNone) {
1367 assert(Parser.getTok().is(AsmToken::LBrac) &&
1368 "Token is not a Left Bracket");
1369 S = Parser.getTok().getLoc();
1370 Parser.Lex(); // Eat left bracket token.
1372 const AsmToken &BaseRegTok = Parser.getTok();
1373 if (BaseRegTok.isNot(AsmToken::Identifier)) {
1374 Error(BaseRegTok.getLoc(), "register expected");
1377 int BaseRegNum = TryParseRegister();
1378 if (BaseRegNum == -1) {
1379 Error(BaseRegTok.getLoc(), "register expected");
1383 // The next token must either be a comma or a closing bracket.
1384 const AsmToken &Tok = Parser.getTok();
1385 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
1388 bool Preindexed = false;
1389 bool Postindexed = false;
1390 bool OffsetIsReg = false;
1391 bool Negative = false;
1392 bool Writeback = false;
1393 ARMOperand *WBOp = 0;
1394 int OffsetRegNum = -1;
1395 bool OffsetRegShifted = false;
1396 enum ARM_AM::ShiftOpc ShiftType = ARM_AM::lsl;
1397 const MCExpr *ShiftAmount = 0;
1398 const MCExpr *Offset = 0;
1400 // First look for preindexed address forms, that is after the "[Rn" we now
1401 // have to see if the next token is a comma.
1402 if (Tok.is(AsmToken::Comma)) {
1404 Parser.Lex(); // Eat comma token.
1406 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
1407 Offset, OffsetIsReg, OffsetRegNum, E))
1409 const AsmToken &RBracTok = Parser.getTok();
1410 if (RBracTok.isNot(AsmToken::RBrac)) {
1411 Error(RBracTok.getLoc(), "']' expected");
1414 E = RBracTok.getLoc();
1415 Parser.Lex(); // Eat right bracket token.
1417 const AsmToken &ExclaimTok = Parser.getTok();
1418 if (ExclaimTok.is(AsmToken::Exclaim)) {
1419 // None of addrmode3 instruction uses "!"
1420 if (AddrMode == ARMII::AddrMode3)
1423 WBOp = ARMOperand::CreateToken(ExclaimTok.getString(),
1424 ExclaimTok.getLoc());
1426 Parser.Lex(); // Eat exclaim token
1427 } else { // In addressing mode 2, pre-indexed mode always end with "!"
1428 if (AddrMode == ARMII::AddrMode2)
1432 // The "[Rn" we have so far was not followed by a comma.
1434 // If there's anything other than the right brace, this is a post indexing
1437 Parser.Lex(); // Eat right bracket token.
1439 const AsmToken &NextTok = Parser.getTok();
1441 if (NextTok.isNot(AsmToken::EndOfStatement)) {
1445 if (NextTok.isNot(AsmToken::Comma)) {
1446 Error(NextTok.getLoc(), "',' expected");
1450 Parser.Lex(); // Eat comma token.
1452 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
1453 ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
1459 // Force Offset to exist if used.
1462 Offset = MCConstantExpr::Create(0, getContext());
1464 if (AddrMode == ARMII::AddrMode3 && OffsetRegShifted) {
1465 Error(E, "shift amount not supported");
1470 Operands.push_back(ARMOperand::CreateMem(AddrMode, BaseRegNum, OffsetIsReg,
1471 Offset, OffsetRegNum, OffsetRegShifted,
1472 ShiftType, ShiftAmount, Preindexed,
1473 Postindexed, Negative, Writeback, S, E));
1475 Operands.push_back(WBOp);
1480 /// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
1481 /// we will parse the following (were +/- means that a plus or minus is
1486 /// we return false on success or an error otherwise.
1487 bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
1488 bool &OffsetRegShifted,
1489 enum ARM_AM::ShiftOpc &ShiftType,
1490 const MCExpr *&ShiftAmount,
1491 const MCExpr *&Offset,
1496 OffsetRegShifted = false;
1497 OffsetIsReg = false;
1499 const AsmToken &NextTok = Parser.getTok();
1500 E = NextTok.getLoc();
1501 if (NextTok.is(AsmToken::Plus))
1502 Parser.Lex(); // Eat plus token.
1503 else if (NextTok.is(AsmToken::Minus)) {
1505 Parser.Lex(); // Eat minus token
1507 // See if there is a register following the "[Rn," or "[Rn]," we have so far.
1508 const AsmToken &OffsetRegTok = Parser.getTok();
1509 if (OffsetRegTok.is(AsmToken::Identifier)) {
1510 SMLoc CurLoc = OffsetRegTok.getLoc();
1511 OffsetRegNum = TryParseRegister();
1512 if (OffsetRegNum != -1) {
1518 // If we parsed a register as the offset then there can be a shift after that.
1519 if (OffsetRegNum != -1) {
1520 // Look for a comma then a shift
1521 const AsmToken &Tok = Parser.getTok();
1522 if (Tok.is(AsmToken::Comma)) {
1523 Parser.Lex(); // Eat comma token.
1525 const AsmToken &Tok = Parser.getTok();
1526 if (ParseShift(ShiftType, ShiftAmount, E))
1527 return Error(Tok.getLoc(), "shift expected");
1528 OffsetRegShifted = true;
1531 else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
1532 // Look for #offset following the "[Rn," or "[Rn],"
1533 const AsmToken &HashTok = Parser.getTok();
1534 if (HashTok.isNot(AsmToken::Hash))
1535 return Error(HashTok.getLoc(), "'#' expected");
1537 Parser.Lex(); // Eat hash token.
1539 if (getParser().ParseExpression(Offset))
1541 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1546 /// ParseShift as one of these two:
1547 /// ( lsl | lsr | asr | ror ) , # shift_amount
1549 /// and returns true if it parses a shift otherwise it returns false.
1550 bool ARMAsmParser::ParseShift(ARM_AM::ShiftOpc &St,
1551 const MCExpr *&ShiftAmount, SMLoc &E) {
1552 const AsmToken &Tok = Parser.getTok();
1553 if (Tok.isNot(AsmToken::Identifier))
1555 StringRef ShiftName = Tok.getString();
1556 if (ShiftName == "lsl" || ShiftName == "LSL")
1558 else if (ShiftName == "lsr" || ShiftName == "LSR")
1560 else if (ShiftName == "asr" || ShiftName == "ASR")
1562 else if (ShiftName == "ror" || ShiftName == "ROR")
1564 else if (ShiftName == "rrx" || ShiftName == "RRX")
1568 Parser.Lex(); // Eat shift type token.
1570 // Rrx stands alone.
1571 if (St == ARM_AM::rrx)
1574 // Otherwise, there must be a '#' and a shift amount.
1575 const AsmToken &HashTok = Parser.getTok();
1576 if (HashTok.isNot(AsmToken::Hash))
1577 return Error(HashTok.getLoc(), "'#' expected");
1578 Parser.Lex(); // Eat hash token.
1580 if (getParser().ParseExpression(ShiftAmount))
1586 /// Parse a arm instruction operand. For now this parses the operand regardless
1587 /// of the mnemonic.
1588 bool ARMAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1589 StringRef Mnemonic) {
1592 // Check if the current operand has a custom associated parser, if so, try to
1593 // custom parse the operand, or fallback to the general approach.
1594 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1595 if (ResTy == MatchOperand_Success)
1597 // If there wasn't a custom match, try the generic matcher below. Otherwise,
1598 // there was a match, but an error occurred, in which case, just return that
1599 // the operand parsing failed.
1600 if (ResTy == MatchOperand_ParseFail)
1603 switch (getLexer().getKind()) {
1605 Error(Parser.getTok().getLoc(), "unexpected token in operand");
1607 case AsmToken::Identifier:
1608 if (!TryParseRegisterWithWriteBack(Operands))
1610 if (!TryParseShiftRegister(Operands))
1614 // Fall though for the Identifier case that is not a register or a
1616 case AsmToken::Integer: // things like 1f and 2b as a branch targets
1617 case AsmToken::Dot: { // . as a branch target
1618 // This was not a register so parse other operands that start with an
1619 // identifier (like labels) as expressions and create them as immediates.
1620 const MCExpr *IdVal;
1621 S = Parser.getTok().getLoc();
1622 if (getParser().ParseExpression(IdVal))
1624 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1625 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
1628 case AsmToken::LBrac:
1629 return ParseMemory(Operands);
1630 case AsmToken::LCurly:
1631 return ParseRegisterList(Operands);
1632 case AsmToken::Hash:
1633 // #42 -> immediate.
1634 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
1635 S = Parser.getTok().getLoc();
1637 const MCExpr *ImmVal;
1638 if (getParser().ParseExpression(ImmVal))
1640 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1641 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
1643 case AsmToken::Colon: {
1644 // ":lower16:" and ":upper16:" expression prefixes
1645 // FIXME: Check it's an expression prefix,
1646 // e.g. (FOO - :lower16:BAR) isn't legal.
1647 ARMMCExpr::VariantKind RefKind;
1648 if (ParsePrefix(RefKind))
1651 const MCExpr *SubExprVal;
1652 if (getParser().ParseExpression(SubExprVal))
1655 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
1657 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1658 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
1664 // ParsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
1665 // :lower16: and :upper16:.
1666 bool ARMAsmParser::ParsePrefix(ARMMCExpr::VariantKind &RefKind) {
1667 RefKind = ARMMCExpr::VK_ARM_None;
1669 // :lower16: and :upper16: modifiers
1670 assert(getLexer().is(AsmToken::Colon) && "expected a :");
1671 Parser.Lex(); // Eat ':'
1673 if (getLexer().isNot(AsmToken::Identifier)) {
1674 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
1678 StringRef IDVal = Parser.getTok().getIdentifier();
1679 if (IDVal == "lower16") {
1680 RefKind = ARMMCExpr::VK_ARM_LO16;
1681 } else if (IDVal == "upper16") {
1682 RefKind = ARMMCExpr::VK_ARM_HI16;
1684 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
1689 if (getLexer().isNot(AsmToken::Colon)) {
1690 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
1693 Parser.Lex(); // Eat the last ':'
1698 ARMAsmParser::ApplyPrefixToExpr(const MCExpr *E,
1699 MCSymbolRefExpr::VariantKind Variant) {
1700 // Recurse over the given expression, rebuilding it to apply the given variant
1701 // to the leftmost symbol.
1702 if (Variant == MCSymbolRefExpr::VK_None)
1705 switch (E->getKind()) {
1706 case MCExpr::Target:
1707 llvm_unreachable("Can't handle target expr yet");
1708 case MCExpr::Constant:
1709 llvm_unreachable("Can't handle lower16/upper16 of constant yet");
1711 case MCExpr::SymbolRef: {
1712 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1714 if (SRE->getKind() != MCSymbolRefExpr::VK_None)
1717 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext());
1721 llvm_unreachable("Can't handle unary expressions yet");
1723 case MCExpr::Binary: {
1724 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1725 const MCExpr *LHS = ApplyPrefixToExpr(BE->getLHS(), Variant);
1726 const MCExpr *RHS = BE->getRHS();
1730 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext());
1734 assert(0 && "Invalid expression kind!");
1738 /// \brief Given a mnemonic, split out possible predication code and carry
1739 /// setting letters to form a canonical mnemonic and flags.
1741 // FIXME: Would be nice to autogen this.
1742 static StringRef SplitMnemonic(StringRef Mnemonic,
1743 unsigned &PredicationCode,
1745 unsigned &ProcessorIMod) {
1746 PredicationCode = ARMCC::AL;
1747 CarrySetting = false;
1750 // Ignore some mnemonics we know aren't predicated forms.
1752 // FIXME: Would be nice to autogen this.
1753 if (Mnemonic == "teq" || Mnemonic == "vceq" ||
1754 Mnemonic == "movs" ||
1755 Mnemonic == "svc" ||
1756 (Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
1757 Mnemonic == "vmls" || Mnemonic == "vnmls") ||
1758 Mnemonic == "vacge" || Mnemonic == "vcge" ||
1759 Mnemonic == "vclt" ||
1760 Mnemonic == "vacgt" || Mnemonic == "vcgt" ||
1761 Mnemonic == "vcle" ||
1762 (Mnemonic == "smlal" || Mnemonic == "umaal" || Mnemonic == "umlal" ||
1763 Mnemonic == "vabal" || Mnemonic == "vmlal" || Mnemonic == "vpadal" ||
1764 Mnemonic == "vqdmlal" || Mnemonic == "bics"))
1767 // First, split out any predication code.
1768 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
1769 .Case("eq", ARMCC::EQ)
1770 .Case("ne", ARMCC::NE)
1771 .Case("hs", ARMCC::HS)
1772 .Case("cs", ARMCC::HS)
1773 .Case("lo", ARMCC::LO)
1774 .Case("cc", ARMCC::LO)
1775 .Case("mi", ARMCC::MI)
1776 .Case("pl", ARMCC::PL)
1777 .Case("vs", ARMCC::VS)
1778 .Case("vc", ARMCC::VC)
1779 .Case("hi", ARMCC::HI)
1780 .Case("ls", ARMCC::LS)
1781 .Case("ge", ARMCC::GE)
1782 .Case("lt", ARMCC::LT)
1783 .Case("gt", ARMCC::GT)
1784 .Case("le", ARMCC::LE)
1785 .Case("al", ARMCC::AL)
1788 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
1789 PredicationCode = CC;
1792 // Next, determine if we have a carry setting bit. We explicitly ignore all
1793 // the instructions we know end in 's'.
1794 if (Mnemonic.endswith("s") &&
1795 !(Mnemonic == "asrs" || Mnemonic == "cps" || Mnemonic == "mls" ||
1796 Mnemonic == "movs" || Mnemonic == "mrs" || Mnemonic == "smmls" ||
1797 Mnemonic == "vabs" || Mnemonic == "vcls" || Mnemonic == "vmls" ||
1798 Mnemonic == "vmrs" || Mnemonic == "vnmls" || Mnemonic == "vqabs" ||
1799 Mnemonic == "vrecps" || Mnemonic == "vrsqrts")) {
1800 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
1801 CarrySetting = true;
1804 // The "cps" instruction can have a interrupt mode operand which is glued into
1805 // the mnemonic. Check if this is the case, split it and parse the imod op
1806 if (Mnemonic.startswith("cps")) {
1807 // Split out any imod code.
1809 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
1810 .Case("ie", ARM_PROC::IE)
1811 .Case("id", ARM_PROC::ID)
1814 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
1815 ProcessorIMod = IMod;
1822 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
1823 /// inclusion of carry set or predication code operands.
1825 // FIXME: It would be nice to autogen this.
1827 GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
1828 bool &CanAcceptPredicationCode) {
1829 bool isThumbOne = TM.getSubtarget<ARMSubtarget>().isThumb1Only();
1830 bool isThumb = TM.getSubtarget<ARMSubtarget>().isThumb();
1832 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
1833 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
1834 Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
1835 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
1836 Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" ||
1837 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
1838 Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
1839 Mnemonic == "eor" || Mnemonic == "smlal" ||
1840 (Mnemonic == "mov" && !isThumbOne)) {
1841 CanAcceptCarrySet = true;
1843 CanAcceptCarrySet = false;
1846 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
1847 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
1848 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
1849 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
1850 Mnemonic == "dsb" || Mnemonic == "movs" || Mnemonic == "isb" ||
1851 Mnemonic == "clrex" || Mnemonic.startswith("cps")) {
1852 CanAcceptPredicationCode = false;
1854 CanAcceptPredicationCode = true;
1858 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
1859 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp" ||
1860 (Mnemonic == "mov" && isThumbOne))
1861 CanAcceptPredicationCode = false;
1864 /// Parse an arm instruction mnemonic followed by its operands.
1865 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
1866 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1867 // Create the leading tokens for the mnemonic, split by '.' characters.
1868 size_t Start = 0, Next = Name.find('.');
1869 StringRef Head = Name.slice(Start, Next);
1871 // Split out the predication code and carry setting flag from the mnemonic.
1872 unsigned PredicationCode;
1873 unsigned ProcessorIMod;
1875 Head = SplitMnemonic(Head, PredicationCode, CarrySetting,
1878 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
1880 // Next, add the CCOut and ConditionCode operands, if needed.
1882 // For mnemonics which can ever incorporate a carry setting bit or predication
1883 // code, our matching model involves us always generating CCOut and
1884 // ConditionCode operands to match the mnemonic "as written" and then we let
1885 // the matcher deal with finding the right instruction or generating an
1886 // appropriate error.
1887 bool CanAcceptCarrySet, CanAcceptPredicationCode;
1888 GetMnemonicAcceptInfo(Head, CanAcceptCarrySet, CanAcceptPredicationCode);
1890 // Add the carry setting operand, if necessary.
1892 // FIXME: It would be awesome if we could somehow invent a location such that
1893 // match errors on this operand would print a nice diagnostic about how the
1894 // 's' character in the mnemonic resulted in a CCOut operand.
1895 if (CanAcceptCarrySet) {
1896 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
1899 // This mnemonic can't ever accept a carry set, but the user wrote one (or
1900 // misspelled another mnemonic).
1902 // FIXME: Issue a nice error.
1905 // Add the predication code operand, if necessary.
1906 if (CanAcceptPredicationCode) {
1907 Operands.push_back(ARMOperand::CreateCondCode(
1908 ARMCC::CondCodes(PredicationCode), NameLoc));
1910 // This mnemonic can't ever accept a predication code, but the user wrote
1911 // one (or misspelled another mnemonic).
1913 // FIXME: Issue a nice error.
1916 // Add the processor imod operand, if necessary.
1917 if (ProcessorIMod) {
1918 Operands.push_back(ARMOperand::CreateImm(
1919 MCConstantExpr::Create(ProcessorIMod, getContext()),
1922 // This mnemonic can't ever accept a imod, but the user wrote
1923 // one (or misspelled another mnemonic).
1925 // FIXME: Issue a nice error.
1928 // Add the remaining tokens in the mnemonic.
1929 while (Next != StringRef::npos) {
1931 Next = Name.find('.', Start + 1);
1932 StringRef ExtraToken = Name.slice(Start, Next);
1934 Operands.push_back(ARMOperand::CreateToken(ExtraToken, NameLoc));
1937 // Read the remaining operands.
1938 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1939 // Read the first operand.
1940 if (ParseOperand(Operands, Head)) {
1941 Parser.EatToEndOfStatement();
1945 while (getLexer().is(AsmToken::Comma)) {
1946 Parser.Lex(); // Eat the comma.
1948 // Parse and remember the operand.
1949 if (ParseOperand(Operands, Head)) {
1950 Parser.EatToEndOfStatement();
1956 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1957 Parser.EatToEndOfStatement();
1958 return TokError("unexpected token in argument list");
1961 Parser.Lex(); // Consume the EndOfStatement
1966 MatchAndEmitInstruction(SMLoc IDLoc,
1967 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1971 MatchResultTy MatchResult, MatchResult2;
1972 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
1973 if (MatchResult != Match_Success) {
1974 // If we get a Match_InvalidOperand it might be some arithmetic instruction
1975 // that does not update the condition codes. So try adding a CCOut operand
1976 // with a value of reg0.
1977 if (MatchResult == Match_InvalidOperand) {
1978 Operands.insert(Operands.begin() + 1,
1979 ARMOperand::CreateCCOut(0,
1980 ((ARMOperand*)Operands[0])->getStartLoc()));
1981 MatchResult2 = MatchInstructionImpl(Operands, Inst, ErrorInfo);
1982 if (MatchResult2 == Match_Success)
1983 MatchResult = Match_Success;
1985 ARMOperand *CCOut = ((ARMOperand*)Operands[1]);
1986 Operands.erase(Operands.begin() + 1);
1990 // If we get a Match_MnemonicFail it might be some arithmetic instruction
1991 // that updates the condition codes if it ends in 's'. So see if the
1992 // mnemonic ends in 's' and if so try removing the 's' and adding a CCOut
1993 // operand with a value of CPSR.
1994 else if(MatchResult == Match_MnemonicFail) {
1995 // Get the instruction mnemonic, which is the first token.
1996 StringRef Mnemonic = ((ARMOperand*)Operands[0])->getToken();
1997 if (Mnemonic.substr(Mnemonic.size()-1) == "s") {
1998 // removed the 's' from the mnemonic for matching.
1999 StringRef MnemonicNoS = Mnemonic.slice(0, Mnemonic.size() - 1);
2000 SMLoc NameLoc = ((ARMOperand*)Operands[0])->getStartLoc();
2001 ARMOperand *OldMnemonic = ((ARMOperand*)Operands[0]);
2002 Operands.erase(Operands.begin());
2004 Operands.insert(Operands.begin(),
2005 ARMOperand::CreateToken(MnemonicNoS, NameLoc));
2006 Operands.insert(Operands.begin() + 1,
2007 ARMOperand::CreateCCOut(ARM::CPSR, NameLoc));
2008 MatchResult2 = MatchInstructionImpl(Operands, Inst, ErrorInfo);
2009 if (MatchResult2 == Match_Success)
2010 MatchResult = Match_Success;
2012 ARMOperand *OldMnemonic = ((ARMOperand*)Operands[0]);
2013 Operands.erase(Operands.begin());
2015 Operands.insert(Operands.begin(),
2016 ARMOperand::CreateToken(Mnemonic, NameLoc));
2017 ARMOperand *CCOut = ((ARMOperand*)Operands[1]);
2018 Operands.erase(Operands.begin() + 1);
2024 switch (MatchResult) {
2026 Out.EmitInstruction(Inst);
2028 case Match_MissingFeature:
2029 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
2031 case Match_InvalidOperand: {
2032 SMLoc ErrorLoc = IDLoc;
2033 if (ErrorInfo != ~0U) {
2034 if (ErrorInfo >= Operands.size())
2035 return Error(IDLoc, "too few operands for instruction");
2037 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
2038 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
2041 return Error(ErrorLoc, "invalid operand for instruction");
2043 case Match_MnemonicFail:
2044 return Error(IDLoc, "unrecognized instruction mnemonic");
2045 case Match_ConversionFail:
2046 return Error(IDLoc, "unable to convert operands to instruction");
2049 llvm_unreachable("Implement any new match types added!");
2053 /// ParseDirective parses the arm specific directives
2054 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
2055 StringRef IDVal = DirectiveID.getIdentifier();
2056 if (IDVal == ".word")
2057 return ParseDirectiveWord(4, DirectiveID.getLoc());
2058 else if (IDVal == ".thumb")
2059 return ParseDirectiveThumb(DirectiveID.getLoc());
2060 else if (IDVal == ".thumb_func")
2061 return ParseDirectiveThumbFunc(DirectiveID.getLoc());
2062 else if (IDVal == ".code")
2063 return ParseDirectiveCode(DirectiveID.getLoc());
2064 else if (IDVal == ".syntax")
2065 return ParseDirectiveSyntax(DirectiveID.getLoc());
2069 /// ParseDirectiveWord
2070 /// ::= .word [ expression (, expression)* ]
2071 bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
2072 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2074 const MCExpr *Value;
2075 if (getParser().ParseExpression(Value))
2078 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
2080 if (getLexer().is(AsmToken::EndOfStatement))
2083 // FIXME: Improve diagnostic.
2084 if (getLexer().isNot(AsmToken::Comma))
2085 return Error(L, "unexpected token in directive");
2094 /// ParseDirectiveThumb
2096 bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
2097 if (getLexer().isNot(AsmToken::EndOfStatement))
2098 return Error(L, "unexpected token in directive");
2101 // TODO: set thumb mode
2102 // TODO: tell the MC streamer the mode
2103 // getParser().getStreamer().Emit???();
2107 /// ParseDirectiveThumbFunc
2108 /// ::= .thumbfunc symbol_name
2109 bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
2110 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
2111 bool isMachO = MAI.hasSubsectionsViaSymbols();
2114 // Darwin asm has function name after .thumb_func direction
2117 const AsmToken &Tok = Parser.getTok();
2118 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
2119 return Error(L, "unexpected token in .thumb_func directive");
2120 Name = Tok.getString();
2121 Parser.Lex(); // Consume the identifier token.
2124 if (getLexer().isNot(AsmToken::EndOfStatement))
2125 return Error(L, "unexpected token in directive");
2128 // FIXME: assuming function name will be the line following .thumb_func
2130 Name = Parser.getTok().getString();
2133 // Mark symbol as a thumb symbol.
2134 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
2135 getParser().getStreamer().EmitThumbFunc(Func);
2139 /// ParseDirectiveSyntax
2140 /// ::= .syntax unified | divided
2141 bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
2142 const AsmToken &Tok = Parser.getTok();
2143 if (Tok.isNot(AsmToken::Identifier))
2144 return Error(L, "unexpected token in .syntax directive");
2145 StringRef Mode = Tok.getString();
2146 if (Mode == "unified" || Mode == "UNIFIED")
2148 else if (Mode == "divided" || Mode == "DIVIDED")
2149 return Error(L, "'.syntax divided' arm asssembly not supported");
2151 return Error(L, "unrecognized syntax mode in .syntax directive");
2153 if (getLexer().isNot(AsmToken::EndOfStatement))
2154 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
2157 // TODO tell the MC streamer the mode
2158 // getParser().getStreamer().Emit???();
2162 /// ParseDirectiveCode
2163 /// ::= .code 16 | 32
2164 bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
2165 const AsmToken &Tok = Parser.getTok();
2166 if (Tok.isNot(AsmToken::Integer))
2167 return Error(L, "unexpected token in .code directive");
2168 int64_t Val = Parser.getTok().getIntVal();
2174 return Error(L, "invalid operand to .code directive");
2176 if (getLexer().isNot(AsmToken::EndOfStatement))
2177 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
2180 // FIXME: We need to be able switch subtargets at this point so that
2181 // MatchInstructionImpl() will work when it gets the AvailableFeatures which
2182 // includes Feature_IsThumb or not to match the right instructions. This is
2183 // blocked on the FIXME in llvm-mc.cpp when creating the TargetMachine.
2185 assert(TM.getSubtarget<ARMSubtarget>().isThumb() &&
2186 "switching between arm/thumb not yet suppported via .code 16)");
2187 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
2190 assert(!TM.getSubtarget<ARMSubtarget>().isThumb() &&
2191 "switching between thumb/arm not yet suppported via .code 32)");
2192 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
2198 extern "C" void LLVMInitializeARMAsmLexer();
2200 /// Force static initialization.
2201 extern "C" void LLVMInitializeARMAsmParser() {
2202 RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
2203 RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
2204 LLVMInitializeARMAsmLexer();
2207 #define GET_REGISTER_MATCHER
2208 #define GET_MATCHER_IMPLEMENTATION
2209 #include "ARMGenAsmMatcher.inc"