1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "llvm/ADT/SmallVector.h"
12 #include "llvm/ADT/Twine.h"
13 #include "llvm/MC/MCAsmLexer.h"
14 #include "llvm/MC/MCAsmParser.h"
15 #include "llvm/MC/MCStreamer.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/Support/SourceMgr.h"
19 #include "llvm/Target/TargetRegistry.h"
20 #include "llvm/Target/TargetAsmParser.h"
26 // The shift types for register controlled shifts in arm memory addressing
35 class ARMAsmParser : public TargetAsmParser {
39 MCAsmParser &getParser() const { return Parser; }
41 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
43 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
45 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
47 bool ParseRegister(ARMOperand &Op);
49 bool ParseRegisterList(ARMOperand &Op);
51 bool ParseMemory(ARMOperand &Op);
53 bool ParseShift(enum ShiftType *St, const MCExpr *&ShiftAmount);
55 bool ParseOperand(ARMOperand &Op);
57 bool ParseDirectiveWord(unsigned Size, SMLoc L);
59 bool ParseDirectiveThumb(SMLoc L);
61 bool ParseDirectiveThumbFunc(SMLoc L);
63 bool ParseDirectiveCode(SMLoc L);
65 bool ParseDirectiveSyntax(SMLoc L);
67 // TODO - For now hacked versions of the next two are in here in this file to
68 // allow some parser testing until the table gen versions are implemented.
70 /// @name Auto-generated Match Functions
72 bool MatchInstruction(SmallVectorImpl<ARMOperand> &Operands,
75 /// MatchRegisterName - Match the given string to a register name and return
76 /// its register number, or -1 if there is no match. To allow return values
77 /// to be used directly in register lists, arm registers have values between
79 int MatchRegisterName(const StringRef &Name);
85 ARMAsmParser(const Target &T, MCAsmParser &_Parser)
86 : TargetAsmParser(T), Parser(_Parser) {}
88 virtual bool ParseInstruction(const StringRef &Name, MCInst &Inst);
90 virtual bool ParseDirective(AsmToken DirectiveID);
93 } // end anonymous namespace
97 /// ARMOperand - Instances of this class represent a parsed ARM machine
123 // This is for all forms of ARM address expressions
127 const MCExpr *Offset; // used when OffsetIsReg is false
128 unsigned OffsetRegNum; // used when OffsetIsReg is true
129 bool OffsetRegShifted; // only used when OffsetIsReg is true
130 enum ShiftType ShiftType; // used when OffsetRegShifted is true
131 const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
134 bool Negative; // only used when OffsetIsReg is true
140 StringRef getToken() const {
141 assert(Kind == Token && "Invalid access!");
142 return StringRef(Tok.Data, Tok.Length);
145 unsigned getReg() const {
146 assert(Kind == Register && "Invalid access!");
150 const MCExpr *getImm() const {
151 assert(Kind == Immediate && "Invalid access!");
155 bool isToken() const {return Kind == Token; }
157 bool isReg() const { return Kind == Register; }
159 void addRegOperands(MCInst &Inst, unsigned N) const {
160 assert(N == 1 && "Invalid number of operands!");
161 Inst.addOperand(MCOperand::CreateReg(getReg()));
164 static ARMOperand CreateToken(StringRef Str) {
167 Res.Tok.Data = Str.data();
168 Res.Tok.Length = Str.size();
172 static ARMOperand CreateReg(unsigned RegNum, bool Writeback) {
175 Res.Reg.RegNum = RegNum;
176 Res.Reg.Writeback = Writeback;
180 static ARMOperand CreateImm(const MCExpr *Val) {
182 Res.Kind = Immediate;
187 static ARMOperand CreateMem(unsigned BaseRegNum, bool OffsetIsReg,
188 const MCExpr *Offset, unsigned OffsetRegNum,
189 bool OffsetRegShifted, enum ShiftType ShiftType,
190 const MCExpr *ShiftAmount, bool Preindexed,
191 bool Postindexed, bool Negative, bool Writeback) {
194 Res.Mem.BaseRegNum = BaseRegNum;
195 Res.Mem.OffsetIsReg = OffsetIsReg;
196 Res.Mem.Offset = Offset;
197 Res.Mem.OffsetRegNum = OffsetRegNum;
198 Res.Mem.OffsetRegShifted = OffsetRegShifted;
199 Res.Mem.ShiftType = ShiftType;
200 Res.Mem.ShiftAmount = ShiftAmount;
201 Res.Mem.Preindexed = Preindexed;
202 Res.Mem.Postindexed = Postindexed;
203 Res.Mem.Negative = Negative;
204 Res.Mem.Writeback = Writeback;
209 } // end anonymous namespace.
211 // Try to parse a register name. The token must be an Identifier when called,
212 // and if it is a register name a Reg operand is created, the token is eaten
213 // and false is returned. Else true is returned and no token is eaten.
214 // TODO this is likely to change to allow different register types and or to
215 // parse for a specific register type.
216 bool ARMAsmParser::ParseRegister(ARMOperand &Op) {
217 const AsmToken &Tok = getLexer().getTok();
218 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
220 // FIXME: Validate register for the current architecture; we have to do
221 // validation later, so maybe there is no need for this here.
224 RegNum = MatchRegisterName(Tok.getString());
227 getLexer().Lex(); // Eat identifier token.
229 bool Writeback = false;
230 const AsmToken &ExclaimTok = getLexer().getTok();
231 if (ExclaimTok.is(AsmToken::Exclaim)) {
233 getLexer().Lex(); // Eat exclaim token
236 Op = ARMOperand::CreateReg(RegNum, Writeback);
241 // Parse a register list, return false if successful else return true or an
242 // error. The first token must be a '{' when called.
243 bool ARMAsmParser::ParseRegisterList(ARMOperand &Op) {
244 assert(getLexer().getTok().is(AsmToken::LCurly) &&
245 "Token is not an Left Curly Brace");
246 getLexer().Lex(); // Eat left curly brace token.
248 const AsmToken &RegTok = getLexer().getTok();
249 SMLoc RegLoc = RegTok.getLoc();
250 if (RegTok.isNot(AsmToken::Identifier))
251 return Error(RegLoc, "register expected");
252 int RegNum = MatchRegisterName(RegTok.getString());
254 return Error(RegLoc, "register expected");
255 getLexer().Lex(); // Eat identifier token.
256 unsigned RegList = 1 << RegNum;
258 int HighRegNum = RegNum;
259 // TODO ranges like "{Rn-Rm}"
260 while (getLexer().getTok().is(AsmToken::Comma)) {
261 getLexer().Lex(); // Eat comma token.
263 const AsmToken &RegTok = getLexer().getTok();
264 SMLoc RegLoc = RegTok.getLoc();
265 if (RegTok.isNot(AsmToken::Identifier))
266 return Error(RegLoc, "register expected");
267 int RegNum = MatchRegisterName(RegTok.getString());
269 return Error(RegLoc, "register expected");
271 if (RegList & (1 << RegNum))
272 Warning(RegLoc, "register duplicated in register list");
273 else if (RegNum <= HighRegNum)
274 Warning(RegLoc, "register not in ascending order in register list");
275 RegList |= 1 << RegNum;
278 getLexer().Lex(); // Eat identifier token.
280 const AsmToken &RCurlyTok = getLexer().getTok();
281 if (RCurlyTok.isNot(AsmToken::RCurly))
282 return Error(RCurlyTok.getLoc(), "'}' expected");
283 getLexer().Lex(); // Eat left curly brace token.
288 // Parse an arm memory expression, return false if successful else return true
289 // or an error. The first token must be a '[' when called.
290 // TODO Only preindexing and postindexing addressing are started, unindexed
291 // with option, etc are still to do.
292 bool ARMAsmParser::ParseMemory(ARMOperand &Op) {
293 assert(getLexer().getTok().is(AsmToken::LBrac) &&
294 "Token is not an Left Bracket");
295 getLexer().Lex(); // Eat left bracket token.
297 const AsmToken &BaseRegTok = getLexer().getTok();
298 if (BaseRegTok.isNot(AsmToken::Identifier))
299 return Error(BaseRegTok.getLoc(), "register expected");
300 int BaseRegNum = MatchRegisterName(BaseRegTok.getString());
301 if (BaseRegNum == -1)
302 return Error(BaseRegTok.getLoc(), "register expected");
303 getLexer().Lex(); // Eat identifier token.
305 bool Preindexed = false;
306 bool Postindexed = false;
307 bool OffsetIsReg = false;
308 bool Negative = false;
309 bool Writeback = false;
311 // First look for preindexed address forms:
314 // [Rn, +/-Rm, shift]
315 // that is after the "[Rn" we now have see if the next token is a comma.
316 const AsmToken &Tok = getLexer().getTok();
317 if (Tok.is(AsmToken::Comma)) {
319 getLexer().Lex(); // Eat comma token.
321 const AsmToken &NextTok = getLexer().getTok();
322 if (NextTok.is(AsmToken::Plus))
323 getLexer().Lex(); // Eat plus token.
324 else if (NextTok.is(AsmToken::Minus)) {
326 getLexer().Lex(); // Eat minus token
329 // See if there is a register following the "[Rn," we have so far.
330 const AsmToken &OffsetRegTok = getLexer().getTok();
331 int OffsetRegNum = MatchRegisterName(OffsetRegTok.getString());
332 bool OffsetRegShifted = false;
333 enum ShiftType ShiftType;
334 const MCExpr *ShiftAmount;
335 const MCExpr *Offset;
336 if (OffsetRegNum != -1) {
338 getLexer().Lex(); // Eat identifier token for the offset register.
339 // Look for a comma then a shift
340 const AsmToken &Tok = getLexer().getTok();
341 if (Tok.is(AsmToken::Comma)) {
342 getLexer().Lex(); // Eat comma token.
344 const AsmToken &Tok = getLexer().getTok();
345 if (ParseShift(&ShiftType, ShiftAmount))
346 return Error(Tok.getLoc(), "shift expected");
347 OffsetRegShifted = true;
350 else { // "[Rn," we have so far was not followed by "Rm"
351 // Look for #offset following the "[Rn,"
352 const AsmToken &HashTok = getLexer().getTok();
353 if (HashTok.isNot(AsmToken::Hash))
354 return Error(HashTok.getLoc(), "'#' expected");
355 getLexer().Lex(); // Eat hash token.
357 if (getParser().ParseExpression(Offset))
360 const AsmToken &RBracTok = getLexer().getTok();
361 if (RBracTok.isNot(AsmToken::RBrac))
362 return Error(RBracTok.getLoc(), "']' expected");
363 getLexer().Lex(); // Eat right bracket token.
365 const AsmToken &ExclaimTok = getLexer().getTok();
366 if (ExclaimTok.is(AsmToken::Exclaim)) {
368 getLexer().Lex(); // Eat exclaim token
370 Op = ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
371 OffsetRegShifted, ShiftType, ShiftAmount,
372 Preindexed, Postindexed, Negative, Writeback);
375 // The "[Rn" we have so far was not followed by a comma.
376 else if (Tok.is(AsmToken::RBrac)) {
377 // This is a post indexing addressing forms:
380 // [Rn], +/-Rm, shift
381 // that is a ']' follows after the "[Rn".
384 getLexer().Lex(); // Eat right bracket token.
386 int OffsetRegNum = 0;
387 bool OffsetRegShifted = false;
388 enum ShiftType ShiftType;
389 const MCExpr *ShiftAmount;
390 const MCExpr *Offset;
392 const AsmToken &NextTok = getLexer().getTok();
393 if (NextTok.isNot(AsmToken::EndOfStatement)) {
394 if (NextTok.isNot(AsmToken::Comma))
395 return Error(NextTok.getLoc(), "',' expected");
396 getLexer().Lex(); // Eat comma token.
398 const AsmToken &PlusMinusTok = getLexer().getTok();
399 if (PlusMinusTok.is(AsmToken::Plus))
400 getLexer().Lex(); // Eat plus token.
401 else if (PlusMinusTok.is(AsmToken::Minus)) {
403 getLexer().Lex(); // Eat minus token
406 // See if there is a register following the "[Rn]," we have so far.
407 const AsmToken &OffsetRegTok = getLexer().getTok();
408 OffsetRegNum = MatchRegisterName(OffsetRegTok.getString());
409 if (OffsetRegNum != -1) {
411 getLexer().Lex(); // Eat identifier token for the offset register.
412 // Look for a comma then a shift
413 const AsmToken &Tok = getLexer().getTok();
414 if (Tok.is(AsmToken::Comma)) {
415 getLexer().Lex(); // Eat comma token.
417 const AsmToken &Tok = getLexer().getTok();
418 if (ParseShift(&ShiftType, ShiftAmount))
419 return Error(Tok.getLoc(), "shift expected");
420 OffsetRegShifted = true;
423 else { // "[Rn]," we have so far was not followed by "Rm"
424 // Look for #offset following the "[Rn],"
425 const AsmToken &HashTok = getLexer().getTok();
426 if (HashTok.isNot(AsmToken::Hash))
427 return Error(HashTok.getLoc(), "'#' expected");
428 getLexer().Lex(); // Eat hash token.
430 if (getParser().ParseExpression(Offset))
435 Op = ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
436 OffsetRegShifted, ShiftType, ShiftAmount,
437 Preindexed, Postindexed, Negative, Writeback);
444 /// ParseShift as one of these two:
445 /// ( lsl | lsr | asr | ror ) , # shift_amount
447 /// and returns true if it parses a shift otherwise it returns false.
448 bool ARMAsmParser::ParseShift(ShiftType *St, const MCExpr *&ShiftAmount) {
449 const AsmToken &Tok = getLexer().getTok();
450 if (Tok.isNot(AsmToken::Identifier))
452 const StringRef &ShiftName = Tok.getString();
453 if (ShiftName == "lsl" || ShiftName == "LSL")
455 else if (ShiftName == "lsr" || ShiftName == "LSR")
457 else if (ShiftName == "asr" || ShiftName == "ASR")
459 else if (ShiftName == "ror" || ShiftName == "ROR")
461 else if (ShiftName == "rrx" || ShiftName == "RRX")
465 getLexer().Lex(); // Eat shift type token.
467 // For all but a Rotate right there must be a '#' and a shift amount
469 // Look for # following the shift type
470 const AsmToken &HashTok = getLexer().getTok();
471 if (HashTok.isNot(AsmToken::Hash))
472 return Error(HashTok.getLoc(), "'#' expected");
473 getLexer().Lex(); // Eat hash token.
475 if (getParser().ParseExpression(ShiftAmount))
482 // A hack to allow some testing, to be replaced by a real table gen version.
483 int ARMAsmParser::MatchRegisterName(const StringRef &Name) {
484 if (Name == "r0" || Name == "R0")
486 else if (Name == "r1" || Name == "R1")
488 else if (Name == "r2" || Name == "R2")
490 else if (Name == "r3" || Name == "R3")
492 else if (Name == "r3" || Name == "R3")
494 else if (Name == "r4" || Name == "R4")
496 else if (Name == "r5" || Name == "R5")
498 else if (Name == "r6" || Name == "R6")
500 else if (Name == "r7" || Name == "R7")
502 else if (Name == "r8" || Name == "R8")
504 else if (Name == "r9" || Name == "R9")
506 else if (Name == "r10" || Name == "R10")
508 else if (Name == "r11" || Name == "R11" || Name == "fp")
510 else if (Name == "r12" || Name == "R12" || Name == "ip")
512 else if (Name == "r13" || Name == "R13" || Name == "sp")
514 else if (Name == "r14" || Name == "R14" || Name == "lr")
516 else if (Name == "r15" || Name == "R15" || Name == "pc")
521 // A hack to allow some testing, to be replaced by a real table gen version.
522 bool ARMAsmParser::MatchInstruction(SmallVectorImpl<ARMOperand> &Operands,
524 struct ARMOperand Op0 = Operands[0];
525 assert(Op0.Kind == ARMOperand::Token && "First operand not a Token");
526 const StringRef &Mnemonic = Op0.getToken();
527 if (Mnemonic == "add" ||
528 Mnemonic == "stmfd" ||
530 Mnemonic == "ldmfd" ||
535 Mnemonic == "push" ||
543 // Parse a arm instruction operand. For now this parses the operand regardless
545 bool ARMAsmParser::ParseOperand(ARMOperand &Op) {
546 switch (getLexer().getKind()) {
547 case AsmToken::Identifier:
548 if (!ParseRegister(Op))
550 // This was not a register so parse other operands that start with an
551 // identifier (like labels) as expressions and create them as immediates.
553 if (getParser().ParseExpression(IdVal))
555 Op = ARMOperand::CreateImm(IdVal);
557 case AsmToken::LBrac:
558 return ParseMemory(Op);
559 case AsmToken::LCurly:
560 return ParseRegisterList(Op);
563 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
565 const MCExpr *ImmVal;
566 if (getParser().ParseExpression(ImmVal))
568 Op = ARMOperand::CreateImm(ImmVal);
571 return Error(getLexer().getTok().getLoc(), "unexpected token in operand");
575 // Parse an arm instruction mnemonic followed by its operands.
576 bool ARMAsmParser::ParseInstruction(const StringRef &Name, MCInst &Inst) {
577 SmallVector<ARMOperand, 7> Operands;
579 Operands.push_back(ARMOperand::CreateToken(Name));
581 SMLoc Loc = getLexer().getTok().getLoc();
582 if (getLexer().isNot(AsmToken::EndOfStatement)) {
584 // Read the first operand.
585 Operands.push_back(ARMOperand());
586 if (ParseOperand(Operands.back()))
589 while (getLexer().is(AsmToken::Comma)) {
590 getLexer().Lex(); // Eat the comma.
592 // Parse and remember the operand.
593 Operands.push_back(ARMOperand());
594 if (ParseOperand(Operands.back()))
598 if (!MatchInstruction(Operands, Inst))
601 Error(Loc, "ARMAsmParser::ParseInstruction only partly implemented");
605 /// ParseDirective parses the arm specific directives
606 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
607 StringRef IDVal = DirectiveID.getIdentifier();
608 if (IDVal == ".word")
609 return ParseDirectiveWord(4, DirectiveID.getLoc());
610 else if (IDVal == ".thumb")
611 return ParseDirectiveThumb(DirectiveID.getLoc());
612 else if (IDVal == ".thumb_func")
613 return ParseDirectiveThumbFunc(DirectiveID.getLoc());
614 else if (IDVal == ".code")
615 return ParseDirectiveCode(DirectiveID.getLoc());
616 else if (IDVal == ".syntax")
617 return ParseDirectiveSyntax(DirectiveID.getLoc());
621 /// ParseDirectiveWord
622 /// ::= .word [ expression (, expression)* ]
623 bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
624 if (getLexer().isNot(AsmToken::EndOfStatement)) {
627 if (getParser().ParseExpression(Value))
630 getParser().getStreamer().EmitValue(Value, Size);
632 if (getLexer().is(AsmToken::EndOfStatement))
635 // FIXME: Improve diagnostic.
636 if (getLexer().isNot(AsmToken::Comma))
637 return Error(L, "unexpected token in directive");
646 /// ParseDirectiveThumb
648 bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
649 if (getLexer().isNot(AsmToken::EndOfStatement))
650 return Error(L, "unexpected token in directive");
653 // TODO: set thumb mode
654 // TODO: tell the MC streamer the mode
655 // getParser().getStreamer().Emit???();
659 /// ParseDirectiveThumbFunc
660 /// ::= .thumbfunc symbol_name
661 bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
662 const AsmToken &Tok = getLexer().getTok();
663 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
664 return Error(L, "unexpected token in .syntax directive");
665 StringRef SymbolName = getLexer().getTok().getIdentifier();
666 getLexer().Lex(); // Consume the identifier token.
668 if (getLexer().isNot(AsmToken::EndOfStatement))
669 return Error(L, "unexpected token in directive");
672 // TODO: mark symbol as a thumb symbol
673 // getParser().getStreamer().Emit???();
677 /// ParseDirectiveSyntax
678 /// ::= .syntax unified | divided
679 bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
680 const AsmToken &Tok = getLexer().getTok();
681 if (Tok.isNot(AsmToken::Identifier))
682 return Error(L, "unexpected token in .syntax directive");
683 const StringRef &Mode = Tok.getString();
685 if (Mode == "unified" || Mode == "UNIFIED") {
687 unified_syntax = true;
689 else if (Mode == "divided" || Mode == "DIVIDED") {
691 unified_syntax = false;
694 return Error(L, "unrecognized syntax mode in .syntax directive");
696 if (getLexer().isNot(AsmToken::EndOfStatement))
697 return Error(getLexer().getTok().getLoc(), "unexpected token in directive");
700 // TODO tell the MC streamer the mode
701 // getParser().getStreamer().Emit???();
705 /// ParseDirectiveCode
706 /// ::= .code 16 | 32
707 bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
708 const AsmToken &Tok = getLexer().getTok();
709 if (Tok.isNot(AsmToken::Integer))
710 return Error(L, "unexpected token in .code directive");
711 int64_t Val = getLexer().getTok().getIntVal();
717 else if (Val == 32) {
722 return Error(L, "invalid operand to .code directive");
724 if (getLexer().isNot(AsmToken::EndOfStatement))
725 return Error(getLexer().getTok().getLoc(), "unexpected token in directive");
728 // TODO tell the MC streamer the mode
729 // getParser().getStreamer().Emit???();
733 // Force static initialization.
734 extern "C" void LLVMInitializeARMAsmParser() {
735 RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
736 RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);