1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMBaseInfo.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMMCExpr.h"
13 #include "llvm/MC/MCParser/MCAsmLexer.h"
14 #include "llvm/MC/MCParser/MCAsmParser.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCAsmInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCTargetAsmParser.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/SourceMgr.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/ADT/BitVector.h"
30 #include "llvm/ADT/OwningPtr.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/StringExtras.h"
34 #include "llvm/ADT/StringSwitch.h"
35 #include "llvm/ADT/Twine.h"
43 class ARMAsmParser : public MCTargetAsmParser {
48 ARMCC::CondCodes Cond; // Condition for IT block.
49 unsigned Mask:4; // Condition mask for instructions.
50 // Starting at first 1 (from lsb).
51 // '1' condition as indicated in IT.
52 // '0' inverse of condition (else).
53 // Count of instructions in IT block is
54 // 4 - trailingzeroes(mask)
56 bool FirstCond; // Explicit flag for when we're parsing the
57 // First instruction in the IT block. It's
58 // implied in the mask, so needs special
61 unsigned CurPosition; // Current position in parsing of IT
62 // block. In range [0,3]. Initialized
63 // according to count of instructions in block.
64 // ~0U if no active IT block.
66 bool inITBlock() { return ITState.CurPosition != ~0U;}
67 void forwardITPosition() {
68 if (!inITBlock()) return;
69 // Move to the next instruction in the IT block, if there is one. If not,
70 // mark the block as done.
71 unsigned TZ = CountTrailingZeros_32(ITState.Mask);
72 if (++ITState.CurPosition == 5 - TZ)
73 ITState.CurPosition = ~0U; // Done with the IT block after this.
77 MCAsmParser &getParser() const { return Parser; }
78 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
80 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
81 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
83 int tryParseRegister();
84 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
85 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
86 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
87 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
88 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
89 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
90 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
91 unsigned &ShiftAmount);
92 bool parseDirectiveWord(unsigned Size, SMLoc L);
93 bool parseDirectiveThumb(SMLoc L);
94 bool parseDirectiveThumbFunc(SMLoc L);
95 bool parseDirectiveCode(SMLoc L);
96 bool parseDirectiveSyntax(SMLoc L);
98 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
99 bool &CarrySetting, unsigned &ProcessorIMod,
101 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
102 bool &CanAcceptPredicationCode);
104 bool isThumb() const {
105 // FIXME: Can tablegen auto-generate this?
106 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
108 bool isThumbOne() const {
109 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
111 bool isThumbTwo() const {
112 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
114 bool hasV6Ops() const {
115 return STI.getFeatureBits() & ARM::HasV6Ops;
117 bool hasV7Ops() const {
118 return STI.getFeatureBits() & ARM::HasV7Ops;
121 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
122 setAvailableFeatures(FB);
124 bool isMClass() const {
125 return STI.getFeatureBits() & ARM::FeatureMClass;
128 /// @name Auto-generated Match Functions
131 #define GET_ASSEMBLER_HEADER
132 #include "ARMGenAsmMatcher.inc"
136 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
137 OperandMatchResultTy parseCoprocNumOperand(
138 SmallVectorImpl<MCParsedAsmOperand*>&);
139 OperandMatchResultTy parseCoprocRegOperand(
140 SmallVectorImpl<MCParsedAsmOperand*>&);
141 OperandMatchResultTy parseCoprocOptionOperand(
142 SmallVectorImpl<MCParsedAsmOperand*>&);
143 OperandMatchResultTy parseMemBarrierOptOperand(
144 SmallVectorImpl<MCParsedAsmOperand*>&);
145 OperandMatchResultTy parseProcIFlagsOperand(
146 SmallVectorImpl<MCParsedAsmOperand*>&);
147 OperandMatchResultTy parseMSRMaskOperand(
148 SmallVectorImpl<MCParsedAsmOperand*>&);
149 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
150 StringRef Op, int Low, int High);
151 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
152 return parsePKHImm(O, "lsl", 0, 31);
154 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
155 return parsePKHImm(O, "asr", 1, 32);
157 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
158 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
159 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
160 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
161 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
162 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
163 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
165 // Asm Match Converter Methods
166 bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
167 const SmallVectorImpl<MCParsedAsmOperand*> &);
168 bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
169 const SmallVectorImpl<MCParsedAsmOperand*> &);
170 bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
171 const SmallVectorImpl<MCParsedAsmOperand*> &);
172 bool cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
173 const SmallVectorImpl<MCParsedAsmOperand*> &);
174 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
175 const SmallVectorImpl<MCParsedAsmOperand*> &);
176 bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
177 const SmallVectorImpl<MCParsedAsmOperand*> &);
178 bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
179 const SmallVectorImpl<MCParsedAsmOperand*> &);
180 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
181 const SmallVectorImpl<MCParsedAsmOperand*> &);
182 bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
183 const SmallVectorImpl<MCParsedAsmOperand*> &);
184 bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
185 const SmallVectorImpl<MCParsedAsmOperand*> &);
186 bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
187 const SmallVectorImpl<MCParsedAsmOperand*> &);
188 bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
189 const SmallVectorImpl<MCParsedAsmOperand*> &);
190 bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
191 const SmallVectorImpl<MCParsedAsmOperand*> &);
192 bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
193 const SmallVectorImpl<MCParsedAsmOperand*> &);
194 bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
195 const SmallVectorImpl<MCParsedAsmOperand*> &);
196 bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
197 const SmallVectorImpl<MCParsedAsmOperand*> &);
198 bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
199 const SmallVectorImpl<MCParsedAsmOperand*> &);
201 bool validateInstruction(MCInst &Inst,
202 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
203 void processInstruction(MCInst &Inst,
204 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
205 bool shouldOmitCCOutOperand(StringRef Mnemonic,
206 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
209 enum ARMMatchResultTy {
210 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
211 Match_RequiresNotITBlock,
216 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
217 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
218 MCAsmParserExtension::Initialize(_Parser);
220 // Initialize the set of available features.
221 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
223 // Not in an ITBlock to start with.
224 ITState.CurPosition = ~0U;
227 // Implementation of the MCTargetAsmParser interface:
228 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
229 bool ParseInstruction(StringRef Name, SMLoc NameLoc,
230 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
231 bool ParseDirective(AsmToken DirectiveID);
233 unsigned checkTargetMatchPredicate(MCInst &Inst);
235 bool MatchAndEmitInstruction(SMLoc IDLoc,
236 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
239 } // end anonymous namespace
243 /// ARMOperand - Instances of this class represent a parsed ARM machine
245 class ARMOperand : public MCParsedAsmOperand {
269 k_BitfieldDescriptor,
273 SMLoc StartLoc, EndLoc;
274 SmallVector<unsigned, 8> Registers;
278 ARMCC::CondCodes Val;
298 ARM_PROC::IFlags Val;
323 unsigned Val; // encoded 8-bit representation
326 /// Combined record for all forms of ARM address expressions.
329 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
331 const MCConstantExpr *OffsetImm; // Offset immediate value
332 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
333 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
334 unsigned ShiftImm; // shift for OffsetReg.
335 unsigned Alignment; // 0 = no alignment specified
336 // n = alignment in bytes (8, 16, or 32)
337 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
343 ARM_AM::ShiftOpc ShiftTy;
352 ARM_AM::ShiftOpc ShiftTy;
358 ARM_AM::ShiftOpc ShiftTy;
371 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
373 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
375 StartLoc = o.StartLoc;
392 case k_DPRRegisterList:
393 case k_SPRRegisterList:
394 Registers = o.Registers;
401 CoprocOption = o.CoprocOption;
409 case k_MemBarrierOpt:
415 case k_PostIndexRegister:
416 PostIdxReg = o.PostIdxReg;
424 case k_ShifterImmediate:
425 ShifterImm = o.ShifterImm;
427 case k_ShiftedRegister:
428 RegShiftedReg = o.RegShiftedReg;
430 case k_ShiftedImmediate:
431 RegShiftedImm = o.RegShiftedImm;
433 case k_RotateImmediate:
436 case k_BitfieldDescriptor:
437 Bitfield = o.Bitfield;
440 VectorIndex = o.VectorIndex;
445 /// getStartLoc - Get the location of the first token of this operand.
446 SMLoc getStartLoc() const { return StartLoc; }
447 /// getEndLoc - Get the location of the last token of this operand.
448 SMLoc getEndLoc() const { return EndLoc; }
450 ARMCC::CondCodes getCondCode() const {
451 assert(Kind == k_CondCode && "Invalid access!");
455 unsigned getCoproc() const {
456 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
460 StringRef getToken() const {
461 assert(Kind == k_Token && "Invalid access!");
462 return StringRef(Tok.Data, Tok.Length);
465 unsigned getReg() const {
466 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
470 const SmallVectorImpl<unsigned> &getRegList() const {
471 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
472 Kind == k_SPRRegisterList) && "Invalid access!");
476 const MCExpr *getImm() const {
477 assert(Kind == k_Immediate && "Invalid access!");
481 unsigned getFPImm() const {
482 assert(Kind == k_FPImmediate && "Invalid access!");
486 unsigned getVectorIndex() const {
487 assert(Kind == k_VectorIndex && "Invalid access!");
488 return VectorIndex.Val;
491 ARM_MB::MemBOpt getMemBarrierOpt() const {
492 assert(Kind == k_MemBarrierOpt && "Invalid access!");
496 ARM_PROC::IFlags getProcIFlags() const {
497 assert(Kind == k_ProcIFlags && "Invalid access!");
501 unsigned getMSRMask() const {
502 assert(Kind == k_MSRMask && "Invalid access!");
506 bool isCoprocNum() const { return Kind == k_CoprocNum; }
507 bool isCoprocReg() const { return Kind == k_CoprocReg; }
508 bool isCoprocOption() const { return Kind == k_CoprocOption; }
509 bool isCondCode() const { return Kind == k_CondCode; }
510 bool isCCOut() const { return Kind == k_CCOut; }
511 bool isITMask() const { return Kind == k_ITCondMask; }
512 bool isITCondCode() const { return Kind == k_CondCode; }
513 bool isImm() const { return Kind == k_Immediate; }
514 bool isFPImm() const { return Kind == k_FPImmediate; }
515 bool isImm8s4() const {
516 if (Kind != k_Immediate)
518 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
519 if (!CE) return false;
520 int64_t Value = CE->getValue();
521 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
523 bool isImm0_1020s4() const {
524 if (Kind != k_Immediate)
526 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
527 if (!CE) return false;
528 int64_t Value = CE->getValue();
529 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
531 bool isImm0_508s4() const {
532 if (Kind != k_Immediate)
534 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
535 if (!CE) return false;
536 int64_t Value = CE->getValue();
537 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
539 bool isImm0_255() const {
540 if (Kind != k_Immediate)
542 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
543 if (!CE) return false;
544 int64_t Value = CE->getValue();
545 return Value >= 0 && Value < 256;
547 bool isImm0_7() const {
548 if (Kind != k_Immediate)
550 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
551 if (!CE) return false;
552 int64_t Value = CE->getValue();
553 return Value >= 0 && Value < 8;
555 bool isImm0_15() const {
556 if (Kind != k_Immediate)
558 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
559 if (!CE) return false;
560 int64_t Value = CE->getValue();
561 return Value >= 0 && Value < 16;
563 bool isImm0_31() const {
564 if (Kind != k_Immediate)
566 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
567 if (!CE) return false;
568 int64_t Value = CE->getValue();
569 return Value >= 0 && Value < 32;
571 bool isImm1_16() const {
572 if (Kind != k_Immediate)
574 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
575 if (!CE) return false;
576 int64_t Value = CE->getValue();
577 return Value > 0 && Value < 17;
579 bool isImm1_32() const {
580 if (Kind != k_Immediate)
582 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
583 if (!CE) return false;
584 int64_t Value = CE->getValue();
585 return Value > 0 && Value < 33;
587 bool isImm0_65535() const {
588 if (Kind != k_Immediate)
590 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
591 if (!CE) return false;
592 int64_t Value = CE->getValue();
593 return Value >= 0 && Value < 65536;
595 bool isImm0_65535Expr() const {
596 if (Kind != k_Immediate)
598 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
599 // If it's not a constant expression, it'll generate a fixup and be
601 if (!CE) return true;
602 int64_t Value = CE->getValue();
603 return Value >= 0 && Value < 65536;
605 bool isImm24bit() const {
606 if (Kind != k_Immediate)
608 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
609 if (!CE) return false;
610 int64_t Value = CE->getValue();
611 return Value >= 0 && Value <= 0xffffff;
613 bool isImmThumbSR() const {
614 if (Kind != k_Immediate)
616 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
617 if (!CE) return false;
618 int64_t Value = CE->getValue();
619 return Value > 0 && Value < 33;
621 bool isPKHLSLImm() const {
622 if (Kind != k_Immediate)
624 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
625 if (!CE) return false;
626 int64_t Value = CE->getValue();
627 return Value >= 0 && Value < 32;
629 bool isPKHASRImm() const {
630 if (Kind != k_Immediate)
632 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
633 if (!CE) return false;
634 int64_t Value = CE->getValue();
635 return Value > 0 && Value <= 32;
637 bool isARMSOImm() const {
638 if (Kind != k_Immediate)
640 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
641 if (!CE) return false;
642 int64_t Value = CE->getValue();
643 return ARM_AM::getSOImmVal(Value) != -1;
645 bool isT2SOImm() const {
646 if (Kind != k_Immediate)
648 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
649 if (!CE) return false;
650 int64_t Value = CE->getValue();
651 return ARM_AM::getT2SOImmVal(Value) != -1;
653 bool isSetEndImm() const {
654 if (Kind != k_Immediate)
656 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
657 if (!CE) return false;
658 int64_t Value = CE->getValue();
659 return Value == 1 || Value == 0;
661 bool isReg() const { return Kind == k_Register; }
662 bool isRegList() const { return Kind == k_RegisterList; }
663 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
664 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
665 bool isToken() const { return Kind == k_Token; }
666 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
667 bool isMemory() const { return Kind == k_Memory; }
668 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
669 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
670 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
671 bool isRotImm() const { return Kind == k_RotateImmediate; }
672 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
673 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
674 bool isPostIdxReg() const {
675 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
677 bool isMemNoOffset(bool alignOK = false) const {
680 // No offset of any kind.
681 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
682 (alignOK || Memory.Alignment == 0);
684 bool isAlignedMemory() const {
685 return isMemNoOffset(true);
687 bool isAddrMode2() const {
688 if (!isMemory() || Memory.Alignment != 0) return false;
689 // Check for register offset.
690 if (Memory.OffsetRegNum) return true;
691 // Immediate offset in range [-4095, 4095].
692 if (!Memory.OffsetImm) return true;
693 int64_t Val = Memory.OffsetImm->getValue();
694 return Val > -4096 && Val < 4096;
696 bool isAM2OffsetImm() const {
697 if (Kind != k_Immediate)
699 // Immediate offset in range [-4095, 4095].
700 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
701 if (!CE) return false;
702 int64_t Val = CE->getValue();
703 return Val > -4096 && Val < 4096;
705 bool isAddrMode3() const {
706 if (!isMemory() || Memory.Alignment != 0) return false;
707 // No shifts are legal for AM3.
708 if (Memory.ShiftType != ARM_AM::no_shift) return false;
709 // Check for register offset.
710 if (Memory.OffsetRegNum) return true;
711 // Immediate offset in range [-255, 255].
712 if (!Memory.OffsetImm) return true;
713 int64_t Val = Memory.OffsetImm->getValue();
714 return Val > -256 && Val < 256;
716 bool isAM3Offset() const {
717 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
719 if (Kind == k_PostIndexRegister)
720 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
721 // Immediate offset in range [-255, 255].
722 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
723 if (!CE) return false;
724 int64_t Val = CE->getValue();
725 // Special case, #-0 is INT32_MIN.
726 return (Val > -256 && Val < 256) || Val == INT32_MIN;
728 bool isAddrMode5() const {
729 if (!isMemory() || Memory.Alignment != 0) return false;
730 // Check for register offset.
731 if (Memory.OffsetRegNum) return false;
732 // Immediate offset in range [-1020, 1020] and a multiple of 4.
733 if (!Memory.OffsetImm) return true;
734 int64_t Val = Memory.OffsetImm->getValue();
735 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
738 bool isMemTBB() const {
739 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
740 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
744 bool isMemTBH() const {
745 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
746 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
747 Memory.Alignment != 0 )
751 bool isMemRegOffset() const {
752 if (!isMemory() || !Memory.OffsetRegNum || Memory.Alignment != 0)
756 bool isT2MemRegOffset() const {
757 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
758 Memory.Alignment != 0)
760 // Only lsl #{0, 1, 2, 3} allowed.
761 if (Memory.ShiftType == ARM_AM::no_shift)
763 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
767 bool isMemThumbRR() const {
768 // Thumb reg+reg addressing is simple. Just two registers, a base and
769 // an offset. No shifts, negations or any other complicating factors.
770 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
771 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
773 return isARMLowRegister(Memory.BaseRegNum) &&
774 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
776 bool isMemThumbRIs4() const {
777 if (!isMemory() || Memory.OffsetRegNum != 0 ||
778 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
780 // Immediate offset, multiple of 4 in range [0, 124].
781 if (!Memory.OffsetImm) return true;
782 int64_t Val = Memory.OffsetImm->getValue();
783 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
785 bool isMemThumbRIs2() const {
786 if (!isMemory() || Memory.OffsetRegNum != 0 ||
787 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
789 // Immediate offset, multiple of 4 in range [0, 62].
790 if (!Memory.OffsetImm) return true;
791 int64_t Val = Memory.OffsetImm->getValue();
792 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
794 bool isMemThumbRIs1() const {
795 if (!isMemory() || Memory.OffsetRegNum != 0 ||
796 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
798 // Immediate offset in range [0, 31].
799 if (!Memory.OffsetImm) return true;
800 int64_t Val = Memory.OffsetImm->getValue();
801 return Val >= 0 && Val <= 31;
803 bool isMemThumbSPI() const {
804 if (!isMemory() || Memory.OffsetRegNum != 0 ||
805 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
807 // Immediate offset, multiple of 4 in range [0, 1020].
808 if (!Memory.OffsetImm) return true;
809 int64_t Val = Memory.OffsetImm->getValue();
810 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
812 bool isMemImm8s4Offset() const {
813 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
815 // Immediate offset a multiple of 4 in range [-1020, 1020].
816 if (!Memory.OffsetImm) return true;
817 int64_t Val = Memory.OffsetImm->getValue();
818 return Val >= -1020 && Val <= 1020 && (Val & 3) == 0;
820 bool isMemImm0_1020s4Offset() const {
821 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
823 // Immediate offset a multiple of 4 in range [0, 1020].
824 if (!Memory.OffsetImm) return true;
825 int64_t Val = Memory.OffsetImm->getValue();
826 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
828 bool isMemImm8Offset() const {
829 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
831 // Immediate offset in range [-255, 255].
832 if (!Memory.OffsetImm) return true;
833 int64_t Val = Memory.OffsetImm->getValue();
834 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
836 bool isMemPosImm8Offset() const {
837 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
839 // Immediate offset in range [0, 255].
840 if (!Memory.OffsetImm) return true;
841 int64_t Val = Memory.OffsetImm->getValue();
842 return Val >= 0 && Val < 256;
844 bool isMemNegImm8Offset() const {
845 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
847 // Immediate offset in range [-255, -1].
848 if (!Memory.OffsetImm) return true;
849 int64_t Val = Memory.OffsetImm->getValue();
850 return Val > -256 && Val < 0;
852 bool isMemUImm12Offset() const {
853 // If we have an immediate that's not a constant, treat it as a label
854 // reference needing a fixup. If it is a constant, it's something else
856 if (Kind == k_Immediate && !isa<MCConstantExpr>(getImm()))
859 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
861 // Immediate offset in range [0, 4095].
862 if (!Memory.OffsetImm) return true;
863 int64_t Val = Memory.OffsetImm->getValue();
864 return (Val >= 0 && Val < 4096);
866 bool isMemImm12Offset() const {
867 // If we have an immediate that's not a constant, treat it as a label
868 // reference needing a fixup. If it is a constant, it's something else
870 if (Kind == k_Immediate && !isa<MCConstantExpr>(getImm()))
873 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
875 // Immediate offset in range [-4095, 4095].
876 if (!Memory.OffsetImm) return true;
877 int64_t Val = Memory.OffsetImm->getValue();
878 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
880 bool isPostIdxImm8() const {
881 if (Kind != k_Immediate)
883 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
884 if (!CE) return false;
885 int64_t Val = CE->getValue();
886 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
888 bool isPostIdxImm8s4() const {
889 if (Kind != k_Immediate)
891 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
892 if (!CE) return false;
893 int64_t Val = CE->getValue();
894 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
898 bool isMSRMask() const { return Kind == k_MSRMask; }
899 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
902 bool isVectorIndex8() const {
903 if (Kind != k_VectorIndex) return false;
904 return VectorIndex.Val < 8;
906 bool isVectorIndex16() const {
907 if (Kind != k_VectorIndex) return false;
908 return VectorIndex.Val < 4;
910 bool isVectorIndex32() const {
911 if (Kind != k_VectorIndex) return false;
912 return VectorIndex.Val < 2;
915 bool isNEONi8splat() const {
916 if (Kind != k_Immediate)
918 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
919 // Must be a constant.
920 if (!CE) return false;
921 int64_t Value = CE->getValue();
922 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
924 return Value >= 0 && Value < 256;
927 bool isNEONi16splat() const {
928 if (Kind != k_Immediate)
930 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
931 // Must be a constant.
932 if (!CE) return false;
933 int64_t Value = CE->getValue();
934 // i16 value in the range [0,255] or [0x0100, 0xff00]
935 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
938 bool isNEONi32splat() const {
939 if (Kind != k_Immediate)
941 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
942 // Must be a constant.
943 if (!CE) return false;
944 int64_t Value = CE->getValue();
945 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
946 return (Value >= 0 && Value < 256) ||
947 (Value >= 0x0100 && Value <= 0xff00) ||
948 (Value >= 0x010000 && Value <= 0xff0000) ||
949 (Value >= 0x01000000 && Value <= 0xff000000);
952 bool isNEONi32vmov() const {
953 if (Kind != k_Immediate)
955 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
956 // Must be a constant.
957 if (!CE) return false;
958 int64_t Value = CE->getValue();
959 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
960 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
961 return (Value >= 0 && Value < 256) ||
962 (Value >= 0x0100 && Value <= 0xff00) ||
963 (Value >= 0x010000 && Value <= 0xff0000) ||
964 (Value >= 0x01000000 && Value <= 0xff000000) ||
965 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
966 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
969 bool isNEONi64splat() const {
970 if (Kind != k_Immediate)
972 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
973 // Must be a constant.
974 if (!CE) return false;
975 uint64_t Value = CE->getValue();
976 // i64 value with each byte being either 0 or 0xff.
977 for (unsigned i = 0; i < 8; ++i)
978 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
982 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
983 // Add as immediates when possible. Null MCExpr = 0.
985 Inst.addOperand(MCOperand::CreateImm(0));
986 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
987 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
989 Inst.addOperand(MCOperand::CreateExpr(Expr));
992 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
993 assert(N == 2 && "Invalid number of operands!");
994 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
995 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
996 Inst.addOperand(MCOperand::CreateReg(RegNum));
999 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1000 assert(N == 1 && "Invalid number of operands!");
1001 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1004 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1005 assert(N == 1 && "Invalid number of operands!");
1006 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1009 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1010 assert(N == 1 && "Invalid number of operands!");
1011 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1014 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1015 assert(N == 1 && "Invalid number of operands!");
1016 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1019 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1020 assert(N == 1 && "Invalid number of operands!");
1021 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1024 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1025 assert(N == 1 && "Invalid number of operands!");
1026 Inst.addOperand(MCOperand::CreateReg(getReg()));
1029 void addRegOperands(MCInst &Inst, unsigned N) const {
1030 assert(N == 1 && "Invalid number of operands!");
1031 Inst.addOperand(MCOperand::CreateReg(getReg()));
1034 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1035 assert(N == 3 && "Invalid number of operands!");
1036 assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
1037 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1038 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1039 Inst.addOperand(MCOperand::CreateImm(
1040 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1043 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1044 assert(N == 2 && "Invalid number of operands!");
1045 assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
1046 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1047 Inst.addOperand(MCOperand::CreateImm(
1048 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
1051 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1052 assert(N == 1 && "Invalid number of operands!");
1053 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1057 void addRegListOperands(MCInst &Inst, unsigned N) const {
1058 assert(N == 1 && "Invalid number of operands!");
1059 const SmallVectorImpl<unsigned> &RegList = getRegList();
1060 for (SmallVectorImpl<unsigned>::const_iterator
1061 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1062 Inst.addOperand(MCOperand::CreateReg(*I));
1065 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1066 addRegListOperands(Inst, N);
1069 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1070 addRegListOperands(Inst, N);
1073 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1074 assert(N == 1 && "Invalid number of operands!");
1075 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1076 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1079 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1080 assert(N == 1 && "Invalid number of operands!");
1081 // Munge the lsb/width into a bitfield mask.
1082 unsigned lsb = Bitfield.LSB;
1083 unsigned width = Bitfield.Width;
1084 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1085 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1086 (32 - (lsb + width)));
1087 Inst.addOperand(MCOperand::CreateImm(Mask));
1090 void addImmOperands(MCInst &Inst, unsigned N) const {
1091 assert(N == 1 && "Invalid number of operands!");
1092 addExpr(Inst, getImm());
1095 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1096 assert(N == 1 && "Invalid number of operands!");
1097 Inst.addOperand(MCOperand::CreateImm(getFPImm()));
1100 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1101 assert(N == 1 && "Invalid number of operands!");
1102 // FIXME: We really want to scale the value here, but the LDRD/STRD
1103 // instruction don't encode operands that way yet.
1104 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1105 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1108 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1109 assert(N == 1 && "Invalid number of operands!");
1110 // The immediate is scaled by four in the encoding and is stored
1111 // in the MCInst as such. Lop off the low two bits here.
1112 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1113 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1116 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1117 assert(N == 1 && "Invalid number of operands!");
1118 // The immediate is scaled by four in the encoding and is stored
1119 // in the MCInst as such. Lop off the low two bits here.
1120 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1121 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1124 void addImm0_255Operands(MCInst &Inst, unsigned N) const {
1125 assert(N == 1 && "Invalid number of operands!");
1126 addExpr(Inst, getImm());
1129 void addImm0_7Operands(MCInst &Inst, unsigned N) const {
1130 assert(N == 1 && "Invalid number of operands!");
1131 addExpr(Inst, getImm());
1134 void addImm0_15Operands(MCInst &Inst, unsigned N) const {
1135 assert(N == 1 && "Invalid number of operands!");
1136 addExpr(Inst, getImm());
1139 void addImm0_31Operands(MCInst &Inst, unsigned N) const {
1140 assert(N == 1 && "Invalid number of operands!");
1141 addExpr(Inst, getImm());
1144 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1145 assert(N == 1 && "Invalid number of operands!");
1146 // The constant encodes as the immediate-1, and we store in the instruction
1147 // the bits as encoded, so subtract off one here.
1148 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1149 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1152 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1153 assert(N == 1 && "Invalid number of operands!");
1154 // The constant encodes as the immediate-1, and we store in the instruction
1155 // the bits as encoded, so subtract off one here.
1156 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1157 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1160 void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
1161 assert(N == 1 && "Invalid number of operands!");
1162 addExpr(Inst, getImm());
1165 void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
1166 assert(N == 1 && "Invalid number of operands!");
1167 addExpr(Inst, getImm());
1170 void addImm24bitOperands(MCInst &Inst, unsigned N) const {
1171 assert(N == 1 && "Invalid number of operands!");
1172 addExpr(Inst, getImm());
1175 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1176 assert(N == 1 && "Invalid number of operands!");
1177 // The constant encodes as the immediate, except for 32, which encodes as
1179 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1180 unsigned Imm = CE->getValue();
1181 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1184 void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
1185 assert(N == 1 && "Invalid number of operands!");
1186 addExpr(Inst, getImm());
1189 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1190 assert(N == 1 && "Invalid number of operands!");
1191 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1192 // the instruction as well.
1193 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1194 int Val = CE->getValue();
1195 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1198 void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
1199 assert(N == 1 && "Invalid number of operands!");
1200 addExpr(Inst, getImm());
1203 void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
1204 assert(N == 1 && "Invalid number of operands!");
1205 addExpr(Inst, getImm());
1208 void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
1209 assert(N == 1 && "Invalid number of operands!");
1210 addExpr(Inst, getImm());
1213 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1214 assert(N == 1 && "Invalid number of operands!");
1215 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1218 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1219 assert(N == 1 && "Invalid number of operands!");
1220 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1223 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1224 assert(N == 2 && "Invalid number of operands!");
1225 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1226 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1229 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1230 assert(N == 3 && "Invalid number of operands!");
1231 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1232 if (!Memory.OffsetRegNum) {
1233 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1234 // Special case for #-0
1235 if (Val == INT32_MIN) Val = 0;
1236 if (Val < 0) Val = -Val;
1237 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1239 // For register offset, we encode the shift type and negation flag
1241 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1242 Memory.ShiftImm, Memory.ShiftType);
1244 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1245 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1246 Inst.addOperand(MCOperand::CreateImm(Val));
1249 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1250 assert(N == 2 && "Invalid number of operands!");
1251 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1252 assert(CE && "non-constant AM2OffsetImm operand!");
1253 int32_t Val = CE->getValue();
1254 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1255 // Special case for #-0
1256 if (Val == INT32_MIN) Val = 0;
1257 if (Val < 0) Val = -Val;
1258 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1259 Inst.addOperand(MCOperand::CreateReg(0));
1260 Inst.addOperand(MCOperand::CreateImm(Val));
1263 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1264 assert(N == 3 && "Invalid number of operands!");
1265 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1266 if (!Memory.OffsetRegNum) {
1267 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1268 // Special case for #-0
1269 if (Val == INT32_MIN) Val = 0;
1270 if (Val < 0) Val = -Val;
1271 Val = ARM_AM::getAM3Opc(AddSub, Val);
1273 // For register offset, we encode the shift type and negation flag
1275 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1277 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1278 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1279 Inst.addOperand(MCOperand::CreateImm(Val));
1282 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1283 assert(N == 2 && "Invalid number of operands!");
1284 if (Kind == k_PostIndexRegister) {
1286 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1287 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1288 Inst.addOperand(MCOperand::CreateImm(Val));
1293 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1294 int32_t Val = CE->getValue();
1295 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1296 // Special case for #-0
1297 if (Val == INT32_MIN) Val = 0;
1298 if (Val < 0) Val = -Val;
1299 Val = ARM_AM::getAM3Opc(AddSub, Val);
1300 Inst.addOperand(MCOperand::CreateReg(0));
1301 Inst.addOperand(MCOperand::CreateImm(Val));
1304 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1305 assert(N == 2 && "Invalid number of operands!");
1306 // The lower two bits are always zero and as such are not encoded.
1307 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1308 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1309 // Special case for #-0
1310 if (Val == INT32_MIN) Val = 0;
1311 if (Val < 0) Val = -Val;
1312 Val = ARM_AM::getAM5Opc(AddSub, Val);
1313 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1314 Inst.addOperand(MCOperand::CreateImm(Val));
1317 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1318 assert(N == 2 && "Invalid number of operands!");
1319 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1320 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1321 Inst.addOperand(MCOperand::CreateImm(Val));
1324 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1325 assert(N == 2 && "Invalid number of operands!");
1326 // The lower two bits are always zero and as such are not encoded.
1327 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1328 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1329 Inst.addOperand(MCOperand::CreateImm(Val));
1332 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1333 assert(N == 2 && "Invalid number of operands!");
1334 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1335 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1336 Inst.addOperand(MCOperand::CreateImm(Val));
1339 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1340 addMemImm8OffsetOperands(Inst, N);
1343 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1344 addMemImm8OffsetOperands(Inst, N);
1347 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1348 assert(N == 2 && "Invalid number of operands!");
1349 // If this is an immediate, it's a label reference.
1350 if (Kind == k_Immediate) {
1351 addExpr(Inst, getImm());
1352 Inst.addOperand(MCOperand::CreateImm(0));
1356 // Otherwise, it's a normal memory reg+offset.
1357 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1358 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1359 Inst.addOperand(MCOperand::CreateImm(Val));
1362 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1363 assert(N == 2 && "Invalid number of operands!");
1364 // If this is an immediate, it's a label reference.
1365 if (Kind == k_Immediate) {
1366 addExpr(Inst, getImm());
1367 Inst.addOperand(MCOperand::CreateImm(0));
1371 // Otherwise, it's a normal memory reg+offset.
1372 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1373 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1374 Inst.addOperand(MCOperand::CreateImm(Val));
1377 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1378 assert(N == 2 && "Invalid number of operands!");
1379 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1380 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1383 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
1384 assert(N == 2 && "Invalid number of operands!");
1385 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1386 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1389 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1390 assert(N == 3 && "Invalid number of operands!");
1391 unsigned Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1392 Memory.ShiftImm, Memory.ShiftType);
1393 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1394 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1395 Inst.addOperand(MCOperand::CreateImm(Val));
1398 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1399 assert(N == 3 && "Invalid number of operands!");
1400 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1401 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1402 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
1405 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1406 assert(N == 2 && "Invalid number of operands!");
1407 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1408 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1411 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1412 assert(N == 2 && "Invalid number of operands!");
1413 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1414 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1415 Inst.addOperand(MCOperand::CreateImm(Val));
1418 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1419 assert(N == 2 && "Invalid number of operands!");
1420 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
1421 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1422 Inst.addOperand(MCOperand::CreateImm(Val));
1425 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1426 assert(N == 2 && "Invalid number of operands!");
1427 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
1428 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1429 Inst.addOperand(MCOperand::CreateImm(Val));
1432 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1433 assert(N == 2 && "Invalid number of operands!");
1434 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1435 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1436 Inst.addOperand(MCOperand::CreateImm(Val));
1439 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1440 assert(N == 1 && "Invalid number of operands!");
1441 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1442 assert(CE && "non-constant post-idx-imm8 operand!");
1443 int Imm = CE->getValue();
1444 bool isAdd = Imm >= 0;
1445 if (Imm == INT32_MIN) Imm = 0;
1446 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1447 Inst.addOperand(MCOperand::CreateImm(Imm));
1450 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
1451 assert(N == 1 && "Invalid number of operands!");
1452 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1453 assert(CE && "non-constant post-idx-imm8s4 operand!");
1454 int Imm = CE->getValue();
1455 bool isAdd = Imm >= 0;
1456 if (Imm == INT32_MIN) Imm = 0;
1457 // Immediate is scaled by 4.
1458 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
1459 Inst.addOperand(MCOperand::CreateImm(Imm));
1462 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1463 assert(N == 2 && "Invalid number of operands!");
1464 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1465 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1468 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1469 assert(N == 2 && "Invalid number of operands!");
1470 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1471 // The sign, shift type, and shift amount are encoded in a single operand
1472 // using the AM2 encoding helpers.
1473 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1474 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1475 PostIdxReg.ShiftTy);
1476 Inst.addOperand(MCOperand::CreateImm(Imm));
1479 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1480 assert(N == 1 && "Invalid number of operands!");
1481 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1484 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1485 assert(N == 1 && "Invalid number of operands!");
1486 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1489 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
1490 assert(N == 1 && "Invalid number of operands!");
1491 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1494 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
1495 assert(N == 1 && "Invalid number of operands!");
1496 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1499 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
1500 assert(N == 1 && "Invalid number of operands!");
1501 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1504 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
1505 assert(N == 1 && "Invalid number of operands!");
1506 // The immediate encodes the type of constant as well as the value.
1507 // Mask in that this is an i8 splat.
1508 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1509 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
1512 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
1513 assert(N == 1 && "Invalid number of operands!");
1514 // The immediate encodes the type of constant as well as the value.
1515 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1516 unsigned Value = CE->getValue();
1518 Value = (Value >> 8) | 0xa00;
1521 Inst.addOperand(MCOperand::CreateImm(Value));
1524 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
1525 assert(N == 1 && "Invalid number of operands!");
1526 // The immediate encodes the type of constant as well as the value.
1527 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1528 unsigned Value = CE->getValue();
1529 if (Value >= 256 && Value <= 0xff00)
1530 Value = (Value >> 8) | 0x200;
1531 else if (Value > 0xffff && Value <= 0xff0000)
1532 Value = (Value >> 16) | 0x400;
1533 else if (Value > 0xffffff)
1534 Value = (Value >> 24) | 0x600;
1535 Inst.addOperand(MCOperand::CreateImm(Value));
1538 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
1539 assert(N == 1 && "Invalid number of operands!");
1540 // The immediate encodes the type of constant as well as the value.
1541 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1542 unsigned Value = CE->getValue();
1543 if (Value >= 256 && Value <= 0xffff)
1544 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
1545 else if (Value > 0xffff && Value <= 0xffffff)
1546 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
1547 else if (Value > 0xffffff)
1548 Value = (Value >> 24) | 0x600;
1549 Inst.addOperand(MCOperand::CreateImm(Value));
1552 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
1553 assert(N == 1 && "Invalid number of operands!");
1554 // The immediate encodes the type of constant as well as the value.
1555 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1556 uint64_t Value = CE->getValue();
1558 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
1559 Imm |= (Value & 1) << i;
1561 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
1564 virtual void print(raw_ostream &OS) const;
1566 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
1567 ARMOperand *Op = new ARMOperand(k_ITCondMask);
1568 Op->ITMask.Mask = Mask;
1574 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1575 ARMOperand *Op = new ARMOperand(k_CondCode);
1582 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1583 ARMOperand *Op = new ARMOperand(k_CoprocNum);
1584 Op->Cop.Val = CopVal;
1590 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1591 ARMOperand *Op = new ARMOperand(k_CoprocReg);
1592 Op->Cop.Val = CopVal;
1598 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
1599 ARMOperand *Op = new ARMOperand(k_CoprocOption);
1606 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1607 ARMOperand *Op = new ARMOperand(k_CCOut);
1608 Op->Reg.RegNum = RegNum;
1614 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1615 ARMOperand *Op = new ARMOperand(k_Token);
1616 Op->Tok.Data = Str.data();
1617 Op->Tok.Length = Str.size();
1623 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1624 ARMOperand *Op = new ARMOperand(k_Register);
1625 Op->Reg.RegNum = RegNum;
1631 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1636 ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
1637 Op->RegShiftedReg.ShiftTy = ShTy;
1638 Op->RegShiftedReg.SrcReg = SrcReg;
1639 Op->RegShiftedReg.ShiftReg = ShiftReg;
1640 Op->RegShiftedReg.ShiftImm = ShiftImm;
1646 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1650 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
1651 Op->RegShiftedImm.ShiftTy = ShTy;
1652 Op->RegShiftedImm.SrcReg = SrcReg;
1653 Op->RegShiftedImm.ShiftImm = ShiftImm;
1659 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1661 ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
1662 Op->ShifterImm.isASR = isASR;
1663 Op->ShifterImm.Imm = Imm;
1669 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1670 ARMOperand *Op = new ARMOperand(k_RotateImmediate);
1671 Op->RotImm.Imm = Imm;
1677 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1679 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
1680 Op->Bitfield.LSB = LSB;
1681 Op->Bitfield.Width = Width;
1688 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1689 SMLoc StartLoc, SMLoc EndLoc) {
1690 KindTy Kind = k_RegisterList;
1692 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
1693 Kind = k_DPRRegisterList;
1694 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
1695 contains(Regs.front().first))
1696 Kind = k_SPRRegisterList;
1698 ARMOperand *Op = new ARMOperand(Kind);
1699 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1700 I = Regs.begin(), E = Regs.end(); I != E; ++I)
1701 Op->Registers.push_back(I->first);
1702 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1703 Op->StartLoc = StartLoc;
1704 Op->EndLoc = EndLoc;
1708 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
1710 ARMOperand *Op = new ARMOperand(k_VectorIndex);
1711 Op->VectorIndex.Val = Idx;
1717 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1718 ARMOperand *Op = new ARMOperand(k_Immediate);
1725 static ARMOperand *CreateFPImm(unsigned Val, SMLoc S, MCContext &Ctx) {
1726 ARMOperand *Op = new ARMOperand(k_FPImmediate);
1727 Op->FPImm.Val = Val;
1733 static ARMOperand *CreateMem(unsigned BaseRegNum,
1734 const MCConstantExpr *OffsetImm,
1735 unsigned OffsetRegNum,
1736 ARM_AM::ShiftOpc ShiftType,
1741 ARMOperand *Op = new ARMOperand(k_Memory);
1742 Op->Memory.BaseRegNum = BaseRegNum;
1743 Op->Memory.OffsetImm = OffsetImm;
1744 Op->Memory.OffsetRegNum = OffsetRegNum;
1745 Op->Memory.ShiftType = ShiftType;
1746 Op->Memory.ShiftImm = ShiftImm;
1747 Op->Memory.Alignment = Alignment;
1748 Op->Memory.isNegative = isNegative;
1754 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1755 ARM_AM::ShiftOpc ShiftTy,
1758 ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
1759 Op->PostIdxReg.RegNum = RegNum;
1760 Op->PostIdxReg.isAdd = isAdd;
1761 Op->PostIdxReg.ShiftTy = ShiftTy;
1762 Op->PostIdxReg.ShiftImm = ShiftImm;
1768 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1769 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
1770 Op->MBOpt.Val = Opt;
1776 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1777 ARMOperand *Op = new ARMOperand(k_ProcIFlags);
1778 Op->IFlags.Val = IFlags;
1784 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1785 ARMOperand *Op = new ARMOperand(k_MSRMask);
1786 Op->MMask.Val = MMask;
1793 } // end anonymous namespace.
1795 void ARMOperand::print(raw_ostream &OS) const {
1798 OS << "<fpimm " << getFPImm() << "(" << ARM_AM::getFPImmFloat(getFPImm())
1802 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1805 OS << "<ccout " << getReg() << ">";
1807 case k_ITCondMask: {
1808 static char MaskStr[][6] = { "()", "(t)", "(e)", "(tt)", "(et)", "(te)",
1809 "(ee)", "(ttt)", "(ett)", "(tet)", "(eet)", "(tte)", "(ete)",
1811 assert((ITMask.Mask & 0xf) == ITMask.Mask);
1812 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
1816 OS << "<coprocessor number: " << getCoproc() << ">";
1819 OS << "<coprocessor register: " << getCoproc() << ">";
1821 case k_CoprocOption:
1822 OS << "<coprocessor option: " << CoprocOption.Val << ">";
1825 OS << "<mask: " << getMSRMask() << ">";
1828 getImm()->print(OS);
1830 case k_MemBarrierOpt:
1831 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1835 << " base:" << Memory.BaseRegNum;
1838 case k_PostIndexRegister:
1839 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
1840 << PostIdxReg.RegNum;
1841 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1842 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1843 << PostIdxReg.ShiftImm;
1846 case k_ProcIFlags: {
1847 OS << "<ARM_PROC::";
1848 unsigned IFlags = getProcIFlags();
1849 for (int i=2; i >= 0; --i)
1850 if (IFlags & (1 << i))
1851 OS << ARM_PROC::IFlagsToString(1 << i);
1856 OS << "<register " << getReg() << ">";
1858 case k_ShifterImmediate:
1859 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1860 << " #" << ShifterImm.Imm << ">";
1862 case k_ShiftedRegister:
1863 OS << "<so_reg_reg "
1864 << RegShiftedReg.SrcReg
1865 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1866 << ", " << RegShiftedReg.ShiftReg << ", "
1867 << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1870 case k_ShiftedImmediate:
1871 OS << "<so_reg_imm "
1872 << RegShiftedImm.SrcReg
1873 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1874 << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
1877 case k_RotateImmediate:
1878 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
1880 case k_BitfieldDescriptor:
1881 OS << "<bitfield " << "lsb: " << Bitfield.LSB
1882 << ", width: " << Bitfield.Width << ">";
1884 case k_RegisterList:
1885 case k_DPRRegisterList:
1886 case k_SPRRegisterList: {
1887 OS << "<register_list ";
1889 const SmallVectorImpl<unsigned> &RegList = getRegList();
1890 for (SmallVectorImpl<unsigned>::const_iterator
1891 I = RegList.begin(), E = RegList.end(); I != E; ) {
1893 if (++I < E) OS << ", ";
1900 OS << "'" << getToken() << "'";
1903 OS << "<vectorindex " << getVectorIndex() << ">";
1908 /// @name Auto-generated Match Functions
1911 static unsigned MatchRegisterName(StringRef Name);
1915 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
1916 SMLoc &StartLoc, SMLoc &EndLoc) {
1917 RegNo = tryParseRegister();
1919 return (RegNo == (unsigned)-1);
1922 /// Try to parse a register name. The token must be an Identifier when called,
1923 /// and if it is a register name the token is eaten and the register number is
1924 /// returned. Otherwise return -1.
1926 int ARMAsmParser::tryParseRegister() {
1927 const AsmToken &Tok = Parser.getTok();
1928 if (Tok.isNot(AsmToken::Identifier)) return -1;
1930 // FIXME: Validate register for the current architecture; we have to do
1931 // validation later, so maybe there is no need for this here.
1932 std::string upperCase = Tok.getString().str();
1933 std::string lowerCase = LowercaseString(upperCase);
1934 unsigned RegNum = MatchRegisterName(lowerCase);
1936 RegNum = StringSwitch<unsigned>(lowerCase)
1937 .Case("r13", ARM::SP)
1938 .Case("r14", ARM::LR)
1939 .Case("r15", ARM::PC)
1940 .Case("ip", ARM::R12)
1943 if (!RegNum) return -1;
1945 Parser.Lex(); // Eat identifier token.
1948 // Also check for an index operand. This is only legal for vector registers,
1949 // but that'll get caught OK in operand matching, so we don't need to
1950 // explicitly filter everything else out here.
1951 if (Parser.getTok().is(AsmToken::LBrac)) {
1952 SMLoc SIdx = Parser.getTok().getLoc();
1953 Parser.Lex(); // Eat left bracket token.
1955 const MCExpr *ImmVal;
1956 if (getParser().ParseExpression(ImmVal))
1957 return MatchOperand_ParseFail;
1958 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
1960 TokError("immediate value expected for vector index");
1961 return MatchOperand_ParseFail;
1964 SMLoc E = Parser.getTok().getLoc();
1965 if (Parser.getTok().isNot(AsmToken::RBrac)) {
1966 Error(E, "']' expected");
1967 return MatchOperand_ParseFail;
1970 Parser.Lex(); // Eat right bracket token.
1972 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
1981 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
1982 // If a recoverable error occurs, return 1. If an irrecoverable error
1983 // occurs, return -1. An irrecoverable error is one where tokens have been
1984 // consumed in the process of trying to parse the shifter (i.e., when it is
1985 // indeed a shifter operand, but malformed).
1986 int ARMAsmParser::tryParseShiftRegister(
1987 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1988 SMLoc S = Parser.getTok().getLoc();
1989 const AsmToken &Tok = Parser.getTok();
1990 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1992 std::string upperCase = Tok.getString().str();
1993 std::string lowerCase = LowercaseString(upperCase);
1994 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
1995 .Case("lsl", ARM_AM::lsl)
1996 .Case("lsr", ARM_AM::lsr)
1997 .Case("asr", ARM_AM::asr)
1998 .Case("ror", ARM_AM::ror)
1999 .Case("rrx", ARM_AM::rrx)
2000 .Default(ARM_AM::no_shift);
2002 if (ShiftTy == ARM_AM::no_shift)
2005 Parser.Lex(); // Eat the operator.
2007 // The source register for the shift has already been added to the
2008 // operand list, so we need to pop it off and combine it into the shifted
2009 // register operand instead.
2010 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2011 if (!PrevOp->isReg())
2012 return Error(PrevOp->getStartLoc(), "shift must be of a register");
2013 int SrcReg = PrevOp->getReg();
2016 if (ShiftTy == ARM_AM::rrx) {
2017 // RRX Doesn't have an explicit shift amount. The encoder expects
2018 // the shift register to be the same as the source register. Seems odd,
2022 // Figure out if this is shifted by a constant or a register (for non-RRX).
2023 if (Parser.getTok().is(AsmToken::Hash)) {
2024 Parser.Lex(); // Eat hash.
2025 SMLoc ImmLoc = Parser.getTok().getLoc();
2026 const MCExpr *ShiftExpr = 0;
2027 if (getParser().ParseExpression(ShiftExpr)) {
2028 Error(ImmLoc, "invalid immediate shift value");
2031 // The expression must be evaluatable as an immediate.
2032 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2034 Error(ImmLoc, "invalid immediate shift value");
2037 // Range check the immediate.
2038 // lsl, ror: 0 <= imm <= 31
2039 // lsr, asr: 0 <= imm <= 32
2040 Imm = CE->getValue();
2042 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2043 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2044 Error(ImmLoc, "immediate shift value out of range");
2047 } else if (Parser.getTok().is(AsmToken::Identifier)) {
2048 ShiftReg = tryParseRegister();
2049 SMLoc L = Parser.getTok().getLoc();
2050 if (ShiftReg == -1) {
2051 Error (L, "expected immediate or register in shift operand");
2055 Error (Parser.getTok().getLoc(),
2056 "expected immediate or register in shift operand");
2061 if (ShiftReg && ShiftTy != ARM_AM::rrx)
2062 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2064 S, Parser.getTok().getLoc()));
2066 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2067 S, Parser.getTok().getLoc()));
2073 /// Try to parse a register name. The token must be an Identifier when called.
2074 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
2075 /// if there is a "writeback". 'true' if it's not a register.
2077 /// TODO this is likely to change to allow different register types and or to
2078 /// parse for a specific register type.
2080 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2081 SMLoc S = Parser.getTok().getLoc();
2082 int RegNo = tryParseRegister();
2086 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
2088 const AsmToken &ExclaimTok = Parser.getTok();
2089 if (ExclaimTok.is(AsmToken::Exclaim)) {
2090 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2091 ExclaimTok.getLoc()));
2092 Parser.Lex(); // Eat exclaim token
2096 // Also check for an index operand. This is only legal for vector registers,
2097 // but that'll get caught OK in operand matching, so we don't need to
2098 // explicitly filter everything else out here.
2099 if (Parser.getTok().is(AsmToken::LBrac)) {
2100 SMLoc SIdx = Parser.getTok().getLoc();
2101 Parser.Lex(); // Eat left bracket token.
2103 const MCExpr *ImmVal;
2104 if (getParser().ParseExpression(ImmVal))
2105 return MatchOperand_ParseFail;
2106 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2108 TokError("immediate value expected for vector index");
2109 return MatchOperand_ParseFail;
2112 SMLoc E = Parser.getTok().getLoc();
2113 if (Parser.getTok().isNot(AsmToken::RBrac)) {
2114 Error(E, "']' expected");
2115 return MatchOperand_ParseFail;
2118 Parser.Lex(); // Eat right bracket token.
2120 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2128 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
2129 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2131 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2132 // Use the same layout as the tablegen'erated register name matcher. Ugly,
2134 switch (Name.size()) {
2137 if (Name[0] != CoprocOp)
2154 if (Name[0] != CoprocOp || Name[1] != '1')
2158 case '0': return 10;
2159 case '1': return 11;
2160 case '2': return 12;
2161 case '3': return 13;
2162 case '4': return 14;
2163 case '5': return 15;
2171 /// parseITCondCode - Try to parse a condition code for an IT instruction.
2172 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2173 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2174 SMLoc S = Parser.getTok().getLoc();
2175 const AsmToken &Tok = Parser.getTok();
2176 if (!Tok.is(AsmToken::Identifier))
2177 return MatchOperand_NoMatch;
2178 unsigned CC = StringSwitch<unsigned>(Tok.getString())
2179 .Case("eq", ARMCC::EQ)
2180 .Case("ne", ARMCC::NE)
2181 .Case("hs", ARMCC::HS)
2182 .Case("cs", ARMCC::HS)
2183 .Case("lo", ARMCC::LO)
2184 .Case("cc", ARMCC::LO)
2185 .Case("mi", ARMCC::MI)
2186 .Case("pl", ARMCC::PL)
2187 .Case("vs", ARMCC::VS)
2188 .Case("vc", ARMCC::VC)
2189 .Case("hi", ARMCC::HI)
2190 .Case("ls", ARMCC::LS)
2191 .Case("ge", ARMCC::GE)
2192 .Case("lt", ARMCC::LT)
2193 .Case("gt", ARMCC::GT)
2194 .Case("le", ARMCC::LE)
2195 .Case("al", ARMCC::AL)
2198 return MatchOperand_NoMatch;
2199 Parser.Lex(); // Eat the token.
2201 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2203 return MatchOperand_Success;
2206 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2207 /// token must be an Identifier when called, and if it is a coprocessor
2208 /// number, the token is eaten and the operand is added to the operand list.
2209 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2210 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2211 SMLoc S = Parser.getTok().getLoc();
2212 const AsmToken &Tok = Parser.getTok();
2213 if (Tok.isNot(AsmToken::Identifier))
2214 return MatchOperand_NoMatch;
2216 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2218 return MatchOperand_NoMatch;
2220 Parser.Lex(); // Eat identifier token.
2221 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2222 return MatchOperand_Success;
2225 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2226 /// token must be an Identifier when called, and if it is a coprocessor
2227 /// number, the token is eaten and the operand is added to the operand list.
2228 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2229 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2230 SMLoc S = Parser.getTok().getLoc();
2231 const AsmToken &Tok = Parser.getTok();
2232 if (Tok.isNot(AsmToken::Identifier))
2233 return MatchOperand_NoMatch;
2235 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2237 return MatchOperand_NoMatch;
2239 Parser.Lex(); // Eat identifier token.
2240 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2241 return MatchOperand_Success;
2244 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2245 /// coproc_option : '{' imm0_255 '}'
2246 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2247 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2248 SMLoc S = Parser.getTok().getLoc();
2250 // If this isn't a '{', this isn't a coprocessor immediate operand.
2251 if (Parser.getTok().isNot(AsmToken::LCurly))
2252 return MatchOperand_NoMatch;
2253 Parser.Lex(); // Eat the '{'
2256 SMLoc Loc = Parser.getTok().getLoc();
2257 if (getParser().ParseExpression(Expr)) {
2258 Error(Loc, "illegal expression");
2259 return MatchOperand_ParseFail;
2261 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2262 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2263 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2264 return MatchOperand_ParseFail;
2266 int Val = CE->getValue();
2268 // Check for and consume the closing '}'
2269 if (Parser.getTok().isNot(AsmToken::RCurly))
2270 return MatchOperand_ParseFail;
2271 SMLoc E = Parser.getTok().getLoc();
2272 Parser.Lex(); // Eat the '}'
2274 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2275 return MatchOperand_Success;
2278 // For register list parsing, we need to map from raw GPR register numbering
2279 // to the enumeration values. The enumeration values aren't sorted by
2280 // register number due to our using "sp", "lr" and "pc" as canonical names.
2281 static unsigned getNextRegister(unsigned Reg) {
2282 // If this is a GPR, we need to do it manually, otherwise we can rely
2283 // on the sort ordering of the enumeration since the other reg-classes
2285 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2288 default: assert(0 && "Invalid GPR number!");
2289 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
2290 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
2291 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
2292 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
2293 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
2294 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2295 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
2296 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
2300 /// Parse a register list.
2302 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2303 assert(Parser.getTok().is(AsmToken::LCurly) &&
2304 "Token is not a Left Curly Brace");
2305 SMLoc S = Parser.getTok().getLoc();
2306 Parser.Lex(); // Eat '{' token.
2307 SMLoc RegLoc = Parser.getTok().getLoc();
2309 // Check the first register in the list to see what register class
2310 // this is a list of.
2311 int Reg = tryParseRegister();
2313 return Error(RegLoc, "register expected");
2315 MCRegisterClass *RC;
2316 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2317 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
2318 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
2319 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
2320 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
2321 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
2323 return Error(RegLoc, "invalid register in register list");
2325 // The reglist instructions have at most 16 registers, so reserve
2326 // space for that many.
2327 SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
2328 // Store the first register.
2329 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2331 // This starts immediately after the first register token in the list,
2332 // so we can see either a comma or a minus (range separator) as a legal
2334 while (Parser.getTok().is(AsmToken::Comma) ||
2335 Parser.getTok().is(AsmToken::Minus)) {
2336 if (Parser.getTok().is(AsmToken::Minus)) {
2337 Parser.Lex(); // Eat the comma.
2338 SMLoc EndLoc = Parser.getTok().getLoc();
2339 int EndReg = tryParseRegister();
2341 return Error(EndLoc, "register expected");
2342 // If the register is the same as the start reg, there's nothing
2346 // The register must be in the same register class as the first.
2347 if (!RC->contains(EndReg))
2348 return Error(EndLoc, "invalid register in register list");
2349 // Ranges must go from low to high.
2350 if (getARMRegisterNumbering(Reg) > getARMRegisterNumbering(EndReg))
2351 return Error(EndLoc, "bad range in register list");
2353 // Add all the registers in the range to the register list.
2354 while (Reg != EndReg) {
2355 Reg = getNextRegister(Reg);
2356 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2360 Parser.Lex(); // Eat the comma.
2361 RegLoc = Parser.getTok().getLoc();
2363 Reg = tryParseRegister();
2365 return Error(RegLoc, "register expected");
2366 // The register must be in the same register class as the first.
2367 if (!RC->contains(Reg))
2368 return Error(RegLoc, "invalid register in register list");
2369 // List must be monotonically increasing.
2370 if (getARMRegisterNumbering(Reg) <= getARMRegisterNumbering(OldReg))
2371 return Error(RegLoc, "register list not in ascending order");
2372 // VFP register lists must also be contiguous.
2373 // It's OK to use the enumeration values directly here rather, as the
2374 // VFP register classes have the enum sorted properly.
2375 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
2377 return Error(RegLoc, "non-contiguous register range");
2378 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2381 SMLoc E = Parser.getTok().getLoc();
2382 if (Parser.getTok().isNot(AsmToken::RCurly))
2383 return Error(E, "'}' expected");
2384 Parser.Lex(); // Eat '}' token.
2386 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
2390 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
2391 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2392 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2393 SMLoc S = Parser.getTok().getLoc();
2394 const AsmToken &Tok = Parser.getTok();
2395 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2396 StringRef OptStr = Tok.getString();
2398 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
2399 .Case("sy", ARM_MB::SY)
2400 .Case("st", ARM_MB::ST)
2401 .Case("sh", ARM_MB::ISH)
2402 .Case("ish", ARM_MB::ISH)
2403 .Case("shst", ARM_MB::ISHST)
2404 .Case("ishst", ARM_MB::ISHST)
2405 .Case("nsh", ARM_MB::NSH)
2406 .Case("un", ARM_MB::NSH)
2407 .Case("nshst", ARM_MB::NSHST)
2408 .Case("unst", ARM_MB::NSHST)
2409 .Case("osh", ARM_MB::OSH)
2410 .Case("oshst", ARM_MB::OSHST)
2414 return MatchOperand_NoMatch;
2416 Parser.Lex(); // Eat identifier token.
2417 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
2418 return MatchOperand_Success;
2421 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
2422 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2423 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2424 SMLoc S = Parser.getTok().getLoc();
2425 const AsmToken &Tok = Parser.getTok();
2426 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2427 StringRef IFlagsStr = Tok.getString();
2429 // An iflags string of "none" is interpreted to mean that none of the AIF
2430 // bits are set. Not a terribly useful instruction, but a valid encoding.
2431 unsigned IFlags = 0;
2432 if (IFlagsStr != "none") {
2433 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
2434 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
2435 .Case("a", ARM_PROC::A)
2436 .Case("i", ARM_PROC::I)
2437 .Case("f", ARM_PROC::F)
2440 // If some specific iflag is already set, it means that some letter is
2441 // present more than once, this is not acceptable.
2442 if (Flag == ~0U || (IFlags & Flag))
2443 return MatchOperand_NoMatch;
2449 Parser.Lex(); // Eat identifier token.
2450 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
2451 return MatchOperand_Success;
2454 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
2455 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2456 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2457 SMLoc S = Parser.getTok().getLoc();
2458 const AsmToken &Tok = Parser.getTok();
2459 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2460 StringRef Mask = Tok.getString();
2463 // See ARMv6-M 10.1.1
2464 unsigned FlagsVal = StringSwitch<unsigned>(Mask)
2474 .Case("primask", 16)
2475 .Case("basepri", 17)
2476 .Case("basepri_max", 18)
2477 .Case("faultmask", 19)
2478 .Case("control", 20)
2481 if (FlagsVal == ~0U)
2482 return MatchOperand_NoMatch;
2484 if (!hasV7Ops() && FlagsVal >= 17 && FlagsVal <= 19)
2485 // basepri, basepri_max and faultmask only valid for V7m.
2486 return MatchOperand_NoMatch;
2488 Parser.Lex(); // Eat identifier token.
2489 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
2490 return MatchOperand_Success;
2493 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
2494 size_t Start = 0, Next = Mask.find('_');
2495 StringRef Flags = "";
2496 std::string SpecReg = LowercaseString(Mask.slice(Start, Next));
2497 if (Next != StringRef::npos)
2498 Flags = Mask.slice(Next+1, Mask.size());
2500 // FlagsVal contains the complete mask:
2502 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
2503 unsigned FlagsVal = 0;
2505 if (SpecReg == "apsr") {
2506 FlagsVal = StringSwitch<unsigned>(Flags)
2507 .Case("nzcvq", 0x8) // same as CPSR_f
2508 .Case("g", 0x4) // same as CPSR_s
2509 .Case("nzcvqg", 0xc) // same as CPSR_fs
2512 if (FlagsVal == ~0U) {
2514 return MatchOperand_NoMatch;
2516 FlagsVal = 8; // No flag
2518 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
2519 if (Flags == "all") // cpsr_all is an alias for cpsr_fc
2521 for (int i = 0, e = Flags.size(); i != e; ++i) {
2522 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
2529 // If some specific flag is already set, it means that some letter is
2530 // present more than once, this is not acceptable.
2531 if (FlagsVal == ~0U || (FlagsVal & Flag))
2532 return MatchOperand_NoMatch;
2535 } else // No match for special register.
2536 return MatchOperand_NoMatch;
2538 // Special register without flags are equivalent to "fc" flags.
2542 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
2543 if (SpecReg == "spsr")
2546 Parser.Lex(); // Eat identifier token.
2547 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
2548 return MatchOperand_Success;
2551 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2552 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
2553 int Low, int High) {
2554 const AsmToken &Tok = Parser.getTok();
2555 if (Tok.isNot(AsmToken::Identifier)) {
2556 Error(Parser.getTok().getLoc(), Op + " operand expected.");
2557 return MatchOperand_ParseFail;
2559 StringRef ShiftName = Tok.getString();
2560 std::string LowerOp = LowercaseString(Op);
2561 std::string UpperOp = UppercaseString(Op);
2562 if (ShiftName != LowerOp && ShiftName != UpperOp) {
2563 Error(Parser.getTok().getLoc(), Op + " operand expected.");
2564 return MatchOperand_ParseFail;
2566 Parser.Lex(); // Eat shift type token.
2568 // There must be a '#' and a shift amount.
2569 if (Parser.getTok().isNot(AsmToken::Hash)) {
2570 Error(Parser.getTok().getLoc(), "'#' expected");
2571 return MatchOperand_ParseFail;
2573 Parser.Lex(); // Eat hash token.
2575 const MCExpr *ShiftAmount;
2576 SMLoc Loc = Parser.getTok().getLoc();
2577 if (getParser().ParseExpression(ShiftAmount)) {
2578 Error(Loc, "illegal expression");
2579 return MatchOperand_ParseFail;
2581 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2583 Error(Loc, "constant expression expected");
2584 return MatchOperand_ParseFail;
2586 int Val = CE->getValue();
2587 if (Val < Low || Val > High) {
2588 Error(Loc, "immediate value out of range");
2589 return MatchOperand_ParseFail;
2592 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
2594 return MatchOperand_Success;
2597 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2598 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2599 const AsmToken &Tok = Parser.getTok();
2600 SMLoc S = Tok.getLoc();
2601 if (Tok.isNot(AsmToken::Identifier)) {
2602 Error(Tok.getLoc(), "'be' or 'le' operand expected");
2603 return MatchOperand_ParseFail;
2605 int Val = StringSwitch<int>(Tok.getString())
2609 Parser.Lex(); // Eat the token.
2612 Error(Tok.getLoc(), "'be' or 'le' operand expected");
2613 return MatchOperand_ParseFail;
2615 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
2617 S, Parser.getTok().getLoc()));
2618 return MatchOperand_Success;
2621 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
2622 /// instructions. Legal values are:
2623 /// lsl #n 'n' in [0,31]
2624 /// asr #n 'n' in [1,32]
2625 /// n == 32 encoded as n == 0.
2626 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2627 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2628 const AsmToken &Tok = Parser.getTok();
2629 SMLoc S = Tok.getLoc();
2630 if (Tok.isNot(AsmToken::Identifier)) {
2631 Error(S, "shift operator 'asr' or 'lsl' expected");
2632 return MatchOperand_ParseFail;
2634 StringRef ShiftName = Tok.getString();
2636 if (ShiftName == "lsl" || ShiftName == "LSL")
2638 else if (ShiftName == "asr" || ShiftName == "ASR")
2641 Error(S, "shift operator 'asr' or 'lsl' expected");
2642 return MatchOperand_ParseFail;
2644 Parser.Lex(); // Eat the operator.
2646 // A '#' and a shift amount.
2647 if (Parser.getTok().isNot(AsmToken::Hash)) {
2648 Error(Parser.getTok().getLoc(), "'#' expected");
2649 return MatchOperand_ParseFail;
2651 Parser.Lex(); // Eat hash token.
2653 const MCExpr *ShiftAmount;
2654 SMLoc E = Parser.getTok().getLoc();
2655 if (getParser().ParseExpression(ShiftAmount)) {
2656 Error(E, "malformed shift expression");
2657 return MatchOperand_ParseFail;
2659 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2661 Error(E, "shift amount must be an immediate");
2662 return MatchOperand_ParseFail;
2665 int64_t Val = CE->getValue();
2667 // Shift amount must be in [1,32]
2668 if (Val < 1 || Val > 32) {
2669 Error(E, "'asr' shift amount must be in range [1,32]");
2670 return MatchOperand_ParseFail;
2672 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
2673 if (isThumb() && Val == 32) {
2674 Error(E, "'asr #32' shift amount not allowed in Thumb mode");
2675 return MatchOperand_ParseFail;
2677 if (Val == 32) Val = 0;
2679 // Shift amount must be in [1,32]
2680 if (Val < 0 || Val > 31) {
2681 Error(E, "'lsr' shift amount must be in range [0,31]");
2682 return MatchOperand_ParseFail;
2686 E = Parser.getTok().getLoc();
2687 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
2689 return MatchOperand_Success;
2692 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
2693 /// of instructions. Legal values are:
2694 /// ror #n 'n' in {0, 8, 16, 24}
2695 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2696 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2697 const AsmToken &Tok = Parser.getTok();
2698 SMLoc S = Tok.getLoc();
2699 if (Tok.isNot(AsmToken::Identifier))
2700 return MatchOperand_NoMatch;
2701 StringRef ShiftName = Tok.getString();
2702 if (ShiftName != "ror" && ShiftName != "ROR")
2703 return MatchOperand_NoMatch;
2704 Parser.Lex(); // Eat the operator.
2706 // A '#' and a rotate amount.
2707 if (Parser.getTok().isNot(AsmToken::Hash)) {
2708 Error(Parser.getTok().getLoc(), "'#' expected");
2709 return MatchOperand_ParseFail;
2711 Parser.Lex(); // Eat hash token.
2713 const MCExpr *ShiftAmount;
2714 SMLoc E = Parser.getTok().getLoc();
2715 if (getParser().ParseExpression(ShiftAmount)) {
2716 Error(E, "malformed rotate expression");
2717 return MatchOperand_ParseFail;
2719 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2721 Error(E, "rotate amount must be an immediate");
2722 return MatchOperand_ParseFail;
2725 int64_t Val = CE->getValue();
2726 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
2727 // normally, zero is represented in asm by omitting the rotate operand
2729 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
2730 Error(E, "'ror' rotate amount must be 8, 16, or 24");
2731 return MatchOperand_ParseFail;
2734 E = Parser.getTok().getLoc();
2735 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
2737 return MatchOperand_Success;
2740 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2741 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2742 SMLoc S = Parser.getTok().getLoc();
2743 // The bitfield descriptor is really two operands, the LSB and the width.
2744 if (Parser.getTok().isNot(AsmToken::Hash)) {
2745 Error(Parser.getTok().getLoc(), "'#' expected");
2746 return MatchOperand_ParseFail;
2748 Parser.Lex(); // Eat hash token.
2750 const MCExpr *LSBExpr;
2751 SMLoc E = Parser.getTok().getLoc();
2752 if (getParser().ParseExpression(LSBExpr)) {
2753 Error(E, "malformed immediate expression");
2754 return MatchOperand_ParseFail;
2756 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
2758 Error(E, "'lsb' operand must be an immediate");
2759 return MatchOperand_ParseFail;
2762 int64_t LSB = CE->getValue();
2763 // The LSB must be in the range [0,31]
2764 if (LSB < 0 || LSB > 31) {
2765 Error(E, "'lsb' operand must be in the range [0,31]");
2766 return MatchOperand_ParseFail;
2768 E = Parser.getTok().getLoc();
2770 // Expect another immediate operand.
2771 if (Parser.getTok().isNot(AsmToken::Comma)) {
2772 Error(Parser.getTok().getLoc(), "too few operands");
2773 return MatchOperand_ParseFail;
2775 Parser.Lex(); // Eat hash token.
2776 if (Parser.getTok().isNot(AsmToken::Hash)) {
2777 Error(Parser.getTok().getLoc(), "'#' expected");
2778 return MatchOperand_ParseFail;
2780 Parser.Lex(); // Eat hash token.
2782 const MCExpr *WidthExpr;
2783 if (getParser().ParseExpression(WidthExpr)) {
2784 Error(E, "malformed immediate expression");
2785 return MatchOperand_ParseFail;
2787 CE = dyn_cast<MCConstantExpr>(WidthExpr);
2789 Error(E, "'width' operand must be an immediate");
2790 return MatchOperand_ParseFail;
2793 int64_t Width = CE->getValue();
2794 // The LSB must be in the range [1,32-lsb]
2795 if (Width < 1 || Width > 32 - LSB) {
2796 Error(E, "'width' operand must be in the range [1,32-lsb]");
2797 return MatchOperand_ParseFail;
2799 E = Parser.getTok().getLoc();
2801 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
2803 return MatchOperand_Success;
2806 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2807 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2808 // Check for a post-index addressing register operand. Specifically:
2809 // postidx_reg := '+' register {, shift}
2810 // | '-' register {, shift}
2811 // | register {, shift}
2813 // This method must return MatchOperand_NoMatch without consuming any tokens
2814 // in the case where there is no match, as other alternatives take other
2816 AsmToken Tok = Parser.getTok();
2817 SMLoc S = Tok.getLoc();
2818 bool haveEaten = false;
2821 if (Tok.is(AsmToken::Plus)) {
2822 Parser.Lex(); // Eat the '+' token.
2824 } else if (Tok.is(AsmToken::Minus)) {
2825 Parser.Lex(); // Eat the '-' token.
2829 if (Parser.getTok().is(AsmToken::Identifier))
2830 Reg = tryParseRegister();
2833 return MatchOperand_NoMatch;
2834 Error(Parser.getTok().getLoc(), "register expected");
2835 return MatchOperand_ParseFail;
2837 SMLoc E = Parser.getTok().getLoc();
2839 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
2840 unsigned ShiftImm = 0;
2841 if (Parser.getTok().is(AsmToken::Comma)) {
2842 Parser.Lex(); // Eat the ','.
2843 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
2844 return MatchOperand_ParseFail;
2847 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
2850 return MatchOperand_Success;
2853 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2854 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2855 // Check for a post-index addressing register operand. Specifically:
2856 // am3offset := '+' register
2863 // This method must return MatchOperand_NoMatch without consuming any tokens
2864 // in the case where there is no match, as other alternatives take other
2866 AsmToken Tok = Parser.getTok();
2867 SMLoc S = Tok.getLoc();
2869 // Do immediates first, as we always parse those if we have a '#'.
2870 if (Parser.getTok().is(AsmToken::Hash)) {
2871 Parser.Lex(); // Eat the '#'.
2872 // Explicitly look for a '-', as we need to encode negative zero
2874 bool isNegative = Parser.getTok().is(AsmToken::Minus);
2875 const MCExpr *Offset;
2876 if (getParser().ParseExpression(Offset))
2877 return MatchOperand_ParseFail;
2878 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2880 Error(S, "constant expression expected");
2881 return MatchOperand_ParseFail;
2883 SMLoc E = Tok.getLoc();
2884 // Negative zero is encoded as the flag value INT32_MIN.
2885 int32_t Val = CE->getValue();
2886 if (isNegative && Val == 0)
2890 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
2892 return MatchOperand_Success;
2896 bool haveEaten = false;
2899 if (Tok.is(AsmToken::Plus)) {
2900 Parser.Lex(); // Eat the '+' token.
2902 } else if (Tok.is(AsmToken::Minus)) {
2903 Parser.Lex(); // Eat the '-' token.
2907 if (Parser.getTok().is(AsmToken::Identifier))
2908 Reg = tryParseRegister();
2911 return MatchOperand_NoMatch;
2912 Error(Parser.getTok().getLoc(), "register expected");
2913 return MatchOperand_ParseFail;
2915 SMLoc E = Parser.getTok().getLoc();
2917 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
2920 return MatchOperand_Success;
2923 /// cvtT2LdrdPre - Convert parsed operands to MCInst.
2924 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2925 /// when they refer multiple MIOperands inside a single one.
2927 cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
2928 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2930 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2931 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2932 // Create a writeback register dummy placeholder.
2933 Inst.addOperand(MCOperand::CreateReg(0));
2935 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
2937 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2941 /// cvtT2StrdPre - Convert parsed operands to MCInst.
2942 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2943 /// when they refer multiple MIOperands inside a single one.
2945 cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
2946 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2947 // Create a writeback register dummy placeholder.
2948 Inst.addOperand(MCOperand::CreateReg(0));
2950 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2951 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2953 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
2955 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2959 /// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
2960 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2961 /// when they refer multiple MIOperands inside a single one.
2963 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
2964 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2965 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2967 // Create a writeback register dummy placeholder.
2968 Inst.addOperand(MCOperand::CreateImm(0));
2970 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
2971 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2975 /// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
2976 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2977 /// when they refer multiple MIOperands inside a single one.
2979 cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
2980 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2981 // Create a writeback register dummy placeholder.
2982 Inst.addOperand(MCOperand::CreateImm(0));
2983 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2984 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
2985 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2989 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2990 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2991 /// when they refer multiple MIOperands inside a single one.
2993 cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2994 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2995 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2997 // Create a writeback register dummy placeholder.
2998 Inst.addOperand(MCOperand::CreateImm(0));
3000 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3001 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3005 /// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3006 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3007 /// when they refer multiple MIOperands inside a single one.
3009 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3010 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3011 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3013 // Create a writeback register dummy placeholder.
3014 Inst.addOperand(MCOperand::CreateImm(0));
3016 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3017 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3022 /// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3023 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3024 /// when they refer multiple MIOperands inside a single one.
3026 cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3027 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3028 // Create a writeback register dummy placeholder.
3029 Inst.addOperand(MCOperand::CreateImm(0));
3030 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3031 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3032 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3036 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3037 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3038 /// when they refer multiple MIOperands inside a single one.
3040 cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3041 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3042 // Create a writeback register dummy placeholder.
3043 Inst.addOperand(MCOperand::CreateImm(0));
3044 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3045 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3046 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3050 /// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
3051 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3052 /// when they refer multiple MIOperands inside a single one.
3054 cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
3055 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3056 // Create a writeback register dummy placeholder.
3057 Inst.addOperand(MCOperand::CreateImm(0));
3058 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3059 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
3060 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3064 /// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
3065 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3066 /// when they refer multiple MIOperands inside a single one.
3068 cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
3069 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3071 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3072 // Create a writeback register dummy placeholder.
3073 Inst.addOperand(MCOperand::CreateImm(0));
3075 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3077 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
3079 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3083 /// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
3084 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3085 /// when they refer multiple MIOperands inside a single one.
3087 cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
3088 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3090 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3091 // Create a writeback register dummy placeholder.
3092 Inst.addOperand(MCOperand::CreateImm(0));
3094 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3096 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
3098 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3102 /// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
3103 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3104 /// when they refer multiple MIOperands inside a single one.
3106 cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
3107 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3108 // Create a writeback register dummy placeholder.
3109 Inst.addOperand(MCOperand::CreateImm(0));
3111 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3113 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3115 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
3117 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3121 /// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
3122 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3123 /// when they refer multiple MIOperands inside a single one.
3125 cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
3126 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3127 // Create a writeback register dummy placeholder.
3128 Inst.addOperand(MCOperand::CreateImm(0));
3130 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3132 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3134 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
3136 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3140 /// cvtLdrdPre - Convert parsed operands to MCInst.
3141 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3142 /// when they refer multiple MIOperands inside a single one.
3144 cvtLdrdPre(MCInst &Inst, unsigned Opcode,
3145 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3147 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3148 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3149 // Create a writeback register dummy placeholder.
3150 Inst.addOperand(MCOperand::CreateImm(0));
3152 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
3154 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3158 /// cvtStrdPre - Convert parsed operands to MCInst.
3159 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3160 /// when they refer multiple MIOperands inside a single one.
3162 cvtStrdPre(MCInst &Inst, unsigned Opcode,
3163 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3164 // Create a writeback register dummy placeholder.
3165 Inst.addOperand(MCOperand::CreateImm(0));
3167 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3168 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3170 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
3172 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3176 /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
3177 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3178 /// when they refer multiple MIOperands inside a single one.
3180 cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
3181 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3182 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3183 // Create a writeback register dummy placeholder.
3184 Inst.addOperand(MCOperand::CreateImm(0));
3185 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
3186 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3190 /// cvtThumbMultiple- Convert parsed operands to MCInst.
3191 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3192 /// when they refer multiple MIOperands inside a single one.
3194 cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
3195 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3196 // The second source operand must be the same register as the destination
3198 if (Operands.size() == 6 &&
3199 (((ARMOperand*)Operands[3])->getReg() !=
3200 ((ARMOperand*)Operands[5])->getReg()) &&
3201 (((ARMOperand*)Operands[3])->getReg() !=
3202 ((ARMOperand*)Operands[4])->getReg())) {
3203 Error(Operands[3]->getStartLoc(),
3204 "destination register must match source register");
3207 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3208 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
3209 ((ARMOperand*)Operands[4])->addRegOperands(Inst, 1);
3210 // If we have a three-operand form, use that, else the second source operand
3211 // is just the destination operand again.
3212 if (Operands.size() == 6)
3213 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
3215 Inst.addOperand(Inst.getOperand(0));
3216 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
3221 /// Parse an ARM memory expression, return false if successful else return true
3222 /// or an error. The first token must be a '[' when called.
3224 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3226 assert(Parser.getTok().is(AsmToken::LBrac) &&
3227 "Token is not a Left Bracket");
3228 S = Parser.getTok().getLoc();
3229 Parser.Lex(); // Eat left bracket token.
3231 const AsmToken &BaseRegTok = Parser.getTok();
3232 int BaseRegNum = tryParseRegister();
3233 if (BaseRegNum == -1)
3234 return Error(BaseRegTok.getLoc(), "register expected");
3236 // The next token must either be a comma or a closing bracket.
3237 const AsmToken &Tok = Parser.getTok();
3238 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
3239 return Error(Tok.getLoc(), "malformed memory operand");
3241 if (Tok.is(AsmToken::RBrac)) {
3243 Parser.Lex(); // Eat right bracket token.
3245 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
3246 0, 0, false, S, E));
3248 // If there's a pre-indexing writeback marker, '!', just add it as a token
3249 // operand. It's rather odd, but syntactically valid.
3250 if (Parser.getTok().is(AsmToken::Exclaim)) {
3251 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3252 Parser.Lex(); // Eat the '!'.
3258 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
3259 Parser.Lex(); // Eat the comma.
3261 // If we have a ':', it's an alignment specifier.
3262 if (Parser.getTok().is(AsmToken::Colon)) {
3263 Parser.Lex(); // Eat the ':'.
3264 E = Parser.getTok().getLoc();
3267 if (getParser().ParseExpression(Expr))
3270 // The expression has to be a constant. Memory references with relocations
3271 // don't come through here, as they use the <label> forms of the relevant
3273 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3275 return Error (E, "constant expression expected");
3278 switch (CE->getValue()) {
3280 return Error(E, "alignment specifier must be 64, 128, or 256 bits");
3281 case 64: Align = 8; break;
3282 case 128: Align = 16; break;
3283 case 256: Align = 32; break;
3286 // Now we should have the closing ']'
3287 E = Parser.getTok().getLoc();
3288 if (Parser.getTok().isNot(AsmToken::RBrac))
3289 return Error(E, "']' expected");
3290 Parser.Lex(); // Eat right bracket token.
3292 // Don't worry about range checking the value here. That's handled by
3293 // the is*() predicates.
3294 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
3295 ARM_AM::no_shift, 0, Align,
3298 // If there's a pre-indexing writeback marker, '!', just add it as a token
3300 if (Parser.getTok().is(AsmToken::Exclaim)) {
3301 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3302 Parser.Lex(); // Eat the '!'.
3308 // If we have a '#', it's an immediate offset, else assume it's a register
3310 if (Parser.getTok().is(AsmToken::Hash)) {
3311 Parser.Lex(); // Eat the '#'.
3312 E = Parser.getTok().getLoc();
3314 bool isNegative = getParser().getTok().is(AsmToken::Minus);
3315 const MCExpr *Offset;
3316 if (getParser().ParseExpression(Offset))
3319 // The expression has to be a constant. Memory references with relocations
3320 // don't come through here, as they use the <label> forms of the relevant
3322 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
3324 return Error (E, "constant expression expected");
3326 // If the constant was #-0, represent it as INT32_MIN.
3327 int32_t Val = CE->getValue();
3328 if (isNegative && Val == 0)
3329 CE = MCConstantExpr::Create(INT32_MIN, getContext());
3331 // Now we should have the closing ']'
3332 E = Parser.getTok().getLoc();
3333 if (Parser.getTok().isNot(AsmToken::RBrac))
3334 return Error(E, "']' expected");
3335 Parser.Lex(); // Eat right bracket token.
3337 // Don't worry about range checking the value here. That's handled by
3338 // the is*() predicates.
3339 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
3340 ARM_AM::no_shift, 0, 0,
3343 // If there's a pre-indexing writeback marker, '!', just add it as a token
3345 if (Parser.getTok().is(AsmToken::Exclaim)) {
3346 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3347 Parser.Lex(); // Eat the '!'.
3353 // The register offset is optionally preceded by a '+' or '-'
3354 bool isNegative = false;
3355 if (Parser.getTok().is(AsmToken::Minus)) {
3357 Parser.Lex(); // Eat the '-'.
3358 } else if (Parser.getTok().is(AsmToken::Plus)) {
3360 Parser.Lex(); // Eat the '+'.
3363 E = Parser.getTok().getLoc();
3364 int OffsetRegNum = tryParseRegister();
3365 if (OffsetRegNum == -1)
3366 return Error(E, "register expected");
3368 // If there's a shift operator, handle it.
3369 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
3370 unsigned ShiftImm = 0;
3371 if (Parser.getTok().is(AsmToken::Comma)) {
3372 Parser.Lex(); // Eat the ','.
3373 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
3377 // Now we should have the closing ']'
3378 E = Parser.getTok().getLoc();
3379 if (Parser.getTok().isNot(AsmToken::RBrac))
3380 return Error(E, "']' expected");
3381 Parser.Lex(); // Eat right bracket token.
3383 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
3384 ShiftType, ShiftImm, 0, isNegative,
3387 // If there's a pre-indexing writeback marker, '!', just add it as a token
3389 if (Parser.getTok().is(AsmToken::Exclaim)) {
3390 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3391 Parser.Lex(); // Eat the '!'.
3397 /// parseMemRegOffsetShift - one of these two:
3398 /// ( lsl | lsr | asr | ror ) , # shift_amount
3400 /// return true if it parses a shift otherwise it returns false.
3401 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
3403 SMLoc Loc = Parser.getTok().getLoc();
3404 const AsmToken &Tok = Parser.getTok();
3405 if (Tok.isNot(AsmToken::Identifier))
3407 StringRef ShiftName = Tok.getString();
3408 if (ShiftName == "lsl" || ShiftName == "LSL")
3410 else if (ShiftName == "lsr" || ShiftName == "LSR")
3412 else if (ShiftName == "asr" || ShiftName == "ASR")
3414 else if (ShiftName == "ror" || ShiftName == "ROR")
3416 else if (ShiftName == "rrx" || ShiftName == "RRX")
3419 return Error(Loc, "illegal shift operator");
3420 Parser.Lex(); // Eat shift type token.
3422 // rrx stands alone.
3424 if (St != ARM_AM::rrx) {
3425 Loc = Parser.getTok().getLoc();
3426 // A '#' and a shift amount.
3427 const AsmToken &HashTok = Parser.getTok();
3428 if (HashTok.isNot(AsmToken::Hash))
3429 return Error(HashTok.getLoc(), "'#' expected");
3430 Parser.Lex(); // Eat hash token.
3433 if (getParser().ParseExpression(Expr))
3435 // Range check the immediate.
3436 // lsl, ror: 0 <= imm <= 31
3437 // lsr, asr: 0 <= imm <= 32
3438 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3440 return Error(Loc, "shift amount must be an immediate");
3441 int64_t Imm = CE->getValue();
3443 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
3444 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
3445 return Error(Loc, "immediate shift value out of range");
3452 /// parseFPImm - A floating point immediate expression operand.
3453 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3454 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3455 SMLoc S = Parser.getTok().getLoc();
3457 if (Parser.getTok().isNot(AsmToken::Hash))
3458 return MatchOperand_NoMatch;
3460 // Disambiguate the VMOV forms that can accept an FP immediate.
3461 // vmov.f32 <sreg>, #imm
3462 // vmov.f64 <dreg>, #imm
3463 // vmov.f32 <dreg>, #imm @ vector f32x2
3464 // vmov.f32 <qreg>, #imm @ vector f32x4
3466 // There are also the NEON VMOV instructions which expect an
3467 // integer constant. Make sure we don't try to parse an FPImm
3469 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
3470 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
3471 if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
3472 TyOp->getToken() != ".f64"))
3473 return MatchOperand_NoMatch;
3475 Parser.Lex(); // Eat the '#'.
3477 // Handle negation, as that still comes through as a separate token.
3478 bool isNegative = false;
3479 if (Parser.getTok().is(AsmToken::Minus)) {
3483 const AsmToken &Tok = Parser.getTok();
3484 if (Tok.is(AsmToken::Real)) {
3485 APFloat RealVal(APFloat::IEEEdouble, Tok.getString());
3486 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
3487 // If we had a '-' in front, toggle the sign bit.
3488 IntVal ^= (uint64_t)isNegative << 63;
3489 int Val = ARM_AM::getFP64Imm(APInt(64, IntVal));
3490 Parser.Lex(); // Eat the token.
3492 TokError("floating point value out of range");
3493 return MatchOperand_ParseFail;
3495 Operands.push_back(ARMOperand::CreateFPImm(Val, S, getContext()));
3496 return MatchOperand_Success;
3498 if (Tok.is(AsmToken::Integer)) {
3499 int64_t Val = Tok.getIntVal();
3500 Parser.Lex(); // Eat the token.
3501 if (Val > 255 || Val < 0) {
3502 TokError("encoded floating point value out of range");
3503 return MatchOperand_ParseFail;
3505 Operands.push_back(ARMOperand::CreateFPImm(Val, S, getContext()));
3506 return MatchOperand_Success;
3509 TokError("invalid floating point immediate");
3510 return MatchOperand_ParseFail;
3512 /// Parse a arm instruction operand. For now this parses the operand regardless
3513 /// of the mnemonic.
3514 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
3515 StringRef Mnemonic) {
3518 // Check if the current operand has a custom associated parser, if so, try to
3519 // custom parse the operand, or fallback to the general approach.
3520 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
3521 if (ResTy == MatchOperand_Success)
3523 // If there wasn't a custom match, try the generic matcher below. Otherwise,
3524 // there was a match, but an error occurred, in which case, just return that
3525 // the operand parsing failed.
3526 if (ResTy == MatchOperand_ParseFail)
3529 switch (getLexer().getKind()) {
3531 Error(Parser.getTok().getLoc(), "unexpected token in operand");
3533 case AsmToken::Identifier: {
3534 // If this is VMRS, check for the apsr_nzcv operand.
3535 if (!tryParseRegisterWithWriteBack(Operands))
3537 int Res = tryParseShiftRegister(Operands);
3538 if (Res == 0) // success
3540 else if (Res == -1) // irrecoverable error
3542 if (Mnemonic == "vmrs" && Parser.getTok().getString() == "apsr_nzcv") {
3543 S = Parser.getTok().getLoc();
3545 Operands.push_back(ARMOperand::CreateToken("apsr_nzcv", S));
3549 // Fall though for the Identifier case that is not a register or a
3552 case AsmToken::Integer: // things like 1f and 2b as a branch targets
3553 case AsmToken::Dot: { // . as a branch target
3554 // This was not a register so parse other operands that start with an
3555 // identifier (like labels) as expressions and create them as immediates.
3556 const MCExpr *IdVal;
3557 S = Parser.getTok().getLoc();
3558 if (getParser().ParseExpression(IdVal))
3560 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3561 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
3564 case AsmToken::LBrac:
3565 return parseMemory(Operands);
3566 case AsmToken::LCurly:
3567 return parseRegisterList(Operands);
3568 case AsmToken::Hash: {
3569 // #42 -> immediate.
3570 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
3571 S = Parser.getTok().getLoc();
3573 bool isNegative = Parser.getTok().is(AsmToken::Minus);
3574 const MCExpr *ImmVal;
3575 if (getParser().ParseExpression(ImmVal))
3577 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
3579 Error(S, "constant expression expected");
3580 return MatchOperand_ParseFail;
3582 int32_t Val = CE->getValue();
3583 if (isNegative && Val == 0)
3584 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
3585 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3586 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
3589 case AsmToken::Colon: {
3590 // ":lower16:" and ":upper16:" expression prefixes
3591 // FIXME: Check it's an expression prefix,
3592 // e.g. (FOO - :lower16:BAR) isn't legal.
3593 ARMMCExpr::VariantKind RefKind;
3594 if (parsePrefix(RefKind))
3597 const MCExpr *SubExprVal;
3598 if (getParser().ParseExpression(SubExprVal))
3601 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
3603 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3604 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
3610 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
3611 // :lower16: and :upper16:.
3612 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
3613 RefKind = ARMMCExpr::VK_ARM_None;
3615 // :lower16: and :upper16: modifiers
3616 assert(getLexer().is(AsmToken::Colon) && "expected a :");
3617 Parser.Lex(); // Eat ':'
3619 if (getLexer().isNot(AsmToken::Identifier)) {
3620 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
3624 StringRef IDVal = Parser.getTok().getIdentifier();
3625 if (IDVal == "lower16") {
3626 RefKind = ARMMCExpr::VK_ARM_LO16;
3627 } else if (IDVal == "upper16") {
3628 RefKind = ARMMCExpr::VK_ARM_HI16;
3630 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
3635 if (getLexer().isNot(AsmToken::Colon)) {
3636 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
3639 Parser.Lex(); // Eat the last ':'
3643 /// \brief Given a mnemonic, split out possible predication code and carry
3644 /// setting letters to form a canonical mnemonic and flags.
3646 // FIXME: Would be nice to autogen this.
3647 // FIXME: This is a bit of a maze of special cases.
3648 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
3649 unsigned &PredicationCode,
3651 unsigned &ProcessorIMod,
3652 StringRef &ITMask) {
3653 PredicationCode = ARMCC::AL;
3654 CarrySetting = false;
3657 // Ignore some mnemonics we know aren't predicated forms.
3659 // FIXME: Would be nice to autogen this.
3660 if ((Mnemonic == "movs" && isThumb()) ||
3661 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
3662 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
3663 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
3664 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
3665 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
3666 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
3667 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
3670 // First, split out any predication code. Ignore mnemonics we know aren't
3671 // predicated but do have a carry-set and so weren't caught above.
3672 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
3673 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
3674 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
3675 Mnemonic != "sbcs" && Mnemonic != "rscs") {
3676 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
3677 .Case("eq", ARMCC::EQ)
3678 .Case("ne", ARMCC::NE)
3679 .Case("hs", ARMCC::HS)
3680 .Case("cs", ARMCC::HS)
3681 .Case("lo", ARMCC::LO)
3682 .Case("cc", ARMCC::LO)
3683 .Case("mi", ARMCC::MI)
3684 .Case("pl", ARMCC::PL)
3685 .Case("vs", ARMCC::VS)
3686 .Case("vc", ARMCC::VC)
3687 .Case("hi", ARMCC::HI)
3688 .Case("ls", ARMCC::LS)
3689 .Case("ge", ARMCC::GE)
3690 .Case("lt", ARMCC::LT)
3691 .Case("gt", ARMCC::GT)
3692 .Case("le", ARMCC::LE)
3693 .Case("al", ARMCC::AL)
3696 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
3697 PredicationCode = CC;
3701 // Next, determine if we have a carry setting bit. We explicitly ignore all
3702 // the instructions we know end in 's'.
3703 if (Mnemonic.endswith("s") &&
3704 !(Mnemonic == "cps" || Mnemonic == "mls" ||
3705 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
3706 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
3707 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
3708 Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
3709 (Mnemonic == "movs" && isThumb()))) {
3710 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
3711 CarrySetting = true;
3714 // The "cps" instruction can have a interrupt mode operand which is glued into
3715 // the mnemonic. Check if this is the case, split it and parse the imod op
3716 if (Mnemonic.startswith("cps")) {
3717 // Split out any imod code.
3719 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
3720 .Case("ie", ARM_PROC::IE)
3721 .Case("id", ARM_PROC::ID)
3724 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
3725 ProcessorIMod = IMod;
3729 // The "it" instruction has the condition mask on the end of the mnemonic.
3730 if (Mnemonic.startswith("it")) {
3731 ITMask = Mnemonic.slice(2, Mnemonic.size());
3732 Mnemonic = Mnemonic.slice(0, 2);
3738 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
3739 /// inclusion of carry set or predication code operands.
3741 // FIXME: It would be nice to autogen this.
3743 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
3744 bool &CanAcceptPredicationCode) {
3745 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
3746 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
3747 Mnemonic == "add" || Mnemonic == "adc" ||
3748 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
3749 Mnemonic == "orr" || Mnemonic == "mvn" ||
3750 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
3751 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
3752 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
3753 Mnemonic == "mla" || Mnemonic == "smlal" ||
3754 Mnemonic == "umlal" || Mnemonic == "umull"))) {
3755 CanAcceptCarrySet = true;
3757 CanAcceptCarrySet = false;
3759 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
3760 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
3761 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
3762 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
3763 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
3764 (Mnemonic == "clrex" && !isThumb()) ||
3765 (Mnemonic == "nop" && isThumbOne()) ||
3766 ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" ||
3767 Mnemonic == "ldc2" || Mnemonic == "ldc2l" ||
3768 Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) ||
3769 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
3771 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
3772 CanAcceptPredicationCode = false;
3774 CanAcceptPredicationCode = true;
3777 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
3778 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
3779 CanAcceptPredicationCode = false;
3783 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
3784 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3785 // FIXME: This is all horribly hacky. We really need a better way to deal
3786 // with optional operands like this in the matcher table.
3788 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
3789 // another does not. Specifically, the MOVW instruction does not. So we
3790 // special case it here and remove the defaulted (non-setting) cc_out
3791 // operand if that's the instruction we're trying to match.
3793 // We do this as post-processing of the explicit operands rather than just
3794 // conditionally adding the cc_out in the first place because we need
3795 // to check the type of the parsed immediate operand.
3796 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
3797 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
3798 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
3799 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3802 // Register-register 'add' for thumb does not have a cc_out operand
3803 // when there are only two register operands.
3804 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
3805 static_cast<ARMOperand*>(Operands[3])->isReg() &&
3806 static_cast<ARMOperand*>(Operands[4])->isReg() &&
3807 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3809 // Register-register 'add' for thumb does not have a cc_out operand
3810 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
3811 // have to check the immediate range here since Thumb2 has a variant
3812 // that can handle a different range and has a cc_out operand.
3813 if (((isThumb() && Mnemonic == "add") ||
3814 (isThumbTwo() && Mnemonic == "sub")) &&
3815 Operands.size() == 6 &&
3816 static_cast<ARMOperand*>(Operands[3])->isReg() &&
3817 static_cast<ARMOperand*>(Operands[4])->isReg() &&
3818 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
3819 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
3820 (static_cast<ARMOperand*>(Operands[5])->isReg() ||
3821 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
3823 // For Thumb2, add/sub immediate does not have a cc_out operand for the
3824 // imm0_4095 variant. That's the least-preferred variant when
3825 // selecting via the generic "add" mnemonic, so to know that we
3826 // should remove the cc_out operand, we have to explicitly check that
3827 // it's not one of the other variants. Ugh.
3828 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
3829 Operands.size() == 6 &&
3830 static_cast<ARMOperand*>(Operands[3])->isReg() &&
3831 static_cast<ARMOperand*>(Operands[4])->isReg() &&
3832 static_cast<ARMOperand*>(Operands[5])->isImm()) {
3833 // Nest conditions rather than one big 'if' statement for readability.
3835 // If either register is a high reg, it's either one of the SP
3836 // variants (handled above) or a 32-bit encoding, so we just
3837 // check against T3.
3838 if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
3839 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
3840 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
3842 // If both registers are low, we're in an IT block, and the immediate is
3843 // in range, we should use encoding T1 instead, which has a cc_out.
3845 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
3846 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
3847 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
3850 // Otherwise, we use encoding T4, which does not have a cc_out
3855 // The thumb2 multiply instruction doesn't have a CCOut register, so
3856 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
3857 // use the 16-bit encoding or not.
3858 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
3859 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
3860 static_cast<ARMOperand*>(Operands[3])->isReg() &&
3861 static_cast<ARMOperand*>(Operands[4])->isReg() &&
3862 static_cast<ARMOperand*>(Operands[5])->isReg() &&
3863 // If the registers aren't low regs, the destination reg isn't the
3864 // same as one of the source regs, or the cc_out operand is zero
3865 // outside of an IT block, we have to use the 32-bit encoding, so
3866 // remove the cc_out operand.
3867 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
3868 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
3870 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
3871 static_cast<ARMOperand*>(Operands[5])->getReg() &&
3872 static_cast<ARMOperand*>(Operands[3])->getReg() !=
3873 static_cast<ARMOperand*>(Operands[4])->getReg())))
3878 // Register-register 'add/sub' for thumb does not have a cc_out operand
3879 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
3880 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
3881 // right, this will result in better diagnostics (which operand is off)
3883 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
3884 (Operands.size() == 5 || Operands.size() == 6) &&
3885 static_cast<ARMOperand*>(Operands[3])->isReg() &&
3886 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
3887 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3893 /// Parse an arm instruction mnemonic followed by its operands.
3894 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
3895 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3896 // Create the leading tokens for the mnemonic, split by '.' characters.
3897 size_t Start = 0, Next = Name.find('.');
3898 StringRef Mnemonic = Name.slice(Start, Next);
3900 // Split out the predication code and carry setting flag from the mnemonic.
3901 unsigned PredicationCode;
3902 unsigned ProcessorIMod;
3905 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
3906 ProcessorIMod, ITMask);
3908 // In Thumb1, only the branch (B) instruction can be predicated.
3909 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
3910 Parser.EatToEndOfStatement();
3911 return Error(NameLoc, "conditional execution not supported in Thumb1");
3914 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
3916 // Handle the IT instruction ITMask. Convert it to a bitmask. This
3917 // is the mask as it will be for the IT encoding if the conditional
3918 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
3919 // where the conditional bit0 is zero, the instruction post-processing
3920 // will adjust the mask accordingly.
3921 if (Mnemonic == "it") {
3922 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
3923 if (ITMask.size() > 3) {
3924 Parser.EatToEndOfStatement();
3925 return Error(Loc, "too many conditions on IT instruction");
3928 for (unsigned i = ITMask.size(); i != 0; --i) {
3929 char pos = ITMask[i - 1];
3930 if (pos != 't' && pos != 'e') {
3931 Parser.EatToEndOfStatement();
3932 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
3935 if (ITMask[i - 1] == 't')
3938 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
3941 // FIXME: This is all a pretty gross hack. We should automatically handle
3942 // optional operands like this via tblgen.
3944 // Next, add the CCOut and ConditionCode operands, if needed.
3946 // For mnemonics which can ever incorporate a carry setting bit or predication
3947 // code, our matching model involves us always generating CCOut and
3948 // ConditionCode operands to match the mnemonic "as written" and then we let
3949 // the matcher deal with finding the right instruction or generating an
3950 // appropriate error.
3951 bool CanAcceptCarrySet, CanAcceptPredicationCode;
3952 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
3954 // If we had a carry-set on an instruction that can't do that, issue an
3956 if (!CanAcceptCarrySet && CarrySetting) {
3957 Parser.EatToEndOfStatement();
3958 return Error(NameLoc, "instruction '" + Mnemonic +
3959 "' can not set flags, but 's' suffix specified");
3961 // If we had a predication code on an instruction that can't do that, issue an
3963 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
3964 Parser.EatToEndOfStatement();
3965 return Error(NameLoc, "instruction '" + Mnemonic +
3966 "' is not predicable, but condition code specified");
3969 // Add the carry setting operand, if necessary.
3970 if (CanAcceptCarrySet) {
3971 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
3972 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
3976 // Add the predication code operand, if necessary.
3977 if (CanAcceptPredicationCode) {
3978 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
3980 Operands.push_back(ARMOperand::CreateCondCode(
3981 ARMCC::CondCodes(PredicationCode), Loc));
3984 // Add the processor imod operand, if necessary.
3985 if (ProcessorIMod) {
3986 Operands.push_back(ARMOperand::CreateImm(
3987 MCConstantExpr::Create(ProcessorIMod, getContext()),
3991 // Add the remaining tokens in the mnemonic.
3992 while (Next != StringRef::npos) {
3994 Next = Name.find('.', Start + 1);
3995 StringRef ExtraToken = Name.slice(Start, Next);
3997 // For now, we're only parsing Thumb1 (for the most part), so
3998 // just ignore ".n" qualifiers. We'll use them to restrict
3999 // matching when we do Thumb2.
4000 if (ExtraToken != ".n") {
4001 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
4002 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
4006 // Read the remaining operands.
4007 if (getLexer().isNot(AsmToken::EndOfStatement)) {
4008 // Read the first operand.
4009 if (parseOperand(Operands, Mnemonic)) {
4010 Parser.EatToEndOfStatement();
4014 while (getLexer().is(AsmToken::Comma)) {
4015 Parser.Lex(); // Eat the comma.
4017 // Parse and remember the operand.
4018 if (parseOperand(Operands, Mnemonic)) {
4019 Parser.EatToEndOfStatement();
4025 if (getLexer().isNot(AsmToken::EndOfStatement)) {
4026 SMLoc Loc = getLexer().getLoc();
4027 Parser.EatToEndOfStatement();
4028 return Error(Loc, "unexpected token in argument list");
4031 Parser.Lex(); // Consume the EndOfStatement
4033 // Some instructions, mostly Thumb, have forms for the same mnemonic that
4034 // do and don't have a cc_out optional-def operand. With some spot-checks
4035 // of the operand list, we can figure out which variant we're trying to
4036 // parse and adjust accordingly before actually matching. We shouldn't ever
4037 // try to remove a cc_out operand that was explicitly set on the the
4038 // mnemonic, of course (CarrySetting == true). Reason number #317 the
4039 // table driven matcher doesn't fit well with the ARM instruction set.
4040 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
4041 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
4042 Operands.erase(Operands.begin() + 1);
4046 // ARM mode 'blx' need special handling, as the register operand version
4047 // is predicable, but the label operand version is not. So, we can't rely
4048 // on the Mnemonic based checking to correctly figure out when to put
4049 // a k_CondCode operand in the list. If we're trying to match the label
4050 // version, remove the k_CondCode operand here.
4051 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
4052 static_cast<ARMOperand*>(Operands[2])->isImm()) {
4053 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
4054 Operands.erase(Operands.begin() + 1);
4058 // The vector-compare-to-zero instructions have a literal token "#0" at
4059 // the end that comes to here as an immediate operand. Convert it to a
4060 // token to play nicely with the matcher.
4061 if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
4062 Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
4063 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4064 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
4065 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4066 if (CE && CE->getValue() == 0) {
4067 Operands.erase(Operands.begin() + 5);
4068 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4072 // VCMP{E} does the same thing, but with a different operand count.
4073 if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 &&
4074 static_cast<ARMOperand*>(Operands[4])->isImm()) {
4075 ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]);
4076 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4077 if (CE && CE->getValue() == 0) {
4078 Operands.erase(Operands.begin() + 4);
4079 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4083 // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
4084 // end. Convert it to a token here.
4085 if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
4086 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4087 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
4088 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4089 if (CE && CE->getValue() == 0) {
4090 Operands.erase(Operands.begin() + 5);
4091 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4099 // Validate context-sensitive operand constraints.
4101 // return 'true' if register list contains non-low GPR registers,
4102 // 'false' otherwise. If Reg is in the register list or is HiReg, set
4103 // 'containsReg' to true.
4104 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
4105 unsigned HiReg, bool &containsReg) {
4106 containsReg = false;
4107 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
4108 unsigned OpReg = Inst.getOperand(i).getReg();
4111 // Anything other than a low register isn't legal here.
4112 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
4118 // Check if the specified regisgter is in the register list of the inst,
4119 // starting at the indicated operand number.
4120 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
4121 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
4122 unsigned OpReg = Inst.getOperand(i).getReg();
4129 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around
4130 // the ARMInsts array) instead. Getting that here requires awkward
4131 // API changes, though. Better way?
4133 extern MCInstrDesc ARMInsts[];
4135 static MCInstrDesc &getInstDesc(unsigned Opcode) {
4136 return ARMInsts[Opcode];
4139 // FIXME: We would really like to be able to tablegen'erate this.
4141 validateInstruction(MCInst &Inst,
4142 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4143 MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
4144 SMLoc Loc = Operands[0]->getStartLoc();
4145 // Check the IT block state first.
4146 // NOTE: In Thumb mode, the BKPT instruction has the interesting property of
4147 // being allowed in IT blocks, but not being predicable. It just always
4149 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT) {
4151 if (ITState.FirstCond)
4152 ITState.FirstCond = false;
4154 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
4155 // The instruction must be predicable.
4156 if (!MCID.isPredicable())
4157 return Error(Loc, "instructions in IT block must be predicable");
4158 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
4159 unsigned ITCond = bit ? ITState.Cond :
4160 ARMCC::getOppositeCondition(ITState.Cond);
4161 if (Cond != ITCond) {
4162 // Find the condition code Operand to get its SMLoc information.
4164 for (unsigned i = 1; i < Operands.size(); ++i)
4165 if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
4166 CondLoc = Operands[i]->getStartLoc();
4167 return Error(CondLoc, "incorrect condition in IT block; got '" +
4168 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
4169 "', but expected '" +
4170 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
4172 // Check for non-'al' condition codes outside of the IT block.
4173 } else if (isThumbTwo() && MCID.isPredicable() &&
4174 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
4175 ARMCC::AL && Inst.getOpcode() != ARM::tB &&
4176 Inst.getOpcode() != ARM::t2B)
4177 return Error(Loc, "predicated instructions must be in IT block");
4179 switch (Inst.getOpcode()) {
4182 case ARM::LDRD_POST:
4184 // Rt2 must be Rt + 1.
4185 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
4186 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
4188 return Error(Operands[3]->getStartLoc(),
4189 "destination operands must be sequential");
4193 // Rt2 must be Rt + 1.
4194 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
4195 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
4197 return Error(Operands[3]->getStartLoc(),
4198 "source operands must be sequential");
4202 case ARM::STRD_POST:
4204 // Rt2 must be Rt + 1.
4205 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
4206 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
4208 return Error(Operands[3]->getStartLoc(),
4209 "source operands must be sequential");
4214 // width must be in range [1, 32-lsb]
4215 unsigned lsb = Inst.getOperand(2).getImm();
4216 unsigned widthm1 = Inst.getOperand(3).getImm();
4217 if (widthm1 >= 32 - lsb)
4218 return Error(Operands[5]->getStartLoc(),
4219 "bitfield width must be in range [1,32-lsb]");
4223 // If we're parsing Thumb2, the .w variant is available and handles
4224 // most cases that are normally illegal for a Thumb1 LDM
4225 // instruction. We'll make the transformation in processInstruction()
4228 // Thumb LDM instructions are writeback iff the base register is not
4229 // in the register list.
4230 unsigned Rn = Inst.getOperand(0).getReg();
4231 bool hasWritebackToken =
4232 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
4233 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
4234 bool listContainsBase;
4235 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
4236 return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
4237 "registers must be in range r0-r7");
4238 // If we should have writeback, then there should be a '!' token.
4239 if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
4240 return Error(Operands[2]->getStartLoc(),
4241 "writeback operator '!' expected");
4242 // If we should not have writeback, there must not be a '!'. This is
4243 // true even for the 32-bit wide encodings.
4244 if (listContainsBase && hasWritebackToken)
4245 return Error(Operands[3]->getStartLoc(),
4246 "writeback operator '!' not allowed when base register "
4247 "in register list");
4251 case ARM::t2LDMIA_UPD: {
4252 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
4253 return Error(Operands[4]->getStartLoc(),
4254 "writeback operator '!' not allowed when base register "
4255 "in register list");
4259 bool listContainsBase;
4260 if (checkLowRegisterList(Inst, 3, 0, ARM::PC, listContainsBase))
4261 return Error(Operands[2]->getStartLoc(),
4262 "registers must be in range r0-r7 or pc");
4266 bool listContainsBase;
4267 if (checkLowRegisterList(Inst, 3, 0, ARM::LR, listContainsBase))
4268 return Error(Operands[2]->getStartLoc(),
4269 "registers must be in range r0-r7 or lr");
4272 case ARM::tSTMIA_UPD: {
4273 bool listContainsBase;
4274 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
4275 return Error(Operands[4]->getStartLoc(),
4276 "registers must be in range r0-r7");
4285 processInstruction(MCInst &Inst,
4286 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4287 switch (Inst.getOpcode()) {
4288 case ARM::LDMIA_UPD:
4289 // If this is a load of a single register via a 'pop', then we should use
4290 // a post-indexed LDR instruction instead, per the ARM ARM.
4291 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
4292 Inst.getNumOperands() == 5) {
4294 TmpInst.setOpcode(ARM::LDR_POST_IMM);
4295 TmpInst.addOperand(Inst.getOperand(4)); // Rt
4296 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
4297 TmpInst.addOperand(Inst.getOperand(1)); // Rn
4298 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
4299 TmpInst.addOperand(MCOperand::CreateImm(4));
4300 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
4301 TmpInst.addOperand(Inst.getOperand(3));
4305 case ARM::STMDB_UPD:
4306 // If this is a store of a single register via a 'push', then we should use
4307 // a pre-indexed STR instruction instead, per the ARM ARM.
4308 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
4309 Inst.getNumOperands() == 5) {
4311 TmpInst.setOpcode(ARM::STR_PRE_IMM);
4312 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
4313 TmpInst.addOperand(Inst.getOperand(4)); // Rt
4314 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
4315 TmpInst.addOperand(MCOperand::CreateImm(-4));
4316 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
4317 TmpInst.addOperand(Inst.getOperand(3));
4322 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
4323 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
4324 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
4325 // to encoding T1 if <Rd> is omitted."
4326 if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6)
4327 Inst.setOpcode(ARM::tADDi3);
4330 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
4331 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
4332 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
4333 // to encoding T1 if <Rd> is omitted."
4334 if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6)
4335 Inst.setOpcode(ARM::tSUBi3);
4338 // A Thumb conditional branch outside of an IT block is a tBcc.
4339 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock())
4340 Inst.setOpcode(ARM::tBcc);
4343 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
4344 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock())
4345 Inst.setOpcode(ARM::t2Bcc);
4348 // If the conditional is AL or we're in an IT block, we really want t2B.
4349 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock())
4350 Inst.setOpcode(ARM::t2B);
4353 // If the conditional is AL, we really want tB.
4354 if (Inst.getOperand(1).getImm() == ARMCC::AL)
4355 Inst.setOpcode(ARM::tB);
4358 // If the register list contains any high registers, or if the writeback
4359 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
4360 // instead if we're in Thumb2. Otherwise, this should have generated
4361 // an error in validateInstruction().
4362 unsigned Rn = Inst.getOperand(0).getReg();
4363 bool hasWritebackToken =
4364 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
4365 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
4366 bool listContainsBase;
4367 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
4368 (!listContainsBase && !hasWritebackToken) ||
4369 (listContainsBase && hasWritebackToken)) {
4370 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
4371 assert (isThumbTwo());
4372 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
4373 // If we're switching to the updating version, we need to insert
4374 // the writeback tied operand.
4375 if (hasWritebackToken)
4376 Inst.insert(Inst.begin(),
4377 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
4381 case ARM::tSTMIA_UPD: {
4382 // If the register list contains any high registers, we need to use
4383 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
4384 // should have generated an error in validateInstruction().
4385 unsigned Rn = Inst.getOperand(0).getReg();
4386 bool listContainsBase;
4387 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
4388 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
4389 assert (isThumbTwo());
4390 Inst.setOpcode(ARM::t2STMIA_UPD);
4395 // If we can use the 16-bit encoding and the user didn't explicitly
4396 // request the 32-bit variant, transform it here.
4397 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
4398 Inst.getOperand(1).getImm() <= 255 &&
4399 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
4400 Inst.getOperand(4).getReg() == ARM::CPSR) ||
4401 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
4402 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
4403 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
4404 // The operands aren't in the same order for tMOVi8...
4406 TmpInst.setOpcode(ARM::tMOVi8);
4407 TmpInst.addOperand(Inst.getOperand(0));
4408 TmpInst.addOperand(Inst.getOperand(4));
4409 TmpInst.addOperand(Inst.getOperand(1));
4410 TmpInst.addOperand(Inst.getOperand(2));
4411 TmpInst.addOperand(Inst.getOperand(3));
4417 // If we can use the 16-bit encoding and the user didn't explicitly
4418 // request the 32-bit variant, transform it here.
4419 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
4420 isARMLowRegister(Inst.getOperand(1).getReg()) &&
4421 Inst.getOperand(2).getImm() == ARMCC::AL &&
4422 Inst.getOperand(4).getReg() == ARM::CPSR &&
4423 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
4424 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
4425 // The operands aren't the same for tMOV[S]r... (no cc_out)
4427 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
4428 TmpInst.addOperand(Inst.getOperand(0));
4429 TmpInst.addOperand(Inst.getOperand(1));
4430 TmpInst.addOperand(Inst.getOperand(2));
4431 TmpInst.addOperand(Inst.getOperand(3));
4440 // If we can use the 16-bit encoding and the user didn't explicitly
4441 // request the 32-bit variant, transform it here.
4442 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
4443 isARMLowRegister(Inst.getOperand(1).getReg()) &&
4444 Inst.getOperand(2).getImm() == 0 &&
4445 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
4446 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
4448 switch (Inst.getOpcode()) {
4449 default: llvm_unreachable("Illegal opcode!");
4450 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
4451 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
4452 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
4453 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
4455 // The operands aren't the same for thumb1 (no rotate operand).
4457 TmpInst.setOpcode(NewOpc);
4458 TmpInst.addOperand(Inst.getOperand(0));
4459 TmpInst.addOperand(Inst.getOperand(1));
4460 TmpInst.addOperand(Inst.getOperand(3));
4461 TmpInst.addOperand(Inst.getOperand(4));
4467 // The mask bits for all but the first condition are represented as
4468 // the low bit of the condition code value implies 't'. We currently
4469 // always have 1 implies 't', so XOR toggle the bits if the low bit
4470 // of the condition code is zero. The encoding also expects the low
4471 // bit of the condition to be encoded as bit 4 of the mask operand,
4472 // so mask that in if needed
4473 MCOperand &MO = Inst.getOperand(1);
4474 unsigned Mask = MO.getImm();
4475 unsigned OrigMask = Mask;
4476 unsigned TZ = CountTrailingZeros_32(Mask);
4477 if ((Inst.getOperand(0).getImm() & 1) == 0) {
4478 assert(Mask && TZ <= 3 && "illegal IT mask value!");
4479 for (unsigned i = 3; i != TZ; --i)
4485 // Set up the IT block state according to the IT instruction we just
4487 assert(!inITBlock() && "nested IT blocks?!");
4488 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
4489 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
4490 ITState.CurPosition = 0;
4491 ITState.FirstCond = true;
4497 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
4498 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
4499 // suffix depending on whether they're in an IT block or not.
4500 unsigned Opc = Inst.getOpcode();
4501 MCInstrDesc &MCID = getInstDesc(Opc);
4502 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
4503 assert(MCID.hasOptionalDef() &&
4504 "optionally flag setting instruction missing optional def operand");
4505 assert(MCID.NumOperands == Inst.getNumOperands() &&
4506 "operand count mismatch!");
4507 // Find the optional-def operand (cc_out).
4510 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
4513 // If we're parsing Thumb1, reject it completely.
4514 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
4515 return Match_MnemonicFail;
4516 // If we're parsing Thumb2, which form is legal depends on whether we're
4518 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
4520 return Match_RequiresITBlock;
4521 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
4523 return Match_RequiresNotITBlock;
4525 // Some high-register supporting Thumb1 encodings only allow both registers
4526 // to be from r0-r7 when in Thumb2.
4527 else if (Opc == ARM::tADDhirr && isThumbOne() &&
4528 isARMLowRegister(Inst.getOperand(1).getReg()) &&
4529 isARMLowRegister(Inst.getOperand(2).getReg()))
4530 return Match_RequiresThumb2;
4531 // Others only require ARMv6 or later.
4532 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
4533 isARMLowRegister(Inst.getOperand(0).getReg()) &&
4534 isARMLowRegister(Inst.getOperand(1).getReg()))
4535 return Match_RequiresV6;
4536 return Match_Success;
4540 MatchAndEmitInstruction(SMLoc IDLoc,
4541 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4545 unsigned MatchResult;
4546 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
4547 switch (MatchResult) {
4550 // Context sensitive operand constraints aren't handled by the matcher,
4551 // so check them here.
4552 if (validateInstruction(Inst, Operands)) {
4553 // Still progress the IT block, otherwise one wrong condition causes
4554 // nasty cascading errors.
4555 forwardITPosition();
4559 // Some instructions need post-processing to, for example, tweak which
4560 // encoding is selected.
4561 processInstruction(Inst, Operands);
4563 // Only move forward at the very end so that everything in validate
4564 // and process gets a consistent answer about whether we're in an IT
4566 forwardITPosition();
4568 Out.EmitInstruction(Inst);
4570 case Match_MissingFeature:
4571 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
4573 case Match_InvalidOperand: {
4574 SMLoc ErrorLoc = IDLoc;
4575 if (ErrorInfo != ~0U) {
4576 if (ErrorInfo >= Operands.size())
4577 return Error(IDLoc, "too few operands for instruction");
4579 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
4580 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
4583 return Error(ErrorLoc, "invalid operand for instruction");
4585 case Match_MnemonicFail:
4586 return Error(IDLoc, "invalid instruction");
4587 case Match_ConversionFail:
4588 // The converter function will have already emited a diagnostic.
4590 case Match_RequiresNotITBlock:
4591 return Error(IDLoc, "flag setting instruction only valid outside IT block");
4592 case Match_RequiresITBlock:
4593 return Error(IDLoc, "instruction only valid inside IT block");
4594 case Match_RequiresV6:
4595 return Error(IDLoc, "instruction variant requires ARMv6 or later");
4596 case Match_RequiresThumb2:
4597 return Error(IDLoc, "instruction variant requires Thumb2");
4600 llvm_unreachable("Implement any new match types added!");
4604 /// parseDirective parses the arm specific directives
4605 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
4606 StringRef IDVal = DirectiveID.getIdentifier();
4607 if (IDVal == ".word")
4608 return parseDirectiveWord(4, DirectiveID.getLoc());
4609 else if (IDVal == ".thumb")
4610 return parseDirectiveThumb(DirectiveID.getLoc());
4611 else if (IDVal == ".thumb_func")
4612 return parseDirectiveThumbFunc(DirectiveID.getLoc());
4613 else if (IDVal == ".code")
4614 return parseDirectiveCode(DirectiveID.getLoc());
4615 else if (IDVal == ".syntax")
4616 return parseDirectiveSyntax(DirectiveID.getLoc());
4620 /// parseDirectiveWord
4621 /// ::= .word [ expression (, expression)* ]
4622 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
4623 if (getLexer().isNot(AsmToken::EndOfStatement)) {
4625 const MCExpr *Value;
4626 if (getParser().ParseExpression(Value))
4629 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
4631 if (getLexer().is(AsmToken::EndOfStatement))
4634 // FIXME: Improve diagnostic.
4635 if (getLexer().isNot(AsmToken::Comma))
4636 return Error(L, "unexpected token in directive");
4645 /// parseDirectiveThumb
4647 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
4648 if (getLexer().isNot(AsmToken::EndOfStatement))
4649 return Error(L, "unexpected token in directive");
4652 // TODO: set thumb mode
4653 // TODO: tell the MC streamer the mode
4654 // getParser().getStreamer().Emit???();
4658 /// parseDirectiveThumbFunc
4659 /// ::= .thumbfunc symbol_name
4660 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
4661 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
4662 bool isMachO = MAI.hasSubsectionsViaSymbols();
4665 // Darwin asm has function name after .thumb_func direction
4668 const AsmToken &Tok = Parser.getTok();
4669 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
4670 return Error(L, "unexpected token in .thumb_func directive");
4671 Name = Tok.getString();
4672 Parser.Lex(); // Consume the identifier token.
4675 if (getLexer().isNot(AsmToken::EndOfStatement))
4676 return Error(L, "unexpected token in directive");
4679 // FIXME: assuming function name will be the line following .thumb_func
4681 Name = Parser.getTok().getString();
4684 // Mark symbol as a thumb symbol.
4685 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
4686 getParser().getStreamer().EmitThumbFunc(Func);
4690 /// parseDirectiveSyntax
4691 /// ::= .syntax unified | divided
4692 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
4693 const AsmToken &Tok = Parser.getTok();
4694 if (Tok.isNot(AsmToken::Identifier))
4695 return Error(L, "unexpected token in .syntax directive");
4696 StringRef Mode = Tok.getString();
4697 if (Mode == "unified" || Mode == "UNIFIED")
4699 else if (Mode == "divided" || Mode == "DIVIDED")
4700 return Error(L, "'.syntax divided' arm asssembly not supported");
4702 return Error(L, "unrecognized syntax mode in .syntax directive");
4704 if (getLexer().isNot(AsmToken::EndOfStatement))
4705 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
4708 // TODO tell the MC streamer the mode
4709 // getParser().getStreamer().Emit???();
4713 /// parseDirectiveCode
4714 /// ::= .code 16 | 32
4715 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
4716 const AsmToken &Tok = Parser.getTok();
4717 if (Tok.isNot(AsmToken::Integer))
4718 return Error(L, "unexpected token in .code directive");
4719 int64_t Val = Parser.getTok().getIntVal();
4725 return Error(L, "invalid operand to .code directive");
4727 if (getLexer().isNot(AsmToken::EndOfStatement))
4728 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
4734 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
4738 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
4744 extern "C" void LLVMInitializeARMAsmLexer();
4746 /// Force static initialization.
4747 extern "C" void LLVMInitializeARMAsmParser() {
4748 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
4749 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
4750 LLVMInitializeARMAsmLexer();
4753 #define GET_REGISTER_MATCHER
4754 #define GET_MATCHER_IMPLEMENTATION
4755 #include "ARMGenAsmMatcher.inc"