1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMInstPrinter.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMMCInstLower.h"
23 #include "ARMTargetMachine.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Module.h"
26 #include "llvm/Assembly/Writer.h"
27 #include "llvm/CodeGen/AsmPrinter.h"
28 #include "llvm/CodeGen/DwarfWriter.h"
29 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
30 #include "llvm/CodeGen/MachineFunctionPass.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/MC/MCContext.h"
34 #include "llvm/MC/MCInst.h"
35 #include "llvm/MC/MCSectionMachO.h"
36 #include "llvm/MC/MCStreamer.h"
37 #include "llvm/MC/MCSymbol.h"
38 #include "llvm/Target/TargetData.h"
39 #include "llvm/Target/TargetLoweringObjectFile.h"
40 #include "llvm/Target/TargetMachine.h"
41 #include "llvm/Target/TargetOptions.h"
42 #include "llvm/Target/TargetRegistry.h"
43 #include "llvm/ADT/SmallPtrSet.h"
44 #include "llvm/ADT/SmallString.h"
45 #include "llvm/ADT/Statistic.h"
46 #include "llvm/ADT/StringSet.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/FormattedStream.h"
50 #include "llvm/Support/Mangler.h"
51 #include "llvm/Support/MathExtras.h"
55 STATISTIC(EmittedInsts, "Number of machine instrs printed");
58 EnableMCInst("enable-arm-mcinst-printer", cl::Hidden,
59 cl::desc("enable experimental asmprinter gunk in the arm backend"));
62 class ARMAsmPrinter : public AsmPrinter {
64 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
65 /// make the right decision when printing asm code for different targets.
66 const ARMSubtarget *Subtarget;
68 /// AFI - Keep a pointer to ARMFunctionInfo for the current
72 /// MCP - Keep a pointer to constantpool entries of the current
74 const MachineConstantPool *MCP;
77 explicit ARMAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM,
78 const MCAsmInfo *T, bool V)
79 : AsmPrinter(O, TM, T, V), AFI(NULL), MCP(NULL) {
80 Subtarget = &TM.getSubtarget<ARMSubtarget>();
83 virtual const char *getPassName() const {
84 return "ARM Assembly Printer";
87 void printMCInst(const MCInst *MI) {
88 ARMInstPrinter(O, *MAI).printInstruction(MI);
91 void printInstructionThroughMCStreamer(const MachineInstr *MI);
94 void printOperand(const MachineInstr *MI, int OpNum,
95 const char *Modifier = 0);
96 void printSOImmOperand(const MachineInstr *MI, int OpNum);
97 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum);
98 void printSORegOperand(const MachineInstr *MI, int OpNum);
99 void printAddrMode2Operand(const MachineInstr *MI, int OpNum);
100 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum);
101 void printAddrMode3Operand(const MachineInstr *MI, int OpNum);
102 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum);
103 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,
104 const char *Modifier = 0);
105 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,
106 const char *Modifier = 0);
107 void printAddrMode6Operand(const MachineInstr *MI, int OpNum);
108 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
109 const char *Modifier = 0);
110 void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum);
112 void printThumbITMask(const MachineInstr *MI, int OpNum);
113 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum);
114 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
116 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum);
117 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum);
118 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum);
119 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum);
121 void printT2SOOperand(const MachineInstr *MI, int OpNum);
122 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum);
123 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum);
124 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum);
125 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum);
126 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum);
128 void printPredicateOperand(const MachineInstr *MI, int OpNum);
129 void printSBitModifierOperand(const MachineInstr *MI, int OpNum);
130 void printPCLabel(const MachineInstr *MI, int OpNum);
131 void printRegisterList(const MachineInstr *MI, int OpNum);
132 void printCPInstOperand(const MachineInstr *MI, int OpNum,
133 const char *Modifier);
134 void printJTBlockOperand(const MachineInstr *MI, int OpNum);
135 void printJT2BlockOperand(const MachineInstr *MI, int OpNum);
136 void printTBAddrMode(const MachineInstr *MI, int OpNum);
137 void printNoHashImmediate(const MachineInstr *MI, int OpNum);
139 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
140 unsigned AsmVariant, const char *ExtraCode);
141 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
143 const char *ExtraCode);
145 void PrintGlobalVariable(const GlobalVariable* GVar);
146 void printInstruction(const MachineInstr *MI); // autogenerated.
147 static const char *getRegisterName(unsigned RegNo);
149 void printMachineInstruction(const MachineInstr *MI);
150 bool runOnMachineFunction(MachineFunction &F);
151 void EmitStartOfAsmFile(Module &M);
152 void EmitEndOfAsmFile(Module &M);
154 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
156 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
157 printDataDirective(MCPV->getType());
159 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
160 GlobalValue *GV = ACPV->getGV();
163 if (ACPV->isLSDA()) {
164 SmallString<16> LSDAName;
165 raw_svector_ostream(LSDAName) << MAI->getPrivateGlobalPrefix() <<
166 "_LSDA_" << getFunctionNumber();
167 Name = LSDAName.str();
169 bool isIndirect = Subtarget->isTargetDarwin() &&
170 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
172 Name = Mang->getMangledName(GV);
174 // FIXME: Remove this when Darwin transition to @GOT like syntax.
175 Name = Mang->getMangledName(GV, "$non_lazy_ptr", true);
176 MCSymbol *Sym = OutContext.GetOrCreateSymbol(Name.c_str());
178 MachineModuleInfoMachO &MMIMachO =
179 MMI->getObjFileInfo<MachineModuleInfoMachO>();
180 const MCSymbol *&StubSym =
181 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
182 MMIMachO.getGVStubEntry(Sym);
184 SmallString<128> NameStr;
185 Mang->getNameWithPrefix(NameStr, GV, false);
186 StubSym = OutContext.GetOrCreateSymbol(NameStr.str());
190 Name = Mang->makeNameProper(ACPV->getSymbol());
193 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
194 if (ACPV->getPCAdjustment() != 0) {
195 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
196 << ACPV->getLabelId()
197 << "+" << (unsigned)ACPV->getPCAdjustment();
198 if (ACPV->mustAddCurrentAddress())
205 void getAnalysisUsage(AnalysisUsage &AU) const {
206 AsmPrinter::getAnalysisUsage(AU);
207 AU.setPreservesAll();
208 AU.addRequired<MachineModuleInfo>();
209 AU.addRequired<DwarfWriter>();
212 } // end of anonymous namespace
214 #include "ARMGenAsmWriter.inc"
216 /// runOnMachineFunction - This uses the printInstruction()
217 /// method to print assembly for each instruction.
219 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
222 AFI = MF.getInfo<ARMFunctionInfo>();
223 MCP = MF.getConstantPool();
225 SetupMachineFunction(MF);
228 // NOTE: we don't print out constant pools here, they are handled as
233 // Print out labels for the function.
234 const Function *F = MF.getFunction();
235 OutStreamer.SwitchSection(getObjFileLowering().SectionForGlobal(F, Mang, TM));
237 switch (F->getLinkage()) {
238 default: llvm_unreachable("Unknown linkage type!");
239 case Function::PrivateLinkage:
240 case Function::InternalLinkage:
242 case Function::ExternalLinkage:
243 O << "\t.globl\t" << CurrentFnName << "\n";
245 case Function::LinkerPrivateLinkage:
246 case Function::WeakAnyLinkage:
247 case Function::WeakODRLinkage:
248 case Function::LinkOnceAnyLinkage:
249 case Function::LinkOnceODRLinkage:
250 if (Subtarget->isTargetDarwin()) {
251 O << "\t.globl\t" << CurrentFnName << "\n";
252 O << "\t.weak_definition\t" << CurrentFnName << "\n";
254 O << MAI->getWeakRefDirective() << CurrentFnName << "\n";
259 printVisibility(CurrentFnName, F->getVisibility());
261 unsigned FnAlign = 1 << MF.getAlignment(); // MF alignment is log2.
262 if (AFI->isThumbFunction()) {
263 EmitAlignment(FnAlign, F, AFI->getAlign());
264 O << "\t.code\t16\n";
265 O << "\t.thumb_func";
266 if (Subtarget->isTargetDarwin())
267 O << "\t" << CurrentFnName;
270 EmitAlignment(FnAlign, F);
273 O << CurrentFnName << ":\n";
274 // Emit pre-function debug information.
275 DW->BeginFunction(&MF);
277 if (Subtarget->isTargetDarwin()) {
278 // If the function is empty, then we need to emit *something*. Otherwise,
279 // the function's label might be associated with something that it wasn't
280 // meant to be associated with. We emit a noop in this situation.
281 MachineFunction::iterator I = MF.begin();
283 if (++I == MF.end() && MF.front().empty())
287 // Print out code for the function.
288 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
290 // Print a label for the basic block.
292 EmitBasicBlockStart(I);
294 // Print the assembly for the instruction.
295 for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
297 printMachineInstruction(II);
300 if (MAI->hasDotTypeDotSizeDirective())
301 O << "\t.size " << CurrentFnName << ", .-" << CurrentFnName << "\n";
303 // Emit post-function debug information.
304 DW->EndFunction(&MF);
309 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
310 const char *Modifier) {
311 const MachineOperand &MO = MI->getOperand(OpNum);
312 switch (MO.getType()) {
313 case MachineOperand::MO_Register: {
314 unsigned Reg = MO.getReg();
315 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
316 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
317 unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
318 unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
320 << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
322 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
323 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
324 unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1,
325 &ARM::DPR_VFP2RegClass);
326 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
328 O << getRegisterName(Reg);
331 llvm_unreachable("not implemented");
334 case MachineOperand::MO_Immediate: {
335 int64_t Imm = MO.getImm();
338 if (strcmp(Modifier, "lo16") == 0)
340 else if (strcmp(Modifier, "hi16") == 0)
346 case MachineOperand::MO_MachineBasicBlock:
347 GetMBBSymbol(MO.getMBB()->getNumber())->print(O, MAI);
349 case MachineOperand::MO_GlobalAddress: {
350 bool isCallOp = Modifier && !strcmp(Modifier, "call");
351 GlobalValue *GV = MO.getGlobal();
352 O << Mang->getMangledName(GV);
354 printOffset(MO.getOffset());
356 if (isCallOp && Subtarget->isTargetELF() &&
357 TM.getRelocationModel() == Reloc::PIC_)
361 case MachineOperand::MO_ExternalSymbol: {
362 bool isCallOp = Modifier && !strcmp(Modifier, "call");
363 std::string Name = Mang->makeNameProper(MO.getSymbolName());
366 if (isCallOp && Subtarget->isTargetELF() &&
367 TM.getRelocationModel() == Reloc::PIC_)
371 case MachineOperand::MO_ConstantPoolIndex:
372 O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
373 << '_' << MO.getIndex();
375 case MachineOperand::MO_JumpTableIndex:
376 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
377 << '_' << MO.getIndex();
380 O << "<unknown operand type>"; abort (); break;
384 static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm,
385 const MCAsmInfo *MAI) {
386 // Break it up into two parts that make up a shifter immediate.
387 V = ARM_AM::getSOImmVal(V);
388 assert(V != -1 && "Not a valid so_imm value!");
390 unsigned Imm = ARM_AM::getSOImmValImm(V);
391 unsigned Rot = ARM_AM::getSOImmValRot(V);
393 // Print low-level immediate formation info, per
394 // A5.1.3: "Data-processing operands - Immediate".
396 O << "#" << Imm << ", " << Rot;
397 // Pretty printed version.
399 O << ' ' << MAI->getCommentString()
400 << ' ' << (int)ARM_AM::rotr32(Imm, Rot);
406 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
407 /// immediate in bits 0-7.
408 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
409 const MachineOperand &MO = MI->getOperand(OpNum);
410 assert(MO.isImm() && "Not a valid so_imm value!");
411 printSOImm(O, MO.getImm(), VerboseAsm, MAI);
414 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
415 /// followed by an 'orr' to materialize.
416 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
417 const MachineOperand &MO = MI->getOperand(OpNum);
418 assert(MO.isImm() && "Not a valid so_imm value!");
419 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
420 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
421 printSOImm(O, V1, VerboseAsm, MAI);
423 printPredicateOperand(MI, 2);
429 printSOImm(O, V2, VerboseAsm, MAI);
432 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
433 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
435 // REG REG 0,SH_OPC - e.g. R5, ROR R3
436 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
437 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
438 const MachineOperand &MO1 = MI->getOperand(Op);
439 const MachineOperand &MO2 = MI->getOperand(Op+1);
440 const MachineOperand &MO3 = MI->getOperand(Op+2);
442 O << getRegisterName(MO1.getReg());
444 // Print the shift opc.
446 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
450 O << getRegisterName(MO2.getReg());
451 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
453 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
457 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
458 const MachineOperand &MO1 = MI->getOperand(Op);
459 const MachineOperand &MO2 = MI->getOperand(Op+1);
460 const MachineOperand &MO3 = MI->getOperand(Op+2);
462 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
463 printOperand(MI, Op);
467 O << "[" << getRegisterName(MO1.getReg());
470 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
472 << (char)ARM_AM::getAM2Op(MO3.getImm())
473 << ARM_AM::getAM2Offset(MO3.getImm());
479 << (char)ARM_AM::getAM2Op(MO3.getImm())
480 << getRegisterName(MO2.getReg());
482 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
484 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
489 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
490 const MachineOperand &MO1 = MI->getOperand(Op);
491 const MachineOperand &MO2 = MI->getOperand(Op+1);
494 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
495 assert(ImmOffs && "Malformed indexed load / store!");
497 << (char)ARM_AM::getAM2Op(MO2.getImm())
502 O << (char)ARM_AM::getAM2Op(MO2.getImm())
503 << getRegisterName(MO1.getReg());
505 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
507 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
511 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) {
512 const MachineOperand &MO1 = MI->getOperand(Op);
513 const MachineOperand &MO2 = MI->getOperand(Op+1);
514 const MachineOperand &MO3 = MI->getOperand(Op+2);
516 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
517 O << "[" << getRegisterName(MO1.getReg());
521 << (char)ARM_AM::getAM3Op(MO3.getImm())
522 << getRegisterName(MO2.getReg())
527 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
529 << (char)ARM_AM::getAM3Op(MO3.getImm())
534 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
535 const MachineOperand &MO1 = MI->getOperand(Op);
536 const MachineOperand &MO2 = MI->getOperand(Op+1);
539 O << (char)ARM_AM::getAM3Op(MO2.getImm())
540 << getRegisterName(MO1.getReg());
544 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
545 assert(ImmOffs && "Malformed indexed load / store!");
547 << (char)ARM_AM::getAM3Op(MO2.getImm())
551 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
552 const char *Modifier) {
553 const MachineOperand &MO1 = MI->getOperand(Op);
554 const MachineOperand &MO2 = MI->getOperand(Op+1);
555 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
556 if (Modifier && strcmp(Modifier, "submode") == 0) {
557 if (MO1.getReg() == ARM::SP) {
559 bool isLDM = (MI->getOpcode() == ARM::LDM ||
560 MI->getOpcode() == ARM::LDM_RET ||
561 MI->getOpcode() == ARM::t2LDM ||
562 MI->getOpcode() == ARM::t2LDM_RET);
563 O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
565 O << ARM_AM::getAMSubModeStr(Mode);
566 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
567 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
568 if (Mode == ARM_AM::ia)
571 printOperand(MI, Op);
572 if (ARM_AM::getAM4WBFlag(MO2.getImm()))
577 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
578 const char *Modifier) {
579 const MachineOperand &MO1 = MI->getOperand(Op);
580 const MachineOperand &MO2 = MI->getOperand(Op+1);
582 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
583 printOperand(MI, Op);
587 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
589 if (Modifier && strcmp(Modifier, "submode") == 0) {
590 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
591 if (MO1.getReg() == ARM::SP) {
592 bool isFLDM = (MI->getOpcode() == ARM::FLDMD ||
593 MI->getOpcode() == ARM::FLDMS);
594 O << ARM_AM::getAMSubModeAltStr(Mode, isFLDM);
596 O << ARM_AM::getAMSubModeStr(Mode);
598 } else if (Modifier && strcmp(Modifier, "base") == 0) {
599 // Used for FSTM{D|S} and LSTM{D|S} operations.
600 O << getRegisterName(MO1.getReg());
601 if (ARM_AM::getAM5WBFlag(MO2.getImm()))
606 O << "[" << getRegisterName(MO1.getReg());
608 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
610 << (char)ARM_AM::getAM5Op(MO2.getImm())
616 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) {
617 const MachineOperand &MO1 = MI->getOperand(Op);
618 const MachineOperand &MO2 = MI->getOperand(Op+1);
619 const MachineOperand &MO3 = MI->getOperand(Op+2);
621 // FIXME: No support yet for specifying alignment.
622 O << "[" << getRegisterName(MO1.getReg()) << "]";
624 if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
625 if (MO2.getReg() == 0)
628 O << ", " << getRegisterName(MO2.getReg());
632 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
633 const char *Modifier) {
634 if (Modifier && strcmp(Modifier, "label") == 0) {
635 printPCLabel(MI, Op+1);
639 const MachineOperand &MO1 = MI->getOperand(Op);
640 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
641 O << "[pc, +" << getRegisterName(MO1.getReg()) << "]";
645 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) {
646 const MachineOperand &MO = MI->getOperand(Op);
647 uint32_t v = ~MO.getImm();
648 int32_t lsb = CountTrailingZeros_32(v);
649 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
650 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
651 O << "#" << lsb << ", #" << width;
654 //===--------------------------------------------------------------------===//
657 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) {
658 // (3 - the number of trailing zeros) is the number of then / else.
659 unsigned Mask = MI->getOperand(Op).getImm();
660 unsigned NumTZ = CountTrailingZeros_32(Mask);
661 assert(NumTZ <= 3 && "Invalid IT mask!");
662 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
663 bool T = (Mask & (1 << Pos)) == 0;
672 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
673 const MachineOperand &MO1 = MI->getOperand(Op);
674 const MachineOperand &MO2 = MI->getOperand(Op+1);
675 O << "[" << getRegisterName(MO1.getReg());
676 O << ", " << getRegisterName(MO2.getReg()) << "]";
680 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
682 const MachineOperand &MO1 = MI->getOperand(Op);
683 const MachineOperand &MO2 = MI->getOperand(Op+1);
684 const MachineOperand &MO3 = MI->getOperand(Op+2);
686 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
687 printOperand(MI, Op);
691 O << "[" << getRegisterName(MO1.getReg());
693 O << ", " << getRegisterName(MO3.getReg());
694 else if (unsigned ImmOffs = MO2.getImm()) {
695 O << ", #" << ImmOffs;
703 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) {
704 printThumbAddrModeRI5Operand(MI, Op, 1);
707 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) {
708 printThumbAddrModeRI5Operand(MI, Op, 2);
711 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
712 printThumbAddrModeRI5Operand(MI, Op, 4);
715 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
716 const MachineOperand &MO1 = MI->getOperand(Op);
717 const MachineOperand &MO2 = MI->getOperand(Op+1);
718 O << "[" << getRegisterName(MO1.getReg());
719 if (unsigned ImmOffs = MO2.getImm())
720 O << ", #" << ImmOffs << " * 4";
724 //===--------------------------------------------------------------------===//
726 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
727 // register with shift forms.
729 // REG IMM, SH_OPC - e.g. R5, LSL #3
730 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) {
731 const MachineOperand &MO1 = MI->getOperand(OpNum);
732 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
734 unsigned Reg = MO1.getReg();
735 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
736 O << getRegisterName(Reg);
738 // Print the shift opc.
740 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
743 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
744 O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
747 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
749 const MachineOperand &MO1 = MI->getOperand(OpNum);
750 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
752 O << "[" << getRegisterName(MO1.getReg());
754 unsigned OffImm = MO2.getImm();
755 if (OffImm) // Don't print +0.
756 O << ", #+" << OffImm;
760 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
762 const MachineOperand &MO1 = MI->getOperand(OpNum);
763 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
765 O << "[" << getRegisterName(MO1.getReg());
767 int32_t OffImm = (int32_t)MO2.getImm();
770 O << ", #-" << -OffImm;
772 O << ", #+" << OffImm;
776 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
778 const MachineOperand &MO1 = MI->getOperand(OpNum);
779 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
781 O << "[" << getRegisterName(MO1.getReg());
783 int32_t OffImm = (int32_t)MO2.getImm() / 4;
786 O << ", #-" << -OffImm << " * 4";
788 O << ", #+" << OffImm << " * 4";
792 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
794 const MachineOperand &MO1 = MI->getOperand(OpNum);
795 int32_t OffImm = (int32_t)MO1.getImm();
798 O << "#-" << -OffImm;
803 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
805 const MachineOperand &MO1 = MI->getOperand(OpNum);
806 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
807 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
809 O << "[" << getRegisterName(MO1.getReg());
811 assert(MO2.getReg() && "Invalid so_reg load / store address!");
812 O << ", " << getRegisterName(MO2.getReg());
814 unsigned ShAmt = MO3.getImm();
816 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
817 O << ", lsl #" << ShAmt;
823 //===--------------------------------------------------------------------===//
825 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum) {
826 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
828 O << ARMCondCodeToString(CC);
831 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){
832 unsigned Reg = MI->getOperand(OpNum).getReg();
834 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
839 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) {
840 int Id = (int)MI->getOperand(OpNum).getImm();
841 O << MAI->getPrivateGlobalPrefix() << "PC" << Id;
844 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) {
846 // Always skip the first operand, it's the optional (and implicit writeback).
847 for (unsigned i = OpNum+1, e = MI->getNumOperands(); i != e; ++i) {
848 if (MI->getOperand(i).isImplicit())
850 if ((int)i != OpNum+1) O << ", ";
856 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
857 const char *Modifier) {
858 assert(Modifier && "This operand only works with a modifier!");
859 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
861 if (!strcmp(Modifier, "label")) {
862 unsigned ID = MI->getOperand(OpNum).getImm();
863 O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
864 << '_' << ID << ":\n";
866 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
867 unsigned CPI = MI->getOperand(OpNum).getIndex();
869 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
871 if (MCPE.isMachineConstantPoolEntry()) {
872 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
874 EmitGlobalConstant(MCPE.Val.ConstVal);
879 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) {
880 assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
882 const MachineOperand &MO1 = MI->getOperand(OpNum);
883 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
884 unsigned JTI = MO1.getIndex();
885 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
886 << '_' << JTI << '_' << MO2.getImm() << ":\n";
888 const char *JTEntryDirective = MAI->getData32bitsDirective();
890 const MachineFunction *MF = MI->getParent()->getParent();
891 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
892 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
893 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
894 bool UseSet= MAI->getSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
895 SmallPtrSet<MachineBasicBlock*, 8> JTSets;
896 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
897 MachineBasicBlock *MBB = JTBBs[i];
898 bool isNew = JTSets.insert(MBB);
901 printPICJumpTableSetLabel(JTI, MO2.getImm(), MBB);
903 O << JTEntryDirective << ' ';
905 O << MAI->getPrivateGlobalPrefix() << getFunctionNumber()
906 << '_' << JTI << '_' << MO2.getImm()
907 << "_set_" << MBB->getNumber();
908 else if (TM.getRelocationModel() == Reloc::PIC_) {
909 GetMBBSymbol(MBB->getNumber())->print(O, MAI);
910 O << '-' << MAI->getPrivateGlobalPrefix() << "JTI"
911 << getFunctionNumber() << '_' << JTI << '_' << MO2.getImm();
913 GetMBBSymbol(MBB->getNumber())->print(O, MAI);
920 void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum) {
921 const MachineOperand &MO1 = MI->getOperand(OpNum);
922 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
923 unsigned JTI = MO1.getIndex();
924 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
925 << '_' << JTI << '_' << MO2.getImm() << ":\n";
927 const MachineFunction *MF = MI->getParent()->getParent();
928 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
929 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
930 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
931 bool ByteOffset = false, HalfWordOffset = false;
932 if (MI->getOpcode() == ARM::t2TBB)
934 else if (MI->getOpcode() == ARM::t2TBH)
935 HalfWordOffset = true;
937 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
938 MachineBasicBlock *MBB = JTBBs[i];
940 O << MAI->getData8bitsDirective();
941 else if (HalfWordOffset)
942 O << MAI->getData16bitsDirective();
943 if (ByteOffset || HalfWordOffset) {
945 GetMBBSymbol(MBB->getNumber())->print(O, MAI);
946 O << "-" << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
947 << '_' << JTI << '_' << MO2.getImm() << ")/2";
950 GetMBBSymbol(MBB->getNumber())->print(O, MAI);
956 // Make sure the instruction that follows TBB is 2-byte aligned.
957 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
958 if (ByteOffset && (JTBBs.size() & 1)) {
964 void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum) {
965 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
966 if (MI->getOpcode() == ARM::t2TBH)
971 void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum) {
972 O << MI->getOperand(OpNum).getImm();
975 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
976 unsigned AsmVariant, const char *ExtraCode){
977 // Does this asm operand have a single letter operand modifier?
978 if (ExtraCode && ExtraCode[0]) {
979 if (ExtraCode[1] != 0) return true; // Unknown modifier.
981 switch (ExtraCode[0]) {
982 default: return true; // Unknown modifier.
983 case 'a': // Print as a memory address.
984 if (MI->getOperand(OpNum).isReg()) {
985 O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
989 case 'c': // Don't print "#" before an immediate operand.
990 if (!MI->getOperand(OpNum).isImm())
992 printNoHashImmediate(MI, OpNum);
994 case 'P': // Print a VFP double precision register.
995 printOperand(MI, OpNum);
998 if (TM.getTargetData()->isLittleEndian())
1002 if (TM.getTargetData()->isBigEndian())
1005 case 'H': // Write second word of DI / DF reference.
1006 // Verify that this operand has two consecutive registers.
1007 if (!MI->getOperand(OpNum).isReg() ||
1008 OpNum+1 == MI->getNumOperands() ||
1009 !MI->getOperand(OpNum+1).isReg())
1011 ++OpNum; // Return the high-part.
1015 printOperand(MI, OpNum);
1019 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1020 unsigned OpNum, unsigned AsmVariant,
1021 const char *ExtraCode) {
1022 if (ExtraCode && ExtraCode[0])
1023 return true; // Unknown modifier.
1025 const MachineOperand &MO = MI->getOperand(OpNum);
1026 assert(MO.isReg() && "unexpected inline asm memory operand");
1027 O << "[" << getRegisterName(MO.getReg()) << "]";
1031 void ARMAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
1034 int Opc = MI->getOpcode();
1035 if (Opc == ARM::CONSTPOOL_ENTRY)
1038 // Call the autogenerated instruction printer routines.
1039 processDebugLoc(MI, true);
1042 printInstructionThroughMCStreamer(MI);
1044 printInstruction(MI);
1047 if (VerboseAsm && !MI->getDebugLoc().isUnknown())
1050 processDebugLoc(MI, false);
1053 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
1054 if (Subtarget->isTargetDarwin()) {
1055 Reloc::Model RelocM = TM.getRelocationModel();
1056 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
1057 // Declare all the text sections up front (before the DWARF sections
1058 // emitted by AsmPrinter::doInitialization) so the assembler will keep
1059 // them together at the beginning of the object file. This helps
1060 // avoid out-of-range branches that are due a fundamental limitation of
1061 // the way symbol offsets are encoded with the current Darwin ARM
1063 TargetLoweringObjectFileMachO &TLOFMacho =
1064 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1065 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
1066 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
1067 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
1068 if (RelocM == Reloc::DynamicNoPIC) {
1069 const MCSection *sect =
1070 TLOFMacho.getMachOSection("__TEXT", "__symbol_stub4",
1071 MCSectionMachO::S_SYMBOL_STUBS,
1072 12, SectionKind::getText());
1073 OutStreamer.SwitchSection(sect);
1075 const MCSection *sect =
1076 TLOFMacho.getMachOSection("__TEXT", "__picsymbolstub4",
1077 MCSectionMachO::S_SYMBOL_STUBS,
1078 16, SectionKind::getText());
1079 OutStreamer.SwitchSection(sect);
1084 // Use unified assembler syntax mode for Thumb.
1085 if (Subtarget->isThumb())
1086 O << "\t.syntax unified\n";
1088 // Emit ARM Build Attributes
1089 if (Subtarget->isTargetELF()) {
1091 std::string CPUString = Subtarget->getCPUString();
1092 if (CPUString != "generic")
1093 O << "\t.cpu " << CPUString << '\n';
1095 // FIXME: Emit FPU type
1096 if (Subtarget->hasVFP2())
1097 O << "\t.eabi_attribute " << ARMBuildAttrs::VFP_arch << ", 2\n";
1099 // Signal various FP modes.
1101 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_denormal << ", 1\n"
1102 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_exceptions << ", 1\n";
1104 if (FiniteOnlyFPMath())
1105 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 1\n";
1107 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 3\n";
1109 // 8-bytes alignment stuff.
1110 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_needed << ", 1\n"
1111 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_preserved << ", 1\n";
1113 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
1114 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard)
1115 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_HardFP_use << ", 3\n"
1116 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_VFP_args << ", 1\n";
1118 // FIXME: Should we signal R9 usage?
1122 void ARMAsmPrinter::PrintGlobalVariable(const GlobalVariable* GVar) {
1123 const TargetData *TD = TM.getTargetData();
1125 if (!GVar->hasInitializer()) // External global require no code
1128 // Check to see if this is a special global used by LLVM, if so, emit it.
1130 if (EmitSpecialLLVMGlobal(GVar)) {
1131 if (Subtarget->isTargetDarwin() &&
1132 TM.getRelocationModel() == Reloc::Static) {
1133 if (GVar->getName() == "llvm.global_ctors")
1134 O << ".reference .constructors_used\n";
1135 else if (GVar->getName() == "llvm.global_dtors")
1136 O << ".reference .destructors_used\n";
1141 std::string name = Mang->getMangledName(GVar);
1142 Constant *C = GVar->getInitializer();
1143 const Type *Type = C->getType();
1144 unsigned Size = TD->getTypeAllocSize(Type);
1145 unsigned Align = TD->getPreferredAlignmentLog(GVar);
1146 bool isDarwin = Subtarget->isTargetDarwin();
1148 printVisibility(name, GVar->getVisibility());
1150 if (Subtarget->isTargetELF())
1151 O << "\t.type " << name << ",%object\n";
1153 const MCSection *TheSection =
1154 getObjFileLowering().SectionForGlobal(GVar, Mang, TM);
1155 OutStreamer.SwitchSection(TheSection);
1157 // FIXME: get this stuff from section kind flags.
1158 if (C->isNullValue() && !GVar->hasSection() && !GVar->isThreadLocal() &&
1159 // Don't put things that should go in the cstring section into "comm".
1160 !TheSection->getKind().isMergeableCString()) {
1161 if (GVar->hasExternalLinkage()) {
1162 if (const char *Directive = MAI->getZeroFillDirective()) {
1163 O << "\t.globl\t" << name << "\n";
1164 O << Directive << "__DATA, __common, " << name << ", "
1165 << Size << ", " << Align << "\n";
1170 if (GVar->hasLocalLinkage() || GVar->isWeakForLinker()) {
1171 if (Size == 0) Size = 1; // .comm Foo, 0 is undefined, avoid it.
1174 if (GVar->hasLocalLinkage()) {
1175 O << MAI->getLCOMMDirective() << name << "," << Size
1177 } else if (GVar->hasCommonLinkage()) {
1178 O << MAI->getCOMMDirective() << name << "," << Size
1181 OutStreamer.SwitchSection(TheSection);
1182 O << "\t.globl " << name << '\n'
1183 << MAI->getWeakDefDirective() << name << '\n';
1184 EmitAlignment(Align, GVar);
1187 O << "\t\t\t\t" << MAI->getCommentString() << ' ';
1188 WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
1191 EmitGlobalConstant(C);
1194 } else if (MAI->getLCOMMDirective() != NULL) {
1195 if (GVar->hasLocalLinkage()) {
1196 O << MAI->getLCOMMDirective() << name << "," << Size;
1198 O << MAI->getCOMMDirective() << name << "," << Size;
1199 if (MAI->getCOMMDirectiveTakesAlignment())
1200 O << ',' << (MAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1203 if (GVar->hasLocalLinkage())
1204 O << "\t.local\t" << name << "\n";
1205 O << MAI->getCOMMDirective() << name << "," << Size;
1206 if (MAI->getCOMMDirectiveTakesAlignment())
1207 O << "," << (MAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1210 O << "\t\t" << MAI->getCommentString() << " ";
1211 WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
1218 switch (GVar->getLinkage()) {
1219 case GlobalValue::CommonLinkage:
1220 case GlobalValue::LinkOnceAnyLinkage:
1221 case GlobalValue::LinkOnceODRLinkage:
1222 case GlobalValue::WeakAnyLinkage:
1223 case GlobalValue::WeakODRLinkage:
1224 case GlobalValue::LinkerPrivateLinkage:
1226 O << "\t.globl " << name << "\n"
1227 << "\t.weak_definition " << name << "\n";
1229 O << "\t.weak " << name << "\n";
1232 case GlobalValue::AppendingLinkage:
1233 // FIXME: appending linkage variables should go into a section of
1234 // their name or something. For now, just emit them as external.
1235 case GlobalValue::ExternalLinkage:
1236 O << "\t.globl " << name << "\n";
1238 case GlobalValue::PrivateLinkage:
1239 case GlobalValue::InternalLinkage:
1242 llvm_unreachable("Unknown linkage type!");
1245 EmitAlignment(Align, GVar);
1248 O << "\t\t\t\t" << MAI->getCommentString() << " ";
1249 WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
1252 if (MAI->hasDotTypeDotSizeDirective())
1253 O << "\t.size " << name << ", " << Size << "\n";
1255 EmitGlobalConstant(C);
1260 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
1261 if (Subtarget->isTargetDarwin()) {
1262 // All darwin targets use mach-o.
1263 TargetLoweringObjectFileMachO &TLOFMacho =
1264 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1265 MachineModuleInfoMachO &MMIMacho =
1266 MMI->getObjFileInfo<MachineModuleInfoMachO>();
1270 // Output non-lazy-pointers for external and common global variables.
1271 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
1273 if (!Stubs.empty()) {
1274 // Switch with ".non_lazy_symbol_pointer" directive.
1275 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
1277 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1278 Stubs[i].first->print(O, MAI);
1279 O << ":\n\t.indirect_symbol ";
1280 Stubs[i].second->print(O, MAI);
1281 O << "\n\t.long\t0\n";
1285 Stubs = MMIMacho.GetHiddenGVStubList();
1286 if (!Stubs.empty()) {
1287 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
1289 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1290 Stubs[i].first->print(O, MAI);
1292 Stubs[i].second->print(O, MAI);
1297 // Funny Darwin hack: This flag tells the linker that no global symbols
1298 // contain code that falls through to other global symbols (e.g. the obvious
1299 // implementation of multiple entry points). If this doesn't occur, the
1300 // linker can safely perform dead code stripping. Since LLVM never
1301 // generates code that does this, it is always safe to set.
1302 OutStreamer.EmitAssemblerFlag(MCStreamer::SubsectionsViaSymbols);
1306 // Force static initialization.
1307 extern "C" void LLVMInitializeARMAsmPrinter() {
1308 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1309 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1313 //===----------------------------------------------------------------------===//
1315 void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
1316 ARMMCInstLower MCInstLowering(OutContext, Mang);
1317 switch (MI->getOpcode()) {
1318 case TargetInstrInfo::DBG_LABEL:
1319 case TargetInstrInfo::EH_LABEL:
1320 case TargetInstrInfo::GC_LABEL:
1323 case TargetInstrInfo::KILL:
1325 case TargetInstrInfo::INLINEASM:
1329 case TargetInstrInfo::IMPLICIT_DEF:
1330 printImplicitDef(MI);
1336 MCInstLowering.Lower(MI, TmpInst);
1338 printMCInst(&TmpInst);