1 // The LLVM Compiler Infrastructure
3 // This file is distributed under the University of Illinois Open Source
4 // License. See LICENSE.TXT for details.
6 //===----------------------------------------------------------------------===//
8 // This file contains a printer that converts from our internal representation
9 // of machine-dependent LLVM code to GAS-format ARM assembly language.
11 //===----------------------------------------------------------------------===//
13 #define DEBUG_TYPE "asm-printer"
15 #include "ARMBuildAttrs.h"
16 #include "ARMTargetMachine.h"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "llvm/Constants.h"
21 #include "llvm/Module.h"
22 #include "llvm/Assembly/Writer.h"
23 #include "llvm/CodeGen/AsmPrinter.h"
24 #include "llvm/CodeGen/DwarfWriter.h"
25 #include "llvm/CodeGen/MachineModuleInfo.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineJumpTableInfo.h"
28 #include "llvm/MC/MCSectionMachO.h"
29 #include "llvm/MC/MCStreamer.h"
30 #include "llvm/MC/MCAsmInfo.h"
31 #include "llvm/MC/MCSymbol.h"
32 #include "llvm/Target/TargetData.h"
33 #include "llvm/Target/TargetLoweringObjectFile.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/Target/TargetRegistry.h"
37 #include "llvm/ADT/SmallPtrSet.h"
38 #include "llvm/ADT/SmallString.h"
39 #include "llvm/ADT/Statistic.h"
40 #include "llvm/ADT/StringSet.h"
41 #include "llvm/Support/Compiler.h"
42 #include "llvm/Support/ErrorHandling.h"
43 #include "llvm/Support/Mangler.h"
44 #include "llvm/Support/MathExtras.h"
45 #include "llvm/Support/FormattedStream.h"
49 STATISTIC(EmittedInsts, "Number of machine instrs printed");
52 class VISIBILITY_HIDDEN ARMAsmPrinter : public AsmPrinter {
54 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
55 /// make the right decision when printing asm code for different targets.
56 const ARMSubtarget *Subtarget;
58 /// AFI - Keep a pointer to ARMFunctionInfo for the current
62 /// MCP - Keep a pointer to constantpool entries of the current
64 const MachineConstantPool *MCP;
66 /// We name each basic block in a Function with a unique number, so
67 /// that we can consistently refer to them later. This is cleared
68 /// at the beginning of each call to runOnMachineFunction().
70 typedef std::map<const Value *, unsigned> ValueMapTy;
71 ValueMapTy NumberForBB;
73 /// GVNonLazyPtrs - Keeps the set of GlobalValues that require
74 /// non-lazy-pointers for indirect access.
75 StringMap<std::string> GVNonLazyPtrs;
77 /// HiddenGVNonLazyPtrs - Keeps the set of GlobalValues with hidden
78 /// visibility that require non-lazy-pointers for indirect access.
79 StringMap<std::string> HiddenGVNonLazyPtrs;
81 /// True if asm printer is printing a series of CONSTPOOL_ENTRY.
84 explicit ARMAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM,
85 const MCAsmInfo *T, bool V)
86 : AsmPrinter(O, TM, T, V), AFI(NULL), MCP(NULL),
88 Subtarget = &TM.getSubtarget<ARMSubtarget>();
91 virtual const char *getPassName() const {
92 return "ARM Assembly Printer";
95 void printOperand(const MachineInstr *MI, int OpNum,
96 const char *Modifier = 0);
97 void printSOImmOperand(const MachineInstr *MI, int OpNum);
98 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum);
99 void printSORegOperand(const MachineInstr *MI, int OpNum);
100 void printAddrMode2Operand(const MachineInstr *MI, int OpNum);
101 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum);
102 void printAddrMode3Operand(const MachineInstr *MI, int OpNum);
103 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum);
104 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,
105 const char *Modifier = 0);
106 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,
107 const char *Modifier = 0);
108 void printAddrMode6Operand(const MachineInstr *MI, int OpNum);
109 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
110 const char *Modifier = 0);
111 void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum);
113 void printThumbITMask(const MachineInstr *MI, int OpNum);
114 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum);
115 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
117 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum);
118 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum);
119 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum);
120 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum);
122 void printT2SOOperand(const MachineInstr *MI, int OpNum);
123 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum);
124 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum);
125 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum);
126 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum);
127 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum);
129 void printPredicateOperand(const MachineInstr *MI, int OpNum);
130 void printSBitModifierOperand(const MachineInstr *MI, int OpNum);
131 void printPCLabel(const MachineInstr *MI, int OpNum);
132 void printRegisterList(const MachineInstr *MI, int OpNum);
133 void printCPInstOperand(const MachineInstr *MI, int OpNum,
134 const char *Modifier);
135 void printJTBlockOperand(const MachineInstr *MI, int OpNum);
136 void printJT2BlockOperand(const MachineInstr *MI, int OpNum);
137 void printTBAddrMode(const MachineInstr *MI, int OpNum);
138 void printNoHashImmediate(const MachineInstr *MI, int OpNum);
140 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
141 unsigned AsmVariant, const char *ExtraCode);
142 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
144 const char *ExtraCode);
146 void PrintGlobalVariable(const GlobalVariable* GVar);
147 void printInstruction(const MachineInstr *MI); // autogenerated.
148 static const char *getRegisterName(unsigned RegNo);
150 void printMachineInstruction(const MachineInstr *MI);
151 bool runOnMachineFunction(MachineFunction &F);
152 bool doFinalization(Module &M);
153 void EmitStartOfAsmFile(Module &M);
155 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
157 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
158 printDataDirective(MCPV->getType());
160 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
161 GlobalValue *GV = ACPV->getGV();
164 if (ACPV->isLSDA()) {
165 SmallString<16> LSDAName;
166 raw_svector_ostream(LSDAName) << MAI->getPrivateGlobalPrefix() <<
167 "_LSDA_" << getFunctionNumber();
168 Name = LSDAName.str();
170 bool isIndirect = Subtarget->isTargetDarwin() &&
171 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
173 Name = Mang->getMangledName(GV);
175 // FIXME: Remove this when Darwin transition to @GOT like syntax.
176 std::string SymName = Mang->getMangledName(GV);
177 Name = Mang->getMangledName(GV, "$non_lazy_ptr", true);
178 if (GV->hasHiddenVisibility())
179 HiddenGVNonLazyPtrs[SymName] = Name;
181 GVNonLazyPtrs[SymName] = Name;
184 Name = Mang->makeNameProper(ACPV->getSymbol());
187 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
188 if (ACPV->getPCAdjustment() != 0) {
189 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
190 << ACPV->getLabelId()
191 << "+" << (unsigned)ACPV->getPCAdjustment();
192 if (ACPV->mustAddCurrentAddress())
199 void getAnalysisUsage(AnalysisUsage &AU) const {
200 AsmPrinter::getAnalysisUsage(AU);
201 AU.setPreservesAll();
202 AU.addRequired<MachineModuleInfo>();
203 AU.addRequired<DwarfWriter>();
206 } // end of anonymous namespace
208 #include "ARMGenAsmWriter.inc"
210 /// runOnMachineFunction - This uses the printInstruction()
211 /// method to print assembly for each instruction.
213 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
216 AFI = MF.getInfo<ARMFunctionInfo>();
217 MCP = MF.getConstantPool();
219 SetupMachineFunction(MF);
222 // NOTE: we don't print out constant pools here, they are handled as
227 // Print out labels for the function.
228 const Function *F = MF.getFunction();
229 OutStreamer.SwitchSection(getObjFileLowering().SectionForGlobal(F, Mang, TM));
231 switch (F->getLinkage()) {
232 default: llvm_unreachable("Unknown linkage type!");
233 case Function::PrivateLinkage:
234 case Function::InternalLinkage:
236 case Function::ExternalLinkage:
237 O << "\t.globl\t" << CurrentFnName << "\n";
239 case Function::LinkerPrivateLinkage:
240 case Function::WeakAnyLinkage:
241 case Function::WeakODRLinkage:
242 case Function::LinkOnceAnyLinkage:
243 case Function::LinkOnceODRLinkage:
244 if (Subtarget->isTargetDarwin()) {
245 O << "\t.globl\t" << CurrentFnName << "\n";
246 O << "\t.weak_definition\t" << CurrentFnName << "\n";
248 O << MAI->getWeakRefDirective() << CurrentFnName << "\n";
253 printVisibility(CurrentFnName, F->getVisibility());
255 unsigned FnAlign = 1 << MF.getAlignment(); // MF alignment is log2.
256 if (AFI->isThumbFunction()) {
257 EmitAlignment(FnAlign, F, AFI->getAlign());
258 O << "\t.code\t16\n";
259 O << "\t.thumb_func";
260 if (Subtarget->isTargetDarwin())
261 O << "\t" << CurrentFnName;
265 EmitAlignment(FnAlign, F);
268 O << CurrentFnName << ":\n";
269 // Emit pre-function debug information.
270 DW->BeginFunction(&MF);
272 if (Subtarget->isTargetDarwin()) {
273 // If the function is empty, then we need to emit *something*. Otherwise,
274 // the function's label might be associated with something that it wasn't
275 // meant to be associated with. We emit a noop in this situation.
276 MachineFunction::iterator I = MF.begin();
278 if (++I == MF.end() && MF.front().empty())
282 // Print out code for the function.
283 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
285 // Print a label for the basic block.
286 if (I != MF.begin()) {
287 EmitBasicBlockStart(I);
289 for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
291 // Print the assembly for the instruction.
292 printMachineInstruction(II);
296 if (MAI->hasDotTypeDotSizeDirective())
297 O << "\t.size " << CurrentFnName << ", .-" << CurrentFnName << "\n";
299 // Emit post-function debug information.
300 DW->EndFunction(&MF);
305 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
306 const char *Modifier) {
307 const MachineOperand &MO = MI->getOperand(OpNum);
308 switch (MO.getType()) {
309 case MachineOperand::MO_Register: {
310 unsigned Reg = MO.getReg();
311 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
312 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
313 unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
314 unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
316 << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
318 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
319 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
320 unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1,
321 &ARM::DPR_VFP2RegClass);
322 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
324 O << getRegisterName(Reg);
327 llvm_unreachable("not implemented");
330 case MachineOperand::MO_Immediate: {
331 int64_t Imm = MO.getImm();
334 if (strcmp(Modifier, "lo16") == 0)
336 else if (strcmp(Modifier, "hi16") == 0)
342 case MachineOperand::MO_MachineBasicBlock:
343 GetMBBSymbol(MO.getMBB()->getNumber())->print(O, MAI);
345 case MachineOperand::MO_GlobalAddress: {
346 bool isCallOp = Modifier && !strcmp(Modifier, "call");
347 GlobalValue *GV = MO.getGlobal();
348 O << Mang->getMangledName(GV);
350 printOffset(MO.getOffset());
352 if (isCallOp && Subtarget->isTargetELF() &&
353 TM.getRelocationModel() == Reloc::PIC_)
357 case MachineOperand::MO_ExternalSymbol: {
358 bool isCallOp = Modifier && !strcmp(Modifier, "call");
359 std::string Name = Mang->makeNameProper(MO.getSymbolName());
362 if (isCallOp && Subtarget->isTargetELF() &&
363 TM.getRelocationModel() == Reloc::PIC_)
367 case MachineOperand::MO_ConstantPoolIndex:
368 O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
369 << '_' << MO.getIndex();
371 case MachineOperand::MO_JumpTableIndex:
372 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
373 << '_' << MO.getIndex();
376 O << "<unknown operand type>"; abort (); break;
380 static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm,
381 const MCAsmInfo *MAI) {
382 // Break it up into two parts that make up a shifter immediate.
383 V = ARM_AM::getSOImmVal(V);
384 assert(V != -1 && "Not a valid so_imm value!");
386 unsigned Imm = ARM_AM::getSOImmValImm(V);
387 unsigned Rot = ARM_AM::getSOImmValRot(V);
389 // Print low-level immediate formation info, per
390 // A5.1.3: "Data-processing operands - Immediate".
392 O << "#" << Imm << ", " << Rot;
393 // Pretty printed version.
395 O << ' ' << MAI->getCommentString()
396 << ' ' << (int)ARM_AM::rotr32(Imm, Rot);
402 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
403 /// immediate in bits 0-7.
404 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
405 const MachineOperand &MO = MI->getOperand(OpNum);
406 assert(MO.isImm() && "Not a valid so_imm value!");
407 printSOImm(O, MO.getImm(), VerboseAsm, MAI);
410 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
411 /// followed by an 'orr' to materialize.
412 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
413 const MachineOperand &MO = MI->getOperand(OpNum);
414 assert(MO.isImm() && "Not a valid so_imm value!");
415 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
416 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
417 printSOImm(O, V1, VerboseAsm, MAI);
419 printPredicateOperand(MI, 2);
425 printSOImm(O, V2, VerboseAsm, MAI);
428 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
429 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
431 // REG REG 0,SH_OPC - e.g. R5, ROR R3
432 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
433 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
434 const MachineOperand &MO1 = MI->getOperand(Op);
435 const MachineOperand &MO2 = MI->getOperand(Op+1);
436 const MachineOperand &MO3 = MI->getOperand(Op+2);
438 O << getRegisterName(MO1.getReg());
440 // Print the shift opc.
442 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
446 O << getRegisterName(MO2.getReg());
447 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
449 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
453 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
454 const MachineOperand &MO1 = MI->getOperand(Op);
455 const MachineOperand &MO2 = MI->getOperand(Op+1);
456 const MachineOperand &MO3 = MI->getOperand(Op+2);
458 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
459 printOperand(MI, Op);
463 O << "[" << getRegisterName(MO1.getReg());
466 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
468 << (char)ARM_AM::getAM2Op(MO3.getImm())
469 << ARM_AM::getAM2Offset(MO3.getImm());
475 << (char)ARM_AM::getAM2Op(MO3.getImm())
476 << getRegisterName(MO2.getReg());
478 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
480 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
485 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
486 const MachineOperand &MO1 = MI->getOperand(Op);
487 const MachineOperand &MO2 = MI->getOperand(Op+1);
490 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
491 assert(ImmOffs && "Malformed indexed load / store!");
493 << (char)ARM_AM::getAM2Op(MO2.getImm())
498 O << (char)ARM_AM::getAM2Op(MO2.getImm())
499 << getRegisterName(MO1.getReg());
501 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
503 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
507 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) {
508 const MachineOperand &MO1 = MI->getOperand(Op);
509 const MachineOperand &MO2 = MI->getOperand(Op+1);
510 const MachineOperand &MO3 = MI->getOperand(Op+2);
512 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
513 O << "[" << getRegisterName(MO1.getReg());
517 << (char)ARM_AM::getAM3Op(MO3.getImm())
518 << getRegisterName(MO2.getReg())
523 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
525 << (char)ARM_AM::getAM3Op(MO3.getImm())
530 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
531 const MachineOperand &MO1 = MI->getOperand(Op);
532 const MachineOperand &MO2 = MI->getOperand(Op+1);
535 O << (char)ARM_AM::getAM3Op(MO2.getImm())
536 << getRegisterName(MO1.getReg());
540 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
541 assert(ImmOffs && "Malformed indexed load / store!");
543 << (char)ARM_AM::getAM3Op(MO2.getImm())
547 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
548 const char *Modifier) {
549 const MachineOperand &MO1 = MI->getOperand(Op);
550 const MachineOperand &MO2 = MI->getOperand(Op+1);
551 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
552 if (Modifier && strcmp(Modifier, "submode") == 0) {
553 if (MO1.getReg() == ARM::SP) {
555 bool isLDM = (MI->getOpcode() == ARM::LDM ||
556 MI->getOpcode() == ARM::LDM_RET ||
557 MI->getOpcode() == ARM::t2LDM ||
558 MI->getOpcode() == ARM::t2LDM_RET);
559 O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
561 O << ARM_AM::getAMSubModeStr(Mode);
562 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
563 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
564 if (Mode == ARM_AM::ia)
567 printOperand(MI, Op);
568 if (ARM_AM::getAM4WBFlag(MO2.getImm()))
573 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
574 const char *Modifier) {
575 const MachineOperand &MO1 = MI->getOperand(Op);
576 const MachineOperand &MO2 = MI->getOperand(Op+1);
578 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
579 printOperand(MI, Op);
583 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
585 if (Modifier && strcmp(Modifier, "submode") == 0) {
586 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
587 if (MO1.getReg() == ARM::SP) {
588 bool isFLDM = (MI->getOpcode() == ARM::FLDMD ||
589 MI->getOpcode() == ARM::FLDMS);
590 O << ARM_AM::getAMSubModeAltStr(Mode, isFLDM);
592 O << ARM_AM::getAMSubModeStr(Mode);
594 } else if (Modifier && strcmp(Modifier, "base") == 0) {
595 // Used for FSTM{D|S} and LSTM{D|S} operations.
596 O << getRegisterName(MO1.getReg());
597 if (ARM_AM::getAM5WBFlag(MO2.getImm()))
602 O << "[" << getRegisterName(MO1.getReg());
604 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
606 << (char)ARM_AM::getAM5Op(MO2.getImm())
612 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) {
613 const MachineOperand &MO1 = MI->getOperand(Op);
614 const MachineOperand &MO2 = MI->getOperand(Op+1);
615 const MachineOperand &MO3 = MI->getOperand(Op+2);
617 // FIXME: No support yet for specifying alignment.
618 O << "[" << getRegisterName(MO1.getReg()) << "]";
620 if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
621 if (MO2.getReg() == 0)
624 O << ", " << getRegisterName(MO2.getReg());
628 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
629 const char *Modifier) {
630 if (Modifier && strcmp(Modifier, "label") == 0) {
631 printPCLabel(MI, Op+1);
635 const MachineOperand &MO1 = MI->getOperand(Op);
636 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
637 O << "[pc, +" << getRegisterName(MO1.getReg()) << "]";
641 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) {
642 const MachineOperand &MO = MI->getOperand(Op);
643 uint32_t v = ~MO.getImm();
644 int32_t lsb = CountTrailingZeros_32(v);
645 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
646 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
647 O << "#" << lsb << ", #" << width;
650 //===--------------------------------------------------------------------===//
653 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) {
654 // (3 - the number of trailing zeros) is the number of then / else.
655 unsigned Mask = MI->getOperand(Op).getImm();
656 unsigned NumTZ = CountTrailingZeros_32(Mask);
657 assert(NumTZ <= 3 && "Invalid IT mask!");
658 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
659 bool T = (Mask & (1 << Pos)) == 0;
668 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
669 const MachineOperand &MO1 = MI->getOperand(Op);
670 const MachineOperand &MO2 = MI->getOperand(Op+1);
671 O << "[" << getRegisterName(MO1.getReg());
672 O << ", " << getRegisterName(MO2.getReg()) << "]";
676 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
678 const MachineOperand &MO1 = MI->getOperand(Op);
679 const MachineOperand &MO2 = MI->getOperand(Op+1);
680 const MachineOperand &MO3 = MI->getOperand(Op+2);
682 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
683 printOperand(MI, Op);
687 O << "[" << getRegisterName(MO1.getReg());
689 O << ", " << getRegisterName(MO3.getReg());
690 else if (unsigned ImmOffs = MO2.getImm()) {
691 O << ", #" << ImmOffs;
699 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) {
700 printThumbAddrModeRI5Operand(MI, Op, 1);
703 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) {
704 printThumbAddrModeRI5Operand(MI, Op, 2);
707 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
708 printThumbAddrModeRI5Operand(MI, Op, 4);
711 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
712 const MachineOperand &MO1 = MI->getOperand(Op);
713 const MachineOperand &MO2 = MI->getOperand(Op+1);
714 O << "[" << getRegisterName(MO1.getReg());
715 if (unsigned ImmOffs = MO2.getImm())
716 O << ", #" << ImmOffs << " * 4";
720 //===--------------------------------------------------------------------===//
722 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
723 // register with shift forms.
725 // REG IMM, SH_OPC - e.g. R5, LSL #3
726 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) {
727 const MachineOperand &MO1 = MI->getOperand(OpNum);
728 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
730 unsigned Reg = MO1.getReg();
731 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
732 O << getRegisterName(Reg);
734 // Print the shift opc.
736 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
739 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
740 O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
743 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
745 const MachineOperand &MO1 = MI->getOperand(OpNum);
746 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
748 O << "[" << getRegisterName(MO1.getReg());
750 unsigned OffImm = MO2.getImm();
751 if (OffImm) // Don't print +0.
752 O << ", #+" << OffImm;
756 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
758 const MachineOperand &MO1 = MI->getOperand(OpNum);
759 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
761 O << "[" << getRegisterName(MO1.getReg());
763 int32_t OffImm = (int32_t)MO2.getImm();
766 O << ", #-" << -OffImm;
768 O << ", #+" << OffImm;
772 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
774 const MachineOperand &MO1 = MI->getOperand(OpNum);
775 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
777 O << "[" << getRegisterName(MO1.getReg());
779 int32_t OffImm = (int32_t)MO2.getImm() / 4;
782 O << ", #-" << -OffImm << " * 4";
784 O << ", #+" << OffImm << " * 4";
788 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
790 const MachineOperand &MO1 = MI->getOperand(OpNum);
791 int32_t OffImm = (int32_t)MO1.getImm();
794 O << "#-" << -OffImm;
799 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
801 const MachineOperand &MO1 = MI->getOperand(OpNum);
802 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
803 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
805 O << "[" << getRegisterName(MO1.getReg());
807 assert(MO2.getReg() && "Invalid so_reg load / store address!");
808 O << ", " << getRegisterName(MO2.getReg());
810 unsigned ShAmt = MO3.getImm();
812 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
813 O << ", lsl #" << ShAmt;
819 //===--------------------------------------------------------------------===//
821 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum) {
822 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
824 O << ARMCondCodeToString(CC);
827 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){
828 unsigned Reg = MI->getOperand(OpNum).getReg();
830 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
835 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) {
836 int Id = (int)MI->getOperand(OpNum).getImm();
837 O << MAI->getPrivateGlobalPrefix() << "PC" << Id;
840 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) {
842 // Always skip the first operand, it's the optional (and implicit writeback).
843 for (unsigned i = OpNum+1, e = MI->getNumOperands(); i != e; ++i) {
844 if (MI->getOperand(i).isImplicit())
846 if ((int)i != OpNum+1) O << ", ";
852 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
853 const char *Modifier) {
854 assert(Modifier && "This operand only works with a modifier!");
855 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
857 if (!strcmp(Modifier, "label")) {
858 unsigned ID = MI->getOperand(OpNum).getImm();
859 O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
860 << '_' << ID << ":\n";
862 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
863 unsigned CPI = MI->getOperand(OpNum).getIndex();
865 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
867 if (MCPE.isMachineConstantPoolEntry()) {
868 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
870 EmitGlobalConstant(MCPE.Val.ConstVal);
875 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) {
876 assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
878 const MachineOperand &MO1 = MI->getOperand(OpNum);
879 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
880 unsigned JTI = MO1.getIndex();
881 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
882 << '_' << JTI << '_' << MO2.getImm() << ":\n";
884 const char *JTEntryDirective = MAI->getData32bitsDirective();
886 const MachineFunction *MF = MI->getParent()->getParent();
887 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
888 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
889 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
890 bool UseSet= MAI->getSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
891 SmallPtrSet<MachineBasicBlock*, 8> JTSets;
892 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
893 MachineBasicBlock *MBB = JTBBs[i];
894 bool isNew = JTSets.insert(MBB);
897 printPICJumpTableSetLabel(JTI, MO2.getImm(), MBB);
899 O << JTEntryDirective << ' ';
901 O << MAI->getPrivateGlobalPrefix() << getFunctionNumber()
902 << '_' << JTI << '_' << MO2.getImm()
903 << "_set_" << MBB->getNumber();
904 else if (TM.getRelocationModel() == Reloc::PIC_) {
905 GetMBBSymbol(MBB->getNumber())->print(O, MAI);
906 O << '-' << MAI->getPrivateGlobalPrefix() << "JTI"
907 << getFunctionNumber() << '_' << JTI << '_' << MO2.getImm();
909 GetMBBSymbol(MBB->getNumber())->print(O, MAI);
916 void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum) {
917 const MachineOperand &MO1 = MI->getOperand(OpNum);
918 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
919 unsigned JTI = MO1.getIndex();
920 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
921 << '_' << JTI << '_' << MO2.getImm() << ":\n";
923 const MachineFunction *MF = MI->getParent()->getParent();
924 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
925 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
926 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
927 bool ByteOffset = false, HalfWordOffset = false;
928 if (MI->getOpcode() == ARM::t2TBB)
930 else if (MI->getOpcode() == ARM::t2TBH)
931 HalfWordOffset = true;
933 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
934 MachineBasicBlock *MBB = JTBBs[i];
936 O << MAI->getData8bitsDirective();
937 else if (HalfWordOffset)
938 O << MAI->getData16bitsDirective();
939 if (ByteOffset || HalfWordOffset) {
941 GetMBBSymbol(MBB->getNumber())->print(O, MAI);
942 O << "-" << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
943 << '_' << JTI << '_' << MO2.getImm() << ")/2";
946 GetMBBSymbol(MBB->getNumber())->print(O, MAI);
952 // Make sure the instruction that follows TBB is 2-byte aligned.
953 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
954 if (ByteOffset && (JTBBs.size() & 1)) {
960 void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum) {
961 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
962 if (MI->getOpcode() == ARM::t2TBH)
967 void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum) {
968 O << MI->getOperand(OpNum).getImm();
971 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
972 unsigned AsmVariant, const char *ExtraCode){
973 // Does this asm operand have a single letter operand modifier?
974 if (ExtraCode && ExtraCode[0]) {
975 if (ExtraCode[1] != 0) return true; // Unknown modifier.
977 switch (ExtraCode[0]) {
978 default: return true; // Unknown modifier.
979 case 'a': // Print as a memory address.
980 if (MI->getOperand(OpNum).isReg()) {
981 O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
985 case 'c': // Don't print "#" before an immediate operand.
986 if (!MI->getOperand(OpNum).isImm())
988 printNoHashImmediate(MI, OpNum);
990 case 'P': // Print a VFP double precision register.
991 printOperand(MI, OpNum);
994 if (TM.getTargetData()->isLittleEndian())
998 if (TM.getTargetData()->isBigEndian())
1001 case 'H': // Write second word of DI / DF reference.
1002 // Verify that this operand has two consecutive registers.
1003 if (!MI->getOperand(OpNum).isReg() ||
1004 OpNum+1 == MI->getNumOperands() ||
1005 !MI->getOperand(OpNum+1).isReg())
1007 ++OpNum; // Return the high-part.
1011 printOperand(MI, OpNum);
1015 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1016 unsigned OpNum, unsigned AsmVariant,
1017 const char *ExtraCode) {
1018 if (ExtraCode && ExtraCode[0])
1019 return true; // Unknown modifier.
1021 const MachineOperand &MO = MI->getOperand(OpNum);
1022 assert(MO.isReg() && "unexpected inline asm memory operand");
1023 O << "[" << getRegisterName(MO.getReg()) << "]";
1027 void ARMAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
1030 int Opc = MI->getOpcode();
1032 case ARM::CONSTPOOL_ENTRY:
1033 if (!InCPMode && AFI->isThumbFunction()) {
1039 if (InCPMode && AFI->isThumbFunction())
1043 // Call the autogenerated instruction printer routines.
1044 processDebugLoc(MI, true);
1045 printInstruction(MI);
1046 if (VerboseAsm && !MI->getDebugLoc().isUnknown())
1049 processDebugLoc(MI, false);
1052 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
1053 if (Subtarget->isTargetDarwin()) {
1054 Reloc::Model RelocM = TM.getRelocationModel();
1055 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
1056 // Declare all the text sections up front (before the DWARF sections
1057 // emitted by AsmPrinter::doInitialization) so the assembler will keep
1058 // them together at the beginning of the object file. This helps
1059 // avoid out-of-range branches that are due a fundamental limitation of
1060 // the way symbol offsets are encoded with the current Darwin ARM
1062 TargetLoweringObjectFileMachO &TLOFMacho =
1063 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1064 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
1065 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
1066 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
1067 if (RelocM == Reloc::DynamicNoPIC) {
1068 const MCSection *sect =
1069 TLOFMacho.getMachOSection("__TEXT", "__symbol_stub4",
1070 MCSectionMachO::S_SYMBOL_STUBS,
1071 12, SectionKind::getText());
1072 OutStreamer.SwitchSection(sect);
1074 const MCSection *sect =
1075 TLOFMacho.getMachOSection("__TEXT", "__picsymbolstub4",
1076 MCSectionMachO::S_SYMBOL_STUBS,
1077 16, SectionKind::getText());
1078 OutStreamer.SwitchSection(sect);
1083 // Use unified assembler syntax mode for Thumb.
1084 if (Subtarget->isThumb())
1085 O << "\t.syntax unified\n";
1087 // Emit ARM Build Attributes
1088 if (Subtarget->isTargetELF()) {
1090 std::string CPUString = Subtarget->getCPUString();
1091 if (CPUString != "generic")
1092 O << "\t.cpu " << CPUString << '\n';
1094 // FIXME: Emit FPU type
1095 if (Subtarget->hasVFP2())
1096 O << "\t.eabi_attribute " << ARMBuildAttrs::VFP_arch << ", 2\n";
1098 // Signal various FP modes.
1100 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_denormal << ", 1\n"
1101 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_exceptions << ", 1\n";
1103 if (FiniteOnlyFPMath())
1104 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 1\n";
1106 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 3\n";
1108 // 8-bytes alignment stuff.
1109 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_needed << ", 1\n"
1110 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_preserved << ", 1\n";
1112 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
1113 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard)
1114 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_HardFP_use << ", 3\n"
1115 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_VFP_args << ", 1\n";
1117 // FIXME: Should we signal R9 usage?
1121 void ARMAsmPrinter::PrintGlobalVariable(const GlobalVariable* GVar) {
1122 const TargetData *TD = TM.getTargetData();
1124 if (!GVar->hasInitializer()) // External global require no code
1127 // Check to see if this is a special global used by LLVM, if so, emit it.
1129 if (EmitSpecialLLVMGlobal(GVar)) {
1130 if (Subtarget->isTargetDarwin() &&
1131 TM.getRelocationModel() == Reloc::Static) {
1132 if (GVar->getName() == "llvm.global_ctors")
1133 O << ".reference .constructors_used\n";
1134 else if (GVar->getName() == "llvm.global_dtors")
1135 O << ".reference .destructors_used\n";
1140 std::string name = Mang->getMangledName(GVar);
1141 Constant *C = GVar->getInitializer();
1142 const Type *Type = C->getType();
1143 unsigned Size = TD->getTypeAllocSize(Type);
1144 unsigned Align = TD->getPreferredAlignmentLog(GVar);
1145 bool isDarwin = Subtarget->isTargetDarwin();
1147 printVisibility(name, GVar->getVisibility());
1149 if (Subtarget->isTargetELF())
1150 O << "\t.type " << name << ",%object\n";
1152 const MCSection *TheSection =
1153 getObjFileLowering().SectionForGlobal(GVar, Mang, TM);
1154 OutStreamer.SwitchSection(TheSection);
1156 // FIXME: get this stuff from section kind flags.
1157 if (C->isNullValue() && !GVar->hasSection() && !GVar->isThreadLocal() &&
1158 // Don't put things that should go in the cstring section into "comm".
1159 !TheSection->getKind().isMergeableCString()) {
1160 if (GVar->hasExternalLinkage()) {
1161 if (const char *Directive = MAI->getZeroFillDirective()) {
1162 O << "\t.globl\t" << name << "\n";
1163 O << Directive << "__DATA, __common, " << name << ", "
1164 << Size << ", " << Align << "\n";
1169 if (GVar->hasLocalLinkage() || GVar->isWeakForLinker()) {
1170 if (Size == 0) Size = 1; // .comm Foo, 0 is undefined, avoid it.
1173 if (GVar->hasLocalLinkage()) {
1174 O << MAI->getLCOMMDirective() << name << "," << Size
1176 } else if (GVar->hasCommonLinkage()) {
1177 O << MAI->getCOMMDirective() << name << "," << Size
1180 OutStreamer.SwitchSection(TheSection);
1181 O << "\t.globl " << name << '\n'
1182 << MAI->getWeakDefDirective() << name << '\n';
1183 EmitAlignment(Align, GVar);
1186 O << "\t\t\t\t" << MAI->getCommentString() << ' ';
1187 WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
1190 EmitGlobalConstant(C);
1193 } else if (MAI->getLCOMMDirective() != NULL) {
1194 if (GVar->hasLocalLinkage()) {
1195 O << MAI->getLCOMMDirective() << name << "," << Size;
1197 O << MAI->getCOMMDirective() << name << "," << Size;
1198 if (MAI->getCOMMDirectiveTakesAlignment())
1199 O << ',' << (MAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1202 if (GVar->hasLocalLinkage())
1203 O << "\t.local\t" << name << "\n";
1204 O << MAI->getCOMMDirective() << name << "," << Size;
1205 if (MAI->getCOMMDirectiveTakesAlignment())
1206 O << "," << (MAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1209 O << "\t\t" << MAI->getCommentString() << " ";
1210 WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
1217 switch (GVar->getLinkage()) {
1218 case GlobalValue::CommonLinkage:
1219 case GlobalValue::LinkOnceAnyLinkage:
1220 case GlobalValue::LinkOnceODRLinkage:
1221 case GlobalValue::WeakAnyLinkage:
1222 case GlobalValue::WeakODRLinkage:
1223 case GlobalValue::LinkerPrivateLinkage:
1225 O << "\t.globl " << name << "\n"
1226 << "\t.weak_definition " << name << "\n";
1228 O << "\t.weak " << name << "\n";
1231 case GlobalValue::AppendingLinkage:
1232 // FIXME: appending linkage variables should go into a section of
1233 // their name or something. For now, just emit them as external.
1234 case GlobalValue::ExternalLinkage:
1235 O << "\t.globl " << name << "\n";
1237 case GlobalValue::PrivateLinkage:
1238 case GlobalValue::InternalLinkage:
1241 llvm_unreachable("Unknown linkage type!");
1244 EmitAlignment(Align, GVar);
1247 O << "\t\t\t\t" << MAI->getCommentString() << " ";
1248 WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
1251 if (MAI->hasDotTypeDotSizeDirective())
1252 O << "\t.size " << name << ", " << Size << "\n";
1254 EmitGlobalConstant(C);
1259 bool ARMAsmPrinter::doFinalization(Module &M) {
1260 if (Subtarget->isTargetDarwin()) {
1261 // All darwin targets use mach-o.
1262 TargetLoweringObjectFileMachO &TLOFMacho =
1263 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1267 // Output non-lazy-pointers for external and common global variables.
1268 if (!GVNonLazyPtrs.empty()) {
1269 // Switch with ".non_lazy_symbol_pointer" directive.
1270 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
1272 for (StringMap<std::string>::iterator I = GVNonLazyPtrs.begin(),
1273 E = GVNonLazyPtrs.end(); I != E; ++I) {
1274 O << I->second << ":\n";
1275 O << "\t.indirect_symbol " << I->getKeyData() << "\n";
1276 O << "\t.long\t0\n";
1280 if (!HiddenGVNonLazyPtrs.empty()) {
1281 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
1283 for (StringMap<std::string>::iterator I = HiddenGVNonLazyPtrs.begin(),
1284 E = HiddenGVNonLazyPtrs.end(); I != E; ++I) {
1285 O << I->second << ":\n";
1286 O << "\t.long " << I->getKeyData() << "\n";
1290 // Funny Darwin hack: This flag tells the linker that no global symbols
1291 // contain code that falls through to other global symbols (e.g. the obvious
1292 // implementation of multiple entry points). If this doesn't occur, the
1293 // linker can safely perform dead code stripping. Since LLVM never
1294 // generates code that does this, it is always safe to set.
1295 O << "\t.subsections_via_symbols\n";
1298 return AsmPrinter::doFinalization(M);
1301 // Force static initialization.
1302 extern "C" void LLVMInitializeARMAsmPrinter() {
1303 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1304 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);