1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMInstPrinter.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMMCInstLower.h"
23 #include "ARMTargetMachine.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Module.h"
26 #include "llvm/Type.h"
27 #include "llvm/Assembly/Writer.h"
28 #include "llvm/CodeGen/AsmPrinter.h"
29 #include "llvm/CodeGen/DwarfWriter.h"
30 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCContext.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/MC/MCSectionMachO.h"
37 #include "llvm/MC/MCStreamer.h"
38 #include "llvm/MC/MCSymbol.h"
39 #include "llvm/Target/TargetData.h"
40 #include "llvm/Target/TargetLoweringObjectFile.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetOptions.h"
43 #include "llvm/Target/TargetRegistry.h"
44 #include "llvm/ADT/SmallPtrSet.h"
45 #include "llvm/ADT/SmallString.h"
46 #include "llvm/ADT/Statistic.h"
47 #include "llvm/ADT/StringExtras.h"
48 #include "llvm/ADT/StringSet.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/FormattedStream.h"
52 #include "llvm/Support/MathExtras.h"
56 STATISTIC(EmittedInsts, "Number of machine instrs printed");
59 EnableMCInst("enable-arm-mcinst-printer", cl::Hidden,
60 cl::desc("enable experimental asmprinter gunk in the arm backend"));
63 class ARMAsmPrinter : public AsmPrinter {
65 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
66 /// make the right decision when printing asm code for different targets.
67 const ARMSubtarget *Subtarget;
69 /// AFI - Keep a pointer to ARMFunctionInfo for the current
73 /// MCP - Keep a pointer to constantpool entries of the current
75 const MachineConstantPool *MCP;
78 explicit ARMAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM,
79 const MCAsmInfo *T, bool V)
80 : AsmPrinter(O, TM, T, V), AFI(NULL), MCP(NULL) {
81 Subtarget = &TM.getSubtarget<ARMSubtarget>();
84 virtual const char *getPassName() const {
85 return "ARM Assembly Printer";
88 void printMCInst(const MCInst *MI) {
89 ARMInstPrinter(O, *MAI, VerboseAsm).printInstruction(MI);
92 void printInstructionThroughMCStreamer(const MachineInstr *MI);
95 void printOperand(const MachineInstr *MI, int OpNum,
96 const char *Modifier = 0);
97 void printSOImmOperand(const MachineInstr *MI, int OpNum);
98 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum);
99 void printSORegOperand(const MachineInstr *MI, int OpNum);
100 void printAddrMode2Operand(const MachineInstr *MI, int OpNum);
101 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum);
102 void printAddrMode3Operand(const MachineInstr *MI, int OpNum);
103 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum);
104 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,
105 const char *Modifier = 0);
106 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,
107 const char *Modifier = 0);
108 void printAddrMode6Operand(const MachineInstr *MI, int OpNum);
109 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
110 const char *Modifier = 0);
111 void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum);
113 void printThumbS4ImmOperand(const MachineInstr *MI, int OpNum);
114 void printThumbITMask(const MachineInstr *MI, int OpNum);
115 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum);
116 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
118 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum);
119 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum);
120 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum);
121 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum);
123 void printT2SOOperand(const MachineInstr *MI, int OpNum);
124 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum);
125 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum);
126 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum);
127 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum);
128 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum);
130 void printPredicateOperand(const MachineInstr *MI, int OpNum);
131 void printSBitModifierOperand(const MachineInstr *MI, int OpNum);
132 void printPCLabel(const MachineInstr *MI, int OpNum);
133 void printRegisterList(const MachineInstr *MI, int OpNum);
134 void printCPInstOperand(const MachineInstr *MI, int OpNum,
135 const char *Modifier);
136 void printJTBlockOperand(const MachineInstr *MI, int OpNum);
137 void printJT2BlockOperand(const MachineInstr *MI, int OpNum);
138 void printTBAddrMode(const MachineInstr *MI, int OpNum);
139 void printNoHashImmediate(const MachineInstr *MI, int OpNum);
140 void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum);
141 void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum);
143 void printHex8ImmOperand(const MachineInstr *MI, int OpNum) {
144 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xff);
146 void printHex16ImmOperand(const MachineInstr *MI, int OpNum) {
147 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffff);
149 void printHex32ImmOperand(const MachineInstr *MI, int OpNum) {
150 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffffffff);
152 void printHex64ImmOperand(const MachineInstr *MI, int OpNum) {
153 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm());
156 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
157 unsigned AsmVariant, const char *ExtraCode);
158 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
160 const char *ExtraCode);
162 void printInstruction(const MachineInstr *MI); // autogenerated.
163 static const char *getRegisterName(unsigned RegNo);
165 void printMachineInstruction(const MachineInstr *MI);
166 bool runOnMachineFunction(MachineFunction &F);
168 virtual void EmitConstantPool() {} // we emit constant pools customly!
169 virtual void EmitFunctionEntryLabel();
170 void EmitStartOfAsmFile(Module &M);
171 void EmitEndOfAsmFile(Module &M);
173 MCSymbol *GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
174 const MachineBasicBlock *MBB) const;
175 MCSymbol *GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const;
177 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
179 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
180 switch (TM.getTargetData()->getTypeAllocSize(MCPV->getType())) {
181 case 1: O << MAI->getData8bitsDirective(0); break;
182 case 2: O << MAI->getData16bitsDirective(0); break;
183 case 4: O << MAI->getData32bitsDirective(0); break;
184 default: assert(0 && "Unknown CPV size");
187 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
188 SmallString<128> TmpNameStr;
190 if (ACPV->isLSDA()) {
191 raw_svector_ostream(TmpNameStr) << MAI->getPrivateGlobalPrefix() <<
192 "_LSDA_" << getFunctionNumber();
193 O << TmpNameStr.str();
194 } else if (ACPV->isBlockAddress()) {
195 O << GetBlockAddressSymbol(ACPV->getBlockAddress())->getName();
196 } else if (ACPV->isGlobalValue()) {
197 GlobalValue *GV = ACPV->getGV();
198 bool isIndirect = Subtarget->isTargetDarwin() &&
199 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
201 O << *GetGlobalValueSymbol(GV);
203 // FIXME: Remove this when Darwin transition to @GOT like syntax.
204 MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
207 MachineModuleInfoMachO &MMIMachO =
208 MMI->getObjFileInfo<MachineModuleInfoMachO>();
209 const MCSymbol *&StubSym =
210 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
211 MMIMachO.getGVStubEntry(Sym);
213 StubSym = GetGlobalValueSymbol(GV);
216 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
217 O << *GetExternalSymbolSymbol(ACPV->getSymbol());
220 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
221 if (ACPV->getPCAdjustment() != 0) {
222 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
223 << getFunctionNumber() << "_" << ACPV->getLabelId()
224 << "+" << (unsigned)ACPV->getPCAdjustment();
225 if (ACPV->mustAddCurrentAddress())
232 void getAnalysisUsage(AnalysisUsage &AU) const {
233 AsmPrinter::getAnalysisUsage(AU);
234 AU.setPreservesAll();
235 AU.addRequired<MachineModuleInfo>();
236 AU.addRequired<DwarfWriter>();
239 } // end of anonymous namespace
241 #include "ARMGenAsmWriter.inc"
243 void ARMAsmPrinter::EmitFunctionEntryLabel() {
244 if (AFI->isThumbFunction()) {
245 O << "\t.code\t16\n";
246 O << "\t.thumb_func";
247 if (Subtarget->isTargetDarwin())
248 O << '\t' << *CurrentFnSym;
252 OutStreamer.EmitLabel(CurrentFnSym);
255 /// runOnMachineFunction - This uses the printInstruction()
256 /// method to print assembly for each instruction.
258 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
259 AFI = MF.getInfo<ARMFunctionInfo>();
260 MCP = MF.getConstantPool();
262 SetupMachineFunction(MF);
265 // NOTE: we don't print out constant pools here, they are handled as
267 EmitFunctionHeader();
269 // Print out code for the function.
270 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
272 // Print a label for the basic block.
273 EmitBasicBlockStart(I);
275 // Print the assembly for the instruction.
276 for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
278 printMachineInstruction(II);
281 if (Subtarget->isTargetDarwin()) {
282 // If the function is empty, then we need to emit *something*. Otherwise,
283 // the function's label might be associated with something that it wasn't
284 // meant to be associated with. We emit a noop in this situation.
285 MachineFunction::iterator I = MF.begin();
286 if (++I == MF.end() && MF.front().empty())
290 if (MAI->hasDotTypeDotSizeDirective())
291 O << "\t.size " << *CurrentFnSym << ", .-" << *CurrentFnSym << "\n";
293 // Emit post-function debug information.
294 DW->EndFunction(&MF);
299 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
300 const char *Modifier) {
301 const MachineOperand &MO = MI->getOperand(OpNum);
302 unsigned TF = MO.getTargetFlags();
304 switch (MO.getType()) {
306 assert(0 && "<unknown operand type>");
307 case MachineOperand::MO_Register: {
308 unsigned Reg = MO.getReg();
309 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
310 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
311 unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
312 unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
314 << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
316 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
317 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
318 unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1,
319 &ARM::DPR_VFP2RegClass);
320 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
322 assert(!MO.getSubReg() && "Subregs should be eliminated!");
323 O << getRegisterName(Reg);
327 case MachineOperand::MO_Immediate: {
328 int64_t Imm = MO.getImm();
330 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
331 (TF & ARMII::MO_LO16))
333 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
334 (TF & ARMII::MO_HI16))
339 case MachineOperand::MO_MachineBasicBlock:
340 O << *MO.getMBB()->getSymbol(OutContext);
342 case MachineOperand::MO_GlobalAddress: {
343 bool isCallOp = Modifier && !strcmp(Modifier, "call");
344 GlobalValue *GV = MO.getGlobal();
346 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
347 (TF & ARMII::MO_LO16))
349 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
350 (TF & ARMII::MO_HI16))
352 O << *GetGlobalValueSymbol(GV);
354 printOffset(MO.getOffset());
356 if (isCallOp && Subtarget->isTargetELF() &&
357 TM.getRelocationModel() == Reloc::PIC_)
361 case MachineOperand::MO_ExternalSymbol: {
362 bool isCallOp = Modifier && !strcmp(Modifier, "call");
363 O << *GetExternalSymbolSymbol(MO.getSymbolName());
365 if (isCallOp && Subtarget->isTargetELF() &&
366 TM.getRelocationModel() == Reloc::PIC_)
370 case MachineOperand::MO_ConstantPoolIndex:
371 O << *GetCPISymbol(MO.getIndex());
373 case MachineOperand::MO_JumpTableIndex:
374 O << *GetJTISymbol(MO.getIndex());
379 static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm,
380 const MCAsmInfo *MAI) {
381 // Break it up into two parts that make up a shifter immediate.
382 V = ARM_AM::getSOImmVal(V);
383 assert(V != -1 && "Not a valid so_imm value!");
385 unsigned Imm = ARM_AM::getSOImmValImm(V);
386 unsigned Rot = ARM_AM::getSOImmValRot(V);
388 // Print low-level immediate formation info, per
389 // A5.1.3: "Data-processing operands - Immediate".
391 O << "#" << Imm << ", " << Rot;
392 // Pretty printed version.
394 O.PadToColumn(MAI->getCommentColumn());
395 O << MAI->getCommentString() << ' ';
396 O << (int)ARM_AM::rotr32(Imm, Rot);
403 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
404 /// immediate in bits 0-7.
405 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
406 const MachineOperand &MO = MI->getOperand(OpNum);
407 assert(MO.isImm() && "Not a valid so_imm value!");
408 printSOImm(O, MO.getImm(), VerboseAsm, MAI);
411 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
412 /// followed by an 'orr' to materialize.
413 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
414 const MachineOperand &MO = MI->getOperand(OpNum);
415 assert(MO.isImm() && "Not a valid so_imm value!");
416 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
417 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
418 printSOImm(O, V1, VerboseAsm, MAI);
420 printPredicateOperand(MI, 2);
426 printSOImm(O, V2, VerboseAsm, MAI);
429 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
430 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
432 // REG REG 0,SH_OPC - e.g. R5, ROR R3
433 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
434 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
435 const MachineOperand &MO1 = MI->getOperand(Op);
436 const MachineOperand &MO2 = MI->getOperand(Op+1);
437 const MachineOperand &MO3 = MI->getOperand(Op+2);
439 O << getRegisterName(MO1.getReg());
441 // Print the shift opc.
443 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
447 O << getRegisterName(MO2.getReg());
448 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
450 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
454 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
455 const MachineOperand &MO1 = MI->getOperand(Op);
456 const MachineOperand &MO2 = MI->getOperand(Op+1);
457 const MachineOperand &MO3 = MI->getOperand(Op+2);
459 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
460 printOperand(MI, Op);
464 O << "[" << getRegisterName(MO1.getReg());
467 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
469 << (char)ARM_AM::getAM2Op(MO3.getImm())
470 << ARM_AM::getAM2Offset(MO3.getImm());
476 << (char)ARM_AM::getAM2Op(MO3.getImm())
477 << getRegisterName(MO2.getReg());
479 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
481 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
486 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
487 const MachineOperand &MO1 = MI->getOperand(Op);
488 const MachineOperand &MO2 = MI->getOperand(Op+1);
491 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
492 assert(ImmOffs && "Malformed indexed load / store!");
494 << (char)ARM_AM::getAM2Op(MO2.getImm())
499 O << (char)ARM_AM::getAM2Op(MO2.getImm())
500 << getRegisterName(MO1.getReg());
502 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
504 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
508 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) {
509 const MachineOperand &MO1 = MI->getOperand(Op);
510 const MachineOperand &MO2 = MI->getOperand(Op+1);
511 const MachineOperand &MO3 = MI->getOperand(Op+2);
513 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
514 O << "[" << getRegisterName(MO1.getReg());
518 << (char)ARM_AM::getAM3Op(MO3.getImm())
519 << getRegisterName(MO2.getReg())
524 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
526 << (char)ARM_AM::getAM3Op(MO3.getImm())
531 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
532 const MachineOperand &MO1 = MI->getOperand(Op);
533 const MachineOperand &MO2 = MI->getOperand(Op+1);
536 O << (char)ARM_AM::getAM3Op(MO2.getImm())
537 << getRegisterName(MO1.getReg());
541 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
542 assert(ImmOffs && "Malformed indexed load / store!");
544 << (char)ARM_AM::getAM3Op(MO2.getImm())
548 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
549 const char *Modifier) {
550 const MachineOperand &MO1 = MI->getOperand(Op);
551 const MachineOperand &MO2 = MI->getOperand(Op+1);
552 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
553 if (Modifier && strcmp(Modifier, "submode") == 0) {
554 if (MO1.getReg() == ARM::SP) {
556 bool isLDM = (MI->getOpcode() == ARM::LDM ||
557 MI->getOpcode() == ARM::LDM_RET ||
558 MI->getOpcode() == ARM::t2LDM ||
559 MI->getOpcode() == ARM::t2LDM_RET);
560 O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
562 O << ARM_AM::getAMSubModeStr(Mode);
563 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
564 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
565 if (Mode == ARM_AM::ia)
568 printOperand(MI, Op);
569 if (ARM_AM::getAM4WBFlag(MO2.getImm()))
574 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
575 const char *Modifier) {
576 const MachineOperand &MO1 = MI->getOperand(Op);
577 const MachineOperand &MO2 = MI->getOperand(Op+1);
579 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
580 printOperand(MI, Op);
584 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
586 if (Modifier && strcmp(Modifier, "submode") == 0) {
587 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
588 O << ARM_AM::getAMSubModeStr(Mode);
590 } else if (Modifier && strcmp(Modifier, "base") == 0) {
591 // Used for FSTM{D|S} and LSTM{D|S} operations.
592 O << getRegisterName(MO1.getReg());
593 if (ARM_AM::getAM5WBFlag(MO2.getImm()))
598 O << "[" << getRegisterName(MO1.getReg());
600 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
602 << (char)ARM_AM::getAM5Op(MO2.getImm())
608 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) {
609 const MachineOperand &MO1 = MI->getOperand(Op);
610 const MachineOperand &MO2 = MI->getOperand(Op+1);
611 const MachineOperand &MO3 = MI->getOperand(Op+2);
612 const MachineOperand &MO4 = MI->getOperand(Op+3);
614 O << "[" << getRegisterName(MO1.getReg());
616 // FIXME: Both darwin as and GNU as violate ARM docs here.
617 O << ", :" << MO4.getImm();
621 if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
622 if (MO2.getReg() == 0)
625 O << ", " << getRegisterName(MO2.getReg());
629 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
630 const char *Modifier) {
631 if (Modifier && strcmp(Modifier, "label") == 0) {
632 printPCLabel(MI, Op+1);
636 const MachineOperand &MO1 = MI->getOperand(Op);
637 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
638 O << "[pc, +" << getRegisterName(MO1.getReg()) << "]";
642 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) {
643 const MachineOperand &MO = MI->getOperand(Op);
644 uint32_t v = ~MO.getImm();
645 int32_t lsb = CountTrailingZeros_32(v);
646 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
647 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
648 O << "#" << lsb << ", #" << width;
651 //===--------------------------------------------------------------------===//
653 void ARMAsmPrinter::printThumbS4ImmOperand(const MachineInstr *MI, int Op) {
654 O << "#" << MI->getOperand(Op).getImm() * 4;
658 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) {
659 // (3 - the number of trailing zeros) is the number of then / else.
660 unsigned Mask = MI->getOperand(Op).getImm();
661 unsigned NumTZ = CountTrailingZeros_32(Mask);
662 assert(NumTZ <= 3 && "Invalid IT mask!");
663 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
664 bool T = (Mask & (1 << Pos)) == 0;
673 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
674 const MachineOperand &MO1 = MI->getOperand(Op);
675 const MachineOperand &MO2 = MI->getOperand(Op+1);
676 O << "[" << getRegisterName(MO1.getReg());
677 O << ", " << getRegisterName(MO2.getReg()) << "]";
681 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
683 const MachineOperand &MO1 = MI->getOperand(Op);
684 const MachineOperand &MO2 = MI->getOperand(Op+1);
685 const MachineOperand &MO3 = MI->getOperand(Op+2);
687 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
688 printOperand(MI, Op);
692 O << "[" << getRegisterName(MO1.getReg());
694 O << ", " << getRegisterName(MO3.getReg());
695 else if (unsigned ImmOffs = MO2.getImm())
696 O << ", #+" << ImmOffs * Scale;
701 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) {
702 printThumbAddrModeRI5Operand(MI, Op, 1);
705 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) {
706 printThumbAddrModeRI5Operand(MI, Op, 2);
709 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
710 printThumbAddrModeRI5Operand(MI, Op, 4);
713 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
714 const MachineOperand &MO1 = MI->getOperand(Op);
715 const MachineOperand &MO2 = MI->getOperand(Op+1);
716 O << "[" << getRegisterName(MO1.getReg());
717 if (unsigned ImmOffs = MO2.getImm())
718 O << ", #+" << ImmOffs*4;
722 //===--------------------------------------------------------------------===//
724 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
725 // register with shift forms.
727 // REG IMM, SH_OPC - e.g. R5, LSL #3
728 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) {
729 const MachineOperand &MO1 = MI->getOperand(OpNum);
730 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
732 unsigned Reg = MO1.getReg();
733 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
734 O << getRegisterName(Reg);
736 // Print the shift opc.
738 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
741 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
742 O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
745 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
747 const MachineOperand &MO1 = MI->getOperand(OpNum);
748 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
750 O << "[" << getRegisterName(MO1.getReg());
752 unsigned OffImm = MO2.getImm();
753 if (OffImm) // Don't print +0.
754 O << ", #+" << OffImm;
758 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
760 const MachineOperand &MO1 = MI->getOperand(OpNum);
761 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
763 O << "[" << getRegisterName(MO1.getReg());
765 int32_t OffImm = (int32_t)MO2.getImm();
768 O << ", #-" << -OffImm;
770 O << ", #+" << OffImm;
774 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
776 const MachineOperand &MO1 = MI->getOperand(OpNum);
777 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
779 O << "[" << getRegisterName(MO1.getReg());
781 int32_t OffImm = (int32_t)MO2.getImm() / 4;
784 O << ", #-" << -OffImm * 4;
786 O << ", #+" << OffImm * 4;
790 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
792 const MachineOperand &MO1 = MI->getOperand(OpNum);
793 int32_t OffImm = (int32_t)MO1.getImm();
796 O << "#-" << -OffImm;
801 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
803 const MachineOperand &MO1 = MI->getOperand(OpNum);
804 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
805 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
807 O << "[" << getRegisterName(MO1.getReg());
809 assert(MO2.getReg() && "Invalid so_reg load / store address!");
810 O << ", " << getRegisterName(MO2.getReg());
812 unsigned ShAmt = MO3.getImm();
814 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
815 O << ", lsl #" << ShAmt;
821 //===--------------------------------------------------------------------===//
823 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum) {
824 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
826 O << ARMCondCodeToString(CC);
829 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){
830 unsigned Reg = MI->getOperand(OpNum).getReg();
832 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
837 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) {
838 int Id = (int)MI->getOperand(OpNum).getImm();
839 O << MAI->getPrivateGlobalPrefix()
840 << "PC" << getFunctionNumber() << "_" << Id;
843 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) {
845 // Always skip the first operand, it's the optional (and implicit writeback).
846 for (unsigned i = OpNum+1, e = MI->getNumOperands(); i != e; ++i) {
847 if (MI->getOperand(i).isImplicit())
849 if ((int)i != OpNum+1) O << ", ";
855 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
856 const char *Modifier) {
857 assert(Modifier && "This operand only works with a modifier!");
858 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
860 if (!strcmp(Modifier, "label")) {
861 unsigned ID = MI->getOperand(OpNum).getImm();
862 O << *GetCPISymbol(ID) << ":\n";
864 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
865 unsigned CPI = MI->getOperand(OpNum).getIndex();
867 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
869 if (MCPE.isMachineConstantPoolEntry()) {
870 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
872 EmitGlobalConstant(MCPE.Val.ConstVal);
877 MCSymbol *ARMAsmPrinter::
878 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
879 const MachineBasicBlock *MBB) const {
880 SmallString<60> Name;
881 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
882 << getFunctionNumber() << '_' << uid << '_' << uid2
883 << "_set_" << MBB->getNumber();
884 return OutContext.GetOrCreateSymbol(Name.str());
887 MCSymbol *ARMAsmPrinter::
888 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
889 SmallString<60> Name;
890 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
891 << getFunctionNumber() << '_' << uid << '_' << uid2;
892 return OutContext.GetOrCreateSymbol(Name.str());
895 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) {
896 assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
898 const MachineOperand &MO1 = MI->getOperand(OpNum);
899 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
901 unsigned JTI = MO1.getIndex();
902 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
903 OutStreamer.EmitLabel(JTISymbol);
905 const char *JTEntryDirective = MAI->getData32bitsDirective();
907 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
908 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
909 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
910 bool UseSet= MAI->hasSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
911 SmallPtrSet<MachineBasicBlock*, 8> JTSets;
912 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
913 MachineBasicBlock *MBB = JTBBs[i];
914 bool isNew = JTSets.insert(MBB);
916 if (UseSet && isNew) {
918 << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB) << ','
919 << *MBB->getSymbol(OutContext) << '-' << *JTISymbol << '\n';
922 O << JTEntryDirective << ' ';
924 O << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB);
925 else if (TM.getRelocationModel() == Reloc::PIC_)
926 O << *MBB->getSymbol(OutContext) << '-' << *JTISymbol;
928 O << *MBB->getSymbol(OutContext);
935 void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum) {
936 const MachineOperand &MO1 = MI->getOperand(OpNum);
937 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
938 unsigned JTI = MO1.getIndex();
940 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
941 OutStreamer.EmitLabel(JTISymbol);
943 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
944 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
945 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
946 bool ByteOffset = false, HalfWordOffset = false;
947 if (MI->getOpcode() == ARM::t2TBB)
949 else if (MI->getOpcode() == ARM::t2TBH)
950 HalfWordOffset = true;
952 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
953 MachineBasicBlock *MBB = JTBBs[i];
955 O << MAI->getData8bitsDirective();
956 else if (HalfWordOffset)
957 O << MAI->getData16bitsDirective();
959 if (ByteOffset || HalfWordOffset)
960 O << '(' << *MBB->getSymbol(OutContext) << "-" << *JTISymbol << ")/2";
962 O << "\tb.w " << *MBB->getSymbol(OutContext);
968 // Make sure the instruction that follows TBB is 2-byte aligned.
969 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
970 if (ByteOffset && (JTBBs.size() & 1)) {
976 void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum) {
977 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
978 if (MI->getOpcode() == ARM::t2TBH)
983 void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum) {
984 O << MI->getOperand(OpNum).getImm();
987 void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum) {
988 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
989 O << '#' << FP->getValueAPF().convertToFloat();
991 O.PadToColumn(MAI->getCommentColumn());
992 O << MAI->getCommentString() << ' ';
993 WriteAsOperand(O, FP, /*PrintType=*/false);
997 void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum) {
998 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
999 O << '#' << FP->getValueAPF().convertToDouble();
1001 O.PadToColumn(MAI->getCommentColumn());
1002 O << MAI->getCommentString() << ' ';
1003 WriteAsOperand(O, FP, /*PrintType=*/false);
1007 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
1008 unsigned AsmVariant, const char *ExtraCode){
1009 // Does this asm operand have a single letter operand modifier?
1010 if (ExtraCode && ExtraCode[0]) {
1011 if (ExtraCode[1] != 0) return true; // Unknown modifier.
1013 switch (ExtraCode[0]) {
1014 default: return true; // Unknown modifier.
1015 case 'a': // Print as a memory address.
1016 if (MI->getOperand(OpNum).isReg()) {
1017 O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
1021 case 'c': // Don't print "#" before an immediate operand.
1022 if (!MI->getOperand(OpNum).isImm())
1024 printNoHashImmediate(MI, OpNum);
1026 case 'P': // Print a VFP double precision register.
1027 case 'q': // Print a NEON quad precision register.
1028 printOperand(MI, OpNum);
1031 if (TM.getTargetData()->isLittleEndian())
1035 if (TM.getTargetData()->isBigEndian())
1038 case 'H': // Write second word of DI / DF reference.
1039 // Verify that this operand has two consecutive registers.
1040 if (!MI->getOperand(OpNum).isReg() ||
1041 OpNum+1 == MI->getNumOperands() ||
1042 !MI->getOperand(OpNum+1).isReg())
1044 ++OpNum; // Return the high-part.
1048 printOperand(MI, OpNum);
1052 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1053 unsigned OpNum, unsigned AsmVariant,
1054 const char *ExtraCode) {
1055 if (ExtraCode && ExtraCode[0])
1056 return true; // Unknown modifier.
1058 const MachineOperand &MO = MI->getOperand(OpNum);
1059 assert(MO.isReg() && "unexpected inline asm memory operand");
1060 O << "[" << getRegisterName(MO.getReg()) << "]";
1064 void ARMAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
1067 // Call the autogenerated instruction printer routines.
1068 processDebugLoc(MI, true);
1071 printInstructionThroughMCStreamer(MI);
1073 int Opc = MI->getOpcode();
1074 if (Opc == ARM::CONSTPOOL_ENTRY)
1077 printInstruction(MI);
1083 processDebugLoc(MI, false);
1086 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
1087 if (Subtarget->isTargetDarwin()) {
1088 Reloc::Model RelocM = TM.getRelocationModel();
1089 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
1090 // Declare all the text sections up front (before the DWARF sections
1091 // emitted by AsmPrinter::doInitialization) so the assembler will keep
1092 // them together at the beginning of the object file. This helps
1093 // avoid out-of-range branches that are due a fundamental limitation of
1094 // the way symbol offsets are encoded with the current Darwin ARM
1096 TargetLoweringObjectFileMachO &TLOFMacho =
1097 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1098 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
1099 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
1100 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
1101 if (RelocM == Reloc::DynamicNoPIC) {
1102 const MCSection *sect =
1103 TLOFMacho.getMachOSection("__TEXT", "__symbol_stub4",
1104 MCSectionMachO::S_SYMBOL_STUBS,
1105 12, SectionKind::getText());
1106 OutStreamer.SwitchSection(sect);
1108 const MCSection *sect =
1109 TLOFMacho.getMachOSection("__TEXT", "__picsymbolstub4",
1110 MCSectionMachO::S_SYMBOL_STUBS,
1111 16, SectionKind::getText());
1112 OutStreamer.SwitchSection(sect);
1117 // Use unified assembler syntax.
1118 O << "\t.syntax unified\n";
1120 // Emit ARM Build Attributes
1121 if (Subtarget->isTargetELF()) {
1123 std::string CPUString = Subtarget->getCPUString();
1124 if (CPUString != "generic")
1125 O << "\t.cpu " << CPUString << '\n';
1127 // FIXME: Emit FPU type
1128 if (Subtarget->hasVFP2())
1129 O << "\t.eabi_attribute " << ARMBuildAttrs::VFP_arch << ", 2\n";
1131 // Signal various FP modes.
1133 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_denormal << ", 1\n"
1134 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_exceptions << ", 1\n";
1136 if (FiniteOnlyFPMath())
1137 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 1\n";
1139 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 3\n";
1141 // 8-bytes alignment stuff.
1142 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_needed << ", 1\n"
1143 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_preserved << ", 1\n";
1145 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
1146 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard)
1147 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_HardFP_use << ", 3\n"
1148 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_VFP_args << ", 1\n";
1150 // FIXME: Should we signal R9 usage?
1155 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
1156 if (Subtarget->isTargetDarwin()) {
1157 // All darwin targets use mach-o.
1158 TargetLoweringObjectFileMachO &TLOFMacho =
1159 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1160 MachineModuleInfoMachO &MMIMacho =
1161 MMI->getObjFileInfo<MachineModuleInfoMachO>();
1165 // Output non-lazy-pointers for external and common global variables.
1166 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
1168 if (!Stubs.empty()) {
1169 // Switch with ".non_lazy_symbol_pointer" directive.
1170 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
1172 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1173 O << *Stubs[i].first << ":\n\t.indirect_symbol ";
1174 O << *Stubs[i].second << "\n\t.long\t0\n";
1178 Stubs = MMIMacho.GetHiddenGVStubList();
1179 if (!Stubs.empty()) {
1180 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
1182 for (unsigned i = 0, e = Stubs.size(); i != e; ++i)
1183 O << *Stubs[i].first << ":\n\t.long " << *Stubs[i].second << "\n";
1186 // Funny Darwin hack: This flag tells the linker that no global symbols
1187 // contain code that falls through to other global symbols (e.g. the obvious
1188 // implementation of multiple entry points). If this doesn't occur, the
1189 // linker can safely perform dead code stripping. Since LLVM never
1190 // generates code that does this, it is always safe to set.
1191 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
1195 //===----------------------------------------------------------------------===//
1197 void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
1198 ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
1199 switch (MI->getOpcode()) {
1200 case ARM::t2MOVi32imm:
1201 assert(0 && "Should be lowered by thumb2it pass");
1203 case TargetInstrInfo::DBG_LABEL:
1204 case TargetInstrInfo::EH_LABEL:
1205 case TargetInstrInfo::GC_LABEL:
1208 case TargetInstrInfo::KILL:
1211 case TargetInstrInfo::INLINEASM:
1214 case TargetInstrInfo::IMPLICIT_DEF:
1215 printImplicitDef(MI);
1217 case ARM::PICADD: { // FIXME: Remove asm string from td file.
1218 // This is a pseudo op for a label + instruction sequence, which looks like:
1221 // This adds the address of LPC0 to r0.
1224 // FIXME: MOVE TO SHARED PLACE.
1225 unsigned Id = (unsigned)MI->getOperand(2).getImm();
1226 const char *Prefix = MAI->getPrivateGlobalPrefix();
1227 MCSymbol *Label =OutContext.GetOrCreateSymbol(Twine(Prefix)
1228 + "PC" + Twine(getFunctionNumber()) + "_" + Twine(Id));
1229 OutStreamer.EmitLabel(Label);
1232 // Form and emit tha dd.
1234 AddInst.setOpcode(ARM::ADDrr);
1235 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1236 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1237 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1238 printMCInst(&AddInst);
1241 case ARM::CONSTPOOL_ENTRY: { // FIXME: Remove asm string from td file.
1242 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1243 /// in the function. The first operand is the ID# for this instruction, the
1244 /// second is the index into the MachineConstantPool that this is, the third
1245 /// is the size in bytes of this constant pool entry.
1246 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1247 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1250 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1252 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1253 if (MCPE.isMachineConstantPoolEntry())
1254 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1256 EmitGlobalConstant(MCPE.Val.ConstVal);
1260 case ARM::MOVi2pieces: { // FIXME: Remove asmstring from td file.
1261 // This is a hack that lowers as a two instruction sequence.
1262 unsigned DstReg = MI->getOperand(0).getReg();
1263 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1265 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
1266 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
1270 TmpInst.setOpcode(ARM::MOVi);
1271 TmpInst.addOperand(MCOperand::CreateReg(DstReg));
1272 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1));
1275 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1276 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1278 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1279 printMCInst(&TmpInst);
1285 TmpInst.setOpcode(ARM::ORRri);
1286 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1287 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // inreg
1288 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV2)); // so_imm
1290 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1291 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1293 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1294 printMCInst(&TmpInst);
1298 case ARM::MOVi32imm: { // FIXME: Remove asmstring from td file.
1299 // This is a hack that lowers as a two instruction sequence.
1300 unsigned DstReg = MI->getOperand(0).getReg();
1301 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1305 TmpInst.setOpcode(ARM::MOVi16);
1306 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1307 TmpInst.addOperand(MCOperand::CreateImm(ImmVal & 65535)); // lower16(imm)
1310 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1311 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1313 printMCInst(&TmpInst);
1319 TmpInst.setOpcode(ARM::MOVTi16);
1320 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1321 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
1322 TmpInst.addOperand(MCOperand::CreateImm(ImmVal >> 16)); // upper16(imm)
1325 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1326 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1328 printMCInst(&TmpInst);
1336 MCInstLowering.Lower(MI, TmpInst);
1338 printMCInst(&TmpInst);
1341 //===----------------------------------------------------------------------===//
1342 // Target Registry Stuff
1343 //===----------------------------------------------------------------------===//
1345 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1346 unsigned SyntaxVariant,
1347 const MCAsmInfo &MAI,
1349 if (SyntaxVariant == 0)
1350 return new ARMInstPrinter(O, MAI, false);
1354 // Force static initialization.
1355 extern "C" void LLVMInitializeARMAsmPrinter() {
1356 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1357 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1359 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1360 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);