1 //===-- ARMAsmPrinter.cpp - ARM LLVM assembly writer ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMTargetMachine.h"
19 #include "ARMAddressingModes.h"
20 #include "ARMConstantPoolValue.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Module.h"
24 #include "llvm/MDNode.h"
25 #include "llvm/CodeGen/AsmPrinter.h"
26 #include "llvm/CodeGen/DwarfWriter.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineJumpTableInfo.h"
30 #include "llvm/Target/TargetAsmInfo.h"
31 #include "llvm/Target/TargetData.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/ADT/StringExtras.h"
36 #include "llvm/ADT/StringSet.h"
37 #include "llvm/Support/Compiler.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/Mangler.h"
40 #include "llvm/Support/MathExtras.h"
41 #include "llvm/Support/FormattedStream.h"
45 STATISTIC(EmittedInsts, "Number of machine instrs printed");
48 class VISIBILITY_HIDDEN ARMAsmPrinter : public AsmPrinter {
51 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
52 /// make the right decision when printing asm code for different targets.
53 const ARMSubtarget *Subtarget;
55 /// AFI - Keep a pointer to ARMFunctionInfo for the current
59 /// MCP - Keep a pointer to constantpool entries of the current
61 const MachineConstantPool *MCP;
63 /// We name each basic block in a Function with a unique number, so
64 /// that we can consistently refer to them later. This is cleared
65 /// at the beginning of each call to runOnMachineFunction().
67 typedef std::map<const Value *, unsigned> ValueMapTy;
68 ValueMapTy NumberForBB;
70 /// GVNonLazyPtrs - Keeps the set of GlobalValues that require
71 /// non-lazy-pointers for indirect access.
72 StringMap<std::string> GVNonLazyPtrs;
74 /// HiddenGVNonLazyPtrs - Keeps the set of GlobalValues with hidden
75 /// visibility that require non-lazy-pointers for indirect access.
76 StringMap<std::string> HiddenGVNonLazyPtrs;
78 /// FnStubs - Keeps the set of external function GlobalAddresses that the
79 /// asm printer should generate stubs for.
82 /// True if asm printer is printing a series of CONSTPOOL_ENTRY.
85 explicit ARMAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM,
86 const TargetAsmInfo *T, bool V)
87 : AsmPrinter(O, TM, T, V), DW(0), AFI(NULL), MCP(NULL),
89 Subtarget = &TM.getSubtarget<ARMSubtarget>();
92 virtual const char *getPassName() const {
93 return "ARM Assembly Printer";
96 void printOperand(const MachineInstr *MI, int OpNum,
97 const char *Modifier = 0);
98 void printSOImmOperand(const MachineInstr *MI, int OpNum);
99 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum);
100 void printSORegOperand(const MachineInstr *MI, int OpNum);
101 void printAddrMode2Operand(const MachineInstr *MI, int OpNum);
102 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum);
103 void printAddrMode3Operand(const MachineInstr *MI, int OpNum);
104 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum);
105 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,
106 const char *Modifier = 0);
107 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,
108 const char *Modifier = 0);
109 void printAddrMode6Operand(const MachineInstr *MI, int OpNum);
110 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
111 const char *Modifier = 0);
112 void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum);
114 void printThumbITMask(const MachineInstr *MI, int OpNum);
115 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum);
116 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
118 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum);
119 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum);
120 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum);
121 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum);
123 void printT2SOOperand(const MachineInstr *MI, int OpNum);
124 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum);
125 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum);
126 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum);
127 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum);
128 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum);
130 void printPredicateOperand(const MachineInstr *MI, int OpNum);
131 void printSBitModifierOperand(const MachineInstr *MI, int OpNum);
132 void printPCLabel(const MachineInstr *MI, int OpNum);
133 void printRegisterList(const MachineInstr *MI, int OpNum);
134 void printCPInstOperand(const MachineInstr *MI, int OpNum,
135 const char *Modifier);
136 void printJTBlockOperand(const MachineInstr *MI, int OpNum);
138 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
139 unsigned AsmVariant, const char *ExtraCode);
140 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
142 const char *ExtraCode);
144 void printModuleLevelGV(const GlobalVariable* GVar);
145 bool printInstruction(const MachineInstr *MI); // autogenerated.
146 void printMachineInstruction(const MachineInstr *MI);
147 bool runOnMachineFunction(MachineFunction &F);
148 bool doInitialization(Module &M);
149 bool doFinalization(Module &M);
151 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
153 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
154 printDataDirective(MCPV->getType());
156 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
157 GlobalValue *GV = ACPV->getGV();
161 if (ACPV->isNonLazyPointer()) {
162 std::string SymName = Mang->getMangledName(GV);
163 Name = Mang->getMangledName(GV, "$non_lazy_ptr", true);
165 if (GV->hasHiddenVisibility())
166 HiddenGVNonLazyPtrs[SymName] = Name;
168 GVNonLazyPtrs[SymName] = Name;
170 } else if (ACPV->isStub()) {
172 //Name = Mang->getMangledName(GV, "$stub", true);
174 //Name = Mang->makeNameProper(ACPV->getSymbol()+"$stub", true);
177 Name = Mang->getMangledName(GV);
179 Name = Mang->makeNameProper(ACPV->getSymbol());
181 FnStubs.insert(Name);
182 printSuffixedName(Name, "$stub");
185 Name = Mang->getMangledName(GV);
187 Name = Mang->makeNameProper(ACPV->getSymbol());
193 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
194 if (ACPV->getPCAdjustment() != 0) {
195 O << "-(" << TAI->getPrivateGlobalPrefix() << "PC"
196 << utostr(ACPV->getLabelId())
197 << "+" << (unsigned)ACPV->getPCAdjustment();
198 if (ACPV->mustAddCurrentAddress())
205 void getAnalysisUsage(AnalysisUsage &AU) const {
206 AsmPrinter::getAnalysisUsage(AU);
207 AU.setPreservesAll();
208 AU.addRequired<MachineModuleInfo>();
209 AU.addRequired<DwarfWriter>();
212 } // end of anonymous namespace
214 #include "ARMGenAsmWriter.inc"
216 /// runOnMachineFunction - This uses the printInstruction()
217 /// method to print assembly for each instruction.
219 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
222 AFI = MF.getInfo<ARMFunctionInfo>();
223 MCP = MF.getConstantPool();
225 SetupMachineFunction(MF);
228 // NOTE: we don't print out constant pools here, they are handled as
232 // Print out labels for the function.
233 const Function *F = MF.getFunction();
234 switch (F->getLinkage()) {
235 default: llvm_unreachable("Unknown linkage type!");
236 case Function::PrivateLinkage:
237 case Function::InternalLinkage:
238 SwitchToTextSection("\t.text", F);
240 case Function::ExternalLinkage:
241 SwitchToTextSection("\t.text", F);
242 O << "\t.globl\t" << CurrentFnName << "\n";
244 case Function::WeakAnyLinkage:
245 case Function::WeakODRLinkage:
246 case Function::LinkOnceAnyLinkage:
247 case Function::LinkOnceODRLinkage:
248 if (Subtarget->isTargetDarwin()) {
250 ".section __TEXT,__textcoal_nt,coalesced,pure_instructions", F);
251 O << "\t.globl\t" << CurrentFnName << "\n";
252 O << "\t.weak_definition\t" << CurrentFnName << "\n";
254 O << TAI->getWeakRefDirective() << CurrentFnName << "\n";
259 printVisibility(CurrentFnName, F->getVisibility());
261 if (AFI->isThumbFunction()) {
262 EmitAlignment(MF.getAlignment(), F, AFI->getAlign());
263 O << "\t.code\t16\n";
264 O << "\t.thumb_func";
265 if (Subtarget->isTargetDarwin())
266 O << "\t" << CurrentFnName;
270 EmitAlignment(MF.getAlignment(), F);
273 O << CurrentFnName << ":\n";
274 // Emit pre-function debug information.
275 DW->BeginFunction(&MF);
277 if (Subtarget->isTargetDarwin()) {
278 // If the function is empty, then we need to emit *something*. Otherwise,
279 // the function's label might be associated with something that it wasn't
280 // meant to be associated with. We emit a noop in this situation.
281 MachineFunction::iterator I = MF.begin();
283 if (++I == MF.end() && MF.front().empty())
287 // Print out code for the function.
288 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
290 // Print a label for the basic block.
291 if (I != MF.begin()) {
292 printBasicBlockLabel(I, true, true, VerboseAsm);
295 for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
297 // Print the assembly for the instruction.
298 printMachineInstruction(II);
302 if (TAI->hasDotTypeDotSizeDirective())
303 O << "\t.size " << CurrentFnName << ", .-" << CurrentFnName << "\n";
305 // Emit post-function debug information.
306 DW->EndFunction(&MF);
313 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
314 const char *Modifier) {
315 const MachineOperand &MO = MI->getOperand(OpNum);
316 switch (MO.getType()) {
317 case MachineOperand::MO_Register: {
318 unsigned Reg = MO.getReg();
319 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
320 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
321 unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
322 unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
324 << TRI->getAsmName(DRegLo) << ',' << TRI->getAsmName(DRegHi)
326 } else if (Modifier && strcmp(Modifier, "dregsingle") == 0) {
327 O << '{' << TRI->getAsmName(Reg) << '}';
329 O << TRI->getAsmName(Reg);
332 llvm_unreachable("not implemented");
335 case MachineOperand::MO_Immediate: {
336 if (!Modifier || strcmp(Modifier, "no_hash") != 0)
342 case MachineOperand::MO_MachineBasicBlock:
343 printBasicBlockLabel(MO.getMBB());
345 case MachineOperand::MO_GlobalAddress: {
346 bool isCallOp = Modifier && !strcmp(Modifier, "call");
347 GlobalValue *GV = MO.getGlobal();
348 std::string Name = Mang->getMangledName(GV);
349 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
350 if (isExt && isCallOp && Subtarget->isTargetDarwin() &&
351 TM.getRelocationModel() != Reloc::Static) {
352 printSuffixedName(Name, "$stub");
353 FnStubs.insert(Name);
357 printOffset(MO.getOffset());
359 if (isCallOp && Subtarget->isTargetELF() &&
360 TM.getRelocationModel() == Reloc::PIC_)
364 case MachineOperand::MO_ExternalSymbol: {
365 bool isCallOp = Modifier && !strcmp(Modifier, "call");
366 std::string Name = Mang->makeNameProper(MO.getSymbolName());
367 if (isCallOp && Subtarget->isTargetDarwin() &&
368 TM.getRelocationModel() != Reloc::Static) {
369 printSuffixedName(Name, "$stub");
370 FnStubs.insert(Name);
373 if (isCallOp && Subtarget->isTargetELF() &&
374 TM.getRelocationModel() == Reloc::PIC_)
378 case MachineOperand::MO_ConstantPoolIndex:
379 O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
380 << '_' << MO.getIndex();
382 case MachineOperand::MO_JumpTableIndex:
383 O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
384 << '_' << MO.getIndex();
387 O << "<unknown operand type>"; abort (); break;
391 static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm,
392 const TargetAsmInfo *TAI) {
393 // Break it up into two parts that make up a shifter immediate.
394 V = ARM_AM::getSOImmVal(V);
395 assert(V != -1 && "Not a valid so_imm value!");
397 unsigned Imm = ARM_AM::getSOImmValImm(V);
398 unsigned Rot = ARM_AM::getSOImmValRot(V);
400 // Print low-level immediate formation info, per
401 // A5.1.3: "Data-processing operands - Immediate".
403 O << "#" << Imm << ", " << Rot;
404 // Pretty printed version.
406 O << ' ' << TAI->getCommentString()
407 << ' ' << (int)ARM_AM::rotr32(Imm, Rot);
413 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
414 /// immediate in bits 0-7.
415 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
416 const MachineOperand &MO = MI->getOperand(OpNum);
417 assert(MO.isImm() && "Not a valid so_imm value!");
418 printSOImm(O, MO.getImm(), VerboseAsm, TAI);
421 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
422 /// followed by an 'orr' to materialize.
423 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
424 const MachineOperand &MO = MI->getOperand(OpNum);
425 assert(MO.isImm() && "Not a valid so_imm value!");
426 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
427 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
428 printSOImm(O, V1, VerboseAsm, TAI);
430 printPredicateOperand(MI, 2);
436 printSOImm(O, V2, VerboseAsm, TAI);
439 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
440 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
442 // REG REG 0,SH_OPC - e.g. R5, ROR R3
443 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
444 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
445 const MachineOperand &MO1 = MI->getOperand(Op);
446 const MachineOperand &MO2 = MI->getOperand(Op+1);
447 const MachineOperand &MO3 = MI->getOperand(Op+2);
449 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
450 O << TRI->getAsmName(MO1.getReg());
452 // Print the shift opc.
454 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
458 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
459 O << TRI->getAsmName(MO2.getReg());
460 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
462 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
466 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
467 const MachineOperand &MO1 = MI->getOperand(Op);
468 const MachineOperand &MO2 = MI->getOperand(Op+1);
469 const MachineOperand &MO3 = MI->getOperand(Op+2);
471 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
472 printOperand(MI, Op);
476 O << "[" << TRI->getAsmName(MO1.getReg());
479 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
481 << (char)ARM_AM::getAM2Op(MO3.getImm())
482 << ARM_AM::getAM2Offset(MO3.getImm());
488 << (char)ARM_AM::getAM2Op(MO3.getImm())
489 << TRI->getAsmName(MO2.getReg());
491 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
493 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
498 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
499 const MachineOperand &MO1 = MI->getOperand(Op);
500 const MachineOperand &MO2 = MI->getOperand(Op+1);
503 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
504 assert(ImmOffs && "Malformed indexed load / store!");
506 << (char)ARM_AM::getAM2Op(MO2.getImm())
511 O << (char)ARM_AM::getAM2Op(MO2.getImm())
512 << TRI->getAsmName(MO1.getReg());
514 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
516 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
520 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) {
521 const MachineOperand &MO1 = MI->getOperand(Op);
522 const MachineOperand &MO2 = MI->getOperand(Op+1);
523 const MachineOperand &MO3 = MI->getOperand(Op+2);
525 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
526 O << "[" << TRI->getAsmName(MO1.getReg());
530 << (char)ARM_AM::getAM3Op(MO3.getImm())
531 << TRI->getAsmName(MO2.getReg())
536 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
538 << (char)ARM_AM::getAM3Op(MO3.getImm())
543 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
544 const MachineOperand &MO1 = MI->getOperand(Op);
545 const MachineOperand &MO2 = MI->getOperand(Op+1);
548 O << (char)ARM_AM::getAM3Op(MO2.getImm())
549 << TRI->getAsmName(MO1.getReg());
553 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
554 assert(ImmOffs && "Malformed indexed load / store!");
556 << (char)ARM_AM::getAM3Op(MO2.getImm())
560 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
561 const char *Modifier) {
562 const MachineOperand &MO1 = MI->getOperand(Op);
563 const MachineOperand &MO2 = MI->getOperand(Op+1);
564 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
565 if (Modifier && strcmp(Modifier, "submode") == 0) {
566 if (MO1.getReg() == ARM::SP) {
567 bool isLDM = (MI->getOpcode() == ARM::LDM ||
568 MI->getOpcode() == ARM::LDM_RET);
569 O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
571 O << ARM_AM::getAMSubModeStr(Mode);
573 printOperand(MI, Op);
574 if (ARM_AM::getAM4WBFlag(MO2.getImm()))
579 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
580 const char *Modifier) {
581 const MachineOperand &MO1 = MI->getOperand(Op);
582 const MachineOperand &MO2 = MI->getOperand(Op+1);
584 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
585 printOperand(MI, Op);
589 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
591 if (Modifier && strcmp(Modifier, "submode") == 0) {
592 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
593 if (MO1.getReg() == ARM::SP) {
594 bool isFLDM = (MI->getOpcode() == ARM::FLDMD ||
595 MI->getOpcode() == ARM::FLDMS);
596 O << ARM_AM::getAMSubModeAltStr(Mode, isFLDM);
598 O << ARM_AM::getAMSubModeStr(Mode);
600 } else if (Modifier && strcmp(Modifier, "base") == 0) {
601 // Used for FSTM{D|S} and LSTM{D|S} operations.
602 O << TRI->getAsmName(MO1.getReg());
603 if (ARM_AM::getAM5WBFlag(MO2.getImm()))
608 O << "[" << TRI->getAsmName(MO1.getReg());
610 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
612 << (char)ARM_AM::getAM5Op(MO2.getImm())
618 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) {
619 const MachineOperand &MO1 = MI->getOperand(Op);
620 const MachineOperand &MO2 = MI->getOperand(Op+1);
621 const MachineOperand &MO3 = MI->getOperand(Op+2);
623 // FIXME: No support yet for specifying alignment.
624 O << "[" << TRI->getAsmName(MO1.getReg()) << "]";
626 if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
627 if (MO2.getReg() == 0)
630 O << ", " << TRI->getAsmName(MO2.getReg());
634 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
635 const char *Modifier) {
636 if (Modifier && strcmp(Modifier, "label") == 0) {
637 printPCLabel(MI, Op+1);
641 const MachineOperand &MO1 = MI->getOperand(Op);
642 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
643 O << "[pc, +" << TRI->getAsmName(MO1.getReg()) << "]";
647 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) {
648 const MachineOperand &MO = MI->getOperand(Op);
649 uint32_t v = ~MO.getImm();
650 int32_t lsb = CountTrailingZeros_32(v);
651 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
652 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
653 O << "#" << lsb << ", #" << width;
656 //===--------------------------------------------------------------------===//
659 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) {
660 // (3 - the number of trailing zeros) is the number of then / else.
661 unsigned Mask = MI->getOperand(Op).getImm();
662 unsigned NumTZ = CountTrailingZeros_32(Mask);
663 assert(NumTZ <= 3 && "Invalid IT mask!");
664 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
665 bool T = (Mask & (1 << Pos)) != 0;
674 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
675 const MachineOperand &MO1 = MI->getOperand(Op);
676 const MachineOperand &MO2 = MI->getOperand(Op+1);
677 O << "[" << TRI->getAsmName(MO1.getReg());
678 O << ", " << TRI->getAsmName(MO2.getReg()) << "]";
682 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
684 const MachineOperand &MO1 = MI->getOperand(Op);
685 const MachineOperand &MO2 = MI->getOperand(Op+1);
686 const MachineOperand &MO3 = MI->getOperand(Op+2);
688 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
689 printOperand(MI, Op);
693 O << "[" << TRI->getAsmName(MO1.getReg());
695 O << ", " << TRI->getAsmName(MO3.getReg());
696 else if (unsigned ImmOffs = MO2.getImm()) {
697 O << ", #" << ImmOffs;
705 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) {
706 printThumbAddrModeRI5Operand(MI, Op, 1);
709 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) {
710 printThumbAddrModeRI5Operand(MI, Op, 2);
713 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
714 printThumbAddrModeRI5Operand(MI, Op, 4);
717 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
718 const MachineOperand &MO1 = MI->getOperand(Op);
719 const MachineOperand &MO2 = MI->getOperand(Op+1);
720 O << "[" << TRI->getAsmName(MO1.getReg());
721 if (unsigned ImmOffs = MO2.getImm())
722 O << ", #" << ImmOffs << " * 4";
726 //===--------------------------------------------------------------------===//
728 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
729 // register with shift forms.
731 // REG IMM, SH_OPC - e.g. R5, LSL #3
732 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) {
733 const MachineOperand &MO1 = MI->getOperand(OpNum);
734 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
736 unsigned Reg = MO1.getReg();
737 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
738 O << TRI->getAsmName(Reg);
740 // Print the shift opc.
742 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
745 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
746 O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
749 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
751 const MachineOperand &MO1 = MI->getOperand(OpNum);
752 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
754 O << "[" << TRI->getAsmName(MO1.getReg());
756 unsigned OffImm = MO2.getImm();
757 if (OffImm) // Don't print +0.
758 O << ", #+" << OffImm;
762 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
764 const MachineOperand &MO1 = MI->getOperand(OpNum);
765 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
767 O << "[" << TRI->getAsmName(MO1.getReg());
769 int32_t OffImm = (int32_t)MO2.getImm();
772 O << ", #-" << -OffImm;
774 O << ", #+" << OffImm;
778 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
780 const MachineOperand &MO1 = MI->getOperand(OpNum);
781 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
783 O << "[" << TRI->getAsmName(MO1.getReg());
785 int32_t OffImm = (int32_t)MO2.getImm() / 4;
788 O << ", #-" << -OffImm << " * 4";
790 O << ", #+" << OffImm << " * 4";
794 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
796 const MachineOperand &MO1 = MI->getOperand(OpNum);
797 int32_t OffImm = (int32_t)MO1.getImm();
800 O << "#-" << -OffImm;
805 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
807 const MachineOperand &MO1 = MI->getOperand(OpNum);
808 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
809 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
811 O << "[" << TRI->getAsmName(MO1.getReg());
814 O << ", +" << TRI->getAsmName(MO2.getReg());
816 unsigned ShAmt = MO3.getImm();
818 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
819 O << ", lsl #" << ShAmt;
826 //===--------------------------------------------------------------------===//
828 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum) {
829 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
831 O << ARMCondCodeToString(CC);
834 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){
835 unsigned Reg = MI->getOperand(OpNum).getReg();
837 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
842 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) {
843 int Id = (int)MI->getOperand(OpNum).getImm();
844 O << TAI->getPrivateGlobalPrefix() << "PC" << Id;
847 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) {
849 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
851 if (i != e-1) O << ", ";
856 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
857 const char *Modifier) {
858 assert(Modifier && "This operand only works with a modifier!");
859 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
861 if (!strcmp(Modifier, "label")) {
862 unsigned ID = MI->getOperand(OpNum).getImm();
863 O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
864 << '_' << ID << ":\n";
866 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
867 unsigned CPI = MI->getOperand(OpNum).getIndex();
869 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
871 if (MCPE.isMachineConstantPoolEntry()) {
872 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
874 EmitGlobalConstant(MCPE.Val.ConstVal);
879 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) {
880 const MachineOperand &MO1 = MI->getOperand(OpNum);
881 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
882 unsigned JTI = MO1.getIndex();
883 O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
884 << '_' << JTI << '_' << MO2.getImm() << ":\n";
886 const char *JTEntryDirective = TAI->getJumpTableDirective();
887 if (!JTEntryDirective)
888 JTEntryDirective = TAI->getData32bitsDirective();
890 const MachineFunction *MF = MI->getParent()->getParent();
891 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
892 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
893 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
894 bool UseSet= TAI->getSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
895 std::set<MachineBasicBlock*> JTSets;
896 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
897 MachineBasicBlock *MBB = JTBBs[i];
898 if (UseSet && JTSets.insert(MBB).second)
899 printPICJumpTableSetLabel(JTI, MO2.getImm(), MBB);
901 O << JTEntryDirective << ' ';
903 O << TAI->getPrivateGlobalPrefix() << getFunctionNumber()
904 << '_' << JTI << '_' << MO2.getImm()
905 << "_set_" << MBB->getNumber();
906 else if (TM.getRelocationModel() == Reloc::PIC_) {
907 printBasicBlockLabel(MBB, false, false, false);
908 // If the arch uses custom Jump Table directives, don't calc relative to JT
909 if (!TAI->getJumpTableDirective())
910 O << '-' << TAI->getPrivateGlobalPrefix() << "JTI"
911 << getFunctionNumber() << '_' << JTI << '_' << MO2.getImm();
913 printBasicBlockLabel(MBB, false, false, false);
920 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
921 unsigned AsmVariant, const char *ExtraCode){
922 // Does this asm operand have a single letter operand modifier?
923 if (ExtraCode && ExtraCode[0]) {
924 if (ExtraCode[1] != 0) return true; // Unknown modifier.
926 switch (ExtraCode[0]) {
927 default: return true; // Unknown modifier.
928 case 'a': // Print as a memory address.
929 if (MI->getOperand(OpNum).isReg()) {
930 O << "[" << TRI->getAsmName(MI->getOperand(OpNum).getReg()) << "]";
934 case 'c': // Don't print "#" before an immediate operand.
935 printOperand(MI, OpNum, "no_hash");
937 case 'P': // Print a VFP double precision register.
938 printOperand(MI, OpNum);
941 if (TM.getTargetData()->isLittleEndian())
945 if (TM.getTargetData()->isBigEndian())
948 case 'H': // Write second word of DI / DF reference.
949 // Verify that this operand has two consecutive registers.
950 if (!MI->getOperand(OpNum).isReg() ||
951 OpNum+1 == MI->getNumOperands() ||
952 !MI->getOperand(OpNum+1).isReg())
954 ++OpNum; // Return the high-part.
958 printOperand(MI, OpNum);
962 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
963 unsigned OpNum, unsigned AsmVariant,
964 const char *ExtraCode) {
965 if (ExtraCode && ExtraCode[0])
966 return true; // Unknown modifier.
967 printAddrMode2Operand(MI, OpNum);
971 void ARMAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
974 int Opc = MI->getOpcode();
976 case ARM::CONSTPOOL_ENTRY:
977 if (!InCPMode && AFI->isThumbFunction()) {
983 if (InCPMode && AFI->isThumbFunction())
987 // Call the autogenerated instruction printer routines.
988 printInstruction(MI);
991 bool ARMAsmPrinter::doInitialization(Module &M) {
993 bool Result = AsmPrinter::doInitialization(M);
994 DW = getAnalysisIfAvailable<DwarfWriter>();
996 // Use unified assembler syntax mode for Thumb.
997 if (Subtarget->isThumb())
998 O << "\t.syntax unified\n";
1000 // Emit ARM Build Attributes
1001 if (Subtarget->isTargetELF()) {
1003 std::string CPUString = Subtarget->getCPUString();
1004 if (CPUString != "generic")
1005 O << "\t.cpu " << CPUString << '\n';
1007 // FIXME: Emit FPU type
1008 if (Subtarget->hasVFP2())
1009 O << "\t.eabi_attribute " << ARMBuildAttrs::VFP_arch << ", 2\n";
1011 // Signal various FP modes.
1013 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_denormal << ", 1\n"
1014 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_exceptions << ", 1\n";
1016 if (FiniteOnlyFPMath())
1017 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 1\n";
1019 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 3\n";
1021 // 8-bytes alignment stuff.
1022 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_needed << ", 1\n"
1023 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_preserved << ", 1\n";
1025 // FIXME: Should we signal R9 usage?
1031 /// PrintUnmangledNameSafely - Print out the printable characters in the name.
1032 /// Don't print things like \\n or \\0.
1033 static void PrintUnmangledNameSafely(const Value *V, formatted_raw_ostream &OS) {
1034 for (const char *Name = V->getNameStart(), *E = Name+V->getNameLen();
1040 void ARMAsmPrinter::printModuleLevelGV(const GlobalVariable* GVar) {
1041 const TargetData *TD = TM.getTargetData();
1043 if (!GVar->hasInitializer()) // External global require no code
1046 // Check to see if this is a special global used by LLVM, if so, emit it.
1048 if (EmitSpecialLLVMGlobal(GVar)) {
1049 if (Subtarget->isTargetDarwin() &&
1050 TM.getRelocationModel() == Reloc::Static) {
1051 if (GVar->getName() == "llvm.global_ctors")
1052 O << ".reference .constructors_used\n";
1053 else if (GVar->getName() == "llvm.global_dtors")
1054 O << ".reference .destructors_used\n";
1059 std::string name = Mang->getMangledName(GVar);
1060 Constant *C = GVar->getInitializer();
1061 if (isa<MDNode>(C) || isa<MDString>(C))
1063 const Type *Type = C->getType();
1064 unsigned Size = TD->getTypeAllocSize(Type);
1065 unsigned Align = TD->getPreferredAlignmentLog(GVar);
1066 bool isDarwin = Subtarget->isTargetDarwin();
1068 printVisibility(name, GVar->getVisibility());
1070 if (Subtarget->isTargetELF())
1071 O << "\t.type " << name << ",%object\n";
1073 if (C->isNullValue() && !GVar->hasSection() && !GVar->isThreadLocal() &&
1075 TAI->SectionKindForGlobal(GVar) == SectionKind::RODataMergeStr)) {
1076 // FIXME: This seems to be pretty darwin-specific
1078 if (GVar->hasExternalLinkage()) {
1079 SwitchToSection(TAI->SectionForGlobal(GVar));
1080 if (const char *Directive = TAI->getZeroFillDirective()) {
1081 O << "\t.globl\t" << name << "\n";
1082 O << Directive << "__DATA, __common, " << name << ", "
1083 << Size << ", " << Align << "\n";
1088 if (GVar->hasLocalLinkage() || GVar->isWeakForLinker()) {
1089 if (Size == 0) Size = 1; // .comm Foo, 0 is undefined, avoid it.
1092 if (GVar->hasLocalLinkage()) {
1093 O << TAI->getLCOMMDirective() << name << "," << Size
1095 } else if (GVar->hasCommonLinkage()) {
1096 O << TAI->getCOMMDirective() << name << "," << Size
1099 SwitchToSection(TAI->SectionForGlobal(GVar));
1100 O << "\t.globl " << name << '\n'
1101 << TAI->getWeakDefDirective() << name << '\n';
1102 EmitAlignment(Align, GVar);
1105 O << "\t\t\t\t" << TAI->getCommentString() << ' ';
1106 PrintUnmangledNameSafely(GVar, O);
1109 EmitGlobalConstant(C);
1112 } else if (TAI->getLCOMMDirective() != NULL) {
1113 if (GVar->hasLocalLinkage()) {
1114 O << TAI->getLCOMMDirective() << name << "," << Size;
1116 O << TAI->getCOMMDirective() << name << "," << Size;
1117 if (TAI->getCOMMDirectiveTakesAlignment())
1118 O << ',' << (TAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1121 SwitchToSection(TAI->SectionForGlobal(GVar));
1122 if (GVar->hasLocalLinkage())
1123 O << "\t.local\t" << name << "\n";
1124 O << TAI->getCOMMDirective() << name << "," << Size;
1125 if (TAI->getCOMMDirectiveTakesAlignment())
1126 O << "," << (TAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1129 O << "\t\t" << TAI->getCommentString() << " ";
1130 PrintUnmangledNameSafely(GVar, O);
1137 SwitchToSection(TAI->SectionForGlobal(GVar));
1138 switch (GVar->getLinkage()) {
1139 case GlobalValue::CommonLinkage:
1140 case GlobalValue::LinkOnceAnyLinkage:
1141 case GlobalValue::LinkOnceODRLinkage:
1142 case GlobalValue::WeakAnyLinkage:
1143 case GlobalValue::WeakODRLinkage:
1145 O << "\t.globl " << name << "\n"
1146 << "\t.weak_definition " << name << "\n";
1148 O << "\t.weak " << name << "\n";
1151 case GlobalValue::AppendingLinkage:
1152 // FIXME: appending linkage variables should go into a section of
1153 // their name or something. For now, just emit them as external.
1154 case GlobalValue::ExternalLinkage:
1155 O << "\t.globl " << name << "\n";
1157 case GlobalValue::PrivateLinkage:
1158 case GlobalValue::InternalLinkage:
1161 llvm_unreachable("Unknown linkage type!");
1164 EmitAlignment(Align, GVar);
1167 O << "\t\t\t\t" << TAI->getCommentString() << " ";
1168 PrintUnmangledNameSafely(GVar, O);
1171 if (TAI->hasDotTypeDotSizeDirective())
1172 O << "\t.size " << name << ", " << Size << "\n";
1174 EmitGlobalConstant(C);
1179 bool ARMAsmPrinter::doFinalization(Module &M) {
1180 for (Module::const_global_iterator I = M.global_begin(), E = M.global_end();
1182 printModuleLevelGV(I);
1184 if (Subtarget->isTargetDarwin()) {
1185 SwitchToDataSection("");
1188 // Output stubs for dynamically-linked functions
1189 for (StringSet<>::iterator I = FnStubs.begin(), E = FnStubs.end();
1191 if (TM.getRelocationModel() == Reloc::PIC_)
1192 SwitchToTextSection(".section __TEXT,__picsymbolstub4,symbol_stubs,"
1195 SwitchToTextSection(".section __TEXT,__symbol_stub4,symbol_stubs,"
1199 O << "\t.code\t32\n";
1201 const char *p = I->getKeyData();
1202 printSuffixedName(p, "$stub");
1204 O << "\t.indirect_symbol " << p << "\n";
1206 printSuffixedName(p, "$slp");
1208 if (TM.getRelocationModel() == Reloc::PIC_) {
1209 printSuffixedName(p, "$scv");
1211 O << "\tadd ip, pc, ip\n";
1213 O << "\tldr pc, [ip, #0]\n";
1214 printSuffixedName(p, "$slp");
1217 printSuffixedName(p, "$lazy_ptr");
1218 if (TM.getRelocationModel() == Reloc::PIC_) {
1220 printSuffixedName(p, "$scv");
1224 SwitchToDataSection(".lazy_symbol_pointer", 0);
1225 printSuffixedName(p, "$lazy_ptr");
1227 O << "\t.indirect_symbol " << p << "\n";
1228 O << "\t.long\tdyld_stub_binding_helper\n";
1232 // Output non-lazy-pointers for external and common global variables.
1233 if (!GVNonLazyPtrs.empty()) {
1234 SwitchToDataSection("\t.non_lazy_symbol_pointer", 0);
1235 for (StringMap<std::string>::iterator I = GVNonLazyPtrs.begin(),
1236 E = GVNonLazyPtrs.end(); I != E; ++I) {
1237 O << I->second << ":\n";
1238 O << "\t.indirect_symbol " << I->getKeyData() << "\n";
1239 O << "\t.long\t0\n";
1243 if (!HiddenGVNonLazyPtrs.empty()) {
1244 SwitchToSection(TAI->getDataSection());
1245 for (StringMap<std::string>::iterator I = HiddenGVNonLazyPtrs.begin(),
1246 E = HiddenGVNonLazyPtrs.end(); I != E; ++I) {
1248 O << I->second << ":\n";
1249 O << "\t.long " << I->getKeyData() << "\n";
1254 // Funny Darwin hack: This flag tells the linker that no global symbols
1255 // contain code that falls through to other global symbols (e.g. the obvious
1256 // implementation of multiple entry points). If this doesn't occur, the
1257 // linker can safely perform dead code stripping. Since LLVM never
1258 // generates code that does this, it is always safe to set.
1259 O << "\t.subsections_via_symbols\n";
1262 return AsmPrinter::doFinalization(M);
1265 /// createARMCodePrinterPass - Returns a pass that prints the ARM
1266 /// assembly code for a MachineFunction to the given output stream,
1267 /// using the given target machine description. This should work
1268 /// regardless of whether the function is in SSA form.
1270 FunctionPass *llvm::createARMCodePrinterPass(formatted_raw_ostream &o,
1271 ARMBaseTargetMachine &tm,
1273 return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), verbose);
1277 static struct Register {
1279 ARMBaseTargetMachine::registerAsmPrinter(createARMCodePrinterPass);
1284 // Force static initialization.
1285 extern "C" void LLVMInitializeARMAsmPrinter() { }