1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMInstPrinter.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMMCInstLower.h"
23 #include "ARMTargetMachine.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Module.h"
26 #include "llvm/Type.h"
27 #include "llvm/Assembly/Writer.h"
28 #include "llvm/CodeGen/AsmPrinter.h"
29 #include "llvm/CodeGen/DwarfWriter.h"
30 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCContext.h"
36 #include "llvm/MC/MCExpr.h"
37 #include "llvm/MC/MCInst.h"
38 #include "llvm/MC/MCSectionMachO.h"
39 #include "llvm/MC/MCStreamer.h"
40 #include "llvm/MC/MCSymbol.h"
41 #include "llvm/Target/Mangler.h"
42 #include "llvm/Target/TargetData.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Target/TargetRegistry.h"
46 #include "llvm/ADT/SmallPtrSet.h"
47 #include "llvm/ADT/SmallString.h"
48 #include "llvm/ADT/StringExtras.h"
49 #include "llvm/ADT/StringSet.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/FormattedStream.h"
53 #include "llvm/Support/MathExtras.h"
58 EnableMCInst("enable-arm-mcinst-printer", cl::Hidden,
59 cl::desc("enable experimental asmprinter gunk in the arm backend"));
62 class ARMAsmPrinter : public AsmPrinter {
64 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
65 /// make the right decision when printing asm code for different targets.
66 const ARMSubtarget *Subtarget;
68 /// AFI - Keep a pointer to ARMFunctionInfo for the current
72 /// MCP - Keep a pointer to constantpool entries of the current
74 const MachineConstantPool *MCP;
77 explicit ARMAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM,
78 MCContext &Ctx, MCStreamer &Streamer,
80 : AsmPrinter(O, TM, Ctx, Streamer, T), AFI(NULL), MCP(NULL) {
81 Subtarget = &TM.getSubtarget<ARMSubtarget>();
84 virtual const char *getPassName() const {
85 return "ARM Assembly Printer";
88 void printInstructionThroughMCStreamer(const MachineInstr *MI);
91 void printOperand(const MachineInstr *MI, int OpNum,
92 const char *Modifier = 0);
93 void printSOImmOperand(const MachineInstr *MI, int OpNum);
94 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum);
95 void printSORegOperand(const MachineInstr *MI, int OpNum);
96 void printAddrMode2Operand(const MachineInstr *MI, int OpNum);
97 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum);
98 void printAddrMode3Operand(const MachineInstr *MI, int OpNum);
99 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum);
100 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,
101 const char *Modifier = 0);
102 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,
103 const char *Modifier = 0);
104 void printAddrMode6Operand(const MachineInstr *MI, int OpNum);
105 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
106 const char *Modifier = 0);
107 void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum);
109 void printThumbS4ImmOperand(const MachineInstr *MI, int OpNum);
110 void printThumbITMask(const MachineInstr *MI, int OpNum);
111 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum);
112 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
114 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum);
115 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum);
116 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum);
117 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum);
119 void printT2SOOperand(const MachineInstr *MI, int OpNum);
120 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum);
121 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum);
122 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum);
123 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum);
124 void printT2AddrModeImm8s4OffsetOperand(const MachineInstr *MI, int OpNum) {}
125 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum);
127 void printCPSOptionOperand(const MachineInstr *MI, int OpNum) {}
128 void printMSRMaskOperand(const MachineInstr *MI, int OpNum) {}
129 void printNegZeroOperand(const MachineInstr *MI, int OpNum) {}
130 void printPredicateOperand(const MachineInstr *MI, int OpNum);
131 void printMandatoryPredicateOperand(const MachineInstr *MI, int OpNum);
132 void printSBitModifierOperand(const MachineInstr *MI, int OpNum);
133 void printPCLabel(const MachineInstr *MI, int OpNum);
134 void printRegisterList(const MachineInstr *MI, int OpNum);
135 void printCPInstOperand(const MachineInstr *MI, int OpNum,
136 const char *Modifier);
137 void printJTBlockOperand(const MachineInstr *MI, int OpNum);
138 void printJT2BlockOperand(const MachineInstr *MI, int OpNum);
139 void printTBAddrMode(const MachineInstr *MI, int OpNum);
140 void printNoHashImmediate(const MachineInstr *MI, int OpNum);
141 void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum);
142 void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum);
144 void printHex8ImmOperand(const MachineInstr *MI, int OpNum) {
145 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xff);
147 void printHex16ImmOperand(const MachineInstr *MI, int OpNum) {
148 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffff);
150 void printHex32ImmOperand(const MachineInstr *MI, int OpNum) {
151 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffffffff);
153 void printHex64ImmOperand(const MachineInstr *MI, int OpNum) {
154 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm());
157 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
158 unsigned AsmVariant, const char *ExtraCode);
159 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
161 const char *ExtraCode);
163 void printInstruction(const MachineInstr *MI); // autogenerated.
164 static const char *getRegisterName(unsigned RegNo);
166 virtual void EmitInstruction(const MachineInstr *MI);
167 bool runOnMachineFunction(MachineFunction &F);
169 virtual void EmitConstantPool() {} // we emit constant pools customly!
170 virtual void EmitFunctionEntryLabel();
171 void EmitStartOfAsmFile(Module &M);
172 void EmitEndOfAsmFile(Module &M);
174 MCSymbol *GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
175 const MachineBasicBlock *MBB) const;
176 MCSymbol *GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const;
178 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
180 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
181 switch (TM.getTargetData()->getTypeAllocSize(MCPV->getType())) {
182 case 1: O << MAI->getData8bitsDirective(0); break;
183 case 2: O << MAI->getData16bitsDirective(0); break;
184 case 4: O << MAI->getData32bitsDirective(0); break;
185 default: assert(0 && "Unknown CPV size");
188 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
189 SmallString<128> TmpNameStr;
191 if (ACPV->isLSDA()) {
192 raw_svector_ostream(TmpNameStr) << MAI->getPrivateGlobalPrefix() <<
193 "_LSDA_" << getFunctionNumber();
194 O << TmpNameStr.str();
195 } else if (ACPV->isBlockAddress()) {
196 O << GetBlockAddressSymbol(ACPV->getBlockAddress())->getName();
197 } else if (ACPV->isGlobalValue()) {
198 GlobalValue *GV = ACPV->getGV();
199 bool isIndirect = Subtarget->isTargetDarwin() &&
200 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
202 O << *Mang->getSymbol(GV);
204 // FIXME: Remove this when Darwin transition to @GOT like syntax.
205 MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
208 MachineModuleInfoMachO &MMIMachO =
209 MMI->getObjFileInfo<MachineModuleInfoMachO>();
210 MachineModuleInfoImpl::StubValueTy &StubSym =
211 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
212 MMIMachO.getGVStubEntry(Sym);
213 if (StubSym.getPointer() == 0)
214 StubSym = MachineModuleInfoImpl::
215 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
218 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
219 O << *GetExternalSymbolSymbol(ACPV->getSymbol());
222 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
223 if (ACPV->getPCAdjustment() != 0) {
224 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
225 << getFunctionNumber() << "_" << ACPV->getLabelId()
226 << "+" << (unsigned)ACPV->getPCAdjustment();
227 if (ACPV->mustAddCurrentAddress())
231 OutStreamer.AddBlankLine();
234 void getAnalysisUsage(AnalysisUsage &AU) const {
235 AsmPrinter::getAnalysisUsage(AU);
236 AU.setPreservesAll();
237 AU.addRequired<MachineModuleInfo>();
238 AU.addRequired<DwarfWriter>();
241 } // end of anonymous namespace
243 #include "ARMGenAsmWriter.inc"
245 void ARMAsmPrinter::EmitFunctionEntryLabel() {
246 if (AFI->isThumbFunction()) {
247 O << "\t.code\t16\n";
248 O << "\t.thumb_func";
249 if (Subtarget->isTargetDarwin())
250 O << '\t' << *CurrentFnSym;
254 OutStreamer.EmitLabel(CurrentFnSym);
257 /// runOnMachineFunction - This uses the printInstruction()
258 /// method to print assembly for each instruction.
260 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
261 AFI = MF.getInfo<ARMFunctionInfo>();
262 MCP = MF.getConstantPool();
264 return AsmPrinter::runOnMachineFunction(MF);
267 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
268 const char *Modifier) {
269 const MachineOperand &MO = MI->getOperand(OpNum);
270 unsigned TF = MO.getTargetFlags();
272 switch (MO.getType()) {
274 assert(0 && "<unknown operand type>");
275 case MachineOperand::MO_Register: {
276 unsigned Reg = MO.getReg();
277 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
278 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
279 unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
280 unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
282 << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
284 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
285 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
286 unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1,
287 &ARM::DPR_VFP2RegClass);
288 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
290 assert(!MO.getSubReg() && "Subregs should be eliminated!");
291 O << getRegisterName(Reg);
295 case MachineOperand::MO_Immediate: {
296 int64_t Imm = MO.getImm();
298 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
299 (TF & ARMII::MO_LO16))
301 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
302 (TF & ARMII::MO_HI16))
307 case MachineOperand::MO_MachineBasicBlock:
308 O << *MO.getMBB()->getSymbol(OutContext);
310 case MachineOperand::MO_GlobalAddress: {
311 bool isCallOp = Modifier && !strcmp(Modifier, "call");
312 GlobalValue *GV = MO.getGlobal();
314 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
315 (TF & ARMII::MO_LO16))
317 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
318 (TF & ARMII::MO_HI16))
320 O << *Mang->getSymbol(GV);
322 printOffset(MO.getOffset());
324 if (isCallOp && Subtarget->isTargetELF() &&
325 TM.getRelocationModel() == Reloc::PIC_)
329 case MachineOperand::MO_ExternalSymbol: {
330 bool isCallOp = Modifier && !strcmp(Modifier, "call");
331 O << *GetExternalSymbolSymbol(MO.getSymbolName());
333 if (isCallOp && Subtarget->isTargetELF() &&
334 TM.getRelocationModel() == Reloc::PIC_)
338 case MachineOperand::MO_ConstantPoolIndex:
339 O << *GetCPISymbol(MO.getIndex());
341 case MachineOperand::MO_JumpTableIndex:
342 O << *GetJTISymbol(MO.getIndex());
347 static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm,
348 const MCAsmInfo *MAI) {
349 // Break it up into two parts that make up a shifter immediate.
350 V = ARM_AM::getSOImmVal(V);
351 assert(V != -1 && "Not a valid so_imm value!");
353 unsigned Imm = ARM_AM::getSOImmValImm(V);
354 unsigned Rot = ARM_AM::getSOImmValRot(V);
356 // Print low-level immediate formation info, per
357 // A5.1.3: "Data-processing operands - Immediate".
359 O << "#" << Imm << ", " << Rot;
360 // Pretty printed version.
362 O.PadToColumn(MAI->getCommentColumn());
363 O << MAI->getCommentString() << ' ';
364 O << (int)ARM_AM::rotr32(Imm, Rot);
371 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
372 /// immediate in bits 0-7.
373 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
374 const MachineOperand &MO = MI->getOperand(OpNum);
375 assert(MO.isImm() && "Not a valid so_imm value!");
376 printSOImm(O, MO.getImm(), VerboseAsm, MAI);
379 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
380 /// followed by an 'orr' to materialize.
381 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
382 const MachineOperand &MO = MI->getOperand(OpNum);
383 assert(MO.isImm() && "Not a valid so_imm value!");
384 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
385 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
386 printSOImm(O, V1, VerboseAsm, MAI);
388 printPredicateOperand(MI, 2);
394 printSOImm(O, V2, VerboseAsm, MAI);
397 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
398 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
400 // REG REG 0,SH_OPC - e.g. R5, ROR R3
401 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
402 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
403 const MachineOperand &MO1 = MI->getOperand(Op);
404 const MachineOperand &MO2 = MI->getOperand(Op+1);
405 const MachineOperand &MO3 = MI->getOperand(Op+2);
407 O << getRegisterName(MO1.getReg());
409 // Print the shift opc.
411 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
415 O << getRegisterName(MO2.getReg());
416 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
418 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
422 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
423 const MachineOperand &MO1 = MI->getOperand(Op);
424 const MachineOperand &MO2 = MI->getOperand(Op+1);
425 const MachineOperand &MO3 = MI->getOperand(Op+2);
427 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
428 printOperand(MI, Op);
432 O << "[" << getRegisterName(MO1.getReg());
435 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
437 << (char)ARM_AM::getAM2Op(MO3.getImm())
438 << ARM_AM::getAM2Offset(MO3.getImm());
444 << (char)ARM_AM::getAM2Op(MO3.getImm())
445 << getRegisterName(MO2.getReg());
447 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
449 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
454 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
455 const MachineOperand &MO1 = MI->getOperand(Op);
456 const MachineOperand &MO2 = MI->getOperand(Op+1);
459 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
460 assert(ImmOffs && "Malformed indexed load / store!");
462 << (char)ARM_AM::getAM2Op(MO2.getImm())
467 O << (char)ARM_AM::getAM2Op(MO2.getImm())
468 << getRegisterName(MO1.getReg());
470 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
472 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
476 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) {
477 const MachineOperand &MO1 = MI->getOperand(Op);
478 const MachineOperand &MO2 = MI->getOperand(Op+1);
479 const MachineOperand &MO3 = MI->getOperand(Op+2);
481 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
482 O << "[" << getRegisterName(MO1.getReg());
486 << (char)ARM_AM::getAM3Op(MO3.getImm())
487 << getRegisterName(MO2.getReg())
492 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
494 << (char)ARM_AM::getAM3Op(MO3.getImm())
499 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
500 const MachineOperand &MO1 = MI->getOperand(Op);
501 const MachineOperand &MO2 = MI->getOperand(Op+1);
504 O << (char)ARM_AM::getAM3Op(MO2.getImm())
505 << getRegisterName(MO1.getReg());
509 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
510 assert(ImmOffs && "Malformed indexed load / store!");
512 << (char)ARM_AM::getAM3Op(MO2.getImm())
516 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
517 const char *Modifier) {
518 const MachineOperand &MO1 = MI->getOperand(Op);
519 const MachineOperand &MO2 = MI->getOperand(Op+1);
520 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
521 if (Modifier && strcmp(Modifier, "submode") == 0) {
522 if (MO1.getReg() == ARM::SP) {
524 bool isLDM = (MI->getOpcode() == ARM::LDM ||
525 MI->getOpcode() == ARM::LDM_RET ||
526 MI->getOpcode() == ARM::t2LDM ||
527 MI->getOpcode() == ARM::t2LDM_RET);
528 O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
530 O << ARM_AM::getAMSubModeStr(Mode);
531 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
532 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
533 if (Mode == ARM_AM::ia)
536 printOperand(MI, Op);
537 if (ARM_AM::getAM4WBFlag(MO2.getImm()))
542 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
543 const char *Modifier) {
544 const MachineOperand &MO1 = MI->getOperand(Op);
545 const MachineOperand &MO2 = MI->getOperand(Op+1);
547 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
548 printOperand(MI, Op);
552 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
554 if (Modifier && strcmp(Modifier, "submode") == 0) {
555 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
556 O << ARM_AM::getAMSubModeStr(Mode);
558 } else if (Modifier && strcmp(Modifier, "base") == 0) {
559 // Used for FSTM{D|S} and LSTM{D|S} operations.
560 O << getRegisterName(MO1.getReg());
561 if (ARM_AM::getAM5WBFlag(MO2.getImm()))
566 O << "[" << getRegisterName(MO1.getReg());
568 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
570 << (char)ARM_AM::getAM5Op(MO2.getImm())
576 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) {
577 const MachineOperand &MO1 = MI->getOperand(Op);
578 const MachineOperand &MO2 = MI->getOperand(Op+1);
579 const MachineOperand &MO3 = MI->getOperand(Op+2);
580 const MachineOperand &MO4 = MI->getOperand(Op+3);
582 O << "[" << getRegisterName(MO1.getReg());
584 // FIXME: Both darwin as and GNU as violate ARM docs here.
585 O << ", :" << MO4.getImm();
589 if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
590 if (MO2.getReg() == 0)
593 O << ", " << getRegisterName(MO2.getReg());
597 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
598 const char *Modifier) {
599 if (Modifier && strcmp(Modifier, "label") == 0) {
600 printPCLabel(MI, Op+1);
604 const MachineOperand &MO1 = MI->getOperand(Op);
605 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
606 O << "[pc, +" << getRegisterName(MO1.getReg()) << "]";
610 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) {
611 const MachineOperand &MO = MI->getOperand(Op);
612 uint32_t v = ~MO.getImm();
613 int32_t lsb = CountTrailingZeros_32(v);
614 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
615 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
616 O << "#" << lsb << ", #" << width;
619 //===--------------------------------------------------------------------===//
621 void ARMAsmPrinter::printThumbS4ImmOperand(const MachineInstr *MI, int Op) {
622 O << "#" << MI->getOperand(Op).getImm() * 4;
626 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) {
627 // (3 - the number of trailing zeros) is the number of then / else.
628 unsigned Mask = MI->getOperand(Op).getImm();
629 unsigned NumTZ = CountTrailingZeros_32(Mask);
630 assert(NumTZ <= 3 && "Invalid IT mask!");
631 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
632 bool T = (Mask & (1 << Pos)) == 0;
641 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
642 const MachineOperand &MO1 = MI->getOperand(Op);
643 const MachineOperand &MO2 = MI->getOperand(Op+1);
644 O << "[" << getRegisterName(MO1.getReg());
645 O << ", " << getRegisterName(MO2.getReg()) << "]";
649 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
651 const MachineOperand &MO1 = MI->getOperand(Op);
652 const MachineOperand &MO2 = MI->getOperand(Op+1);
653 const MachineOperand &MO3 = MI->getOperand(Op+2);
655 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
656 printOperand(MI, Op);
660 O << "[" << getRegisterName(MO1.getReg());
662 O << ", " << getRegisterName(MO3.getReg());
663 else if (unsigned ImmOffs = MO2.getImm())
664 O << ", #+" << ImmOffs * Scale;
669 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) {
670 printThumbAddrModeRI5Operand(MI, Op, 1);
673 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) {
674 printThumbAddrModeRI5Operand(MI, Op, 2);
677 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
678 printThumbAddrModeRI5Operand(MI, Op, 4);
681 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
682 const MachineOperand &MO1 = MI->getOperand(Op);
683 const MachineOperand &MO2 = MI->getOperand(Op+1);
684 O << "[" << getRegisterName(MO1.getReg());
685 if (unsigned ImmOffs = MO2.getImm())
686 O << ", #+" << ImmOffs*4;
690 //===--------------------------------------------------------------------===//
692 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
693 // register with shift forms.
695 // REG IMM, SH_OPC - e.g. R5, LSL #3
696 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) {
697 const MachineOperand &MO1 = MI->getOperand(OpNum);
698 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
700 unsigned Reg = MO1.getReg();
701 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
702 O << getRegisterName(Reg);
704 // Print the shift opc.
706 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
709 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
710 O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
713 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
715 const MachineOperand &MO1 = MI->getOperand(OpNum);
716 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
718 O << "[" << getRegisterName(MO1.getReg());
720 unsigned OffImm = MO2.getImm();
721 if (OffImm) // Don't print +0.
722 O << ", #+" << OffImm;
726 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
728 const MachineOperand &MO1 = MI->getOperand(OpNum);
729 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
731 O << "[" << getRegisterName(MO1.getReg());
733 int32_t OffImm = (int32_t)MO2.getImm();
736 O << ", #-" << -OffImm;
738 O << ", #+" << OffImm;
742 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
744 const MachineOperand &MO1 = MI->getOperand(OpNum);
745 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
747 O << "[" << getRegisterName(MO1.getReg());
749 int32_t OffImm = (int32_t)MO2.getImm() / 4;
752 O << ", #-" << -OffImm * 4;
754 O << ", #+" << OffImm * 4;
758 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
760 const MachineOperand &MO1 = MI->getOperand(OpNum);
761 int32_t OffImm = (int32_t)MO1.getImm();
764 O << "#-" << -OffImm;
769 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
771 const MachineOperand &MO1 = MI->getOperand(OpNum);
772 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
773 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
775 O << "[" << getRegisterName(MO1.getReg());
777 assert(MO2.getReg() && "Invalid so_reg load / store address!");
778 O << ", " << getRegisterName(MO2.getReg());
780 unsigned ShAmt = MO3.getImm();
782 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
783 O << ", lsl #" << ShAmt;
789 //===--------------------------------------------------------------------===//
791 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum) {
792 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
794 O << ARMCondCodeToString(CC);
797 void ARMAsmPrinter::printMandatoryPredicateOperand(const MachineInstr *MI,
799 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
800 O << ARMCondCodeToString(CC);
803 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){
804 unsigned Reg = MI->getOperand(OpNum).getReg();
806 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
811 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) {
812 int Id = (int)MI->getOperand(OpNum).getImm();
813 O << MAI->getPrivateGlobalPrefix()
814 << "PC" << getFunctionNumber() << "_" << Id;
817 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) {
819 // Always skip the first operand, it's the optional (and implicit writeback).
820 for (unsigned i = OpNum+1, e = MI->getNumOperands(); i != e; ++i) {
821 if (MI->getOperand(i).isImplicit())
823 if ((int)i != OpNum+1) O << ", ";
829 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
830 const char *Modifier) {
831 assert(Modifier && "This operand only works with a modifier!");
832 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
834 if (!strcmp(Modifier, "label")) {
835 unsigned ID = MI->getOperand(OpNum).getImm();
836 OutStreamer.EmitLabel(GetCPISymbol(ID));
838 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
839 unsigned CPI = MI->getOperand(OpNum).getIndex();
841 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
843 if (MCPE.isMachineConstantPoolEntry()) {
844 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
846 EmitGlobalConstant(MCPE.Val.ConstVal);
851 MCSymbol *ARMAsmPrinter::
852 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
853 const MachineBasicBlock *MBB) const {
854 SmallString<60> Name;
855 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
856 << getFunctionNumber() << '_' << uid << '_' << uid2
857 << "_set_" << MBB->getNumber();
858 return OutContext.GetOrCreateTemporarySymbol(Name.str());
861 MCSymbol *ARMAsmPrinter::
862 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
863 SmallString<60> Name;
864 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
865 << getFunctionNumber() << '_' << uid << '_' << uid2;
866 return OutContext.GetOrCreateTemporarySymbol(Name.str());
869 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) {
870 assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
872 const MachineOperand &MO1 = MI->getOperand(OpNum);
873 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
875 unsigned JTI = MO1.getIndex();
876 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
877 OutStreamer.EmitLabel(JTISymbol);
879 const char *JTEntryDirective = MAI->getData32bitsDirective();
881 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
882 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
883 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
884 bool UseSet= MAI->hasSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
885 SmallPtrSet<MachineBasicBlock*, 8> JTSets;
886 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
887 MachineBasicBlock *MBB = JTBBs[i];
888 bool isNew = JTSets.insert(MBB);
890 if (UseSet && isNew) {
892 << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB) << ','
893 << *MBB->getSymbol(OutContext) << '-' << *JTISymbol << '\n';
896 O << JTEntryDirective << ' ';
898 O << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB);
899 else if (TM.getRelocationModel() == Reloc::PIC_)
900 O << *MBB->getSymbol(OutContext) << '-' << *JTISymbol;
902 O << *MBB->getSymbol(OutContext);
909 void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum) {
910 const MachineOperand &MO1 = MI->getOperand(OpNum);
911 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
912 unsigned JTI = MO1.getIndex();
914 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
915 OutStreamer.EmitLabel(JTISymbol);
917 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
918 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
919 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
920 bool ByteOffset = false, HalfWordOffset = false;
921 if (MI->getOpcode() == ARM::t2TBB)
923 else if (MI->getOpcode() == ARM::t2TBH)
924 HalfWordOffset = true;
926 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
927 MachineBasicBlock *MBB = JTBBs[i];
929 O << MAI->getData8bitsDirective();
930 else if (HalfWordOffset)
931 O << MAI->getData16bitsDirective();
933 if (ByteOffset || HalfWordOffset)
934 O << '(' << *MBB->getSymbol(OutContext) << "-" << *JTISymbol << ")/2";
936 O << "\tb.w " << *MBB->getSymbol(OutContext);
942 // Make sure the instruction that follows TBB is 2-byte aligned.
943 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
944 if (ByteOffset && (JTBBs.size() & 1)) {
950 void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum) {
951 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
952 if (MI->getOpcode() == ARM::t2TBH)
957 void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum) {
958 O << MI->getOperand(OpNum).getImm();
961 void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum) {
962 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
963 O << '#' << FP->getValueAPF().convertToFloat();
965 O.PadToColumn(MAI->getCommentColumn());
966 O << MAI->getCommentString() << ' ';
967 WriteAsOperand(O, FP, /*PrintType=*/false);
971 void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum) {
972 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
973 O << '#' << FP->getValueAPF().convertToDouble();
975 O.PadToColumn(MAI->getCommentColumn());
976 O << MAI->getCommentString() << ' ';
977 WriteAsOperand(O, FP, /*PrintType=*/false);
981 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
982 unsigned AsmVariant, const char *ExtraCode){
983 // Does this asm operand have a single letter operand modifier?
984 if (ExtraCode && ExtraCode[0]) {
985 if (ExtraCode[1] != 0) return true; // Unknown modifier.
987 switch (ExtraCode[0]) {
988 default: return true; // Unknown modifier.
989 case 'a': // Print as a memory address.
990 if (MI->getOperand(OpNum).isReg()) {
991 O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
995 case 'c': // Don't print "#" before an immediate operand.
996 if (!MI->getOperand(OpNum).isImm())
998 printNoHashImmediate(MI, OpNum);
1000 case 'P': // Print a VFP double precision register.
1001 case 'q': // Print a NEON quad precision register.
1002 printOperand(MI, OpNum);
1005 if (TM.getTargetData()->isLittleEndian())
1009 if (TM.getTargetData()->isBigEndian())
1012 case 'H': // Write second word of DI / DF reference.
1013 // Verify that this operand has two consecutive registers.
1014 if (!MI->getOperand(OpNum).isReg() ||
1015 OpNum+1 == MI->getNumOperands() ||
1016 !MI->getOperand(OpNum+1).isReg())
1018 ++OpNum; // Return the high-part.
1022 printOperand(MI, OpNum);
1026 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1027 unsigned OpNum, unsigned AsmVariant,
1028 const char *ExtraCode) {
1029 if (ExtraCode && ExtraCode[0])
1030 return true; // Unknown modifier.
1032 const MachineOperand &MO = MI->getOperand(OpNum);
1033 assert(MO.isReg() && "unexpected inline asm memory operand");
1034 O << "[" << getRegisterName(MO.getReg()) << "]";
1038 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1040 printInstructionThroughMCStreamer(MI);
1042 int Opc = MI->getOpcode();
1043 if (Opc == ARM::CONSTPOOL_ENTRY)
1046 printInstruction(MI);
1047 OutStreamer.AddBlankLine();
1051 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
1052 if (Subtarget->isTargetDarwin()) {
1053 Reloc::Model RelocM = TM.getRelocationModel();
1054 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
1055 // Declare all the text sections up front (before the DWARF sections
1056 // emitted by AsmPrinter::doInitialization) so the assembler will keep
1057 // them together at the beginning of the object file. This helps
1058 // avoid out-of-range branches that are due a fundamental limitation of
1059 // the way symbol offsets are encoded with the current Darwin ARM
1061 TargetLoweringObjectFileMachO &TLOFMacho =
1062 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1063 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
1064 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
1065 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
1066 if (RelocM == Reloc::DynamicNoPIC) {
1067 const MCSection *sect =
1068 TLOFMacho.getMachOSection("__TEXT", "__symbol_stub4",
1069 MCSectionMachO::S_SYMBOL_STUBS,
1070 12, SectionKind::getText());
1071 OutStreamer.SwitchSection(sect);
1073 const MCSection *sect =
1074 TLOFMacho.getMachOSection("__TEXT", "__picsymbolstub4",
1075 MCSectionMachO::S_SYMBOL_STUBS,
1076 16, SectionKind::getText());
1077 OutStreamer.SwitchSection(sect);
1082 // Use unified assembler syntax.
1083 O << "\t.syntax unified\n";
1085 // Emit ARM Build Attributes
1086 if (Subtarget->isTargetELF()) {
1088 std::string CPUString = Subtarget->getCPUString();
1089 if (CPUString != "generic")
1090 O << "\t.cpu " << CPUString << '\n';
1092 // FIXME: Emit FPU type
1093 if (Subtarget->hasVFP2())
1094 O << "\t.eabi_attribute " << ARMBuildAttrs::VFP_arch << ", 2\n";
1096 // Signal various FP modes.
1098 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_denormal << ", 1\n"
1099 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_exceptions << ", 1\n";
1101 if (FiniteOnlyFPMath())
1102 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 1\n";
1104 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 3\n";
1106 // 8-bytes alignment stuff.
1107 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_needed << ", 1\n"
1108 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_preserved << ", 1\n";
1110 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
1111 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard)
1112 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_HardFP_use << ", 3\n"
1113 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_VFP_args << ", 1\n";
1115 // FIXME: Should we signal R9 usage?
1120 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
1121 if (Subtarget->isTargetDarwin()) {
1122 // All darwin targets use mach-o.
1123 TargetLoweringObjectFileMachO &TLOFMacho =
1124 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1125 MachineModuleInfoMachO &MMIMacho =
1126 MMI->getObjFileInfo<MachineModuleInfoMachO>();
1130 // Output non-lazy-pointers for external and common global variables.
1131 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
1133 if (!Stubs.empty()) {
1134 // Switch with ".non_lazy_symbol_pointer" directive.
1135 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
1137 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1139 OutStreamer.EmitLabel(Stubs[i].first);
1140 // .indirect_symbol _foo
1141 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
1142 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
1145 // External to current translation unit.
1146 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
1148 // Internal to current translation unit.
1149 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
1151 4/*size*/, 0/*addrspace*/);
1155 OutStreamer.AddBlankLine();
1158 Stubs = MMIMacho.GetHiddenGVStubList();
1159 if (!Stubs.empty()) {
1160 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
1162 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1164 OutStreamer.EmitLabel(Stubs[i].first);
1166 OutStreamer.EmitValue(MCSymbolRefExpr::
1167 Create(Stubs[i].second.getPointer(),
1169 4/*size*/, 0/*addrspace*/);
1173 OutStreamer.AddBlankLine();
1176 // Funny Darwin hack: This flag tells the linker that no global symbols
1177 // contain code that falls through to other global symbols (e.g. the obvious
1178 // implementation of multiple entry points). If this doesn't occur, the
1179 // linker can safely perform dead code stripping. Since LLVM never
1180 // generates code that does this, it is always safe to set.
1181 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
1185 //===----------------------------------------------------------------------===//
1187 void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
1188 ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
1189 switch (MI->getOpcode()) {
1190 case ARM::t2MOVi32imm:
1191 assert(0 && "Should be lowered by thumb2it pass");
1193 case ARM::PICADD: { // FIXME: Remove asm string from td file.
1194 // This is a pseudo op for a label + instruction sequence, which looks like:
1197 // This adds the address of LPC0 to r0.
1200 // FIXME: MOVE TO SHARED PLACE.
1201 unsigned Id = (unsigned)MI->getOperand(2).getImm();
1202 const char *Prefix = MAI->getPrivateGlobalPrefix();
1203 MCSymbol *Label =OutContext.GetOrCreateTemporarySymbol(Twine(Prefix)
1204 + "PC" + Twine(getFunctionNumber()) + "_" + Twine(Id));
1205 OutStreamer.EmitLabel(Label);
1208 // Form and emit tha dd.
1210 AddInst.setOpcode(ARM::ADDrr);
1211 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1212 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1213 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1214 OutStreamer.EmitInstruction(AddInst);
1217 case ARM::CONSTPOOL_ENTRY: { // FIXME: Remove asm string from td file.
1218 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1219 /// in the function. The first operand is the ID# for this instruction, the
1220 /// second is the index into the MachineConstantPool that this is, the third
1221 /// is the size in bytes of this constant pool entry.
1222 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1223 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1226 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1228 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1229 if (MCPE.isMachineConstantPoolEntry())
1230 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1232 EmitGlobalConstant(MCPE.Val.ConstVal);
1236 case ARM::MOVi2pieces: { // FIXME: Remove asmstring from td file.
1237 // This is a hack that lowers as a two instruction sequence.
1238 unsigned DstReg = MI->getOperand(0).getReg();
1239 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1241 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
1242 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
1246 TmpInst.setOpcode(ARM::MOVi);
1247 TmpInst.addOperand(MCOperand::CreateReg(DstReg));
1248 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1));
1251 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1252 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1254 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1255 OutStreamer.EmitInstruction(TmpInst);
1260 TmpInst.setOpcode(ARM::ORRri);
1261 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1262 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // inreg
1263 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV2)); // so_imm
1265 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1266 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1268 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1269 OutStreamer.EmitInstruction(TmpInst);
1273 case ARM::MOVi32imm: { // FIXME: Remove asmstring from td file.
1274 // This is a hack that lowers as a two instruction sequence.
1275 unsigned DstReg = MI->getOperand(0).getReg();
1276 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1280 TmpInst.setOpcode(ARM::MOVi16);
1281 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1282 TmpInst.addOperand(MCOperand::CreateImm(ImmVal & 65535)); // lower16(imm)
1285 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1286 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1288 OutStreamer.EmitInstruction(TmpInst);
1293 TmpInst.setOpcode(ARM::MOVTi16);
1294 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1295 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
1296 TmpInst.addOperand(MCOperand::CreateImm(ImmVal >> 16)); // upper16(imm)
1299 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1300 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1302 OutStreamer.EmitInstruction(TmpInst);
1310 MCInstLowering.Lower(MI, TmpInst);
1311 OutStreamer.EmitInstruction(TmpInst);
1314 //===----------------------------------------------------------------------===//
1315 // Target Registry Stuff
1316 //===----------------------------------------------------------------------===//
1318 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1319 unsigned SyntaxVariant,
1320 const MCAsmInfo &MAI,
1322 if (SyntaxVariant == 0)
1323 return new ARMInstPrinter(O, MAI, false);
1327 // Force static initialization.
1328 extern "C" void LLVMInitializeARMAsmPrinter() {
1329 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1330 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1332 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1333 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);